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1/* SPDX-License-Identifier: GPL-2.0-only */
2/****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
6 */
7
8#ifndef EFX_NIC_H
9#define EFX_NIC_H
10
11#include "nic_common.h"
12#include "efx.h"
13
14enum {
15 PHY_TYPE_NONE = 0,
16 PHY_TYPE_TXC43128 = 1,
17 PHY_TYPE_88E1111 = 2,
18 PHY_TYPE_SFX7101 = 3,
19 PHY_TYPE_QT2022C2 = 4,
20 PHY_TYPE_PM8358 = 6,
21 PHY_TYPE_SFT9001A = 8,
22 PHY_TYPE_QT2025C = 9,
23 PHY_TYPE_SFT9001B = 10,
24};
25
26enum {
27 EF10_STAT_port_tx_bytes = GENERIC_STAT_COUNT,
28 EF10_STAT_port_tx_packets,
29 EF10_STAT_port_tx_pause,
30 EF10_STAT_port_tx_control,
31 EF10_STAT_port_tx_unicast,
32 EF10_STAT_port_tx_multicast,
33 EF10_STAT_port_tx_broadcast,
34 EF10_STAT_port_tx_lt64,
35 EF10_STAT_port_tx_64,
36 EF10_STAT_port_tx_65_to_127,
37 EF10_STAT_port_tx_128_to_255,
38 EF10_STAT_port_tx_256_to_511,
39 EF10_STAT_port_tx_512_to_1023,
40 EF10_STAT_port_tx_1024_to_15xx,
41 EF10_STAT_port_tx_15xx_to_jumbo,
42 EF10_STAT_port_rx_bytes,
43 EF10_STAT_port_rx_bytes_minus_good_bytes,
44 EF10_STAT_port_rx_good_bytes,
45 EF10_STAT_port_rx_bad_bytes,
46 EF10_STAT_port_rx_packets,
47 EF10_STAT_port_rx_good,
48 EF10_STAT_port_rx_bad,
49 EF10_STAT_port_rx_pause,
50 EF10_STAT_port_rx_control,
51 EF10_STAT_port_rx_unicast,
52 EF10_STAT_port_rx_multicast,
53 EF10_STAT_port_rx_broadcast,
54 EF10_STAT_port_rx_lt64,
55 EF10_STAT_port_rx_64,
56 EF10_STAT_port_rx_65_to_127,
57 EF10_STAT_port_rx_128_to_255,
58 EF10_STAT_port_rx_256_to_511,
59 EF10_STAT_port_rx_512_to_1023,
60 EF10_STAT_port_rx_1024_to_15xx,
61 EF10_STAT_port_rx_15xx_to_jumbo,
62 EF10_STAT_port_rx_gtjumbo,
63 EF10_STAT_port_rx_bad_gtjumbo,
64 EF10_STAT_port_rx_overflow,
65 EF10_STAT_port_rx_align_error,
66 EF10_STAT_port_rx_length_error,
67 EF10_STAT_port_rx_nodesc_drops,
68 EF10_STAT_port_rx_pm_trunc_bb_overflow,
69 EF10_STAT_port_rx_pm_discard_bb_overflow,
70 EF10_STAT_port_rx_pm_trunc_vfifo_full,
71 EF10_STAT_port_rx_pm_discard_vfifo_full,
72 EF10_STAT_port_rx_pm_trunc_qbb,
73 EF10_STAT_port_rx_pm_discard_qbb,
74 EF10_STAT_port_rx_pm_discard_mapping,
75 EF10_STAT_port_rx_dp_q_disabled_packets,
76 EF10_STAT_port_rx_dp_di_dropped_packets,
77 EF10_STAT_port_rx_dp_streaming_packets,
78 EF10_STAT_port_rx_dp_hlb_fetch,
79 EF10_STAT_port_rx_dp_hlb_wait,
80 EF10_STAT_rx_unicast,
81 EF10_STAT_rx_unicast_bytes,
82 EF10_STAT_rx_multicast,
83 EF10_STAT_rx_multicast_bytes,
84 EF10_STAT_rx_broadcast,
85 EF10_STAT_rx_broadcast_bytes,
86 EF10_STAT_rx_bad,
87 EF10_STAT_rx_bad_bytes,
88 EF10_STAT_rx_overflow,
89 EF10_STAT_tx_unicast,
90 EF10_STAT_tx_unicast_bytes,
91 EF10_STAT_tx_multicast,
92 EF10_STAT_tx_multicast_bytes,
93 EF10_STAT_tx_broadcast,
94 EF10_STAT_tx_broadcast_bytes,
95 EF10_STAT_tx_bad,
96 EF10_STAT_tx_bad_bytes,
97 EF10_STAT_tx_overflow,
98 EF10_STAT_V1_COUNT,
99 EF10_STAT_fec_uncorrected_errors = EF10_STAT_V1_COUNT,
100 EF10_STAT_fec_corrected_errors,
101 EF10_STAT_fec_corrected_symbols_lane0,
102 EF10_STAT_fec_corrected_symbols_lane1,
103 EF10_STAT_fec_corrected_symbols_lane2,
104 EF10_STAT_fec_corrected_symbols_lane3,
105 EF10_STAT_ctpio_vi_busy_fallback,
106 EF10_STAT_ctpio_long_write_success,
107 EF10_STAT_ctpio_missing_dbell_fail,
108 EF10_STAT_ctpio_overflow_fail,
109 EF10_STAT_ctpio_underflow_fail,
110 EF10_STAT_ctpio_timeout_fail,
111 EF10_STAT_ctpio_noncontig_wr_fail,
112 EF10_STAT_ctpio_frm_clobber_fail,
113 EF10_STAT_ctpio_invalid_wr_fail,
114 EF10_STAT_ctpio_vi_clobber_fallback,
115 EF10_STAT_ctpio_unqualified_fallback,
116 EF10_STAT_ctpio_runt_fallback,
117 EF10_STAT_ctpio_success,
118 EF10_STAT_ctpio_fallback,
119 EF10_STAT_ctpio_poison,
120 EF10_STAT_ctpio_erase,
121 EF10_STAT_COUNT
122};
123
124/* Maximum number of TX PIO buffers we may allocate to a function.
125 * This matches the total number of buffers on each SFC9100-family
126 * controller.
127 */
128#define EF10_TX_PIOBUF_COUNT 16
129
130/**
131 * struct efx_ef10_nic_data - EF10 architecture NIC state
132 * @mcdi_buf: DMA buffer for MCDI
133 * @warm_boot_count: Last seen MC warm boot count
134 * @vi_base: Absolute index of first VI in this function
135 * @n_allocated_vis: Number of VIs allocated to this function
136 * @n_piobufs: Number of PIO buffers allocated to this function
137 * @wc_membase: Base address of write-combining mapping of the memory BAR
138 * @pio_write_base: Base address for writing PIO buffers
139 * @pio_write_vi_base: Relative VI number for @pio_write_base
140 * @piobuf_handle: Handle of each PIO buffer allocated
141 * @piobuf_size: size of a single PIO buffer
142 * @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC
143 * reboot
144 * @mc_stats: Scratch buffer for converting statistics to the kernel's format
145 * @stats: Hardware statistics
146 * @workaround_35388: Flag: firmware supports workaround for bug 35388
147 * @workaround_26807: Flag: firmware supports workaround for bug 26807
148 * @workaround_61265: Flag: firmware supports workaround for bug 61265
149 * @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated
150 * after MC reboot
151 * @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of
152 * %MC_CMD_GET_CAPABILITIES response)
153 * @datapath_caps2: Further Capabilities of datapath firmware (FLAGS2 field of
154 * %MC_CMD_GET_CAPABILITIES response)
155 * @rx_dpcpu_fw_id: Firmware ID of the RxDPCPU
156 * @tx_dpcpu_fw_id: Firmware ID of the TxDPCPU
157 * @must_probe_vswitching: Flag: vswitching has yet to be setup after MC reboot
158 * @pf_index: The number for this PF, or the parent PF if this is a VF
159#ifdef CONFIG_SFC_SRIOV
160 * @vf: Pointer to VF data structure
161#endif
162 * @vport_mac: The MAC address on the vport, only for PFs; VFs will be zero
163 * @vlan_list: List of VLANs added over the interface. Serialised by vlan_lock.
164 * @vlan_lock: Lock to serialize access to vlan_list.
165 * @udp_tunnels: UDP tunnel port numbers and types.
166 * @udp_tunnels_dirty: flag indicating a reboot occurred while pushing
167 * @udp_tunnels to hardware and thus the push must be re-done.
168 * @udp_tunnels_lock: Serialises writes to @udp_tunnels and @udp_tunnels_dirty.
169 */
170struct efx_ef10_nic_data {
171 struct efx_buffer mcdi_buf;
172 u16 warm_boot_count;
173 unsigned int vi_base;
174 unsigned int n_allocated_vis;
175 unsigned int n_piobufs;
176 void __iomem *wc_membase, *pio_write_base;
177 unsigned int pio_write_vi_base;
178 unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT];
179 u16 piobuf_size;
180 bool must_restore_piobufs;
181 __le64 *mc_stats;
182 u64 stats[EF10_STAT_COUNT];
183 bool workaround_35388;
184 bool workaround_26807;
185 bool workaround_61265;
186 bool must_check_datapath_caps;
187 u32 datapath_caps;
188 u32 datapath_caps2;
189 unsigned int rx_dpcpu_fw_id;
190 unsigned int tx_dpcpu_fw_id;
191 bool must_probe_vswitching;
192 unsigned int pf_index;
193 u8 port_id[ETH_ALEN];
194#ifdef CONFIG_SFC_SRIOV
195 unsigned int vf_index;
196 struct ef10_vf *vf;
197#endif
198 u8 vport_mac[ETH_ALEN];
199 struct list_head vlan_list;
200 struct mutex vlan_lock;
201 struct efx_udp_tunnel udp_tunnels[16];
202 bool udp_tunnels_dirty;
203 struct mutex udp_tunnels_lock;
204 u64 licensed_features;
205};
206
207/* TSOv2 */
208int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, struct sk_buff *skb,
209 bool *data_mapped);
210
211extern const struct efx_nic_type efx_hunt_a0_nic_type;
212extern const struct efx_nic_type efx_hunt_a0_vf_nic_type;
213
214#endif /* EFX_NIC_H */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
6 */
7
8#ifndef EFX_NIC_H
9#define EFX_NIC_H
10
11#include "nic_common.h"
12#include "efx.h"
13
14u32 efx_farch_fpga_ver(struct efx_nic *efx);
15
16enum {
17 PHY_TYPE_NONE = 0,
18 PHY_TYPE_TXC43128 = 1,
19 PHY_TYPE_88E1111 = 2,
20 PHY_TYPE_SFX7101 = 3,
21 PHY_TYPE_QT2022C2 = 4,
22 PHY_TYPE_PM8358 = 6,
23 PHY_TYPE_SFT9001A = 8,
24 PHY_TYPE_QT2025C = 9,
25 PHY_TYPE_SFT9001B = 10,
26};
27
28enum {
29 SIENA_STAT_tx_bytes = GENERIC_STAT_COUNT,
30 SIENA_STAT_tx_good_bytes,
31 SIENA_STAT_tx_bad_bytes,
32 SIENA_STAT_tx_packets,
33 SIENA_STAT_tx_bad,
34 SIENA_STAT_tx_pause,
35 SIENA_STAT_tx_control,
36 SIENA_STAT_tx_unicast,
37 SIENA_STAT_tx_multicast,
38 SIENA_STAT_tx_broadcast,
39 SIENA_STAT_tx_lt64,
40 SIENA_STAT_tx_64,
41 SIENA_STAT_tx_65_to_127,
42 SIENA_STAT_tx_128_to_255,
43 SIENA_STAT_tx_256_to_511,
44 SIENA_STAT_tx_512_to_1023,
45 SIENA_STAT_tx_1024_to_15xx,
46 SIENA_STAT_tx_15xx_to_jumbo,
47 SIENA_STAT_tx_gtjumbo,
48 SIENA_STAT_tx_collision,
49 SIENA_STAT_tx_single_collision,
50 SIENA_STAT_tx_multiple_collision,
51 SIENA_STAT_tx_excessive_collision,
52 SIENA_STAT_tx_deferred,
53 SIENA_STAT_tx_late_collision,
54 SIENA_STAT_tx_excessive_deferred,
55 SIENA_STAT_tx_non_tcpudp,
56 SIENA_STAT_tx_mac_src_error,
57 SIENA_STAT_tx_ip_src_error,
58 SIENA_STAT_rx_bytes,
59 SIENA_STAT_rx_good_bytes,
60 SIENA_STAT_rx_bad_bytes,
61 SIENA_STAT_rx_packets,
62 SIENA_STAT_rx_good,
63 SIENA_STAT_rx_bad,
64 SIENA_STAT_rx_pause,
65 SIENA_STAT_rx_control,
66 SIENA_STAT_rx_unicast,
67 SIENA_STAT_rx_multicast,
68 SIENA_STAT_rx_broadcast,
69 SIENA_STAT_rx_lt64,
70 SIENA_STAT_rx_64,
71 SIENA_STAT_rx_65_to_127,
72 SIENA_STAT_rx_128_to_255,
73 SIENA_STAT_rx_256_to_511,
74 SIENA_STAT_rx_512_to_1023,
75 SIENA_STAT_rx_1024_to_15xx,
76 SIENA_STAT_rx_15xx_to_jumbo,
77 SIENA_STAT_rx_gtjumbo,
78 SIENA_STAT_rx_bad_gtjumbo,
79 SIENA_STAT_rx_overflow,
80 SIENA_STAT_rx_false_carrier,
81 SIENA_STAT_rx_symbol_error,
82 SIENA_STAT_rx_align_error,
83 SIENA_STAT_rx_length_error,
84 SIENA_STAT_rx_internal_error,
85 SIENA_STAT_rx_nodesc_drop_cnt,
86 SIENA_STAT_COUNT
87};
88
89/**
90 * struct siena_nic_data - Siena NIC state
91 * @efx: Pointer back to main interface structure
92 * @wol_filter_id: Wake-on-LAN packet filter id
93 * @stats: Hardware statistics
94 * @vf: Array of &struct siena_vf objects
95 * @vf_buftbl_base: The zeroth buffer table index used to back VF queues.
96 * @vfdi_status: Common VFDI status page to be dmad to VF address space.
97 * @local_addr_list: List of local addresses. Protected by %local_lock.
98 * @local_page_list: List of DMA addressable pages used to broadcast
99 * %local_addr_list. Protected by %local_lock.
100 * @local_lock: Mutex protecting %local_addr_list and %local_page_list.
101 * @peer_work: Work item to broadcast peer addresses to VMs.
102 */
103struct siena_nic_data {
104 struct efx_nic *efx;
105 int wol_filter_id;
106 u64 stats[SIENA_STAT_COUNT];
107#ifdef CONFIG_SFC_SRIOV
108 struct siena_vf *vf;
109 struct efx_channel *vfdi_channel;
110 unsigned vf_buftbl_base;
111 struct efx_buffer vfdi_status;
112 struct list_head local_addr_list;
113 struct list_head local_page_list;
114 struct mutex local_lock;
115 struct work_struct peer_work;
116#endif
117};
118
119enum {
120 EF10_STAT_port_tx_bytes = GENERIC_STAT_COUNT,
121 EF10_STAT_port_tx_packets,
122 EF10_STAT_port_tx_pause,
123 EF10_STAT_port_tx_control,
124 EF10_STAT_port_tx_unicast,
125 EF10_STAT_port_tx_multicast,
126 EF10_STAT_port_tx_broadcast,
127 EF10_STAT_port_tx_lt64,
128 EF10_STAT_port_tx_64,
129 EF10_STAT_port_tx_65_to_127,
130 EF10_STAT_port_tx_128_to_255,
131 EF10_STAT_port_tx_256_to_511,
132 EF10_STAT_port_tx_512_to_1023,
133 EF10_STAT_port_tx_1024_to_15xx,
134 EF10_STAT_port_tx_15xx_to_jumbo,
135 EF10_STAT_port_rx_bytes,
136 EF10_STAT_port_rx_bytes_minus_good_bytes,
137 EF10_STAT_port_rx_good_bytes,
138 EF10_STAT_port_rx_bad_bytes,
139 EF10_STAT_port_rx_packets,
140 EF10_STAT_port_rx_good,
141 EF10_STAT_port_rx_bad,
142 EF10_STAT_port_rx_pause,
143 EF10_STAT_port_rx_control,
144 EF10_STAT_port_rx_unicast,
145 EF10_STAT_port_rx_multicast,
146 EF10_STAT_port_rx_broadcast,
147 EF10_STAT_port_rx_lt64,
148 EF10_STAT_port_rx_64,
149 EF10_STAT_port_rx_65_to_127,
150 EF10_STAT_port_rx_128_to_255,
151 EF10_STAT_port_rx_256_to_511,
152 EF10_STAT_port_rx_512_to_1023,
153 EF10_STAT_port_rx_1024_to_15xx,
154 EF10_STAT_port_rx_15xx_to_jumbo,
155 EF10_STAT_port_rx_gtjumbo,
156 EF10_STAT_port_rx_bad_gtjumbo,
157 EF10_STAT_port_rx_overflow,
158 EF10_STAT_port_rx_align_error,
159 EF10_STAT_port_rx_length_error,
160 EF10_STAT_port_rx_nodesc_drops,
161 EF10_STAT_port_rx_pm_trunc_bb_overflow,
162 EF10_STAT_port_rx_pm_discard_bb_overflow,
163 EF10_STAT_port_rx_pm_trunc_vfifo_full,
164 EF10_STAT_port_rx_pm_discard_vfifo_full,
165 EF10_STAT_port_rx_pm_trunc_qbb,
166 EF10_STAT_port_rx_pm_discard_qbb,
167 EF10_STAT_port_rx_pm_discard_mapping,
168 EF10_STAT_port_rx_dp_q_disabled_packets,
169 EF10_STAT_port_rx_dp_di_dropped_packets,
170 EF10_STAT_port_rx_dp_streaming_packets,
171 EF10_STAT_port_rx_dp_hlb_fetch,
172 EF10_STAT_port_rx_dp_hlb_wait,
173 EF10_STAT_rx_unicast,
174 EF10_STAT_rx_unicast_bytes,
175 EF10_STAT_rx_multicast,
176 EF10_STAT_rx_multicast_bytes,
177 EF10_STAT_rx_broadcast,
178 EF10_STAT_rx_broadcast_bytes,
179 EF10_STAT_rx_bad,
180 EF10_STAT_rx_bad_bytes,
181 EF10_STAT_rx_overflow,
182 EF10_STAT_tx_unicast,
183 EF10_STAT_tx_unicast_bytes,
184 EF10_STAT_tx_multicast,
185 EF10_STAT_tx_multicast_bytes,
186 EF10_STAT_tx_broadcast,
187 EF10_STAT_tx_broadcast_bytes,
188 EF10_STAT_tx_bad,
189 EF10_STAT_tx_bad_bytes,
190 EF10_STAT_tx_overflow,
191 EF10_STAT_V1_COUNT,
192 EF10_STAT_fec_uncorrected_errors = EF10_STAT_V1_COUNT,
193 EF10_STAT_fec_corrected_errors,
194 EF10_STAT_fec_corrected_symbols_lane0,
195 EF10_STAT_fec_corrected_symbols_lane1,
196 EF10_STAT_fec_corrected_symbols_lane2,
197 EF10_STAT_fec_corrected_symbols_lane3,
198 EF10_STAT_ctpio_vi_busy_fallback,
199 EF10_STAT_ctpio_long_write_success,
200 EF10_STAT_ctpio_missing_dbell_fail,
201 EF10_STAT_ctpio_overflow_fail,
202 EF10_STAT_ctpio_underflow_fail,
203 EF10_STAT_ctpio_timeout_fail,
204 EF10_STAT_ctpio_noncontig_wr_fail,
205 EF10_STAT_ctpio_frm_clobber_fail,
206 EF10_STAT_ctpio_invalid_wr_fail,
207 EF10_STAT_ctpio_vi_clobber_fallback,
208 EF10_STAT_ctpio_unqualified_fallback,
209 EF10_STAT_ctpio_runt_fallback,
210 EF10_STAT_ctpio_success,
211 EF10_STAT_ctpio_fallback,
212 EF10_STAT_ctpio_poison,
213 EF10_STAT_ctpio_erase,
214 EF10_STAT_COUNT
215};
216
217/* Maximum number of TX PIO buffers we may allocate to a function.
218 * This matches the total number of buffers on each SFC9100-family
219 * controller.
220 */
221#define EF10_TX_PIOBUF_COUNT 16
222
223/**
224 * struct efx_ef10_nic_data - EF10 architecture NIC state
225 * @mcdi_buf: DMA buffer for MCDI
226 * @warm_boot_count: Last seen MC warm boot count
227 * @vi_base: Absolute index of first VI in this function
228 * @n_allocated_vis: Number of VIs allocated to this function
229 * @n_piobufs: Number of PIO buffers allocated to this function
230 * @wc_membase: Base address of write-combining mapping of the memory BAR
231 * @pio_write_base: Base address for writing PIO buffers
232 * @pio_write_vi_base: Relative VI number for @pio_write_base
233 * @piobuf_handle: Handle of each PIO buffer allocated
234 * @piobuf_size: size of a single PIO buffer
235 * @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC
236 * reboot
237 * @mc_stats: Scratch buffer for converting statistics to the kernel's format
238 * @stats: Hardware statistics
239 * @workaround_35388: Flag: firmware supports workaround for bug 35388
240 * @workaround_26807: Flag: firmware supports workaround for bug 26807
241 * @workaround_61265: Flag: firmware supports workaround for bug 61265
242 * @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated
243 * after MC reboot
244 * @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of
245 * %MC_CMD_GET_CAPABILITIES response)
246 * @datapath_caps2: Further Capabilities of datapath firmware (FLAGS2 field of
247 * %MC_CMD_GET_CAPABILITIES response)
248 * @rx_dpcpu_fw_id: Firmware ID of the RxDPCPU
249 * @tx_dpcpu_fw_id: Firmware ID of the TxDPCPU
250 * @must_probe_vswitching: Flag: vswitching has yet to be setup after MC reboot
251 * @pf_index: The number for this PF, or the parent PF if this is a VF
252#ifdef CONFIG_SFC_SRIOV
253 * @vf: Pointer to VF data structure
254#endif
255 * @vport_mac: The MAC address on the vport, only for PFs; VFs will be zero
256 * @vlan_list: List of VLANs added over the interface. Serialised by vlan_lock.
257 * @vlan_lock: Lock to serialize access to vlan_list.
258 * @udp_tunnels: UDP tunnel port numbers and types.
259 * @udp_tunnels_dirty: flag indicating a reboot occurred while pushing
260 * @udp_tunnels to hardware and thus the push must be re-done.
261 * @udp_tunnels_lock: Serialises writes to @udp_tunnels and @udp_tunnels_dirty.
262 */
263struct efx_ef10_nic_data {
264 struct efx_buffer mcdi_buf;
265 u16 warm_boot_count;
266 unsigned int vi_base;
267 unsigned int n_allocated_vis;
268 unsigned int n_piobufs;
269 void __iomem *wc_membase, *pio_write_base;
270 unsigned int pio_write_vi_base;
271 unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT];
272 u16 piobuf_size;
273 bool must_restore_piobufs;
274 __le64 *mc_stats;
275 u64 stats[EF10_STAT_COUNT];
276 bool workaround_35388;
277 bool workaround_26807;
278 bool workaround_61265;
279 bool must_check_datapath_caps;
280 u32 datapath_caps;
281 u32 datapath_caps2;
282 unsigned int rx_dpcpu_fw_id;
283 unsigned int tx_dpcpu_fw_id;
284 bool must_probe_vswitching;
285 unsigned int pf_index;
286 u8 port_id[ETH_ALEN];
287#ifdef CONFIG_SFC_SRIOV
288 unsigned int vf_index;
289 struct ef10_vf *vf;
290#endif
291 u8 vport_mac[ETH_ALEN];
292 struct list_head vlan_list;
293 struct mutex vlan_lock;
294 struct efx_udp_tunnel udp_tunnels[16];
295 bool udp_tunnels_dirty;
296 struct mutex udp_tunnels_lock;
297 u64 licensed_features;
298};
299
300/* TSOv2 */
301int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, struct sk_buff *skb,
302 bool *data_mapped);
303
304int efx_init_sriov(void);
305void efx_fini_sriov(void);
306
307extern const struct efx_nic_type siena_a0_nic_type;
308extern const struct efx_nic_type efx_hunt_a0_nic_type;
309extern const struct efx_nic_type efx_hunt_a0_vf_nic_type;
310
311int falcon_probe_board(struct efx_nic *efx, u16 revision_info);
312
313/* Falcon/Siena queue operations */
314int efx_farch_tx_probe(struct efx_tx_queue *tx_queue);
315void efx_farch_tx_init(struct efx_tx_queue *tx_queue);
316void efx_farch_tx_fini(struct efx_tx_queue *tx_queue);
317void efx_farch_tx_remove(struct efx_tx_queue *tx_queue);
318void efx_farch_tx_write(struct efx_tx_queue *tx_queue);
319unsigned int efx_farch_tx_limit_len(struct efx_tx_queue *tx_queue,
320 dma_addr_t dma_addr, unsigned int len);
321int efx_farch_rx_probe(struct efx_rx_queue *rx_queue);
322void efx_farch_rx_init(struct efx_rx_queue *rx_queue);
323void efx_farch_rx_fini(struct efx_rx_queue *rx_queue);
324void efx_farch_rx_remove(struct efx_rx_queue *rx_queue);
325void efx_farch_rx_write(struct efx_rx_queue *rx_queue);
326void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue);
327int efx_farch_ev_probe(struct efx_channel *channel);
328int efx_farch_ev_init(struct efx_channel *channel);
329void efx_farch_ev_fini(struct efx_channel *channel);
330void efx_farch_ev_remove(struct efx_channel *channel);
331int efx_farch_ev_process(struct efx_channel *channel, int quota);
332void efx_farch_ev_read_ack(struct efx_channel *channel);
333void efx_farch_ev_test_generate(struct efx_channel *channel);
334
335/* Falcon/Siena filter operations */
336int efx_farch_filter_table_probe(struct efx_nic *efx);
337void efx_farch_filter_table_restore(struct efx_nic *efx);
338void efx_farch_filter_table_remove(struct efx_nic *efx);
339void efx_farch_filter_update_rx_scatter(struct efx_nic *efx);
340s32 efx_farch_filter_insert(struct efx_nic *efx, struct efx_filter_spec *spec,
341 bool replace);
342int efx_farch_filter_remove_safe(struct efx_nic *efx,
343 enum efx_filter_priority priority,
344 u32 filter_id);
345int efx_farch_filter_get_safe(struct efx_nic *efx,
346 enum efx_filter_priority priority, u32 filter_id,
347 struct efx_filter_spec *);
348int efx_farch_filter_clear_rx(struct efx_nic *efx,
349 enum efx_filter_priority priority);
350u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
351 enum efx_filter_priority priority);
352u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx);
353s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
354 enum efx_filter_priority priority, u32 *buf,
355 u32 size);
356#ifdef CONFIG_RFS_ACCEL
357bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
358 unsigned int index);
359#endif
360void efx_farch_filter_sync_rx_mode(struct efx_nic *efx);
361
362/* Falcon/Siena interrupts */
363void efx_farch_irq_enable_master(struct efx_nic *efx);
364int efx_farch_irq_test_generate(struct efx_nic *efx);
365void efx_farch_irq_disable_master(struct efx_nic *efx);
366irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id);
367irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id);
368irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx);
369
370/* Global Resources */
371void siena_prepare_flush(struct efx_nic *efx);
372int efx_farch_fini_dmaq(struct efx_nic *efx);
373void efx_farch_finish_flr(struct efx_nic *efx);
374void siena_finish_flush(struct efx_nic *efx);
375void falcon_start_nic_stats(struct efx_nic *efx);
376void falcon_stop_nic_stats(struct efx_nic *efx);
377int falcon_reset_xaui(struct efx_nic *efx);
378void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
379void efx_farch_init_common(struct efx_nic *efx);
380void efx_farch_rx_push_indir_table(struct efx_nic *efx);
381void efx_farch_rx_pull_indir_table(struct efx_nic *efx);
382
383/* Tests */
384struct efx_farch_register_test {
385 unsigned address;
386 efx_oword_t mask;
387};
388
389int efx_farch_test_registers(struct efx_nic *efx,
390 const struct efx_farch_register_test *regs,
391 size_t n_regs);
392
393void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
394 efx_qword_t *event);
395
396#endif /* EFX_NIC_H */