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v6.8
  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/****************************************************************************
  3 * Driver for Solarflare network controllers and boards
  4 * Copyright 2005-2006 Fen Systems Ltd.
  5 * Copyright 2006-2013 Solarflare Communications Inc.
  6 */
  7
  8#ifndef EFX_NIC_H
  9#define EFX_NIC_H
 10
 11#include "nic_common.h"
 12#include "efx.h"
 13
 14enum {
 15	PHY_TYPE_NONE = 0,
 16	PHY_TYPE_TXC43128 = 1,
 17	PHY_TYPE_88E1111 = 2,
 18	PHY_TYPE_SFX7101 = 3,
 19	PHY_TYPE_QT2022C2 = 4,
 20	PHY_TYPE_PM8358 = 6,
 21	PHY_TYPE_SFT9001A = 8,
 22	PHY_TYPE_QT2025C = 9,
 23	PHY_TYPE_SFT9001B = 10,
 24};
 25
 26enum {
 27	EF10_STAT_port_tx_bytes = GENERIC_STAT_COUNT,
 28	EF10_STAT_port_tx_packets,
 29	EF10_STAT_port_tx_pause,
 30	EF10_STAT_port_tx_control,
 31	EF10_STAT_port_tx_unicast,
 32	EF10_STAT_port_tx_multicast,
 33	EF10_STAT_port_tx_broadcast,
 34	EF10_STAT_port_tx_lt64,
 35	EF10_STAT_port_tx_64,
 36	EF10_STAT_port_tx_65_to_127,
 37	EF10_STAT_port_tx_128_to_255,
 38	EF10_STAT_port_tx_256_to_511,
 39	EF10_STAT_port_tx_512_to_1023,
 40	EF10_STAT_port_tx_1024_to_15xx,
 41	EF10_STAT_port_tx_15xx_to_jumbo,
 42	EF10_STAT_port_rx_bytes,
 43	EF10_STAT_port_rx_bytes_minus_good_bytes,
 44	EF10_STAT_port_rx_good_bytes,
 45	EF10_STAT_port_rx_bad_bytes,
 46	EF10_STAT_port_rx_packets,
 47	EF10_STAT_port_rx_good,
 48	EF10_STAT_port_rx_bad,
 49	EF10_STAT_port_rx_pause,
 50	EF10_STAT_port_rx_control,
 51	EF10_STAT_port_rx_unicast,
 52	EF10_STAT_port_rx_multicast,
 53	EF10_STAT_port_rx_broadcast,
 54	EF10_STAT_port_rx_lt64,
 55	EF10_STAT_port_rx_64,
 56	EF10_STAT_port_rx_65_to_127,
 57	EF10_STAT_port_rx_128_to_255,
 58	EF10_STAT_port_rx_256_to_511,
 59	EF10_STAT_port_rx_512_to_1023,
 60	EF10_STAT_port_rx_1024_to_15xx,
 61	EF10_STAT_port_rx_15xx_to_jumbo,
 62	EF10_STAT_port_rx_gtjumbo,
 63	EF10_STAT_port_rx_bad_gtjumbo,
 64	EF10_STAT_port_rx_overflow,
 65	EF10_STAT_port_rx_align_error,
 66	EF10_STAT_port_rx_length_error,
 67	EF10_STAT_port_rx_nodesc_drops,
 68	EF10_STAT_port_rx_pm_trunc_bb_overflow,
 69	EF10_STAT_port_rx_pm_discard_bb_overflow,
 70	EF10_STAT_port_rx_pm_trunc_vfifo_full,
 71	EF10_STAT_port_rx_pm_discard_vfifo_full,
 72	EF10_STAT_port_rx_pm_trunc_qbb,
 73	EF10_STAT_port_rx_pm_discard_qbb,
 74	EF10_STAT_port_rx_pm_discard_mapping,
 75	EF10_STAT_port_rx_dp_q_disabled_packets,
 76	EF10_STAT_port_rx_dp_di_dropped_packets,
 77	EF10_STAT_port_rx_dp_streaming_packets,
 78	EF10_STAT_port_rx_dp_hlb_fetch,
 79	EF10_STAT_port_rx_dp_hlb_wait,
 80	EF10_STAT_rx_unicast,
 81	EF10_STAT_rx_unicast_bytes,
 82	EF10_STAT_rx_multicast,
 83	EF10_STAT_rx_multicast_bytes,
 84	EF10_STAT_rx_broadcast,
 85	EF10_STAT_rx_broadcast_bytes,
 86	EF10_STAT_rx_bad,
 87	EF10_STAT_rx_bad_bytes,
 88	EF10_STAT_rx_overflow,
 89	EF10_STAT_tx_unicast,
 90	EF10_STAT_tx_unicast_bytes,
 91	EF10_STAT_tx_multicast,
 92	EF10_STAT_tx_multicast_bytes,
 93	EF10_STAT_tx_broadcast,
 94	EF10_STAT_tx_broadcast_bytes,
 95	EF10_STAT_tx_bad,
 96	EF10_STAT_tx_bad_bytes,
 97	EF10_STAT_tx_overflow,
 98	EF10_STAT_V1_COUNT,
 99	EF10_STAT_fec_uncorrected_errors = EF10_STAT_V1_COUNT,
100	EF10_STAT_fec_corrected_errors,
101	EF10_STAT_fec_corrected_symbols_lane0,
102	EF10_STAT_fec_corrected_symbols_lane1,
103	EF10_STAT_fec_corrected_symbols_lane2,
104	EF10_STAT_fec_corrected_symbols_lane3,
105	EF10_STAT_ctpio_vi_busy_fallback,
106	EF10_STAT_ctpio_long_write_success,
107	EF10_STAT_ctpio_missing_dbell_fail,
108	EF10_STAT_ctpio_overflow_fail,
109	EF10_STAT_ctpio_underflow_fail,
110	EF10_STAT_ctpio_timeout_fail,
111	EF10_STAT_ctpio_noncontig_wr_fail,
112	EF10_STAT_ctpio_frm_clobber_fail,
113	EF10_STAT_ctpio_invalid_wr_fail,
114	EF10_STAT_ctpio_vi_clobber_fallback,
115	EF10_STAT_ctpio_unqualified_fallback,
116	EF10_STAT_ctpio_runt_fallback,
117	EF10_STAT_ctpio_success,
118	EF10_STAT_ctpio_fallback,
119	EF10_STAT_ctpio_poison,
120	EF10_STAT_ctpio_erase,
121	EF10_STAT_COUNT
122};
123
124/* Maximum number of TX PIO buffers we may allocate to a function.
125 * This matches the total number of buffers on each SFC9100-family
126 * controller.
127 */
128#define EF10_TX_PIOBUF_COUNT 16
129
130/**
131 * struct efx_ef10_nic_data - EF10 architecture NIC state
132 * @mcdi_buf: DMA buffer for MCDI
133 * @warm_boot_count: Last seen MC warm boot count
134 * @vi_base: Absolute index of first VI in this function
135 * @n_allocated_vis: Number of VIs allocated to this function
136 * @n_piobufs: Number of PIO buffers allocated to this function
137 * @wc_membase: Base address of write-combining mapping of the memory BAR
138 * @pio_write_base: Base address for writing PIO buffers
139 * @pio_write_vi_base: Relative VI number for @pio_write_base
140 * @piobuf_handle: Handle of each PIO buffer allocated
141 * @piobuf_size: size of a single PIO buffer
142 * @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC
143 *	reboot
144 * @mc_stats: Scratch buffer for converting statistics to the kernel's format
145 * @stats: Hardware statistics
146 * @workaround_35388: Flag: firmware supports workaround for bug 35388
147 * @workaround_26807: Flag: firmware supports workaround for bug 26807
148 * @workaround_61265: Flag: firmware supports workaround for bug 61265
149 * @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated
150 *	after MC reboot
151 * @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of
152 *	%MC_CMD_GET_CAPABILITIES response)
153 * @datapath_caps2: Further Capabilities of datapath firmware (FLAGS2 field of
154 * %MC_CMD_GET_CAPABILITIES response)
155 * @rx_dpcpu_fw_id: Firmware ID of the RxDPCPU
156 * @tx_dpcpu_fw_id: Firmware ID of the TxDPCPU
157 * @must_probe_vswitching: Flag: vswitching has yet to be setup after MC reboot
158 * @pf_index: The number for this PF, or the parent PF if this is a VF
159#ifdef CONFIG_SFC_SRIOV
160 * @vf: Pointer to VF data structure
161#endif
162 * @vport_mac: The MAC address on the vport, only for PFs; VFs will be zero
163 * @vlan_list: List of VLANs added over the interface. Serialised by vlan_lock.
164 * @vlan_lock: Lock to serialize access to vlan_list.
165 * @udp_tunnels: UDP tunnel port numbers and types.
166 * @udp_tunnels_dirty: flag indicating a reboot occurred while pushing
167 *	@udp_tunnels to hardware and thus the push must be re-done.
168 * @udp_tunnels_lock: Serialises writes to @udp_tunnels and @udp_tunnels_dirty.
169 */
170struct efx_ef10_nic_data {
171	struct efx_buffer mcdi_buf;
172	u16 warm_boot_count;
173	unsigned int vi_base;
174	unsigned int n_allocated_vis;
175	unsigned int n_piobufs;
176	void __iomem *wc_membase, *pio_write_base;
177	unsigned int pio_write_vi_base;
178	unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT];
179	u16 piobuf_size;
180	bool must_restore_piobufs;
181	__le64 *mc_stats;
182	u64 stats[EF10_STAT_COUNT];
183	bool workaround_35388;
184	bool workaround_26807;
185	bool workaround_61265;
186	bool must_check_datapath_caps;
187	u32 datapath_caps;
188	u32 datapath_caps2;
189	unsigned int rx_dpcpu_fw_id;
190	unsigned int tx_dpcpu_fw_id;
191	bool must_probe_vswitching;
192	unsigned int pf_index;
193	u8 port_id[ETH_ALEN];
194#ifdef CONFIG_SFC_SRIOV
195	unsigned int vf_index;
196	struct ef10_vf *vf;
197#endif
198	u8 vport_mac[ETH_ALEN];
199	struct list_head vlan_list;
200	struct mutex vlan_lock;
201	struct efx_udp_tunnel udp_tunnels[16];
202	bool udp_tunnels_dirty;
203	struct mutex udp_tunnels_lock;
204	u64 licensed_features;
205};
206
207/* TSOv2 */
208int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, struct sk_buff *skb,
209			 bool *data_mapped);
210
211extern const struct efx_nic_type efx_hunt_a0_nic_type;
212extern const struct efx_nic_type efx_hunt_a0_vf_nic_type;
213
 
 
214#endif /* EFX_NIC_H */
v6.13.7
  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/****************************************************************************
  3 * Driver for Solarflare network controllers and boards
  4 * Copyright 2005-2006 Fen Systems Ltd.
  5 * Copyright 2006-2013 Solarflare Communications Inc.
  6 */
  7
  8#ifndef EFX_NIC_H
  9#define EFX_NIC_H
 10
 11#include "nic_common.h"
 12#include "efx.h"
 13
 14enum {
 15	PHY_TYPE_NONE = 0,
 16	PHY_TYPE_TXC43128 = 1,
 17	PHY_TYPE_88E1111 = 2,
 18	PHY_TYPE_SFX7101 = 3,
 19	PHY_TYPE_QT2022C2 = 4,
 20	PHY_TYPE_PM8358 = 6,
 21	PHY_TYPE_SFT9001A = 8,
 22	PHY_TYPE_QT2025C = 9,
 23	PHY_TYPE_SFT9001B = 10,
 24};
 25
 26enum {
 27	EF10_STAT_port_tx_bytes = GENERIC_STAT_COUNT,
 28	EF10_STAT_port_tx_packets,
 29	EF10_STAT_port_tx_pause,
 30	EF10_STAT_port_tx_control,
 31	EF10_STAT_port_tx_unicast,
 32	EF10_STAT_port_tx_multicast,
 33	EF10_STAT_port_tx_broadcast,
 34	EF10_STAT_port_tx_lt64,
 35	EF10_STAT_port_tx_64,
 36	EF10_STAT_port_tx_65_to_127,
 37	EF10_STAT_port_tx_128_to_255,
 38	EF10_STAT_port_tx_256_to_511,
 39	EF10_STAT_port_tx_512_to_1023,
 40	EF10_STAT_port_tx_1024_to_15xx,
 41	EF10_STAT_port_tx_15xx_to_jumbo,
 42	EF10_STAT_port_rx_bytes,
 43	EF10_STAT_port_rx_bytes_minus_good_bytes,
 44	EF10_STAT_port_rx_good_bytes,
 45	EF10_STAT_port_rx_bad_bytes,
 46	EF10_STAT_port_rx_packets,
 47	EF10_STAT_port_rx_good,
 48	EF10_STAT_port_rx_bad,
 49	EF10_STAT_port_rx_pause,
 50	EF10_STAT_port_rx_control,
 51	EF10_STAT_port_rx_unicast,
 52	EF10_STAT_port_rx_multicast,
 53	EF10_STAT_port_rx_broadcast,
 54	EF10_STAT_port_rx_lt64,
 55	EF10_STAT_port_rx_64,
 56	EF10_STAT_port_rx_65_to_127,
 57	EF10_STAT_port_rx_128_to_255,
 58	EF10_STAT_port_rx_256_to_511,
 59	EF10_STAT_port_rx_512_to_1023,
 60	EF10_STAT_port_rx_1024_to_15xx,
 61	EF10_STAT_port_rx_15xx_to_jumbo,
 62	EF10_STAT_port_rx_gtjumbo,
 63	EF10_STAT_port_rx_bad_gtjumbo,
 64	EF10_STAT_port_rx_overflow,
 65	EF10_STAT_port_rx_align_error,
 66	EF10_STAT_port_rx_length_error,
 67	EF10_STAT_port_rx_nodesc_drops,
 68	EF10_STAT_port_rx_pm_trunc_bb_overflow,
 69	EF10_STAT_port_rx_pm_discard_bb_overflow,
 70	EF10_STAT_port_rx_pm_trunc_vfifo_full,
 71	EF10_STAT_port_rx_pm_discard_vfifo_full,
 72	EF10_STAT_port_rx_pm_trunc_qbb,
 73	EF10_STAT_port_rx_pm_discard_qbb,
 74	EF10_STAT_port_rx_pm_discard_mapping,
 75	EF10_STAT_port_rx_dp_q_disabled_packets,
 76	EF10_STAT_port_rx_dp_di_dropped_packets,
 77	EF10_STAT_port_rx_dp_streaming_packets,
 78	EF10_STAT_port_rx_dp_hlb_fetch,
 79	EF10_STAT_port_rx_dp_hlb_wait,
 80	EF10_STAT_rx_unicast,
 81	EF10_STAT_rx_unicast_bytes,
 82	EF10_STAT_rx_multicast,
 83	EF10_STAT_rx_multicast_bytes,
 84	EF10_STAT_rx_broadcast,
 85	EF10_STAT_rx_broadcast_bytes,
 86	EF10_STAT_rx_bad,
 87	EF10_STAT_rx_bad_bytes,
 88	EF10_STAT_rx_overflow,
 89	EF10_STAT_tx_unicast,
 90	EF10_STAT_tx_unicast_bytes,
 91	EF10_STAT_tx_multicast,
 92	EF10_STAT_tx_multicast_bytes,
 93	EF10_STAT_tx_broadcast,
 94	EF10_STAT_tx_broadcast_bytes,
 95	EF10_STAT_tx_bad,
 96	EF10_STAT_tx_bad_bytes,
 97	EF10_STAT_tx_overflow,
 98	EF10_STAT_V1_COUNT,
 99	EF10_STAT_fec_uncorrected_errors = EF10_STAT_V1_COUNT,
100	EF10_STAT_fec_corrected_errors,
101	EF10_STAT_fec_corrected_symbols_lane0,
102	EF10_STAT_fec_corrected_symbols_lane1,
103	EF10_STAT_fec_corrected_symbols_lane2,
104	EF10_STAT_fec_corrected_symbols_lane3,
105	EF10_STAT_ctpio_vi_busy_fallback,
106	EF10_STAT_ctpio_long_write_success,
107	EF10_STAT_ctpio_missing_dbell_fail,
108	EF10_STAT_ctpio_overflow_fail,
109	EF10_STAT_ctpio_underflow_fail,
110	EF10_STAT_ctpio_timeout_fail,
111	EF10_STAT_ctpio_noncontig_wr_fail,
112	EF10_STAT_ctpio_frm_clobber_fail,
113	EF10_STAT_ctpio_invalid_wr_fail,
114	EF10_STAT_ctpio_vi_clobber_fallback,
115	EF10_STAT_ctpio_unqualified_fallback,
116	EF10_STAT_ctpio_runt_fallback,
117	EF10_STAT_ctpio_success,
118	EF10_STAT_ctpio_fallback,
119	EF10_STAT_ctpio_poison,
120	EF10_STAT_ctpio_erase,
121	EF10_STAT_COUNT
122};
123
124/* Maximum number of TX PIO buffers we may allocate to a function.
125 * This matches the total number of buffers on each SFC9100-family
126 * controller.
127 */
128#define EF10_TX_PIOBUF_COUNT 16
129
130/**
131 * struct efx_ef10_nic_data - EF10 architecture NIC state
132 * @mcdi_buf: DMA buffer for MCDI
133 * @warm_boot_count: Last seen MC warm boot count
134 * @vi_base: Absolute index of first VI in this function
135 * @n_allocated_vis: Number of VIs allocated to this function
136 * @n_piobufs: Number of PIO buffers allocated to this function
137 * @wc_membase: Base address of write-combining mapping of the memory BAR
138 * @pio_write_base: Base address for writing PIO buffers
139 * @pio_write_vi_base: Relative VI number for @pio_write_base
140 * @piobuf_handle: Handle of each PIO buffer allocated
141 * @piobuf_size: size of a single PIO buffer
142 * @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC
143 *	reboot
144 * @mc_stats: Scratch buffer for converting statistics to the kernel's format
145 * @stats: Hardware statistics
146 * @workaround_35388: Flag: firmware supports workaround for bug 35388
147 * @workaround_26807: Flag: firmware supports workaround for bug 26807
148 * @workaround_61265: Flag: firmware supports workaround for bug 61265
149 * @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated
150 *	after MC reboot
151 * @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of
152 *	%MC_CMD_GET_CAPABILITIES response)
153 * @datapath_caps2: Further Capabilities of datapath firmware (FLAGS2 field of
154 * %MC_CMD_GET_CAPABILITIES response)
155 * @rx_dpcpu_fw_id: Firmware ID of the RxDPCPU
156 * @tx_dpcpu_fw_id: Firmware ID of the TxDPCPU
157 * @must_probe_vswitching: Flag: vswitching has yet to be setup after MC reboot
158 * @pf_index: The number for this PF, or the parent PF if this is a VF
159#ifdef CONFIG_SFC_SRIOV
160 * @vf: Pointer to VF data structure
161#endif
162 * @vport_mac: The MAC address on the vport, only for PFs; VFs will be zero
163 * @vlan_list: List of VLANs added over the interface. Serialised by vlan_lock.
164 * @vlan_lock: Lock to serialize access to vlan_list.
165 * @udp_tunnels: UDP tunnel port numbers and types.
166 * @udp_tunnels_dirty: flag indicating a reboot occurred while pushing
167 *	@udp_tunnels to hardware and thus the push must be re-done.
168 * @udp_tunnels_lock: Serialises writes to @udp_tunnels and @udp_tunnels_dirty.
169 */
170struct efx_ef10_nic_data {
171	struct efx_buffer mcdi_buf;
172	u16 warm_boot_count;
173	unsigned int vi_base;
174	unsigned int n_allocated_vis;
175	unsigned int n_piobufs;
176	void __iomem *wc_membase, *pio_write_base;
177	unsigned int pio_write_vi_base;
178	unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT];
179	u16 piobuf_size;
180	bool must_restore_piobufs;
181	__le64 *mc_stats;
182	u64 stats[EF10_STAT_COUNT];
183	bool workaround_35388;
184	bool workaround_26807;
185	bool workaround_61265;
186	bool must_check_datapath_caps;
187	u32 datapath_caps;
188	u32 datapath_caps2;
189	unsigned int rx_dpcpu_fw_id;
190	unsigned int tx_dpcpu_fw_id;
191	bool must_probe_vswitching;
192	unsigned int pf_index;
193	u8 port_id[ETH_ALEN];
194#ifdef CONFIG_SFC_SRIOV
195	unsigned int vf_index;
196	struct ef10_vf *vf;
197#endif
198	u8 vport_mac[ETH_ALEN];
199	struct list_head vlan_list;
200	struct mutex vlan_lock;
201	struct efx_udp_tunnel udp_tunnels[16];
202	bool udp_tunnels_dirty;
203	struct mutex udp_tunnels_lock;
204	u64 licensed_features;
205};
206
207/* TSOv2 */
208int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, struct sk_buff *skb,
209			 bool *data_mapped);
210
211extern const struct efx_nic_type efx_hunt_a0_nic_type;
212extern const struct efx_nic_type efx_hunt_a0_vf_nic_type;
213
214extern const struct efx_nic_type efx_x4_nic_type;
215
216#endif /* EFX_NIC_H */