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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
4 * Provides Bus interface for MIIM regs
5 *
6 * Author: Andy Fleming <afleming@freescale.com>
7 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
8 *
9 * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
10 *
11 * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
12 */
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/string.h>
17#include <linux/errno.h>
18#include <linux/slab.h>
19#include <linux/delay.h>
20#include <linux/module.h>
21#include <linux/mii.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/of_mdio.h>
25#include <linux/property.h>
26
27#include <asm/io.h>
28#if IS_ENABLED(CONFIG_UCC_GETH)
29#include <soc/fsl/qe/ucc.h>
30#endif
31
32#include "gianfar.h"
33
34#define MIIMIND_BUSY 0x00000001
35#define MIIMIND_NOTVALID 0x00000004
36#define MIIMCFG_INIT_VALUE 0x00000007
37#define MIIMCFG_RESET 0x80000000
38
39#define MII_READ_COMMAND 0x00000001
40
41struct fsl_pq_mii {
42 u32 miimcfg; /* MII management configuration reg */
43 u32 miimcom; /* MII management command reg */
44 u32 miimadd; /* MII management address reg */
45 u32 miimcon; /* MII management control reg */
46 u32 miimstat; /* MII management status reg */
47 u32 miimind; /* MII management indication reg */
48};
49
50struct fsl_pq_mdio {
51 u8 res1[16];
52 u32 ieventm; /* MDIO Interrupt event register (for etsec2)*/
53 u32 imaskm; /* MDIO Interrupt mask register (for etsec2)*/
54 u8 res2[4];
55 u32 emapm; /* MDIO Event mapping register (for etsec2)*/
56 u8 res3[1280];
57 struct fsl_pq_mii mii;
58 u8 res4[28];
59 u32 utbipar; /* TBI phy address reg (only on UCC) */
60 u8 res5[2728];
61} __packed;
62
63/* Number of microseconds to wait for an MII register to respond */
64#define MII_TIMEOUT 1000
65
66struct fsl_pq_mdio_priv {
67 void __iomem *map;
68 struct fsl_pq_mii __iomem *regs;
69};
70
71/*
72 * Per-device-type data. Each type of device tree node that we support gets
73 * one of these.
74 *
75 * @mii_offset: the offset of the MII registers within the memory map of the
76 * node. Some nodes define only the MII registers, and some define the whole
77 * MAC (which includes the MII registers).
78 *
79 * @get_tbipa: determines the address of the TBIPA register
80 *
81 * @ucc_configure: a special function for extra QE configuration
82 */
83struct fsl_pq_mdio_data {
84 unsigned int mii_offset; /* offset of the MII registers */
85 uint32_t __iomem * (*get_tbipa)(void __iomem *p);
86 void (*ucc_configure)(phys_addr_t start, phys_addr_t end);
87};
88
89/*
90 * Write value to the PHY at mii_id at register regnum, on the bus attached
91 * to the local interface, which may be different from the generic mdio bus
92 * (tied to a single interface), waiting until the write is done before
93 * returning. This is helpful in programming interfaces like the TBI which
94 * control interfaces like onchip SERDES and are always tied to the local
95 * mdio pins, which may not be the same as system mdio bus, used for
96 * controlling the external PHYs, for example.
97 */
98static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
99 u16 value)
100{
101 struct fsl_pq_mdio_priv *priv = bus->priv;
102 struct fsl_pq_mii __iomem *regs = priv->regs;
103 unsigned int timeout;
104
105 /* Set the PHY address and the register address we want to write */
106 iowrite32be((mii_id << 8) | regnum, ®s->miimadd);
107
108 /* Write out the value we want */
109 iowrite32be(value, ®s->miimcon);
110
111 /* Wait for the transaction to finish */
112 timeout = MII_TIMEOUT;
113 while ((ioread32be(®s->miimind) & MIIMIND_BUSY) && timeout) {
114 cpu_relax();
115 timeout--;
116 }
117
118 return timeout ? 0 : -ETIMEDOUT;
119}
120
121/*
122 * Read the bus for PHY at addr mii_id, register regnum, and return the value.
123 * Clears miimcom first.
124 *
125 * All PHY operation done on the bus attached to the local interface, which
126 * may be different from the generic mdio bus. This is helpful in programming
127 * interfaces like the TBI which, in turn, control interfaces like on-chip
128 * SERDES and are always tied to the local mdio pins, which may not be the
129 * same as system mdio bus, used for controlling the external PHYs, for eg.
130 */
131static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
132{
133 struct fsl_pq_mdio_priv *priv = bus->priv;
134 struct fsl_pq_mii __iomem *regs = priv->regs;
135 unsigned int timeout;
136 u16 value;
137
138 /* Set the PHY address and the register address we want to read */
139 iowrite32be((mii_id << 8) | regnum, ®s->miimadd);
140
141 /* Clear miimcom, and then initiate a read */
142 iowrite32be(0, ®s->miimcom);
143 iowrite32be(MII_READ_COMMAND, ®s->miimcom);
144
145 /* Wait for the transaction to finish, normally less than 100us */
146 timeout = MII_TIMEOUT;
147 while ((ioread32be(®s->miimind) &
148 (MIIMIND_NOTVALID | MIIMIND_BUSY)) && timeout) {
149 cpu_relax();
150 timeout--;
151 }
152
153 if (!timeout)
154 return -ETIMEDOUT;
155
156 /* Grab the value of the register from miimstat */
157 value = ioread32be(®s->miimstat);
158
159 dev_dbg(&bus->dev, "read %04x from address %x/%x\n", value, mii_id, regnum);
160 return value;
161}
162
163/* Reset the MIIM registers, and wait for the bus to free */
164static int fsl_pq_mdio_reset(struct mii_bus *bus)
165{
166 struct fsl_pq_mdio_priv *priv = bus->priv;
167 struct fsl_pq_mii __iomem *regs = priv->regs;
168 unsigned int timeout;
169
170 mutex_lock(&bus->mdio_lock);
171
172 /* Reset the management interface */
173 iowrite32be(MIIMCFG_RESET, ®s->miimcfg);
174
175 /* Setup the MII Mgmt clock speed */
176 iowrite32be(MIIMCFG_INIT_VALUE, ®s->miimcfg);
177
178 /* Wait until the bus is free */
179 timeout = MII_TIMEOUT;
180 while ((ioread32be(®s->miimind) & MIIMIND_BUSY) && timeout) {
181 cpu_relax();
182 timeout--;
183 }
184
185 mutex_unlock(&bus->mdio_lock);
186
187 if (!timeout) {
188 dev_err(&bus->dev, "timeout waiting for MII bus\n");
189 return -EBUSY;
190 }
191
192 return 0;
193}
194
195#if IS_ENABLED(CONFIG_GIANFAR)
196/*
197 * Return the TBIPA address, starting from the address
198 * of the mapped GFAR MDIO registers (struct gfar)
199 * This is mildly evil, but so is our hardware for doing this.
200 * Also, we have to cast back to struct gfar because of
201 * definition weirdness done in gianfar.h.
202 */
203static uint32_t __iomem *get_gfar_tbipa_from_mdio(void __iomem *p)
204{
205 struct gfar __iomem *enet_regs = p;
206
207 return &enet_regs->tbipa;
208}
209
210/*
211 * Return the TBIPA address, starting from the address
212 * of the mapped GFAR MII registers (gfar_mii_regs[] within struct gfar)
213 */
214static uint32_t __iomem *get_gfar_tbipa_from_mii(void __iomem *p)
215{
216 return get_gfar_tbipa_from_mdio(container_of(p, struct gfar, gfar_mii_regs));
217}
218
219/*
220 * Return the TBIPAR address for an eTSEC2 node
221 */
222static uint32_t __iomem *get_etsec_tbipa(void __iomem *p)
223{
224 return p;
225}
226#endif
227
228#if IS_ENABLED(CONFIG_UCC_GETH)
229/*
230 * Return the TBIPAR address for a QE MDIO node, starting from the address
231 * of the mapped MII registers (struct fsl_pq_mii)
232 */
233static uint32_t __iomem *get_ucc_tbipa(void __iomem *p)
234{
235 struct fsl_pq_mdio __iomem *mdio = container_of(p, struct fsl_pq_mdio, mii);
236
237 return &mdio->utbipar;
238}
239
240/*
241 * Find the UCC node that controls the given MDIO node
242 *
243 * For some reason, the QE MDIO nodes are not children of the UCC devices
244 * that control them. Therefore, we need to scan all UCC nodes looking for
245 * the one that encompases the given MDIO node. We do this by comparing
246 * physical addresses. The 'start' and 'end' addresses of the MDIO node are
247 * passed, and the correct UCC node will cover the entire address range.
248 *
249 * This assumes that there is only one QE MDIO node in the entire device tree.
250 */
251static void ucc_configure(phys_addr_t start, phys_addr_t end)
252{
253 static bool found_mii_master;
254 struct device_node *np = NULL;
255
256 if (found_mii_master)
257 return;
258
259 for_each_compatible_node(np, NULL, "ucc_geth") {
260 struct resource res;
261 const uint32_t *iprop;
262 uint32_t id;
263 int ret;
264
265 ret = of_address_to_resource(np, 0, &res);
266 if (ret < 0) {
267 pr_debug("fsl-pq-mdio: no address range in node %pOF\n",
268 np);
269 continue;
270 }
271
272 /* if our mdio regs fall within this UCC regs range */
273 if ((start < res.start) || (end > res.end))
274 continue;
275
276 iprop = of_get_property(np, "cell-index", NULL);
277 if (!iprop) {
278 iprop = of_get_property(np, "device-id", NULL);
279 if (!iprop) {
280 pr_debug("fsl-pq-mdio: no UCC ID in node %pOF\n",
281 np);
282 continue;
283 }
284 }
285
286 id = be32_to_cpup(iprop);
287
288 /*
289 * cell-index and device-id for QE nodes are
290 * numbered from 1, not 0.
291 */
292 if (ucc_set_qe_mux_mii_mng(id - 1) < 0) {
293 pr_debug("fsl-pq-mdio: invalid UCC ID in node %pOF\n",
294 np);
295 continue;
296 }
297
298 pr_debug("fsl-pq-mdio: setting node UCC%u to MII master\n", id);
299 found_mii_master = true;
300 }
301}
302
303#endif
304
305static const struct of_device_id fsl_pq_mdio_match[] = {
306#if IS_ENABLED(CONFIG_GIANFAR)
307 {
308 .compatible = "fsl,gianfar-tbi",
309 .data = &(struct fsl_pq_mdio_data) {
310 .mii_offset = 0,
311 .get_tbipa = get_gfar_tbipa_from_mii,
312 },
313 },
314 {
315 .compatible = "fsl,gianfar-mdio",
316 .data = &(struct fsl_pq_mdio_data) {
317 .mii_offset = 0,
318 .get_tbipa = get_gfar_tbipa_from_mii,
319 },
320 },
321 {
322 .type = "mdio",
323 .compatible = "gianfar",
324 .data = &(struct fsl_pq_mdio_data) {
325 .mii_offset = offsetof(struct fsl_pq_mdio, mii),
326 .get_tbipa = get_gfar_tbipa_from_mdio,
327 },
328 },
329 {
330 .compatible = "fsl,etsec2-tbi",
331 .data = &(struct fsl_pq_mdio_data) {
332 .mii_offset = offsetof(struct fsl_pq_mdio, mii),
333 .get_tbipa = get_etsec_tbipa,
334 },
335 },
336 {
337 .compatible = "fsl,etsec2-mdio",
338 .data = &(struct fsl_pq_mdio_data) {
339 .mii_offset = offsetof(struct fsl_pq_mdio, mii),
340 .get_tbipa = get_etsec_tbipa,
341 },
342 },
343#endif
344#if IS_ENABLED(CONFIG_UCC_GETH)
345 {
346 .compatible = "fsl,ucc-mdio",
347 .data = &(struct fsl_pq_mdio_data) {
348 .mii_offset = 0,
349 .get_tbipa = get_ucc_tbipa,
350 .ucc_configure = ucc_configure,
351 },
352 },
353 {
354 /* Legacy UCC MDIO node */
355 .type = "mdio",
356 .compatible = "ucc_geth_phy",
357 .data = &(struct fsl_pq_mdio_data) {
358 .mii_offset = 0,
359 .get_tbipa = get_ucc_tbipa,
360 .ucc_configure = ucc_configure,
361 },
362 },
363#endif
364 /* No Kconfig option for Fman support yet */
365 {
366 .compatible = "fsl,fman-mdio",
367 .data = &(struct fsl_pq_mdio_data) {
368 .mii_offset = 0,
369 /* Fman TBI operations are handled elsewhere */
370 },
371 },
372
373 {},
374};
375MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);
376
377static void set_tbipa(const u32 tbipa_val, struct platform_device *pdev,
378 uint32_t __iomem * (*get_tbipa)(void __iomem *),
379 void __iomem *reg_map, struct resource *reg_res)
380{
381 struct device_node *np = pdev->dev.of_node;
382 uint32_t __iomem *tbipa;
383 bool tbipa_mapped;
384
385 tbipa = of_iomap(np, 1);
386 if (tbipa) {
387 tbipa_mapped = true;
388 } else {
389 tbipa_mapped = false;
390 tbipa = (*get_tbipa)(reg_map);
391
392 /*
393 * Add consistency check to make sure TBI is contained within
394 * the mapped range (not because we would get a segfault,
395 * rather to catch bugs in computing TBI address). Print error
396 * message but continue anyway.
397 */
398 if ((void *)tbipa > reg_map + resource_size(reg_res) - 4)
399 dev_err(&pdev->dev, "invalid register map (should be at least 0x%04zx to contain TBI address)\n",
400 ((void *)tbipa - reg_map) + 4);
401 }
402
403 iowrite32be(be32_to_cpu(tbipa_val), tbipa);
404
405 if (tbipa_mapped)
406 iounmap(tbipa);
407}
408
409static int fsl_pq_mdio_probe(struct platform_device *pdev)
410{
411 const struct fsl_pq_mdio_data *data;
412 struct device_node *np = pdev->dev.of_node;
413 struct resource res;
414 struct device_node *tbi;
415 struct fsl_pq_mdio_priv *priv;
416 struct mii_bus *new_bus;
417 int err;
418
419 data = device_get_match_data(&pdev->dev);
420 if (!data) {
421 dev_err(&pdev->dev, "Failed to match device\n");
422 return -ENODEV;
423 }
424
425 new_bus = mdiobus_alloc_size(sizeof(*priv));
426 if (!new_bus)
427 return -ENOMEM;
428
429 priv = new_bus->priv;
430 new_bus->name = "Freescale PowerQUICC MII Bus";
431 new_bus->read = &fsl_pq_mdio_read;
432 new_bus->write = &fsl_pq_mdio_write;
433 new_bus->reset = &fsl_pq_mdio_reset;
434
435 err = of_address_to_resource(np, 0, &res);
436 if (err < 0) {
437 dev_err(&pdev->dev, "could not obtain address information\n");
438 goto error;
439 }
440
441 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%pOFn@%llx", np,
442 (unsigned long long)res.start);
443
444 priv->map = of_iomap(np, 0);
445 if (!priv->map) {
446 err = -ENOMEM;
447 goto error;
448 }
449
450 /*
451 * Some device tree nodes represent only the MII registers, and
452 * others represent the MAC and MII registers. The 'mii_offset' field
453 * contains the offset of the MII registers inside the mapped register
454 * space.
455 */
456 if (data->mii_offset > resource_size(&res)) {
457 dev_err(&pdev->dev, "invalid register map\n");
458 err = -EINVAL;
459 goto error;
460 }
461 priv->regs = priv->map + data->mii_offset;
462
463 new_bus->parent = &pdev->dev;
464 platform_set_drvdata(pdev, new_bus);
465
466 if (data->get_tbipa) {
467 for_each_child_of_node(np, tbi) {
468 if (of_node_is_type(tbi, "tbi-phy")) {
469 dev_dbg(&pdev->dev, "found TBI PHY node %pOFP\n",
470 tbi);
471 break;
472 }
473 }
474
475 if (tbi) {
476 const u32 *prop = of_get_property(tbi, "reg", NULL);
477 if (!prop) {
478 dev_err(&pdev->dev,
479 "missing 'reg' property in node %pOF\n",
480 tbi);
481 err = -EBUSY;
482 goto error;
483 }
484 set_tbipa(*prop, pdev,
485 data->get_tbipa, priv->map, &res);
486 }
487 }
488
489 if (data->ucc_configure)
490 data->ucc_configure(res.start, res.end);
491
492 err = of_mdiobus_register(new_bus, np);
493 if (err) {
494 dev_err(&pdev->dev, "cannot register %s as MDIO bus\n",
495 new_bus->name);
496 goto error;
497 }
498
499 return 0;
500
501error:
502 if (priv->map)
503 iounmap(priv->map);
504
505 kfree(new_bus);
506
507 return err;
508}
509
510
511static void fsl_pq_mdio_remove(struct platform_device *pdev)
512{
513 struct device *device = &pdev->dev;
514 struct mii_bus *bus = dev_get_drvdata(device);
515 struct fsl_pq_mdio_priv *priv = bus->priv;
516
517 mdiobus_unregister(bus);
518
519 iounmap(priv->map);
520 mdiobus_free(bus);
521}
522
523static struct platform_driver fsl_pq_mdio_driver = {
524 .driver = {
525 .name = "fsl-pq_mdio",
526 .of_match_table = fsl_pq_mdio_match,
527 },
528 .probe = fsl_pq_mdio_probe,
529 .remove_new = fsl_pq_mdio_remove,
530};
531
532module_platform_driver(fsl_pq_mdio_driver);
533
534MODULE_DESCRIPTION("Freescale PQ MDIO helpers");
535MODULE_LICENSE("GPL");
1/*
2 * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
3 * Provides Bus interface for MIIM regs
4 *
5 * Author: Andy Fleming <afleming@freescale.com>
6 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
7 *
8 * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
9 *
10 * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
18
19#include <linux/kernel.h>
20#include <linux/string.h>
21#include <linux/errno.h>
22#include <linux/slab.h>
23#include <linux/delay.h>
24#include <linux/module.h>
25#include <linux/mii.h>
26#include <linux/of_address.h>
27#include <linux/of_mdio.h>
28#include <linux/of_device.h>
29
30#include <asm/io.h>
31#if IS_ENABLED(CONFIG_UCC_GETH)
32#include <soc/fsl/qe/ucc.h>
33#endif
34
35#include "gianfar.h"
36
37#define MIIMIND_BUSY 0x00000001
38#define MIIMIND_NOTVALID 0x00000004
39#define MIIMCFG_INIT_VALUE 0x00000007
40#define MIIMCFG_RESET 0x80000000
41
42#define MII_READ_COMMAND 0x00000001
43
44struct fsl_pq_mii {
45 u32 miimcfg; /* MII management configuration reg */
46 u32 miimcom; /* MII management command reg */
47 u32 miimadd; /* MII management address reg */
48 u32 miimcon; /* MII management control reg */
49 u32 miimstat; /* MII management status reg */
50 u32 miimind; /* MII management indication reg */
51};
52
53struct fsl_pq_mdio {
54 u8 res1[16];
55 u32 ieventm; /* MDIO Interrupt event register (for etsec2)*/
56 u32 imaskm; /* MDIO Interrupt mask register (for etsec2)*/
57 u8 res2[4];
58 u32 emapm; /* MDIO Event mapping register (for etsec2)*/
59 u8 res3[1280];
60 struct fsl_pq_mii mii;
61 u8 res4[28];
62 u32 utbipar; /* TBI phy address reg (only on UCC) */
63 u8 res5[2728];
64} __packed;
65
66/* Number of microseconds to wait for an MII register to respond */
67#define MII_TIMEOUT 1000
68
69struct fsl_pq_mdio_priv {
70 void __iomem *map;
71 struct fsl_pq_mii __iomem *regs;
72};
73
74/*
75 * Per-device-type data. Each type of device tree node that we support gets
76 * one of these.
77 *
78 * @mii_offset: the offset of the MII registers within the memory map of the
79 * node. Some nodes define only the MII registers, and some define the whole
80 * MAC (which includes the MII registers).
81 *
82 * @get_tbipa: determines the address of the TBIPA register
83 *
84 * @ucc_configure: a special function for extra QE configuration
85 */
86struct fsl_pq_mdio_data {
87 unsigned int mii_offset; /* offset of the MII registers */
88 uint32_t __iomem * (*get_tbipa)(void __iomem *p);
89 void (*ucc_configure)(phys_addr_t start, phys_addr_t end);
90};
91
92/*
93 * Write value to the PHY at mii_id at register regnum, on the bus attached
94 * to the local interface, which may be different from the generic mdio bus
95 * (tied to a single interface), waiting until the write is done before
96 * returning. This is helpful in programming interfaces like the TBI which
97 * control interfaces like onchip SERDES and are always tied to the local
98 * mdio pins, which may not be the same as system mdio bus, used for
99 * controlling the external PHYs, for example.
100 */
101static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
102 u16 value)
103{
104 struct fsl_pq_mdio_priv *priv = bus->priv;
105 struct fsl_pq_mii __iomem *regs = priv->regs;
106 unsigned int timeout;
107
108 /* Set the PHY address and the register address we want to write */
109 iowrite32be((mii_id << 8) | regnum, ®s->miimadd);
110
111 /* Write out the value we want */
112 iowrite32be(value, ®s->miimcon);
113
114 /* Wait for the transaction to finish */
115 timeout = MII_TIMEOUT;
116 while ((ioread32be(®s->miimind) & MIIMIND_BUSY) && timeout) {
117 cpu_relax();
118 timeout--;
119 }
120
121 return timeout ? 0 : -ETIMEDOUT;
122}
123
124/*
125 * Read the bus for PHY at addr mii_id, register regnum, and return the value.
126 * Clears miimcom first.
127 *
128 * All PHY operation done on the bus attached to the local interface, which
129 * may be different from the generic mdio bus. This is helpful in programming
130 * interfaces like the TBI which, in turn, control interfaces like on-chip
131 * SERDES and are always tied to the local mdio pins, which may not be the
132 * same as system mdio bus, used for controlling the external PHYs, for eg.
133 */
134static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
135{
136 struct fsl_pq_mdio_priv *priv = bus->priv;
137 struct fsl_pq_mii __iomem *regs = priv->regs;
138 unsigned int timeout;
139 u16 value;
140
141 /* Set the PHY address and the register address we want to read */
142 iowrite32be((mii_id << 8) | regnum, ®s->miimadd);
143
144 /* Clear miimcom, and then initiate a read */
145 iowrite32be(0, ®s->miimcom);
146 iowrite32be(MII_READ_COMMAND, ®s->miimcom);
147
148 /* Wait for the transaction to finish, normally less than 100us */
149 timeout = MII_TIMEOUT;
150 while ((ioread32be(®s->miimind) &
151 (MIIMIND_NOTVALID | MIIMIND_BUSY)) && timeout) {
152 cpu_relax();
153 timeout--;
154 }
155
156 if (!timeout)
157 return -ETIMEDOUT;
158
159 /* Grab the value of the register from miimstat */
160 value = ioread32be(®s->miimstat);
161
162 dev_dbg(&bus->dev, "read %04x from address %x/%x\n", value, mii_id, regnum);
163 return value;
164}
165
166/* Reset the MIIM registers, and wait for the bus to free */
167static int fsl_pq_mdio_reset(struct mii_bus *bus)
168{
169 struct fsl_pq_mdio_priv *priv = bus->priv;
170 struct fsl_pq_mii __iomem *regs = priv->regs;
171 unsigned int timeout;
172
173 mutex_lock(&bus->mdio_lock);
174
175 /* Reset the management interface */
176 iowrite32be(MIIMCFG_RESET, ®s->miimcfg);
177
178 /* Setup the MII Mgmt clock speed */
179 iowrite32be(MIIMCFG_INIT_VALUE, ®s->miimcfg);
180
181 /* Wait until the bus is free */
182 timeout = MII_TIMEOUT;
183 while ((ioread32be(®s->miimind) & MIIMIND_BUSY) && timeout) {
184 cpu_relax();
185 timeout--;
186 }
187
188 mutex_unlock(&bus->mdio_lock);
189
190 if (!timeout) {
191 dev_err(&bus->dev, "timeout waiting for MII bus\n");
192 return -EBUSY;
193 }
194
195 return 0;
196}
197
198#if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
199/*
200 * Return the TBIPA address, starting from the address
201 * of the mapped GFAR MDIO registers (struct gfar)
202 * This is mildly evil, but so is our hardware for doing this.
203 * Also, we have to cast back to struct gfar because of
204 * definition weirdness done in gianfar.h.
205 */
206static uint32_t __iomem *get_gfar_tbipa_from_mdio(void __iomem *p)
207{
208 struct gfar __iomem *enet_regs = p;
209
210 return &enet_regs->tbipa;
211}
212
213/*
214 * Return the TBIPA address, starting from the address
215 * of the mapped GFAR MII registers (gfar_mii_regs[] within struct gfar)
216 */
217static uint32_t __iomem *get_gfar_tbipa_from_mii(void __iomem *p)
218{
219 return get_gfar_tbipa_from_mdio(container_of(p, struct gfar, gfar_mii_regs));
220}
221
222/*
223 * Return the TBIPAR address for an eTSEC2 node
224 */
225static uint32_t __iomem *get_etsec_tbipa(void __iomem *p)
226{
227 return p;
228}
229#endif
230
231#if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
232/*
233 * Return the TBIPAR address for a QE MDIO node, starting from the address
234 * of the mapped MII registers (struct fsl_pq_mii)
235 */
236static uint32_t __iomem *get_ucc_tbipa(void __iomem *p)
237{
238 struct fsl_pq_mdio __iomem *mdio = container_of(p, struct fsl_pq_mdio, mii);
239
240 return &mdio->utbipar;
241}
242
243/*
244 * Find the UCC node that controls the given MDIO node
245 *
246 * For some reason, the QE MDIO nodes are not children of the UCC devices
247 * that control them. Therefore, we need to scan all UCC nodes looking for
248 * the one that encompases the given MDIO node. We do this by comparing
249 * physical addresses. The 'start' and 'end' addresses of the MDIO node are
250 * passed, and the correct UCC node will cover the entire address range.
251 *
252 * This assumes that there is only one QE MDIO node in the entire device tree.
253 */
254static void ucc_configure(phys_addr_t start, phys_addr_t end)
255{
256 static bool found_mii_master;
257 struct device_node *np = NULL;
258
259 if (found_mii_master)
260 return;
261
262 for_each_compatible_node(np, NULL, "ucc_geth") {
263 struct resource res;
264 const uint32_t *iprop;
265 uint32_t id;
266 int ret;
267
268 ret = of_address_to_resource(np, 0, &res);
269 if (ret < 0) {
270 pr_debug("fsl-pq-mdio: no address range in node %s\n",
271 np->full_name);
272 continue;
273 }
274
275 /* if our mdio regs fall within this UCC regs range */
276 if ((start < res.start) || (end > res.end))
277 continue;
278
279 iprop = of_get_property(np, "cell-index", NULL);
280 if (!iprop) {
281 iprop = of_get_property(np, "device-id", NULL);
282 if (!iprop) {
283 pr_debug("fsl-pq-mdio: no UCC ID in node %s\n",
284 np->full_name);
285 continue;
286 }
287 }
288
289 id = be32_to_cpup(iprop);
290
291 /*
292 * cell-index and device-id for QE nodes are
293 * numbered from 1, not 0.
294 */
295 if (ucc_set_qe_mux_mii_mng(id - 1) < 0) {
296 pr_debug("fsl-pq-mdio: invalid UCC ID in node %s\n",
297 np->full_name);
298 continue;
299 }
300
301 pr_debug("fsl-pq-mdio: setting node UCC%u to MII master\n", id);
302 found_mii_master = true;
303 }
304}
305
306#endif
307
308static const struct of_device_id fsl_pq_mdio_match[] = {
309#if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
310 {
311 .compatible = "fsl,gianfar-tbi",
312 .data = &(struct fsl_pq_mdio_data) {
313 .mii_offset = 0,
314 .get_tbipa = get_gfar_tbipa_from_mii,
315 },
316 },
317 {
318 .compatible = "fsl,gianfar-mdio",
319 .data = &(struct fsl_pq_mdio_data) {
320 .mii_offset = 0,
321 .get_tbipa = get_gfar_tbipa_from_mii,
322 },
323 },
324 {
325 .type = "mdio",
326 .compatible = "gianfar",
327 .data = &(struct fsl_pq_mdio_data) {
328 .mii_offset = offsetof(struct fsl_pq_mdio, mii),
329 .get_tbipa = get_gfar_tbipa_from_mdio,
330 },
331 },
332 {
333 .compatible = "fsl,etsec2-tbi",
334 .data = &(struct fsl_pq_mdio_data) {
335 .mii_offset = offsetof(struct fsl_pq_mdio, mii),
336 .get_tbipa = get_etsec_tbipa,
337 },
338 },
339 {
340 .compatible = "fsl,etsec2-mdio",
341 .data = &(struct fsl_pq_mdio_data) {
342 .mii_offset = offsetof(struct fsl_pq_mdio, mii),
343 .get_tbipa = get_etsec_tbipa,
344 },
345 },
346#endif
347#if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
348 {
349 .compatible = "fsl,ucc-mdio",
350 .data = &(struct fsl_pq_mdio_data) {
351 .mii_offset = 0,
352 .get_tbipa = get_ucc_tbipa,
353 .ucc_configure = ucc_configure,
354 },
355 },
356 {
357 /* Legacy UCC MDIO node */
358 .type = "mdio",
359 .compatible = "ucc_geth_phy",
360 .data = &(struct fsl_pq_mdio_data) {
361 .mii_offset = 0,
362 .get_tbipa = get_ucc_tbipa,
363 .ucc_configure = ucc_configure,
364 },
365 },
366#endif
367 /* No Kconfig option for Fman support yet */
368 {
369 .compatible = "fsl,fman-mdio",
370 .data = &(struct fsl_pq_mdio_data) {
371 .mii_offset = 0,
372 /* Fman TBI operations are handled elsewhere */
373 },
374 },
375
376 {},
377};
378MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);
379
380static int fsl_pq_mdio_probe(struct platform_device *pdev)
381{
382 const struct of_device_id *id =
383 of_match_device(fsl_pq_mdio_match, &pdev->dev);
384 const struct fsl_pq_mdio_data *data = id->data;
385 struct device_node *np = pdev->dev.of_node;
386 struct resource res;
387 struct device_node *tbi;
388 struct fsl_pq_mdio_priv *priv;
389 struct mii_bus *new_bus;
390 int err;
391
392 dev_dbg(&pdev->dev, "found %s compatible node\n", id->compatible);
393
394 new_bus = mdiobus_alloc_size(sizeof(*priv));
395 if (!new_bus)
396 return -ENOMEM;
397
398 priv = new_bus->priv;
399 new_bus->name = "Freescale PowerQUICC MII Bus",
400 new_bus->read = &fsl_pq_mdio_read;
401 new_bus->write = &fsl_pq_mdio_write;
402 new_bus->reset = &fsl_pq_mdio_reset;
403
404 err = of_address_to_resource(np, 0, &res);
405 if (err < 0) {
406 dev_err(&pdev->dev, "could not obtain address information\n");
407 goto error;
408 }
409
410 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s@%llx", np->name,
411 (unsigned long long)res.start);
412
413 priv->map = of_iomap(np, 0);
414 if (!priv->map) {
415 err = -ENOMEM;
416 goto error;
417 }
418
419 /*
420 * Some device tree nodes represent only the MII registers, and
421 * others represent the MAC and MII registers. The 'mii_offset' field
422 * contains the offset of the MII registers inside the mapped register
423 * space.
424 */
425 if (data->mii_offset > resource_size(&res)) {
426 dev_err(&pdev->dev, "invalid register map\n");
427 err = -EINVAL;
428 goto error;
429 }
430 priv->regs = priv->map + data->mii_offset;
431
432 new_bus->parent = &pdev->dev;
433 platform_set_drvdata(pdev, new_bus);
434
435 if (data->get_tbipa) {
436 for_each_child_of_node(np, tbi) {
437 if (strcmp(tbi->type, "tbi-phy") == 0) {
438 dev_dbg(&pdev->dev, "found TBI PHY node %s\n",
439 strrchr(tbi->full_name, '/') + 1);
440 break;
441 }
442 }
443
444 if (tbi) {
445 const u32 *prop = of_get_property(tbi, "reg", NULL);
446 uint32_t __iomem *tbipa;
447
448 if (!prop) {
449 dev_err(&pdev->dev,
450 "missing 'reg' property in node %s\n",
451 tbi->full_name);
452 err = -EBUSY;
453 goto error;
454 }
455
456 tbipa = data->get_tbipa(priv->map);
457
458 /*
459 * Add consistency check to make sure TBI is contained
460 * within the mapped range (not because we would get a
461 * segfault, rather to catch bugs in computing TBI
462 * address). Print error message but continue anyway.
463 */
464 if ((void *)tbipa > priv->map + resource_size(&res) - 4)
465 dev_err(&pdev->dev, "invalid register map (should be at least 0x%04zx to contain TBI address)\n",
466 ((void *)tbipa - priv->map) + 4);
467
468 iowrite32be(be32_to_cpup(prop), tbipa);
469 }
470 }
471
472 if (data->ucc_configure)
473 data->ucc_configure(res.start, res.end);
474
475 err = of_mdiobus_register(new_bus, np);
476 if (err) {
477 dev_err(&pdev->dev, "cannot register %s as MDIO bus\n",
478 new_bus->name);
479 goto error;
480 }
481
482 return 0;
483
484error:
485 if (priv->map)
486 iounmap(priv->map);
487
488 kfree(new_bus);
489
490 return err;
491}
492
493
494static int fsl_pq_mdio_remove(struct platform_device *pdev)
495{
496 struct device *device = &pdev->dev;
497 struct mii_bus *bus = dev_get_drvdata(device);
498 struct fsl_pq_mdio_priv *priv = bus->priv;
499
500 mdiobus_unregister(bus);
501
502 iounmap(priv->map);
503 mdiobus_free(bus);
504
505 return 0;
506}
507
508static struct platform_driver fsl_pq_mdio_driver = {
509 .driver = {
510 .name = "fsl-pq_mdio",
511 .of_match_table = fsl_pq_mdio_match,
512 },
513 .probe = fsl_pq_mdio_probe,
514 .remove = fsl_pq_mdio_remove,
515};
516
517module_platform_driver(fsl_pq_mdio_driver);
518
519MODULE_LICENSE("GPL");