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1// SPDX-License-Identifier: GPL-2.0-only
2/****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2012-2013 Solarflare Communications Inc.
5 */
6
7#include "net_driver.h"
8#include "rx_common.h"
9#include "tx_common.h"
10#include "ef10_regs.h"
11#include "io.h"
12#include "mcdi.h"
13#include "mcdi_pcol.h"
14#include "mcdi_port.h"
15#include "mcdi_port_common.h"
16#include "mcdi_functions.h"
17#include "nic.h"
18#include "mcdi_filters.h"
19#include "workarounds.h"
20#include "selftest.h"
21#include "ef10_sriov.h"
22#include <linux/in.h>
23#include <linux/jhash.h>
24#include <linux/wait.h>
25#include <linux/workqueue.h>
26#include <net/udp_tunnel.h>
27
28/* Hardware control for EF10 architecture including 'Huntington'. */
29
30#define EFX_EF10_DRVGEN_EV 7
31enum {
32 EFX_EF10_TEST = 1,
33 EFX_EF10_REFILL,
34};
35
36/* VLAN list entry */
37struct efx_ef10_vlan {
38 struct list_head list;
39 u16 vid;
40};
41
42static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading);
43static const struct udp_tunnel_nic_info efx_ef10_udp_tunnels;
44
45static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
46{
47 efx_dword_t reg;
48
49 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS);
50 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
51 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
52}
53
54/* On all EF10s up to and including SFC9220 (Medford1), all PFs use BAR 0 for
55 * I/O space and BAR 2(&3) for memory. On SFC9250 (Medford2), there is no I/O
56 * bar; PFs use BAR 0/1 for memory.
57 */
58static unsigned int efx_ef10_pf_mem_bar(struct efx_nic *efx)
59{
60 switch (efx->pci_dev->device) {
61 case 0x0b03: /* SFC9250 PF */
62 return 0;
63 default:
64 return 2;
65 }
66}
67
68/* All VFs use BAR 0/1 for memory */
69static unsigned int efx_ef10_vf_mem_bar(struct efx_nic *efx)
70{
71 return 0;
72}
73
74static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
75{
76 int bar;
77
78 bar = efx->type->mem_bar(efx);
79 return resource_size(&efx->pci_dev->resource[bar]);
80}
81
82static bool efx_ef10_is_vf(struct efx_nic *efx)
83{
84 return efx->type->is_vf;
85}
86
87#ifdef CONFIG_SFC_SRIOV
88static int efx_ef10_get_vf_index(struct efx_nic *efx)
89{
90 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
91 struct efx_ef10_nic_data *nic_data = efx->nic_data;
92 size_t outlen;
93 int rc;
94
95 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
96 sizeof(outbuf), &outlen);
97 if (rc)
98 return rc;
99 if (outlen < sizeof(outbuf))
100 return -EIO;
101
102 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
103 return 0;
104}
105#endif
106
107static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
108{
109 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V4_OUT_LEN);
110 struct efx_ef10_nic_data *nic_data = efx->nic_data;
111 size_t outlen;
112 int rc;
113
114 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
115
116 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
117 outbuf, sizeof(outbuf), &outlen);
118 if (rc)
119 return rc;
120 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
121 netif_err(efx, drv, efx->net_dev,
122 "unable to read datapath firmware capabilities\n");
123 return -EIO;
124 }
125
126 nic_data->datapath_caps =
127 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
128
129 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) {
130 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
131 GET_CAPABILITIES_V2_OUT_FLAGS2);
132 nic_data->piobuf_size = MCDI_WORD(outbuf,
133 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF);
134 } else {
135 nic_data->datapath_caps2 = 0;
136 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE;
137 }
138
139 /* record the DPCPU firmware IDs to determine VEB vswitching support.
140 */
141 nic_data->rx_dpcpu_fw_id =
142 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
143 nic_data->tx_dpcpu_fw_id =
144 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
145
146 if (!(nic_data->datapath_caps &
147 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
148 netif_err(efx, probe, efx->net_dev,
149 "current firmware does not support an RX prefix\n");
150 return -ENODEV;
151 }
152
153 if (outlen >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
154 u8 vi_window_mode = MCDI_BYTE(outbuf,
155 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
156
157 rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode);
158 if (rc)
159 return rc;
160 } else {
161 /* keep default VI stride */
162 netif_dbg(efx, probe, efx->net_dev,
163 "firmware did not report VI window mode, assuming vi_stride = %u\n",
164 efx->vi_stride);
165 }
166
167 if (outlen >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
168 efx->num_mac_stats = MCDI_WORD(outbuf,
169 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
170 netif_dbg(efx, probe, efx->net_dev,
171 "firmware reports num_mac_stats = %u\n",
172 efx->num_mac_stats);
173 } else {
174 /* leave num_mac_stats as the default value, MC_CMD_MAC_NSTATS */
175 netif_dbg(efx, probe, efx->net_dev,
176 "firmware did not report num_mac_stats, assuming %u\n",
177 efx->num_mac_stats);
178 }
179
180 return 0;
181}
182
183static void efx_ef10_read_licensed_features(struct efx_nic *efx)
184{
185 MCDI_DECLARE_BUF(inbuf, MC_CMD_LICENSING_V3_IN_LEN);
186 MCDI_DECLARE_BUF(outbuf, MC_CMD_LICENSING_V3_OUT_LEN);
187 struct efx_ef10_nic_data *nic_data = efx->nic_data;
188 size_t outlen;
189 int rc;
190
191 MCDI_SET_DWORD(inbuf, LICENSING_V3_IN_OP,
192 MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE);
193 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_LICENSING_V3, inbuf, sizeof(inbuf),
194 outbuf, sizeof(outbuf), &outlen);
195 if (rc || (outlen < MC_CMD_LICENSING_V3_OUT_LEN))
196 return;
197
198 nic_data->licensed_features = MCDI_QWORD(outbuf,
199 LICENSING_V3_OUT_LICENSED_FEATURES);
200}
201
202static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
203{
204 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
205 int rc;
206
207 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
208 outbuf, sizeof(outbuf), NULL);
209 if (rc)
210 return rc;
211 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
212 return rc > 0 ? rc : -ERANGE;
213}
214
215static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
216{
217 struct efx_ef10_nic_data *nic_data = efx->nic_data;
218 unsigned int implemented;
219 unsigned int enabled;
220 int rc;
221
222 nic_data->workaround_35388 = false;
223 nic_data->workaround_61265 = false;
224
225 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
226
227 if (rc == -ENOSYS) {
228 /* Firmware without GET_WORKAROUNDS - not a problem. */
229 rc = 0;
230 } else if (rc == 0) {
231 /* Bug61265 workaround is always enabled if implemented. */
232 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
233 nic_data->workaround_61265 = true;
234
235 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
236 nic_data->workaround_35388 = true;
237 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
238 /* Workaround is implemented but not enabled.
239 * Try to enable it.
240 */
241 rc = efx_mcdi_set_workaround(efx,
242 MC_CMD_WORKAROUND_BUG35388,
243 true, NULL);
244 if (rc == 0)
245 nic_data->workaround_35388 = true;
246 /* If we failed to set the workaround just carry on. */
247 rc = 0;
248 }
249 }
250
251 netif_dbg(efx, probe, efx->net_dev,
252 "workaround for bug 35388 is %sabled\n",
253 nic_data->workaround_35388 ? "en" : "dis");
254 netif_dbg(efx, probe, efx->net_dev,
255 "workaround for bug 61265 is %sabled\n",
256 nic_data->workaround_61265 ? "en" : "dis");
257
258 return rc;
259}
260
261static void efx_ef10_process_timer_config(struct efx_nic *efx,
262 const efx_dword_t *data)
263{
264 unsigned int max_count;
265
266 if (EFX_EF10_WORKAROUND_61265(efx)) {
267 efx->timer_quantum_ns = MCDI_DWORD(data,
268 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
269 efx->timer_max_ns = MCDI_DWORD(data,
270 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
271 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
272 efx->timer_quantum_ns = MCDI_DWORD(data,
273 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
274 max_count = MCDI_DWORD(data,
275 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
276 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
277 } else {
278 efx->timer_quantum_ns = MCDI_DWORD(data,
279 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
280 max_count = MCDI_DWORD(data,
281 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
282 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
283 }
284
285 netif_dbg(efx, probe, efx->net_dev,
286 "got timer properties from MC: quantum %u ns; max %u ns\n",
287 efx->timer_quantum_ns, efx->timer_max_ns);
288}
289
290static int efx_ef10_get_timer_config(struct efx_nic *efx)
291{
292 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
293 int rc;
294
295 rc = efx_ef10_get_timer_workarounds(efx);
296 if (rc)
297 return rc;
298
299 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
300 outbuf, sizeof(outbuf), NULL);
301
302 if (rc == 0) {
303 efx_ef10_process_timer_config(efx, outbuf);
304 } else if (rc == -ENOSYS || rc == -EPERM) {
305 /* Not available - fall back to Huntington defaults. */
306 unsigned int quantum;
307
308 rc = efx_ef10_get_sysclk_freq(efx);
309 if (rc < 0)
310 return rc;
311
312 quantum = 1536000 / rc; /* 1536 cycles */
313 efx->timer_quantum_ns = quantum;
314 efx->timer_max_ns = efx->type->timer_period_max * quantum;
315 rc = 0;
316 } else {
317 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
318 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
319 NULL, 0, rc);
320 }
321
322 return rc;
323}
324
325static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
326{
327 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
328 size_t outlen;
329 int rc;
330
331 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
332
333 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
334 outbuf, sizeof(outbuf), &outlen);
335 if (rc)
336 return rc;
337 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
338 return -EIO;
339
340 ether_addr_copy(mac_address,
341 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
342 return 0;
343}
344
345static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
346{
347 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
348 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
349 size_t outlen;
350 int num_addrs, rc;
351
352 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
353 EVB_PORT_ID_ASSIGNED);
354 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
355 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
356
357 if (rc)
358 return rc;
359 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
360 return -EIO;
361
362 num_addrs = MCDI_DWORD(outbuf,
363 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
364
365 WARN_ON(num_addrs != 1);
366
367 ether_addr_copy(mac_address,
368 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
369
370 return 0;
371}
372
373static ssize_t link_control_flag_show(struct device *dev,
374 struct device_attribute *attr,
375 char *buf)
376{
377 struct efx_nic *efx = dev_get_drvdata(dev);
378
379 return sprintf(buf, "%d\n",
380 ((efx->mcdi->fn_flags) &
381 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
382 ? 1 : 0);
383}
384
385static ssize_t primary_flag_show(struct device *dev,
386 struct device_attribute *attr,
387 char *buf)
388{
389 struct efx_nic *efx = dev_get_drvdata(dev);
390
391 return sprintf(buf, "%d\n",
392 ((efx->mcdi->fn_flags) &
393 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
394 ? 1 : 0);
395}
396
397static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
398{
399 struct efx_ef10_nic_data *nic_data = efx->nic_data;
400 struct efx_ef10_vlan *vlan;
401
402 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
403
404 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
405 if (vlan->vid == vid)
406 return vlan;
407 }
408
409 return NULL;
410}
411
412static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
413{
414 struct efx_ef10_nic_data *nic_data = efx->nic_data;
415 struct efx_ef10_vlan *vlan;
416 int rc;
417
418 mutex_lock(&nic_data->vlan_lock);
419
420 vlan = efx_ef10_find_vlan(efx, vid);
421 if (vlan) {
422 /* We add VID 0 on init. 8021q adds it on module init
423 * for all interfaces with VLAN filtring feature.
424 */
425 if (vid == 0)
426 goto done_unlock;
427 netif_warn(efx, drv, efx->net_dev,
428 "VLAN %u already added\n", vid);
429 rc = -EALREADY;
430 goto fail_exist;
431 }
432
433 rc = -ENOMEM;
434 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
435 if (!vlan)
436 goto fail_alloc;
437
438 vlan->vid = vid;
439
440 list_add_tail(&vlan->list, &nic_data->vlan_list);
441
442 if (efx->filter_state) {
443 mutex_lock(&efx->mac_lock);
444 down_write(&efx->filter_sem);
445 rc = efx_mcdi_filter_add_vlan(efx, vlan->vid);
446 up_write(&efx->filter_sem);
447 mutex_unlock(&efx->mac_lock);
448 if (rc)
449 goto fail_filter_add_vlan;
450 }
451
452done_unlock:
453 mutex_unlock(&nic_data->vlan_lock);
454 return 0;
455
456fail_filter_add_vlan:
457 list_del(&vlan->list);
458 kfree(vlan);
459fail_alloc:
460fail_exist:
461 mutex_unlock(&nic_data->vlan_lock);
462 return rc;
463}
464
465static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
466 struct efx_ef10_vlan *vlan)
467{
468 struct efx_ef10_nic_data *nic_data = efx->nic_data;
469
470 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
471
472 if (efx->filter_state) {
473 down_write(&efx->filter_sem);
474 efx_mcdi_filter_del_vlan(efx, vlan->vid);
475 up_write(&efx->filter_sem);
476 }
477
478 list_del(&vlan->list);
479 kfree(vlan);
480}
481
482static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
483{
484 struct efx_ef10_nic_data *nic_data = efx->nic_data;
485 struct efx_ef10_vlan *vlan;
486 int rc = 0;
487
488 /* 8021q removes VID 0 on module unload for all interfaces
489 * with VLAN filtering feature. We need to keep it to receive
490 * untagged traffic.
491 */
492 if (vid == 0)
493 return 0;
494
495 mutex_lock(&nic_data->vlan_lock);
496
497 vlan = efx_ef10_find_vlan(efx, vid);
498 if (!vlan) {
499 netif_err(efx, drv, efx->net_dev,
500 "VLAN %u to be deleted not found\n", vid);
501 rc = -ENOENT;
502 } else {
503 efx_ef10_del_vlan_internal(efx, vlan);
504 }
505
506 mutex_unlock(&nic_data->vlan_lock);
507
508 return rc;
509}
510
511static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
512{
513 struct efx_ef10_nic_data *nic_data = efx->nic_data;
514 struct efx_ef10_vlan *vlan, *next_vlan;
515
516 mutex_lock(&nic_data->vlan_lock);
517 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
518 efx_ef10_del_vlan_internal(efx, vlan);
519 mutex_unlock(&nic_data->vlan_lock);
520}
521
522static DEVICE_ATTR_RO(link_control_flag);
523static DEVICE_ATTR_RO(primary_flag);
524
525static int efx_ef10_probe(struct efx_nic *efx)
526{
527 struct efx_ef10_nic_data *nic_data;
528 int i, rc;
529
530 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
531 if (!nic_data)
532 return -ENOMEM;
533 efx->nic_data = nic_data;
534
535 /* we assume later that we can copy from this buffer in dwords */
536 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
537
538 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
539 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
540 if (rc)
541 goto fail1;
542
543 /* Get the MC's warm boot count. In case it's rebooting right
544 * now, be prepared to retry.
545 */
546 i = 0;
547 for (;;) {
548 rc = efx_ef10_get_warm_boot_count(efx);
549 if (rc >= 0)
550 break;
551 if (++i == 5)
552 goto fail2;
553 ssleep(1);
554 }
555 nic_data->warm_boot_count = rc;
556
557 /* In case we're recovering from a crash (kexec), we want to
558 * cancel any outstanding request by the previous user of this
559 * function. We send a special message using the least
560 * significant bits of the 'high' (doorbell) register.
561 */
562 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
563
564 rc = efx_mcdi_init(efx);
565 if (rc)
566 goto fail2;
567
568 mutex_init(&nic_data->udp_tunnels_lock);
569 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i)
570 nic_data->udp_tunnels[i].type =
571 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID;
572
573 /* Reset (most) configuration for this function */
574 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
575 if (rc)
576 goto fail3;
577
578 /* Enable event logging */
579 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
580 if (rc)
581 goto fail3;
582
583 rc = device_create_file(&efx->pci_dev->dev,
584 &dev_attr_link_control_flag);
585 if (rc)
586 goto fail3;
587
588 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
589 if (rc)
590 goto fail4;
591
592 rc = efx_get_pf_index(efx, &nic_data->pf_index);
593 if (rc)
594 goto fail5;
595
596 rc = efx_ef10_init_datapath_caps(efx);
597 if (rc < 0)
598 goto fail5;
599
600 efx_ef10_read_licensed_features(efx);
601
602 /* We can have one VI for each vi_stride-byte region.
603 * However, until we use TX option descriptors we need up to four
604 * TX queues per channel for different checksumming combinations.
605 */
606 if (nic_data->datapath_caps &
607 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
608 efx->tx_queues_per_channel = 4;
609 else
610 efx->tx_queues_per_channel = 2;
611 efx->max_vis = efx_ef10_mem_map_size(efx) / efx->vi_stride;
612 if (!efx->max_vis) {
613 netif_err(efx, drv, efx->net_dev, "error determining max VIs\n");
614 rc = -EIO;
615 goto fail5;
616 }
617 efx->max_channels = min_t(unsigned int, EFX_MAX_CHANNELS,
618 efx->max_vis / efx->tx_queues_per_channel);
619 efx->max_tx_channels = efx->max_channels;
620 if (WARN_ON(efx->max_channels == 0)) {
621 rc = -EIO;
622 goto fail5;
623 }
624
625 efx->rx_packet_len_offset =
626 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
627
628 if (nic_data->datapath_caps &
629 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN))
630 efx->net_dev->hw_features |= NETIF_F_RXFCS;
631
632 rc = efx_mcdi_port_get_number(efx);
633 if (rc < 0)
634 goto fail5;
635 efx->port_num = rc;
636
637 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
638 if (rc)
639 goto fail5;
640
641 rc = efx_ef10_get_timer_config(efx);
642 if (rc < 0)
643 goto fail5;
644
645 rc = efx_mcdi_mon_probe(efx);
646 if (rc && rc != -EPERM)
647 goto fail5;
648
649 efx_ptp_defer_probe_with_channel(efx);
650
651#ifdef CONFIG_SFC_SRIOV
652 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
653 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
654 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
655
656 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
657 } else
658#endif
659 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
660
661 INIT_LIST_HEAD(&nic_data->vlan_list);
662 mutex_init(&nic_data->vlan_lock);
663
664 /* Add unspecified VID to support VLAN filtering being disabled */
665 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
666 if (rc)
667 goto fail_add_vid_unspec;
668
669 /* If VLAN filtering is enabled, we need VID 0 to get untagged
670 * traffic. It is added automatically if 8021q module is loaded,
671 * but we can't rely on it since module may be not loaded.
672 */
673 rc = efx_ef10_add_vlan(efx, 0);
674 if (rc)
675 goto fail_add_vid_0;
676
677 if (nic_data->datapath_caps &
678 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) &&
679 efx->mcdi->fn_flags &
680 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED))
681 efx->net_dev->udp_tunnel_nic_info = &efx_ef10_udp_tunnels;
682
683 return 0;
684
685fail_add_vid_0:
686 efx_ef10_cleanup_vlans(efx);
687fail_add_vid_unspec:
688 mutex_destroy(&nic_data->vlan_lock);
689 efx_ptp_remove(efx);
690 efx_mcdi_mon_remove(efx);
691fail5:
692 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
693fail4:
694 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
695fail3:
696 efx_mcdi_detach(efx);
697
698 mutex_lock(&nic_data->udp_tunnels_lock);
699 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
700 (void)efx_ef10_set_udp_tnl_ports(efx, true);
701 mutex_unlock(&nic_data->udp_tunnels_lock);
702 mutex_destroy(&nic_data->udp_tunnels_lock);
703
704 efx_mcdi_fini(efx);
705fail2:
706 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
707fail1:
708 kfree(nic_data);
709 efx->nic_data = NULL;
710 return rc;
711}
712
713#ifdef EFX_USE_PIO
714
715static void efx_ef10_free_piobufs(struct efx_nic *efx)
716{
717 struct efx_ef10_nic_data *nic_data = efx->nic_data;
718 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
719 unsigned int i;
720 int rc;
721
722 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
723
724 for (i = 0; i < nic_data->n_piobufs; i++) {
725 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
726 nic_data->piobuf_handle[i]);
727 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
728 NULL, 0, NULL);
729 WARN_ON(rc);
730 }
731
732 nic_data->n_piobufs = 0;
733}
734
735static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
736{
737 struct efx_ef10_nic_data *nic_data = efx->nic_data;
738 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
739 unsigned int i;
740 size_t outlen;
741 int rc = 0;
742
743 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
744
745 for (i = 0; i < n; i++) {
746 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
747 outbuf, sizeof(outbuf), &outlen);
748 if (rc) {
749 /* Don't display the MC error if we didn't have space
750 * for a VF.
751 */
752 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
753 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
754 0, outbuf, outlen, rc);
755 break;
756 }
757 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
758 rc = -EIO;
759 break;
760 }
761 nic_data->piobuf_handle[i] =
762 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
763 netif_dbg(efx, probe, efx->net_dev,
764 "allocated PIO buffer %u handle %x\n", i,
765 nic_data->piobuf_handle[i]);
766 }
767
768 nic_data->n_piobufs = i;
769 if (rc)
770 efx_ef10_free_piobufs(efx);
771 return rc;
772}
773
774static int efx_ef10_link_piobufs(struct efx_nic *efx)
775{
776 struct efx_ef10_nic_data *nic_data = efx->nic_data;
777 MCDI_DECLARE_BUF(inbuf, MC_CMD_LINK_PIOBUF_IN_LEN);
778 struct efx_channel *channel;
779 struct efx_tx_queue *tx_queue;
780 unsigned int offset, index;
781 int rc;
782
783 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
784 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
785
786 /* Link a buffer to each VI in the write-combining mapping */
787 for (index = 0; index < nic_data->n_piobufs; ++index) {
788 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
789 nic_data->piobuf_handle[index]);
790 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
791 nic_data->pio_write_vi_base + index);
792 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
793 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
794 NULL, 0, NULL);
795 if (rc) {
796 netif_err(efx, drv, efx->net_dev,
797 "failed to link VI %u to PIO buffer %u (%d)\n",
798 nic_data->pio_write_vi_base + index, index,
799 rc);
800 goto fail;
801 }
802 netif_dbg(efx, probe, efx->net_dev,
803 "linked VI %u to PIO buffer %u\n",
804 nic_data->pio_write_vi_base + index, index);
805 }
806
807 /* Link a buffer to each TX queue */
808 efx_for_each_channel(channel, efx) {
809 /* Extra channels, even those with TXQs (PTP), do not require
810 * PIO resources.
811 */
812 if (!channel->type->want_pio ||
813 channel->channel >= efx->xdp_channel_offset)
814 continue;
815
816 efx_for_each_channel_tx_queue(tx_queue, channel) {
817 /* We assign the PIO buffers to queues in
818 * reverse order to allow for the following
819 * special case.
820 */
821 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
822 tx_queue->channel->channel - 1) *
823 efx_piobuf_size);
824 index = offset / nic_data->piobuf_size;
825 offset = offset % nic_data->piobuf_size;
826
827 /* When the host page size is 4K, the first
828 * host page in the WC mapping may be within
829 * the same VI page as the last TX queue. We
830 * can only link one buffer to each VI.
831 */
832 if (tx_queue->queue == nic_data->pio_write_vi_base) {
833 BUG_ON(index != 0);
834 rc = 0;
835 } else {
836 MCDI_SET_DWORD(inbuf,
837 LINK_PIOBUF_IN_PIOBUF_HANDLE,
838 nic_data->piobuf_handle[index]);
839 MCDI_SET_DWORD(inbuf,
840 LINK_PIOBUF_IN_TXQ_INSTANCE,
841 tx_queue->queue);
842 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
843 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
844 NULL, 0, NULL);
845 }
846
847 if (rc) {
848 /* This is non-fatal; the TX path just
849 * won't use PIO for this queue
850 */
851 netif_err(efx, drv, efx->net_dev,
852 "failed to link VI %u to PIO buffer %u (%d)\n",
853 tx_queue->queue, index, rc);
854 tx_queue->piobuf = NULL;
855 } else {
856 tx_queue->piobuf =
857 nic_data->pio_write_base +
858 index * efx->vi_stride + offset;
859 tx_queue->piobuf_offset = offset;
860 netif_dbg(efx, probe, efx->net_dev,
861 "linked VI %u to PIO buffer %u offset %x addr %p\n",
862 tx_queue->queue, index,
863 tx_queue->piobuf_offset,
864 tx_queue->piobuf);
865 }
866 }
867 }
868
869 return 0;
870
871fail:
872 /* inbuf was defined for MC_CMD_LINK_PIOBUF. We can use the same
873 * buffer for MC_CMD_UNLINK_PIOBUF because it's shorter.
874 */
875 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_IN_LEN < MC_CMD_UNLINK_PIOBUF_IN_LEN);
876 while (index--) {
877 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
878 nic_data->pio_write_vi_base + index);
879 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
880 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
881 NULL, 0, NULL);
882 }
883 return rc;
884}
885
886static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
887{
888 struct efx_channel *channel;
889 struct efx_tx_queue *tx_queue;
890
891 /* All our existing PIO buffers went away */
892 efx_for_each_channel(channel, efx)
893 efx_for_each_channel_tx_queue(tx_queue, channel)
894 tx_queue->piobuf = NULL;
895}
896
897#else /* !EFX_USE_PIO */
898
899static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
900{
901 return n == 0 ? 0 : -ENOBUFS;
902}
903
904static int efx_ef10_link_piobufs(struct efx_nic *efx)
905{
906 return 0;
907}
908
909static void efx_ef10_free_piobufs(struct efx_nic *efx)
910{
911}
912
913static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
914{
915}
916
917#endif /* EFX_USE_PIO */
918
919static void efx_ef10_remove(struct efx_nic *efx)
920{
921 struct efx_ef10_nic_data *nic_data = efx->nic_data;
922 int rc;
923
924#ifdef CONFIG_SFC_SRIOV
925 struct efx_ef10_nic_data *nic_data_pf;
926 struct pci_dev *pci_dev_pf;
927 struct efx_nic *efx_pf;
928 struct ef10_vf *vf;
929
930 if (efx->pci_dev->is_virtfn) {
931 pci_dev_pf = efx->pci_dev->physfn;
932 if (pci_dev_pf) {
933 efx_pf = pci_get_drvdata(pci_dev_pf);
934 nic_data_pf = efx_pf->nic_data;
935 vf = nic_data_pf->vf + nic_data->vf_index;
936 vf->efx = NULL;
937 } else
938 netif_info(efx, drv, efx->net_dev,
939 "Could not get the PF id from VF\n");
940 }
941#endif
942
943 efx_ef10_cleanup_vlans(efx);
944 mutex_destroy(&nic_data->vlan_lock);
945
946 efx_ptp_remove(efx);
947
948 efx_mcdi_mon_remove(efx);
949
950 efx_mcdi_rx_free_indir_table(efx);
951
952 if (nic_data->wc_membase)
953 iounmap(nic_data->wc_membase);
954
955 rc = efx_mcdi_free_vis(efx);
956 WARN_ON(rc != 0);
957
958 if (!nic_data->must_restore_piobufs)
959 efx_ef10_free_piobufs(efx);
960
961 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
962 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
963
964 efx_mcdi_detach(efx);
965
966 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
967 mutex_lock(&nic_data->udp_tunnels_lock);
968 (void)efx_ef10_set_udp_tnl_ports(efx, true);
969 mutex_unlock(&nic_data->udp_tunnels_lock);
970
971 mutex_destroy(&nic_data->udp_tunnels_lock);
972
973 efx_mcdi_fini(efx);
974 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
975 kfree(nic_data);
976}
977
978static int efx_ef10_probe_pf(struct efx_nic *efx)
979{
980 return efx_ef10_probe(efx);
981}
982
983int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
984 u32 *port_flags, u32 *vadaptor_flags,
985 unsigned int *vlan_tags)
986{
987 struct efx_ef10_nic_data *nic_data = efx->nic_data;
988 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
989 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
990 size_t outlen;
991 int rc;
992
993 if (nic_data->datapath_caps &
994 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
995 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
996 port_id);
997
998 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
999 outbuf, sizeof(outbuf), &outlen);
1000 if (rc)
1001 return rc;
1002
1003 if (outlen < sizeof(outbuf)) {
1004 rc = -EIO;
1005 return rc;
1006 }
1007 }
1008
1009 if (port_flags)
1010 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
1011 if (vadaptor_flags)
1012 *vadaptor_flags =
1013 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
1014 if (vlan_tags)
1015 *vlan_tags =
1016 MCDI_DWORD(outbuf,
1017 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
1018
1019 return 0;
1020}
1021
1022int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
1023{
1024 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
1025
1026 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
1027 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
1028 NULL, 0, NULL);
1029}
1030
1031int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
1032{
1033 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
1034
1035 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
1036 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
1037 NULL, 0, NULL);
1038}
1039
1040int efx_ef10_vport_add_mac(struct efx_nic *efx,
1041 unsigned int port_id, const u8 *mac)
1042{
1043 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
1044
1045 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
1046 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
1047
1048 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
1049 sizeof(inbuf), NULL, 0, NULL);
1050}
1051
1052int efx_ef10_vport_del_mac(struct efx_nic *efx,
1053 unsigned int port_id, const u8 *mac)
1054{
1055 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
1056
1057 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
1058 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
1059
1060 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
1061 sizeof(inbuf), NULL, 0, NULL);
1062}
1063
1064#ifdef CONFIG_SFC_SRIOV
1065static int efx_ef10_probe_vf(struct efx_nic *efx)
1066{
1067 int rc;
1068 struct pci_dev *pci_dev_pf;
1069
1070 /* If the parent PF has no VF data structure, it doesn't know about this
1071 * VF so fail probe. The VF needs to be re-created. This can happen
1072 * if the PF driver was unloaded while any VF was assigned to a guest
1073 * (using Xen, only).
1074 */
1075 pci_dev_pf = efx->pci_dev->physfn;
1076 if (pci_dev_pf) {
1077 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
1078 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
1079
1080 if (!nic_data_pf->vf) {
1081 netif_info(efx, drv, efx->net_dev,
1082 "The VF cannot link to its parent PF; "
1083 "please destroy and re-create the VF\n");
1084 return -EBUSY;
1085 }
1086 }
1087
1088 rc = efx_ef10_probe(efx);
1089 if (rc)
1090 return rc;
1091
1092 rc = efx_ef10_get_vf_index(efx);
1093 if (rc)
1094 goto fail;
1095
1096 if (efx->pci_dev->is_virtfn) {
1097 if (efx->pci_dev->physfn) {
1098 struct efx_nic *efx_pf =
1099 pci_get_drvdata(efx->pci_dev->physfn);
1100 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1101 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1102
1103 nic_data_p->vf[nic_data->vf_index].efx = efx;
1104 nic_data_p->vf[nic_data->vf_index].pci_dev =
1105 efx->pci_dev;
1106 } else
1107 netif_info(efx, drv, efx->net_dev,
1108 "Could not get the PF id from VF\n");
1109 }
1110
1111 return 0;
1112
1113fail:
1114 efx_ef10_remove(efx);
1115 return rc;
1116}
1117#else
1118static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1119{
1120 return 0;
1121}
1122#endif
1123
1124static int efx_ef10_alloc_vis(struct efx_nic *efx,
1125 unsigned int min_vis, unsigned int max_vis)
1126{
1127 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1128
1129 return efx_mcdi_alloc_vis(efx, min_vis, max_vis, &nic_data->vi_base,
1130 &nic_data->n_allocated_vis);
1131}
1132
1133/* Note that the failure path of this function does not free
1134 * resources, as this will be done by efx_ef10_remove().
1135 */
1136static int efx_ef10_dimension_resources(struct efx_nic *efx)
1137{
1138 unsigned int min_vis = max_t(unsigned int, efx->tx_queues_per_channel,
1139 efx_separate_tx_channels ? 2 : 1);
1140 unsigned int channel_vis, pio_write_vi_base, max_vis;
1141 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1142 unsigned int uc_mem_map_size, wc_mem_map_size;
1143 void __iomem *membase;
1144 int rc;
1145
1146 channel_vis = max(efx->n_channels,
1147 ((efx->n_tx_channels + efx->n_extra_tx_channels) *
1148 efx->tx_queues_per_channel) +
1149 efx->n_xdp_channels * efx->xdp_tx_per_channel);
1150 if (efx->max_vis && efx->max_vis < channel_vis) {
1151 netif_dbg(efx, drv, efx->net_dev,
1152 "Reducing channel VIs from %u to %u\n",
1153 channel_vis, efx->max_vis);
1154 channel_vis = efx->max_vis;
1155 }
1156
1157#ifdef EFX_USE_PIO
1158 /* Try to allocate PIO buffers if wanted and if the full
1159 * number of PIO buffers would be sufficient to allocate one
1160 * copy-buffer per TX channel. Failure is non-fatal, as there
1161 * are only a small number of PIO buffers shared between all
1162 * functions of the controller.
1163 */
1164 if (efx_piobuf_size != 0 &&
1165 nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
1166 efx->n_tx_channels) {
1167 unsigned int n_piobufs =
1168 DIV_ROUND_UP(efx->n_tx_channels,
1169 nic_data->piobuf_size / efx_piobuf_size);
1170
1171 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
1172 if (rc == -ENOSPC)
1173 netif_dbg(efx, probe, efx->net_dev,
1174 "out of PIO buffers; cannot allocate more\n");
1175 else if (rc == -EPERM)
1176 netif_dbg(efx, probe, efx->net_dev,
1177 "not permitted to allocate PIO buffers\n");
1178 else if (rc)
1179 netif_err(efx, probe, efx->net_dev,
1180 "failed to allocate PIO buffers (%d)\n", rc);
1181 else
1182 netif_dbg(efx, probe, efx->net_dev,
1183 "allocated %u PIO buffers\n", n_piobufs);
1184 }
1185#else
1186 nic_data->n_piobufs = 0;
1187#endif
1188
1189 /* PIO buffers should be mapped with write-combining enabled,
1190 * and we want to make single UC and WC mappings rather than
1191 * several of each (in fact that's the only option if host
1192 * page size is >4K). So we may allocate some extra VIs just
1193 * for writing PIO buffers through.
1194 *
1195 * The UC mapping contains (channel_vis - 1) complete VIs and the
1196 * first 4K of the next VI. Then the WC mapping begins with
1197 * the remainder of this last VI.
1198 */
1199 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * efx->vi_stride +
1200 ER_DZ_TX_PIOBUF);
1201 if (nic_data->n_piobufs) {
1202 /* pio_write_vi_base rounds down to give the number of complete
1203 * VIs inside the UC mapping.
1204 */
1205 pio_write_vi_base = uc_mem_map_size / efx->vi_stride;
1206 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1207 nic_data->n_piobufs) *
1208 efx->vi_stride) -
1209 uc_mem_map_size);
1210 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1211 } else {
1212 pio_write_vi_base = 0;
1213 wc_mem_map_size = 0;
1214 max_vis = channel_vis;
1215 }
1216
1217 /* In case the last attached driver failed to free VIs, do it now */
1218 rc = efx_mcdi_free_vis(efx);
1219 if (rc != 0)
1220 return rc;
1221
1222 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1223 if (rc != 0)
1224 return rc;
1225
1226 if (nic_data->n_allocated_vis < channel_vis) {
1227 netif_info(efx, drv, efx->net_dev,
1228 "Could not allocate enough VIs to satisfy RSS"
1229 " requirements. Performance may not be optimal.\n");
1230 /* We didn't get the VIs to populate our channels.
1231 * We could keep what we got but then we'd have more
1232 * interrupts than we need.
1233 * Instead calculate new max_channels and restart
1234 */
1235 efx->max_channels = nic_data->n_allocated_vis;
1236 efx->max_tx_channels =
1237 nic_data->n_allocated_vis / efx->tx_queues_per_channel;
1238
1239 efx_mcdi_free_vis(efx);
1240 return -EAGAIN;
1241 }
1242
1243 /* If we didn't get enough VIs to map all the PIO buffers, free the
1244 * PIO buffers
1245 */
1246 if (nic_data->n_piobufs &&
1247 nic_data->n_allocated_vis <
1248 pio_write_vi_base + nic_data->n_piobufs) {
1249 netif_dbg(efx, probe, efx->net_dev,
1250 "%u VIs are not sufficient to map %u PIO buffers\n",
1251 nic_data->n_allocated_vis, nic_data->n_piobufs);
1252 efx_ef10_free_piobufs(efx);
1253 }
1254
1255 /* Shrink the original UC mapping of the memory BAR */
1256 membase = ioremap(efx->membase_phys, uc_mem_map_size);
1257 if (!membase) {
1258 netif_err(efx, probe, efx->net_dev,
1259 "could not shrink memory BAR to %x\n",
1260 uc_mem_map_size);
1261 return -ENOMEM;
1262 }
1263 iounmap(efx->membase);
1264 efx->membase = membase;
1265
1266 /* Set up the WC mapping if needed */
1267 if (wc_mem_map_size) {
1268 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1269 uc_mem_map_size,
1270 wc_mem_map_size);
1271 if (!nic_data->wc_membase) {
1272 netif_err(efx, probe, efx->net_dev,
1273 "could not allocate WC mapping of size %x\n",
1274 wc_mem_map_size);
1275 return -ENOMEM;
1276 }
1277 nic_data->pio_write_vi_base = pio_write_vi_base;
1278 nic_data->pio_write_base =
1279 nic_data->wc_membase +
1280 (pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF -
1281 uc_mem_map_size);
1282
1283 rc = efx_ef10_link_piobufs(efx);
1284 if (rc)
1285 efx_ef10_free_piobufs(efx);
1286 }
1287
1288 netif_dbg(efx, probe, efx->net_dev,
1289 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1290 &efx->membase_phys, efx->membase, uc_mem_map_size,
1291 nic_data->wc_membase, wc_mem_map_size);
1292
1293 return 0;
1294}
1295
1296static void efx_ef10_fini_nic(struct efx_nic *efx)
1297{
1298 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1299
1300 spin_lock_bh(&efx->stats_lock);
1301 kfree(nic_data->mc_stats);
1302 nic_data->mc_stats = NULL;
1303 spin_unlock_bh(&efx->stats_lock);
1304}
1305
1306static int efx_ef10_init_nic(struct efx_nic *efx)
1307{
1308 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1309 struct net_device *net_dev = efx->net_dev;
1310 netdev_features_t tun_feats, tso_feats;
1311 int rc;
1312
1313 if (nic_data->must_check_datapath_caps) {
1314 rc = efx_ef10_init_datapath_caps(efx);
1315 if (rc)
1316 return rc;
1317 nic_data->must_check_datapath_caps = false;
1318 }
1319
1320 if (efx->must_realloc_vis) {
1321 /* We cannot let the number of VIs change now */
1322 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1323 nic_data->n_allocated_vis);
1324 if (rc)
1325 return rc;
1326 efx->must_realloc_vis = false;
1327 }
1328
1329 nic_data->mc_stats = kmalloc(efx->num_mac_stats * sizeof(__le64),
1330 GFP_KERNEL);
1331 if (!nic_data->mc_stats)
1332 return -ENOMEM;
1333
1334 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1335 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1336 if (rc == 0) {
1337 rc = efx_ef10_link_piobufs(efx);
1338 if (rc)
1339 efx_ef10_free_piobufs(efx);
1340 }
1341
1342 /* Log an error on failure, but this is non-fatal.
1343 * Permission errors are less important - we've presumably
1344 * had the PIO buffer licence removed.
1345 */
1346 if (rc == -EPERM)
1347 netif_dbg(efx, drv, efx->net_dev,
1348 "not permitted to restore PIO buffers\n");
1349 else if (rc)
1350 netif_err(efx, drv, efx->net_dev,
1351 "failed to restore PIO buffers (%d)\n", rc);
1352 nic_data->must_restore_piobufs = false;
1353 }
1354
1355 /* encap features might change during reset if fw variant changed */
1356 if (efx_has_cap(efx, VXLAN_NVGRE) && !efx_ef10_is_vf(efx))
1357 net_dev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1358 else
1359 net_dev->hw_enc_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
1360
1361 tun_feats = NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
1362 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM;
1363 tso_feats = NETIF_F_TSO | NETIF_F_TSO6;
1364
1365 if (efx_has_cap(efx, TX_TSO_V2_ENCAP)) {
1366 /* If this is first nic_init, or if it is a reset and a new fw
1367 * variant has added new features, enable them by default.
1368 * If the features are not new, maintain their current value.
1369 */
1370 if (!(net_dev->hw_features & tun_feats))
1371 net_dev->features |= tun_feats;
1372 net_dev->hw_enc_features |= tun_feats | tso_feats;
1373 net_dev->hw_features |= tun_feats;
1374 } else {
1375 net_dev->hw_enc_features &= ~(tun_feats | tso_feats);
1376 net_dev->hw_features &= ~tun_feats;
1377 net_dev->features &= ~tun_feats;
1378 }
1379
1380 /* don't fail init if RSS setup doesn't work */
1381 rc = efx->type->rx_push_rss_config(efx, false,
1382 efx->rss_context.rx_indir_table, NULL);
1383
1384 return 0;
1385}
1386
1387static void efx_ef10_table_reset_mc_allocations(struct efx_nic *efx)
1388{
1389 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1390#ifdef CONFIG_SFC_SRIOV
1391 unsigned int i;
1392#endif
1393
1394 /* All our allocations have been reset */
1395 efx->must_realloc_vis = true;
1396 efx_mcdi_filter_table_reset_mc_allocations(efx);
1397 nic_data->must_restore_piobufs = true;
1398 efx_ef10_forget_old_piobufs(efx);
1399 efx->rss_context.context_id = EFX_MCDI_RSS_CONTEXT_INVALID;
1400
1401 /* Driver-created vswitches and vports must be re-created */
1402 nic_data->must_probe_vswitching = true;
1403 efx->vport_id = EVB_PORT_ID_ASSIGNED;
1404#ifdef CONFIG_SFC_SRIOV
1405 if (nic_data->vf)
1406 for (i = 0; i < efx->vf_count; i++)
1407 nic_data->vf[i].vport_id = 0;
1408#endif
1409}
1410
1411static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1412{
1413 if (reason == RESET_TYPE_MC_FAILURE)
1414 return RESET_TYPE_DATAPATH;
1415
1416 return efx_mcdi_map_reset_reason(reason);
1417}
1418
1419static int efx_ef10_map_reset_flags(u32 *flags)
1420{
1421 enum {
1422 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1423 ETH_RESET_SHARED_SHIFT),
1424 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1425 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1426 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1427 ETH_RESET_SHARED_SHIFT)
1428 };
1429
1430 /* We assume for now that our PCI function is permitted to
1431 * reset everything.
1432 */
1433
1434 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1435 *flags &= ~EF10_RESET_MC;
1436 return RESET_TYPE_WORLD;
1437 }
1438
1439 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1440 *flags &= ~EF10_RESET_PORT;
1441 return RESET_TYPE_ALL;
1442 }
1443
1444 /* no invisible reset implemented */
1445
1446 return -EINVAL;
1447}
1448
1449static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1450{
1451 int rc = efx_mcdi_reset(efx, reset_type);
1452
1453 /* Unprivileged functions return -EPERM, but need to return success
1454 * here so that the datapath is brought back up.
1455 */
1456 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1457 rc = 0;
1458
1459 /* If it was a port reset, trigger reallocation of MC resources.
1460 * Note that on an MC reset nothing needs to be done now because we'll
1461 * detect the MC reset later and handle it then.
1462 * For an FLR, we never get an MC reset event, but the MC has reset all
1463 * resources assigned to us, so we have to trigger reallocation now.
1464 */
1465 if ((reset_type == RESET_TYPE_ALL ||
1466 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
1467 efx_ef10_table_reset_mc_allocations(efx);
1468 return rc;
1469}
1470
1471#define EF10_DMA_STAT(ext_name, mcdi_name) \
1472 [EF10_STAT_ ## ext_name] = \
1473 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1474#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1475 [EF10_STAT_ ## int_name] = \
1476 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1477#define EF10_OTHER_STAT(ext_name) \
1478 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1479
1480static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
1481 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1482 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1483 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1484 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1485 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1486 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1487 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1488 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1489 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1490 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1491 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1492 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1493 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1494 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1495 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1496 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1497 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1498 EF10_OTHER_STAT(port_rx_good_bytes),
1499 EF10_OTHER_STAT(port_rx_bad_bytes),
1500 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1501 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1502 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1503 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1504 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1505 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1506 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1507 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1508 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1509 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1510 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1511 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1512 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1513 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1514 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1515 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1516 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1517 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1518 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1519 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1520 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1521 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
1522 EFX_GENERIC_SW_STAT(rx_nodesc_trunc),
1523 EFX_GENERIC_SW_STAT(rx_noskb_drops),
1524 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1525 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1526 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1527 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1528 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1529 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1530 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1531 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1532 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1533 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1534 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1535 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
1536 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1537 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1538 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1539 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1540 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1541 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1542 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1543 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1544 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1545 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1546 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1547 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1548 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1549 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1550 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1551 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1552 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1553 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
1554 EF10_DMA_STAT(fec_uncorrected_errors, FEC_UNCORRECTED_ERRORS),
1555 EF10_DMA_STAT(fec_corrected_errors, FEC_CORRECTED_ERRORS),
1556 EF10_DMA_STAT(fec_corrected_symbols_lane0, FEC_CORRECTED_SYMBOLS_LANE0),
1557 EF10_DMA_STAT(fec_corrected_symbols_lane1, FEC_CORRECTED_SYMBOLS_LANE1),
1558 EF10_DMA_STAT(fec_corrected_symbols_lane2, FEC_CORRECTED_SYMBOLS_LANE2),
1559 EF10_DMA_STAT(fec_corrected_symbols_lane3, FEC_CORRECTED_SYMBOLS_LANE3),
1560 EF10_DMA_STAT(ctpio_vi_busy_fallback, CTPIO_VI_BUSY_FALLBACK),
1561 EF10_DMA_STAT(ctpio_long_write_success, CTPIO_LONG_WRITE_SUCCESS),
1562 EF10_DMA_STAT(ctpio_missing_dbell_fail, CTPIO_MISSING_DBELL_FAIL),
1563 EF10_DMA_STAT(ctpio_overflow_fail, CTPIO_OVERFLOW_FAIL),
1564 EF10_DMA_STAT(ctpio_underflow_fail, CTPIO_UNDERFLOW_FAIL),
1565 EF10_DMA_STAT(ctpio_timeout_fail, CTPIO_TIMEOUT_FAIL),
1566 EF10_DMA_STAT(ctpio_noncontig_wr_fail, CTPIO_NONCONTIG_WR_FAIL),
1567 EF10_DMA_STAT(ctpio_frm_clobber_fail, CTPIO_FRM_CLOBBER_FAIL),
1568 EF10_DMA_STAT(ctpio_invalid_wr_fail, CTPIO_INVALID_WR_FAIL),
1569 EF10_DMA_STAT(ctpio_vi_clobber_fallback, CTPIO_VI_CLOBBER_FALLBACK),
1570 EF10_DMA_STAT(ctpio_unqualified_fallback, CTPIO_UNQUALIFIED_FALLBACK),
1571 EF10_DMA_STAT(ctpio_runt_fallback, CTPIO_RUNT_FALLBACK),
1572 EF10_DMA_STAT(ctpio_success, CTPIO_SUCCESS),
1573 EF10_DMA_STAT(ctpio_fallback, CTPIO_FALLBACK),
1574 EF10_DMA_STAT(ctpio_poison, CTPIO_POISON),
1575 EF10_DMA_STAT(ctpio_erase, CTPIO_ERASE),
1576};
1577
1578#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1579 (1ULL << EF10_STAT_port_tx_packets) | \
1580 (1ULL << EF10_STAT_port_tx_pause) | \
1581 (1ULL << EF10_STAT_port_tx_unicast) | \
1582 (1ULL << EF10_STAT_port_tx_multicast) | \
1583 (1ULL << EF10_STAT_port_tx_broadcast) | \
1584 (1ULL << EF10_STAT_port_rx_bytes) | \
1585 (1ULL << \
1586 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1587 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1588 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1589 (1ULL << EF10_STAT_port_rx_packets) | \
1590 (1ULL << EF10_STAT_port_rx_good) | \
1591 (1ULL << EF10_STAT_port_rx_bad) | \
1592 (1ULL << EF10_STAT_port_rx_pause) | \
1593 (1ULL << EF10_STAT_port_rx_control) | \
1594 (1ULL << EF10_STAT_port_rx_unicast) | \
1595 (1ULL << EF10_STAT_port_rx_multicast) | \
1596 (1ULL << EF10_STAT_port_rx_broadcast) | \
1597 (1ULL << EF10_STAT_port_rx_lt64) | \
1598 (1ULL << EF10_STAT_port_rx_64) | \
1599 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1600 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1601 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1602 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1603 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1604 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1605 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1606 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1607 (1ULL << EF10_STAT_port_rx_overflow) | \
1608 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1609 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1610 (1ULL << GENERIC_STAT_rx_noskb_drops))
1611
1612/* On 7000 series NICs, these statistics are only provided by the 10G MAC.
1613 * For a 10G/40G switchable port we do not expose these because they might
1614 * not include all the packets they should.
1615 * On 8000 series NICs these statistics are always provided.
1616 */
1617#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1618 (1ULL << EF10_STAT_port_tx_lt64) | \
1619 (1ULL << EF10_STAT_port_tx_64) | \
1620 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1621 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1622 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1623 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1624 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1625 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1626
1627/* These statistics are only provided by the 40G MAC. For a 10G/40G
1628 * switchable port we do expose these because the errors will otherwise
1629 * be silent.
1630 */
1631#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1632 (1ULL << EF10_STAT_port_rx_length_error))
1633
1634/* These statistics are only provided if the firmware supports the
1635 * capability PM_AND_RXDP_COUNTERS.
1636 */
1637#define HUNT_PM_AND_RXDP_STAT_MASK ( \
1638 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1639 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1640 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1641 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1642 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1643 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1644 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1645 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1646 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1647 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1648 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1649 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1650
1651/* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V2,
1652 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V2 in
1653 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS.
1654 * These bits are in the second u64 of the raw mask.
1655 */
1656#define EF10_FEC_STAT_MASK ( \
1657 (1ULL << (EF10_STAT_fec_uncorrected_errors - 64)) | \
1658 (1ULL << (EF10_STAT_fec_corrected_errors - 64)) | \
1659 (1ULL << (EF10_STAT_fec_corrected_symbols_lane0 - 64)) | \
1660 (1ULL << (EF10_STAT_fec_corrected_symbols_lane1 - 64)) | \
1661 (1ULL << (EF10_STAT_fec_corrected_symbols_lane2 - 64)) | \
1662 (1ULL << (EF10_STAT_fec_corrected_symbols_lane3 - 64)))
1663
1664/* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V3,
1665 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V3 in
1666 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS.
1667 * These bits are in the second u64 of the raw mask.
1668 */
1669#define EF10_CTPIO_STAT_MASK ( \
1670 (1ULL << (EF10_STAT_ctpio_vi_busy_fallback - 64)) | \
1671 (1ULL << (EF10_STAT_ctpio_long_write_success - 64)) | \
1672 (1ULL << (EF10_STAT_ctpio_missing_dbell_fail - 64)) | \
1673 (1ULL << (EF10_STAT_ctpio_overflow_fail - 64)) | \
1674 (1ULL << (EF10_STAT_ctpio_underflow_fail - 64)) | \
1675 (1ULL << (EF10_STAT_ctpio_timeout_fail - 64)) | \
1676 (1ULL << (EF10_STAT_ctpio_noncontig_wr_fail - 64)) | \
1677 (1ULL << (EF10_STAT_ctpio_frm_clobber_fail - 64)) | \
1678 (1ULL << (EF10_STAT_ctpio_invalid_wr_fail - 64)) | \
1679 (1ULL << (EF10_STAT_ctpio_vi_clobber_fallback - 64)) | \
1680 (1ULL << (EF10_STAT_ctpio_unqualified_fallback - 64)) | \
1681 (1ULL << (EF10_STAT_ctpio_runt_fallback - 64)) | \
1682 (1ULL << (EF10_STAT_ctpio_success - 64)) | \
1683 (1ULL << (EF10_STAT_ctpio_fallback - 64)) | \
1684 (1ULL << (EF10_STAT_ctpio_poison - 64)) | \
1685 (1ULL << (EF10_STAT_ctpio_erase - 64)))
1686
1687static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1688{
1689 u64 raw_mask = HUNT_COMMON_STAT_MASK;
1690 u32 port_caps = efx_mcdi_phy_get_caps(efx);
1691 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1692
1693 if (!(efx->mcdi->fn_flags &
1694 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1695 return 0;
1696
1697 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
1698 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1699 /* 8000 series have everything even at 40G */
1700 if (nic_data->datapath_caps2 &
1701 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN))
1702 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1703 } else {
1704 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1705 }
1706
1707 if (nic_data->datapath_caps &
1708 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1709 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1710
1711 return raw_mask;
1712}
1713
1714static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1715{
1716 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1717 u64 raw_mask[2];
1718
1719 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1720
1721 /* Only show vadaptor stats when EVB capability is present */
1722 if (nic_data->datapath_caps &
1723 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1724 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1725 raw_mask[1] = (1ULL << (EF10_STAT_V1_COUNT - 64)) - 1;
1726 } else {
1727 raw_mask[1] = 0;
1728 }
1729 /* Only show FEC stats when NIC supports MC_CMD_MAC_STATS_V2 */
1730 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V2)
1731 raw_mask[1] |= EF10_FEC_STAT_MASK;
1732
1733 /* CTPIO stats appear in V3. Only show them on devices that actually
1734 * support CTPIO. Although this driver doesn't use CTPIO others might,
1735 * and we may be reporting the stats for the underlying port.
1736 */
1737 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V3 &&
1738 (nic_data->datapath_caps2 &
1739 (1 << MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN)))
1740 raw_mask[1] |= EF10_CTPIO_STAT_MASK;
1741
1742#if BITS_PER_LONG == 64
1743 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
1744 mask[0] = raw_mask[0];
1745 mask[1] = raw_mask[1];
1746#else
1747 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
1748 mask[0] = raw_mask[0] & 0xffffffff;
1749 mask[1] = raw_mask[0] >> 32;
1750 mask[2] = raw_mask[1] & 0xffffffff;
1751#endif
1752}
1753
1754static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1755{
1756 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1757
1758 efx_ef10_get_stat_mask(efx, mask);
1759 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1760 mask, names);
1761}
1762
1763static void efx_ef10_get_fec_stats(struct efx_nic *efx,
1764 struct ethtool_fec_stats *fec_stats)
1765{
1766 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1767 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1768 u64 *stats = nic_data->stats;
1769
1770 efx_ef10_get_stat_mask(efx, mask);
1771 if (test_bit(EF10_STAT_fec_corrected_errors, mask))
1772 fec_stats->corrected_blocks.total =
1773 stats[EF10_STAT_fec_corrected_errors];
1774 if (test_bit(EF10_STAT_fec_uncorrected_errors, mask))
1775 fec_stats->uncorrectable_blocks.total =
1776 stats[EF10_STAT_fec_uncorrected_errors];
1777}
1778
1779static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1780 struct rtnl_link_stats64 *core_stats)
1781{
1782 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1783 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1784 u64 *stats = nic_data->stats;
1785 size_t stats_count = 0, index;
1786
1787 efx_ef10_get_stat_mask(efx, mask);
1788
1789 if (full_stats) {
1790 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1791 if (efx_ef10_stat_desc[index].name) {
1792 *full_stats++ = stats[index];
1793 ++stats_count;
1794 }
1795 }
1796 }
1797
1798 if (!core_stats)
1799 return stats_count;
1800
1801 if (nic_data->datapath_caps &
1802 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1803 /* Use vadaptor stats. */
1804 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1805 stats[EF10_STAT_rx_multicast] +
1806 stats[EF10_STAT_rx_broadcast];
1807 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1808 stats[EF10_STAT_tx_multicast] +
1809 stats[EF10_STAT_tx_broadcast];
1810 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1811 stats[EF10_STAT_rx_multicast_bytes] +
1812 stats[EF10_STAT_rx_broadcast_bytes];
1813 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1814 stats[EF10_STAT_tx_multicast_bytes] +
1815 stats[EF10_STAT_tx_broadcast_bytes];
1816 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
1817 stats[GENERIC_STAT_rx_noskb_drops];
1818 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1819 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1820 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1821 core_stats->rx_errors = core_stats->rx_crc_errors;
1822 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
1823 } else {
1824 /* Use port stats. */
1825 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1826 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1827 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1828 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1829 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1830 stats[GENERIC_STAT_rx_nodesc_trunc] +
1831 stats[GENERIC_STAT_rx_noskb_drops];
1832 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1833 core_stats->rx_length_errors =
1834 stats[EF10_STAT_port_rx_gtjumbo] +
1835 stats[EF10_STAT_port_rx_length_error];
1836 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1837 core_stats->rx_frame_errors =
1838 stats[EF10_STAT_port_rx_align_error];
1839 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1840 core_stats->rx_errors = (core_stats->rx_length_errors +
1841 core_stats->rx_crc_errors +
1842 core_stats->rx_frame_errors);
1843 }
1844
1845 return stats_count;
1846}
1847
1848static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1849 struct rtnl_link_stats64 *core_stats)
1850{
1851 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1852 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1853 u64 *stats = nic_data->stats;
1854
1855 efx_ef10_get_stat_mask(efx, mask);
1856
1857 /* If NIC was fini'd (probably resetting), then we can't read
1858 * updated stats right now.
1859 */
1860 if (nic_data->mc_stats) {
1861 efx_nic_copy_stats(efx, nic_data->mc_stats);
1862 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1863 mask, stats, nic_data->mc_stats, false);
1864 }
1865
1866 /* Update derived statistics */
1867 efx_nic_fix_nodesc_drop_stat(efx,
1868 &stats[EF10_STAT_port_rx_nodesc_drops]);
1869 /* MC Firmware reads RX_BYTES and RX_GOOD_BYTES from the MAC.
1870 * It then calculates RX_BAD_BYTES and DMAs it to us with RX_BYTES.
1871 * We report these as port_rx_ stats. We are not given RX_GOOD_BYTES.
1872 * Here we calculate port_rx_good_bytes.
1873 */
1874 stats[EF10_STAT_port_rx_good_bytes] =
1875 stats[EF10_STAT_port_rx_bytes] -
1876 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1877
1878 /* The asynchronous reads used to calculate RX_BAD_BYTES in
1879 * MC Firmware are done such that we should not see an increase in
1880 * RX_BAD_BYTES when a good packet has arrived. Unfortunately this
1881 * does mean that the stat can decrease at times. Here we do not
1882 * update the stat unless it has increased or has gone to zero
1883 * (In the case of the NIC rebooting).
1884 * Please see Bug 33781 for a discussion of why things work this way.
1885 */
1886 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1887 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
1888 efx_update_sw_stats(efx, stats);
1889
1890 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1891}
1892
1893static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1894 __must_hold(&efx->stats_lock)
1895{
1896 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1897 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1898 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1899 __le64 generation_start, generation_end;
1900 u64 *stats = nic_data->stats;
1901 u32 dma_len = efx->num_mac_stats * sizeof(u64);
1902 struct efx_buffer stats_buf;
1903 __le64 *dma_stats;
1904 int rc;
1905
1906 spin_unlock_bh(&efx->stats_lock);
1907
1908 efx_ef10_get_stat_mask(efx, mask);
1909
1910 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_KERNEL);
1911 if (rc) {
1912 spin_lock_bh(&efx->stats_lock);
1913 return rc;
1914 }
1915
1916 dma_stats = stats_buf.addr;
1917 dma_stats[efx->num_mac_stats - 1] = EFX_MC_STATS_GENERATION_INVALID;
1918
1919 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1920 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
1921 MAC_STATS_IN_DMA, 1);
1922 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1923 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1924
1925 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1926 NULL, 0, NULL);
1927 spin_lock_bh(&efx->stats_lock);
1928 if (rc) {
1929 /* Expect ENOENT if DMA queues have not been set up */
1930 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1931 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1932 sizeof(inbuf), NULL, 0, rc);
1933 goto out;
1934 }
1935
1936 generation_end = dma_stats[efx->num_mac_stats - 1];
1937 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1938 WARN_ON_ONCE(1);
1939 goto out;
1940 }
1941 rmb();
1942 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1943 stats, stats_buf.addr, false);
1944 rmb();
1945 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1946 if (generation_end != generation_start) {
1947 rc = -EAGAIN;
1948 goto out;
1949 }
1950
1951 efx_update_sw_stats(efx, stats);
1952out:
1953 /* releasing a DMA coherent buffer with BH disabled can panic */
1954 spin_unlock_bh(&efx->stats_lock);
1955 efx_nic_free_buffer(efx, &stats_buf);
1956 spin_lock_bh(&efx->stats_lock);
1957 return rc;
1958}
1959
1960static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1961 struct rtnl_link_stats64 *core_stats)
1962{
1963 if (efx_ef10_try_update_nic_stats_vf(efx))
1964 return 0;
1965
1966 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1967}
1968
1969static size_t efx_ef10_update_stats_atomic_vf(struct efx_nic *efx, u64 *full_stats,
1970 struct rtnl_link_stats64 *core_stats)
1971{
1972 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1973
1974 /* In atomic context, cannot update HW stats. Just update the
1975 * software stats and return so the caller can continue.
1976 */
1977 efx_update_sw_stats(efx, nic_data->stats);
1978 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1979}
1980
1981static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1982{
1983 struct efx_nic *efx = channel->efx;
1984 unsigned int mode, usecs;
1985 efx_dword_t timer_cmd;
1986
1987 if (channel->irq_moderation_us) {
1988 mode = 3;
1989 usecs = channel->irq_moderation_us;
1990 } else {
1991 mode = 0;
1992 usecs = 0;
1993 }
1994
1995 if (EFX_EF10_WORKAROUND_61265(efx)) {
1996 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN);
1997 unsigned int ns = usecs * 1000;
1998
1999 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE,
2000 channel->channel);
2001 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns);
2002 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns);
2003 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode);
2004
2005 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR,
2006 inbuf, sizeof(inbuf), 0, NULL, 0);
2007 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
2008 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
2009
2010 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
2011 EFE_DD_EVQ_IND_TIMER_FLAGS,
2012 ERF_DD_EVQ_IND_TIMER_MODE, mode,
2013 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
2014 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
2015 channel->channel);
2016 } else {
2017 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
2018
2019 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
2020 ERF_DZ_TC_TIMER_VAL, ticks,
2021 ERF_FZ_TC_TMR_REL_VAL, ticks);
2022 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
2023 channel->channel);
2024 }
2025}
2026
2027static void efx_ef10_get_wol_vf(struct efx_nic *efx,
2028 struct ethtool_wolinfo *wol) {}
2029
2030static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
2031{
2032 return -EOPNOTSUPP;
2033}
2034
2035static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
2036{
2037 wol->supported = 0;
2038 wol->wolopts = 0;
2039 memset(&wol->sopass, 0, sizeof(wol->sopass));
2040}
2041
2042static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
2043{
2044 if (type != 0)
2045 return -EINVAL;
2046 return 0;
2047}
2048
2049static void efx_ef10_mcdi_request(struct efx_nic *efx,
2050 const efx_dword_t *hdr, size_t hdr_len,
2051 const efx_dword_t *sdu, size_t sdu_len)
2052{
2053 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2054 u8 *pdu = nic_data->mcdi_buf.addr;
2055
2056 memcpy(pdu, hdr, hdr_len);
2057 memcpy(pdu + hdr_len, sdu, sdu_len);
2058 wmb();
2059
2060 /* The hardware provides 'low' and 'high' (doorbell) registers
2061 * for passing the 64-bit address of an MCDI request to
2062 * firmware. However the dwords are swapped by firmware. The
2063 * least significant bits of the doorbell are then 0 for all
2064 * MCDI requests due to alignment.
2065 */
2066 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
2067 ER_DZ_MC_DB_LWRD);
2068 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
2069 ER_DZ_MC_DB_HWRD);
2070}
2071
2072static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
2073{
2074 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2075 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
2076
2077 rmb();
2078 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
2079}
2080
2081static void
2082efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
2083 size_t offset, size_t outlen)
2084{
2085 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2086 const u8 *pdu = nic_data->mcdi_buf.addr;
2087
2088 memcpy(outbuf, pdu + offset, outlen);
2089}
2090
2091static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
2092{
2093 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2094
2095 /* All our allocations have been reset */
2096 efx_ef10_table_reset_mc_allocations(efx);
2097
2098 /* The datapath firmware might have been changed */
2099 nic_data->must_check_datapath_caps = true;
2100
2101 /* MAC statistics have been cleared on the NIC; clear the local
2102 * statistic that we update with efx_update_diff_stat().
2103 */
2104 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
2105}
2106
2107static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
2108{
2109 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2110 int rc;
2111
2112 rc = efx_ef10_get_warm_boot_count(efx);
2113 if (rc < 0) {
2114 /* The firmware is presumably in the process of
2115 * rebooting. However, we are supposed to report each
2116 * reboot just once, so we must only do that once we
2117 * can read and store the updated warm boot count.
2118 */
2119 return 0;
2120 }
2121
2122 if (rc == nic_data->warm_boot_count)
2123 return 0;
2124
2125 nic_data->warm_boot_count = rc;
2126 efx_ef10_mcdi_reboot_detected(efx);
2127
2128 return -EIO;
2129}
2130
2131/* Handle an MSI interrupt
2132 *
2133 * Handle an MSI hardware interrupt. This routine schedules event
2134 * queue processing. No interrupt acknowledgement cycle is necessary.
2135 * Also, we never need to check that the interrupt is for us, since
2136 * MSI interrupts cannot be shared.
2137 */
2138static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
2139{
2140 struct efx_msi_context *context = dev_id;
2141 struct efx_nic *efx = context->efx;
2142
2143 netif_vdbg(efx, intr, efx->net_dev,
2144 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
2145
2146 if (likely(READ_ONCE(efx->irq_soft_enabled))) {
2147 /* Note test interrupts */
2148 if (context->index == efx->irq_level)
2149 efx->last_irq_cpu = raw_smp_processor_id();
2150
2151 /* Schedule processing of the channel */
2152 efx_schedule_channel_irq(efx->channel[context->index]);
2153 }
2154
2155 return IRQ_HANDLED;
2156}
2157
2158static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
2159{
2160 struct efx_nic *efx = dev_id;
2161 bool soft_enabled = READ_ONCE(efx->irq_soft_enabled);
2162 struct efx_channel *channel;
2163 efx_dword_t reg;
2164 u32 queues;
2165
2166 /* Read the ISR which also ACKs the interrupts */
2167 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR);
2168 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
2169
2170 if (queues == 0)
2171 return IRQ_NONE;
2172
2173 if (likely(soft_enabled)) {
2174 /* Note test interrupts */
2175 if (queues & (1U << efx->irq_level))
2176 efx->last_irq_cpu = raw_smp_processor_id();
2177
2178 efx_for_each_channel(channel, efx) {
2179 if (queues & 1)
2180 efx_schedule_channel_irq(channel);
2181 queues >>= 1;
2182 }
2183 }
2184
2185 netif_vdbg(efx, intr, efx->net_dev,
2186 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
2187 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
2188
2189 return IRQ_HANDLED;
2190}
2191
2192static int efx_ef10_irq_test_generate(struct efx_nic *efx)
2193{
2194 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
2195
2196 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true,
2197 NULL) == 0)
2198 return -ENOTSUPP;
2199
2200 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
2201
2202 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
2203 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
2204 inbuf, sizeof(inbuf), NULL, 0, NULL);
2205}
2206
2207static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
2208{
2209 /* low two bits of label are what we want for type */
2210 BUILD_BUG_ON((EFX_TXQ_TYPE_OUTER_CSUM | EFX_TXQ_TYPE_INNER_CSUM) != 3);
2211 tx_queue->type = tx_queue->label & 3;
2212 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd,
2213 (tx_queue->ptr_mask + 1) *
2214 sizeof(efx_qword_t),
2215 GFP_KERNEL);
2216}
2217
2218/* This writes to the TX_DESC_WPTR and also pushes data */
2219static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
2220 const efx_qword_t *txd)
2221{
2222 unsigned int write_ptr;
2223 efx_oword_t reg;
2224
2225 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2226 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
2227 reg.qword[0] = *txd;
2228 efx_writeo_page(tx_queue->efx, ®,
2229 ER_DZ_TX_DESC_UPD, tx_queue->queue);
2230}
2231
2232/* Add Firmware-Assisted TSO v2 option descriptors to a queue.
2233 */
2234int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, struct sk_buff *skb,
2235 bool *data_mapped)
2236{
2237 struct efx_tx_buffer *buffer;
2238 u16 inner_ipv4_id = 0;
2239 u16 outer_ipv4_id = 0;
2240 struct tcphdr *tcp;
2241 struct iphdr *ip;
2242 u16 ip_tot_len;
2243 u32 seqnum;
2244 u32 mss;
2245
2246 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2);
2247
2248 mss = skb_shinfo(skb)->gso_size;
2249
2250 if (unlikely(mss < 4)) {
2251 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss);
2252 return -EINVAL;
2253 }
2254
2255 if (skb->encapsulation) {
2256 if (!tx_queue->tso_encap)
2257 return -EINVAL;
2258 ip = ip_hdr(skb);
2259 if (ip->version == 4)
2260 outer_ipv4_id = ntohs(ip->id);
2261
2262 ip = inner_ip_hdr(skb);
2263 tcp = inner_tcp_hdr(skb);
2264 } else {
2265 ip = ip_hdr(skb);
2266 tcp = tcp_hdr(skb);
2267 }
2268
2269 /* 8000-series EF10 hardware requires that IP Total Length be
2270 * greater than or equal to the value it will have in each segment
2271 * (which is at most mss + 208 + TCP header length), but also less
2272 * than (0x10000 - inner_network_header). Otherwise the TCP
2273 * checksum calculation will be broken for encapsulated packets.
2274 * We fill in ip->tot_len with 0xff30, which should satisfy the
2275 * first requirement unless the MSS is ridiculously large (which
2276 * should be impossible as the driver max MTU is 9216); it is
2277 * guaranteed to satisfy the second as we only attempt TSO if
2278 * inner_network_header <= 208.
2279 */
2280 ip_tot_len = 0x10000 - EFX_TSO2_MAX_HDRLEN;
2281 EFX_WARN_ON_ONCE_PARANOID(mss + EFX_TSO2_MAX_HDRLEN +
2282 (tcp->doff << 2u) > ip_tot_len);
2283
2284 if (ip->version == 4) {
2285 ip->tot_len = htons(ip_tot_len);
2286 ip->check = 0;
2287 inner_ipv4_id = ntohs(ip->id);
2288 } else {
2289 ((struct ipv6hdr *)ip)->payload_len = htons(ip_tot_len);
2290 }
2291
2292 seqnum = ntohl(tcp->seq);
2293
2294 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2295
2296 buffer->flags = EFX_TX_BUF_OPTION;
2297 buffer->len = 0;
2298 buffer->unmap_len = 0;
2299 EFX_POPULATE_QWORD_5(buffer->option,
2300 ESF_DZ_TX_DESC_IS_OPT, 1,
2301 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2302 ESF_DZ_TX_TSO_OPTION_TYPE,
2303 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
2304 ESF_DZ_TX_TSO_IP_ID, inner_ipv4_id,
2305 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum
2306 );
2307 ++tx_queue->insert_count;
2308
2309 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2310
2311 buffer->flags = EFX_TX_BUF_OPTION;
2312 buffer->len = 0;
2313 buffer->unmap_len = 0;
2314 EFX_POPULATE_QWORD_5(buffer->option,
2315 ESF_DZ_TX_DESC_IS_OPT, 1,
2316 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2317 ESF_DZ_TX_TSO_OPTION_TYPE,
2318 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
2319 ESF_DZ_TX_TSO_OUTER_IPID, outer_ipv4_id,
2320 ESF_DZ_TX_TSO_TCP_MSS, mss
2321 );
2322 ++tx_queue->insert_count;
2323
2324 return 0;
2325}
2326
2327static u32 efx_ef10_tso_versions(struct efx_nic *efx)
2328{
2329 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2330 u32 tso_versions = 0;
2331
2332 if (nic_data->datapath_caps &
2333 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))
2334 tso_versions |= BIT(1);
2335 if (nic_data->datapath_caps2 &
2336 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))
2337 tso_versions |= BIT(2);
2338 return tso_versions;
2339}
2340
2341static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
2342{
2343 bool csum_offload = tx_queue->type & EFX_TXQ_TYPE_OUTER_CSUM;
2344 bool inner_csum = tx_queue->type & EFX_TXQ_TYPE_INNER_CSUM;
2345 struct efx_channel *channel = tx_queue->channel;
2346 struct efx_nic *efx = tx_queue->efx;
2347 struct efx_ef10_nic_data *nic_data;
2348 efx_qword_t *txd;
2349 int rc;
2350
2351 nic_data = efx->nic_data;
2352
2353 /* Only attempt to enable TX timestamping if we have the license for it,
2354 * otherwise TXQ init will fail
2355 */
2356 if (!(nic_data->licensed_features &
2357 (1 << LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN))) {
2358 tx_queue->timestamping = false;
2359 /* Disable sync events on this channel. */
2360 if (efx->type->ptp_set_ts_sync_events)
2361 efx->type->ptp_set_ts_sync_events(efx, false, false);
2362 }
2363
2364 /* TSOv2 is a limited resource that can only be configured on a limited
2365 * number of queues. TSO without checksum offload is not really a thing,
2366 * so we only enable it for those queues.
2367 * TSOv2 cannot be used with Hardware timestamping, and is never needed
2368 * for XDP tx.
2369 */
2370 if (efx_has_cap(efx, TX_TSO_V2)) {
2371 if ((csum_offload || inner_csum) &&
2372 !tx_queue->timestamping && !tx_queue->xdp_tx) {
2373 tx_queue->tso_version = 2;
2374 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n",
2375 channel->channel);
2376 }
2377 } else if (efx_has_cap(efx, TX_TSO)) {
2378 tx_queue->tso_version = 1;
2379 }
2380
2381 rc = efx_mcdi_tx_init(tx_queue);
2382 if (rc)
2383 goto fail;
2384
2385 /* A previous user of this TX queue might have set us up the
2386 * bomb by writing a descriptor to the TX push collector but
2387 * not the doorbell. (Each collector belongs to a port, not a
2388 * queue or function, so cannot easily be reset.) We must
2389 * attempt to push a no-op descriptor in its place.
2390 */
2391 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2392 tx_queue->insert_count = 1;
2393 txd = efx_tx_desc(tx_queue, 0);
2394 EFX_POPULATE_QWORD_7(*txd,
2395 ESF_DZ_TX_DESC_IS_OPT, true,
2396 ESF_DZ_TX_OPTION_TYPE,
2397 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2398 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2399 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload && tx_queue->tso_version != 2,
2400 ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM, inner_csum,
2401 ESF_DZ_TX_OPTION_INNER_IP_CSUM, inner_csum && tx_queue->tso_version != 2,
2402 ESF_DZ_TX_TIMESTAMP, tx_queue->timestamping);
2403 tx_queue->write_count = 1;
2404
2405 if (tx_queue->tso_version == 2 && efx_has_cap(efx, TX_TSO_V2_ENCAP))
2406 tx_queue->tso_encap = true;
2407
2408 wmb();
2409 efx_ef10_push_tx_desc(tx_queue, txd);
2410
2411 return;
2412
2413fail:
2414 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2415 tx_queue->queue);
2416}
2417
2418/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2419static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2420{
2421 unsigned int write_ptr;
2422 efx_dword_t reg;
2423
2424 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2425 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2426 efx_writed_page(tx_queue->efx, ®,
2427 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2428}
2429
2430#define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff
2431
2432static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue,
2433 dma_addr_t dma_addr, unsigned int len)
2434{
2435 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) {
2436 /* If we need to break across multiple descriptors we should
2437 * stop at a page boundary. This assumes the length limit is
2438 * greater than the page size.
2439 */
2440 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN;
2441
2442 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE);
2443 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr;
2444 }
2445
2446 return len;
2447}
2448
2449static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2450{
2451 unsigned int old_write_count = tx_queue->write_count;
2452 struct efx_tx_buffer *buffer;
2453 unsigned int write_ptr;
2454 efx_qword_t *txd;
2455
2456 tx_queue->xmit_pending = false;
2457 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2458 return;
2459
2460 do {
2461 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2462 buffer = &tx_queue->buffer[write_ptr];
2463 txd = efx_tx_desc(tx_queue, write_ptr);
2464 ++tx_queue->write_count;
2465
2466 /* Create TX descriptor ring entry */
2467 if (buffer->flags & EFX_TX_BUF_OPTION) {
2468 *txd = buffer->option;
2469 if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1)
2470 /* PIO descriptor */
2471 tx_queue->packet_write_count = tx_queue->write_count;
2472 } else {
2473 tx_queue->packet_write_count = tx_queue->write_count;
2474 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2475 EFX_POPULATE_QWORD_3(
2476 *txd,
2477 ESF_DZ_TX_KER_CONT,
2478 buffer->flags & EFX_TX_BUF_CONT,
2479 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2480 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2481 }
2482 } while (tx_queue->write_count != tx_queue->insert_count);
2483
2484 wmb(); /* Ensure descriptors are written before they are fetched */
2485
2486 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2487 txd = efx_tx_desc(tx_queue,
2488 old_write_count & tx_queue->ptr_mask);
2489 efx_ef10_push_tx_desc(tx_queue, txd);
2490 ++tx_queue->pushes;
2491 } else {
2492 efx_ef10_notify_tx_desc(tx_queue);
2493 }
2494}
2495
2496static int efx_ef10_probe_multicast_chaining(struct efx_nic *efx)
2497{
2498 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2499 unsigned int enabled, implemented;
2500 bool want_workaround_26807;
2501 int rc;
2502
2503 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
2504 if (rc == -ENOSYS) {
2505 /* GET_WORKAROUNDS was implemented before this workaround,
2506 * thus it must be unavailable in this firmware.
2507 */
2508 nic_data->workaround_26807 = false;
2509 return 0;
2510 }
2511 if (rc)
2512 return rc;
2513 want_workaround_26807 =
2514 implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807;
2515 nic_data->workaround_26807 =
2516 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
2517
2518 if (want_workaround_26807 && !nic_data->workaround_26807) {
2519 unsigned int flags;
2520
2521 rc = efx_mcdi_set_workaround(efx,
2522 MC_CMD_WORKAROUND_BUG26807,
2523 true, &flags);
2524 if (!rc) {
2525 if (flags &
2526 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
2527 netif_info(efx, drv, efx->net_dev,
2528 "other functions on NIC have been reset\n");
2529
2530 /* With MCFW v4.6.x and earlier, the
2531 * boot count will have incremented,
2532 * so re-read the warm_boot_count
2533 * value now to ensure this function
2534 * doesn't think it has changed next
2535 * time it checks.
2536 */
2537 rc = efx_ef10_get_warm_boot_count(efx);
2538 if (rc >= 0) {
2539 nic_data->warm_boot_count = rc;
2540 rc = 0;
2541 }
2542 }
2543 nic_data->workaround_26807 = true;
2544 } else if (rc == -EPERM) {
2545 rc = 0;
2546 }
2547 }
2548 return rc;
2549}
2550
2551static int efx_ef10_filter_table_probe(struct efx_nic *efx)
2552{
2553 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2554 int rc = efx_ef10_probe_multicast_chaining(efx);
2555 struct efx_mcdi_filter_vlan *vlan;
2556
2557 if (rc)
2558 return rc;
2559 down_write(&efx->filter_sem);
2560 rc = efx_mcdi_filter_table_probe(efx, nic_data->workaround_26807);
2561
2562 if (rc)
2563 goto out_unlock;
2564
2565 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
2566 rc = efx_mcdi_filter_add_vlan(efx, vlan->vid);
2567 if (rc)
2568 goto fail_add_vlan;
2569 }
2570 goto out_unlock;
2571
2572fail_add_vlan:
2573 efx_mcdi_filter_table_remove(efx);
2574out_unlock:
2575 up_write(&efx->filter_sem);
2576 return rc;
2577}
2578
2579static void efx_ef10_filter_table_remove(struct efx_nic *efx)
2580{
2581 down_write(&efx->filter_sem);
2582 efx_mcdi_filter_table_remove(efx);
2583 up_write(&efx->filter_sem);
2584}
2585
2586/* This creates an entry in the RX descriptor queue */
2587static inline void
2588efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2589{
2590 struct efx_rx_buffer *rx_buf;
2591 efx_qword_t *rxd;
2592
2593 rxd = efx_rx_desc(rx_queue, index);
2594 rx_buf = efx_rx_buffer(rx_queue, index);
2595 EFX_POPULATE_QWORD_2(*rxd,
2596 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2597 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2598}
2599
2600static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2601{
2602 struct efx_nic *efx = rx_queue->efx;
2603 unsigned int write_count;
2604 efx_dword_t reg;
2605
2606 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2607 write_count = rx_queue->added_count & ~7;
2608 if (rx_queue->notified_count == write_count)
2609 return;
2610
2611 do
2612 efx_ef10_build_rx_desc(
2613 rx_queue,
2614 rx_queue->notified_count & rx_queue->ptr_mask);
2615 while (++rx_queue->notified_count != write_count);
2616
2617 wmb();
2618 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2619 write_count & rx_queue->ptr_mask);
2620 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD,
2621 efx_rx_queue_index(rx_queue));
2622}
2623
2624static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2625
2626static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2627{
2628 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2629 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2630 efx_qword_t event;
2631
2632 EFX_POPULATE_QWORD_2(event,
2633 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2634 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2635
2636 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2637
2638 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2639 * already swapped the data to little-endian order.
2640 */
2641 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2642 sizeof(efx_qword_t));
2643
2644 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2645 inbuf, sizeof(inbuf), 0,
2646 efx_ef10_rx_defer_refill_complete, 0);
2647}
2648
2649static void
2650efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2651 int rc, efx_dword_t *outbuf,
2652 size_t outlen_actual)
2653{
2654 /* nothing to do */
2655}
2656
2657static int efx_ef10_ev_init(struct efx_channel *channel)
2658{
2659 struct efx_nic *efx = channel->efx;
2660 struct efx_ef10_nic_data *nic_data;
2661 bool use_v2, cut_thru;
2662
2663 nic_data = efx->nic_data;
2664 use_v2 = nic_data->datapath_caps2 &
2665 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN;
2666 cut_thru = !(nic_data->datapath_caps &
2667 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
2668 return efx_mcdi_ev_init(channel, cut_thru, use_v2);
2669}
2670
2671static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2672 unsigned int rx_queue_label)
2673{
2674 struct efx_nic *efx = rx_queue->efx;
2675
2676 netif_info(efx, hw, efx->net_dev,
2677 "rx event arrived on queue %d labeled as queue %u\n",
2678 efx_rx_queue_index(rx_queue), rx_queue_label);
2679
2680 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2681}
2682
2683static void
2684efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2685 unsigned int actual, unsigned int expected)
2686{
2687 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2688 struct efx_nic *efx = rx_queue->efx;
2689
2690 netif_info(efx, hw, efx->net_dev,
2691 "dropped %d events (index=%d expected=%d)\n",
2692 dropped, actual, expected);
2693
2694 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2695}
2696
2697/* partially received RX was aborted. clean up. */
2698static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
2699{
2700 unsigned int rx_desc_ptr;
2701
2702 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2703 "scattered RX aborted (dropping %u buffers)\n",
2704 rx_queue->scatter_n);
2705
2706 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
2707
2708 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2709 0, EFX_RX_PKT_DISCARD);
2710
2711 rx_queue->removed_count += rx_queue->scatter_n;
2712 rx_queue->scatter_n = 0;
2713 rx_queue->scatter_len = 0;
2714 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
2715}
2716
2717static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel,
2718 unsigned int n_packets,
2719 unsigned int rx_encap_hdr,
2720 unsigned int rx_l3_class,
2721 unsigned int rx_l4_class,
2722 const efx_qword_t *event)
2723{
2724 struct efx_nic *efx = channel->efx;
2725 bool handled = false;
2726
2727 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) {
2728 if (!(efx->net_dev->features & NETIF_F_RXALL)) {
2729 if (!efx->loopback_selftest)
2730 channel->n_rx_eth_crc_err += n_packets;
2731 return EFX_RX_PKT_DISCARD;
2732 }
2733 handled = true;
2734 }
2735 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) {
2736 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
2737 rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
2738 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
2739 rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
2740 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
2741 netdev_WARN(efx->net_dev,
2742 "invalid class for RX_IPCKSUM_ERR: event="
2743 EFX_QWORD_FMT "\n",
2744 EFX_QWORD_VAL(*event));
2745 if (!efx->loopback_selftest)
2746 *(rx_encap_hdr ?
2747 &channel->n_rx_outer_ip_hdr_chksum_err :
2748 &channel->n_rx_ip_hdr_chksum_err) += n_packets;
2749 return 0;
2750 }
2751 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
2752 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
2753 ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
2754 rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
2755 (rx_l4_class != ESE_FZ_L4_CLASS_TCP &&
2756 rx_l4_class != ESE_FZ_L4_CLASS_UDP))))
2757 netdev_WARN(efx->net_dev,
2758 "invalid class for RX_TCPUDP_CKSUM_ERR: event="
2759 EFX_QWORD_FMT "\n",
2760 EFX_QWORD_VAL(*event));
2761 if (!efx->loopback_selftest)
2762 *(rx_encap_hdr ?
2763 &channel->n_rx_outer_tcp_udp_chksum_err :
2764 &channel->n_rx_tcp_udp_chksum_err) += n_packets;
2765 return 0;
2766 }
2767 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) {
2768 if (unlikely(!rx_encap_hdr))
2769 netdev_WARN(efx->net_dev,
2770 "invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event="
2771 EFX_QWORD_FMT "\n",
2772 EFX_QWORD_VAL(*event));
2773 else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
2774 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
2775 rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
2776 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
2777 netdev_WARN(efx->net_dev,
2778 "invalid class for RX_IP_INNER_CHKSUM_ERR: event="
2779 EFX_QWORD_FMT "\n",
2780 EFX_QWORD_VAL(*event));
2781 if (!efx->loopback_selftest)
2782 channel->n_rx_inner_ip_hdr_chksum_err += n_packets;
2783 return 0;
2784 }
2785 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) {
2786 if (unlikely(!rx_encap_hdr))
2787 netdev_WARN(efx->net_dev,
2788 "invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
2789 EFX_QWORD_FMT "\n",
2790 EFX_QWORD_VAL(*event));
2791 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
2792 rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
2793 (rx_l4_class != ESE_FZ_L4_CLASS_TCP &&
2794 rx_l4_class != ESE_FZ_L4_CLASS_UDP)))
2795 netdev_WARN(efx->net_dev,
2796 "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
2797 EFX_QWORD_FMT "\n",
2798 EFX_QWORD_VAL(*event));
2799 if (!efx->loopback_selftest)
2800 channel->n_rx_inner_tcp_udp_chksum_err += n_packets;
2801 return 0;
2802 }
2803
2804 WARN_ON(!handled); /* No error bits were recognised */
2805 return 0;
2806}
2807
2808static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2809 const efx_qword_t *event)
2810{
2811 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label;
2812 unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr;
2813 unsigned int n_descs, n_packets, i;
2814 struct efx_nic *efx = channel->efx;
2815 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2816 struct efx_rx_queue *rx_queue;
2817 efx_qword_t errors;
2818 bool rx_cont;
2819 u16 flags = 0;
2820
2821 if (unlikely(READ_ONCE(efx->reset_pending)))
2822 return 0;
2823
2824 /* Basic packet information */
2825 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2826 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2827 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
2828 rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS);
2829 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_FZ_RX_L4_CLASS);
2830 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
2831 rx_encap_hdr =
2832 nic_data->datapath_caps &
2833 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ?
2834 EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) :
2835 ESE_EZ_ENCAP_HDR_NONE;
2836
2837 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2838 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2839 EFX_QWORD_FMT "\n",
2840 EFX_QWORD_VAL(*event));
2841
2842 rx_queue = efx_channel_get_rx_queue(channel);
2843
2844 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2845 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
2846
2847 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2848 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2849
2850 if (n_descs != rx_queue->scatter_n + 1) {
2851 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2852
2853 /* detect rx abort */
2854 if (unlikely(n_descs == rx_queue->scatter_n)) {
2855 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2856 netdev_WARN(efx->net_dev,
2857 "invalid RX abort: scatter_n=%u event="
2858 EFX_QWORD_FMT "\n",
2859 rx_queue->scatter_n,
2860 EFX_QWORD_VAL(*event));
2861 efx_ef10_handle_rx_abort(rx_queue);
2862 return 0;
2863 }
2864
2865 /* Check that RX completion merging is valid, i.e.
2866 * the current firmware supports it and this is a
2867 * non-scattered packet.
2868 */
2869 if (!(nic_data->datapath_caps &
2870 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2871 rx_queue->scatter_n != 0 || rx_cont) {
2872 efx_ef10_handle_rx_bad_lbits(
2873 rx_queue, next_ptr_lbits,
2874 (rx_queue->removed_count +
2875 rx_queue->scatter_n + 1) &
2876 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2877 return 0;
2878 }
2879
2880 /* Merged completion for multiple non-scattered packets */
2881 rx_queue->scatter_n = 1;
2882 rx_queue->scatter_len = 0;
2883 n_packets = n_descs;
2884 ++channel->n_rx_merge_events;
2885 channel->n_rx_merge_packets += n_packets;
2886 flags |= EFX_RX_PKT_PREFIX_LEN;
2887 } else {
2888 ++rx_queue->scatter_n;
2889 rx_queue->scatter_len += rx_bytes;
2890 if (rx_cont)
2891 return 0;
2892 n_packets = 1;
2893 }
2894
2895 EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1,
2896 ESF_DZ_RX_IPCKSUM_ERR, 1,
2897 ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1,
2898 ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1,
2899 ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1);
2900 EFX_AND_QWORD(errors, *event, errors);
2901 if (unlikely(!EFX_QWORD_IS_ZERO(errors))) {
2902 flags |= efx_ef10_handle_rx_event_errors(channel, n_packets,
2903 rx_encap_hdr,
2904 rx_l3_class, rx_l4_class,
2905 event);
2906 } else {
2907 bool tcpudp = rx_l4_class == ESE_FZ_L4_CLASS_TCP ||
2908 rx_l4_class == ESE_FZ_L4_CLASS_UDP;
2909
2910 switch (rx_encap_hdr) {
2911 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */
2912 flags |= EFX_RX_PKT_CSUMMED; /* outer UDP csum */
2913 if (tcpudp)
2914 flags |= EFX_RX_PKT_CSUM_LEVEL; /* inner L4 */
2915 break;
2916 case ESE_EZ_ENCAP_HDR_GRE:
2917 case ESE_EZ_ENCAP_HDR_NONE:
2918 if (tcpudp)
2919 flags |= EFX_RX_PKT_CSUMMED;
2920 break;
2921 default:
2922 netdev_WARN(efx->net_dev,
2923 "unknown encapsulation type: event="
2924 EFX_QWORD_FMT "\n",
2925 EFX_QWORD_VAL(*event));
2926 }
2927 }
2928
2929 if (rx_l4_class == ESE_FZ_L4_CLASS_TCP)
2930 flags |= EFX_RX_PKT_TCP;
2931
2932 channel->irq_mod_score += 2 * n_packets;
2933
2934 /* Handle received packet(s) */
2935 for (i = 0; i < n_packets; i++) {
2936 efx_rx_packet(rx_queue,
2937 rx_queue->removed_count & rx_queue->ptr_mask,
2938 rx_queue->scatter_n, rx_queue->scatter_len,
2939 flags);
2940 rx_queue->removed_count += rx_queue->scatter_n;
2941 }
2942
2943 rx_queue->scatter_n = 0;
2944 rx_queue->scatter_len = 0;
2945
2946 return n_packets;
2947}
2948
2949static u32 efx_ef10_extract_event_ts(efx_qword_t *event)
2950{
2951 u32 tstamp;
2952
2953 tstamp = EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI);
2954 tstamp <<= 16;
2955 tstamp |= EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO);
2956
2957 return tstamp;
2958}
2959
2960static int
2961efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
2962{
2963 struct efx_nic *efx = channel->efx;
2964 struct efx_tx_queue *tx_queue;
2965 unsigned int tx_ev_desc_ptr;
2966 unsigned int tx_ev_q_label;
2967 unsigned int tx_ev_type;
2968 int work_done;
2969 u64 ts_part;
2970
2971 if (unlikely(READ_ONCE(efx->reset_pending)))
2972 return 0;
2973
2974 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
2975 return 0;
2976
2977 /* Get the transmit queue */
2978 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
2979 tx_queue = channel->tx_queue + (tx_ev_q_label % EFX_MAX_TXQ_PER_CHANNEL);
2980
2981 if (!tx_queue->timestamping) {
2982 /* Transmit completion */
2983 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
2984 return efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
2985 }
2986
2987 /* Transmit timestamps are only available for 8XXX series. They result
2988 * in up to three events per packet. These occur in order, and are:
2989 * - the normal completion event (may be omitted)
2990 * - the low part of the timestamp
2991 * - the high part of the timestamp
2992 *
2993 * It's possible for multiple completion events to appear before the
2994 * corresponding timestamps. So we can for example get:
2995 * COMP N
2996 * COMP N+1
2997 * TS_LO N
2998 * TS_HI N
2999 * TS_LO N+1
3000 * TS_HI N+1
3001 *
3002 * In addition it's also possible for the adjacent completions to be
3003 * merged, so we may not see COMP N above. As such, the completion
3004 * events are not very useful here.
3005 *
3006 * Each part of the timestamp is itself split across two 16 bit
3007 * fields in the event.
3008 */
3009 tx_ev_type = EFX_QWORD_FIELD(*event, ESF_EZ_TX_SOFT1);
3010 work_done = 0;
3011
3012 switch (tx_ev_type) {
3013 case TX_TIMESTAMP_EVENT_TX_EV_COMPLETION:
3014 /* Ignore this event - see above. */
3015 break;
3016
3017 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO:
3018 ts_part = efx_ef10_extract_event_ts(event);
3019 tx_queue->completed_timestamp_minor = ts_part;
3020 break;
3021
3022 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI:
3023 ts_part = efx_ef10_extract_event_ts(event);
3024 tx_queue->completed_timestamp_major = ts_part;
3025
3026 efx_xmit_done_single(tx_queue);
3027 work_done = 1;
3028 break;
3029
3030 default:
3031 netif_err(efx, hw, efx->net_dev,
3032 "channel %d unknown tx event type %d (data "
3033 EFX_QWORD_FMT ")\n",
3034 channel->channel, tx_ev_type,
3035 EFX_QWORD_VAL(*event));
3036 break;
3037 }
3038
3039 return work_done;
3040}
3041
3042static void
3043efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
3044{
3045 struct efx_nic *efx = channel->efx;
3046 int subcode;
3047
3048 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
3049
3050 switch (subcode) {
3051 case ESE_DZ_DRV_TIMER_EV:
3052 case ESE_DZ_DRV_WAKE_UP_EV:
3053 break;
3054 case ESE_DZ_DRV_START_UP_EV:
3055 /* event queue init complete. ok. */
3056 break;
3057 default:
3058 netif_err(efx, hw, efx->net_dev,
3059 "channel %d unknown driver event type %d"
3060 " (data " EFX_QWORD_FMT ")\n",
3061 channel->channel, subcode,
3062 EFX_QWORD_VAL(*event));
3063
3064 }
3065}
3066
3067static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
3068 efx_qword_t *event)
3069{
3070 struct efx_nic *efx = channel->efx;
3071 u32 subcode;
3072
3073 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
3074
3075 switch (subcode) {
3076 case EFX_EF10_TEST:
3077 channel->event_test_cpu = raw_smp_processor_id();
3078 break;
3079 case EFX_EF10_REFILL:
3080 /* The queue must be empty, so we won't receive any rx
3081 * events, so efx_process_channel() won't refill the
3082 * queue. Refill it here
3083 */
3084 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
3085 break;
3086 default:
3087 netif_err(efx, hw, efx->net_dev,
3088 "channel %d unknown driver event type %u"
3089 " (data " EFX_QWORD_FMT ")\n",
3090 channel->channel, (unsigned) subcode,
3091 EFX_QWORD_VAL(*event));
3092 }
3093}
3094
3095#define EFX_NAPI_MAX_TX 512
3096
3097static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
3098{
3099 struct efx_nic *efx = channel->efx;
3100 efx_qword_t event, *p_event;
3101 unsigned int read_ptr;
3102 int spent_tx = 0;
3103 int spent = 0;
3104 int ev_code;
3105
3106 if (quota <= 0)
3107 return spent;
3108
3109 read_ptr = channel->eventq_read_ptr;
3110
3111 for (;;) {
3112 p_event = efx_event(channel, read_ptr);
3113 event = *p_event;
3114
3115 if (!efx_event_present(&event))
3116 break;
3117
3118 EFX_SET_QWORD(*p_event);
3119
3120 ++read_ptr;
3121
3122 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
3123
3124 netif_vdbg(efx, drv, efx->net_dev,
3125 "processing event on %d " EFX_QWORD_FMT "\n",
3126 channel->channel, EFX_QWORD_VAL(event));
3127
3128 switch (ev_code) {
3129 case ESE_DZ_EV_CODE_MCDI_EV:
3130 efx_mcdi_process_event(channel, &event);
3131 break;
3132 case ESE_DZ_EV_CODE_RX_EV:
3133 spent += efx_ef10_handle_rx_event(channel, &event);
3134 if (spent >= quota) {
3135 /* XXX can we split a merged event to
3136 * avoid going over-quota?
3137 */
3138 spent = quota;
3139 goto out;
3140 }
3141 break;
3142 case ESE_DZ_EV_CODE_TX_EV:
3143 spent_tx += efx_ef10_handle_tx_event(channel, &event);
3144 if (spent_tx >= EFX_NAPI_MAX_TX) {
3145 spent = quota;
3146 goto out;
3147 }
3148 break;
3149 case ESE_DZ_EV_CODE_DRIVER_EV:
3150 efx_ef10_handle_driver_event(channel, &event);
3151 if (++spent == quota)
3152 goto out;
3153 break;
3154 case EFX_EF10_DRVGEN_EV:
3155 efx_ef10_handle_driver_generated_event(channel, &event);
3156 break;
3157 default:
3158 netif_err(efx, hw, efx->net_dev,
3159 "channel %d unknown event type %d"
3160 " (data " EFX_QWORD_FMT ")\n",
3161 channel->channel, ev_code,
3162 EFX_QWORD_VAL(event));
3163 }
3164 }
3165
3166out:
3167 channel->eventq_read_ptr = read_ptr;
3168 return spent;
3169}
3170
3171static void efx_ef10_ev_read_ack(struct efx_channel *channel)
3172{
3173 struct efx_nic *efx = channel->efx;
3174 efx_dword_t rptr;
3175
3176 if (EFX_EF10_WORKAROUND_35388(efx)) {
3177 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
3178 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
3179 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
3180 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
3181
3182 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3183 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
3184 ERF_DD_EVQ_IND_RPTR,
3185 (channel->eventq_read_ptr &
3186 channel->eventq_mask) >>
3187 ERF_DD_EVQ_IND_RPTR_WIDTH);
3188 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3189 channel->channel);
3190 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3191 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
3192 ERF_DD_EVQ_IND_RPTR,
3193 channel->eventq_read_ptr &
3194 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
3195 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3196 channel->channel);
3197 } else {
3198 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
3199 channel->eventq_read_ptr &
3200 channel->eventq_mask);
3201 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
3202 }
3203}
3204
3205static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3206{
3207 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3208 struct efx_nic *efx = channel->efx;
3209 efx_qword_t event;
3210 int rc;
3211
3212 EFX_POPULATE_QWORD_2(event,
3213 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3214 ESF_DZ_EV_DATA, EFX_EF10_TEST);
3215
3216 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3217
3218 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3219 * already swapped the data to little-endian order.
3220 */
3221 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3222 sizeof(efx_qword_t));
3223
3224 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3225 NULL, 0, NULL);
3226 if (rc != 0)
3227 goto fail;
3228
3229 return;
3230
3231fail:
3232 WARN_ON(true);
3233 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3234}
3235
3236static void efx_ef10_prepare_flr(struct efx_nic *efx)
3237{
3238 atomic_set(&efx->active_queues, 0);
3239}
3240
3241static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
3242{
3243 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3244 u8 mac_old[ETH_ALEN];
3245 int rc, rc2;
3246
3247 /* Only reconfigure a PF-created vport */
3248 if (is_zero_ether_addr(nic_data->vport_mac))
3249 return 0;
3250
3251 efx_device_detach_sync(efx);
3252 efx_net_stop(efx->net_dev);
3253 efx_ef10_filter_table_remove(efx);
3254
3255 rc = efx_ef10_vadaptor_free(efx, efx->vport_id);
3256 if (rc)
3257 goto restore_filters;
3258
3259 ether_addr_copy(mac_old, nic_data->vport_mac);
3260 rc = efx_ef10_vport_del_mac(efx, efx->vport_id,
3261 nic_data->vport_mac);
3262 if (rc)
3263 goto restore_vadaptor;
3264
3265 rc = efx_ef10_vport_add_mac(efx, efx->vport_id,
3266 efx->net_dev->dev_addr);
3267 if (!rc) {
3268 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
3269 } else {
3270 rc2 = efx_ef10_vport_add_mac(efx, efx->vport_id, mac_old);
3271 if (rc2) {
3272 /* Failed to add original MAC, so clear vport_mac */
3273 eth_zero_addr(nic_data->vport_mac);
3274 goto reset_nic;
3275 }
3276 }
3277
3278restore_vadaptor:
3279 rc2 = efx_ef10_vadaptor_alloc(efx, efx->vport_id);
3280 if (rc2)
3281 goto reset_nic;
3282restore_filters:
3283 rc2 = efx_ef10_filter_table_probe(efx);
3284 if (rc2)
3285 goto reset_nic;
3286
3287 rc2 = efx_net_open(efx->net_dev);
3288 if (rc2)
3289 goto reset_nic;
3290
3291 efx_device_attach_if_not_resetting(efx);
3292
3293 return rc;
3294
3295reset_nic:
3296 netif_err(efx, drv, efx->net_dev,
3297 "Failed to restore when changing MAC address - scheduling reset\n");
3298 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
3299
3300 return rc ? rc : rc2;
3301}
3302
3303static int efx_ef10_set_mac_address(struct efx_nic *efx)
3304{
3305 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
3306 bool was_enabled = efx->port_enabled;
3307 int rc;
3308
3309#ifdef CONFIG_SFC_SRIOV
3310 /* If this function is a VF and we have access to the parent PF,
3311 * then use the PF control path to attempt to change the VF MAC address.
3312 */
3313 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
3314 struct efx_nic *efx_pf = pci_get_drvdata(efx->pci_dev->physfn);
3315 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3316 u8 mac[ETH_ALEN];
3317
3318 /* net_dev->dev_addr can be zeroed by efx_net_stop in
3319 * efx_ef10_sriov_set_vf_mac, so pass in a copy.
3320 */
3321 ether_addr_copy(mac, efx->net_dev->dev_addr);
3322
3323 rc = efx_ef10_sriov_set_vf_mac(efx_pf, nic_data->vf_index, mac);
3324 if (!rc)
3325 return 0;
3326
3327 netif_dbg(efx, drv, efx->net_dev,
3328 "Updating VF mac via PF failed (%d), setting directly\n",
3329 rc);
3330 }
3331#endif
3332
3333 efx_device_detach_sync(efx);
3334 efx_net_stop(efx->net_dev);
3335
3336 mutex_lock(&efx->mac_lock);
3337 efx_ef10_filter_table_remove(efx);
3338
3339 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
3340 efx->net_dev->dev_addr);
3341 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
3342 efx->vport_id);
3343 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
3344 sizeof(inbuf), NULL, 0, NULL);
3345
3346 efx_ef10_filter_table_probe(efx);
3347 mutex_unlock(&efx->mac_lock);
3348
3349 if (was_enabled)
3350 efx_net_open(efx->net_dev);
3351 efx_device_attach_if_not_resetting(efx);
3352
3353 if (rc == -EPERM) {
3354 netif_err(efx, drv, efx->net_dev,
3355 "Cannot change MAC address; use sfboot to enable"
3356 " mac-spoofing on this interface\n");
3357 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
3358 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
3359 * fall-back to the method of changing the MAC address on the
3360 * vport. This only applies to PFs because such versions of
3361 * MCFW do not support VFs.
3362 */
3363 rc = efx_ef10_vport_set_mac_address(efx);
3364 } else if (rc) {
3365 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
3366 sizeof(inbuf), NULL, 0, rc);
3367 }
3368
3369 return rc;
3370}
3371
3372static int efx_ef10_mac_reconfigure(struct efx_nic *efx, bool mtu_only)
3373{
3374 WARN_ON(!mutex_is_locked(&efx->mac_lock));
3375
3376 efx_mcdi_filter_sync_rx_mode(efx);
3377
3378 if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED))
3379 return efx_mcdi_set_mtu(efx);
3380 return efx_mcdi_set_mac(efx);
3381}
3382
3383static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
3384{
3385 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
3386
3387 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
3388 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
3389 NULL, 0, NULL);
3390}
3391
3392/* MC BISTs follow a different poll mechanism to phy BISTs.
3393 * The BIST is done in the poll handler on the MC, and the MCDI command
3394 * will block until the BIST is done.
3395 */
3396static int efx_ef10_poll_bist(struct efx_nic *efx)
3397{
3398 int rc;
3399 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
3400 size_t outlen;
3401 u32 result;
3402
3403 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
3404 outbuf, sizeof(outbuf), &outlen);
3405 if (rc != 0)
3406 return rc;
3407
3408 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
3409 return -EIO;
3410
3411 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
3412 switch (result) {
3413 case MC_CMD_POLL_BIST_PASSED:
3414 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
3415 return 0;
3416 case MC_CMD_POLL_BIST_TIMEOUT:
3417 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
3418 return -EIO;
3419 case MC_CMD_POLL_BIST_FAILED:
3420 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
3421 return -EIO;
3422 default:
3423 netif_err(efx, hw, efx->net_dev,
3424 "BIST returned unknown result %u", result);
3425 return -EIO;
3426 }
3427}
3428
3429static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
3430{
3431 int rc;
3432
3433 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
3434
3435 rc = efx_ef10_start_bist(efx, bist_type);
3436 if (rc != 0)
3437 return rc;
3438
3439 return efx_ef10_poll_bist(efx);
3440}
3441
3442static int
3443efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
3444{
3445 int rc, rc2;
3446
3447 efx_reset_down(efx, RESET_TYPE_WORLD);
3448
3449 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
3450 NULL, 0, NULL, 0, NULL);
3451 if (rc != 0)
3452 goto out;
3453
3454 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
3455 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
3456
3457 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
3458
3459out:
3460 if (rc == -EPERM)
3461 rc = 0;
3462 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
3463 return rc ? rc : rc2;
3464}
3465
3466#ifdef CONFIG_SFC_MTD
3467
3468struct efx_ef10_nvram_type_info {
3469 u16 type, type_mask;
3470 u8 port;
3471 const char *name;
3472};
3473
3474static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
3475 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
3476 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
3477 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
3478 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
3479 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
3480 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
3481 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
3482 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
3483 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
3484 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
3485 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
3486 { NVRAM_PARTITION_TYPE_MUM_FIRMWARE, 0, 0, "sfc_mumfw" },
3487 { NVRAM_PARTITION_TYPE_EXPANSION_UEFI, 0, 0, "sfc_uefi" },
3488 { NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS, 0, 0, "sfc_dynamic_cfg_dflt" },
3489 { NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS, 0, 0, "sfc_exp_rom_cfg_dflt" },
3490 { NVRAM_PARTITION_TYPE_STATUS, 0, 0, "sfc_status" },
3491 { NVRAM_PARTITION_TYPE_BUNDLE, 0, 0, "sfc_bundle" },
3492 { NVRAM_PARTITION_TYPE_BUNDLE_METADATA, 0, 0, "sfc_bundle_metadata" },
3493};
3494#define EF10_NVRAM_PARTITION_COUNT ARRAY_SIZE(efx_ef10_nvram_types)
3495
3496static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
3497 struct efx_mcdi_mtd_partition *part,
3498 unsigned int type,
3499 unsigned long *found)
3500{
3501 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
3502 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
3503 const struct efx_ef10_nvram_type_info *info;
3504 size_t size, erase_size, outlen;
3505 int type_idx = 0;
3506 bool protected;
3507 int rc;
3508
3509 for (type_idx = 0; ; type_idx++) {
3510 if (type_idx == EF10_NVRAM_PARTITION_COUNT)
3511 return -ENODEV;
3512 info = efx_ef10_nvram_types + type_idx;
3513 if ((type & ~info->type_mask) == info->type)
3514 break;
3515 }
3516 if (info->port != efx_port_num(efx))
3517 return -ENODEV;
3518
3519 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
3520 if (rc)
3521 return rc;
3522 if (protected &&
3523 (type != NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS &&
3524 type != NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS))
3525 /* Hide protected partitions that don't provide defaults. */
3526 return -ENODEV;
3527
3528 if (protected)
3529 /* Protected partitions are read only. */
3530 erase_size = 0;
3531
3532 /* If we've already exposed a partition of this type, hide this
3533 * duplicate. All operations on MTDs are keyed by the type anyway,
3534 * so we can't act on the duplicate.
3535 */
3536 if (__test_and_set_bit(type_idx, found))
3537 return -EEXIST;
3538
3539 part->nvram_type = type;
3540
3541 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
3542 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
3543 outbuf, sizeof(outbuf), &outlen);
3544 if (rc)
3545 return rc;
3546 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
3547 return -EIO;
3548 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
3549 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
3550 part->fw_subtype = MCDI_DWORD(outbuf,
3551 NVRAM_METADATA_OUT_SUBTYPE);
3552
3553 part->common.dev_type_name = "EF10 NVRAM manager";
3554 part->common.type_name = info->name;
3555
3556 part->common.mtd.type = MTD_NORFLASH;
3557 part->common.mtd.flags = MTD_CAP_NORFLASH;
3558 part->common.mtd.size = size;
3559 part->common.mtd.erasesize = erase_size;
3560 /* sfc_status is read-only */
3561 if (!erase_size)
3562 part->common.mtd.flags |= MTD_NO_ERASE;
3563
3564 return 0;
3565}
3566
3567static int efx_ef10_mtd_probe(struct efx_nic *efx)
3568{
3569 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
3570 DECLARE_BITMAP(found, EF10_NVRAM_PARTITION_COUNT) = { 0 };
3571 struct efx_mcdi_mtd_partition *parts;
3572 size_t outlen, n_parts_total, i, n_parts;
3573 unsigned int type;
3574 int rc;
3575
3576 ASSERT_RTNL();
3577
3578 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
3579 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
3580 outbuf, sizeof(outbuf), &outlen);
3581 if (rc)
3582 return rc;
3583 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
3584 return -EIO;
3585
3586 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
3587 if (n_parts_total >
3588 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
3589 return -EIO;
3590
3591 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
3592 if (!parts)
3593 return -ENOMEM;
3594
3595 n_parts = 0;
3596 for (i = 0; i < n_parts_total; i++) {
3597 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
3598 i);
3599 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type,
3600 found);
3601 if (rc == -EEXIST || rc == -ENODEV)
3602 continue;
3603 if (rc)
3604 goto fail;
3605 n_parts++;
3606 }
3607
3608 if (!n_parts) {
3609 kfree(parts);
3610 return 0;
3611 }
3612
3613 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
3614fail:
3615 if (rc)
3616 kfree(parts);
3617 return rc;
3618}
3619
3620#endif /* CONFIG_SFC_MTD */
3621
3622static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
3623{
3624 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
3625}
3626
3627static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
3628 u32 host_time) {}
3629
3630static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
3631 bool temp)
3632{
3633 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
3634 int rc;
3635
3636 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
3637 channel->sync_events_state == SYNC_EVENTS_VALID ||
3638 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
3639 return 0;
3640 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
3641
3642 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
3643 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3644 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
3645 channel->channel);
3646
3647 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3648 inbuf, sizeof(inbuf), NULL, 0, NULL);
3649
3650 if (rc != 0)
3651 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3652 SYNC_EVENTS_DISABLED;
3653
3654 return rc;
3655}
3656
3657static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
3658 bool temp)
3659{
3660 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
3661 int rc;
3662
3663 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
3664 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
3665 return 0;
3666 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
3667 channel->sync_events_state = SYNC_EVENTS_DISABLED;
3668 return 0;
3669 }
3670 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3671 SYNC_EVENTS_DISABLED;
3672
3673 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
3674 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3675 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
3676 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
3677 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
3678 channel->channel);
3679
3680 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3681 inbuf, sizeof(inbuf), NULL, 0, NULL);
3682
3683 return rc;
3684}
3685
3686static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
3687 bool temp)
3688{
3689 int (*set)(struct efx_channel *channel, bool temp);
3690 struct efx_channel *channel;
3691
3692 set = en ?
3693 efx_ef10_rx_enable_timestamping :
3694 efx_ef10_rx_disable_timestamping;
3695
3696 channel = efx_ptp_channel(efx);
3697 if (channel) {
3698 int rc = set(channel, temp);
3699 if (en && rc != 0) {
3700 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
3701 return rc;
3702 }
3703 }
3704
3705 return 0;
3706}
3707
3708static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
3709 struct kernel_hwtstamp_config *init)
3710{
3711 return -EOPNOTSUPP;
3712}
3713
3714static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
3715 struct kernel_hwtstamp_config *init)
3716{
3717 int rc;
3718
3719 switch (init->rx_filter) {
3720 case HWTSTAMP_FILTER_NONE:
3721 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
3722 /* if TX timestamping is still requested then leave PTP on */
3723 return efx_ptp_change_mode(efx,
3724 init->tx_type != HWTSTAMP_TX_OFF, 0);
3725 case HWTSTAMP_FILTER_ALL:
3726 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3727 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3728 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3729 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3730 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3731 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3732 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3733 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3734 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3735 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3736 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3737 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3738 case HWTSTAMP_FILTER_NTP_ALL:
3739 init->rx_filter = HWTSTAMP_FILTER_ALL;
3740 rc = efx_ptp_change_mode(efx, true, 0);
3741 if (!rc)
3742 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
3743 if (rc)
3744 efx_ptp_change_mode(efx, false, 0);
3745 return rc;
3746 default:
3747 return -ERANGE;
3748 }
3749}
3750
3751static int efx_ef10_get_phys_port_id(struct efx_nic *efx,
3752 struct netdev_phys_item_id *ppid)
3753{
3754 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3755
3756 if (!is_valid_ether_addr(nic_data->port_id))
3757 return -EOPNOTSUPP;
3758
3759 ppid->id_len = ETH_ALEN;
3760 memcpy(ppid->id, nic_data->port_id, ppid->id_len);
3761
3762 return 0;
3763}
3764
3765static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
3766{
3767 if (proto != htons(ETH_P_8021Q))
3768 return -EINVAL;
3769
3770 return efx_ef10_add_vlan(efx, vid);
3771}
3772
3773static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
3774{
3775 if (proto != htons(ETH_P_8021Q))
3776 return -EINVAL;
3777
3778 return efx_ef10_del_vlan(efx, vid);
3779}
3780
3781/* We rely on the MCDI wiping out our TX rings if it made any changes to the
3782 * ports table, ensuring that any TSO descriptors that were made on a now-
3783 * removed tunnel port will be blown away and won't break things when we try
3784 * to transmit them using the new ports table.
3785 */
3786static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading)
3787{
3788 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3789 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX);
3790 MCDI_DECLARE_BUF(outbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN);
3791 bool will_reset = false;
3792 size_t num_entries = 0;
3793 size_t inlen, outlen;
3794 size_t i;
3795 int rc;
3796 efx_dword_t flags_and_num_entries;
3797
3798 WARN_ON(!mutex_is_locked(&nic_data->udp_tunnels_lock));
3799
3800 nic_data->udp_tunnels_dirty = false;
3801
3802 if (!(nic_data->datapath_caps &
3803 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) {
3804 efx_device_attach_if_not_resetting(efx);
3805 return 0;
3806 }
3807
3808 BUILD_BUG_ON(ARRAY_SIZE(nic_data->udp_tunnels) >
3809 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
3810
3811 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
3812 if (nic_data->udp_tunnels[i].type !=
3813 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID) {
3814 efx_dword_t entry;
3815
3816 EFX_POPULATE_DWORD_2(entry,
3817 TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT,
3818 ntohs(nic_data->udp_tunnels[i].port),
3819 TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL,
3820 nic_data->udp_tunnels[i].type);
3821 *_MCDI_ARRAY_DWORD(inbuf,
3822 SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES,
3823 num_entries++) = entry;
3824 }
3825 }
3826
3827 BUILD_BUG_ON((MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST -
3828 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST) * 8 !=
3829 EFX_WORD_1_LBN);
3830 BUILD_BUG_ON(MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN * 8 !=
3831 EFX_WORD_1_WIDTH);
3832 EFX_POPULATE_DWORD_2(flags_and_num_entries,
3833 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING,
3834 !!unloading,
3835 EFX_WORD_1, num_entries);
3836 *_MCDI_DWORD(inbuf, SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS) =
3837 flags_and_num_entries;
3838
3839 inlen = MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num_entries);
3840
3841 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS,
3842 inbuf, inlen, outbuf, sizeof(outbuf), &outlen);
3843 if (rc == -EIO) {
3844 /* Most likely the MC rebooted due to another function also
3845 * setting its tunnel port list. Mark the tunnel port list as
3846 * dirty, so it will be pushed upon coming up from the reboot.
3847 */
3848 nic_data->udp_tunnels_dirty = true;
3849 return 0;
3850 }
3851
3852 if (rc) {
3853 /* expected not available on unprivileged functions */
3854 if (rc != -EPERM)
3855 netif_warn(efx, drv, efx->net_dev,
3856 "Unable to set UDP tunnel ports; rc=%d.\n", rc);
3857 } else if (MCDI_DWORD(outbuf, SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS) &
3858 (1 << MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN)) {
3859 netif_info(efx, drv, efx->net_dev,
3860 "Rebooting MC due to UDP tunnel port list change\n");
3861 will_reset = true;
3862 if (unloading)
3863 /* Delay for the MC reset to complete. This will make
3864 * unloading other functions a bit smoother. This is a
3865 * race, but the other unload will work whichever way
3866 * it goes, this just avoids an unnecessary error
3867 * message.
3868 */
3869 msleep(100);
3870 }
3871 if (!will_reset && !unloading) {
3872 /* The caller will have detached, relying on the MC reset to
3873 * trigger a re-attach. Since there won't be an MC reset, we
3874 * have to do the attach ourselves.
3875 */
3876 efx_device_attach_if_not_resetting(efx);
3877 }
3878
3879 return rc;
3880}
3881
3882static int efx_ef10_udp_tnl_push_ports(struct efx_nic *efx)
3883{
3884 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3885 int rc = 0;
3886
3887 mutex_lock(&nic_data->udp_tunnels_lock);
3888 if (nic_data->udp_tunnels_dirty) {
3889 /* Make sure all TX are stopped while we modify the table, else
3890 * we might race against an efx_features_check().
3891 */
3892 efx_device_detach_sync(efx);
3893 rc = efx_ef10_set_udp_tnl_ports(efx, false);
3894 }
3895 mutex_unlock(&nic_data->udp_tunnels_lock);
3896 return rc;
3897}
3898
3899static int efx_ef10_udp_tnl_set_port(struct net_device *dev,
3900 unsigned int table, unsigned int entry,
3901 struct udp_tunnel_info *ti)
3902{
3903 struct efx_nic *efx = efx_netdev_priv(dev);
3904 struct efx_ef10_nic_data *nic_data;
3905 int efx_tunnel_type, rc;
3906
3907 if (ti->type == UDP_TUNNEL_TYPE_VXLAN)
3908 efx_tunnel_type = TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN;
3909 else
3910 efx_tunnel_type = TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE;
3911
3912 nic_data = efx->nic_data;
3913 if (!(nic_data->datapath_caps &
3914 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
3915 return -EOPNOTSUPP;
3916
3917 mutex_lock(&nic_data->udp_tunnels_lock);
3918 /* Make sure all TX are stopped while we add to the table, else we
3919 * might race against an efx_features_check().
3920 */
3921 efx_device_detach_sync(efx);
3922 nic_data->udp_tunnels[entry].type = efx_tunnel_type;
3923 nic_data->udp_tunnels[entry].port = ti->port;
3924 rc = efx_ef10_set_udp_tnl_ports(efx, false);
3925 mutex_unlock(&nic_data->udp_tunnels_lock);
3926
3927 return rc;
3928}
3929
3930/* Called under the TX lock with the TX queue running, hence no-one can be
3931 * in the middle of updating the UDP tunnels table. However, they could
3932 * have tried and failed the MCDI, in which case they'll have set the dirty
3933 * flag before dropping their locks.
3934 */
3935static bool efx_ef10_udp_tnl_has_port(struct efx_nic *efx, __be16 port)
3936{
3937 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3938 size_t i;
3939
3940 if (!(nic_data->datapath_caps &
3941 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
3942 return false;
3943
3944 if (nic_data->udp_tunnels_dirty)
3945 /* SW table may not match HW state, so just assume we can't
3946 * use any UDP tunnel offloads.
3947 */
3948 return false;
3949
3950 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i)
3951 if (nic_data->udp_tunnels[i].type !=
3952 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID &&
3953 nic_data->udp_tunnels[i].port == port)
3954 return true;
3955
3956 return false;
3957}
3958
3959static int efx_ef10_udp_tnl_unset_port(struct net_device *dev,
3960 unsigned int table, unsigned int entry,
3961 struct udp_tunnel_info *ti)
3962{
3963 struct efx_nic *efx = efx_netdev_priv(dev);
3964 struct efx_ef10_nic_data *nic_data;
3965 int rc;
3966
3967 nic_data = efx->nic_data;
3968
3969 mutex_lock(&nic_data->udp_tunnels_lock);
3970 /* Make sure all TX are stopped while we remove from the table, else we
3971 * might race against an efx_features_check().
3972 */
3973 efx_device_detach_sync(efx);
3974 nic_data->udp_tunnels[entry].type = TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID;
3975 nic_data->udp_tunnels[entry].port = 0;
3976 rc = efx_ef10_set_udp_tnl_ports(efx, false);
3977 mutex_unlock(&nic_data->udp_tunnels_lock);
3978
3979 return rc;
3980}
3981
3982static const struct udp_tunnel_nic_info efx_ef10_udp_tunnels = {
3983 .set_port = efx_ef10_udp_tnl_set_port,
3984 .unset_port = efx_ef10_udp_tnl_unset_port,
3985 .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP,
3986 .tables = {
3987 {
3988 .n_entries = 16,
3989 .tunnel_types = UDP_TUNNEL_TYPE_VXLAN |
3990 UDP_TUNNEL_TYPE_GENEVE,
3991 },
3992 },
3993};
3994
3995/* EF10 may have multiple datapath firmware variants within a
3996 * single version. Report which variants are running.
3997 */
3998static size_t efx_ef10_print_additional_fwver(struct efx_nic *efx, char *buf,
3999 size_t len)
4000{
4001 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4002
4003 return scnprintf(buf, len, " rx%x tx%x",
4004 nic_data->rx_dpcpu_fw_id,
4005 nic_data->tx_dpcpu_fw_id);
4006}
4007
4008static unsigned int ef10_check_caps(const struct efx_nic *efx,
4009 u8 flag,
4010 u32 offset)
4011{
4012 const struct efx_ef10_nic_data *nic_data = efx->nic_data;
4013
4014 switch (offset) {
4015 case(MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST):
4016 return nic_data->datapath_caps & BIT_ULL(flag);
4017 case(MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST):
4018 return nic_data->datapath_caps2 & BIT_ULL(flag);
4019 default:
4020 return 0;
4021 }
4022}
4023
4024static unsigned int efx_ef10_recycle_ring_size(const struct efx_nic *efx)
4025{
4026 unsigned int ret = EFX_RECYCLE_RING_SIZE_10G;
4027
4028 /* There is no difference between PFs and VFs. The side is based on
4029 * the maximum link speed of a given NIC.
4030 */
4031 switch (efx->pci_dev->device & 0xfff) {
4032 case 0x0903: /* Farmingdale can do up to 10G */
4033 break;
4034 case 0x0923: /* Greenport can do up to 40G */
4035 case 0x0a03: /* Medford can do up to 40G */
4036 ret *= 4;
4037 break;
4038 default: /* Medford2 can do up to 100G */
4039 ret *= 10;
4040 }
4041
4042 if (IS_ENABLED(CONFIG_PPC64))
4043 ret *= 4;
4044
4045 return ret;
4046}
4047
4048#define EF10_OFFLOAD_FEATURES \
4049 (NETIF_F_IP_CSUM | \
4050 NETIF_F_HW_VLAN_CTAG_FILTER | \
4051 NETIF_F_IPV6_CSUM | \
4052 NETIF_F_RXHASH | \
4053 NETIF_F_NTUPLE | \
4054 NETIF_F_SG | \
4055 NETIF_F_RXCSUM | \
4056 NETIF_F_RXALL)
4057
4058const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
4059 .is_vf = true,
4060 .mem_bar = efx_ef10_vf_mem_bar,
4061 .mem_map_size = efx_ef10_mem_map_size,
4062 .probe = efx_ef10_probe_vf,
4063 .remove = efx_ef10_remove,
4064 .dimension_resources = efx_ef10_dimension_resources,
4065 .init = efx_ef10_init_nic,
4066 .fini = efx_ef10_fini_nic,
4067 .map_reset_reason = efx_ef10_map_reset_reason,
4068 .map_reset_flags = efx_ef10_map_reset_flags,
4069 .reset = efx_ef10_reset,
4070 .probe_port = efx_mcdi_port_probe,
4071 .remove_port = efx_mcdi_port_remove,
4072 .fini_dmaq = efx_fini_dmaq,
4073 .prepare_flr = efx_ef10_prepare_flr,
4074 .finish_flr = efx_port_dummy_op_void,
4075 .describe_stats = efx_ef10_describe_stats,
4076 .update_stats = efx_ef10_update_stats_vf,
4077 .update_stats_atomic = efx_ef10_update_stats_atomic_vf,
4078 .start_stats = efx_port_dummy_op_void,
4079 .pull_stats = efx_port_dummy_op_void,
4080 .stop_stats = efx_port_dummy_op_void,
4081 .push_irq_moderation = efx_ef10_push_irq_moderation,
4082 .reconfigure_mac = efx_ef10_mac_reconfigure,
4083 .check_mac_fault = efx_mcdi_mac_check_fault,
4084 .reconfigure_port = efx_mcdi_port_reconfigure,
4085 .get_wol = efx_ef10_get_wol_vf,
4086 .set_wol = efx_ef10_set_wol_vf,
4087 .resume_wol = efx_port_dummy_op_void,
4088 .mcdi_request = efx_ef10_mcdi_request,
4089 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4090 .mcdi_read_response = efx_ef10_mcdi_read_response,
4091 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4092 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
4093 .irq_enable_master = efx_port_dummy_op_void,
4094 .irq_test_generate = efx_ef10_irq_test_generate,
4095 .irq_disable_non_ev = efx_port_dummy_op_void,
4096 .irq_handle_msi = efx_ef10_msi_interrupt,
4097 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4098 .tx_probe = efx_ef10_tx_probe,
4099 .tx_init = efx_ef10_tx_init,
4100 .tx_remove = efx_mcdi_tx_remove,
4101 .tx_write = efx_ef10_tx_write,
4102 .tx_limit_len = efx_ef10_tx_limit_len,
4103 .tx_enqueue = __efx_enqueue_skb,
4104 .rx_push_rss_config = efx_mcdi_vf_rx_push_rss_config,
4105 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
4106 .rx_probe = efx_mcdi_rx_probe,
4107 .rx_init = efx_mcdi_rx_init,
4108 .rx_remove = efx_mcdi_rx_remove,
4109 .rx_write = efx_ef10_rx_write,
4110 .rx_defer_refill = efx_ef10_rx_defer_refill,
4111 .rx_packet = __efx_rx_packet,
4112 .ev_probe = efx_mcdi_ev_probe,
4113 .ev_init = efx_ef10_ev_init,
4114 .ev_fini = efx_mcdi_ev_fini,
4115 .ev_remove = efx_mcdi_ev_remove,
4116 .ev_process = efx_ef10_ev_process,
4117 .ev_read_ack = efx_ef10_ev_read_ack,
4118 .ev_test_generate = efx_ef10_ev_test_generate,
4119 .filter_table_probe = efx_ef10_filter_table_probe,
4120 .filter_table_restore = efx_mcdi_filter_table_restore,
4121 .filter_table_remove = efx_ef10_filter_table_remove,
4122 .filter_update_rx_scatter = efx_mcdi_update_rx_scatter,
4123 .filter_insert = efx_mcdi_filter_insert,
4124 .filter_remove_safe = efx_mcdi_filter_remove_safe,
4125 .filter_get_safe = efx_mcdi_filter_get_safe,
4126 .filter_clear_rx = efx_mcdi_filter_clear_rx,
4127 .filter_count_rx_used = efx_mcdi_filter_count_rx_used,
4128 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
4129 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
4130#ifdef CONFIG_RFS_ACCEL
4131 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
4132#endif
4133#ifdef CONFIG_SFC_MTD
4134 .mtd_probe = efx_port_dummy_op_int,
4135#endif
4136 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
4137 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4138 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
4139 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
4140#ifdef CONFIG_SFC_SRIOV
4141 .vswitching_probe = efx_ef10_vswitching_probe_vf,
4142 .vswitching_restore = efx_ef10_vswitching_restore_vf,
4143 .vswitching_remove = efx_ef10_vswitching_remove_vf,
4144#endif
4145 .get_mac_address = efx_ef10_get_mac_address_vf,
4146 .set_mac_address = efx_ef10_set_mac_address,
4147
4148 .get_phys_port_id = efx_ef10_get_phys_port_id,
4149 .revision = EFX_REV_HUNT_A0,
4150 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4151 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4152 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4153 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4154 .can_rx_scatter = true,
4155 .always_rx_scatter = true,
4156 .min_interrupt_mode = EFX_INT_MODE_MSIX,
4157 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4158 .offload_features = EF10_OFFLOAD_FEATURES,
4159 .mcdi_max_ver = 2,
4160 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
4161 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4162 1 << HWTSTAMP_FILTER_ALL,
4163 .rx_hash_key_size = 40,
4164 .check_caps = ef10_check_caps,
4165 .print_additional_fwver = efx_ef10_print_additional_fwver,
4166 .sensor_event = efx_mcdi_sensor_event,
4167 .rx_recycle_ring_size = efx_ef10_recycle_ring_size,
4168};
4169
4170const struct efx_nic_type efx_hunt_a0_nic_type = {
4171 .is_vf = false,
4172 .mem_bar = efx_ef10_pf_mem_bar,
4173 .mem_map_size = efx_ef10_mem_map_size,
4174 .probe = efx_ef10_probe_pf,
4175 .remove = efx_ef10_remove,
4176 .dimension_resources = efx_ef10_dimension_resources,
4177 .init = efx_ef10_init_nic,
4178 .fini = efx_ef10_fini_nic,
4179 .map_reset_reason = efx_ef10_map_reset_reason,
4180 .map_reset_flags = efx_ef10_map_reset_flags,
4181 .reset = efx_ef10_reset,
4182 .probe_port = efx_mcdi_port_probe,
4183 .remove_port = efx_mcdi_port_remove,
4184 .fini_dmaq = efx_fini_dmaq,
4185 .prepare_flr = efx_ef10_prepare_flr,
4186 .finish_flr = efx_port_dummy_op_void,
4187 .describe_stats = efx_ef10_describe_stats,
4188 .update_stats = efx_ef10_update_stats_pf,
4189 .start_stats = efx_mcdi_mac_start_stats,
4190 .pull_stats = efx_mcdi_mac_pull_stats,
4191 .stop_stats = efx_mcdi_mac_stop_stats,
4192 .push_irq_moderation = efx_ef10_push_irq_moderation,
4193 .reconfigure_mac = efx_ef10_mac_reconfigure,
4194 .check_mac_fault = efx_mcdi_mac_check_fault,
4195 .reconfigure_port = efx_mcdi_port_reconfigure,
4196 .get_wol = efx_ef10_get_wol,
4197 .set_wol = efx_ef10_set_wol,
4198 .resume_wol = efx_port_dummy_op_void,
4199 .get_fec_stats = efx_ef10_get_fec_stats,
4200 .test_chip = efx_ef10_test_chip,
4201 .test_nvram = efx_mcdi_nvram_test_all,
4202 .mcdi_request = efx_ef10_mcdi_request,
4203 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4204 .mcdi_read_response = efx_ef10_mcdi_read_response,
4205 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4206 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
4207 .irq_enable_master = efx_port_dummy_op_void,
4208 .irq_test_generate = efx_ef10_irq_test_generate,
4209 .irq_disable_non_ev = efx_port_dummy_op_void,
4210 .irq_handle_msi = efx_ef10_msi_interrupt,
4211 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4212 .tx_probe = efx_ef10_tx_probe,
4213 .tx_init = efx_ef10_tx_init,
4214 .tx_remove = efx_mcdi_tx_remove,
4215 .tx_write = efx_ef10_tx_write,
4216 .tx_limit_len = efx_ef10_tx_limit_len,
4217 .tx_enqueue = __efx_enqueue_skb,
4218 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config,
4219 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
4220 .rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config,
4221 .rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config,
4222 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts,
4223 .rx_probe = efx_mcdi_rx_probe,
4224 .rx_init = efx_mcdi_rx_init,
4225 .rx_remove = efx_mcdi_rx_remove,
4226 .rx_write = efx_ef10_rx_write,
4227 .rx_defer_refill = efx_ef10_rx_defer_refill,
4228 .rx_packet = __efx_rx_packet,
4229 .ev_probe = efx_mcdi_ev_probe,
4230 .ev_init = efx_ef10_ev_init,
4231 .ev_fini = efx_mcdi_ev_fini,
4232 .ev_remove = efx_mcdi_ev_remove,
4233 .ev_process = efx_ef10_ev_process,
4234 .ev_read_ack = efx_ef10_ev_read_ack,
4235 .ev_test_generate = efx_ef10_ev_test_generate,
4236 .filter_table_probe = efx_ef10_filter_table_probe,
4237 .filter_table_restore = efx_mcdi_filter_table_restore,
4238 .filter_table_remove = efx_ef10_filter_table_remove,
4239 .filter_update_rx_scatter = efx_mcdi_update_rx_scatter,
4240 .filter_insert = efx_mcdi_filter_insert,
4241 .filter_remove_safe = efx_mcdi_filter_remove_safe,
4242 .filter_get_safe = efx_mcdi_filter_get_safe,
4243 .filter_clear_rx = efx_mcdi_filter_clear_rx,
4244 .filter_count_rx_used = efx_mcdi_filter_count_rx_used,
4245 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
4246 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
4247#ifdef CONFIG_RFS_ACCEL
4248 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
4249#endif
4250#ifdef CONFIG_SFC_MTD
4251 .mtd_probe = efx_ef10_mtd_probe,
4252 .mtd_rename = efx_mcdi_mtd_rename,
4253 .mtd_read = efx_mcdi_mtd_read,
4254 .mtd_erase = efx_mcdi_mtd_erase,
4255 .mtd_write = efx_mcdi_mtd_write,
4256 .mtd_sync = efx_mcdi_mtd_sync,
4257#endif
4258 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
4259 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
4260 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
4261 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
4262 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
4263 .udp_tnl_push_ports = efx_ef10_udp_tnl_push_ports,
4264 .udp_tnl_has_port = efx_ef10_udp_tnl_has_port,
4265#ifdef CONFIG_SFC_SRIOV
4266 .sriov_configure = efx_ef10_sriov_configure,
4267 .sriov_init = efx_ef10_sriov_init,
4268 .sriov_fini = efx_ef10_sriov_fini,
4269 .sriov_wanted = efx_ef10_sriov_wanted,
4270 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
4271 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
4272 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
4273 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4274 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
4275 .vswitching_probe = efx_ef10_vswitching_probe_pf,
4276 .vswitching_restore = efx_ef10_vswitching_restore_pf,
4277 .vswitching_remove = efx_ef10_vswitching_remove_pf,
4278#endif
4279 .get_mac_address = efx_ef10_get_mac_address_pf,
4280 .set_mac_address = efx_ef10_set_mac_address,
4281 .tso_versions = efx_ef10_tso_versions,
4282
4283 .get_phys_port_id = efx_ef10_get_phys_port_id,
4284 .revision = EFX_REV_HUNT_A0,
4285 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4286 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4287 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4288 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4289 .can_rx_scatter = true,
4290 .always_rx_scatter = true,
4291 .option_descriptors = true,
4292 .min_interrupt_mode = EFX_INT_MODE_LEGACY,
4293 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4294 .offload_features = EF10_OFFLOAD_FEATURES,
4295 .mcdi_max_ver = 2,
4296 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
4297 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4298 1 << HWTSTAMP_FILTER_ALL,
4299 .rx_hash_key_size = 40,
4300 .check_caps = ef10_check_caps,
4301 .print_additional_fwver = efx_ef10_print_additional_fwver,
4302 .sensor_event = efx_mcdi_sensor_event,
4303 .rx_recycle_ring_size = efx_ef10_recycle_ring_size,
4304};
1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include "net_driver.h"
11#include "ef10_regs.h"
12#include "io.h"
13#include "mcdi.h"
14#include "mcdi_pcol.h"
15#include "nic.h"
16#include "workarounds.h"
17#include "selftest.h"
18#include "ef10_sriov.h"
19#include <linux/in.h>
20#include <linux/jhash.h>
21#include <linux/wait.h>
22#include <linux/workqueue.h>
23
24/* Hardware control for EF10 architecture including 'Huntington'. */
25
26#define EFX_EF10_DRVGEN_EV 7
27enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30};
31
32/* The reserved RSS context value */
33#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
34/* The maximum size of a shared RSS context */
35/* TODO: this should really be from the mcdi protocol export */
36#define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
37
38/* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
45 * table.
46 *
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
49 */
50#define HUNT_FILTER_TBL_ROWS 8192
51
52#define EFX_EF10_FILTER_ID_INVALID 0xffff
53
54#define EFX_EF10_FILTER_DEV_UC_MAX 32
55#define EFX_EF10_FILTER_DEV_MC_MAX 256
56
57/* VLAN list entry */
58struct efx_ef10_vlan {
59 struct list_head list;
60 u16 vid;
61};
62
63/* Per-VLAN filters information */
64struct efx_ef10_filter_vlan {
65 struct list_head list;
66 u16 vid;
67 u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
68 u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
69 u16 ucdef;
70 u16 bcast;
71 u16 mcdef;
72};
73
74struct efx_ef10_dev_addr {
75 u8 addr[ETH_ALEN];
76};
77
78struct efx_ef10_filter_table {
79/* The MCDI match masks supported by this fw & hw, in order of priority */
80 u32 rx_match_mcdi_flags[
81 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
82 unsigned int rx_match_count;
83
84 struct {
85 unsigned long spec; /* pointer to spec plus flag bits */
86/* BUSY flag indicates that an update is in progress. AUTO_OLD is
87 * used to mark and sweep MAC filters for the device address lists.
88 */
89#define EFX_EF10_FILTER_FLAG_BUSY 1UL
90#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
91#define EFX_EF10_FILTER_FLAGS 3UL
92 u64 handle; /* firmware handle */
93 } *entry;
94 wait_queue_head_t waitq;
95/* Shadow of net_device address lists, guarded by mac_lock */
96 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
97 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
98 int dev_uc_count;
99 int dev_mc_count;
100 bool uc_promisc;
101 bool mc_promisc;
102/* Whether in multicast promiscuous mode when last changed */
103 bool mc_promisc_last;
104 bool vlan_filter;
105 struct list_head vlan_list;
106};
107
108/* An arbitrary search limit for the software hash table */
109#define EFX_EF10_FILTER_SEARCH_LIMIT 200
110
111static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
112static void efx_ef10_filter_table_remove(struct efx_nic *efx);
113static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
114static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
115 struct efx_ef10_filter_vlan *vlan);
116static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
117
118static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
119{
120 efx_dword_t reg;
121
122 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS);
123 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
124 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
125}
126
127static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
128{
129 int bar;
130
131 bar = efx->type->mem_bar;
132 return resource_size(&efx->pci_dev->resource[bar]);
133}
134
135static bool efx_ef10_is_vf(struct efx_nic *efx)
136{
137 return efx->type->is_vf;
138}
139
140static int efx_ef10_get_pf_index(struct efx_nic *efx)
141{
142 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
143 struct efx_ef10_nic_data *nic_data = efx->nic_data;
144 size_t outlen;
145 int rc;
146
147 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
148 sizeof(outbuf), &outlen);
149 if (rc)
150 return rc;
151 if (outlen < sizeof(outbuf))
152 return -EIO;
153
154 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
155 return 0;
156}
157
158#ifdef CONFIG_SFC_SRIOV
159static int efx_ef10_get_vf_index(struct efx_nic *efx)
160{
161 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
162 struct efx_ef10_nic_data *nic_data = efx->nic_data;
163 size_t outlen;
164 int rc;
165
166 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
167 sizeof(outbuf), &outlen);
168 if (rc)
169 return rc;
170 if (outlen < sizeof(outbuf))
171 return -EIO;
172
173 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
174 return 0;
175}
176#endif
177
178static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
179{
180 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V2_OUT_LEN);
181 struct efx_ef10_nic_data *nic_data = efx->nic_data;
182 size_t outlen;
183 int rc;
184
185 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
186
187 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
188 outbuf, sizeof(outbuf), &outlen);
189 if (rc)
190 return rc;
191 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
192 netif_err(efx, drv, efx->net_dev,
193 "unable to read datapath firmware capabilities\n");
194 return -EIO;
195 }
196
197 nic_data->datapath_caps =
198 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
199
200 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN)
201 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
202 GET_CAPABILITIES_V2_OUT_FLAGS2);
203 else
204 nic_data->datapath_caps2 = 0;
205
206 /* record the DPCPU firmware IDs to determine VEB vswitching support.
207 */
208 nic_data->rx_dpcpu_fw_id =
209 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
210 nic_data->tx_dpcpu_fw_id =
211 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
212
213 if (!(nic_data->datapath_caps &
214 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
215 netif_err(efx, probe, efx->net_dev,
216 "current firmware does not support an RX prefix\n");
217 return -ENODEV;
218 }
219
220 return 0;
221}
222
223static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
224{
225 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
226 int rc;
227
228 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
229 outbuf, sizeof(outbuf), NULL);
230 if (rc)
231 return rc;
232 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
233 return rc > 0 ? rc : -ERANGE;
234}
235
236static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
237{
238 struct efx_ef10_nic_data *nic_data = efx->nic_data;
239 unsigned int implemented;
240 unsigned int enabled;
241 int rc;
242
243 nic_data->workaround_35388 = false;
244 nic_data->workaround_61265 = false;
245
246 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
247
248 if (rc == -ENOSYS) {
249 /* Firmware without GET_WORKAROUNDS - not a problem. */
250 rc = 0;
251 } else if (rc == 0) {
252 /* Bug61265 workaround is always enabled if implemented. */
253 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
254 nic_data->workaround_61265 = true;
255
256 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
257 nic_data->workaround_35388 = true;
258 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
259 /* Workaround is implemented but not enabled.
260 * Try to enable it.
261 */
262 rc = efx_mcdi_set_workaround(efx,
263 MC_CMD_WORKAROUND_BUG35388,
264 true, NULL);
265 if (rc == 0)
266 nic_data->workaround_35388 = true;
267 /* If we failed to set the workaround just carry on. */
268 rc = 0;
269 }
270 }
271
272 netif_dbg(efx, probe, efx->net_dev,
273 "workaround for bug 35388 is %sabled\n",
274 nic_data->workaround_35388 ? "en" : "dis");
275 netif_dbg(efx, probe, efx->net_dev,
276 "workaround for bug 61265 is %sabled\n",
277 nic_data->workaround_61265 ? "en" : "dis");
278
279 return rc;
280}
281
282static void efx_ef10_process_timer_config(struct efx_nic *efx,
283 const efx_dword_t *data)
284{
285 unsigned int max_count;
286
287 if (EFX_EF10_WORKAROUND_61265(efx)) {
288 efx->timer_quantum_ns = MCDI_DWORD(data,
289 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
290 efx->timer_max_ns = MCDI_DWORD(data,
291 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
292 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
293 efx->timer_quantum_ns = MCDI_DWORD(data,
294 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
295 max_count = MCDI_DWORD(data,
296 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
297 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
298 } else {
299 efx->timer_quantum_ns = MCDI_DWORD(data,
300 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
301 max_count = MCDI_DWORD(data,
302 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
303 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
304 }
305
306 netif_dbg(efx, probe, efx->net_dev,
307 "got timer properties from MC: quantum %u ns; max %u ns\n",
308 efx->timer_quantum_ns, efx->timer_max_ns);
309}
310
311static int efx_ef10_get_timer_config(struct efx_nic *efx)
312{
313 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
314 int rc;
315
316 rc = efx_ef10_get_timer_workarounds(efx);
317 if (rc)
318 return rc;
319
320 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
321 outbuf, sizeof(outbuf), NULL);
322
323 if (rc == 0) {
324 efx_ef10_process_timer_config(efx, outbuf);
325 } else if (rc == -ENOSYS || rc == -EPERM) {
326 /* Not available - fall back to Huntington defaults. */
327 unsigned int quantum;
328
329 rc = efx_ef10_get_sysclk_freq(efx);
330 if (rc < 0)
331 return rc;
332
333 quantum = 1536000 / rc; /* 1536 cycles */
334 efx->timer_quantum_ns = quantum;
335 efx->timer_max_ns = efx->type->timer_period_max * quantum;
336 rc = 0;
337 } else {
338 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
339 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
340 NULL, 0, rc);
341 }
342
343 return rc;
344}
345
346static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
347{
348 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
349 size_t outlen;
350 int rc;
351
352 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
353
354 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
355 outbuf, sizeof(outbuf), &outlen);
356 if (rc)
357 return rc;
358 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
359 return -EIO;
360
361 ether_addr_copy(mac_address,
362 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
363 return 0;
364}
365
366static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
367{
368 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
369 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
370 size_t outlen;
371 int num_addrs, rc;
372
373 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
374 EVB_PORT_ID_ASSIGNED);
375 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
376 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
377
378 if (rc)
379 return rc;
380 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
381 return -EIO;
382
383 num_addrs = MCDI_DWORD(outbuf,
384 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
385
386 WARN_ON(num_addrs != 1);
387
388 ether_addr_copy(mac_address,
389 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
390
391 return 0;
392}
393
394static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
395 struct device_attribute *attr,
396 char *buf)
397{
398 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
399
400 return sprintf(buf, "%d\n",
401 ((efx->mcdi->fn_flags) &
402 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
403 ? 1 : 0);
404}
405
406static ssize_t efx_ef10_show_primary_flag(struct device *dev,
407 struct device_attribute *attr,
408 char *buf)
409{
410 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
411
412 return sprintf(buf, "%d\n",
413 ((efx->mcdi->fn_flags) &
414 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
415 ? 1 : 0);
416}
417
418static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
419{
420 struct efx_ef10_nic_data *nic_data = efx->nic_data;
421 struct efx_ef10_vlan *vlan;
422
423 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
424
425 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
426 if (vlan->vid == vid)
427 return vlan;
428 }
429
430 return NULL;
431}
432
433static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
434{
435 struct efx_ef10_nic_data *nic_data = efx->nic_data;
436 struct efx_ef10_vlan *vlan;
437 int rc;
438
439 mutex_lock(&nic_data->vlan_lock);
440
441 vlan = efx_ef10_find_vlan(efx, vid);
442 if (vlan) {
443 /* We add VID 0 on init. 8021q adds it on module init
444 * for all interfaces with VLAN filtring feature.
445 */
446 if (vid == 0)
447 goto done_unlock;
448 netif_warn(efx, drv, efx->net_dev,
449 "VLAN %u already added\n", vid);
450 rc = -EALREADY;
451 goto fail_exist;
452 }
453
454 rc = -ENOMEM;
455 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
456 if (!vlan)
457 goto fail_alloc;
458
459 vlan->vid = vid;
460
461 list_add_tail(&vlan->list, &nic_data->vlan_list);
462
463 if (efx->filter_state) {
464 mutex_lock(&efx->mac_lock);
465 down_write(&efx->filter_sem);
466 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
467 up_write(&efx->filter_sem);
468 mutex_unlock(&efx->mac_lock);
469 if (rc)
470 goto fail_filter_add_vlan;
471 }
472
473done_unlock:
474 mutex_unlock(&nic_data->vlan_lock);
475 return 0;
476
477fail_filter_add_vlan:
478 list_del(&vlan->list);
479 kfree(vlan);
480fail_alloc:
481fail_exist:
482 mutex_unlock(&nic_data->vlan_lock);
483 return rc;
484}
485
486static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
487 struct efx_ef10_vlan *vlan)
488{
489 struct efx_ef10_nic_data *nic_data = efx->nic_data;
490
491 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
492
493 if (efx->filter_state) {
494 down_write(&efx->filter_sem);
495 efx_ef10_filter_del_vlan(efx, vlan->vid);
496 up_write(&efx->filter_sem);
497 }
498
499 list_del(&vlan->list);
500 kfree(vlan);
501}
502
503static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
504{
505 struct efx_ef10_nic_data *nic_data = efx->nic_data;
506 struct efx_ef10_vlan *vlan;
507 int rc = 0;
508
509 /* 8021q removes VID 0 on module unload for all interfaces
510 * with VLAN filtering feature. We need to keep it to receive
511 * untagged traffic.
512 */
513 if (vid == 0)
514 return 0;
515
516 mutex_lock(&nic_data->vlan_lock);
517
518 vlan = efx_ef10_find_vlan(efx, vid);
519 if (!vlan) {
520 netif_err(efx, drv, efx->net_dev,
521 "VLAN %u to be deleted not found\n", vid);
522 rc = -ENOENT;
523 } else {
524 efx_ef10_del_vlan_internal(efx, vlan);
525 }
526
527 mutex_unlock(&nic_data->vlan_lock);
528
529 return rc;
530}
531
532static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
533{
534 struct efx_ef10_nic_data *nic_data = efx->nic_data;
535 struct efx_ef10_vlan *vlan, *next_vlan;
536
537 mutex_lock(&nic_data->vlan_lock);
538 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
539 efx_ef10_del_vlan_internal(efx, vlan);
540 mutex_unlock(&nic_data->vlan_lock);
541}
542
543static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
544 NULL);
545static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
546
547static int efx_ef10_probe(struct efx_nic *efx)
548{
549 struct efx_ef10_nic_data *nic_data;
550 struct net_device *net_dev = efx->net_dev;
551 int i, rc;
552
553 /* We can have one VI for each 8K region. However, until we
554 * use TX option descriptors we need two TX queues per channel.
555 */
556 efx->max_channels = min_t(unsigned int,
557 EFX_MAX_CHANNELS,
558 efx_ef10_mem_map_size(efx) /
559 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
560 efx->max_tx_channels = efx->max_channels;
561 if (WARN_ON(efx->max_channels == 0))
562 return -EIO;
563
564 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
565 if (!nic_data)
566 return -ENOMEM;
567 efx->nic_data = nic_data;
568
569 /* we assume later that we can copy from this buffer in dwords */
570 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
571
572 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
573 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
574 if (rc)
575 goto fail1;
576
577 /* Get the MC's warm boot count. In case it's rebooting right
578 * now, be prepared to retry.
579 */
580 i = 0;
581 for (;;) {
582 rc = efx_ef10_get_warm_boot_count(efx);
583 if (rc >= 0)
584 break;
585 if (++i == 5)
586 goto fail2;
587 ssleep(1);
588 }
589 nic_data->warm_boot_count = rc;
590
591 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
592
593 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
594
595 /* In case we're recovering from a crash (kexec), we want to
596 * cancel any outstanding request by the previous user of this
597 * function. We send a special message using the least
598 * significant bits of the 'high' (doorbell) register.
599 */
600 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
601
602 rc = efx_mcdi_init(efx);
603 if (rc)
604 goto fail2;
605
606 /* Reset (most) configuration for this function */
607 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
608 if (rc)
609 goto fail3;
610
611 /* Enable event logging */
612 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
613 if (rc)
614 goto fail3;
615
616 rc = device_create_file(&efx->pci_dev->dev,
617 &dev_attr_link_control_flag);
618 if (rc)
619 goto fail3;
620
621 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
622 if (rc)
623 goto fail4;
624
625 rc = efx_ef10_get_pf_index(efx);
626 if (rc)
627 goto fail5;
628
629 rc = efx_ef10_init_datapath_caps(efx);
630 if (rc < 0)
631 goto fail5;
632
633 efx->rx_packet_len_offset =
634 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
635
636 rc = efx_mcdi_port_get_number(efx);
637 if (rc < 0)
638 goto fail5;
639 efx->port_num = rc;
640 net_dev->dev_port = rc;
641
642 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
643 if (rc)
644 goto fail5;
645
646 rc = efx_ef10_get_timer_config(efx);
647 if (rc < 0)
648 goto fail5;
649
650 rc = efx_mcdi_mon_probe(efx);
651 if (rc && rc != -EPERM)
652 goto fail5;
653
654 efx_ptp_probe(efx, NULL);
655
656#ifdef CONFIG_SFC_SRIOV
657 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
658 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
659 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
660
661 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
662 } else
663#endif
664 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
665
666 INIT_LIST_HEAD(&nic_data->vlan_list);
667 mutex_init(&nic_data->vlan_lock);
668
669 /* Add unspecified VID to support VLAN filtering being disabled */
670 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
671 if (rc)
672 goto fail_add_vid_unspec;
673
674 /* If VLAN filtering is enabled, we need VID 0 to get untagged
675 * traffic. It is added automatically if 8021q module is loaded,
676 * but we can't rely on it since module may be not loaded.
677 */
678 rc = efx_ef10_add_vlan(efx, 0);
679 if (rc)
680 goto fail_add_vid_0;
681
682 return 0;
683
684fail_add_vid_0:
685 efx_ef10_cleanup_vlans(efx);
686fail_add_vid_unspec:
687 mutex_destroy(&nic_data->vlan_lock);
688 efx_ptp_remove(efx);
689 efx_mcdi_mon_remove(efx);
690fail5:
691 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
692fail4:
693 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
694fail3:
695 efx_mcdi_fini(efx);
696fail2:
697 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
698fail1:
699 kfree(nic_data);
700 efx->nic_data = NULL;
701 return rc;
702}
703
704static int efx_ef10_free_vis(struct efx_nic *efx)
705{
706 MCDI_DECLARE_BUF_ERR(outbuf);
707 size_t outlen;
708 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
709 outbuf, sizeof(outbuf), &outlen);
710
711 /* -EALREADY means nothing to free, so ignore */
712 if (rc == -EALREADY)
713 rc = 0;
714 if (rc)
715 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
716 rc);
717 return rc;
718}
719
720#ifdef EFX_USE_PIO
721
722static void efx_ef10_free_piobufs(struct efx_nic *efx)
723{
724 struct efx_ef10_nic_data *nic_data = efx->nic_data;
725 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
726 unsigned int i;
727 int rc;
728
729 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
730
731 for (i = 0; i < nic_data->n_piobufs; i++) {
732 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
733 nic_data->piobuf_handle[i]);
734 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
735 NULL, 0, NULL);
736 WARN_ON(rc);
737 }
738
739 nic_data->n_piobufs = 0;
740}
741
742static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
743{
744 struct efx_ef10_nic_data *nic_data = efx->nic_data;
745 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
746 unsigned int i;
747 size_t outlen;
748 int rc = 0;
749
750 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
751
752 for (i = 0; i < n; i++) {
753 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
754 outbuf, sizeof(outbuf), &outlen);
755 if (rc) {
756 /* Don't display the MC error if we didn't have space
757 * for a VF.
758 */
759 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
760 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
761 0, outbuf, outlen, rc);
762 break;
763 }
764 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
765 rc = -EIO;
766 break;
767 }
768 nic_data->piobuf_handle[i] =
769 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
770 netif_dbg(efx, probe, efx->net_dev,
771 "allocated PIO buffer %u handle %x\n", i,
772 nic_data->piobuf_handle[i]);
773 }
774
775 nic_data->n_piobufs = i;
776 if (rc)
777 efx_ef10_free_piobufs(efx);
778 return rc;
779}
780
781static int efx_ef10_link_piobufs(struct efx_nic *efx)
782{
783 struct efx_ef10_nic_data *nic_data = efx->nic_data;
784 _MCDI_DECLARE_BUF(inbuf,
785 max(MC_CMD_LINK_PIOBUF_IN_LEN,
786 MC_CMD_UNLINK_PIOBUF_IN_LEN));
787 struct efx_channel *channel;
788 struct efx_tx_queue *tx_queue;
789 unsigned int offset, index;
790 int rc;
791
792 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
793 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
794
795 memset(inbuf, 0, sizeof(inbuf));
796
797 /* Link a buffer to each VI in the write-combining mapping */
798 for (index = 0; index < nic_data->n_piobufs; ++index) {
799 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
800 nic_data->piobuf_handle[index]);
801 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
802 nic_data->pio_write_vi_base + index);
803 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
804 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
805 NULL, 0, NULL);
806 if (rc) {
807 netif_err(efx, drv, efx->net_dev,
808 "failed to link VI %u to PIO buffer %u (%d)\n",
809 nic_data->pio_write_vi_base + index, index,
810 rc);
811 goto fail;
812 }
813 netif_dbg(efx, probe, efx->net_dev,
814 "linked VI %u to PIO buffer %u\n",
815 nic_data->pio_write_vi_base + index, index);
816 }
817
818 /* Link a buffer to each TX queue */
819 efx_for_each_channel(channel, efx) {
820 efx_for_each_channel_tx_queue(tx_queue, channel) {
821 /* We assign the PIO buffers to queues in
822 * reverse order to allow for the following
823 * special case.
824 */
825 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
826 tx_queue->channel->channel - 1) *
827 efx_piobuf_size);
828 index = offset / ER_DZ_TX_PIOBUF_SIZE;
829 offset = offset % ER_DZ_TX_PIOBUF_SIZE;
830
831 /* When the host page size is 4K, the first
832 * host page in the WC mapping may be within
833 * the same VI page as the last TX queue. We
834 * can only link one buffer to each VI.
835 */
836 if (tx_queue->queue == nic_data->pio_write_vi_base) {
837 BUG_ON(index != 0);
838 rc = 0;
839 } else {
840 MCDI_SET_DWORD(inbuf,
841 LINK_PIOBUF_IN_PIOBUF_HANDLE,
842 nic_data->piobuf_handle[index]);
843 MCDI_SET_DWORD(inbuf,
844 LINK_PIOBUF_IN_TXQ_INSTANCE,
845 tx_queue->queue);
846 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
847 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
848 NULL, 0, NULL);
849 }
850
851 if (rc) {
852 /* This is non-fatal; the TX path just
853 * won't use PIO for this queue
854 */
855 netif_err(efx, drv, efx->net_dev,
856 "failed to link VI %u to PIO buffer %u (%d)\n",
857 tx_queue->queue, index, rc);
858 tx_queue->piobuf = NULL;
859 } else {
860 tx_queue->piobuf =
861 nic_data->pio_write_base +
862 index * EFX_VI_PAGE_SIZE + offset;
863 tx_queue->piobuf_offset = offset;
864 netif_dbg(efx, probe, efx->net_dev,
865 "linked VI %u to PIO buffer %u offset %x addr %p\n",
866 tx_queue->queue, index,
867 tx_queue->piobuf_offset,
868 tx_queue->piobuf);
869 }
870 }
871 }
872
873 return 0;
874
875fail:
876 while (index--) {
877 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
878 nic_data->pio_write_vi_base + index);
879 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
880 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
881 NULL, 0, NULL);
882 }
883 return rc;
884}
885
886static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
887{
888 struct efx_channel *channel;
889 struct efx_tx_queue *tx_queue;
890
891 /* All our existing PIO buffers went away */
892 efx_for_each_channel(channel, efx)
893 efx_for_each_channel_tx_queue(tx_queue, channel)
894 tx_queue->piobuf = NULL;
895}
896
897#else /* !EFX_USE_PIO */
898
899static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
900{
901 return n == 0 ? 0 : -ENOBUFS;
902}
903
904static int efx_ef10_link_piobufs(struct efx_nic *efx)
905{
906 return 0;
907}
908
909static void efx_ef10_free_piobufs(struct efx_nic *efx)
910{
911}
912
913static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
914{
915}
916
917#endif /* EFX_USE_PIO */
918
919static void efx_ef10_remove(struct efx_nic *efx)
920{
921 struct efx_ef10_nic_data *nic_data = efx->nic_data;
922 int rc;
923
924#ifdef CONFIG_SFC_SRIOV
925 struct efx_ef10_nic_data *nic_data_pf;
926 struct pci_dev *pci_dev_pf;
927 struct efx_nic *efx_pf;
928 struct ef10_vf *vf;
929
930 if (efx->pci_dev->is_virtfn) {
931 pci_dev_pf = efx->pci_dev->physfn;
932 if (pci_dev_pf) {
933 efx_pf = pci_get_drvdata(pci_dev_pf);
934 nic_data_pf = efx_pf->nic_data;
935 vf = nic_data_pf->vf + nic_data->vf_index;
936 vf->efx = NULL;
937 } else
938 netif_info(efx, drv, efx->net_dev,
939 "Could not get the PF id from VF\n");
940 }
941#endif
942
943 efx_ef10_cleanup_vlans(efx);
944 mutex_destroy(&nic_data->vlan_lock);
945
946 efx_ptp_remove(efx);
947
948 efx_mcdi_mon_remove(efx);
949
950 efx_ef10_rx_free_indir_table(efx);
951
952 if (nic_data->wc_membase)
953 iounmap(nic_data->wc_membase);
954
955 rc = efx_ef10_free_vis(efx);
956 WARN_ON(rc != 0);
957
958 if (!nic_data->must_restore_piobufs)
959 efx_ef10_free_piobufs(efx);
960
961 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
962 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
963
964 efx_mcdi_fini(efx);
965 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
966 kfree(nic_data);
967}
968
969static int efx_ef10_probe_pf(struct efx_nic *efx)
970{
971 return efx_ef10_probe(efx);
972}
973
974int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
975 u32 *port_flags, u32 *vadaptor_flags,
976 unsigned int *vlan_tags)
977{
978 struct efx_ef10_nic_data *nic_data = efx->nic_data;
979 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
980 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
981 size_t outlen;
982 int rc;
983
984 if (nic_data->datapath_caps &
985 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
986 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
987 port_id);
988
989 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
990 outbuf, sizeof(outbuf), &outlen);
991 if (rc)
992 return rc;
993
994 if (outlen < sizeof(outbuf)) {
995 rc = -EIO;
996 return rc;
997 }
998 }
999
1000 if (port_flags)
1001 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
1002 if (vadaptor_flags)
1003 *vadaptor_flags =
1004 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
1005 if (vlan_tags)
1006 *vlan_tags =
1007 MCDI_DWORD(outbuf,
1008 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
1009
1010 return 0;
1011}
1012
1013int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
1014{
1015 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
1016
1017 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
1018 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
1019 NULL, 0, NULL);
1020}
1021
1022int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
1023{
1024 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
1025
1026 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
1027 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
1028 NULL, 0, NULL);
1029}
1030
1031int efx_ef10_vport_add_mac(struct efx_nic *efx,
1032 unsigned int port_id, u8 *mac)
1033{
1034 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
1035
1036 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
1037 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
1038
1039 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
1040 sizeof(inbuf), NULL, 0, NULL);
1041}
1042
1043int efx_ef10_vport_del_mac(struct efx_nic *efx,
1044 unsigned int port_id, u8 *mac)
1045{
1046 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
1047
1048 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
1049 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
1050
1051 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
1052 sizeof(inbuf), NULL, 0, NULL);
1053}
1054
1055#ifdef CONFIG_SFC_SRIOV
1056static int efx_ef10_probe_vf(struct efx_nic *efx)
1057{
1058 int rc;
1059 struct pci_dev *pci_dev_pf;
1060
1061 /* If the parent PF has no VF data structure, it doesn't know about this
1062 * VF so fail probe. The VF needs to be re-created. This can happen
1063 * if the PF driver is unloaded while the VF is assigned to a guest.
1064 */
1065 pci_dev_pf = efx->pci_dev->physfn;
1066 if (pci_dev_pf) {
1067 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
1068 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
1069
1070 if (!nic_data_pf->vf) {
1071 netif_info(efx, drv, efx->net_dev,
1072 "The VF cannot link to its parent PF; "
1073 "please destroy and re-create the VF\n");
1074 return -EBUSY;
1075 }
1076 }
1077
1078 rc = efx_ef10_probe(efx);
1079 if (rc)
1080 return rc;
1081
1082 rc = efx_ef10_get_vf_index(efx);
1083 if (rc)
1084 goto fail;
1085
1086 if (efx->pci_dev->is_virtfn) {
1087 if (efx->pci_dev->physfn) {
1088 struct efx_nic *efx_pf =
1089 pci_get_drvdata(efx->pci_dev->physfn);
1090 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1091 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1092
1093 nic_data_p->vf[nic_data->vf_index].efx = efx;
1094 nic_data_p->vf[nic_data->vf_index].pci_dev =
1095 efx->pci_dev;
1096 } else
1097 netif_info(efx, drv, efx->net_dev,
1098 "Could not get the PF id from VF\n");
1099 }
1100
1101 return 0;
1102
1103fail:
1104 efx_ef10_remove(efx);
1105 return rc;
1106}
1107#else
1108static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1109{
1110 return 0;
1111}
1112#endif
1113
1114static int efx_ef10_alloc_vis(struct efx_nic *efx,
1115 unsigned int min_vis, unsigned int max_vis)
1116{
1117 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
1118 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
1119 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1120 size_t outlen;
1121 int rc;
1122
1123 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
1124 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
1125 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
1126 outbuf, sizeof(outbuf), &outlen);
1127 if (rc != 0)
1128 return rc;
1129
1130 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
1131 return -EIO;
1132
1133 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
1134 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
1135
1136 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
1137 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
1138 return 0;
1139}
1140
1141/* Note that the failure path of this function does not free
1142 * resources, as this will be done by efx_ef10_remove().
1143 */
1144static int efx_ef10_dimension_resources(struct efx_nic *efx)
1145{
1146 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1147 unsigned int uc_mem_map_size, wc_mem_map_size;
1148 unsigned int min_vis = max(EFX_TXQ_TYPES,
1149 efx_separate_tx_channels ? 2 : 1);
1150 unsigned int channel_vis, pio_write_vi_base, max_vis;
1151 void __iomem *membase;
1152 int rc;
1153
1154 channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
1155
1156#ifdef EFX_USE_PIO
1157 /* Try to allocate PIO buffers if wanted and if the full
1158 * number of PIO buffers would be sufficient to allocate one
1159 * copy-buffer per TX channel. Failure is non-fatal, as there
1160 * are only a small number of PIO buffers shared between all
1161 * functions of the controller.
1162 */
1163 if (efx_piobuf_size != 0 &&
1164 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
1165 efx->n_tx_channels) {
1166 unsigned int n_piobufs =
1167 DIV_ROUND_UP(efx->n_tx_channels,
1168 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
1169
1170 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
1171 if (rc)
1172 netif_err(efx, probe, efx->net_dev,
1173 "failed to allocate PIO buffers (%d)\n", rc);
1174 else
1175 netif_dbg(efx, probe, efx->net_dev,
1176 "allocated %u PIO buffers\n", n_piobufs);
1177 }
1178#else
1179 nic_data->n_piobufs = 0;
1180#endif
1181
1182 /* PIO buffers should be mapped with write-combining enabled,
1183 * and we want to make single UC and WC mappings rather than
1184 * several of each (in fact that's the only option if host
1185 * page size is >4K). So we may allocate some extra VIs just
1186 * for writing PIO buffers through.
1187 *
1188 * The UC mapping contains (channel_vis - 1) complete VIs and the
1189 * first half of the next VI. Then the WC mapping begins with
1190 * the second half of this last VI.
1191 */
1192 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
1193 ER_DZ_TX_PIOBUF);
1194 if (nic_data->n_piobufs) {
1195 /* pio_write_vi_base rounds down to give the number of complete
1196 * VIs inside the UC mapping.
1197 */
1198 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
1199 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1200 nic_data->n_piobufs) *
1201 EFX_VI_PAGE_SIZE) -
1202 uc_mem_map_size);
1203 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1204 } else {
1205 pio_write_vi_base = 0;
1206 wc_mem_map_size = 0;
1207 max_vis = channel_vis;
1208 }
1209
1210 /* In case the last attached driver failed to free VIs, do it now */
1211 rc = efx_ef10_free_vis(efx);
1212 if (rc != 0)
1213 return rc;
1214
1215 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1216 if (rc != 0)
1217 return rc;
1218
1219 if (nic_data->n_allocated_vis < channel_vis) {
1220 netif_info(efx, drv, efx->net_dev,
1221 "Could not allocate enough VIs to satisfy RSS"
1222 " requirements. Performance may not be optimal.\n");
1223 /* We didn't get the VIs to populate our channels.
1224 * We could keep what we got but then we'd have more
1225 * interrupts than we need.
1226 * Instead calculate new max_channels and restart
1227 */
1228 efx->max_channels = nic_data->n_allocated_vis;
1229 efx->max_tx_channels =
1230 nic_data->n_allocated_vis / EFX_TXQ_TYPES;
1231
1232 efx_ef10_free_vis(efx);
1233 return -EAGAIN;
1234 }
1235
1236 /* If we didn't get enough VIs to map all the PIO buffers, free the
1237 * PIO buffers
1238 */
1239 if (nic_data->n_piobufs &&
1240 nic_data->n_allocated_vis <
1241 pio_write_vi_base + nic_data->n_piobufs) {
1242 netif_dbg(efx, probe, efx->net_dev,
1243 "%u VIs are not sufficient to map %u PIO buffers\n",
1244 nic_data->n_allocated_vis, nic_data->n_piobufs);
1245 efx_ef10_free_piobufs(efx);
1246 }
1247
1248 /* Shrink the original UC mapping of the memory BAR */
1249 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
1250 if (!membase) {
1251 netif_err(efx, probe, efx->net_dev,
1252 "could not shrink memory BAR to %x\n",
1253 uc_mem_map_size);
1254 return -ENOMEM;
1255 }
1256 iounmap(efx->membase);
1257 efx->membase = membase;
1258
1259 /* Set up the WC mapping if needed */
1260 if (wc_mem_map_size) {
1261 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1262 uc_mem_map_size,
1263 wc_mem_map_size);
1264 if (!nic_data->wc_membase) {
1265 netif_err(efx, probe, efx->net_dev,
1266 "could not allocate WC mapping of size %x\n",
1267 wc_mem_map_size);
1268 return -ENOMEM;
1269 }
1270 nic_data->pio_write_vi_base = pio_write_vi_base;
1271 nic_data->pio_write_base =
1272 nic_data->wc_membase +
1273 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
1274 uc_mem_map_size);
1275
1276 rc = efx_ef10_link_piobufs(efx);
1277 if (rc)
1278 efx_ef10_free_piobufs(efx);
1279 }
1280
1281 netif_dbg(efx, probe, efx->net_dev,
1282 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1283 &efx->membase_phys, efx->membase, uc_mem_map_size,
1284 nic_data->wc_membase, wc_mem_map_size);
1285
1286 return 0;
1287}
1288
1289static int efx_ef10_init_nic(struct efx_nic *efx)
1290{
1291 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1292 int rc;
1293
1294 if (nic_data->must_check_datapath_caps) {
1295 rc = efx_ef10_init_datapath_caps(efx);
1296 if (rc)
1297 return rc;
1298 nic_data->must_check_datapath_caps = false;
1299 }
1300
1301 if (nic_data->must_realloc_vis) {
1302 /* We cannot let the number of VIs change now */
1303 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1304 nic_data->n_allocated_vis);
1305 if (rc)
1306 return rc;
1307 nic_data->must_realloc_vis = false;
1308 }
1309
1310 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1311 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1312 if (rc == 0) {
1313 rc = efx_ef10_link_piobufs(efx);
1314 if (rc)
1315 efx_ef10_free_piobufs(efx);
1316 }
1317
1318 /* Log an error on failure, but this is non-fatal */
1319 if (rc)
1320 netif_err(efx, drv, efx->net_dev,
1321 "failed to restore PIO buffers (%d)\n", rc);
1322 nic_data->must_restore_piobufs = false;
1323 }
1324
1325 /* don't fail init if RSS setup doesn't work */
1326 rc = efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
1327 efx->rss_active = (rc == 0);
1328
1329 return 0;
1330}
1331
1332static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1333{
1334 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1335#ifdef CONFIG_SFC_SRIOV
1336 unsigned int i;
1337#endif
1338
1339 /* All our allocations have been reset */
1340 nic_data->must_realloc_vis = true;
1341 nic_data->must_restore_filters = true;
1342 nic_data->must_restore_piobufs = true;
1343 efx_ef10_forget_old_piobufs(efx);
1344 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1345
1346 /* Driver-created vswitches and vports must be re-created */
1347 nic_data->must_probe_vswitching = true;
1348 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1349#ifdef CONFIG_SFC_SRIOV
1350 if (nic_data->vf)
1351 for (i = 0; i < efx->vf_count; i++)
1352 nic_data->vf[i].vport_id = 0;
1353#endif
1354}
1355
1356static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1357{
1358 if (reason == RESET_TYPE_MC_FAILURE)
1359 return RESET_TYPE_DATAPATH;
1360
1361 return efx_mcdi_map_reset_reason(reason);
1362}
1363
1364static int efx_ef10_map_reset_flags(u32 *flags)
1365{
1366 enum {
1367 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1368 ETH_RESET_SHARED_SHIFT),
1369 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1370 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1371 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1372 ETH_RESET_SHARED_SHIFT)
1373 };
1374
1375 /* We assume for now that our PCI function is permitted to
1376 * reset everything.
1377 */
1378
1379 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1380 *flags &= ~EF10_RESET_MC;
1381 return RESET_TYPE_WORLD;
1382 }
1383
1384 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1385 *flags &= ~EF10_RESET_PORT;
1386 return RESET_TYPE_ALL;
1387 }
1388
1389 /* no invisible reset implemented */
1390
1391 return -EINVAL;
1392}
1393
1394static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1395{
1396 int rc = efx_mcdi_reset(efx, reset_type);
1397
1398 /* Unprivileged functions return -EPERM, but need to return success
1399 * here so that the datapath is brought back up.
1400 */
1401 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1402 rc = 0;
1403
1404 /* If it was a port reset, trigger reallocation of MC resources.
1405 * Note that on an MC reset nothing needs to be done now because we'll
1406 * detect the MC reset later and handle it then.
1407 * For an FLR, we never get an MC reset event, but the MC has reset all
1408 * resources assigned to us, so we have to trigger reallocation now.
1409 */
1410 if ((reset_type == RESET_TYPE_ALL ||
1411 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
1412 efx_ef10_reset_mc_allocations(efx);
1413 return rc;
1414}
1415
1416#define EF10_DMA_STAT(ext_name, mcdi_name) \
1417 [EF10_STAT_ ## ext_name] = \
1418 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1419#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1420 [EF10_STAT_ ## int_name] = \
1421 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1422#define EF10_OTHER_STAT(ext_name) \
1423 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1424#define GENERIC_SW_STAT(ext_name) \
1425 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1426
1427static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
1428 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1429 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1430 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1431 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1432 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1433 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1434 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1435 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1436 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1437 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1438 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1439 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1440 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1441 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1442 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1443 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1444 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1445 EF10_OTHER_STAT(port_rx_good_bytes),
1446 EF10_OTHER_STAT(port_rx_bad_bytes),
1447 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1448 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1449 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1450 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1451 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1452 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1453 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1454 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1455 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1456 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1457 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1458 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1459 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1460 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1461 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1462 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1463 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1464 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1465 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1466 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1467 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1468 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
1469 GENERIC_SW_STAT(rx_nodesc_trunc),
1470 GENERIC_SW_STAT(rx_noskb_drops),
1471 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1472 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1473 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1474 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1475 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1476 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1477 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1478 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1479 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1480 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1481 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1482 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
1483 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1484 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1485 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1486 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1487 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1488 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1489 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1490 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1491 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1492 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1493 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1494 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1495 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1496 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1497 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1498 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1499 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1500 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
1501};
1502
1503#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1504 (1ULL << EF10_STAT_port_tx_packets) | \
1505 (1ULL << EF10_STAT_port_tx_pause) | \
1506 (1ULL << EF10_STAT_port_tx_unicast) | \
1507 (1ULL << EF10_STAT_port_tx_multicast) | \
1508 (1ULL << EF10_STAT_port_tx_broadcast) | \
1509 (1ULL << EF10_STAT_port_rx_bytes) | \
1510 (1ULL << \
1511 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1512 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1513 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1514 (1ULL << EF10_STAT_port_rx_packets) | \
1515 (1ULL << EF10_STAT_port_rx_good) | \
1516 (1ULL << EF10_STAT_port_rx_bad) | \
1517 (1ULL << EF10_STAT_port_rx_pause) | \
1518 (1ULL << EF10_STAT_port_rx_control) | \
1519 (1ULL << EF10_STAT_port_rx_unicast) | \
1520 (1ULL << EF10_STAT_port_rx_multicast) | \
1521 (1ULL << EF10_STAT_port_rx_broadcast) | \
1522 (1ULL << EF10_STAT_port_rx_lt64) | \
1523 (1ULL << EF10_STAT_port_rx_64) | \
1524 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1525 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1526 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1527 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1528 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1529 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1530 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1531 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1532 (1ULL << EF10_STAT_port_rx_overflow) | \
1533 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1534 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1535 (1ULL << GENERIC_STAT_rx_noskb_drops))
1536
1537/* On 7000 series NICs, these statistics are only provided by the 10G MAC.
1538 * For a 10G/40G switchable port we do not expose these because they might
1539 * not include all the packets they should.
1540 * On 8000 series NICs these statistics are always provided.
1541 */
1542#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1543 (1ULL << EF10_STAT_port_tx_lt64) | \
1544 (1ULL << EF10_STAT_port_tx_64) | \
1545 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1546 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1547 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1548 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1549 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1550 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1551
1552/* These statistics are only provided by the 40G MAC. For a 10G/40G
1553 * switchable port we do expose these because the errors will otherwise
1554 * be silent.
1555 */
1556#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1557 (1ULL << EF10_STAT_port_rx_length_error))
1558
1559/* These statistics are only provided if the firmware supports the
1560 * capability PM_AND_RXDP_COUNTERS.
1561 */
1562#define HUNT_PM_AND_RXDP_STAT_MASK ( \
1563 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1564 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1565 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1566 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1567 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1568 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1569 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1570 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1571 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1572 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1573 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1574 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1575
1576static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1577{
1578 u64 raw_mask = HUNT_COMMON_STAT_MASK;
1579 u32 port_caps = efx_mcdi_phy_get_caps(efx);
1580 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1581
1582 if (!(efx->mcdi->fn_flags &
1583 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1584 return 0;
1585
1586 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
1587 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1588 /* 8000 series have everything even at 40G */
1589 if (nic_data->datapath_caps2 &
1590 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN))
1591 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1592 } else {
1593 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1594 }
1595
1596 if (nic_data->datapath_caps &
1597 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1598 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1599
1600 return raw_mask;
1601}
1602
1603static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1604{
1605 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1606 u64 raw_mask[2];
1607
1608 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1609
1610 /* Only show vadaptor stats when EVB capability is present */
1611 if (nic_data->datapath_caps &
1612 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1613 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1614 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1615 } else {
1616 raw_mask[1] = 0;
1617 }
1618
1619#if BITS_PER_LONG == 64
1620 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
1621 mask[0] = raw_mask[0];
1622 mask[1] = raw_mask[1];
1623#else
1624 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
1625 mask[0] = raw_mask[0] & 0xffffffff;
1626 mask[1] = raw_mask[0] >> 32;
1627 mask[2] = raw_mask[1] & 0xffffffff;
1628#endif
1629}
1630
1631static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1632{
1633 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1634
1635 efx_ef10_get_stat_mask(efx, mask);
1636 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1637 mask, names);
1638}
1639
1640static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1641 struct rtnl_link_stats64 *core_stats)
1642{
1643 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1644 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1645 u64 *stats = nic_data->stats;
1646 size_t stats_count = 0, index;
1647
1648 efx_ef10_get_stat_mask(efx, mask);
1649
1650 if (full_stats) {
1651 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1652 if (efx_ef10_stat_desc[index].name) {
1653 *full_stats++ = stats[index];
1654 ++stats_count;
1655 }
1656 }
1657 }
1658
1659 if (!core_stats)
1660 return stats_count;
1661
1662 if (nic_data->datapath_caps &
1663 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1664 /* Use vadaptor stats. */
1665 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1666 stats[EF10_STAT_rx_multicast] +
1667 stats[EF10_STAT_rx_broadcast];
1668 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1669 stats[EF10_STAT_tx_multicast] +
1670 stats[EF10_STAT_tx_broadcast];
1671 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1672 stats[EF10_STAT_rx_multicast_bytes] +
1673 stats[EF10_STAT_rx_broadcast_bytes];
1674 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1675 stats[EF10_STAT_tx_multicast_bytes] +
1676 stats[EF10_STAT_tx_broadcast_bytes];
1677 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
1678 stats[GENERIC_STAT_rx_noskb_drops];
1679 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1680 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1681 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1682 core_stats->rx_errors = core_stats->rx_crc_errors;
1683 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
1684 } else {
1685 /* Use port stats. */
1686 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1687 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1688 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1689 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1690 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1691 stats[GENERIC_STAT_rx_nodesc_trunc] +
1692 stats[GENERIC_STAT_rx_noskb_drops];
1693 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1694 core_stats->rx_length_errors =
1695 stats[EF10_STAT_port_rx_gtjumbo] +
1696 stats[EF10_STAT_port_rx_length_error];
1697 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1698 core_stats->rx_frame_errors =
1699 stats[EF10_STAT_port_rx_align_error];
1700 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1701 core_stats->rx_errors = (core_stats->rx_length_errors +
1702 core_stats->rx_crc_errors +
1703 core_stats->rx_frame_errors);
1704 }
1705
1706 return stats_count;
1707}
1708
1709static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
1710{
1711 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1712 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1713 __le64 generation_start, generation_end;
1714 u64 *stats = nic_data->stats;
1715 __le64 *dma_stats;
1716
1717 efx_ef10_get_stat_mask(efx, mask);
1718
1719 dma_stats = efx->stats_buffer.addr;
1720
1721 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1722 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1723 return 0;
1724 rmb();
1725 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1726 stats, efx->stats_buffer.addr, false);
1727 rmb();
1728 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1729 if (generation_end != generation_start)
1730 return -EAGAIN;
1731
1732 /* Update derived statistics */
1733 efx_nic_fix_nodesc_drop_stat(efx,
1734 &stats[EF10_STAT_port_rx_nodesc_drops]);
1735 stats[EF10_STAT_port_rx_good_bytes] =
1736 stats[EF10_STAT_port_rx_bytes] -
1737 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1738 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1739 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
1740 efx_update_sw_stats(efx, stats);
1741 return 0;
1742}
1743
1744
1745static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1746 struct rtnl_link_stats64 *core_stats)
1747{
1748 int retry;
1749
1750 /* If we're unlucky enough to read statistics during the DMA, wait
1751 * up to 10ms for it to finish (typically takes <500us)
1752 */
1753 for (retry = 0; retry < 100; ++retry) {
1754 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
1755 break;
1756 udelay(100);
1757 }
1758
1759 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1760}
1761
1762static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1763{
1764 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1765 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1766 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1767 __le64 generation_start, generation_end;
1768 u64 *stats = nic_data->stats;
1769 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1770 struct efx_buffer stats_buf;
1771 __le64 *dma_stats;
1772 int rc;
1773
1774 spin_unlock_bh(&efx->stats_lock);
1775
1776 if (in_interrupt()) {
1777 /* If in atomic context, cannot update stats. Just update the
1778 * software stats and return so the caller can continue.
1779 */
1780 spin_lock_bh(&efx->stats_lock);
1781 efx_update_sw_stats(efx, stats);
1782 return 0;
1783 }
1784
1785 efx_ef10_get_stat_mask(efx, mask);
1786
1787 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
1788 if (rc) {
1789 spin_lock_bh(&efx->stats_lock);
1790 return rc;
1791 }
1792
1793 dma_stats = stats_buf.addr;
1794 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1795
1796 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1797 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
1798 MAC_STATS_IN_DMA, 1);
1799 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1800 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1801
1802 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1803 NULL, 0, NULL);
1804 spin_lock_bh(&efx->stats_lock);
1805 if (rc) {
1806 /* Expect ENOENT if DMA queues have not been set up */
1807 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1808 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1809 sizeof(inbuf), NULL, 0, rc);
1810 goto out;
1811 }
1812
1813 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1814 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1815 WARN_ON_ONCE(1);
1816 goto out;
1817 }
1818 rmb();
1819 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1820 stats, stats_buf.addr, false);
1821 rmb();
1822 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1823 if (generation_end != generation_start) {
1824 rc = -EAGAIN;
1825 goto out;
1826 }
1827
1828 efx_update_sw_stats(efx, stats);
1829out:
1830 efx_nic_free_buffer(efx, &stats_buf);
1831 return rc;
1832}
1833
1834static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1835 struct rtnl_link_stats64 *core_stats)
1836{
1837 if (efx_ef10_try_update_nic_stats_vf(efx))
1838 return 0;
1839
1840 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1841}
1842
1843static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1844{
1845 struct efx_nic *efx = channel->efx;
1846 unsigned int mode, usecs;
1847 efx_dword_t timer_cmd;
1848
1849 if (channel->irq_moderation_us) {
1850 mode = 3;
1851 usecs = channel->irq_moderation_us;
1852 } else {
1853 mode = 0;
1854 usecs = 0;
1855 }
1856
1857 if (EFX_EF10_WORKAROUND_61265(efx)) {
1858 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN);
1859 unsigned int ns = usecs * 1000;
1860
1861 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE,
1862 channel->channel);
1863 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns);
1864 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns);
1865 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode);
1866
1867 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR,
1868 inbuf, sizeof(inbuf), 0, NULL, 0);
1869 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
1870 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1871
1872 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1873 EFE_DD_EVQ_IND_TIMER_FLAGS,
1874 ERF_DD_EVQ_IND_TIMER_MODE, mode,
1875 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
1876 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1877 channel->channel);
1878 } else {
1879 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1880
1881 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1882 ERF_DZ_TC_TIMER_VAL, ticks);
1883 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1884 channel->channel);
1885 }
1886}
1887
1888static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1889 struct ethtool_wolinfo *wol) {}
1890
1891static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1892{
1893 return -EOPNOTSUPP;
1894}
1895
1896static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1897{
1898 wol->supported = 0;
1899 wol->wolopts = 0;
1900 memset(&wol->sopass, 0, sizeof(wol->sopass));
1901}
1902
1903static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1904{
1905 if (type != 0)
1906 return -EINVAL;
1907 return 0;
1908}
1909
1910static void efx_ef10_mcdi_request(struct efx_nic *efx,
1911 const efx_dword_t *hdr, size_t hdr_len,
1912 const efx_dword_t *sdu, size_t sdu_len)
1913{
1914 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1915 u8 *pdu = nic_data->mcdi_buf.addr;
1916
1917 memcpy(pdu, hdr, hdr_len);
1918 memcpy(pdu + hdr_len, sdu, sdu_len);
1919 wmb();
1920
1921 /* The hardware provides 'low' and 'high' (doorbell) registers
1922 * for passing the 64-bit address of an MCDI request to
1923 * firmware. However the dwords are swapped by firmware. The
1924 * least significant bits of the doorbell are then 0 for all
1925 * MCDI requests due to alignment.
1926 */
1927 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1928 ER_DZ_MC_DB_LWRD);
1929 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1930 ER_DZ_MC_DB_HWRD);
1931}
1932
1933static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1934{
1935 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1936 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1937
1938 rmb();
1939 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1940}
1941
1942static void
1943efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1944 size_t offset, size_t outlen)
1945{
1946 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1947 const u8 *pdu = nic_data->mcdi_buf.addr;
1948
1949 memcpy(outbuf, pdu + offset, outlen);
1950}
1951
1952static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
1953{
1954 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1955
1956 /* All our allocations have been reset */
1957 efx_ef10_reset_mc_allocations(efx);
1958
1959 /* The datapath firmware might have been changed */
1960 nic_data->must_check_datapath_caps = true;
1961
1962 /* MAC statistics have been cleared on the NIC; clear the local
1963 * statistic that we update with efx_update_diff_stat().
1964 */
1965 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
1966}
1967
1968static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1969{
1970 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1971 int rc;
1972
1973 rc = efx_ef10_get_warm_boot_count(efx);
1974 if (rc < 0) {
1975 /* The firmware is presumably in the process of
1976 * rebooting. However, we are supposed to report each
1977 * reboot just once, so we must only do that once we
1978 * can read and store the updated warm boot count.
1979 */
1980 return 0;
1981 }
1982
1983 if (rc == nic_data->warm_boot_count)
1984 return 0;
1985
1986 nic_data->warm_boot_count = rc;
1987 efx_ef10_mcdi_reboot_detected(efx);
1988
1989 return -EIO;
1990}
1991
1992/* Handle an MSI interrupt
1993 *
1994 * Handle an MSI hardware interrupt. This routine schedules event
1995 * queue processing. No interrupt acknowledgement cycle is necessary.
1996 * Also, we never need to check that the interrupt is for us, since
1997 * MSI interrupts cannot be shared.
1998 */
1999static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
2000{
2001 struct efx_msi_context *context = dev_id;
2002 struct efx_nic *efx = context->efx;
2003
2004 netif_vdbg(efx, intr, efx->net_dev,
2005 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
2006
2007 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
2008 /* Note test interrupts */
2009 if (context->index == efx->irq_level)
2010 efx->last_irq_cpu = raw_smp_processor_id();
2011
2012 /* Schedule processing of the channel */
2013 efx_schedule_channel_irq(efx->channel[context->index]);
2014 }
2015
2016 return IRQ_HANDLED;
2017}
2018
2019static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
2020{
2021 struct efx_nic *efx = dev_id;
2022 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
2023 struct efx_channel *channel;
2024 efx_dword_t reg;
2025 u32 queues;
2026
2027 /* Read the ISR which also ACKs the interrupts */
2028 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR);
2029 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
2030
2031 if (queues == 0)
2032 return IRQ_NONE;
2033
2034 if (likely(soft_enabled)) {
2035 /* Note test interrupts */
2036 if (queues & (1U << efx->irq_level))
2037 efx->last_irq_cpu = raw_smp_processor_id();
2038
2039 efx_for_each_channel(channel, efx) {
2040 if (queues & 1)
2041 efx_schedule_channel_irq(channel);
2042 queues >>= 1;
2043 }
2044 }
2045
2046 netif_vdbg(efx, intr, efx->net_dev,
2047 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
2048 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
2049
2050 return IRQ_HANDLED;
2051}
2052
2053static int efx_ef10_irq_test_generate(struct efx_nic *efx)
2054{
2055 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
2056
2057 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true,
2058 NULL) == 0)
2059 return -ENOTSUPP;
2060
2061 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
2062
2063 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
2064 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
2065 inbuf, sizeof(inbuf), NULL, 0, NULL);
2066}
2067
2068static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
2069{
2070 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
2071 (tx_queue->ptr_mask + 1) *
2072 sizeof(efx_qword_t),
2073 GFP_KERNEL);
2074}
2075
2076/* This writes to the TX_DESC_WPTR and also pushes data */
2077static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
2078 const efx_qword_t *txd)
2079{
2080 unsigned int write_ptr;
2081 efx_oword_t reg;
2082
2083 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2084 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
2085 reg.qword[0] = *txd;
2086 efx_writeo_page(tx_queue->efx, ®,
2087 ER_DZ_TX_DESC_UPD, tx_queue->queue);
2088}
2089
2090/* Add Firmware-Assisted TSO v2 option descriptors to a queue.
2091 */
2092static int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue,
2093 struct sk_buff *skb,
2094 bool *data_mapped)
2095{
2096 struct efx_tx_buffer *buffer;
2097 struct tcphdr *tcp;
2098 struct iphdr *ip;
2099
2100 u16 ipv4_id;
2101 u32 seqnum;
2102 u32 mss;
2103
2104 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2);
2105
2106 mss = skb_shinfo(skb)->gso_size;
2107
2108 if (unlikely(mss < 4)) {
2109 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss);
2110 return -EINVAL;
2111 }
2112
2113 ip = ip_hdr(skb);
2114 if (ip->version == 4) {
2115 /* Modify IPv4 header if needed. */
2116 ip->tot_len = 0;
2117 ip->check = 0;
2118 ipv4_id = ip->id;
2119 } else {
2120 /* Modify IPv6 header if needed. */
2121 struct ipv6hdr *ipv6 = ipv6_hdr(skb);
2122
2123 ipv6->payload_len = 0;
2124 ipv4_id = 0;
2125 }
2126
2127 tcp = tcp_hdr(skb);
2128 seqnum = ntohl(tcp->seq);
2129
2130 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2131
2132 buffer->flags = EFX_TX_BUF_OPTION;
2133 buffer->len = 0;
2134 buffer->unmap_len = 0;
2135 EFX_POPULATE_QWORD_5(buffer->option,
2136 ESF_DZ_TX_DESC_IS_OPT, 1,
2137 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2138 ESF_DZ_TX_TSO_OPTION_TYPE,
2139 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
2140 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
2141 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum
2142 );
2143 ++tx_queue->insert_count;
2144
2145 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2146
2147 buffer->flags = EFX_TX_BUF_OPTION;
2148 buffer->len = 0;
2149 buffer->unmap_len = 0;
2150 EFX_POPULATE_QWORD_4(buffer->option,
2151 ESF_DZ_TX_DESC_IS_OPT, 1,
2152 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2153 ESF_DZ_TX_TSO_OPTION_TYPE,
2154 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
2155 ESF_DZ_TX_TSO_TCP_MSS, mss
2156 );
2157 ++tx_queue->insert_count;
2158
2159 return 0;
2160}
2161
2162static u32 efx_ef10_tso_versions(struct efx_nic *efx)
2163{
2164 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2165 u32 tso_versions = 0;
2166
2167 if (nic_data->datapath_caps &
2168 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))
2169 tso_versions |= BIT(1);
2170 if (nic_data->datapath_caps2 &
2171 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))
2172 tso_versions |= BIT(2);
2173 return tso_versions;
2174}
2175
2176static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
2177{
2178 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2179 EFX_BUF_SIZE));
2180 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
2181 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
2182 struct efx_channel *channel = tx_queue->channel;
2183 struct efx_nic *efx = tx_queue->efx;
2184 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2185 bool tso_v2 = false;
2186 size_t inlen;
2187 dma_addr_t dma_addr;
2188 efx_qword_t *txd;
2189 int rc;
2190 int i;
2191 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
2192
2193 /* TSOv2 is a limited resource that can only be configured on a limited
2194 * number of queues. TSO without checksum offload is not really a thing,
2195 * so we only enable it for those queues.
2196 */
2197 if (csum_offload && (nic_data->datapath_caps2 &
2198 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))) {
2199 tso_v2 = true;
2200 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n",
2201 channel->channel);
2202 }
2203
2204 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
2205 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
2206 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
2207 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
2208 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
2209 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
2210
2211 dma_addr = tx_queue->txd.buf.dma_addr;
2212
2213 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
2214 tx_queue->queue, entries, (u64)dma_addr);
2215
2216 for (i = 0; i < entries; ++i) {
2217 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
2218 dma_addr += EFX_BUF_SIZE;
2219 }
2220
2221 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
2222
2223 do {
2224 MCDI_POPULATE_DWORD_3(inbuf, INIT_TXQ_IN_FLAGS,
2225 /* This flag was removed from mcdi_pcol.h for
2226 * the non-_EXT version of INIT_TXQ. However,
2227 * firmware still honours it.
2228 */
2229 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, tso_v2,
2230 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
2231 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
2232
2233 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
2234 NULL, 0, NULL);
2235 if (rc == -ENOSPC && tso_v2) {
2236 /* Retry without TSOv2 if we're short on contexts. */
2237 tso_v2 = false;
2238 netif_warn(efx, probe, efx->net_dev,
2239 "TSOv2 context not available to segment in hardware. TCP performance may be reduced.\n");
2240 } else if (rc) {
2241 efx_mcdi_display_error(efx, MC_CMD_INIT_TXQ,
2242 MC_CMD_INIT_TXQ_EXT_IN_LEN,
2243 NULL, 0, rc);
2244 goto fail;
2245 }
2246 } while (rc);
2247
2248 /* A previous user of this TX queue might have set us up the
2249 * bomb by writing a descriptor to the TX push collector but
2250 * not the doorbell. (Each collector belongs to a port, not a
2251 * queue or function, so cannot easily be reset.) We must
2252 * attempt to push a no-op descriptor in its place.
2253 */
2254 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2255 tx_queue->insert_count = 1;
2256 txd = efx_tx_desc(tx_queue, 0);
2257 EFX_POPULATE_QWORD_4(*txd,
2258 ESF_DZ_TX_DESC_IS_OPT, true,
2259 ESF_DZ_TX_OPTION_TYPE,
2260 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2261 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2262 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
2263 tx_queue->write_count = 1;
2264
2265 if (tso_v2) {
2266 tx_queue->handle_tso = efx_ef10_tx_tso_desc;
2267 tx_queue->tso_version = 2;
2268 } else if (nic_data->datapath_caps &
2269 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
2270 tx_queue->tso_version = 1;
2271 }
2272
2273 wmb();
2274 efx_ef10_push_tx_desc(tx_queue, txd);
2275
2276 return;
2277
2278fail:
2279 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2280 tx_queue->queue);
2281}
2282
2283static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
2284{
2285 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
2286 MCDI_DECLARE_BUF_ERR(outbuf);
2287 struct efx_nic *efx = tx_queue->efx;
2288 size_t outlen;
2289 int rc;
2290
2291 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
2292 tx_queue->queue);
2293
2294 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
2295 outbuf, sizeof(outbuf), &outlen);
2296
2297 if (rc && rc != -EALREADY)
2298 goto fail;
2299
2300 return;
2301
2302fail:
2303 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
2304 outbuf, outlen, rc);
2305}
2306
2307static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
2308{
2309 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
2310}
2311
2312/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2313static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2314{
2315 unsigned int write_ptr;
2316 efx_dword_t reg;
2317
2318 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2319 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2320 efx_writed_page(tx_queue->efx, ®,
2321 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2322}
2323
2324#define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff
2325
2326static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue,
2327 dma_addr_t dma_addr, unsigned int len)
2328{
2329 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) {
2330 /* If we need to break across multiple descriptors we should
2331 * stop at a page boundary. This assumes the length limit is
2332 * greater than the page size.
2333 */
2334 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN;
2335
2336 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE);
2337 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr;
2338 }
2339
2340 return len;
2341}
2342
2343static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2344{
2345 unsigned int old_write_count = tx_queue->write_count;
2346 struct efx_tx_buffer *buffer;
2347 unsigned int write_ptr;
2348 efx_qword_t *txd;
2349
2350 tx_queue->xmit_more_available = false;
2351 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2352 return;
2353
2354 do {
2355 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2356 buffer = &tx_queue->buffer[write_ptr];
2357 txd = efx_tx_desc(tx_queue, write_ptr);
2358 ++tx_queue->write_count;
2359
2360 /* Create TX descriptor ring entry */
2361 if (buffer->flags & EFX_TX_BUF_OPTION) {
2362 *txd = buffer->option;
2363 } else {
2364 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2365 EFX_POPULATE_QWORD_3(
2366 *txd,
2367 ESF_DZ_TX_KER_CONT,
2368 buffer->flags & EFX_TX_BUF_CONT,
2369 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2370 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2371 }
2372 } while (tx_queue->write_count != tx_queue->insert_count);
2373
2374 wmb(); /* Ensure descriptors are written before they are fetched */
2375
2376 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2377 txd = efx_tx_desc(tx_queue,
2378 old_write_count & tx_queue->ptr_mask);
2379 efx_ef10_push_tx_desc(tx_queue, txd);
2380 ++tx_queue->pushes;
2381 } else {
2382 efx_ef10_notify_tx_desc(tx_queue);
2383 }
2384}
2385
2386#define RSS_MODE_HASH_ADDRS (1 << RSS_MODE_HASH_SRC_ADDR_LBN |\
2387 1 << RSS_MODE_HASH_DST_ADDR_LBN)
2388#define RSS_MODE_HASH_PORTS (1 << RSS_MODE_HASH_SRC_PORT_LBN |\
2389 1 << RSS_MODE_HASH_DST_PORT_LBN)
2390#define RSS_CONTEXT_FLAGS_DEFAULT (1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN |\
2391 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN |\
2392 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN |\
2393 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN |\
2394 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN |\
2395 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN |\
2396 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN |\
2397 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN |\
2398 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN |\
2399 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN)
2400
2401static int efx_ef10_get_rss_flags(struct efx_nic *efx, u32 context, u32 *flags)
2402{
2403 /* Firmware had a bug (sfc bug 61952) where it would not actually
2404 * fill in the flags field in the response to MC_CMD_RSS_CONTEXT_GET_FLAGS.
2405 * This meant that it would always contain whatever was previously
2406 * in the MCDI buffer. Fortunately, all firmware versions with
2407 * this bug have the same default flags value for a newly-allocated
2408 * RSS context, and the only time we want to get the flags is just
2409 * after allocating. Moreover, the response has a 32-bit hole
2410 * where the context ID would be in the request, so we can use an
2411 * overlength buffer in the request and pre-fill the flags field
2412 * with what we believe the default to be. Thus if the firmware
2413 * has the bug, it will leave our pre-filled value in the flags
2414 * field of the response, and we will get the right answer.
2415 *
2416 * However, this does mean that this function should NOT be used if
2417 * the RSS context flags might not be their defaults - it is ONLY
2418 * reliably correct for a newly-allocated RSS context.
2419 */
2420 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2421 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2422 size_t outlen;
2423 int rc;
2424
2425 /* Check we have a hole for the context ID */
2426 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN != MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST);
2427 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID, context);
2428 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS,
2429 RSS_CONTEXT_FLAGS_DEFAULT);
2430 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_FLAGS, inbuf,
2431 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
2432 if (rc == 0) {
2433 if (outlen < MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN)
2434 rc = -EIO;
2435 else
2436 *flags = MCDI_DWORD(outbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS);
2437 }
2438 return rc;
2439}
2440
2441/* Attempt to enable 4-tuple UDP hashing on the specified RSS context.
2442 * If we fail, we just leave the RSS context at its default hash settings,
2443 * which is safe but may slightly reduce performance.
2444 * Defaults are 4-tuple for TCP and 2-tuple for UDP and other-IP, so we
2445 * just need to set the UDP ports flags (for both IP versions).
2446 */
2447static void efx_ef10_set_rss_flags(struct efx_nic *efx, u32 context)
2448{
2449 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN);
2450 u32 flags;
2451
2452 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN != 0);
2453
2454 if (efx_ef10_get_rss_flags(efx, context, &flags) != 0)
2455 return;
2456 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID, context);
2457 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN;
2458 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN;
2459 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_FLAGS, flags);
2460 if (!efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_FLAGS, inbuf, sizeof(inbuf),
2461 NULL, 0, NULL))
2462 /* Succeeded, so UDP 4-tuple is now enabled */
2463 efx->rx_hash_udp_4tuple = true;
2464}
2465
2466static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
2467 bool exclusive, unsigned *context_size)
2468{
2469 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
2470 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
2471 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2472 size_t outlen;
2473 int rc;
2474 u32 alloc_type = exclusive ?
2475 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
2476 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
2477 unsigned rss_spread = exclusive ?
2478 efx->rss_spread :
2479 min(rounddown_pow_of_two(efx->rss_spread),
2480 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
2481
2482 if (!exclusive && rss_spread == 1) {
2483 *context = EFX_EF10_RSS_CONTEXT_INVALID;
2484 if (context_size)
2485 *context_size = 1;
2486 return 0;
2487 }
2488
2489 if (nic_data->datapath_caps &
2490 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
2491 return -EOPNOTSUPP;
2492
2493 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
2494 nic_data->vport_id);
2495 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
2496 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
2497
2498 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
2499 outbuf, sizeof(outbuf), &outlen);
2500 if (rc != 0)
2501 return rc;
2502
2503 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
2504 return -EIO;
2505
2506 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
2507
2508 if (context_size)
2509 *context_size = rss_spread;
2510
2511 if (nic_data->datapath_caps &
2512 1 << MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN)
2513 efx_ef10_set_rss_flags(efx, *context);
2514
2515 return 0;
2516}
2517
2518static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
2519{
2520 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
2521 int rc;
2522
2523 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
2524 context);
2525
2526 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
2527 NULL, 0, NULL);
2528 WARN_ON(rc != 0);
2529}
2530
2531static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
2532 const u32 *rx_indir_table)
2533{
2534 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
2535 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
2536 int i, rc;
2537
2538 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
2539 context);
2540 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2541 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
2542
2543 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
2544 MCDI_PTR(tablebuf,
2545 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
2546 (u8) rx_indir_table[i];
2547
2548 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
2549 sizeof(tablebuf), NULL, 0, NULL);
2550 if (rc != 0)
2551 return rc;
2552
2553 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
2554 context);
2555 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2556 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2557 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2558 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
2559 efx->rx_hash_key[i];
2560
2561 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
2562 sizeof(keybuf), NULL, 0, NULL);
2563}
2564
2565static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
2566{
2567 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2568
2569 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2570 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
2571 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
2572}
2573
2574static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2575 unsigned *context_size)
2576{
2577 u32 new_rx_rss_context;
2578 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2579 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2580 false, context_size);
2581
2582 if (rc != 0)
2583 return rc;
2584
2585 nic_data->rx_rss_context = new_rx_rss_context;
2586 nic_data->rx_rss_context_exclusive = false;
2587 efx_set_default_rx_indir_table(efx);
2588 return 0;
2589}
2590
2591static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2592 const u32 *rx_indir_table)
2593{
2594 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2595 int rc;
2596 u32 new_rx_rss_context;
2597
2598 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2599 !nic_data->rx_rss_context_exclusive) {
2600 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2601 true, NULL);
2602 if (rc == -EOPNOTSUPP)
2603 return rc;
2604 else if (rc != 0)
2605 goto fail1;
2606 } else {
2607 new_rx_rss_context = nic_data->rx_rss_context;
2608 }
2609
2610 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
2611 rx_indir_table);
2612 if (rc != 0)
2613 goto fail2;
2614
2615 if (nic_data->rx_rss_context != new_rx_rss_context)
2616 efx_ef10_rx_free_indir_table(efx);
2617 nic_data->rx_rss_context = new_rx_rss_context;
2618 nic_data->rx_rss_context_exclusive = true;
2619 if (rx_indir_table != efx->rx_indir_table)
2620 memcpy(efx->rx_indir_table, rx_indir_table,
2621 sizeof(efx->rx_indir_table));
2622 return 0;
2623
2624fail2:
2625 if (new_rx_rss_context != nic_data->rx_rss_context)
2626 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2627fail1:
2628 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2629 return rc;
2630}
2631
2632static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
2633 const u32 *rx_indir_table)
2634{
2635 int rc;
2636
2637 if (efx->rss_spread == 1)
2638 return 0;
2639
2640 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
2641
2642 if (rc == -ENOBUFS && !user) {
2643 unsigned context_size;
2644 bool mismatch = false;
2645 size_t i;
2646
2647 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2648 i++)
2649 mismatch = rx_indir_table[i] !=
2650 ethtool_rxfh_indir_default(i, efx->rss_spread);
2651
2652 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2653 if (rc == 0) {
2654 if (context_size != efx->rss_spread)
2655 netif_warn(efx, probe, efx->net_dev,
2656 "Could not allocate an exclusive RSS"
2657 " context; allocated a shared one of"
2658 " different size."
2659 " Wanted %u, got %u.\n",
2660 efx->rss_spread, context_size);
2661 else if (mismatch)
2662 netif_warn(efx, probe, efx->net_dev,
2663 "Could not allocate an exclusive RSS"
2664 " context; allocated a shared one but"
2665 " could not apply custom"
2666 " indirection.\n");
2667 else
2668 netif_info(efx, probe, efx->net_dev,
2669 "Could not allocate an exclusive RSS"
2670 " context; allocated a shared one.\n");
2671 }
2672 }
2673 return rc;
2674}
2675
2676static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2677 const u32 *rx_indir_table
2678 __attribute__ ((unused)))
2679{
2680 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2681
2682 if (user)
2683 return -EOPNOTSUPP;
2684 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2685 return 0;
2686 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
2687}
2688
2689static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2690{
2691 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2692 (rx_queue->ptr_mask + 1) *
2693 sizeof(efx_qword_t),
2694 GFP_KERNEL);
2695}
2696
2697static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2698{
2699 MCDI_DECLARE_BUF(inbuf,
2700 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2701 EFX_BUF_SIZE));
2702 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2703 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2704 struct efx_nic *efx = rx_queue->efx;
2705 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2706 size_t inlen;
2707 dma_addr_t dma_addr;
2708 int rc;
2709 int i;
2710 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
2711
2712 rx_queue->scatter_n = 0;
2713 rx_queue->scatter_len = 0;
2714
2715 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2716 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2717 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2718 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2719 efx_rx_queue_index(rx_queue));
2720 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2721 INIT_RXQ_IN_FLAG_PREFIX, 1,
2722 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
2723 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
2724 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
2725
2726 dma_addr = rx_queue->rxd.buf.dma_addr;
2727
2728 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2729 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2730
2731 for (i = 0; i < entries; ++i) {
2732 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2733 dma_addr += EFX_BUF_SIZE;
2734 }
2735
2736 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2737
2738 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
2739 NULL, 0, NULL);
2740 if (rc)
2741 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2742 efx_rx_queue_index(rx_queue));
2743}
2744
2745static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2746{
2747 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
2748 MCDI_DECLARE_BUF_ERR(outbuf);
2749 struct efx_nic *efx = rx_queue->efx;
2750 size_t outlen;
2751 int rc;
2752
2753 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2754 efx_rx_queue_index(rx_queue));
2755
2756 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
2757 outbuf, sizeof(outbuf), &outlen);
2758
2759 if (rc && rc != -EALREADY)
2760 goto fail;
2761
2762 return;
2763
2764fail:
2765 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2766 outbuf, outlen, rc);
2767}
2768
2769static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2770{
2771 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2772}
2773
2774/* This creates an entry in the RX descriptor queue */
2775static inline void
2776efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2777{
2778 struct efx_rx_buffer *rx_buf;
2779 efx_qword_t *rxd;
2780
2781 rxd = efx_rx_desc(rx_queue, index);
2782 rx_buf = efx_rx_buffer(rx_queue, index);
2783 EFX_POPULATE_QWORD_2(*rxd,
2784 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2785 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2786}
2787
2788static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2789{
2790 struct efx_nic *efx = rx_queue->efx;
2791 unsigned int write_count;
2792 efx_dword_t reg;
2793
2794 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2795 write_count = rx_queue->added_count & ~7;
2796 if (rx_queue->notified_count == write_count)
2797 return;
2798
2799 do
2800 efx_ef10_build_rx_desc(
2801 rx_queue,
2802 rx_queue->notified_count & rx_queue->ptr_mask);
2803 while (++rx_queue->notified_count != write_count);
2804
2805 wmb();
2806 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2807 write_count & rx_queue->ptr_mask);
2808 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD,
2809 efx_rx_queue_index(rx_queue));
2810}
2811
2812static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2813
2814static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2815{
2816 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2817 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2818 efx_qword_t event;
2819
2820 EFX_POPULATE_QWORD_2(event,
2821 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2822 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2823
2824 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2825
2826 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2827 * already swapped the data to little-endian order.
2828 */
2829 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2830 sizeof(efx_qword_t));
2831
2832 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2833 inbuf, sizeof(inbuf), 0,
2834 efx_ef10_rx_defer_refill_complete, 0);
2835}
2836
2837static void
2838efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2839 int rc, efx_dword_t *outbuf,
2840 size_t outlen_actual)
2841{
2842 /* nothing to do */
2843}
2844
2845static int efx_ef10_ev_probe(struct efx_channel *channel)
2846{
2847 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2848 (channel->eventq_mask + 1) *
2849 sizeof(efx_qword_t),
2850 GFP_KERNEL);
2851}
2852
2853static void efx_ef10_ev_fini(struct efx_channel *channel)
2854{
2855 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2856 MCDI_DECLARE_BUF_ERR(outbuf);
2857 struct efx_nic *efx = channel->efx;
2858 size_t outlen;
2859 int rc;
2860
2861 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2862
2863 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
2864 outbuf, sizeof(outbuf), &outlen);
2865
2866 if (rc && rc != -EALREADY)
2867 goto fail;
2868
2869 return;
2870
2871fail:
2872 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2873 outbuf, outlen, rc);
2874}
2875
2876static int efx_ef10_ev_init(struct efx_channel *channel)
2877{
2878 MCDI_DECLARE_BUF(inbuf,
2879 MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
2880 EFX_BUF_SIZE));
2881 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN);
2882 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
2883 struct efx_nic *efx = channel->efx;
2884 struct efx_ef10_nic_data *nic_data;
2885 size_t inlen, outlen;
2886 unsigned int enabled, implemented;
2887 dma_addr_t dma_addr;
2888 int rc;
2889 int i;
2890
2891 nic_data = efx->nic_data;
2892
2893 /* Fill event queue with all ones (i.e. empty events) */
2894 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
2895
2896 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
2897 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
2898 /* INIT_EVQ expects index in vector table, not absolute */
2899 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
2900 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
2901 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
2902 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
2903 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
2904 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
2905 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
2906 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
2907
2908 if (nic_data->datapath_caps2 &
2909 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN) {
2910 /* Use the new generic approach to specifying event queue
2911 * configuration, requesting lower latency or higher throughput.
2912 * The options that actually get used appear in the output.
2913 */
2914 MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS,
2915 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1,
2916 INIT_EVQ_V2_IN_FLAG_TYPE,
2917 MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO);
2918 } else {
2919 bool cut_thru = !(nic_data->datapath_caps &
2920 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
2921
2922 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
2923 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
2924 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
2925 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
2926 INIT_EVQ_IN_FLAG_CUT_THRU, cut_thru);
2927 }
2928
2929 dma_addr = channel->eventq.buf.dma_addr;
2930 for (i = 0; i < entries; ++i) {
2931 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
2932 dma_addr += EFX_BUF_SIZE;
2933 }
2934
2935 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
2936
2937 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
2938 outbuf, sizeof(outbuf), &outlen);
2939
2940 if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN)
2941 netif_dbg(efx, drv, efx->net_dev,
2942 "Channel %d using event queue flags %08x\n",
2943 channel->channel,
2944 MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS));
2945
2946 /* IRQ return is ignored */
2947 if (channel->channel || rc)
2948 return rc;
2949
2950 /* Successfully created event queue on channel 0 */
2951 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
2952 if (rc == -ENOSYS) {
2953 /* GET_WORKAROUNDS was implemented before this workaround,
2954 * thus it must be unavailable in this firmware.
2955 */
2956 nic_data->workaround_26807 = false;
2957 rc = 0;
2958 } else if (rc) {
2959 goto fail;
2960 } else {
2961 nic_data->workaround_26807 =
2962 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
2963
2964 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
2965 !nic_data->workaround_26807) {
2966 unsigned int flags;
2967
2968 rc = efx_mcdi_set_workaround(efx,
2969 MC_CMD_WORKAROUND_BUG26807,
2970 true, &flags);
2971
2972 if (!rc) {
2973 if (flags &
2974 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
2975 netif_info(efx, drv, efx->net_dev,
2976 "other functions on NIC have been reset\n");
2977
2978 /* With MCFW v4.6.x and earlier, the
2979 * boot count will have incremented,
2980 * so re-read the warm_boot_count
2981 * value now to ensure this function
2982 * doesn't think it has changed next
2983 * time it checks.
2984 */
2985 rc = efx_ef10_get_warm_boot_count(efx);
2986 if (rc >= 0) {
2987 nic_data->warm_boot_count = rc;
2988 rc = 0;
2989 }
2990 }
2991 nic_data->workaround_26807 = true;
2992 } else if (rc == -EPERM) {
2993 rc = 0;
2994 }
2995 }
2996 }
2997
2998 if (!rc)
2999 return 0;
3000
3001fail:
3002 efx_ef10_ev_fini(channel);
3003 return rc;
3004}
3005
3006static void efx_ef10_ev_remove(struct efx_channel *channel)
3007{
3008 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
3009}
3010
3011static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
3012 unsigned int rx_queue_label)
3013{
3014 struct efx_nic *efx = rx_queue->efx;
3015
3016 netif_info(efx, hw, efx->net_dev,
3017 "rx event arrived on queue %d labeled as queue %u\n",
3018 efx_rx_queue_index(rx_queue), rx_queue_label);
3019
3020 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3021}
3022
3023static void
3024efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
3025 unsigned int actual, unsigned int expected)
3026{
3027 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
3028 struct efx_nic *efx = rx_queue->efx;
3029
3030 netif_info(efx, hw, efx->net_dev,
3031 "dropped %d events (index=%d expected=%d)\n",
3032 dropped, actual, expected);
3033
3034 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3035}
3036
3037/* partially received RX was aborted. clean up. */
3038static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
3039{
3040 unsigned int rx_desc_ptr;
3041
3042 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
3043 "scattered RX aborted (dropping %u buffers)\n",
3044 rx_queue->scatter_n);
3045
3046 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
3047
3048 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
3049 0, EFX_RX_PKT_DISCARD);
3050
3051 rx_queue->removed_count += rx_queue->scatter_n;
3052 rx_queue->scatter_n = 0;
3053 rx_queue->scatter_len = 0;
3054 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
3055}
3056
3057static int efx_ef10_handle_rx_event(struct efx_channel *channel,
3058 const efx_qword_t *event)
3059{
3060 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
3061 unsigned int n_descs, n_packets, i;
3062 struct efx_nic *efx = channel->efx;
3063 struct efx_rx_queue *rx_queue;
3064 bool rx_cont;
3065 u16 flags = 0;
3066
3067 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
3068 return 0;
3069
3070 /* Basic packet information */
3071 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
3072 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
3073 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
3074 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
3075 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
3076
3077 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
3078 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
3079 EFX_QWORD_FMT "\n",
3080 EFX_QWORD_VAL(*event));
3081
3082 rx_queue = efx_channel_get_rx_queue(channel);
3083
3084 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
3085 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
3086
3087 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
3088 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3089
3090 if (n_descs != rx_queue->scatter_n + 1) {
3091 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3092
3093 /* detect rx abort */
3094 if (unlikely(n_descs == rx_queue->scatter_n)) {
3095 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
3096 netdev_WARN(efx->net_dev,
3097 "invalid RX abort: scatter_n=%u event="
3098 EFX_QWORD_FMT "\n",
3099 rx_queue->scatter_n,
3100 EFX_QWORD_VAL(*event));
3101 efx_ef10_handle_rx_abort(rx_queue);
3102 return 0;
3103 }
3104
3105 /* Check that RX completion merging is valid, i.e.
3106 * the current firmware supports it and this is a
3107 * non-scattered packet.
3108 */
3109 if (!(nic_data->datapath_caps &
3110 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
3111 rx_queue->scatter_n != 0 || rx_cont) {
3112 efx_ef10_handle_rx_bad_lbits(
3113 rx_queue, next_ptr_lbits,
3114 (rx_queue->removed_count +
3115 rx_queue->scatter_n + 1) &
3116 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3117 return 0;
3118 }
3119
3120 /* Merged completion for multiple non-scattered packets */
3121 rx_queue->scatter_n = 1;
3122 rx_queue->scatter_len = 0;
3123 n_packets = n_descs;
3124 ++channel->n_rx_merge_events;
3125 channel->n_rx_merge_packets += n_packets;
3126 flags |= EFX_RX_PKT_PREFIX_LEN;
3127 } else {
3128 ++rx_queue->scatter_n;
3129 rx_queue->scatter_len += rx_bytes;
3130 if (rx_cont)
3131 return 0;
3132 n_packets = 1;
3133 }
3134
3135 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
3136 flags |= EFX_RX_PKT_DISCARD;
3137
3138 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
3139 channel->n_rx_ip_hdr_chksum_err += n_packets;
3140 } else if (unlikely(EFX_QWORD_FIELD(*event,
3141 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
3142 channel->n_rx_tcp_udp_chksum_err += n_packets;
3143 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
3144 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
3145 flags |= EFX_RX_PKT_CSUMMED;
3146 }
3147
3148 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
3149 flags |= EFX_RX_PKT_TCP;
3150
3151 channel->irq_mod_score += 2 * n_packets;
3152
3153 /* Handle received packet(s) */
3154 for (i = 0; i < n_packets; i++) {
3155 efx_rx_packet(rx_queue,
3156 rx_queue->removed_count & rx_queue->ptr_mask,
3157 rx_queue->scatter_n, rx_queue->scatter_len,
3158 flags);
3159 rx_queue->removed_count += rx_queue->scatter_n;
3160 }
3161
3162 rx_queue->scatter_n = 0;
3163 rx_queue->scatter_len = 0;
3164
3165 return n_packets;
3166}
3167
3168static int
3169efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
3170{
3171 struct efx_nic *efx = channel->efx;
3172 struct efx_tx_queue *tx_queue;
3173 unsigned int tx_ev_desc_ptr;
3174 unsigned int tx_ev_q_label;
3175 int tx_descs = 0;
3176
3177 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
3178 return 0;
3179
3180 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
3181 return 0;
3182
3183 /* Transmit completion */
3184 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
3185 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
3186 tx_queue = efx_channel_get_tx_queue(channel,
3187 tx_ev_q_label % EFX_TXQ_TYPES);
3188 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
3189 tx_queue->ptr_mask);
3190 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
3191
3192 return tx_descs;
3193}
3194
3195static void
3196efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
3197{
3198 struct efx_nic *efx = channel->efx;
3199 int subcode;
3200
3201 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
3202
3203 switch (subcode) {
3204 case ESE_DZ_DRV_TIMER_EV:
3205 case ESE_DZ_DRV_WAKE_UP_EV:
3206 break;
3207 case ESE_DZ_DRV_START_UP_EV:
3208 /* event queue init complete. ok. */
3209 break;
3210 default:
3211 netif_err(efx, hw, efx->net_dev,
3212 "channel %d unknown driver event type %d"
3213 " (data " EFX_QWORD_FMT ")\n",
3214 channel->channel, subcode,
3215 EFX_QWORD_VAL(*event));
3216
3217 }
3218}
3219
3220static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
3221 efx_qword_t *event)
3222{
3223 struct efx_nic *efx = channel->efx;
3224 u32 subcode;
3225
3226 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
3227
3228 switch (subcode) {
3229 case EFX_EF10_TEST:
3230 channel->event_test_cpu = raw_smp_processor_id();
3231 break;
3232 case EFX_EF10_REFILL:
3233 /* The queue must be empty, so we won't receive any rx
3234 * events, so efx_process_channel() won't refill the
3235 * queue. Refill it here
3236 */
3237 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
3238 break;
3239 default:
3240 netif_err(efx, hw, efx->net_dev,
3241 "channel %d unknown driver event type %u"
3242 " (data " EFX_QWORD_FMT ")\n",
3243 channel->channel, (unsigned) subcode,
3244 EFX_QWORD_VAL(*event));
3245 }
3246}
3247
3248static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
3249{
3250 struct efx_nic *efx = channel->efx;
3251 efx_qword_t event, *p_event;
3252 unsigned int read_ptr;
3253 int ev_code;
3254 int tx_descs = 0;
3255 int spent = 0;
3256
3257 if (quota <= 0)
3258 return spent;
3259
3260 read_ptr = channel->eventq_read_ptr;
3261
3262 for (;;) {
3263 p_event = efx_event(channel, read_ptr);
3264 event = *p_event;
3265
3266 if (!efx_event_present(&event))
3267 break;
3268
3269 EFX_SET_QWORD(*p_event);
3270
3271 ++read_ptr;
3272
3273 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
3274
3275 netif_vdbg(efx, drv, efx->net_dev,
3276 "processing event on %d " EFX_QWORD_FMT "\n",
3277 channel->channel, EFX_QWORD_VAL(event));
3278
3279 switch (ev_code) {
3280 case ESE_DZ_EV_CODE_MCDI_EV:
3281 efx_mcdi_process_event(channel, &event);
3282 break;
3283 case ESE_DZ_EV_CODE_RX_EV:
3284 spent += efx_ef10_handle_rx_event(channel, &event);
3285 if (spent >= quota) {
3286 /* XXX can we split a merged event to
3287 * avoid going over-quota?
3288 */
3289 spent = quota;
3290 goto out;
3291 }
3292 break;
3293 case ESE_DZ_EV_CODE_TX_EV:
3294 tx_descs += efx_ef10_handle_tx_event(channel, &event);
3295 if (tx_descs > efx->txq_entries) {
3296 spent = quota;
3297 goto out;
3298 } else if (++spent == quota) {
3299 goto out;
3300 }
3301 break;
3302 case ESE_DZ_EV_CODE_DRIVER_EV:
3303 efx_ef10_handle_driver_event(channel, &event);
3304 if (++spent == quota)
3305 goto out;
3306 break;
3307 case EFX_EF10_DRVGEN_EV:
3308 efx_ef10_handle_driver_generated_event(channel, &event);
3309 break;
3310 default:
3311 netif_err(efx, hw, efx->net_dev,
3312 "channel %d unknown event type %d"
3313 " (data " EFX_QWORD_FMT ")\n",
3314 channel->channel, ev_code,
3315 EFX_QWORD_VAL(event));
3316 }
3317 }
3318
3319out:
3320 channel->eventq_read_ptr = read_ptr;
3321 return spent;
3322}
3323
3324static void efx_ef10_ev_read_ack(struct efx_channel *channel)
3325{
3326 struct efx_nic *efx = channel->efx;
3327 efx_dword_t rptr;
3328
3329 if (EFX_EF10_WORKAROUND_35388(efx)) {
3330 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
3331 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
3332 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
3333 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
3334
3335 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3336 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
3337 ERF_DD_EVQ_IND_RPTR,
3338 (channel->eventq_read_ptr &
3339 channel->eventq_mask) >>
3340 ERF_DD_EVQ_IND_RPTR_WIDTH);
3341 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3342 channel->channel);
3343 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3344 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
3345 ERF_DD_EVQ_IND_RPTR,
3346 channel->eventq_read_ptr &
3347 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
3348 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3349 channel->channel);
3350 } else {
3351 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
3352 channel->eventq_read_ptr &
3353 channel->eventq_mask);
3354 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
3355 }
3356}
3357
3358static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3359{
3360 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3361 struct efx_nic *efx = channel->efx;
3362 efx_qword_t event;
3363 int rc;
3364
3365 EFX_POPULATE_QWORD_2(event,
3366 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3367 ESF_DZ_EV_DATA, EFX_EF10_TEST);
3368
3369 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3370
3371 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3372 * already swapped the data to little-endian order.
3373 */
3374 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3375 sizeof(efx_qword_t));
3376
3377 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3378 NULL, 0, NULL);
3379 if (rc != 0)
3380 goto fail;
3381
3382 return;
3383
3384fail:
3385 WARN_ON(true);
3386 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3387}
3388
3389void efx_ef10_handle_drain_event(struct efx_nic *efx)
3390{
3391 if (atomic_dec_and_test(&efx->active_queues))
3392 wake_up(&efx->flush_wq);
3393
3394 WARN_ON(atomic_read(&efx->active_queues) < 0);
3395}
3396
3397static int efx_ef10_fini_dmaq(struct efx_nic *efx)
3398{
3399 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3400 struct efx_channel *channel;
3401 struct efx_tx_queue *tx_queue;
3402 struct efx_rx_queue *rx_queue;
3403 int pending;
3404
3405 /* If the MC has just rebooted, the TX/RX queues will have already been
3406 * torn down, but efx->active_queues needs to be set to zero.
3407 */
3408 if (nic_data->must_realloc_vis) {
3409 atomic_set(&efx->active_queues, 0);
3410 return 0;
3411 }
3412
3413 /* Do not attempt to write to the NIC during EEH recovery */
3414 if (efx->state != STATE_RECOVERY) {
3415 efx_for_each_channel(channel, efx) {
3416 efx_for_each_channel_rx_queue(rx_queue, channel)
3417 efx_ef10_rx_fini(rx_queue);
3418 efx_for_each_channel_tx_queue(tx_queue, channel)
3419 efx_ef10_tx_fini(tx_queue);
3420 }
3421
3422 wait_event_timeout(efx->flush_wq,
3423 atomic_read(&efx->active_queues) == 0,
3424 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
3425 pending = atomic_read(&efx->active_queues);
3426 if (pending) {
3427 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
3428 pending);
3429 return -ETIMEDOUT;
3430 }
3431 }
3432
3433 return 0;
3434}
3435
3436static void efx_ef10_prepare_flr(struct efx_nic *efx)
3437{
3438 atomic_set(&efx->active_queues, 0);
3439}
3440
3441static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
3442 const struct efx_filter_spec *right)
3443{
3444 if ((left->match_flags ^ right->match_flags) |
3445 ((left->flags ^ right->flags) &
3446 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
3447 return false;
3448
3449 return memcmp(&left->outer_vid, &right->outer_vid,
3450 sizeof(struct efx_filter_spec) -
3451 offsetof(struct efx_filter_spec, outer_vid)) == 0;
3452}
3453
3454static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
3455{
3456 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
3457 return jhash2((const u32 *)&spec->outer_vid,
3458 (sizeof(struct efx_filter_spec) -
3459 offsetof(struct efx_filter_spec, outer_vid)) / 4,
3460 0);
3461 /* XXX should we randomise the initval? */
3462}
3463
3464/* Decide whether a filter should be exclusive or else should allow
3465 * delivery to additional recipients. Currently we decide that
3466 * filters for specific local unicast MAC and IP addresses are
3467 * exclusive.
3468 */
3469static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
3470{
3471 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
3472 !is_multicast_ether_addr(spec->loc_mac))
3473 return true;
3474
3475 if ((spec->match_flags &
3476 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
3477 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
3478 if (spec->ether_type == htons(ETH_P_IP) &&
3479 !ipv4_is_multicast(spec->loc_host[0]))
3480 return true;
3481 if (spec->ether_type == htons(ETH_P_IPV6) &&
3482 ((const u8 *)spec->loc_host)[0] != 0xff)
3483 return true;
3484 }
3485
3486 return false;
3487}
3488
3489static struct efx_filter_spec *
3490efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
3491 unsigned int filter_idx)
3492{
3493 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
3494 ~EFX_EF10_FILTER_FLAGS);
3495}
3496
3497static unsigned int
3498efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
3499 unsigned int filter_idx)
3500{
3501 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
3502}
3503
3504static void
3505efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
3506 unsigned int filter_idx,
3507 const struct efx_filter_spec *spec,
3508 unsigned int flags)
3509{
3510 table->entry[filter_idx].spec = (unsigned long)spec | flags;
3511}
3512
3513static void efx_ef10_filter_push_prep(struct efx_nic *efx,
3514 const struct efx_filter_spec *spec,
3515 efx_dword_t *inbuf, u64 handle,
3516 bool replacing)
3517{
3518 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3519 u32 flags = spec->flags;
3520
3521 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
3522
3523 /* Remove RSS flag if we don't have an RSS context. */
3524 if (flags & EFX_FILTER_FLAG_RX_RSS &&
3525 spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT &&
3526 nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
3527 flags &= ~EFX_FILTER_FLAG_RX_RSS;
3528
3529 if (replacing) {
3530 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3531 MC_CMD_FILTER_OP_IN_OP_REPLACE);
3532 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
3533 } else {
3534 u32 match_fields = 0;
3535
3536 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3537 efx_ef10_filter_is_exclusive(spec) ?
3538 MC_CMD_FILTER_OP_IN_OP_INSERT :
3539 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
3540
3541 /* Convert match flags and values. Unlike almost
3542 * everything else in MCDI, these fields are in
3543 * network byte order.
3544 */
3545 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
3546 match_fields |=
3547 is_multicast_ether_addr(spec->loc_mac) ?
3548 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
3549 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
3550#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
3551 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
3552 match_fields |= \
3553 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3554 mcdi_field ## _LBN; \
3555 BUILD_BUG_ON( \
3556 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
3557 sizeof(spec->gen_field)); \
3558 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
3559 &spec->gen_field, sizeof(spec->gen_field)); \
3560 }
3561 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
3562 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
3563 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
3564 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
3565 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
3566 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
3567 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
3568 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
3569 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
3570 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
3571#undef COPY_FIELD
3572 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
3573 match_fields);
3574 }
3575
3576 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
3577 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
3578 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3579 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
3580 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
3581 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
3582 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
3583 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
3584 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
3585 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3586 0 : spec->dmaq_id);
3587 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
3588 (flags & EFX_FILTER_FLAG_RX_RSS) ?
3589 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
3590 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
3591 if (flags & EFX_FILTER_FLAG_RX_RSS)
3592 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
3593 spec->rss_context !=
3594 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
3595 spec->rss_context : nic_data->rx_rss_context);
3596}
3597
3598static int efx_ef10_filter_push(struct efx_nic *efx,
3599 const struct efx_filter_spec *spec,
3600 u64 *handle, bool replacing)
3601{
3602 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3603 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
3604 int rc;
3605
3606 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
3607 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3608 outbuf, sizeof(outbuf), NULL);
3609 if (rc == 0)
3610 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3611 if (rc == -ENOSPC)
3612 rc = -EBUSY; /* to match efx_farch_filter_insert() */
3613 return rc;
3614}
3615
3616static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec)
3617{
3618 unsigned int match_flags = spec->match_flags;
3619 u32 mcdi_flags = 0;
3620
3621 if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) {
3622 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG;
3623 mcdi_flags |=
3624 is_multicast_ether_addr(spec->loc_mac) ?
3625 (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN) :
3626 (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN);
3627 }
3628
3629#define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field) { \
3630 unsigned int old_match_flags = match_flags; \
3631 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag; \
3632 if (match_flags != old_match_flags) \
3633 mcdi_flags |= \
3634 (1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3635 mcdi_field ## _LBN); \
3636 }
3637 MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP);
3638 MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP);
3639 MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC);
3640 MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT);
3641 MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC);
3642 MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT);
3643 MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE);
3644 MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN);
3645 MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN);
3646 MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO);
3647#undef MAP_FILTER_TO_MCDI_FLAG
3648
3649 /* Did we map them all? */
3650 WARN_ON_ONCE(match_flags);
3651
3652 return mcdi_flags;
3653}
3654
3655static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table,
3656 const struct efx_filter_spec *spec)
3657{
3658 u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
3659 unsigned int match_pri;
3660
3661 for (match_pri = 0;
3662 match_pri < table->rx_match_count;
3663 match_pri++)
3664 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags)
3665 return match_pri;
3666
3667 return -EPROTONOSUPPORT;
3668}
3669
3670static s32 efx_ef10_filter_insert(struct efx_nic *efx,
3671 struct efx_filter_spec *spec,
3672 bool replace_equal)
3673{
3674 struct efx_ef10_filter_table *table = efx->filter_state;
3675 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3676 struct efx_filter_spec *saved_spec;
3677 unsigned int match_pri, hash;
3678 unsigned int priv_flags;
3679 bool replacing = false;
3680 int ins_index = -1;
3681 DEFINE_WAIT(wait);
3682 bool is_mc_recip;
3683 s32 rc;
3684
3685 /* For now, only support RX filters */
3686 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
3687 EFX_FILTER_FLAG_RX)
3688 return -EINVAL;
3689
3690 rc = efx_ef10_filter_pri(table, spec);
3691 if (rc < 0)
3692 return rc;
3693 match_pri = rc;
3694
3695 hash = efx_ef10_filter_hash(spec);
3696 is_mc_recip = efx_filter_is_mc_recipient(spec);
3697 if (is_mc_recip)
3698 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3699
3700 /* Find any existing filters with the same match tuple or
3701 * else a free slot to insert at. If any of them are busy,
3702 * we have to wait and retry.
3703 */
3704 for (;;) {
3705 unsigned int depth = 1;
3706 unsigned int i;
3707
3708 spin_lock_bh(&efx->filter_lock);
3709
3710 for (;;) {
3711 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3712 saved_spec = efx_ef10_filter_entry_spec(table, i);
3713
3714 if (!saved_spec) {
3715 if (ins_index < 0)
3716 ins_index = i;
3717 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3718 if (table->entry[i].spec &
3719 EFX_EF10_FILTER_FLAG_BUSY)
3720 break;
3721 if (spec->priority < saved_spec->priority &&
3722 spec->priority != EFX_FILTER_PRI_AUTO) {
3723 rc = -EPERM;
3724 goto out_unlock;
3725 }
3726 if (!is_mc_recip) {
3727 /* This is the only one */
3728 if (spec->priority ==
3729 saved_spec->priority &&
3730 !replace_equal) {
3731 rc = -EEXIST;
3732 goto out_unlock;
3733 }
3734 ins_index = i;
3735 goto found;
3736 } else if (spec->priority >
3737 saved_spec->priority ||
3738 (spec->priority ==
3739 saved_spec->priority &&
3740 replace_equal)) {
3741 if (ins_index < 0)
3742 ins_index = i;
3743 else
3744 __set_bit(depth, mc_rem_map);
3745 }
3746 }
3747
3748 /* Once we reach the maximum search depth, use
3749 * the first suitable slot or return -EBUSY if
3750 * there was none
3751 */
3752 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3753 if (ins_index < 0) {
3754 rc = -EBUSY;
3755 goto out_unlock;
3756 }
3757 goto found;
3758 }
3759
3760 ++depth;
3761 }
3762
3763 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3764 spin_unlock_bh(&efx->filter_lock);
3765 schedule();
3766 }
3767
3768found:
3769 /* Create a software table entry if necessary, and mark it
3770 * busy. We might yet fail to insert, but any attempt to
3771 * insert a conflicting filter while we're waiting for the
3772 * firmware must find the busy entry.
3773 */
3774 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3775 if (saved_spec) {
3776 if (spec->priority == EFX_FILTER_PRI_AUTO &&
3777 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
3778 /* Just make sure it won't be removed */
3779 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
3780 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
3781 table->entry[ins_index].spec &=
3782 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3783 rc = ins_index;
3784 goto out_unlock;
3785 }
3786 replacing = true;
3787 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
3788 } else {
3789 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3790 if (!saved_spec) {
3791 rc = -ENOMEM;
3792 goto out_unlock;
3793 }
3794 *saved_spec = *spec;
3795 priv_flags = 0;
3796 }
3797 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3798 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
3799
3800 /* Mark lower-priority multicast recipients busy prior to removal */
3801 if (is_mc_recip) {
3802 unsigned int depth, i;
3803
3804 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3805 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3806 if (test_bit(depth, mc_rem_map))
3807 table->entry[i].spec |=
3808 EFX_EF10_FILTER_FLAG_BUSY;
3809 }
3810 }
3811
3812 spin_unlock_bh(&efx->filter_lock);
3813
3814 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
3815 replacing);
3816
3817 /* Finalise the software table entry */
3818 spin_lock_bh(&efx->filter_lock);
3819 if (rc == 0) {
3820 if (replacing) {
3821 /* Update the fields that may differ */
3822 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
3823 saved_spec->flags |=
3824 EFX_FILTER_FLAG_RX_OVER_AUTO;
3825 saved_spec->priority = spec->priority;
3826 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
3827 saved_spec->flags |= spec->flags;
3828 saved_spec->rss_context = spec->rss_context;
3829 saved_spec->dmaq_id = spec->dmaq_id;
3830 }
3831 } else if (!replacing) {
3832 kfree(saved_spec);
3833 saved_spec = NULL;
3834 }
3835 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
3836
3837 /* Remove and finalise entries for lower-priority multicast
3838 * recipients
3839 */
3840 if (is_mc_recip) {
3841 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3842 unsigned int depth, i;
3843
3844 memset(inbuf, 0, sizeof(inbuf));
3845
3846 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3847 if (!test_bit(depth, mc_rem_map))
3848 continue;
3849
3850 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3851 saved_spec = efx_ef10_filter_entry_spec(table, i);
3852 priv_flags = efx_ef10_filter_entry_flags(table, i);
3853
3854 if (rc == 0) {
3855 spin_unlock_bh(&efx->filter_lock);
3856 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3857 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3858 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3859 table->entry[i].handle);
3860 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3861 inbuf, sizeof(inbuf),
3862 NULL, 0, NULL);
3863 spin_lock_bh(&efx->filter_lock);
3864 }
3865
3866 if (rc == 0) {
3867 kfree(saved_spec);
3868 saved_spec = NULL;
3869 priv_flags = 0;
3870 } else {
3871 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
3872 }
3873 efx_ef10_filter_set_entry(table, i, saved_spec,
3874 priv_flags);
3875 }
3876 }
3877
3878 /* If successful, return the inserted filter ID */
3879 if (rc == 0)
3880 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
3881
3882 wake_up_all(&table->waitq);
3883out_unlock:
3884 spin_unlock_bh(&efx->filter_lock);
3885 finish_wait(&table->waitq, &wait);
3886 return rc;
3887}
3888
3889static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
3890{
3891 /* no need to do anything here on EF10 */
3892}
3893
3894/* Remove a filter.
3895 * If !by_index, remove by ID
3896 * If by_index, remove by index
3897 * Filter ID may come from userland and must be range-checked.
3898 */
3899static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
3900 unsigned int priority_mask,
3901 u32 filter_id, bool by_index)
3902{
3903 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3904 struct efx_ef10_filter_table *table = efx->filter_state;
3905 MCDI_DECLARE_BUF(inbuf,
3906 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3907 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3908 struct efx_filter_spec *spec;
3909 DEFINE_WAIT(wait);
3910 int rc;
3911
3912 /* Find the software table entry and mark it busy. Don't
3913 * remove it yet; any attempt to update while we're waiting
3914 * for the firmware must find the busy entry.
3915 */
3916 for (;;) {
3917 spin_lock_bh(&efx->filter_lock);
3918 if (!(table->entry[filter_idx].spec &
3919 EFX_EF10_FILTER_FLAG_BUSY))
3920 break;
3921 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3922 spin_unlock_bh(&efx->filter_lock);
3923 schedule();
3924 }
3925
3926 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3927 if (!spec ||
3928 (!by_index &&
3929 efx_ef10_filter_pri(table, spec) !=
3930 filter_id / HUNT_FILTER_TBL_ROWS)) {
3931 rc = -ENOENT;
3932 goto out_unlock;
3933 }
3934
3935 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
3936 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
3937 /* Just remove flags */
3938 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
3939 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3940 rc = 0;
3941 goto out_unlock;
3942 }
3943
3944 if (!(priority_mask & (1U << spec->priority))) {
3945 rc = -ENOENT;
3946 goto out_unlock;
3947 }
3948
3949 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3950 spin_unlock_bh(&efx->filter_lock);
3951
3952 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
3953 /* Reset to an automatic filter */
3954
3955 struct efx_filter_spec new_spec = *spec;
3956
3957 new_spec.priority = EFX_FILTER_PRI_AUTO;
3958 new_spec.flags = (EFX_FILTER_FLAG_RX |
3959 (efx_rss_enabled(efx) ?
3960 EFX_FILTER_FLAG_RX_RSS : 0));
3961 new_spec.dmaq_id = 0;
3962 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
3963 rc = efx_ef10_filter_push(efx, &new_spec,
3964 &table->entry[filter_idx].handle,
3965 true);
3966
3967 spin_lock_bh(&efx->filter_lock);
3968 if (rc == 0)
3969 *spec = new_spec;
3970 } else {
3971 /* Really remove the filter */
3972
3973 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3974 efx_ef10_filter_is_exclusive(spec) ?
3975 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3976 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3977 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3978 table->entry[filter_idx].handle);
3979 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3980 inbuf, sizeof(inbuf), NULL, 0, NULL);
3981
3982 spin_lock_bh(&efx->filter_lock);
3983 if (rc == 0) {
3984 kfree(spec);
3985 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3986 }
3987 }
3988
3989 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3990 wake_up_all(&table->waitq);
3991out_unlock:
3992 spin_unlock_bh(&efx->filter_lock);
3993 finish_wait(&table->waitq, &wait);
3994 return rc;
3995}
3996
3997static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
3998 enum efx_filter_priority priority,
3999 u32 filter_id)
4000{
4001 return efx_ef10_filter_remove_internal(efx, 1U << priority,
4002 filter_id, false);
4003}
4004
4005static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id)
4006{
4007 return filter_id % HUNT_FILTER_TBL_ROWS;
4008}
4009
4010static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
4011 enum efx_filter_priority priority,
4012 u32 filter_id)
4013{
4014 if (filter_id == EFX_EF10_FILTER_ID_INVALID)
4015 return;
4016 efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id, true);
4017}
4018
4019static int efx_ef10_filter_get_safe(struct efx_nic *efx,
4020 enum efx_filter_priority priority,
4021 u32 filter_id, struct efx_filter_spec *spec)
4022{
4023 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
4024 struct efx_ef10_filter_table *table = efx->filter_state;
4025 const struct efx_filter_spec *saved_spec;
4026 int rc;
4027
4028 spin_lock_bh(&efx->filter_lock);
4029 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
4030 if (saved_spec && saved_spec->priority == priority &&
4031 efx_ef10_filter_pri(table, saved_spec) ==
4032 filter_id / HUNT_FILTER_TBL_ROWS) {
4033 *spec = *saved_spec;
4034 rc = 0;
4035 } else {
4036 rc = -ENOENT;
4037 }
4038 spin_unlock_bh(&efx->filter_lock);
4039 return rc;
4040}
4041
4042static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
4043 enum efx_filter_priority priority)
4044{
4045 unsigned int priority_mask;
4046 unsigned int i;
4047 int rc;
4048
4049 priority_mask = (((1U << (priority + 1)) - 1) &
4050 ~(1U << EFX_FILTER_PRI_AUTO));
4051
4052 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4053 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
4054 i, true);
4055 if (rc && rc != -ENOENT)
4056 return rc;
4057 }
4058
4059 return 0;
4060}
4061
4062static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
4063 enum efx_filter_priority priority)
4064{
4065 struct efx_ef10_filter_table *table = efx->filter_state;
4066 unsigned int filter_idx;
4067 s32 count = 0;
4068
4069 spin_lock_bh(&efx->filter_lock);
4070 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4071 if (table->entry[filter_idx].spec &&
4072 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
4073 priority)
4074 ++count;
4075 }
4076 spin_unlock_bh(&efx->filter_lock);
4077 return count;
4078}
4079
4080static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
4081{
4082 struct efx_ef10_filter_table *table = efx->filter_state;
4083
4084 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
4085}
4086
4087static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
4088 enum efx_filter_priority priority,
4089 u32 *buf, u32 size)
4090{
4091 struct efx_ef10_filter_table *table = efx->filter_state;
4092 struct efx_filter_spec *spec;
4093 unsigned int filter_idx;
4094 s32 count = 0;
4095
4096 spin_lock_bh(&efx->filter_lock);
4097 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4098 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4099 if (spec && spec->priority == priority) {
4100 if (count == size) {
4101 count = -EMSGSIZE;
4102 break;
4103 }
4104 buf[count++] = (efx_ef10_filter_pri(table, spec) *
4105 HUNT_FILTER_TBL_ROWS +
4106 filter_idx);
4107 }
4108 }
4109 spin_unlock_bh(&efx->filter_lock);
4110 return count;
4111}
4112
4113#ifdef CONFIG_RFS_ACCEL
4114
4115static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
4116
4117static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
4118 struct efx_filter_spec *spec)
4119{
4120 struct efx_ef10_filter_table *table = efx->filter_state;
4121 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
4122 struct efx_filter_spec *saved_spec;
4123 unsigned int hash, i, depth = 1;
4124 bool replacing = false;
4125 int ins_index = -1;
4126 u64 cookie;
4127 s32 rc;
4128
4129 /* Must be an RX filter without RSS and not for a multicast
4130 * destination address (RFS only works for connected sockets).
4131 * These restrictions allow us to pass only a tiny amount of
4132 * data through to the completion function.
4133 */
4134 EFX_WARN_ON_PARANOID(spec->flags !=
4135 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
4136 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
4137 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
4138
4139 hash = efx_ef10_filter_hash(spec);
4140
4141 spin_lock_bh(&efx->filter_lock);
4142
4143 /* Find any existing filter with the same match tuple or else
4144 * a free slot to insert at. If an existing filter is busy,
4145 * we have to give up.
4146 */
4147 for (;;) {
4148 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4149 saved_spec = efx_ef10_filter_entry_spec(table, i);
4150
4151 if (!saved_spec) {
4152 if (ins_index < 0)
4153 ins_index = i;
4154 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4155 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
4156 rc = -EBUSY;
4157 goto fail_unlock;
4158 }
4159 if (spec->priority < saved_spec->priority) {
4160 rc = -EPERM;
4161 goto fail_unlock;
4162 }
4163 ins_index = i;
4164 break;
4165 }
4166
4167 /* Once we reach the maximum search depth, use the
4168 * first suitable slot or return -EBUSY if there was
4169 * none
4170 */
4171 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
4172 if (ins_index < 0) {
4173 rc = -EBUSY;
4174 goto fail_unlock;
4175 }
4176 break;
4177 }
4178
4179 ++depth;
4180 }
4181
4182 /* Create a software table entry if necessary, and mark it
4183 * busy. We might yet fail to insert, but any attempt to
4184 * insert a conflicting filter while we're waiting for the
4185 * firmware must find the busy entry.
4186 */
4187 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4188 if (saved_spec) {
4189 replacing = true;
4190 } else {
4191 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4192 if (!saved_spec) {
4193 rc = -ENOMEM;
4194 goto fail_unlock;
4195 }
4196 *saved_spec = *spec;
4197 }
4198 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
4199 EFX_EF10_FILTER_FLAG_BUSY);
4200
4201 spin_unlock_bh(&efx->filter_lock);
4202
4203 /* Pack up the variables needed on completion */
4204 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
4205
4206 efx_ef10_filter_push_prep(efx, spec, inbuf,
4207 table->entry[ins_index].handle, replacing);
4208 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
4209 MC_CMD_FILTER_OP_OUT_LEN,
4210 efx_ef10_filter_rfs_insert_complete, cookie);
4211
4212 return ins_index;
4213
4214fail_unlock:
4215 spin_unlock_bh(&efx->filter_lock);
4216 return rc;
4217}
4218
4219static void
4220efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
4221 int rc, efx_dword_t *outbuf,
4222 size_t outlen_actual)
4223{
4224 struct efx_ef10_filter_table *table = efx->filter_state;
4225 unsigned int ins_index, dmaq_id;
4226 struct efx_filter_spec *spec;
4227 bool replacing;
4228
4229 /* Unpack the cookie */
4230 replacing = cookie >> 31;
4231 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
4232 dmaq_id = cookie & 0xffff;
4233
4234 spin_lock_bh(&efx->filter_lock);
4235 spec = efx_ef10_filter_entry_spec(table, ins_index);
4236 if (rc == 0) {
4237 table->entry[ins_index].handle =
4238 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
4239 if (replacing)
4240 spec->dmaq_id = dmaq_id;
4241 } else if (!replacing) {
4242 kfree(spec);
4243 spec = NULL;
4244 }
4245 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
4246 spin_unlock_bh(&efx->filter_lock);
4247
4248 wake_up_all(&table->waitq);
4249}
4250
4251static void
4252efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4253 unsigned long filter_idx,
4254 int rc, efx_dword_t *outbuf,
4255 size_t outlen_actual);
4256
4257static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
4258 unsigned int filter_idx)
4259{
4260 struct efx_ef10_filter_table *table = efx->filter_state;
4261 struct efx_filter_spec *spec =
4262 efx_ef10_filter_entry_spec(table, filter_idx);
4263 MCDI_DECLARE_BUF(inbuf,
4264 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4265 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4266
4267 if (!spec ||
4268 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
4269 spec->priority != EFX_FILTER_PRI_HINT ||
4270 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
4271 flow_id, filter_idx))
4272 return false;
4273
4274 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4275 MC_CMD_FILTER_OP_IN_OP_REMOVE);
4276 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4277 table->entry[filter_idx].handle);
4278 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
4279 efx_ef10_filter_rfs_expire_complete, filter_idx))
4280 return false;
4281
4282 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4283 return true;
4284}
4285
4286static void
4287efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4288 unsigned long filter_idx,
4289 int rc, efx_dword_t *outbuf,
4290 size_t outlen_actual)
4291{
4292 struct efx_ef10_filter_table *table = efx->filter_state;
4293 struct efx_filter_spec *spec =
4294 efx_ef10_filter_entry_spec(table, filter_idx);
4295
4296 spin_lock_bh(&efx->filter_lock);
4297 if (rc == 0) {
4298 kfree(spec);
4299 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4300 }
4301 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4302 wake_up_all(&table->waitq);
4303 spin_unlock_bh(&efx->filter_lock);
4304}
4305
4306#endif /* CONFIG_RFS_ACCEL */
4307
4308static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
4309{
4310 int match_flags = 0;
4311
4312#define MAP_FLAG(gen_flag, mcdi_field) { \
4313 u32 old_mcdi_flags = mcdi_flags; \
4314 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
4315 mcdi_field ## _LBN); \
4316 if (mcdi_flags != old_mcdi_flags) \
4317 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
4318 }
4319 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
4320 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
4321 MAP_FLAG(REM_HOST, SRC_IP);
4322 MAP_FLAG(LOC_HOST, DST_IP);
4323 MAP_FLAG(REM_MAC, SRC_MAC);
4324 MAP_FLAG(REM_PORT, SRC_PORT);
4325 MAP_FLAG(LOC_MAC, DST_MAC);
4326 MAP_FLAG(LOC_PORT, DST_PORT);
4327 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
4328 MAP_FLAG(INNER_VID, INNER_VLAN);
4329 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4330 MAP_FLAG(IP_PROTO, IP_PROTO);
4331#undef MAP_FLAG
4332
4333 /* Did we map them all? */
4334 if (mcdi_flags)
4335 return -EINVAL;
4336
4337 return match_flags;
4338}
4339
4340static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
4341{
4342 struct efx_ef10_filter_table *table = efx->filter_state;
4343 struct efx_ef10_filter_vlan *vlan, *next_vlan;
4344
4345 /* See comment in efx_ef10_filter_table_remove() */
4346 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4347 return;
4348
4349 if (!table)
4350 return;
4351
4352 list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
4353 efx_ef10_filter_del_vlan_internal(efx, vlan);
4354}
4355
4356static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table,
4357 enum efx_filter_match_flags match_flags)
4358{
4359 unsigned int match_pri;
4360 int mf;
4361
4362 for (match_pri = 0;
4363 match_pri < table->rx_match_count;
4364 match_pri++) {
4365 mf = efx_ef10_filter_match_flags_from_mcdi(
4366 table->rx_match_mcdi_flags[match_pri]);
4367 if (mf == match_flags)
4368 return true;
4369 }
4370
4371 return false;
4372}
4373
4374static int efx_ef10_filter_table_probe(struct efx_nic *efx)
4375{
4376 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
4377 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
4378 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4379 struct net_device *net_dev = efx->net_dev;
4380 unsigned int pd_match_pri, pd_match_count;
4381 struct efx_ef10_filter_table *table;
4382 struct efx_ef10_vlan *vlan;
4383 size_t outlen;
4384 int rc;
4385
4386 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4387 return -EINVAL;
4388
4389 if (efx->filter_state) /* already probed */
4390 return 0;
4391
4392 table = kzalloc(sizeof(*table), GFP_KERNEL);
4393 if (!table)
4394 return -ENOMEM;
4395
4396 /* Find out which RX filter types are supported, and their priorities */
4397 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
4398 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
4399 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
4400 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
4401 &outlen);
4402 if (rc)
4403 goto fail;
4404 pd_match_count = MCDI_VAR_ARRAY_LEN(
4405 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
4406 table->rx_match_count = 0;
4407
4408 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
4409 u32 mcdi_flags =
4410 MCDI_ARRAY_DWORD(
4411 outbuf,
4412 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
4413 pd_match_pri);
4414 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
4415 if (rc < 0) {
4416 netif_dbg(efx, probe, efx->net_dev,
4417 "%s: fw flags %#x pri %u not supported in driver\n",
4418 __func__, mcdi_flags, pd_match_pri);
4419 } else {
4420 netif_dbg(efx, probe, efx->net_dev,
4421 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4422 __func__, mcdi_flags, pd_match_pri,
4423 rc, table->rx_match_count);
4424 table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags;
4425 table->rx_match_count++;
4426 }
4427 }
4428
4429 if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) &&
4430 !(efx_ef10_filter_match_supported(table,
4431 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) &&
4432 efx_ef10_filter_match_supported(table,
4433 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) {
4434 netif_info(efx, probe, net_dev,
4435 "VLAN filters are not supported in this firmware variant\n");
4436 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4437 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4438 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4439 }
4440
4441 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
4442 if (!table->entry) {
4443 rc = -ENOMEM;
4444 goto fail;
4445 }
4446
4447 table->mc_promisc_last = false;
4448 table->vlan_filter =
4449 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
4450 INIT_LIST_HEAD(&table->vlan_list);
4451
4452 efx->filter_state = table;
4453 init_waitqueue_head(&table->waitq);
4454
4455 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
4456 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
4457 if (rc)
4458 goto fail_add_vlan;
4459 }
4460
4461 return 0;
4462
4463fail_add_vlan:
4464 efx_ef10_filter_cleanup_vlans(efx);
4465 efx->filter_state = NULL;
4466fail:
4467 kfree(table);
4468 return rc;
4469}
4470
4471/* Caller must hold efx->filter_sem for read if race against
4472 * efx_ef10_filter_table_remove() is possible
4473 */
4474static void efx_ef10_filter_table_restore(struct efx_nic *efx)
4475{
4476 struct efx_ef10_filter_table *table = efx->filter_state;
4477 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4478 struct efx_filter_spec *spec;
4479 unsigned int filter_idx;
4480 bool failed = false;
4481 int rc;
4482
4483 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4484
4485 if (!nic_data->must_restore_filters)
4486 return;
4487
4488 if (!table)
4489 return;
4490
4491 spin_lock_bh(&efx->filter_lock);
4492
4493 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4494 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4495 if (!spec)
4496 continue;
4497
4498 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4499 spin_unlock_bh(&efx->filter_lock);
4500
4501 rc = efx_ef10_filter_push(efx, spec,
4502 &table->entry[filter_idx].handle,
4503 false);
4504 if (rc)
4505 failed = true;
4506
4507 spin_lock_bh(&efx->filter_lock);
4508 if (rc) {
4509 kfree(spec);
4510 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4511 } else {
4512 table->entry[filter_idx].spec &=
4513 ~EFX_EF10_FILTER_FLAG_BUSY;
4514 }
4515 }
4516
4517 spin_unlock_bh(&efx->filter_lock);
4518
4519 if (failed)
4520 netif_err(efx, hw, efx->net_dev,
4521 "unable to restore all filters\n");
4522 else
4523 nic_data->must_restore_filters = false;
4524}
4525
4526static void efx_ef10_filter_table_remove(struct efx_nic *efx)
4527{
4528 struct efx_ef10_filter_table *table = efx->filter_state;
4529 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
4530 struct efx_filter_spec *spec;
4531 unsigned int filter_idx;
4532 int rc;
4533
4534 efx_ef10_filter_cleanup_vlans(efx);
4535 efx->filter_state = NULL;
4536 /* If we were called without locking, then it's not safe to free
4537 * the table as others might be using it. So we just WARN, leak
4538 * the memory, and potentially get an inconsistent filter table
4539 * state.
4540 * This should never actually happen.
4541 */
4542 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4543 return;
4544
4545 if (!table)
4546 return;
4547
4548 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4549 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4550 if (!spec)
4551 continue;
4552
4553 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4554 efx_ef10_filter_is_exclusive(spec) ?
4555 MC_CMD_FILTER_OP_IN_OP_REMOVE :
4556 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4557 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4558 table->entry[filter_idx].handle);
4559 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
4560 sizeof(inbuf), NULL, 0, NULL);
4561 if (rc)
4562 netif_info(efx, drv, efx->net_dev,
4563 "%s: filter %04x remove failed\n",
4564 __func__, filter_idx);
4565 kfree(spec);
4566 }
4567
4568 vfree(table->entry);
4569 kfree(table);
4570}
4571
4572static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
4573{
4574 struct efx_ef10_filter_table *table = efx->filter_state;
4575 unsigned int filter_idx;
4576
4577 if (*id != EFX_EF10_FILTER_ID_INVALID) {
4578 filter_idx = efx_ef10_filter_get_unsafe_id(efx, *id);
4579 if (!table->entry[filter_idx].spec)
4580 netif_dbg(efx, drv, efx->net_dev,
4581 "marked null spec old %04x:%04x\n", *id,
4582 filter_idx);
4583 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
4584 *id = EFX_EF10_FILTER_ID_INVALID;
4585 }
4586}
4587
4588/* Mark old per-VLAN filters that may need to be removed */
4589static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
4590 struct efx_ef10_filter_vlan *vlan)
4591{
4592 struct efx_ef10_filter_table *table = efx->filter_state;
4593 unsigned int i;
4594
4595 for (i = 0; i < table->dev_uc_count; i++)
4596 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
4597 for (i = 0; i < table->dev_mc_count; i++)
4598 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
4599 efx_ef10_filter_mark_one_old(efx, &vlan->ucdef);
4600 efx_ef10_filter_mark_one_old(efx, &vlan->bcast);
4601 efx_ef10_filter_mark_one_old(efx, &vlan->mcdef);
4602}
4603
4604/* Mark old filters that may need to be removed.
4605 * Caller must hold efx->filter_sem for read if race against
4606 * efx_ef10_filter_table_remove() is possible
4607 */
4608static void efx_ef10_filter_mark_old(struct efx_nic *efx)
4609{
4610 struct efx_ef10_filter_table *table = efx->filter_state;
4611 struct efx_ef10_filter_vlan *vlan;
4612
4613 spin_lock_bh(&efx->filter_lock);
4614 list_for_each_entry(vlan, &table->vlan_list, list)
4615 _efx_ef10_filter_vlan_mark_old(efx, vlan);
4616 spin_unlock_bh(&efx->filter_lock);
4617}
4618
4619static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
4620{
4621 struct efx_ef10_filter_table *table = efx->filter_state;
4622 struct net_device *net_dev = efx->net_dev;
4623 struct netdev_hw_addr *uc;
4624 int addr_count;
4625 unsigned int i;
4626
4627 addr_count = netdev_uc_count(net_dev);
4628 table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
4629 table->dev_uc_count = 1 + addr_count;
4630 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
4631 i = 1;
4632 netdev_for_each_uc_addr(uc, net_dev) {
4633 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
4634 table->uc_promisc = true;
4635 break;
4636 }
4637 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
4638 i++;
4639 }
4640}
4641
4642static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
4643{
4644 struct efx_ef10_filter_table *table = efx->filter_state;
4645 struct net_device *net_dev = efx->net_dev;
4646 struct netdev_hw_addr *mc;
4647 unsigned int i, addr_count;
4648
4649 table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
4650
4651 addr_count = netdev_mc_count(net_dev);
4652 i = 0;
4653 netdev_for_each_mc_addr(mc, net_dev) {
4654 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
4655 table->mc_promisc = true;
4656 break;
4657 }
4658 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
4659 i++;
4660 }
4661
4662 table->dev_mc_count = i;
4663}
4664
4665static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
4666 struct efx_ef10_filter_vlan *vlan,
4667 bool multicast, bool rollback)
4668{
4669 struct efx_ef10_filter_table *table = efx->filter_state;
4670 struct efx_ef10_dev_addr *addr_list;
4671 enum efx_filter_flags filter_flags;
4672 struct efx_filter_spec spec;
4673 u8 baddr[ETH_ALEN];
4674 unsigned int i, j;
4675 int addr_count;
4676 u16 *ids;
4677 int rc;
4678
4679 if (multicast) {
4680 addr_list = table->dev_mc_list;
4681 addr_count = table->dev_mc_count;
4682 ids = vlan->mc;
4683 } else {
4684 addr_list = table->dev_uc_list;
4685 addr_count = table->dev_uc_count;
4686 ids = vlan->uc;
4687 }
4688
4689 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4690
4691 /* Insert/renew filters */
4692 for (i = 0; i < addr_count; i++) {
4693 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
4694 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
4695 rc = efx_ef10_filter_insert(efx, &spec, true);
4696 if (rc < 0) {
4697 if (rollback) {
4698 netif_info(efx, drv, efx->net_dev,
4699 "efx_ef10_filter_insert failed rc=%d\n",
4700 rc);
4701 /* Fall back to promiscuous */
4702 for (j = 0; j < i; j++) {
4703 efx_ef10_filter_remove_unsafe(
4704 efx, EFX_FILTER_PRI_AUTO,
4705 ids[j]);
4706 ids[j] = EFX_EF10_FILTER_ID_INVALID;
4707 }
4708 return rc;
4709 } else {
4710 /* mark as not inserted, and carry on */
4711 rc = EFX_EF10_FILTER_ID_INVALID;
4712 }
4713 }
4714 ids[i] = efx_ef10_filter_get_unsafe_id(efx, rc);
4715 }
4716
4717 if (multicast && rollback) {
4718 /* Also need an Ethernet broadcast filter */
4719 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
4720 eth_broadcast_addr(baddr);
4721 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
4722 rc = efx_ef10_filter_insert(efx, &spec, true);
4723 if (rc < 0) {
4724 netif_warn(efx, drv, efx->net_dev,
4725 "Broadcast filter insert failed rc=%d\n", rc);
4726 /* Fall back to promiscuous */
4727 for (j = 0; j < i; j++) {
4728 efx_ef10_filter_remove_unsafe(
4729 efx, EFX_FILTER_PRI_AUTO,
4730 ids[j]);
4731 ids[j] = EFX_EF10_FILTER_ID_INVALID;
4732 }
4733 return rc;
4734 } else {
4735 EFX_WARN_ON_PARANOID(vlan->bcast !=
4736 EFX_EF10_FILTER_ID_INVALID);
4737 vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc);
4738 }
4739 }
4740
4741 return 0;
4742}
4743
4744static int efx_ef10_filter_insert_def(struct efx_nic *efx,
4745 struct efx_ef10_filter_vlan *vlan,
4746 bool multicast, bool rollback)
4747{
4748 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4749 enum efx_filter_flags filter_flags;
4750 struct efx_filter_spec spec;
4751 u8 baddr[ETH_ALEN];
4752 int rc;
4753
4754 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4755
4756 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
4757
4758 if (multicast)
4759 efx_filter_set_mc_def(&spec);
4760 else
4761 efx_filter_set_uc_def(&spec);
4762
4763 if (vlan->vid != EFX_FILTER_VID_UNSPEC)
4764 efx_filter_set_eth_local(&spec, vlan->vid, NULL);
4765
4766 rc = efx_ef10_filter_insert(efx, &spec, true);
4767 if (rc < 0) {
4768 netif_printk(efx, drv, rc == -EPERM ? KERN_DEBUG : KERN_WARNING,
4769 efx->net_dev,
4770 "%scast mismatch filter insert failed rc=%d\n",
4771 multicast ? "Multi" : "Uni", rc);
4772 } else if (multicast) {
4773 EFX_WARN_ON_PARANOID(vlan->mcdef != EFX_EF10_FILTER_ID_INVALID);
4774 vlan->mcdef = efx_ef10_filter_get_unsafe_id(efx, rc);
4775 if (!nic_data->workaround_26807) {
4776 /* Also need an Ethernet broadcast filter */
4777 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
4778 filter_flags, 0);
4779 eth_broadcast_addr(baddr);
4780 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
4781 rc = efx_ef10_filter_insert(efx, &spec, true);
4782 if (rc < 0) {
4783 netif_warn(efx, drv, efx->net_dev,
4784 "Broadcast filter insert failed rc=%d\n",
4785 rc);
4786 if (rollback) {
4787 /* Roll back the mc_def filter */
4788 efx_ef10_filter_remove_unsafe(
4789 efx, EFX_FILTER_PRI_AUTO,
4790 vlan->mcdef);
4791 vlan->mcdef = EFX_EF10_FILTER_ID_INVALID;
4792 return rc;
4793 }
4794 } else {
4795 EFX_WARN_ON_PARANOID(vlan->bcast !=
4796 EFX_EF10_FILTER_ID_INVALID);
4797 vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc);
4798 }
4799 }
4800 rc = 0;
4801 } else {
4802 EFX_WARN_ON_PARANOID(vlan->ucdef != EFX_EF10_FILTER_ID_INVALID);
4803 vlan->ucdef = rc;
4804 rc = 0;
4805 }
4806 return rc;
4807}
4808
4809/* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
4810 * flag or removes these filters, we don't need to hold the filter_lock while
4811 * scanning for these filters.
4812 */
4813static void efx_ef10_filter_remove_old(struct efx_nic *efx)
4814{
4815 struct efx_ef10_filter_table *table = efx->filter_state;
4816 int remove_failed = 0;
4817 int remove_noent = 0;
4818 int rc;
4819 int i;
4820
4821 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4822 if (ACCESS_ONCE(table->entry[i].spec) &
4823 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
4824 rc = efx_ef10_filter_remove_internal(efx,
4825 1U << EFX_FILTER_PRI_AUTO, i, true);
4826 if (rc == -ENOENT)
4827 remove_noent++;
4828 else if (rc)
4829 remove_failed++;
4830 }
4831 }
4832
4833 if (remove_failed)
4834 netif_info(efx, drv, efx->net_dev,
4835 "%s: failed to remove %d filters\n",
4836 __func__, remove_failed);
4837 if (remove_noent)
4838 netif_info(efx, drv, efx->net_dev,
4839 "%s: failed to remove %d non-existent filters\n",
4840 __func__, remove_noent);
4841}
4842
4843static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
4844{
4845 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4846 u8 mac_old[ETH_ALEN];
4847 int rc, rc2;
4848
4849 /* Only reconfigure a PF-created vport */
4850 if (is_zero_ether_addr(nic_data->vport_mac))
4851 return 0;
4852
4853 efx_device_detach_sync(efx);
4854 efx_net_stop(efx->net_dev);
4855 down_write(&efx->filter_sem);
4856 efx_ef10_filter_table_remove(efx);
4857 up_write(&efx->filter_sem);
4858
4859 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
4860 if (rc)
4861 goto restore_filters;
4862
4863 ether_addr_copy(mac_old, nic_data->vport_mac);
4864 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
4865 nic_data->vport_mac);
4866 if (rc)
4867 goto restore_vadaptor;
4868
4869 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
4870 efx->net_dev->dev_addr);
4871 if (!rc) {
4872 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
4873 } else {
4874 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
4875 if (rc2) {
4876 /* Failed to add original MAC, so clear vport_mac */
4877 eth_zero_addr(nic_data->vport_mac);
4878 goto reset_nic;
4879 }
4880 }
4881
4882restore_vadaptor:
4883 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
4884 if (rc2)
4885 goto reset_nic;
4886restore_filters:
4887 down_write(&efx->filter_sem);
4888 rc2 = efx_ef10_filter_table_probe(efx);
4889 up_write(&efx->filter_sem);
4890 if (rc2)
4891 goto reset_nic;
4892
4893 rc2 = efx_net_open(efx->net_dev);
4894 if (rc2)
4895 goto reset_nic;
4896
4897 netif_device_attach(efx->net_dev);
4898
4899 return rc;
4900
4901reset_nic:
4902 netif_err(efx, drv, efx->net_dev,
4903 "Failed to restore when changing MAC address - scheduling reset\n");
4904 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
4905
4906 return rc ? rc : rc2;
4907}
4908
4909/* Caller must hold efx->filter_sem for read if race against
4910 * efx_ef10_filter_table_remove() is possible
4911 */
4912static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
4913 struct efx_ef10_filter_vlan *vlan)
4914{
4915 struct efx_ef10_filter_table *table = efx->filter_state;
4916 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4917
4918 /* Do not install unspecified VID if VLAN filtering is enabled.
4919 * Do not install all specified VIDs if VLAN filtering is disabled.
4920 */
4921 if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
4922 return;
4923
4924 /* Insert/renew unicast filters */
4925 if (table->uc_promisc) {
4926 efx_ef10_filter_insert_def(efx, vlan, false, false);
4927 efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
4928 } else {
4929 /* If any of the filters failed to insert, fall back to
4930 * promiscuous mode - add in the uc_def filter. But keep
4931 * our individual unicast filters.
4932 */
4933 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
4934 efx_ef10_filter_insert_def(efx, vlan, false, false);
4935 }
4936
4937 /* Insert/renew multicast filters */
4938 /* If changing promiscuous state with cascaded multicast filters, remove
4939 * old filters first, so that packets are dropped rather than duplicated
4940 */
4941 if (nic_data->workaround_26807 &&
4942 table->mc_promisc_last != table->mc_promisc)
4943 efx_ef10_filter_remove_old(efx);
4944 if (table->mc_promisc) {
4945 if (nic_data->workaround_26807) {
4946 /* If we failed to insert promiscuous filters, rollback
4947 * and fall back to individual multicast filters
4948 */
4949 if (efx_ef10_filter_insert_def(efx, vlan, true, true)) {
4950 /* Changing promisc state, so remove old filters */
4951 efx_ef10_filter_remove_old(efx);
4952 efx_ef10_filter_insert_addr_list(efx, vlan,
4953 true, false);
4954 }
4955 } else {
4956 /* If we failed to insert promiscuous filters, don't
4957 * rollback. Regardless, also insert the mc_list
4958 */
4959 efx_ef10_filter_insert_def(efx, vlan, true, false);
4960 efx_ef10_filter_insert_addr_list(efx, vlan, true, false);
4961 }
4962 } else {
4963 /* If any filters failed to insert, rollback and fall back to
4964 * promiscuous mode - mc_def filter and maybe broadcast. If
4965 * that fails, roll back again and insert as many of our
4966 * individual multicast filters as we can.
4967 */
4968 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
4969 /* Changing promisc state, so remove old filters */
4970 if (nic_data->workaround_26807)
4971 efx_ef10_filter_remove_old(efx);
4972 if (efx_ef10_filter_insert_def(efx, vlan, true, true))
4973 efx_ef10_filter_insert_addr_list(efx, vlan,
4974 true, false);
4975 }
4976 }
4977}
4978
4979/* Caller must hold efx->filter_sem for read if race against
4980 * efx_ef10_filter_table_remove() is possible
4981 */
4982static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
4983{
4984 struct efx_ef10_filter_table *table = efx->filter_state;
4985 struct net_device *net_dev = efx->net_dev;
4986 struct efx_ef10_filter_vlan *vlan;
4987 bool vlan_filter;
4988
4989 if (!efx_dev_registered(efx))
4990 return;
4991
4992 if (!table)
4993 return;
4994
4995 efx_ef10_filter_mark_old(efx);
4996
4997 /* Copy/convert the address lists; add the primary station
4998 * address and broadcast address
4999 */
5000 netif_addr_lock_bh(net_dev);
5001 efx_ef10_filter_uc_addr_list(efx);
5002 efx_ef10_filter_mc_addr_list(efx);
5003 netif_addr_unlock_bh(net_dev);
5004
5005 /* If VLAN filtering changes, all old filters are finally removed.
5006 * Do it in advance to avoid conflicts for unicast untagged and
5007 * VLAN 0 tagged filters.
5008 */
5009 vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
5010 if (table->vlan_filter != vlan_filter) {
5011 table->vlan_filter = vlan_filter;
5012 efx_ef10_filter_remove_old(efx);
5013 }
5014
5015 list_for_each_entry(vlan, &table->vlan_list, list)
5016 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5017
5018 efx_ef10_filter_remove_old(efx);
5019 table->mc_promisc_last = table->mc_promisc;
5020}
5021
5022static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
5023{
5024 struct efx_ef10_filter_table *table = efx->filter_state;
5025 struct efx_ef10_filter_vlan *vlan;
5026
5027 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
5028
5029 list_for_each_entry(vlan, &table->vlan_list, list) {
5030 if (vlan->vid == vid)
5031 return vlan;
5032 }
5033
5034 return NULL;
5035}
5036
5037static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
5038{
5039 struct efx_ef10_filter_table *table = efx->filter_state;
5040 struct efx_ef10_filter_vlan *vlan;
5041 unsigned int i;
5042
5043 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5044 return -EINVAL;
5045
5046 vlan = efx_ef10_filter_find_vlan(efx, vid);
5047 if (WARN_ON(vlan)) {
5048 netif_err(efx, drv, efx->net_dev,
5049 "VLAN %u already added\n", vid);
5050 return -EALREADY;
5051 }
5052
5053 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
5054 if (!vlan)
5055 return -ENOMEM;
5056
5057 vlan->vid = vid;
5058
5059 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5060 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
5061 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5062 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
5063 vlan->ucdef = EFX_EF10_FILTER_ID_INVALID;
5064 vlan->bcast = EFX_EF10_FILTER_ID_INVALID;
5065 vlan->mcdef = EFX_EF10_FILTER_ID_INVALID;
5066
5067 list_add_tail(&vlan->list, &table->vlan_list);
5068
5069 if (efx_dev_registered(efx))
5070 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5071
5072 return 0;
5073}
5074
5075static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
5076 struct efx_ef10_filter_vlan *vlan)
5077{
5078 unsigned int i;
5079
5080 /* See comment in efx_ef10_filter_table_remove() */
5081 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5082 return;
5083
5084 list_del(&vlan->list);
5085
5086 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5087 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5088 vlan->uc[i]);
5089 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5090 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5091 vlan->mc[i]);
5092 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->ucdef);
5093 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->bcast);
5094 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->mcdef);
5095
5096 kfree(vlan);
5097}
5098
5099static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
5100{
5101 struct efx_ef10_filter_vlan *vlan;
5102
5103 /* See comment in efx_ef10_filter_table_remove() */
5104 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5105 return;
5106
5107 vlan = efx_ef10_filter_find_vlan(efx, vid);
5108 if (!vlan) {
5109 netif_err(efx, drv, efx->net_dev,
5110 "VLAN %u not found in filter state\n", vid);
5111 return;
5112 }
5113
5114 efx_ef10_filter_del_vlan_internal(efx, vlan);
5115}
5116
5117static int efx_ef10_set_mac_address(struct efx_nic *efx)
5118{
5119 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
5120 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5121 bool was_enabled = efx->port_enabled;
5122 int rc;
5123
5124 efx_device_detach_sync(efx);
5125 efx_net_stop(efx->net_dev);
5126
5127 mutex_lock(&efx->mac_lock);
5128 down_write(&efx->filter_sem);
5129 efx_ef10_filter_table_remove(efx);
5130
5131 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
5132 efx->net_dev->dev_addr);
5133 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
5134 nic_data->vport_id);
5135 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
5136 sizeof(inbuf), NULL, 0, NULL);
5137
5138 efx_ef10_filter_table_probe(efx);
5139 up_write(&efx->filter_sem);
5140 mutex_unlock(&efx->mac_lock);
5141
5142 if (was_enabled)
5143 efx_net_open(efx->net_dev);
5144 netif_device_attach(efx->net_dev);
5145
5146#ifdef CONFIG_SFC_SRIOV
5147 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
5148 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
5149
5150 if (rc == -EPERM) {
5151 struct efx_nic *efx_pf;
5152
5153 /* Switch to PF and change MAC address on vport */
5154 efx_pf = pci_get_drvdata(pci_dev_pf);
5155
5156 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
5157 nic_data->vf_index,
5158 efx->net_dev->dev_addr);
5159 } else if (!rc) {
5160 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
5161 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
5162 unsigned int i;
5163
5164 /* MAC address successfully changed by VF (with MAC
5165 * spoofing) so update the parent PF if possible.
5166 */
5167 for (i = 0; i < efx_pf->vf_count; ++i) {
5168 struct ef10_vf *vf = nic_data->vf + i;
5169
5170 if (vf->efx == efx) {
5171 ether_addr_copy(vf->mac,
5172 efx->net_dev->dev_addr);
5173 return 0;
5174 }
5175 }
5176 }
5177 } else
5178#endif
5179 if (rc == -EPERM) {
5180 netif_err(efx, drv, efx->net_dev,
5181 "Cannot change MAC address; use sfboot to enable"
5182 " mac-spoofing on this interface\n");
5183 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
5184 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
5185 * fall-back to the method of changing the MAC address on the
5186 * vport. This only applies to PFs because such versions of
5187 * MCFW do not support VFs.
5188 */
5189 rc = efx_ef10_vport_set_mac_address(efx);
5190 } else {
5191 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
5192 sizeof(inbuf), NULL, 0, rc);
5193 }
5194
5195 return rc;
5196}
5197
5198static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
5199{
5200 efx_ef10_filter_sync_rx_mode(efx);
5201
5202 return efx_mcdi_set_mac(efx);
5203}
5204
5205static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
5206{
5207 efx_ef10_filter_sync_rx_mode(efx);
5208
5209 return 0;
5210}
5211
5212static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
5213{
5214 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
5215
5216 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
5217 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
5218 NULL, 0, NULL);
5219}
5220
5221/* MC BISTs follow a different poll mechanism to phy BISTs.
5222 * The BIST is done in the poll handler on the MC, and the MCDI command
5223 * will block until the BIST is done.
5224 */
5225static int efx_ef10_poll_bist(struct efx_nic *efx)
5226{
5227 int rc;
5228 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
5229 size_t outlen;
5230 u32 result;
5231
5232 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
5233 outbuf, sizeof(outbuf), &outlen);
5234 if (rc != 0)
5235 return rc;
5236
5237 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
5238 return -EIO;
5239
5240 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
5241 switch (result) {
5242 case MC_CMD_POLL_BIST_PASSED:
5243 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
5244 return 0;
5245 case MC_CMD_POLL_BIST_TIMEOUT:
5246 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
5247 return -EIO;
5248 case MC_CMD_POLL_BIST_FAILED:
5249 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
5250 return -EIO;
5251 default:
5252 netif_err(efx, hw, efx->net_dev,
5253 "BIST returned unknown result %u", result);
5254 return -EIO;
5255 }
5256}
5257
5258static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
5259{
5260 int rc;
5261
5262 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
5263
5264 rc = efx_ef10_start_bist(efx, bist_type);
5265 if (rc != 0)
5266 return rc;
5267
5268 return efx_ef10_poll_bist(efx);
5269}
5270
5271static int
5272efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
5273{
5274 int rc, rc2;
5275
5276 efx_reset_down(efx, RESET_TYPE_WORLD);
5277
5278 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
5279 NULL, 0, NULL, 0, NULL);
5280 if (rc != 0)
5281 goto out;
5282
5283 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
5284 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
5285
5286 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
5287
5288out:
5289 if (rc == -EPERM)
5290 rc = 0;
5291 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
5292 return rc ? rc : rc2;
5293}
5294
5295#ifdef CONFIG_SFC_MTD
5296
5297struct efx_ef10_nvram_type_info {
5298 u16 type, type_mask;
5299 u8 port;
5300 const char *name;
5301};
5302
5303static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
5304 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
5305 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
5306 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
5307 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
5308 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
5309 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
5310 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
5311 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
5312 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
5313 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
5314 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
5315};
5316
5317static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
5318 struct efx_mcdi_mtd_partition *part,
5319 unsigned int type)
5320{
5321 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
5322 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
5323 const struct efx_ef10_nvram_type_info *info;
5324 size_t size, erase_size, outlen;
5325 bool protected;
5326 int rc;
5327
5328 for (info = efx_ef10_nvram_types; ; info++) {
5329 if (info ==
5330 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
5331 return -ENODEV;
5332 if ((type & ~info->type_mask) == info->type)
5333 break;
5334 }
5335 if (info->port != efx_port_num(efx))
5336 return -ENODEV;
5337
5338 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
5339 if (rc)
5340 return rc;
5341 if (protected)
5342 return -ENODEV; /* hide it */
5343
5344 part->nvram_type = type;
5345
5346 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
5347 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
5348 outbuf, sizeof(outbuf), &outlen);
5349 if (rc)
5350 return rc;
5351 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
5352 return -EIO;
5353 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
5354 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
5355 part->fw_subtype = MCDI_DWORD(outbuf,
5356 NVRAM_METADATA_OUT_SUBTYPE);
5357
5358 part->common.dev_type_name = "EF10 NVRAM manager";
5359 part->common.type_name = info->name;
5360
5361 part->common.mtd.type = MTD_NORFLASH;
5362 part->common.mtd.flags = MTD_CAP_NORFLASH;
5363 part->common.mtd.size = size;
5364 part->common.mtd.erasesize = erase_size;
5365
5366 return 0;
5367}
5368
5369static int efx_ef10_mtd_probe(struct efx_nic *efx)
5370{
5371 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
5372 struct efx_mcdi_mtd_partition *parts;
5373 size_t outlen, n_parts_total, i, n_parts;
5374 unsigned int type;
5375 int rc;
5376
5377 ASSERT_RTNL();
5378
5379 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
5380 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
5381 outbuf, sizeof(outbuf), &outlen);
5382 if (rc)
5383 return rc;
5384 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
5385 return -EIO;
5386
5387 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
5388 if (n_parts_total >
5389 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
5390 return -EIO;
5391
5392 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
5393 if (!parts)
5394 return -ENOMEM;
5395
5396 n_parts = 0;
5397 for (i = 0; i < n_parts_total; i++) {
5398 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
5399 i);
5400 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
5401 if (rc == 0)
5402 n_parts++;
5403 else if (rc != -ENODEV)
5404 goto fail;
5405 }
5406
5407 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
5408fail:
5409 if (rc)
5410 kfree(parts);
5411 return rc;
5412}
5413
5414#endif /* CONFIG_SFC_MTD */
5415
5416static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
5417{
5418 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
5419}
5420
5421static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
5422 u32 host_time) {}
5423
5424static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
5425 bool temp)
5426{
5427 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
5428 int rc;
5429
5430 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
5431 channel->sync_events_state == SYNC_EVENTS_VALID ||
5432 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
5433 return 0;
5434 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
5435
5436 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
5437 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5438 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
5439 channel->channel);
5440
5441 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5442 inbuf, sizeof(inbuf), NULL, 0, NULL);
5443
5444 if (rc != 0)
5445 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5446 SYNC_EVENTS_DISABLED;
5447
5448 return rc;
5449}
5450
5451static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
5452 bool temp)
5453{
5454 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
5455 int rc;
5456
5457 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
5458 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
5459 return 0;
5460 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
5461 channel->sync_events_state = SYNC_EVENTS_DISABLED;
5462 return 0;
5463 }
5464 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5465 SYNC_EVENTS_DISABLED;
5466
5467 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
5468 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5469 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
5470 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
5471 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
5472 channel->channel);
5473
5474 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5475 inbuf, sizeof(inbuf), NULL, 0, NULL);
5476
5477 return rc;
5478}
5479
5480static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
5481 bool temp)
5482{
5483 int (*set)(struct efx_channel *channel, bool temp);
5484 struct efx_channel *channel;
5485
5486 set = en ?
5487 efx_ef10_rx_enable_timestamping :
5488 efx_ef10_rx_disable_timestamping;
5489
5490 efx_for_each_channel(channel, efx) {
5491 int rc = set(channel, temp);
5492 if (en && rc != 0) {
5493 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
5494 return rc;
5495 }
5496 }
5497
5498 return 0;
5499}
5500
5501static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
5502 struct hwtstamp_config *init)
5503{
5504 return -EOPNOTSUPP;
5505}
5506
5507static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
5508 struct hwtstamp_config *init)
5509{
5510 int rc;
5511
5512 switch (init->rx_filter) {
5513 case HWTSTAMP_FILTER_NONE:
5514 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
5515 /* if TX timestamping is still requested then leave PTP on */
5516 return efx_ptp_change_mode(efx,
5517 init->tx_type != HWTSTAMP_TX_OFF, 0);
5518 case HWTSTAMP_FILTER_ALL:
5519 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5520 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
5521 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
5522 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5523 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5524 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5525 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5526 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5527 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5528 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5529 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5530 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5531 init->rx_filter = HWTSTAMP_FILTER_ALL;
5532 rc = efx_ptp_change_mode(efx, true, 0);
5533 if (!rc)
5534 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
5535 if (rc)
5536 efx_ptp_change_mode(efx, false, 0);
5537 return rc;
5538 default:
5539 return -ERANGE;
5540 }
5541}
5542
5543static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
5544{
5545 if (proto != htons(ETH_P_8021Q))
5546 return -EINVAL;
5547
5548 return efx_ef10_add_vlan(efx, vid);
5549}
5550
5551static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
5552{
5553 if (proto != htons(ETH_P_8021Q))
5554 return -EINVAL;
5555
5556 return efx_ef10_del_vlan(efx, vid);
5557}
5558
5559#define EF10_OFFLOAD_FEATURES \
5560 (NETIF_F_IP_CSUM | \
5561 NETIF_F_HW_VLAN_CTAG_FILTER | \
5562 NETIF_F_IPV6_CSUM | \
5563 NETIF_F_RXHASH | \
5564 NETIF_F_NTUPLE)
5565
5566const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
5567 .is_vf = true,
5568 .mem_bar = EFX_MEM_VF_BAR,
5569 .mem_map_size = efx_ef10_mem_map_size,
5570 .probe = efx_ef10_probe_vf,
5571 .remove = efx_ef10_remove,
5572 .dimension_resources = efx_ef10_dimension_resources,
5573 .init = efx_ef10_init_nic,
5574 .fini = efx_port_dummy_op_void,
5575 .map_reset_reason = efx_ef10_map_reset_reason,
5576 .map_reset_flags = efx_ef10_map_reset_flags,
5577 .reset = efx_ef10_reset,
5578 .probe_port = efx_mcdi_port_probe,
5579 .remove_port = efx_mcdi_port_remove,
5580 .fini_dmaq = efx_ef10_fini_dmaq,
5581 .prepare_flr = efx_ef10_prepare_flr,
5582 .finish_flr = efx_port_dummy_op_void,
5583 .describe_stats = efx_ef10_describe_stats,
5584 .update_stats = efx_ef10_update_stats_vf,
5585 .start_stats = efx_port_dummy_op_void,
5586 .pull_stats = efx_port_dummy_op_void,
5587 .stop_stats = efx_port_dummy_op_void,
5588 .set_id_led = efx_mcdi_set_id_led,
5589 .push_irq_moderation = efx_ef10_push_irq_moderation,
5590 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
5591 .check_mac_fault = efx_mcdi_mac_check_fault,
5592 .reconfigure_port = efx_mcdi_port_reconfigure,
5593 .get_wol = efx_ef10_get_wol_vf,
5594 .set_wol = efx_ef10_set_wol_vf,
5595 .resume_wol = efx_port_dummy_op_void,
5596 .mcdi_request = efx_ef10_mcdi_request,
5597 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
5598 .mcdi_read_response = efx_ef10_mcdi_read_response,
5599 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
5600 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
5601 .irq_enable_master = efx_port_dummy_op_void,
5602 .irq_test_generate = efx_ef10_irq_test_generate,
5603 .irq_disable_non_ev = efx_port_dummy_op_void,
5604 .irq_handle_msi = efx_ef10_msi_interrupt,
5605 .irq_handle_legacy = efx_ef10_legacy_interrupt,
5606 .tx_probe = efx_ef10_tx_probe,
5607 .tx_init = efx_ef10_tx_init,
5608 .tx_remove = efx_ef10_tx_remove,
5609 .tx_write = efx_ef10_tx_write,
5610 .tx_limit_len = efx_ef10_tx_limit_len,
5611 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
5612 .rx_probe = efx_ef10_rx_probe,
5613 .rx_init = efx_ef10_rx_init,
5614 .rx_remove = efx_ef10_rx_remove,
5615 .rx_write = efx_ef10_rx_write,
5616 .rx_defer_refill = efx_ef10_rx_defer_refill,
5617 .ev_probe = efx_ef10_ev_probe,
5618 .ev_init = efx_ef10_ev_init,
5619 .ev_fini = efx_ef10_ev_fini,
5620 .ev_remove = efx_ef10_ev_remove,
5621 .ev_process = efx_ef10_ev_process,
5622 .ev_read_ack = efx_ef10_ev_read_ack,
5623 .ev_test_generate = efx_ef10_ev_test_generate,
5624 .filter_table_probe = efx_ef10_filter_table_probe,
5625 .filter_table_restore = efx_ef10_filter_table_restore,
5626 .filter_table_remove = efx_ef10_filter_table_remove,
5627 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
5628 .filter_insert = efx_ef10_filter_insert,
5629 .filter_remove_safe = efx_ef10_filter_remove_safe,
5630 .filter_get_safe = efx_ef10_filter_get_safe,
5631 .filter_clear_rx = efx_ef10_filter_clear_rx,
5632 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
5633 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
5634 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
5635#ifdef CONFIG_RFS_ACCEL
5636 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
5637 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
5638#endif
5639#ifdef CONFIG_SFC_MTD
5640 .mtd_probe = efx_port_dummy_op_int,
5641#endif
5642 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
5643 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
5644 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
5645 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
5646#ifdef CONFIG_SFC_SRIOV
5647 .vswitching_probe = efx_ef10_vswitching_probe_vf,
5648 .vswitching_restore = efx_ef10_vswitching_restore_vf,
5649 .vswitching_remove = efx_ef10_vswitching_remove_vf,
5650 .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id,
5651#endif
5652 .get_mac_address = efx_ef10_get_mac_address_vf,
5653 .set_mac_address = efx_ef10_set_mac_address,
5654
5655 .revision = EFX_REV_HUNT_A0,
5656 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
5657 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
5658 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
5659 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
5660 .can_rx_scatter = true,
5661 .always_rx_scatter = true,
5662 .max_interrupt_mode = EFX_INT_MODE_MSIX,
5663 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
5664 .offload_features = EF10_OFFLOAD_FEATURES,
5665 .mcdi_max_ver = 2,
5666 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
5667 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
5668 1 << HWTSTAMP_FILTER_ALL,
5669};
5670
5671const struct efx_nic_type efx_hunt_a0_nic_type = {
5672 .is_vf = false,
5673 .mem_bar = EFX_MEM_BAR,
5674 .mem_map_size = efx_ef10_mem_map_size,
5675 .probe = efx_ef10_probe_pf,
5676 .remove = efx_ef10_remove,
5677 .dimension_resources = efx_ef10_dimension_resources,
5678 .init = efx_ef10_init_nic,
5679 .fini = efx_port_dummy_op_void,
5680 .map_reset_reason = efx_ef10_map_reset_reason,
5681 .map_reset_flags = efx_ef10_map_reset_flags,
5682 .reset = efx_ef10_reset,
5683 .probe_port = efx_mcdi_port_probe,
5684 .remove_port = efx_mcdi_port_remove,
5685 .fini_dmaq = efx_ef10_fini_dmaq,
5686 .prepare_flr = efx_ef10_prepare_flr,
5687 .finish_flr = efx_port_dummy_op_void,
5688 .describe_stats = efx_ef10_describe_stats,
5689 .update_stats = efx_ef10_update_stats_pf,
5690 .start_stats = efx_mcdi_mac_start_stats,
5691 .pull_stats = efx_mcdi_mac_pull_stats,
5692 .stop_stats = efx_mcdi_mac_stop_stats,
5693 .set_id_led = efx_mcdi_set_id_led,
5694 .push_irq_moderation = efx_ef10_push_irq_moderation,
5695 .reconfigure_mac = efx_ef10_mac_reconfigure,
5696 .check_mac_fault = efx_mcdi_mac_check_fault,
5697 .reconfigure_port = efx_mcdi_port_reconfigure,
5698 .get_wol = efx_ef10_get_wol,
5699 .set_wol = efx_ef10_set_wol,
5700 .resume_wol = efx_port_dummy_op_void,
5701 .test_chip = efx_ef10_test_chip,
5702 .test_nvram = efx_mcdi_nvram_test_all,
5703 .mcdi_request = efx_ef10_mcdi_request,
5704 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
5705 .mcdi_read_response = efx_ef10_mcdi_read_response,
5706 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
5707 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
5708 .irq_enable_master = efx_port_dummy_op_void,
5709 .irq_test_generate = efx_ef10_irq_test_generate,
5710 .irq_disable_non_ev = efx_port_dummy_op_void,
5711 .irq_handle_msi = efx_ef10_msi_interrupt,
5712 .irq_handle_legacy = efx_ef10_legacy_interrupt,
5713 .tx_probe = efx_ef10_tx_probe,
5714 .tx_init = efx_ef10_tx_init,
5715 .tx_remove = efx_ef10_tx_remove,
5716 .tx_write = efx_ef10_tx_write,
5717 .tx_limit_len = efx_ef10_tx_limit_len,
5718 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
5719 .rx_probe = efx_ef10_rx_probe,
5720 .rx_init = efx_ef10_rx_init,
5721 .rx_remove = efx_ef10_rx_remove,
5722 .rx_write = efx_ef10_rx_write,
5723 .rx_defer_refill = efx_ef10_rx_defer_refill,
5724 .ev_probe = efx_ef10_ev_probe,
5725 .ev_init = efx_ef10_ev_init,
5726 .ev_fini = efx_ef10_ev_fini,
5727 .ev_remove = efx_ef10_ev_remove,
5728 .ev_process = efx_ef10_ev_process,
5729 .ev_read_ack = efx_ef10_ev_read_ack,
5730 .ev_test_generate = efx_ef10_ev_test_generate,
5731 .filter_table_probe = efx_ef10_filter_table_probe,
5732 .filter_table_restore = efx_ef10_filter_table_restore,
5733 .filter_table_remove = efx_ef10_filter_table_remove,
5734 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
5735 .filter_insert = efx_ef10_filter_insert,
5736 .filter_remove_safe = efx_ef10_filter_remove_safe,
5737 .filter_get_safe = efx_ef10_filter_get_safe,
5738 .filter_clear_rx = efx_ef10_filter_clear_rx,
5739 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
5740 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
5741 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
5742#ifdef CONFIG_RFS_ACCEL
5743 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
5744 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
5745#endif
5746#ifdef CONFIG_SFC_MTD
5747 .mtd_probe = efx_ef10_mtd_probe,
5748 .mtd_rename = efx_mcdi_mtd_rename,
5749 .mtd_read = efx_mcdi_mtd_read,
5750 .mtd_erase = efx_mcdi_mtd_erase,
5751 .mtd_write = efx_mcdi_mtd_write,
5752 .mtd_sync = efx_mcdi_mtd_sync,
5753#endif
5754 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
5755 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
5756 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
5757 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
5758 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
5759#ifdef CONFIG_SFC_SRIOV
5760 .sriov_configure = efx_ef10_sriov_configure,
5761 .sriov_init = efx_ef10_sriov_init,
5762 .sriov_fini = efx_ef10_sriov_fini,
5763 .sriov_wanted = efx_ef10_sriov_wanted,
5764 .sriov_reset = efx_ef10_sriov_reset,
5765 .sriov_flr = efx_ef10_sriov_flr,
5766 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
5767 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
5768 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
5769 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
5770 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
5771 .vswitching_probe = efx_ef10_vswitching_probe_pf,
5772 .vswitching_restore = efx_ef10_vswitching_restore_pf,
5773 .vswitching_remove = efx_ef10_vswitching_remove_pf,
5774#endif
5775 .get_mac_address = efx_ef10_get_mac_address_pf,
5776 .set_mac_address = efx_ef10_set_mac_address,
5777 .tso_versions = efx_ef10_tso_versions,
5778
5779 .revision = EFX_REV_HUNT_A0,
5780 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
5781 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
5782 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
5783 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
5784 .can_rx_scatter = true,
5785 .always_rx_scatter = true,
5786 .max_interrupt_mode = EFX_INT_MODE_MSIX,
5787 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
5788 .offload_features = EF10_OFFLOAD_FEATURES,
5789 .mcdi_max_ver = 2,
5790 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
5791 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
5792 1 << HWTSTAMP_FILTER_ALL,
5793};