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1/* winbond-840.c: A Linux PCI network adapter device driver. */
2/*
3 Written 1998-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 The author may be reached as becker@scyld.com, or C/O
13 Scyld Computing Corporation
14 410 Severn Ave., Suite 210
15 Annapolis MD 21403
16
17 Support and updates available at
18 http://www.scyld.com/network/drivers.html
19
20 Do not remove the copyright information.
21 Do not change the version information unless an improvement has been made.
22 Merely removing my name, as Compex has done in the past, does not count
23 as an improvement.
24
25 Changelog:
26 * ported to 2.4
27 ???
28 * spin lock update, memory barriers, new style dma mappings
29 limit each tx buffer to < 1024 bytes
30 remove DescIntr from Rx descriptors (that's an Tx flag)
31 remove next pointer from Tx descriptors
32 synchronize tx_q_bytes
33 software reset in tx_timeout
34 Copyright (C) 2000 Manfred Spraul
35 * further cleanups
36 power management.
37 support for big endian descriptors
38 Copyright (C) 2001 Manfred Spraul
39 * ethtool support (jgarzik)
40 * Replace some MII-related magic numbers with constants (jgarzik)
41
42 TODO:
43 * enable pci_power_off
44 * Wake-On-LAN
45*/
46
47#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
48
49#define DRV_NAME "winbond-840"
50
51/* Automatically extracted configuration info:
52probe-func: winbond840_probe
53config-in: tristate 'Winbond W89c840 Ethernet support' CONFIG_WINBOND_840
54
55c-help-name: Winbond W89c840 PCI Ethernet support
56c-help-symbol: CONFIG_WINBOND_840
57c-help: This driver is for the Winbond W89c840 chip. It also works with
58c-help: the TX9882 chip on the Compex RL100-ATX board.
59c-help: More specific information and updates are available from
60c-help: http://www.scyld.com/network/drivers.html
61*/
62
63/* The user-configurable values.
64 These may be modified when a driver module is loaded.*/
65
66static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
67static int max_interrupt_work = 20;
68/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
69 The '840 uses a 64 element hash table based on the Ethernet CRC. */
70static int multicast_filter_limit = 32;
71
72/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
73 Setting to > 1518 effectively disables this feature. */
74static int rx_copybreak;
75
76/* Used to pass the media type, etc.
77 Both 'options[]' and 'full_duplex[]' should exist for driver
78 interoperability.
79 The media type is usually passed in 'options[]'.
80*/
81#define MAX_UNITS 8 /* More are supported, limit only on options */
82static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
83static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
84
85/* Operational parameters that are set at compile time. */
86
87/* Keep the ring sizes a power of two for compile efficiency.
88 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
89 Making the Tx ring too large decreases the effectiveness of channel
90 bonding and packet priority.
91 There are no ill effects from too-large receive rings. */
92#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
93#define TX_QUEUE_LEN_RESTART 5
94
95#define TX_BUFLIMIT (1024-128)
96
97/* The presumed FIFO size for working around the Tx-FIFO-overflow bug.
98 To avoid overflowing we don't queue again until we have room for a
99 full-size packet.
100 */
101#define TX_FIFO_SIZE (2048)
102#define TX_BUG_FIFO_LIMIT (TX_FIFO_SIZE-1514-16)
103
104
105/* Operational parameters that usually are not changed. */
106/* Time in jiffies before concluding the transmitter is hung. */
107#define TX_TIMEOUT (2*HZ)
108
109/* Include files, designed to support most kernel versions 2.0.0 and later. */
110#include <linux/module.h>
111#include <linux/kernel.h>
112#include <linux/string.h>
113#include <linux/timer.h>
114#include <linux/errno.h>
115#include <linux/ioport.h>
116#include <linux/interrupt.h>
117#include <linux/pci.h>
118#include <linux/dma-mapping.h>
119#include <linux/netdevice.h>
120#include <linux/etherdevice.h>
121#include <linux/skbuff.h>
122#include <linux/init.h>
123#include <linux/delay.h>
124#include <linux/ethtool.h>
125#include <linux/mii.h>
126#include <linux/rtnetlink.h>
127#include <linux/crc32.h>
128#include <linux/bitops.h>
129#include <linux/uaccess.h>
130#include <asm/processor.h> /* Processor type for cache alignment. */
131#include <asm/io.h>
132#include <asm/irq.h>
133
134#include "tulip.h"
135
136#undef PKT_BUF_SZ /* tulip.h also defines this */
137#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
138
139MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
140MODULE_DESCRIPTION("Winbond W89c840 Ethernet driver");
141MODULE_LICENSE("GPL");
142
143module_param(max_interrupt_work, int, 0);
144module_param(debug, int, 0);
145module_param(rx_copybreak, int, 0);
146module_param(multicast_filter_limit, int, 0);
147module_param_array(options, int, NULL, 0);
148module_param_array(full_duplex, int, NULL, 0);
149MODULE_PARM_DESC(max_interrupt_work, "winbond-840 maximum events handled per interrupt");
150MODULE_PARM_DESC(debug, "winbond-840 debug level (0-6)");
151MODULE_PARM_DESC(rx_copybreak, "winbond-840 copy breakpoint for copy-only-tiny-frames");
152MODULE_PARM_DESC(multicast_filter_limit, "winbond-840 maximum number of filtered multicast addresses");
153MODULE_PARM_DESC(options, "winbond-840: Bits 0-3: media type, bit 17: full duplex");
154MODULE_PARM_DESC(full_duplex, "winbond-840 full duplex setting(s) (1)");
155
156/*
157 Theory of Operation
158
159I. Board Compatibility
160
161This driver is for the Winbond w89c840 chip.
162
163II. Board-specific settings
164
165None.
166
167III. Driver operation
168
169This chip is very similar to the Digital 21*4* "Tulip" family. The first
170twelve registers and the descriptor format are nearly identical. Read a
171Tulip manual for operational details.
172
173A significant difference is that the multicast filter and station address are
174stored in registers rather than loaded through a pseudo-transmit packet.
175
176Unlike the Tulip, transmit buffers are limited to 1KB. To transmit a
177full-sized packet we must use both data buffers in a descriptor. Thus the
178driver uses ring mode where descriptors are implicitly sequential in memory,
179rather than using the second descriptor address as a chain pointer to
180subsequent descriptors.
181
182IV. Notes
183
184If you are going to almost clone a Tulip, why not go all the way and avoid
185the need for a new driver?
186
187IVb. References
188
189http://www.scyld.com/expert/100mbps.html
190http://www.scyld.com/expert/NWay.html
191http://www.winbond.com.tw/
192
193IVc. Errata
194
195A horrible bug exists in the transmit FIFO. Apparently the chip doesn't
196correctly detect a full FIFO, and queuing more than 2048 bytes may result in
197silent data corruption.
198
199Test with 'ping -s 10000' on a fast computer.
200
201*/
202
203
204
205/*
206 PCI probe table.
207*/
208enum chip_capability_flags {
209 CanHaveMII=1, HasBrokenTx=2, AlwaysFDX=4, FDXOnNoMII=8,
210};
211
212static const struct pci_device_id w840_pci_tbl[] = {
213 { 0x1050, 0x0840, PCI_ANY_ID, 0x8153, 0, 0, 0 },
214 { 0x1050, 0x0840, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
215 { 0x11f6, 0x2011, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
216 { }
217};
218MODULE_DEVICE_TABLE(pci, w840_pci_tbl);
219
220enum {
221 netdev_res_size = 128, /* size of PCI BAR resource */
222};
223
224struct pci_id_info {
225 const char *name;
226 int drv_flags; /* Driver use, intended as capability flags. */
227};
228
229static const struct pci_id_info pci_id_tbl[] = {
230 { /* Sometime a Level-One switch card. */
231 "Winbond W89c840", CanHaveMII | HasBrokenTx | FDXOnNoMII},
232 { "Winbond W89c840", CanHaveMII | HasBrokenTx},
233 { "Compex RL100-ATX", CanHaveMII | HasBrokenTx},
234 { } /* terminate list. */
235};
236
237/* This driver was written to use PCI memory space, however some x86 systems
238 work only with I/O space accesses. See CONFIG_TULIP_MMIO in .config
239*/
240
241/* Offsets to the Command and Status Registers, "CSRs".
242 While similar to the Tulip, these registers are longword aligned.
243 Note: It's not useful to define symbolic names for every register bit in
244 the device. The name can only partially document the semantics and make
245 the driver longer and more difficult to read.
246*/
247enum w840_offsets {
248 PCIBusCfg=0x00, TxStartDemand=0x04, RxStartDemand=0x08,
249 RxRingPtr=0x0C, TxRingPtr=0x10,
250 IntrStatus=0x14, NetworkConfig=0x18, IntrEnable=0x1C,
251 RxMissed=0x20, EECtrl=0x24, MIICtrl=0x24, BootRom=0x28, GPTimer=0x2C,
252 CurRxDescAddr=0x30, CurRxBufAddr=0x34, /* Debug use */
253 MulticastFilter0=0x38, MulticastFilter1=0x3C, StationAddr=0x40,
254 CurTxDescAddr=0x4C, CurTxBufAddr=0x50,
255};
256
257/* Bits in the NetworkConfig register. */
258enum rx_mode_bits {
259 AcceptErr=0x80,
260 RxAcceptBroadcast=0x20, AcceptMulticast=0x10,
261 RxAcceptAllPhys=0x08, AcceptMyPhys=0x02,
262};
263
264enum mii_reg_bits {
265 MDIO_ShiftClk=0x10000, MDIO_DataIn=0x80000, MDIO_DataOut=0x20000,
266 MDIO_EnbOutput=0x40000, MDIO_EnbIn = 0x00000,
267};
268
269/* The Tulip Rx and Tx buffer descriptors. */
270struct w840_rx_desc {
271 s32 status;
272 s32 length;
273 u32 buffer1;
274 u32 buffer2;
275};
276
277struct w840_tx_desc {
278 s32 status;
279 s32 length;
280 u32 buffer1, buffer2;
281};
282
283#define MII_CNT 1 /* winbond only supports one MII */
284struct netdev_private {
285 struct w840_rx_desc *rx_ring;
286 dma_addr_t rx_addr[RX_RING_SIZE];
287 struct w840_tx_desc *tx_ring;
288 dma_addr_t tx_addr[TX_RING_SIZE];
289 dma_addr_t ring_dma_addr;
290 /* The addresses of receive-in-place skbuffs. */
291 struct sk_buff* rx_skbuff[RX_RING_SIZE];
292 /* The saved address of a sent-in-place packet/buffer, for later free(). */
293 struct sk_buff* tx_skbuff[TX_RING_SIZE];
294 struct net_device_stats stats;
295 struct timer_list timer; /* Media monitoring timer. */
296 /* Frequently used values: keep some adjacent for cache effect. */
297 spinlock_t lock;
298 int chip_id, drv_flags;
299 struct pci_dev *pci_dev;
300 int csr6;
301 struct w840_rx_desc *rx_head_desc;
302 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
303 unsigned int rx_buf_sz; /* Based on MTU+slack. */
304 unsigned int cur_tx, dirty_tx;
305 unsigned int tx_q_bytes;
306 unsigned int tx_full; /* The Tx queue is full. */
307 /* MII transceiver section. */
308 int mii_cnt; /* MII device addresses. */
309 unsigned char phys[MII_CNT]; /* MII device addresses, but only the first is used */
310 u32 mii;
311 struct mii_if_info mii_if;
312 void __iomem *base_addr;
313};
314
315static int eeprom_read(void __iomem *ioaddr, int location);
316static int mdio_read(struct net_device *dev, int phy_id, int location);
317static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
318static int netdev_open(struct net_device *dev);
319static int update_link(struct net_device *dev);
320static void netdev_timer(struct timer_list *t);
321static void init_rxtx_rings(struct net_device *dev);
322static void free_rxtx_rings(struct netdev_private *np);
323static void init_registers(struct net_device *dev);
324static void tx_timeout(struct net_device *dev, unsigned int txqueue);
325static int alloc_ringdesc(struct net_device *dev);
326static void free_ringdesc(struct netdev_private *np);
327static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
328static irqreturn_t intr_handler(int irq, void *dev_instance);
329static void netdev_error(struct net_device *dev, int intr_status);
330static int netdev_rx(struct net_device *dev);
331static u32 __set_rx_mode(struct net_device *dev);
332static void set_rx_mode(struct net_device *dev);
333static struct net_device_stats *get_stats(struct net_device *dev);
334static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
335static const struct ethtool_ops netdev_ethtool_ops;
336static int netdev_close(struct net_device *dev);
337
338static const struct net_device_ops netdev_ops = {
339 .ndo_open = netdev_open,
340 .ndo_stop = netdev_close,
341 .ndo_start_xmit = start_tx,
342 .ndo_get_stats = get_stats,
343 .ndo_set_rx_mode = set_rx_mode,
344 .ndo_eth_ioctl = netdev_ioctl,
345 .ndo_tx_timeout = tx_timeout,
346 .ndo_set_mac_address = eth_mac_addr,
347 .ndo_validate_addr = eth_validate_addr,
348};
349
350static int w840_probe1(struct pci_dev *pdev, const struct pci_device_id *ent)
351{
352 struct net_device *dev;
353 struct netdev_private *np;
354 static int find_cnt;
355 int chip_idx = ent->driver_data;
356 int irq;
357 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
358 __le16 addr[ETH_ALEN / 2];
359 void __iomem *ioaddr;
360
361 i = pcim_enable_device(pdev);
362 if (i) return i;
363
364 pci_set_master(pdev);
365
366 irq = pdev->irq;
367
368 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
369 pr_warn("Device %s disabled due to DMA limitations\n",
370 pci_name(pdev));
371 return -EIO;
372 }
373 dev = alloc_etherdev(sizeof(*np));
374 if (!dev)
375 return -ENOMEM;
376 SET_NETDEV_DEV(dev, &pdev->dev);
377
378 if (pci_request_regions(pdev, DRV_NAME))
379 goto err_out_netdev;
380
381 ioaddr = pci_iomap(pdev, TULIP_BAR, netdev_res_size);
382 if (!ioaddr)
383 goto err_out_netdev;
384
385 for (i = 0; i < 3; i++)
386 addr[i] = cpu_to_le16(eeprom_read(ioaddr, i));
387 eth_hw_addr_set(dev, (u8 *)addr);
388
389 /* Reset the chip to erase previous misconfiguration.
390 No hold time required! */
391 iowrite32(0x00000001, ioaddr + PCIBusCfg);
392
393 np = netdev_priv(dev);
394 np->pci_dev = pdev;
395 np->chip_id = chip_idx;
396 np->drv_flags = pci_id_tbl[chip_idx].drv_flags;
397 spin_lock_init(&np->lock);
398 np->mii_if.dev = dev;
399 np->mii_if.mdio_read = mdio_read;
400 np->mii_if.mdio_write = mdio_write;
401 np->base_addr = ioaddr;
402
403 pci_set_drvdata(pdev, dev);
404
405 if (dev->mem_start)
406 option = dev->mem_start;
407
408 /* The lower four bits are the media type. */
409 if (option > 0) {
410 if (option & 0x200)
411 np->mii_if.full_duplex = 1;
412 if (option & 15)
413 dev_info(&dev->dev,
414 "ignoring user supplied media type %d",
415 option & 15);
416 }
417 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
418 np->mii_if.full_duplex = 1;
419
420 if (np->mii_if.full_duplex)
421 np->mii_if.force_media = 1;
422
423 /* The chip-specific entries in the device structure. */
424 dev->netdev_ops = &netdev_ops;
425 dev->ethtool_ops = &netdev_ethtool_ops;
426 dev->watchdog_timeo = TX_TIMEOUT;
427
428 i = register_netdev(dev);
429 if (i)
430 goto err_out_cleardev;
431
432 dev_info(&dev->dev, "%s at %p, %pM, IRQ %d\n",
433 pci_id_tbl[chip_idx].name, ioaddr, dev->dev_addr, irq);
434
435 if (np->drv_flags & CanHaveMII) {
436 int phy, phy_idx = 0;
437 for (phy = 1; phy < 32 && phy_idx < MII_CNT; phy++) {
438 int mii_status = mdio_read(dev, phy, MII_BMSR);
439 if (mii_status != 0xffff && mii_status != 0x0000) {
440 np->phys[phy_idx++] = phy;
441 np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
442 np->mii = (mdio_read(dev, phy, MII_PHYSID1) << 16)+
443 mdio_read(dev, phy, MII_PHYSID2);
444 dev_info(&dev->dev,
445 "MII PHY %08xh found at address %d, status 0x%04x advertising %04x\n",
446 np->mii, phy, mii_status,
447 np->mii_if.advertising);
448 }
449 }
450 np->mii_cnt = phy_idx;
451 np->mii_if.phy_id = np->phys[0];
452 if (phy_idx == 0) {
453 dev_warn(&dev->dev,
454 "MII PHY not found -- this device may not operate correctly\n");
455 }
456 }
457
458 find_cnt++;
459 return 0;
460
461err_out_cleardev:
462 pci_iounmap(pdev, ioaddr);
463err_out_netdev:
464 free_netdev (dev);
465 return -ENODEV;
466}
467
468
469/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. These are
470 often serial bit streams generated by the host processor.
471 The example below is for the common 93c46 EEPROM, 64 16 bit words. */
472
473/* Delay between EEPROM clock transitions.
474 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
475 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
476 made udelay() unreliable.
477*/
478#define eeprom_delay(ee_addr) ioread32(ee_addr)
479
480enum EEPROM_Ctrl_Bits {
481 EE_ShiftClk=0x02, EE_Write0=0x801, EE_Write1=0x805,
482 EE_ChipSelect=0x801, EE_DataIn=0x08,
483};
484
485/* The EEPROM commands include the alway-set leading bit. */
486enum EEPROM_Cmds {
487 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
488};
489
490static int eeprom_read(void __iomem *addr, int location)
491{
492 int i;
493 int retval = 0;
494 void __iomem *ee_addr = addr + EECtrl;
495 int read_cmd = location | EE_ReadCmd;
496 iowrite32(EE_ChipSelect, ee_addr);
497
498 /* Shift the read command bits out. */
499 for (i = 10; i >= 0; i--) {
500 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
501 iowrite32(dataval, ee_addr);
502 eeprom_delay(ee_addr);
503 iowrite32(dataval | EE_ShiftClk, ee_addr);
504 eeprom_delay(ee_addr);
505 }
506 iowrite32(EE_ChipSelect, ee_addr);
507 eeprom_delay(ee_addr);
508
509 for (i = 16; i > 0; i--) {
510 iowrite32(EE_ChipSelect | EE_ShiftClk, ee_addr);
511 eeprom_delay(ee_addr);
512 retval = (retval << 1) | ((ioread32(ee_addr) & EE_DataIn) ? 1 : 0);
513 iowrite32(EE_ChipSelect, ee_addr);
514 eeprom_delay(ee_addr);
515 }
516
517 /* Terminate the EEPROM access. */
518 iowrite32(0, ee_addr);
519 return retval;
520}
521
522/* MII transceiver control section.
523 Read and write the MII registers using software-generated serial
524 MDIO protocol. See the MII specifications or DP83840A data sheet
525 for details.
526
527 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
528 met by back-to-back 33Mhz PCI cycles. */
529#define mdio_delay(mdio_addr) ioread32(mdio_addr)
530
531/* Set iff a MII transceiver on any interface requires mdio preamble.
532 This only set with older transceivers, so the extra
533 code size of a per-interface flag is not worthwhile. */
534static char mii_preamble_required = 1;
535
536#define MDIO_WRITE0 (MDIO_EnbOutput)
537#define MDIO_WRITE1 (MDIO_DataOut | MDIO_EnbOutput)
538
539/* Generate the preamble required for initial synchronization and
540 a few older transceivers. */
541static void mdio_sync(void __iomem *mdio_addr)
542{
543 int bits = 32;
544
545 /* Establish sync by sending at least 32 logic ones. */
546 while (--bits >= 0) {
547 iowrite32(MDIO_WRITE1, mdio_addr);
548 mdio_delay(mdio_addr);
549 iowrite32(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
550 mdio_delay(mdio_addr);
551 }
552}
553
554static int mdio_read(struct net_device *dev, int phy_id, int location)
555{
556 struct netdev_private *np = netdev_priv(dev);
557 void __iomem *mdio_addr = np->base_addr + MIICtrl;
558 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
559 int i, retval = 0;
560
561 if (mii_preamble_required)
562 mdio_sync(mdio_addr);
563
564 /* Shift the read command bits out. */
565 for (i = 15; i >= 0; i--) {
566 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
567
568 iowrite32(dataval, mdio_addr);
569 mdio_delay(mdio_addr);
570 iowrite32(dataval | MDIO_ShiftClk, mdio_addr);
571 mdio_delay(mdio_addr);
572 }
573 /* Read the two transition, 16 data, and wire-idle bits. */
574 for (i = 20; i > 0; i--) {
575 iowrite32(MDIO_EnbIn, mdio_addr);
576 mdio_delay(mdio_addr);
577 retval = (retval << 1) | ((ioread32(mdio_addr) & MDIO_DataIn) ? 1 : 0);
578 iowrite32(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
579 mdio_delay(mdio_addr);
580 }
581 return (retval>>1) & 0xffff;
582}
583
584static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
585{
586 struct netdev_private *np = netdev_priv(dev);
587 void __iomem *mdio_addr = np->base_addr + MIICtrl;
588 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value;
589 int i;
590
591 if (location == 4 && phy_id == np->phys[0])
592 np->mii_if.advertising = value;
593
594 if (mii_preamble_required)
595 mdio_sync(mdio_addr);
596
597 /* Shift the command bits out. */
598 for (i = 31; i >= 0; i--) {
599 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
600
601 iowrite32(dataval, mdio_addr);
602 mdio_delay(mdio_addr);
603 iowrite32(dataval | MDIO_ShiftClk, mdio_addr);
604 mdio_delay(mdio_addr);
605 }
606 /* Clear out extra bits. */
607 for (i = 2; i > 0; i--) {
608 iowrite32(MDIO_EnbIn, mdio_addr);
609 mdio_delay(mdio_addr);
610 iowrite32(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
611 mdio_delay(mdio_addr);
612 }
613}
614
615
616static int netdev_open(struct net_device *dev)
617{
618 struct netdev_private *np = netdev_priv(dev);
619 void __iomem *ioaddr = np->base_addr;
620 const int irq = np->pci_dev->irq;
621 int i;
622
623 iowrite32(0x00000001, ioaddr + PCIBusCfg); /* Reset */
624
625 netif_device_detach(dev);
626 i = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev);
627 if (i)
628 goto out_err;
629
630 if (debug > 1)
631 netdev_dbg(dev, "%s() irq %d\n", __func__, irq);
632
633 i = alloc_ringdesc(dev);
634 if (i)
635 goto out_err;
636
637 spin_lock_irq(&np->lock);
638 netif_device_attach(dev);
639 init_registers(dev);
640 spin_unlock_irq(&np->lock);
641
642 netif_start_queue(dev);
643 if (debug > 2)
644 netdev_dbg(dev, "Done %s()\n", __func__);
645
646 /* Set the timer to check for link beat. */
647 timer_setup(&np->timer, netdev_timer, 0);
648 np->timer.expires = jiffies + 1*HZ;
649 add_timer(&np->timer);
650 return 0;
651out_err:
652 netif_device_attach(dev);
653 return i;
654}
655
656#define MII_DAVICOM_DM9101 0x0181b800
657
658static int update_link(struct net_device *dev)
659{
660 struct netdev_private *np = netdev_priv(dev);
661 int duplex, fasteth, result, mii_reg;
662
663 /* BSMR */
664 mii_reg = mdio_read(dev, np->phys[0], MII_BMSR);
665
666 if (mii_reg == 0xffff)
667 return np->csr6;
668 /* reread: the link status bit is sticky */
669 mii_reg = mdio_read(dev, np->phys[0], MII_BMSR);
670 if (!(mii_reg & 0x4)) {
671 if (netif_carrier_ok(dev)) {
672 if (debug)
673 dev_info(&dev->dev,
674 "MII #%d reports no link. Disabling watchdog\n",
675 np->phys[0]);
676 netif_carrier_off(dev);
677 }
678 return np->csr6;
679 }
680 if (!netif_carrier_ok(dev)) {
681 if (debug)
682 dev_info(&dev->dev,
683 "MII #%d link is back. Enabling watchdog\n",
684 np->phys[0]);
685 netif_carrier_on(dev);
686 }
687
688 if ((np->mii & ~0xf) == MII_DAVICOM_DM9101) {
689 /* If the link partner doesn't support autonegotiation
690 * the MII detects it's abilities with the "parallel detection".
691 * Some MIIs update the LPA register to the result of the parallel
692 * detection, some don't.
693 * The Davicom PHY [at least 0181b800] doesn't.
694 * Instead bit 9 and 13 of the BMCR are updated to the result
695 * of the negotiation..
696 */
697 mii_reg = mdio_read(dev, np->phys[0], MII_BMCR);
698 duplex = mii_reg & BMCR_FULLDPLX;
699 fasteth = mii_reg & BMCR_SPEED100;
700 } else {
701 int negotiated;
702 mii_reg = mdio_read(dev, np->phys[0], MII_LPA);
703 negotiated = mii_reg & np->mii_if.advertising;
704
705 duplex = (negotiated & LPA_100FULL) || ((negotiated & 0x02C0) == LPA_10FULL);
706 fasteth = negotiated & 0x380;
707 }
708 duplex |= np->mii_if.force_media;
709 /* remove fastether and fullduplex */
710 result = np->csr6 & ~0x20000200;
711 if (duplex)
712 result |= 0x200;
713 if (fasteth)
714 result |= 0x20000000;
715 if (result != np->csr6 && debug)
716 dev_info(&dev->dev,
717 "Setting %dMBit-%s-duplex based on MII#%d\n",
718 fasteth ? 100 : 10, duplex ? "full" : "half",
719 np->phys[0]);
720 return result;
721}
722
723#define RXTX_TIMEOUT 2000
724static inline void update_csr6(struct net_device *dev, int new)
725{
726 struct netdev_private *np = netdev_priv(dev);
727 void __iomem *ioaddr = np->base_addr;
728 int limit = RXTX_TIMEOUT;
729
730 if (!netif_device_present(dev))
731 new = 0;
732 if (new==np->csr6)
733 return;
734 /* stop both Tx and Rx processes */
735 iowrite32(np->csr6 & ~0x2002, ioaddr + NetworkConfig);
736 /* wait until they have really stopped */
737 for (;;) {
738 int csr5 = ioread32(ioaddr + IntrStatus);
739 int t;
740
741 t = (csr5 >> 17) & 0x07;
742 if (t==0||t==1) {
743 /* rx stopped */
744 t = (csr5 >> 20) & 0x07;
745 if (t==0||t==1)
746 break;
747 }
748
749 limit--;
750 if(!limit) {
751 dev_info(&dev->dev,
752 "couldn't stop rxtx, IntrStatus %xh\n", csr5);
753 break;
754 }
755 udelay(1);
756 }
757 np->csr6 = new;
758 /* and restart them with the new configuration */
759 iowrite32(np->csr6, ioaddr + NetworkConfig);
760 if (new & 0x200)
761 np->mii_if.full_duplex = 1;
762}
763
764static void netdev_timer(struct timer_list *t)
765{
766 struct netdev_private *np = from_timer(np, t, timer);
767 struct net_device *dev = pci_get_drvdata(np->pci_dev);
768 void __iomem *ioaddr = np->base_addr;
769
770 if (debug > 2)
771 netdev_dbg(dev, "Media selection timer tick, status %08x config %08x\n",
772 ioread32(ioaddr + IntrStatus),
773 ioread32(ioaddr + NetworkConfig));
774 spin_lock_irq(&np->lock);
775 update_csr6(dev, update_link(dev));
776 spin_unlock_irq(&np->lock);
777 np->timer.expires = jiffies + 10*HZ;
778 add_timer(&np->timer);
779}
780
781static void init_rxtx_rings(struct net_device *dev)
782{
783 struct netdev_private *np = netdev_priv(dev);
784 int i;
785
786 np->rx_head_desc = &np->rx_ring[0];
787 np->tx_ring = (struct w840_tx_desc*)&np->rx_ring[RX_RING_SIZE];
788
789 /* Initial all Rx descriptors. */
790 for (i = 0; i < RX_RING_SIZE; i++) {
791 np->rx_ring[i].length = np->rx_buf_sz;
792 np->rx_ring[i].status = 0;
793 np->rx_skbuff[i] = NULL;
794 }
795 /* Mark the last entry as wrapping the ring. */
796 np->rx_ring[i-1].length |= DescEndRing;
797
798 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
799 for (i = 0; i < RX_RING_SIZE; i++) {
800 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz);
801 np->rx_skbuff[i] = skb;
802 if (skb == NULL)
803 break;
804 np->rx_addr[i] = dma_map_single(&np->pci_dev->dev, skb->data,
805 np->rx_buf_sz,
806 DMA_FROM_DEVICE);
807
808 np->rx_ring[i].buffer1 = np->rx_addr[i];
809 np->rx_ring[i].status = DescOwned;
810 }
811
812 np->cur_rx = 0;
813 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
814
815 /* Initialize the Tx descriptors */
816 for (i = 0; i < TX_RING_SIZE; i++) {
817 np->tx_skbuff[i] = NULL;
818 np->tx_ring[i].status = 0;
819 }
820 np->tx_full = 0;
821 np->tx_q_bytes = np->dirty_tx = np->cur_tx = 0;
822
823 iowrite32(np->ring_dma_addr, np->base_addr + RxRingPtr);
824 iowrite32(np->ring_dma_addr+sizeof(struct w840_rx_desc)*RX_RING_SIZE,
825 np->base_addr + TxRingPtr);
826
827}
828
829static void free_rxtx_rings(struct netdev_private* np)
830{
831 int i;
832 /* Free all the skbuffs in the Rx queue. */
833 for (i = 0; i < RX_RING_SIZE; i++) {
834 np->rx_ring[i].status = 0;
835 if (np->rx_skbuff[i]) {
836 dma_unmap_single(&np->pci_dev->dev, np->rx_addr[i],
837 np->rx_skbuff[i]->len,
838 DMA_FROM_DEVICE);
839 dev_kfree_skb(np->rx_skbuff[i]);
840 }
841 np->rx_skbuff[i] = NULL;
842 }
843 for (i = 0; i < TX_RING_SIZE; i++) {
844 if (np->tx_skbuff[i]) {
845 dma_unmap_single(&np->pci_dev->dev, np->tx_addr[i],
846 np->tx_skbuff[i]->len, DMA_TO_DEVICE);
847 dev_kfree_skb(np->tx_skbuff[i]);
848 }
849 np->tx_skbuff[i] = NULL;
850 }
851}
852
853static void init_registers(struct net_device *dev)
854{
855 struct netdev_private *np = netdev_priv(dev);
856 void __iomem *ioaddr = np->base_addr;
857 int i;
858
859 for (i = 0; i < 6; i++)
860 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
861
862 /* Initialize other registers. */
863#ifdef __BIG_ENDIAN
864 i = (1<<20); /* Big-endian descriptors */
865#else
866 i = 0;
867#endif
868 i |= (0x04<<2); /* skip length 4 u32 */
869 i |= 0x02; /* give Rx priority */
870
871 /* Configure the PCI bus bursts and FIFO thresholds.
872 486: Set 8 longword cache alignment, 8 longword burst.
873 586: Set 16 longword cache alignment, no burst limit.
874 Cache alignment bits 15:14 Burst length 13:8
875 0000 <not allowed> 0000 align to cache 0800 8 longwords
876 4000 8 longwords 0100 1 longword 1000 16 longwords
877 8000 16 longwords 0200 2 longwords 2000 32 longwords
878 C000 32 longwords 0400 4 longwords */
879
880#if defined (__i386__) && !defined(MODULE) && !defined(CONFIG_UML)
881 /* When not a module we can work around broken '486 PCI boards. */
882 if (boot_cpu_data.x86 <= 4) {
883 i |= 0x4800;
884 dev_info(&dev->dev,
885 "This is a 386/486 PCI system, setting cache alignment to 8 longwords\n");
886 } else {
887 i |= 0xE000;
888 }
889#elif defined(__powerpc__) || defined(__i386__) || defined(__alpha__) || defined(__ia64__) || defined(__x86_64__)
890 i |= 0xE000;
891#elif defined(CONFIG_SPARC) || defined (CONFIG_PARISC) || defined(CONFIG_ARM)
892 i |= 0x4800;
893#else
894 dev_warn(&dev->dev, "unknown CPU architecture, using default csr0 setting\n");
895 i |= 0x4800;
896#endif
897 iowrite32(i, ioaddr + PCIBusCfg);
898
899 np->csr6 = 0;
900 /* 128 byte Tx threshold;
901 Transmit on; Receive on; */
902 update_csr6(dev, 0x00022002 | update_link(dev) | __set_rx_mode(dev));
903
904 /* Clear and Enable interrupts by setting the interrupt mask. */
905 iowrite32(0x1A0F5, ioaddr + IntrStatus);
906 iowrite32(0x1A0F5, ioaddr + IntrEnable);
907
908 iowrite32(0, ioaddr + RxStartDemand);
909}
910
911static void tx_timeout(struct net_device *dev, unsigned int txqueue)
912{
913 struct netdev_private *np = netdev_priv(dev);
914 void __iomem *ioaddr = np->base_addr;
915 const int irq = np->pci_dev->irq;
916
917 dev_warn(&dev->dev, "Transmit timed out, status %08x, resetting...\n",
918 ioread32(ioaddr + IntrStatus));
919
920 {
921 int i;
922 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
923 for (i = 0; i < RX_RING_SIZE; i++)
924 printk(KERN_CONT " %08x", (unsigned int)np->rx_ring[i].status);
925 printk(KERN_CONT "\n");
926 printk(KERN_DEBUG " Tx ring %p: ", np->tx_ring);
927 for (i = 0; i < TX_RING_SIZE; i++)
928 printk(KERN_CONT " %08x", np->tx_ring[i].status);
929 printk(KERN_CONT "\n");
930 }
931 printk(KERN_DEBUG "Tx cur %d Tx dirty %d Tx Full %d, q bytes %d\n",
932 np->cur_tx, np->dirty_tx, np->tx_full, np->tx_q_bytes);
933 printk(KERN_DEBUG "Tx Descriptor addr %xh\n", ioread32(ioaddr+0x4C));
934
935 disable_irq(irq);
936 spin_lock_irq(&np->lock);
937 /*
938 * Under high load dirty_tx and the internal tx descriptor pointer
939 * come out of sync, thus perform a software reset and reinitialize
940 * everything.
941 */
942
943 iowrite32(1, np->base_addr+PCIBusCfg);
944 udelay(1);
945
946 free_rxtx_rings(np);
947 init_rxtx_rings(dev);
948 init_registers(dev);
949 spin_unlock_irq(&np->lock);
950 enable_irq(irq);
951
952 netif_wake_queue(dev);
953 netif_trans_update(dev); /* prevent tx timeout */
954 np->stats.tx_errors++;
955}
956
957/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
958static int alloc_ringdesc(struct net_device *dev)
959{
960 struct netdev_private *np = netdev_priv(dev);
961
962 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
963
964 np->rx_ring = dma_alloc_coherent(&np->pci_dev->dev,
965 sizeof(struct w840_rx_desc) * RX_RING_SIZE +
966 sizeof(struct w840_tx_desc) * TX_RING_SIZE,
967 &np->ring_dma_addr, GFP_KERNEL);
968 if(!np->rx_ring)
969 return -ENOMEM;
970 init_rxtx_rings(dev);
971 return 0;
972}
973
974static void free_ringdesc(struct netdev_private *np)
975{
976 dma_free_coherent(&np->pci_dev->dev,
977 sizeof(struct w840_rx_desc) * RX_RING_SIZE +
978 sizeof(struct w840_tx_desc) * TX_RING_SIZE,
979 np->rx_ring, np->ring_dma_addr);
980
981}
982
983static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
984{
985 struct netdev_private *np = netdev_priv(dev);
986 unsigned entry;
987
988 /* Caution: the write order is important here, set the field
989 with the "ownership" bits last. */
990
991 /* Calculate the next Tx descriptor entry. */
992 entry = np->cur_tx % TX_RING_SIZE;
993
994 np->tx_addr[entry] = dma_map_single(&np->pci_dev->dev, skb->data,
995 skb->len, DMA_TO_DEVICE);
996 np->tx_skbuff[entry] = skb;
997
998 np->tx_ring[entry].buffer1 = np->tx_addr[entry];
999 if (skb->len < TX_BUFLIMIT) {
1000 np->tx_ring[entry].length = DescWholePkt | skb->len;
1001 } else {
1002 int len = skb->len - TX_BUFLIMIT;
1003
1004 np->tx_ring[entry].buffer2 = np->tx_addr[entry]+TX_BUFLIMIT;
1005 np->tx_ring[entry].length = DescWholePkt | (len << 11) | TX_BUFLIMIT;
1006 }
1007 if(entry == TX_RING_SIZE-1)
1008 np->tx_ring[entry].length |= DescEndRing;
1009
1010 /* Now acquire the irq spinlock.
1011 * The difficult race is the ordering between
1012 * increasing np->cur_tx and setting DescOwned:
1013 * - if np->cur_tx is increased first the interrupt
1014 * handler could consider the packet as transmitted
1015 * since DescOwned is cleared.
1016 * - If DescOwned is set first the NIC could report the
1017 * packet as sent, but the interrupt handler would ignore it
1018 * since the np->cur_tx was not yet increased.
1019 */
1020 spin_lock_irq(&np->lock);
1021 np->cur_tx++;
1022
1023 wmb(); /* flush length, buffer1, buffer2 */
1024 np->tx_ring[entry].status = DescOwned;
1025 wmb(); /* flush status and kick the hardware */
1026 iowrite32(0, np->base_addr + TxStartDemand);
1027 np->tx_q_bytes += skb->len;
1028 /* Work around horrible bug in the chip by marking the queue as full
1029 when we do not have FIFO room for a maximum sized packet. */
1030 if (np->cur_tx - np->dirty_tx > TX_QUEUE_LEN ||
1031 ((np->drv_flags & HasBrokenTx) && np->tx_q_bytes > TX_BUG_FIFO_LIMIT)) {
1032 netif_stop_queue(dev);
1033 wmb();
1034 np->tx_full = 1;
1035 }
1036 spin_unlock_irq(&np->lock);
1037
1038 if (debug > 4) {
1039 netdev_dbg(dev, "Transmit frame #%d queued in slot %d\n",
1040 np->cur_tx, entry);
1041 }
1042 return NETDEV_TX_OK;
1043}
1044
1045static void netdev_tx_done(struct net_device *dev)
1046{
1047 struct netdev_private *np = netdev_priv(dev);
1048 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1049 int entry = np->dirty_tx % TX_RING_SIZE;
1050 int tx_status = np->tx_ring[entry].status;
1051
1052 if (tx_status < 0)
1053 break;
1054 if (tx_status & 0x8000) { /* There was an error, log it. */
1055#ifndef final_version
1056 if (debug > 1)
1057 netdev_dbg(dev, "Transmit error, Tx status %08x\n",
1058 tx_status);
1059#endif
1060 np->stats.tx_errors++;
1061 if (tx_status & 0x0104) np->stats.tx_aborted_errors++;
1062 if (tx_status & 0x0C80) np->stats.tx_carrier_errors++;
1063 if (tx_status & 0x0200) np->stats.tx_window_errors++;
1064 if (tx_status & 0x0002) np->stats.tx_fifo_errors++;
1065 if ((tx_status & 0x0080) && np->mii_if.full_duplex == 0)
1066 np->stats.tx_heartbeat_errors++;
1067 } else {
1068#ifndef final_version
1069 if (debug > 3)
1070 netdev_dbg(dev, "Transmit slot %d ok, Tx status %08x\n",
1071 entry, tx_status);
1072#endif
1073 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
1074 np->stats.collisions += (tx_status >> 3) & 15;
1075 np->stats.tx_packets++;
1076 }
1077 /* Free the original skb. */
1078 dma_unmap_single(&np->pci_dev->dev, np->tx_addr[entry],
1079 np->tx_skbuff[entry]->len, DMA_TO_DEVICE);
1080 np->tx_q_bytes -= np->tx_skbuff[entry]->len;
1081 dev_kfree_skb_irq(np->tx_skbuff[entry]);
1082 np->tx_skbuff[entry] = NULL;
1083 }
1084 if (np->tx_full &&
1085 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN_RESTART &&
1086 np->tx_q_bytes < TX_BUG_FIFO_LIMIT) {
1087 /* The ring is no longer full, clear tbusy. */
1088 np->tx_full = 0;
1089 wmb();
1090 netif_wake_queue(dev);
1091 }
1092}
1093
1094/* The interrupt handler does all of the Rx thread work and cleans up
1095 after the Tx thread. */
1096static irqreturn_t intr_handler(int irq, void *dev_instance)
1097{
1098 struct net_device *dev = (struct net_device *)dev_instance;
1099 struct netdev_private *np = netdev_priv(dev);
1100 void __iomem *ioaddr = np->base_addr;
1101 int work_limit = max_interrupt_work;
1102 int handled = 0;
1103
1104 if (!netif_device_present(dev))
1105 return IRQ_NONE;
1106 do {
1107 u32 intr_status = ioread32(ioaddr + IntrStatus);
1108
1109 /* Acknowledge all of the current interrupt sources ASAP. */
1110 iowrite32(intr_status & 0x001ffff, ioaddr + IntrStatus);
1111
1112 if (debug > 4)
1113 netdev_dbg(dev, "Interrupt, status %04x\n", intr_status);
1114
1115 if ((intr_status & (NormalIntr|AbnormalIntr)) == 0)
1116 break;
1117
1118 handled = 1;
1119
1120 if (intr_status & (RxIntr | RxNoBuf))
1121 netdev_rx(dev);
1122 if (intr_status & RxNoBuf)
1123 iowrite32(0, ioaddr + RxStartDemand);
1124
1125 if (intr_status & (TxNoBuf | TxIntr) &&
1126 np->cur_tx != np->dirty_tx) {
1127 spin_lock(&np->lock);
1128 netdev_tx_done(dev);
1129 spin_unlock(&np->lock);
1130 }
1131
1132 /* Abnormal error summary/uncommon events handlers. */
1133 if (intr_status & (AbnormalIntr | TxFIFOUnderflow | SystemError |
1134 TimerInt | TxDied))
1135 netdev_error(dev, intr_status);
1136
1137 if (--work_limit < 0) {
1138 dev_warn(&dev->dev,
1139 "Too much work at interrupt, status=0x%04x\n",
1140 intr_status);
1141 /* Set the timer to re-enable the other interrupts after
1142 10*82usec ticks. */
1143 spin_lock(&np->lock);
1144 if (netif_device_present(dev)) {
1145 iowrite32(AbnormalIntr | TimerInt, ioaddr + IntrEnable);
1146 iowrite32(10, ioaddr + GPTimer);
1147 }
1148 spin_unlock(&np->lock);
1149 break;
1150 }
1151 } while (1);
1152
1153 if (debug > 3)
1154 netdev_dbg(dev, "exiting interrupt, status=%#4.4x\n",
1155 ioread32(ioaddr + IntrStatus));
1156 return IRQ_RETVAL(handled);
1157}
1158
1159/* This routine is logically part of the interrupt handler, but separated
1160 for clarity and better register allocation. */
1161static int netdev_rx(struct net_device *dev)
1162{
1163 struct netdev_private *np = netdev_priv(dev);
1164 int entry = np->cur_rx % RX_RING_SIZE;
1165 int work_limit = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
1166
1167 if (debug > 4) {
1168 netdev_dbg(dev, " In netdev_rx(), entry %d status %04x\n",
1169 entry, np->rx_ring[entry].status);
1170 }
1171
1172 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1173 while (--work_limit >= 0) {
1174 struct w840_rx_desc *desc = np->rx_head_desc;
1175 s32 status = desc->status;
1176
1177 if (debug > 4)
1178 netdev_dbg(dev, " netdev_rx() status was %08x\n",
1179 status);
1180 if (status < 0)
1181 break;
1182 if ((status & 0x38008300) != 0x0300) {
1183 if ((status & 0x38000300) != 0x0300) {
1184 /* Ingore earlier buffers. */
1185 if ((status & 0xffff) != 0x7fff) {
1186 dev_warn(&dev->dev,
1187 "Oversized Ethernet frame spanned multiple buffers, entry %#x status %04x!\n",
1188 np->cur_rx, status);
1189 np->stats.rx_length_errors++;
1190 }
1191 } else if (status & 0x8000) {
1192 /* There was a fatal error. */
1193 if (debug > 2)
1194 netdev_dbg(dev, "Receive error, Rx status %08x\n",
1195 status);
1196 np->stats.rx_errors++; /* end of a packet.*/
1197 if (status & 0x0890) np->stats.rx_length_errors++;
1198 if (status & 0x004C) np->stats.rx_frame_errors++;
1199 if (status & 0x0002) np->stats.rx_crc_errors++;
1200 }
1201 } else {
1202 struct sk_buff *skb;
1203 /* Omit the four octet CRC from the length. */
1204 int pkt_len = ((status >> 16) & 0x7ff) - 4;
1205
1206#ifndef final_version
1207 if (debug > 4)
1208 netdev_dbg(dev, " netdev_rx() normal Rx pkt length %d status %x\n",
1209 pkt_len, status);
1210#endif
1211 /* Check if the packet is long enough to accept without copying
1212 to a minimally-sized skbuff. */
1213 if (pkt_len < rx_copybreak &&
1214 (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
1215 skb_reserve(skb, 2); /* 16 byte align the IP header */
1216 dma_sync_single_for_cpu(&np->pci_dev->dev,
1217 np->rx_addr[entry],
1218 np->rx_skbuff[entry]->len,
1219 DMA_FROM_DEVICE);
1220 skb_copy_to_linear_data(skb, np->rx_skbuff[entry]->data, pkt_len);
1221 skb_put(skb, pkt_len);
1222 dma_sync_single_for_device(&np->pci_dev->dev,
1223 np->rx_addr[entry],
1224 np->rx_skbuff[entry]->len,
1225 DMA_FROM_DEVICE);
1226 } else {
1227 dma_unmap_single(&np->pci_dev->dev,
1228 np->rx_addr[entry],
1229 np->rx_skbuff[entry]->len,
1230 DMA_FROM_DEVICE);
1231 skb_put(skb = np->rx_skbuff[entry], pkt_len);
1232 np->rx_skbuff[entry] = NULL;
1233 }
1234#ifndef final_version /* Remove after testing. */
1235 /* You will want this info for the initial debug. */
1236 if (debug > 5)
1237 netdev_dbg(dev, " Rx data %pM %pM %02x%02x %pI4\n",
1238 &skb->data[0], &skb->data[6],
1239 skb->data[12], skb->data[13],
1240 &skb->data[14]);
1241#endif
1242 skb->protocol = eth_type_trans(skb, dev);
1243 netif_rx(skb);
1244 np->stats.rx_packets++;
1245 np->stats.rx_bytes += pkt_len;
1246 }
1247 entry = (++np->cur_rx) % RX_RING_SIZE;
1248 np->rx_head_desc = &np->rx_ring[entry];
1249 }
1250
1251 /* Refill the Rx ring buffers. */
1252 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1253 struct sk_buff *skb;
1254 entry = np->dirty_rx % RX_RING_SIZE;
1255 if (np->rx_skbuff[entry] == NULL) {
1256 skb = netdev_alloc_skb(dev, np->rx_buf_sz);
1257 np->rx_skbuff[entry] = skb;
1258 if (skb == NULL)
1259 break; /* Better luck next round. */
1260 np->rx_addr[entry] = dma_map_single(&np->pci_dev->dev,
1261 skb->data,
1262 np->rx_buf_sz,
1263 DMA_FROM_DEVICE);
1264 np->rx_ring[entry].buffer1 = np->rx_addr[entry];
1265 }
1266 wmb();
1267 np->rx_ring[entry].status = DescOwned;
1268 }
1269
1270 return 0;
1271}
1272
1273static void netdev_error(struct net_device *dev, int intr_status)
1274{
1275 struct netdev_private *np = netdev_priv(dev);
1276 void __iomem *ioaddr = np->base_addr;
1277
1278 if (debug > 2)
1279 netdev_dbg(dev, "Abnormal event, %08x\n", intr_status);
1280 if (intr_status == 0xffffffff)
1281 return;
1282 spin_lock(&np->lock);
1283 if (intr_status & TxFIFOUnderflow) {
1284 int new;
1285 /* Bump up the Tx threshold */
1286#if 0
1287 /* This causes lots of dropped packets,
1288 * and under high load even tx_timeouts
1289 */
1290 new = np->csr6 + 0x4000;
1291#else
1292 new = (np->csr6 >> 14)&0x7f;
1293 if (new < 64)
1294 new *= 2;
1295 else
1296 new = 127; /* load full packet before starting */
1297 new = (np->csr6 & ~(0x7F << 14)) | (new<<14);
1298#endif
1299 netdev_dbg(dev, "Tx underflow, new csr6 %08x\n", new);
1300 update_csr6(dev, new);
1301 }
1302 if (intr_status & RxDied) { /* Missed a Rx frame. */
1303 np->stats.rx_errors++;
1304 }
1305 if (intr_status & TimerInt) {
1306 /* Re-enable other interrupts. */
1307 if (netif_device_present(dev))
1308 iowrite32(0x1A0F5, ioaddr + IntrEnable);
1309 }
1310 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1311 iowrite32(0, ioaddr + RxStartDemand);
1312 spin_unlock(&np->lock);
1313}
1314
1315static struct net_device_stats *get_stats(struct net_device *dev)
1316{
1317 struct netdev_private *np = netdev_priv(dev);
1318 void __iomem *ioaddr = np->base_addr;
1319
1320 /* The chip only need report frame silently dropped. */
1321 spin_lock_irq(&np->lock);
1322 if (netif_running(dev) && netif_device_present(dev))
1323 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1324 spin_unlock_irq(&np->lock);
1325
1326 return &np->stats;
1327}
1328
1329
1330static u32 __set_rx_mode(struct net_device *dev)
1331{
1332 struct netdev_private *np = netdev_priv(dev);
1333 void __iomem *ioaddr = np->base_addr;
1334 u32 mc_filter[2]; /* Multicast hash filter */
1335 u32 rx_mode;
1336
1337 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1338 memset(mc_filter, 0xff, sizeof(mc_filter));
1339 rx_mode = RxAcceptBroadcast | AcceptMulticast | RxAcceptAllPhys
1340 | AcceptMyPhys;
1341 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
1342 (dev->flags & IFF_ALLMULTI)) {
1343 /* Too many to match, or accept all multicasts. */
1344 memset(mc_filter, 0xff, sizeof(mc_filter));
1345 rx_mode = RxAcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1346 } else {
1347 struct netdev_hw_addr *ha;
1348
1349 memset(mc_filter, 0, sizeof(mc_filter));
1350 netdev_for_each_mc_addr(ha, dev) {
1351 int filbit;
1352
1353 filbit = (ether_crc(ETH_ALEN, ha->addr) >> 26) ^ 0x3F;
1354 filbit &= 0x3f;
1355 mc_filter[filbit >> 5] |= 1 << (filbit & 31);
1356 }
1357 rx_mode = RxAcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1358 }
1359 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
1360 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
1361 return rx_mode;
1362}
1363
1364static void set_rx_mode(struct net_device *dev)
1365{
1366 struct netdev_private *np = netdev_priv(dev);
1367 u32 rx_mode = __set_rx_mode(dev);
1368 spin_lock_irq(&np->lock);
1369 update_csr6(dev, (np->csr6 & ~0x00F8) | rx_mode);
1370 spin_unlock_irq(&np->lock);
1371}
1372
1373static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1374{
1375 struct netdev_private *np = netdev_priv(dev);
1376
1377 strscpy(info->driver, DRV_NAME, sizeof(info->driver));
1378 strscpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
1379}
1380
1381static int netdev_get_link_ksettings(struct net_device *dev,
1382 struct ethtool_link_ksettings *cmd)
1383{
1384 struct netdev_private *np = netdev_priv(dev);
1385
1386 spin_lock_irq(&np->lock);
1387 mii_ethtool_get_link_ksettings(&np->mii_if, cmd);
1388 spin_unlock_irq(&np->lock);
1389
1390 return 0;
1391}
1392
1393static int netdev_set_link_ksettings(struct net_device *dev,
1394 const struct ethtool_link_ksettings *cmd)
1395{
1396 struct netdev_private *np = netdev_priv(dev);
1397 int rc;
1398
1399 spin_lock_irq(&np->lock);
1400 rc = mii_ethtool_set_link_ksettings(&np->mii_if, cmd);
1401 spin_unlock_irq(&np->lock);
1402
1403 return rc;
1404}
1405
1406static int netdev_nway_reset(struct net_device *dev)
1407{
1408 struct netdev_private *np = netdev_priv(dev);
1409 return mii_nway_restart(&np->mii_if);
1410}
1411
1412static u32 netdev_get_link(struct net_device *dev)
1413{
1414 struct netdev_private *np = netdev_priv(dev);
1415 return mii_link_ok(&np->mii_if);
1416}
1417
1418static u32 netdev_get_msglevel(struct net_device *dev)
1419{
1420 return debug;
1421}
1422
1423static void netdev_set_msglevel(struct net_device *dev, u32 value)
1424{
1425 debug = value;
1426}
1427
1428static const struct ethtool_ops netdev_ethtool_ops = {
1429 .get_drvinfo = netdev_get_drvinfo,
1430 .nway_reset = netdev_nway_reset,
1431 .get_link = netdev_get_link,
1432 .get_msglevel = netdev_get_msglevel,
1433 .set_msglevel = netdev_set_msglevel,
1434 .get_link_ksettings = netdev_get_link_ksettings,
1435 .set_link_ksettings = netdev_set_link_ksettings,
1436};
1437
1438static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1439{
1440 struct mii_ioctl_data *data = if_mii(rq);
1441 struct netdev_private *np = netdev_priv(dev);
1442
1443 switch(cmd) {
1444 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1445 data->phy_id = ((struct netdev_private *)netdev_priv(dev))->phys[0] & 0x1f;
1446 fallthrough;
1447
1448 case SIOCGMIIREG: /* Read MII PHY register. */
1449 spin_lock_irq(&np->lock);
1450 data->val_out = mdio_read(dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1451 spin_unlock_irq(&np->lock);
1452 return 0;
1453
1454 case SIOCSMIIREG: /* Write MII PHY register. */
1455 spin_lock_irq(&np->lock);
1456 mdio_write(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1457 spin_unlock_irq(&np->lock);
1458 return 0;
1459 default:
1460 return -EOPNOTSUPP;
1461 }
1462}
1463
1464static int netdev_close(struct net_device *dev)
1465{
1466 struct netdev_private *np = netdev_priv(dev);
1467 void __iomem *ioaddr = np->base_addr;
1468
1469 netif_stop_queue(dev);
1470
1471 if (debug > 1) {
1472 netdev_dbg(dev, "Shutting down ethercard, status was %08x Config %08x\n",
1473 ioread32(ioaddr + IntrStatus),
1474 ioread32(ioaddr + NetworkConfig));
1475 netdev_dbg(dev, "Queue pointers were Tx %d / %d, Rx %d / %d\n",
1476 np->cur_tx, np->dirty_tx,
1477 np->cur_rx, np->dirty_rx);
1478 }
1479
1480 /* Stop the chip's Tx and Rx processes. */
1481 spin_lock_irq(&np->lock);
1482 netif_device_detach(dev);
1483 update_csr6(dev, 0);
1484 iowrite32(0x0000, ioaddr + IntrEnable);
1485 spin_unlock_irq(&np->lock);
1486
1487 free_irq(np->pci_dev->irq, dev);
1488 wmb();
1489 netif_device_attach(dev);
1490
1491 if (ioread32(ioaddr + NetworkConfig) != 0xffffffff)
1492 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1493
1494#ifdef __i386__
1495 if (debug > 2) {
1496 int i;
1497
1498 printk(KERN_DEBUG" Tx ring at %p:\n", np->tx_ring);
1499 for (i = 0; i < TX_RING_SIZE; i++)
1500 printk(KERN_DEBUG " #%d desc. %04x %04x %08x\n",
1501 i, np->tx_ring[i].length,
1502 np->tx_ring[i].status, np->tx_ring[i].buffer1);
1503 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1504 for (i = 0; i < RX_RING_SIZE; i++) {
1505 printk(KERN_DEBUG " #%d desc. %04x %04x %08x\n",
1506 i, np->rx_ring[i].length,
1507 np->rx_ring[i].status, np->rx_ring[i].buffer1);
1508 }
1509 }
1510#endif /* __i386__ debugging only */
1511
1512 del_timer_sync(&np->timer);
1513
1514 free_rxtx_rings(np);
1515 free_ringdesc(np);
1516
1517 return 0;
1518}
1519
1520static void w840_remove1(struct pci_dev *pdev)
1521{
1522 struct net_device *dev = pci_get_drvdata(pdev);
1523
1524 if (dev) {
1525 struct netdev_private *np = netdev_priv(dev);
1526 unregister_netdev(dev);
1527 pci_iounmap(pdev, np->base_addr);
1528 free_netdev(dev);
1529 }
1530}
1531
1532/*
1533 * suspend/resume synchronization:
1534 * - open, close, do_ioctl:
1535 * rtnl_lock, & netif_device_detach after the rtnl_unlock.
1536 * - get_stats:
1537 * spin_lock_irq(np->lock), doesn't touch hw if not present
1538 * - start_xmit:
1539 * synchronize_irq + netif_tx_disable;
1540 * - tx_timeout:
1541 * netif_device_detach + netif_tx_disable;
1542 * - set_multicast_list
1543 * netif_device_detach + netif_tx_disable;
1544 * - interrupt handler
1545 * doesn't touch hw if not present, synchronize_irq waits for
1546 * running instances of the interrupt handler.
1547 *
1548 * Disabling hw requires clearing csr6 & IntrEnable.
1549 * update_csr6 & all function that write IntrEnable check netif_device_present
1550 * before settings any bits.
1551 *
1552 * Detach must occur under spin_unlock_irq(), interrupts from a detached
1553 * device would cause an irq storm.
1554 */
1555static int __maybe_unused w840_suspend(struct device *dev_d)
1556{
1557 struct net_device *dev = dev_get_drvdata(dev_d);
1558 struct netdev_private *np = netdev_priv(dev);
1559 void __iomem *ioaddr = np->base_addr;
1560
1561 rtnl_lock();
1562 if (netif_running (dev)) {
1563 del_timer_sync(&np->timer);
1564
1565 spin_lock_irq(&np->lock);
1566 netif_device_detach(dev);
1567 update_csr6(dev, 0);
1568 iowrite32(0, ioaddr + IntrEnable);
1569 spin_unlock_irq(&np->lock);
1570
1571 synchronize_irq(np->pci_dev->irq);
1572 netif_tx_disable(dev);
1573
1574 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1575
1576 /* no more hardware accesses behind this line. */
1577
1578 BUG_ON(np->csr6 || ioread32(ioaddr + IntrEnable));
1579
1580 /* pci_power_off(pdev, -1); */
1581
1582 free_rxtx_rings(np);
1583 } else {
1584 netif_device_detach(dev);
1585 }
1586 rtnl_unlock();
1587 return 0;
1588}
1589
1590static int __maybe_unused w840_resume(struct device *dev_d)
1591{
1592 struct net_device *dev = dev_get_drvdata(dev_d);
1593 struct netdev_private *np = netdev_priv(dev);
1594
1595 rtnl_lock();
1596 if (netif_device_present(dev))
1597 goto out; /* device not suspended */
1598 if (netif_running(dev)) {
1599 spin_lock_irq(&np->lock);
1600 iowrite32(1, np->base_addr+PCIBusCfg);
1601 ioread32(np->base_addr+PCIBusCfg);
1602 udelay(1);
1603 netif_device_attach(dev);
1604 init_rxtx_rings(dev);
1605 init_registers(dev);
1606 spin_unlock_irq(&np->lock);
1607
1608 netif_wake_queue(dev);
1609
1610 mod_timer(&np->timer, jiffies + 1*HZ);
1611 } else {
1612 netif_device_attach(dev);
1613 }
1614out:
1615 rtnl_unlock();
1616 return 0;
1617}
1618
1619static SIMPLE_DEV_PM_OPS(w840_pm_ops, w840_suspend, w840_resume);
1620
1621static struct pci_driver w840_driver = {
1622 .name = DRV_NAME,
1623 .id_table = w840_pci_tbl,
1624 .probe = w840_probe1,
1625 .remove = w840_remove1,
1626 .driver.pm = &w840_pm_ops,
1627};
1628
1629module_pci_driver(w840_driver);
1/* winbond-840.c: A Linux PCI network adapter device driver. */
2/*
3 Written 1998-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 The author may be reached as becker@scyld.com, or C/O
13 Scyld Computing Corporation
14 410 Severn Ave., Suite 210
15 Annapolis MD 21403
16
17 Support and updates available at
18 http://www.scyld.com/network/drivers.html
19
20 Do not remove the copyright information.
21 Do not change the version information unless an improvement has been made.
22 Merely removing my name, as Compex has done in the past, does not count
23 as an improvement.
24
25 Changelog:
26 * ported to 2.4
27 ???
28 * spin lock update, memory barriers, new style dma mappings
29 limit each tx buffer to < 1024 bytes
30 remove DescIntr from Rx descriptors (that's an Tx flag)
31 remove next pointer from Tx descriptors
32 synchronize tx_q_bytes
33 software reset in tx_timeout
34 Copyright (C) 2000 Manfred Spraul
35 * further cleanups
36 power management.
37 support for big endian descriptors
38 Copyright (C) 2001 Manfred Spraul
39 * ethtool support (jgarzik)
40 * Replace some MII-related magic numbers with constants (jgarzik)
41
42 TODO:
43 * enable pci_power_off
44 * Wake-On-LAN
45*/
46
47#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
48
49#define DRV_NAME "winbond-840"
50#define DRV_VERSION "1.01-e"
51#define DRV_RELDATE "Sep-11-2006"
52
53
54/* Automatically extracted configuration info:
55probe-func: winbond840_probe
56config-in: tristate 'Winbond W89c840 Ethernet support' CONFIG_WINBOND_840
57
58c-help-name: Winbond W89c840 PCI Ethernet support
59c-help-symbol: CONFIG_WINBOND_840
60c-help: This driver is for the Winbond W89c840 chip. It also works with
61c-help: the TX9882 chip on the Compex RL100-ATX board.
62c-help: More specific information and updates are available from
63c-help: http://www.scyld.com/network/drivers.html
64*/
65
66/* The user-configurable values.
67 These may be modified when a driver module is loaded.*/
68
69static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
70static int max_interrupt_work = 20;
71/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
72 The '840 uses a 64 element hash table based on the Ethernet CRC. */
73static int multicast_filter_limit = 32;
74
75/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
76 Setting to > 1518 effectively disables this feature. */
77static int rx_copybreak;
78
79/* Used to pass the media type, etc.
80 Both 'options[]' and 'full_duplex[]' should exist for driver
81 interoperability.
82 The media type is usually passed in 'options[]'.
83*/
84#define MAX_UNITS 8 /* More are supported, limit only on options */
85static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
86static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
87
88/* Operational parameters that are set at compile time. */
89
90/* Keep the ring sizes a power of two for compile efficiency.
91 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
92 Making the Tx ring too large decreases the effectiveness of channel
93 bonding and packet priority.
94 There are no ill effects from too-large receive rings. */
95#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
96#define TX_QUEUE_LEN_RESTART 5
97
98#define TX_BUFLIMIT (1024-128)
99
100/* The presumed FIFO size for working around the Tx-FIFO-overflow bug.
101 To avoid overflowing we don't queue again until we have room for a
102 full-size packet.
103 */
104#define TX_FIFO_SIZE (2048)
105#define TX_BUG_FIFO_LIMIT (TX_FIFO_SIZE-1514-16)
106
107
108/* Operational parameters that usually are not changed. */
109/* Time in jiffies before concluding the transmitter is hung. */
110#define TX_TIMEOUT (2*HZ)
111
112/* Include files, designed to support most kernel versions 2.0.0 and later. */
113#include <linux/module.h>
114#include <linux/kernel.h>
115#include <linux/string.h>
116#include <linux/timer.h>
117#include <linux/errno.h>
118#include <linux/ioport.h>
119#include <linux/interrupt.h>
120#include <linux/pci.h>
121#include <linux/dma-mapping.h>
122#include <linux/netdevice.h>
123#include <linux/etherdevice.h>
124#include <linux/skbuff.h>
125#include <linux/init.h>
126#include <linux/delay.h>
127#include <linux/ethtool.h>
128#include <linux/mii.h>
129#include <linux/rtnetlink.h>
130#include <linux/crc32.h>
131#include <linux/bitops.h>
132#include <asm/uaccess.h>
133#include <asm/processor.h> /* Processor type for cache alignment. */
134#include <asm/io.h>
135#include <asm/irq.h>
136
137#include "tulip.h"
138
139#undef PKT_BUF_SZ /* tulip.h also defines this */
140#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
141
142/* These identify the driver base version and may not be removed. */
143static const char version[] __initconst =
144 "v" DRV_VERSION " (2.4 port) "
145 DRV_RELDATE " Donald Becker <becker@scyld.com>\n"
146 " http://www.scyld.com/network/drivers.html\n";
147
148MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
149MODULE_DESCRIPTION("Winbond W89c840 Ethernet driver");
150MODULE_LICENSE("GPL");
151MODULE_VERSION(DRV_VERSION);
152
153module_param(max_interrupt_work, int, 0);
154module_param(debug, int, 0);
155module_param(rx_copybreak, int, 0);
156module_param(multicast_filter_limit, int, 0);
157module_param_array(options, int, NULL, 0);
158module_param_array(full_duplex, int, NULL, 0);
159MODULE_PARM_DESC(max_interrupt_work, "winbond-840 maximum events handled per interrupt");
160MODULE_PARM_DESC(debug, "winbond-840 debug level (0-6)");
161MODULE_PARM_DESC(rx_copybreak, "winbond-840 copy breakpoint for copy-only-tiny-frames");
162MODULE_PARM_DESC(multicast_filter_limit, "winbond-840 maximum number of filtered multicast addresses");
163MODULE_PARM_DESC(options, "winbond-840: Bits 0-3: media type, bit 17: full duplex");
164MODULE_PARM_DESC(full_duplex, "winbond-840 full duplex setting(s) (1)");
165
166/*
167 Theory of Operation
168
169I. Board Compatibility
170
171This driver is for the Winbond w89c840 chip.
172
173II. Board-specific settings
174
175None.
176
177III. Driver operation
178
179This chip is very similar to the Digital 21*4* "Tulip" family. The first
180twelve registers and the descriptor format are nearly identical. Read a
181Tulip manual for operational details.
182
183A significant difference is that the multicast filter and station address are
184stored in registers rather than loaded through a pseudo-transmit packet.
185
186Unlike the Tulip, transmit buffers are limited to 1KB. To transmit a
187full-sized packet we must use both data buffers in a descriptor. Thus the
188driver uses ring mode where descriptors are implicitly sequential in memory,
189rather than using the second descriptor address as a chain pointer to
190subsequent descriptors.
191
192IV. Notes
193
194If you are going to almost clone a Tulip, why not go all the way and avoid
195the need for a new driver?
196
197IVb. References
198
199http://www.scyld.com/expert/100mbps.html
200http://www.scyld.com/expert/NWay.html
201http://www.winbond.com.tw/
202
203IVc. Errata
204
205A horrible bug exists in the transmit FIFO. Apparently the chip doesn't
206correctly detect a full FIFO, and queuing more than 2048 bytes may result in
207silent data corruption.
208
209Test with 'ping -s 10000' on a fast computer.
210
211*/
212
213
214
215/*
216 PCI probe table.
217*/
218enum chip_capability_flags {
219 CanHaveMII=1, HasBrokenTx=2, AlwaysFDX=4, FDXOnNoMII=8,
220};
221
222static DEFINE_PCI_DEVICE_TABLE(w840_pci_tbl) = {
223 { 0x1050, 0x0840, PCI_ANY_ID, 0x8153, 0, 0, 0 },
224 { 0x1050, 0x0840, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
225 { 0x11f6, 0x2011, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
226 { }
227};
228MODULE_DEVICE_TABLE(pci, w840_pci_tbl);
229
230enum {
231 netdev_res_size = 128, /* size of PCI BAR resource */
232};
233
234struct pci_id_info {
235 const char *name;
236 int drv_flags; /* Driver use, intended as capability flags. */
237};
238
239static const struct pci_id_info pci_id_tbl[] = {
240 { /* Sometime a Level-One switch card. */
241 "Winbond W89c840", CanHaveMII | HasBrokenTx | FDXOnNoMII},
242 { "Winbond W89c840", CanHaveMII | HasBrokenTx},
243 { "Compex RL100-ATX", CanHaveMII | HasBrokenTx},
244 { } /* terminate list. */
245};
246
247/* This driver was written to use PCI memory space, however some x86 systems
248 work only with I/O space accesses. See CONFIG_TULIP_MMIO in .config
249*/
250
251/* Offsets to the Command and Status Registers, "CSRs".
252 While similar to the Tulip, these registers are longword aligned.
253 Note: It's not useful to define symbolic names for every register bit in
254 the device. The name can only partially document the semantics and make
255 the driver longer and more difficult to read.
256*/
257enum w840_offsets {
258 PCIBusCfg=0x00, TxStartDemand=0x04, RxStartDemand=0x08,
259 RxRingPtr=0x0C, TxRingPtr=0x10,
260 IntrStatus=0x14, NetworkConfig=0x18, IntrEnable=0x1C,
261 RxMissed=0x20, EECtrl=0x24, MIICtrl=0x24, BootRom=0x28, GPTimer=0x2C,
262 CurRxDescAddr=0x30, CurRxBufAddr=0x34, /* Debug use */
263 MulticastFilter0=0x38, MulticastFilter1=0x3C, StationAddr=0x40,
264 CurTxDescAddr=0x4C, CurTxBufAddr=0x50,
265};
266
267/* Bits in the NetworkConfig register. */
268enum rx_mode_bits {
269 AcceptErr=0x80,
270 RxAcceptBroadcast=0x20, AcceptMulticast=0x10,
271 RxAcceptAllPhys=0x08, AcceptMyPhys=0x02,
272};
273
274enum mii_reg_bits {
275 MDIO_ShiftClk=0x10000, MDIO_DataIn=0x80000, MDIO_DataOut=0x20000,
276 MDIO_EnbOutput=0x40000, MDIO_EnbIn = 0x00000,
277};
278
279/* The Tulip Rx and Tx buffer descriptors. */
280struct w840_rx_desc {
281 s32 status;
282 s32 length;
283 u32 buffer1;
284 u32 buffer2;
285};
286
287struct w840_tx_desc {
288 s32 status;
289 s32 length;
290 u32 buffer1, buffer2;
291};
292
293#define MII_CNT 1 /* winbond only supports one MII */
294struct netdev_private {
295 struct w840_rx_desc *rx_ring;
296 dma_addr_t rx_addr[RX_RING_SIZE];
297 struct w840_tx_desc *tx_ring;
298 dma_addr_t tx_addr[TX_RING_SIZE];
299 dma_addr_t ring_dma_addr;
300 /* The addresses of receive-in-place skbuffs. */
301 struct sk_buff* rx_skbuff[RX_RING_SIZE];
302 /* The saved address of a sent-in-place packet/buffer, for later free(). */
303 struct sk_buff* tx_skbuff[TX_RING_SIZE];
304 struct net_device_stats stats;
305 struct timer_list timer; /* Media monitoring timer. */
306 /* Frequently used values: keep some adjacent for cache effect. */
307 spinlock_t lock;
308 int chip_id, drv_flags;
309 struct pci_dev *pci_dev;
310 int csr6;
311 struct w840_rx_desc *rx_head_desc;
312 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
313 unsigned int rx_buf_sz; /* Based on MTU+slack. */
314 unsigned int cur_tx, dirty_tx;
315 unsigned int tx_q_bytes;
316 unsigned int tx_full; /* The Tx queue is full. */
317 /* MII transceiver section. */
318 int mii_cnt; /* MII device addresses. */
319 unsigned char phys[MII_CNT]; /* MII device addresses, but only the first is used */
320 u32 mii;
321 struct mii_if_info mii_if;
322 void __iomem *base_addr;
323};
324
325static int eeprom_read(void __iomem *ioaddr, int location);
326static int mdio_read(struct net_device *dev, int phy_id, int location);
327static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
328static int netdev_open(struct net_device *dev);
329static int update_link(struct net_device *dev);
330static void netdev_timer(unsigned long data);
331static void init_rxtx_rings(struct net_device *dev);
332static void free_rxtx_rings(struct netdev_private *np);
333static void init_registers(struct net_device *dev);
334static void tx_timeout(struct net_device *dev);
335static int alloc_ringdesc(struct net_device *dev);
336static void free_ringdesc(struct netdev_private *np);
337static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
338static irqreturn_t intr_handler(int irq, void *dev_instance);
339static void netdev_error(struct net_device *dev, int intr_status);
340static int netdev_rx(struct net_device *dev);
341static u32 __set_rx_mode(struct net_device *dev);
342static void set_rx_mode(struct net_device *dev);
343static struct net_device_stats *get_stats(struct net_device *dev);
344static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
345static const struct ethtool_ops netdev_ethtool_ops;
346static int netdev_close(struct net_device *dev);
347
348static const struct net_device_ops netdev_ops = {
349 .ndo_open = netdev_open,
350 .ndo_stop = netdev_close,
351 .ndo_start_xmit = start_tx,
352 .ndo_get_stats = get_stats,
353 .ndo_set_rx_mode = set_rx_mode,
354 .ndo_do_ioctl = netdev_ioctl,
355 .ndo_tx_timeout = tx_timeout,
356 .ndo_change_mtu = eth_change_mtu,
357 .ndo_set_mac_address = eth_mac_addr,
358 .ndo_validate_addr = eth_validate_addr,
359};
360
361static int w840_probe1(struct pci_dev *pdev, const struct pci_device_id *ent)
362{
363 struct net_device *dev;
364 struct netdev_private *np;
365 static int find_cnt;
366 int chip_idx = ent->driver_data;
367 int irq;
368 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
369 void __iomem *ioaddr;
370
371 i = pci_enable_device(pdev);
372 if (i) return i;
373
374 pci_set_master(pdev);
375
376 irq = pdev->irq;
377
378 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
379 pr_warn("Device %s disabled due to DMA limitations\n",
380 pci_name(pdev));
381 return -EIO;
382 }
383 dev = alloc_etherdev(sizeof(*np));
384 if (!dev)
385 return -ENOMEM;
386 SET_NETDEV_DEV(dev, &pdev->dev);
387
388 if (pci_request_regions(pdev, DRV_NAME))
389 goto err_out_netdev;
390
391 ioaddr = pci_iomap(pdev, TULIP_BAR, netdev_res_size);
392 if (!ioaddr)
393 goto err_out_free_res;
394
395 for (i = 0; i < 3; i++)
396 ((__le16 *)dev->dev_addr)[i] = cpu_to_le16(eeprom_read(ioaddr, i));
397
398 /* Reset the chip to erase previous misconfiguration.
399 No hold time required! */
400 iowrite32(0x00000001, ioaddr + PCIBusCfg);
401
402 np = netdev_priv(dev);
403 np->pci_dev = pdev;
404 np->chip_id = chip_idx;
405 np->drv_flags = pci_id_tbl[chip_idx].drv_flags;
406 spin_lock_init(&np->lock);
407 np->mii_if.dev = dev;
408 np->mii_if.mdio_read = mdio_read;
409 np->mii_if.mdio_write = mdio_write;
410 np->base_addr = ioaddr;
411
412 pci_set_drvdata(pdev, dev);
413
414 if (dev->mem_start)
415 option = dev->mem_start;
416
417 /* The lower four bits are the media type. */
418 if (option > 0) {
419 if (option & 0x200)
420 np->mii_if.full_duplex = 1;
421 if (option & 15)
422 dev_info(&dev->dev,
423 "ignoring user supplied media type %d",
424 option & 15);
425 }
426 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
427 np->mii_if.full_duplex = 1;
428
429 if (np->mii_if.full_duplex)
430 np->mii_if.force_media = 1;
431
432 /* The chip-specific entries in the device structure. */
433 dev->netdev_ops = &netdev_ops;
434 dev->ethtool_ops = &netdev_ethtool_ops;
435 dev->watchdog_timeo = TX_TIMEOUT;
436
437 i = register_netdev(dev);
438 if (i)
439 goto err_out_cleardev;
440
441 dev_info(&dev->dev, "%s at %p, %pM, IRQ %d\n",
442 pci_id_tbl[chip_idx].name, ioaddr, dev->dev_addr, irq);
443
444 if (np->drv_flags & CanHaveMII) {
445 int phy, phy_idx = 0;
446 for (phy = 1; phy < 32 && phy_idx < MII_CNT; phy++) {
447 int mii_status = mdio_read(dev, phy, MII_BMSR);
448 if (mii_status != 0xffff && mii_status != 0x0000) {
449 np->phys[phy_idx++] = phy;
450 np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
451 np->mii = (mdio_read(dev, phy, MII_PHYSID1) << 16)+
452 mdio_read(dev, phy, MII_PHYSID2);
453 dev_info(&dev->dev,
454 "MII PHY %08xh found at address %d, status 0x%04x advertising %04x\n",
455 np->mii, phy, mii_status,
456 np->mii_if.advertising);
457 }
458 }
459 np->mii_cnt = phy_idx;
460 np->mii_if.phy_id = np->phys[0];
461 if (phy_idx == 0) {
462 dev_warn(&dev->dev,
463 "MII PHY not found -- this device may not operate correctly\n");
464 }
465 }
466
467 find_cnt++;
468 return 0;
469
470err_out_cleardev:
471 pci_iounmap(pdev, ioaddr);
472err_out_free_res:
473 pci_release_regions(pdev);
474err_out_netdev:
475 free_netdev (dev);
476 return -ENODEV;
477}
478
479
480/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. These are
481 often serial bit streams generated by the host processor.
482 The example below is for the common 93c46 EEPROM, 64 16 bit words. */
483
484/* Delay between EEPROM clock transitions.
485 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
486 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
487 made udelay() unreliable.
488 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
489 deprecated.
490*/
491#define eeprom_delay(ee_addr) ioread32(ee_addr)
492
493enum EEPROM_Ctrl_Bits {
494 EE_ShiftClk=0x02, EE_Write0=0x801, EE_Write1=0x805,
495 EE_ChipSelect=0x801, EE_DataIn=0x08,
496};
497
498/* The EEPROM commands include the alway-set leading bit. */
499enum EEPROM_Cmds {
500 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
501};
502
503static int eeprom_read(void __iomem *addr, int location)
504{
505 int i;
506 int retval = 0;
507 void __iomem *ee_addr = addr + EECtrl;
508 int read_cmd = location | EE_ReadCmd;
509 iowrite32(EE_ChipSelect, ee_addr);
510
511 /* Shift the read command bits out. */
512 for (i = 10; i >= 0; i--) {
513 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
514 iowrite32(dataval, ee_addr);
515 eeprom_delay(ee_addr);
516 iowrite32(dataval | EE_ShiftClk, ee_addr);
517 eeprom_delay(ee_addr);
518 }
519 iowrite32(EE_ChipSelect, ee_addr);
520 eeprom_delay(ee_addr);
521
522 for (i = 16; i > 0; i--) {
523 iowrite32(EE_ChipSelect | EE_ShiftClk, ee_addr);
524 eeprom_delay(ee_addr);
525 retval = (retval << 1) | ((ioread32(ee_addr) & EE_DataIn) ? 1 : 0);
526 iowrite32(EE_ChipSelect, ee_addr);
527 eeprom_delay(ee_addr);
528 }
529
530 /* Terminate the EEPROM access. */
531 iowrite32(0, ee_addr);
532 return retval;
533}
534
535/* MII transceiver control section.
536 Read and write the MII registers using software-generated serial
537 MDIO protocol. See the MII specifications or DP83840A data sheet
538 for details.
539
540 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
541 met by back-to-back 33Mhz PCI cycles. */
542#define mdio_delay(mdio_addr) ioread32(mdio_addr)
543
544/* Set iff a MII transceiver on any interface requires mdio preamble.
545 This only set with older transceivers, so the extra
546 code size of a per-interface flag is not worthwhile. */
547static char mii_preamble_required = 1;
548
549#define MDIO_WRITE0 (MDIO_EnbOutput)
550#define MDIO_WRITE1 (MDIO_DataOut | MDIO_EnbOutput)
551
552/* Generate the preamble required for initial synchronization and
553 a few older transceivers. */
554static void mdio_sync(void __iomem *mdio_addr)
555{
556 int bits = 32;
557
558 /* Establish sync by sending at least 32 logic ones. */
559 while (--bits >= 0) {
560 iowrite32(MDIO_WRITE1, mdio_addr);
561 mdio_delay(mdio_addr);
562 iowrite32(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
563 mdio_delay(mdio_addr);
564 }
565}
566
567static int mdio_read(struct net_device *dev, int phy_id, int location)
568{
569 struct netdev_private *np = netdev_priv(dev);
570 void __iomem *mdio_addr = np->base_addr + MIICtrl;
571 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
572 int i, retval = 0;
573
574 if (mii_preamble_required)
575 mdio_sync(mdio_addr);
576
577 /* Shift the read command bits out. */
578 for (i = 15; i >= 0; i--) {
579 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
580
581 iowrite32(dataval, mdio_addr);
582 mdio_delay(mdio_addr);
583 iowrite32(dataval | MDIO_ShiftClk, mdio_addr);
584 mdio_delay(mdio_addr);
585 }
586 /* Read the two transition, 16 data, and wire-idle bits. */
587 for (i = 20; i > 0; i--) {
588 iowrite32(MDIO_EnbIn, mdio_addr);
589 mdio_delay(mdio_addr);
590 retval = (retval << 1) | ((ioread32(mdio_addr) & MDIO_DataIn) ? 1 : 0);
591 iowrite32(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
592 mdio_delay(mdio_addr);
593 }
594 return (retval>>1) & 0xffff;
595}
596
597static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
598{
599 struct netdev_private *np = netdev_priv(dev);
600 void __iomem *mdio_addr = np->base_addr + MIICtrl;
601 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value;
602 int i;
603
604 if (location == 4 && phy_id == np->phys[0])
605 np->mii_if.advertising = value;
606
607 if (mii_preamble_required)
608 mdio_sync(mdio_addr);
609
610 /* Shift the command bits out. */
611 for (i = 31; i >= 0; i--) {
612 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
613
614 iowrite32(dataval, mdio_addr);
615 mdio_delay(mdio_addr);
616 iowrite32(dataval | MDIO_ShiftClk, mdio_addr);
617 mdio_delay(mdio_addr);
618 }
619 /* Clear out extra bits. */
620 for (i = 2; i > 0; i--) {
621 iowrite32(MDIO_EnbIn, mdio_addr);
622 mdio_delay(mdio_addr);
623 iowrite32(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
624 mdio_delay(mdio_addr);
625 }
626}
627
628
629static int netdev_open(struct net_device *dev)
630{
631 struct netdev_private *np = netdev_priv(dev);
632 void __iomem *ioaddr = np->base_addr;
633 const int irq = np->pci_dev->irq;
634 int i;
635
636 iowrite32(0x00000001, ioaddr + PCIBusCfg); /* Reset */
637
638 netif_device_detach(dev);
639 i = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev);
640 if (i)
641 goto out_err;
642
643 if (debug > 1)
644 netdev_dbg(dev, "w89c840_open() irq %d\n", irq);
645
646 if((i=alloc_ringdesc(dev)))
647 goto out_err;
648
649 spin_lock_irq(&np->lock);
650 netif_device_attach(dev);
651 init_registers(dev);
652 spin_unlock_irq(&np->lock);
653
654 netif_start_queue(dev);
655 if (debug > 2)
656 netdev_dbg(dev, "Done netdev_open()\n");
657
658 /* Set the timer to check for link beat. */
659 init_timer(&np->timer);
660 np->timer.expires = jiffies + 1*HZ;
661 np->timer.data = (unsigned long)dev;
662 np->timer.function = netdev_timer; /* timer handler */
663 add_timer(&np->timer);
664 return 0;
665out_err:
666 netif_device_attach(dev);
667 return i;
668}
669
670#define MII_DAVICOM_DM9101 0x0181b800
671
672static int update_link(struct net_device *dev)
673{
674 struct netdev_private *np = netdev_priv(dev);
675 int duplex, fasteth, result, mii_reg;
676
677 /* BSMR */
678 mii_reg = mdio_read(dev, np->phys[0], MII_BMSR);
679
680 if (mii_reg == 0xffff)
681 return np->csr6;
682 /* reread: the link status bit is sticky */
683 mii_reg = mdio_read(dev, np->phys[0], MII_BMSR);
684 if (!(mii_reg & 0x4)) {
685 if (netif_carrier_ok(dev)) {
686 if (debug)
687 dev_info(&dev->dev,
688 "MII #%d reports no link. Disabling watchdog\n",
689 np->phys[0]);
690 netif_carrier_off(dev);
691 }
692 return np->csr6;
693 }
694 if (!netif_carrier_ok(dev)) {
695 if (debug)
696 dev_info(&dev->dev,
697 "MII #%d link is back. Enabling watchdog\n",
698 np->phys[0]);
699 netif_carrier_on(dev);
700 }
701
702 if ((np->mii & ~0xf) == MII_DAVICOM_DM9101) {
703 /* If the link partner doesn't support autonegotiation
704 * the MII detects it's abilities with the "parallel detection".
705 * Some MIIs update the LPA register to the result of the parallel
706 * detection, some don't.
707 * The Davicom PHY [at least 0181b800] doesn't.
708 * Instead bit 9 and 13 of the BMCR are updated to the result
709 * of the negotiation..
710 */
711 mii_reg = mdio_read(dev, np->phys[0], MII_BMCR);
712 duplex = mii_reg & BMCR_FULLDPLX;
713 fasteth = mii_reg & BMCR_SPEED100;
714 } else {
715 int negotiated;
716 mii_reg = mdio_read(dev, np->phys[0], MII_LPA);
717 negotiated = mii_reg & np->mii_if.advertising;
718
719 duplex = (negotiated & LPA_100FULL) || ((negotiated & 0x02C0) == LPA_10FULL);
720 fasteth = negotiated & 0x380;
721 }
722 duplex |= np->mii_if.force_media;
723 /* remove fastether and fullduplex */
724 result = np->csr6 & ~0x20000200;
725 if (duplex)
726 result |= 0x200;
727 if (fasteth)
728 result |= 0x20000000;
729 if (result != np->csr6 && debug)
730 dev_info(&dev->dev,
731 "Setting %dMBit-%s-duplex based on MII#%d\n",
732 fasteth ? 100 : 10, duplex ? "full" : "half",
733 np->phys[0]);
734 return result;
735}
736
737#define RXTX_TIMEOUT 2000
738static inline void update_csr6(struct net_device *dev, int new)
739{
740 struct netdev_private *np = netdev_priv(dev);
741 void __iomem *ioaddr = np->base_addr;
742 int limit = RXTX_TIMEOUT;
743
744 if (!netif_device_present(dev))
745 new = 0;
746 if (new==np->csr6)
747 return;
748 /* stop both Tx and Rx processes */
749 iowrite32(np->csr6 & ~0x2002, ioaddr + NetworkConfig);
750 /* wait until they have really stopped */
751 for (;;) {
752 int csr5 = ioread32(ioaddr + IntrStatus);
753 int t;
754
755 t = (csr5 >> 17) & 0x07;
756 if (t==0||t==1) {
757 /* rx stopped */
758 t = (csr5 >> 20) & 0x07;
759 if (t==0||t==1)
760 break;
761 }
762
763 limit--;
764 if(!limit) {
765 dev_info(&dev->dev,
766 "couldn't stop rxtx, IntrStatus %xh\n", csr5);
767 break;
768 }
769 udelay(1);
770 }
771 np->csr6 = new;
772 /* and restart them with the new configuration */
773 iowrite32(np->csr6, ioaddr + NetworkConfig);
774 if (new & 0x200)
775 np->mii_if.full_duplex = 1;
776}
777
778static void netdev_timer(unsigned long data)
779{
780 struct net_device *dev = (struct net_device *)data;
781 struct netdev_private *np = netdev_priv(dev);
782 void __iomem *ioaddr = np->base_addr;
783
784 if (debug > 2)
785 netdev_dbg(dev, "Media selection timer tick, status %08x config %08x\n",
786 ioread32(ioaddr + IntrStatus),
787 ioread32(ioaddr + NetworkConfig));
788 spin_lock_irq(&np->lock);
789 update_csr6(dev, update_link(dev));
790 spin_unlock_irq(&np->lock);
791 np->timer.expires = jiffies + 10*HZ;
792 add_timer(&np->timer);
793}
794
795static void init_rxtx_rings(struct net_device *dev)
796{
797 struct netdev_private *np = netdev_priv(dev);
798 int i;
799
800 np->rx_head_desc = &np->rx_ring[0];
801 np->tx_ring = (struct w840_tx_desc*)&np->rx_ring[RX_RING_SIZE];
802
803 /* Initial all Rx descriptors. */
804 for (i = 0; i < RX_RING_SIZE; i++) {
805 np->rx_ring[i].length = np->rx_buf_sz;
806 np->rx_ring[i].status = 0;
807 np->rx_skbuff[i] = NULL;
808 }
809 /* Mark the last entry as wrapping the ring. */
810 np->rx_ring[i-1].length |= DescEndRing;
811
812 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
813 for (i = 0; i < RX_RING_SIZE; i++) {
814 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz);
815 np->rx_skbuff[i] = skb;
816 if (skb == NULL)
817 break;
818 np->rx_addr[i] = pci_map_single(np->pci_dev,skb->data,
819 np->rx_buf_sz,PCI_DMA_FROMDEVICE);
820
821 np->rx_ring[i].buffer1 = np->rx_addr[i];
822 np->rx_ring[i].status = DescOwned;
823 }
824
825 np->cur_rx = 0;
826 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
827
828 /* Initialize the Tx descriptors */
829 for (i = 0; i < TX_RING_SIZE; i++) {
830 np->tx_skbuff[i] = NULL;
831 np->tx_ring[i].status = 0;
832 }
833 np->tx_full = 0;
834 np->tx_q_bytes = np->dirty_tx = np->cur_tx = 0;
835
836 iowrite32(np->ring_dma_addr, np->base_addr + RxRingPtr);
837 iowrite32(np->ring_dma_addr+sizeof(struct w840_rx_desc)*RX_RING_SIZE,
838 np->base_addr + TxRingPtr);
839
840}
841
842static void free_rxtx_rings(struct netdev_private* np)
843{
844 int i;
845 /* Free all the skbuffs in the Rx queue. */
846 for (i = 0; i < RX_RING_SIZE; i++) {
847 np->rx_ring[i].status = 0;
848 if (np->rx_skbuff[i]) {
849 pci_unmap_single(np->pci_dev,
850 np->rx_addr[i],
851 np->rx_skbuff[i]->len,
852 PCI_DMA_FROMDEVICE);
853 dev_kfree_skb(np->rx_skbuff[i]);
854 }
855 np->rx_skbuff[i] = NULL;
856 }
857 for (i = 0; i < TX_RING_SIZE; i++) {
858 if (np->tx_skbuff[i]) {
859 pci_unmap_single(np->pci_dev,
860 np->tx_addr[i],
861 np->tx_skbuff[i]->len,
862 PCI_DMA_TODEVICE);
863 dev_kfree_skb(np->tx_skbuff[i]);
864 }
865 np->tx_skbuff[i] = NULL;
866 }
867}
868
869static void init_registers(struct net_device *dev)
870{
871 struct netdev_private *np = netdev_priv(dev);
872 void __iomem *ioaddr = np->base_addr;
873 int i;
874
875 for (i = 0; i < 6; i++)
876 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
877
878 /* Initialize other registers. */
879#ifdef __BIG_ENDIAN
880 i = (1<<20); /* Big-endian descriptors */
881#else
882 i = 0;
883#endif
884 i |= (0x04<<2); /* skip length 4 u32 */
885 i |= 0x02; /* give Rx priority */
886
887 /* Configure the PCI bus bursts and FIFO thresholds.
888 486: Set 8 longword cache alignment, 8 longword burst.
889 586: Set 16 longword cache alignment, no burst limit.
890 Cache alignment bits 15:14 Burst length 13:8
891 0000 <not allowed> 0000 align to cache 0800 8 longwords
892 4000 8 longwords 0100 1 longword 1000 16 longwords
893 8000 16 longwords 0200 2 longwords 2000 32 longwords
894 C000 32 longwords 0400 4 longwords */
895
896#if defined (__i386__) && !defined(MODULE)
897 /* When not a module we can work around broken '486 PCI boards. */
898 if (boot_cpu_data.x86 <= 4) {
899 i |= 0x4800;
900 dev_info(&dev->dev,
901 "This is a 386/486 PCI system, setting cache alignment to 8 longwords\n");
902 } else {
903 i |= 0xE000;
904 }
905#elif defined(__powerpc__) || defined(__i386__) || defined(__alpha__) || defined(__ia64__) || defined(__x86_64__)
906 i |= 0xE000;
907#elif defined(CONFIG_SPARC) || defined (CONFIG_PARISC)
908 i |= 0x4800;
909#else
910#warning Processor architecture undefined
911 i |= 0x4800;
912#endif
913 iowrite32(i, ioaddr + PCIBusCfg);
914
915 np->csr6 = 0;
916 /* 128 byte Tx threshold;
917 Transmit on; Receive on; */
918 update_csr6(dev, 0x00022002 | update_link(dev) | __set_rx_mode(dev));
919
920 /* Clear and Enable interrupts by setting the interrupt mask. */
921 iowrite32(0x1A0F5, ioaddr + IntrStatus);
922 iowrite32(0x1A0F5, ioaddr + IntrEnable);
923
924 iowrite32(0, ioaddr + RxStartDemand);
925}
926
927static void tx_timeout(struct net_device *dev)
928{
929 struct netdev_private *np = netdev_priv(dev);
930 void __iomem *ioaddr = np->base_addr;
931 const int irq = np->pci_dev->irq;
932
933 dev_warn(&dev->dev, "Transmit timed out, status %08x, resetting...\n",
934 ioread32(ioaddr + IntrStatus));
935
936 {
937 int i;
938 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
939 for (i = 0; i < RX_RING_SIZE; i++)
940 printk(KERN_CONT " %08x", (unsigned int)np->rx_ring[i].status);
941 printk(KERN_CONT "\n");
942 printk(KERN_DEBUG " Tx ring %p: ", np->tx_ring);
943 for (i = 0; i < TX_RING_SIZE; i++)
944 printk(KERN_CONT " %08x", np->tx_ring[i].status);
945 printk(KERN_CONT "\n");
946 }
947 printk(KERN_DEBUG "Tx cur %d Tx dirty %d Tx Full %d, q bytes %d\n",
948 np->cur_tx, np->dirty_tx, np->tx_full, np->tx_q_bytes);
949 printk(KERN_DEBUG "Tx Descriptor addr %xh\n", ioread32(ioaddr+0x4C));
950
951 disable_irq(irq);
952 spin_lock_irq(&np->lock);
953 /*
954 * Under high load dirty_tx and the internal tx descriptor pointer
955 * come out of sync, thus perform a software reset and reinitialize
956 * everything.
957 */
958
959 iowrite32(1, np->base_addr+PCIBusCfg);
960 udelay(1);
961
962 free_rxtx_rings(np);
963 init_rxtx_rings(dev);
964 init_registers(dev);
965 spin_unlock_irq(&np->lock);
966 enable_irq(irq);
967
968 netif_wake_queue(dev);
969 dev->trans_start = jiffies; /* prevent tx timeout */
970 np->stats.tx_errors++;
971}
972
973/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
974static int alloc_ringdesc(struct net_device *dev)
975{
976 struct netdev_private *np = netdev_priv(dev);
977
978 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
979
980 np->rx_ring = pci_alloc_consistent(np->pci_dev,
981 sizeof(struct w840_rx_desc)*RX_RING_SIZE +
982 sizeof(struct w840_tx_desc)*TX_RING_SIZE,
983 &np->ring_dma_addr);
984 if(!np->rx_ring)
985 return -ENOMEM;
986 init_rxtx_rings(dev);
987 return 0;
988}
989
990static void free_ringdesc(struct netdev_private *np)
991{
992 pci_free_consistent(np->pci_dev,
993 sizeof(struct w840_rx_desc)*RX_RING_SIZE +
994 sizeof(struct w840_tx_desc)*TX_RING_SIZE,
995 np->rx_ring, np->ring_dma_addr);
996
997}
998
999static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
1000{
1001 struct netdev_private *np = netdev_priv(dev);
1002 unsigned entry;
1003
1004 /* Caution: the write order is important here, set the field
1005 with the "ownership" bits last. */
1006
1007 /* Calculate the next Tx descriptor entry. */
1008 entry = np->cur_tx % TX_RING_SIZE;
1009
1010 np->tx_addr[entry] = pci_map_single(np->pci_dev,
1011 skb->data,skb->len, PCI_DMA_TODEVICE);
1012 np->tx_skbuff[entry] = skb;
1013
1014 np->tx_ring[entry].buffer1 = np->tx_addr[entry];
1015 if (skb->len < TX_BUFLIMIT) {
1016 np->tx_ring[entry].length = DescWholePkt | skb->len;
1017 } else {
1018 int len = skb->len - TX_BUFLIMIT;
1019
1020 np->tx_ring[entry].buffer2 = np->tx_addr[entry]+TX_BUFLIMIT;
1021 np->tx_ring[entry].length = DescWholePkt | (len << 11) | TX_BUFLIMIT;
1022 }
1023 if(entry == TX_RING_SIZE-1)
1024 np->tx_ring[entry].length |= DescEndRing;
1025
1026 /* Now acquire the irq spinlock.
1027 * The difficult race is the ordering between
1028 * increasing np->cur_tx and setting DescOwned:
1029 * - if np->cur_tx is increased first the interrupt
1030 * handler could consider the packet as transmitted
1031 * since DescOwned is cleared.
1032 * - If DescOwned is set first the NIC could report the
1033 * packet as sent, but the interrupt handler would ignore it
1034 * since the np->cur_tx was not yet increased.
1035 */
1036 spin_lock_irq(&np->lock);
1037 np->cur_tx++;
1038
1039 wmb(); /* flush length, buffer1, buffer2 */
1040 np->tx_ring[entry].status = DescOwned;
1041 wmb(); /* flush status and kick the hardware */
1042 iowrite32(0, np->base_addr + TxStartDemand);
1043 np->tx_q_bytes += skb->len;
1044 /* Work around horrible bug in the chip by marking the queue as full
1045 when we do not have FIFO room for a maximum sized packet. */
1046 if (np->cur_tx - np->dirty_tx > TX_QUEUE_LEN ||
1047 ((np->drv_flags & HasBrokenTx) && np->tx_q_bytes > TX_BUG_FIFO_LIMIT)) {
1048 netif_stop_queue(dev);
1049 wmb();
1050 np->tx_full = 1;
1051 }
1052 spin_unlock_irq(&np->lock);
1053
1054 if (debug > 4) {
1055 netdev_dbg(dev, "Transmit frame #%d queued in slot %d\n",
1056 np->cur_tx, entry);
1057 }
1058 return NETDEV_TX_OK;
1059}
1060
1061static void netdev_tx_done(struct net_device *dev)
1062{
1063 struct netdev_private *np = netdev_priv(dev);
1064 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1065 int entry = np->dirty_tx % TX_RING_SIZE;
1066 int tx_status = np->tx_ring[entry].status;
1067
1068 if (tx_status < 0)
1069 break;
1070 if (tx_status & 0x8000) { /* There was an error, log it. */
1071#ifndef final_version
1072 if (debug > 1)
1073 netdev_dbg(dev, "Transmit error, Tx status %08x\n",
1074 tx_status);
1075#endif
1076 np->stats.tx_errors++;
1077 if (tx_status & 0x0104) np->stats.tx_aborted_errors++;
1078 if (tx_status & 0x0C80) np->stats.tx_carrier_errors++;
1079 if (tx_status & 0x0200) np->stats.tx_window_errors++;
1080 if (tx_status & 0x0002) np->stats.tx_fifo_errors++;
1081 if ((tx_status & 0x0080) && np->mii_if.full_duplex == 0)
1082 np->stats.tx_heartbeat_errors++;
1083 } else {
1084#ifndef final_version
1085 if (debug > 3)
1086 netdev_dbg(dev, "Transmit slot %d ok, Tx status %08x\n",
1087 entry, tx_status);
1088#endif
1089 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
1090 np->stats.collisions += (tx_status >> 3) & 15;
1091 np->stats.tx_packets++;
1092 }
1093 /* Free the original skb. */
1094 pci_unmap_single(np->pci_dev,np->tx_addr[entry],
1095 np->tx_skbuff[entry]->len,
1096 PCI_DMA_TODEVICE);
1097 np->tx_q_bytes -= np->tx_skbuff[entry]->len;
1098 dev_kfree_skb_irq(np->tx_skbuff[entry]);
1099 np->tx_skbuff[entry] = NULL;
1100 }
1101 if (np->tx_full &&
1102 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN_RESTART &&
1103 np->tx_q_bytes < TX_BUG_FIFO_LIMIT) {
1104 /* The ring is no longer full, clear tbusy. */
1105 np->tx_full = 0;
1106 wmb();
1107 netif_wake_queue(dev);
1108 }
1109}
1110
1111/* The interrupt handler does all of the Rx thread work and cleans up
1112 after the Tx thread. */
1113static irqreturn_t intr_handler(int irq, void *dev_instance)
1114{
1115 struct net_device *dev = (struct net_device *)dev_instance;
1116 struct netdev_private *np = netdev_priv(dev);
1117 void __iomem *ioaddr = np->base_addr;
1118 int work_limit = max_interrupt_work;
1119 int handled = 0;
1120
1121 if (!netif_device_present(dev))
1122 return IRQ_NONE;
1123 do {
1124 u32 intr_status = ioread32(ioaddr + IntrStatus);
1125
1126 /* Acknowledge all of the current interrupt sources ASAP. */
1127 iowrite32(intr_status & 0x001ffff, ioaddr + IntrStatus);
1128
1129 if (debug > 4)
1130 netdev_dbg(dev, "Interrupt, status %04x\n", intr_status);
1131
1132 if ((intr_status & (NormalIntr|AbnormalIntr)) == 0)
1133 break;
1134
1135 handled = 1;
1136
1137 if (intr_status & (RxIntr | RxNoBuf))
1138 netdev_rx(dev);
1139 if (intr_status & RxNoBuf)
1140 iowrite32(0, ioaddr + RxStartDemand);
1141
1142 if (intr_status & (TxNoBuf | TxIntr) &&
1143 np->cur_tx != np->dirty_tx) {
1144 spin_lock(&np->lock);
1145 netdev_tx_done(dev);
1146 spin_unlock(&np->lock);
1147 }
1148
1149 /* Abnormal error summary/uncommon events handlers. */
1150 if (intr_status & (AbnormalIntr | TxFIFOUnderflow | SystemError |
1151 TimerInt | TxDied))
1152 netdev_error(dev, intr_status);
1153
1154 if (--work_limit < 0) {
1155 dev_warn(&dev->dev,
1156 "Too much work at interrupt, status=0x%04x\n",
1157 intr_status);
1158 /* Set the timer to re-enable the other interrupts after
1159 10*82usec ticks. */
1160 spin_lock(&np->lock);
1161 if (netif_device_present(dev)) {
1162 iowrite32(AbnormalIntr | TimerInt, ioaddr + IntrEnable);
1163 iowrite32(10, ioaddr + GPTimer);
1164 }
1165 spin_unlock(&np->lock);
1166 break;
1167 }
1168 } while (1);
1169
1170 if (debug > 3)
1171 netdev_dbg(dev, "exiting interrupt, status=%#4.4x\n",
1172 ioread32(ioaddr + IntrStatus));
1173 return IRQ_RETVAL(handled);
1174}
1175
1176/* This routine is logically part of the interrupt handler, but separated
1177 for clarity and better register allocation. */
1178static int netdev_rx(struct net_device *dev)
1179{
1180 struct netdev_private *np = netdev_priv(dev);
1181 int entry = np->cur_rx % RX_RING_SIZE;
1182 int work_limit = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
1183
1184 if (debug > 4) {
1185 netdev_dbg(dev, " In netdev_rx(), entry %d status %04x\n",
1186 entry, np->rx_ring[entry].status);
1187 }
1188
1189 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1190 while (--work_limit >= 0) {
1191 struct w840_rx_desc *desc = np->rx_head_desc;
1192 s32 status = desc->status;
1193
1194 if (debug > 4)
1195 netdev_dbg(dev, " netdev_rx() status was %08x\n",
1196 status);
1197 if (status < 0)
1198 break;
1199 if ((status & 0x38008300) != 0x0300) {
1200 if ((status & 0x38000300) != 0x0300) {
1201 /* Ingore earlier buffers. */
1202 if ((status & 0xffff) != 0x7fff) {
1203 dev_warn(&dev->dev,
1204 "Oversized Ethernet frame spanned multiple buffers, entry %#x status %04x!\n",
1205 np->cur_rx, status);
1206 np->stats.rx_length_errors++;
1207 }
1208 } else if (status & 0x8000) {
1209 /* There was a fatal error. */
1210 if (debug > 2)
1211 netdev_dbg(dev, "Receive error, Rx status %08x\n",
1212 status);
1213 np->stats.rx_errors++; /* end of a packet.*/
1214 if (status & 0x0890) np->stats.rx_length_errors++;
1215 if (status & 0x004C) np->stats.rx_frame_errors++;
1216 if (status & 0x0002) np->stats.rx_crc_errors++;
1217 }
1218 } else {
1219 struct sk_buff *skb;
1220 /* Omit the four octet CRC from the length. */
1221 int pkt_len = ((status >> 16) & 0x7ff) - 4;
1222
1223#ifndef final_version
1224 if (debug > 4)
1225 netdev_dbg(dev, " netdev_rx() normal Rx pkt length %d status %x\n",
1226 pkt_len, status);
1227#endif
1228 /* Check if the packet is long enough to accept without copying
1229 to a minimally-sized skbuff. */
1230 if (pkt_len < rx_copybreak &&
1231 (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
1232 skb_reserve(skb, 2); /* 16 byte align the IP header */
1233 pci_dma_sync_single_for_cpu(np->pci_dev,np->rx_addr[entry],
1234 np->rx_skbuff[entry]->len,
1235 PCI_DMA_FROMDEVICE);
1236 skb_copy_to_linear_data(skb, np->rx_skbuff[entry]->data, pkt_len);
1237 skb_put(skb, pkt_len);
1238 pci_dma_sync_single_for_device(np->pci_dev,np->rx_addr[entry],
1239 np->rx_skbuff[entry]->len,
1240 PCI_DMA_FROMDEVICE);
1241 } else {
1242 pci_unmap_single(np->pci_dev,np->rx_addr[entry],
1243 np->rx_skbuff[entry]->len,
1244 PCI_DMA_FROMDEVICE);
1245 skb_put(skb = np->rx_skbuff[entry], pkt_len);
1246 np->rx_skbuff[entry] = NULL;
1247 }
1248#ifndef final_version /* Remove after testing. */
1249 /* You will want this info for the initial debug. */
1250 if (debug > 5)
1251 netdev_dbg(dev, " Rx data %pM %pM %02x%02x %pI4\n",
1252 &skb->data[0], &skb->data[6],
1253 skb->data[12], skb->data[13],
1254 &skb->data[14]);
1255#endif
1256 skb->protocol = eth_type_trans(skb, dev);
1257 netif_rx(skb);
1258 np->stats.rx_packets++;
1259 np->stats.rx_bytes += pkt_len;
1260 }
1261 entry = (++np->cur_rx) % RX_RING_SIZE;
1262 np->rx_head_desc = &np->rx_ring[entry];
1263 }
1264
1265 /* Refill the Rx ring buffers. */
1266 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1267 struct sk_buff *skb;
1268 entry = np->dirty_rx % RX_RING_SIZE;
1269 if (np->rx_skbuff[entry] == NULL) {
1270 skb = netdev_alloc_skb(dev, np->rx_buf_sz);
1271 np->rx_skbuff[entry] = skb;
1272 if (skb == NULL)
1273 break; /* Better luck next round. */
1274 np->rx_addr[entry] = pci_map_single(np->pci_dev,
1275 skb->data,
1276 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1277 np->rx_ring[entry].buffer1 = np->rx_addr[entry];
1278 }
1279 wmb();
1280 np->rx_ring[entry].status = DescOwned;
1281 }
1282
1283 return 0;
1284}
1285
1286static void netdev_error(struct net_device *dev, int intr_status)
1287{
1288 struct netdev_private *np = netdev_priv(dev);
1289 void __iomem *ioaddr = np->base_addr;
1290
1291 if (debug > 2)
1292 netdev_dbg(dev, "Abnormal event, %08x\n", intr_status);
1293 if (intr_status == 0xffffffff)
1294 return;
1295 spin_lock(&np->lock);
1296 if (intr_status & TxFIFOUnderflow) {
1297 int new;
1298 /* Bump up the Tx threshold */
1299#if 0
1300 /* This causes lots of dropped packets,
1301 * and under high load even tx_timeouts
1302 */
1303 new = np->csr6 + 0x4000;
1304#else
1305 new = (np->csr6 >> 14)&0x7f;
1306 if (new < 64)
1307 new *= 2;
1308 else
1309 new = 127; /* load full packet before starting */
1310 new = (np->csr6 & ~(0x7F << 14)) | (new<<14);
1311#endif
1312 netdev_dbg(dev, "Tx underflow, new csr6 %08x\n", new);
1313 update_csr6(dev, new);
1314 }
1315 if (intr_status & RxDied) { /* Missed a Rx frame. */
1316 np->stats.rx_errors++;
1317 }
1318 if (intr_status & TimerInt) {
1319 /* Re-enable other interrupts. */
1320 if (netif_device_present(dev))
1321 iowrite32(0x1A0F5, ioaddr + IntrEnable);
1322 }
1323 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1324 iowrite32(0, ioaddr + RxStartDemand);
1325 spin_unlock(&np->lock);
1326}
1327
1328static struct net_device_stats *get_stats(struct net_device *dev)
1329{
1330 struct netdev_private *np = netdev_priv(dev);
1331 void __iomem *ioaddr = np->base_addr;
1332
1333 /* The chip only need report frame silently dropped. */
1334 spin_lock_irq(&np->lock);
1335 if (netif_running(dev) && netif_device_present(dev))
1336 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1337 spin_unlock_irq(&np->lock);
1338
1339 return &np->stats;
1340}
1341
1342
1343static u32 __set_rx_mode(struct net_device *dev)
1344{
1345 struct netdev_private *np = netdev_priv(dev);
1346 void __iomem *ioaddr = np->base_addr;
1347 u32 mc_filter[2]; /* Multicast hash filter */
1348 u32 rx_mode;
1349
1350 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1351 memset(mc_filter, 0xff, sizeof(mc_filter));
1352 rx_mode = RxAcceptBroadcast | AcceptMulticast | RxAcceptAllPhys
1353 | AcceptMyPhys;
1354 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
1355 (dev->flags & IFF_ALLMULTI)) {
1356 /* Too many to match, or accept all multicasts. */
1357 memset(mc_filter, 0xff, sizeof(mc_filter));
1358 rx_mode = RxAcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1359 } else {
1360 struct netdev_hw_addr *ha;
1361
1362 memset(mc_filter, 0, sizeof(mc_filter));
1363 netdev_for_each_mc_addr(ha, dev) {
1364 int filbit;
1365
1366 filbit = (ether_crc(ETH_ALEN, ha->addr) >> 26) ^ 0x3F;
1367 filbit &= 0x3f;
1368 mc_filter[filbit >> 5] |= 1 << (filbit & 31);
1369 }
1370 rx_mode = RxAcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1371 }
1372 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
1373 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
1374 return rx_mode;
1375}
1376
1377static void set_rx_mode(struct net_device *dev)
1378{
1379 struct netdev_private *np = netdev_priv(dev);
1380 u32 rx_mode = __set_rx_mode(dev);
1381 spin_lock_irq(&np->lock);
1382 update_csr6(dev, (np->csr6 & ~0x00F8) | rx_mode);
1383 spin_unlock_irq(&np->lock);
1384}
1385
1386static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1387{
1388 struct netdev_private *np = netdev_priv(dev);
1389
1390 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1391 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1392 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
1393}
1394
1395static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1396{
1397 struct netdev_private *np = netdev_priv(dev);
1398 int rc;
1399
1400 spin_lock_irq(&np->lock);
1401 rc = mii_ethtool_gset(&np->mii_if, cmd);
1402 spin_unlock_irq(&np->lock);
1403
1404 return rc;
1405}
1406
1407static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1408{
1409 struct netdev_private *np = netdev_priv(dev);
1410 int rc;
1411
1412 spin_lock_irq(&np->lock);
1413 rc = mii_ethtool_sset(&np->mii_if, cmd);
1414 spin_unlock_irq(&np->lock);
1415
1416 return rc;
1417}
1418
1419static int netdev_nway_reset(struct net_device *dev)
1420{
1421 struct netdev_private *np = netdev_priv(dev);
1422 return mii_nway_restart(&np->mii_if);
1423}
1424
1425static u32 netdev_get_link(struct net_device *dev)
1426{
1427 struct netdev_private *np = netdev_priv(dev);
1428 return mii_link_ok(&np->mii_if);
1429}
1430
1431static u32 netdev_get_msglevel(struct net_device *dev)
1432{
1433 return debug;
1434}
1435
1436static void netdev_set_msglevel(struct net_device *dev, u32 value)
1437{
1438 debug = value;
1439}
1440
1441static const struct ethtool_ops netdev_ethtool_ops = {
1442 .get_drvinfo = netdev_get_drvinfo,
1443 .get_settings = netdev_get_settings,
1444 .set_settings = netdev_set_settings,
1445 .nway_reset = netdev_nway_reset,
1446 .get_link = netdev_get_link,
1447 .get_msglevel = netdev_get_msglevel,
1448 .set_msglevel = netdev_set_msglevel,
1449};
1450
1451static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1452{
1453 struct mii_ioctl_data *data = if_mii(rq);
1454 struct netdev_private *np = netdev_priv(dev);
1455
1456 switch(cmd) {
1457 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1458 data->phy_id = ((struct netdev_private *)netdev_priv(dev))->phys[0] & 0x1f;
1459 /* Fall Through */
1460
1461 case SIOCGMIIREG: /* Read MII PHY register. */
1462 spin_lock_irq(&np->lock);
1463 data->val_out = mdio_read(dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1464 spin_unlock_irq(&np->lock);
1465 return 0;
1466
1467 case SIOCSMIIREG: /* Write MII PHY register. */
1468 spin_lock_irq(&np->lock);
1469 mdio_write(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1470 spin_unlock_irq(&np->lock);
1471 return 0;
1472 default:
1473 return -EOPNOTSUPP;
1474 }
1475}
1476
1477static int netdev_close(struct net_device *dev)
1478{
1479 struct netdev_private *np = netdev_priv(dev);
1480 void __iomem *ioaddr = np->base_addr;
1481
1482 netif_stop_queue(dev);
1483
1484 if (debug > 1) {
1485 netdev_dbg(dev, "Shutting down ethercard, status was %08x Config %08x\n",
1486 ioread32(ioaddr + IntrStatus),
1487 ioread32(ioaddr + NetworkConfig));
1488 netdev_dbg(dev, "Queue pointers were Tx %d / %d, Rx %d / %d\n",
1489 np->cur_tx, np->dirty_tx,
1490 np->cur_rx, np->dirty_rx);
1491 }
1492
1493 /* Stop the chip's Tx and Rx processes. */
1494 spin_lock_irq(&np->lock);
1495 netif_device_detach(dev);
1496 update_csr6(dev, 0);
1497 iowrite32(0x0000, ioaddr + IntrEnable);
1498 spin_unlock_irq(&np->lock);
1499
1500 free_irq(np->pci_dev->irq, dev);
1501 wmb();
1502 netif_device_attach(dev);
1503
1504 if (ioread32(ioaddr + NetworkConfig) != 0xffffffff)
1505 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1506
1507#ifdef __i386__
1508 if (debug > 2) {
1509 int i;
1510
1511 printk(KERN_DEBUG" Tx ring at %p:\n", np->tx_ring);
1512 for (i = 0; i < TX_RING_SIZE; i++)
1513 printk(KERN_DEBUG " #%d desc. %04x %04x %08x\n",
1514 i, np->tx_ring[i].length,
1515 np->tx_ring[i].status, np->tx_ring[i].buffer1);
1516 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1517 for (i = 0; i < RX_RING_SIZE; i++) {
1518 printk(KERN_DEBUG " #%d desc. %04x %04x %08x\n",
1519 i, np->rx_ring[i].length,
1520 np->rx_ring[i].status, np->rx_ring[i].buffer1);
1521 }
1522 }
1523#endif /* __i386__ debugging only */
1524
1525 del_timer_sync(&np->timer);
1526
1527 free_rxtx_rings(np);
1528 free_ringdesc(np);
1529
1530 return 0;
1531}
1532
1533static void w840_remove1(struct pci_dev *pdev)
1534{
1535 struct net_device *dev = pci_get_drvdata(pdev);
1536
1537 if (dev) {
1538 struct netdev_private *np = netdev_priv(dev);
1539 unregister_netdev(dev);
1540 pci_release_regions(pdev);
1541 pci_iounmap(pdev, np->base_addr);
1542 free_netdev(dev);
1543 }
1544}
1545
1546#ifdef CONFIG_PM
1547
1548/*
1549 * suspend/resume synchronization:
1550 * - open, close, do_ioctl:
1551 * rtnl_lock, & netif_device_detach after the rtnl_unlock.
1552 * - get_stats:
1553 * spin_lock_irq(np->lock), doesn't touch hw if not present
1554 * - start_xmit:
1555 * synchronize_irq + netif_tx_disable;
1556 * - tx_timeout:
1557 * netif_device_detach + netif_tx_disable;
1558 * - set_multicast_list
1559 * netif_device_detach + netif_tx_disable;
1560 * - interrupt handler
1561 * doesn't touch hw if not present, synchronize_irq waits for
1562 * running instances of the interrupt handler.
1563 *
1564 * Disabling hw requires clearing csr6 & IntrEnable.
1565 * update_csr6 & all function that write IntrEnable check netif_device_present
1566 * before settings any bits.
1567 *
1568 * Detach must occur under spin_unlock_irq(), interrupts from a detached
1569 * device would cause an irq storm.
1570 */
1571static int w840_suspend (struct pci_dev *pdev, pm_message_t state)
1572{
1573 struct net_device *dev = pci_get_drvdata (pdev);
1574 struct netdev_private *np = netdev_priv(dev);
1575 void __iomem *ioaddr = np->base_addr;
1576
1577 rtnl_lock();
1578 if (netif_running (dev)) {
1579 del_timer_sync(&np->timer);
1580
1581 spin_lock_irq(&np->lock);
1582 netif_device_detach(dev);
1583 update_csr6(dev, 0);
1584 iowrite32(0, ioaddr + IntrEnable);
1585 spin_unlock_irq(&np->lock);
1586
1587 synchronize_irq(np->pci_dev->irq);
1588 netif_tx_disable(dev);
1589
1590 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1591
1592 /* no more hardware accesses behind this line. */
1593
1594 BUG_ON(np->csr6 || ioread32(ioaddr + IntrEnable));
1595
1596 /* pci_power_off(pdev, -1); */
1597
1598 free_rxtx_rings(np);
1599 } else {
1600 netif_device_detach(dev);
1601 }
1602 rtnl_unlock();
1603 return 0;
1604}
1605
1606static int w840_resume (struct pci_dev *pdev)
1607{
1608 struct net_device *dev = pci_get_drvdata (pdev);
1609 struct netdev_private *np = netdev_priv(dev);
1610 int retval = 0;
1611
1612 rtnl_lock();
1613 if (netif_device_present(dev))
1614 goto out; /* device not suspended */
1615 if (netif_running(dev)) {
1616 if ((retval = pci_enable_device(pdev))) {
1617 dev_err(&dev->dev,
1618 "pci_enable_device failed in resume\n");
1619 goto out;
1620 }
1621 spin_lock_irq(&np->lock);
1622 iowrite32(1, np->base_addr+PCIBusCfg);
1623 ioread32(np->base_addr+PCIBusCfg);
1624 udelay(1);
1625 netif_device_attach(dev);
1626 init_rxtx_rings(dev);
1627 init_registers(dev);
1628 spin_unlock_irq(&np->lock);
1629
1630 netif_wake_queue(dev);
1631
1632 mod_timer(&np->timer, jiffies + 1*HZ);
1633 } else {
1634 netif_device_attach(dev);
1635 }
1636out:
1637 rtnl_unlock();
1638 return retval;
1639}
1640#endif
1641
1642static struct pci_driver w840_driver = {
1643 .name = DRV_NAME,
1644 .id_table = w840_pci_tbl,
1645 .probe = w840_probe1,
1646 .remove = w840_remove1,
1647#ifdef CONFIG_PM
1648 .suspend = w840_suspend,
1649 .resume = w840_resume,
1650#endif
1651};
1652
1653static int __init w840_init(void)
1654{
1655 printk(version);
1656 return pci_register_driver(&w840_driver);
1657}
1658
1659static void __exit w840_exit(void)
1660{
1661 pci_unregister_driver(&w840_driver);
1662}
1663
1664module_init(w840_init);
1665module_exit(w840_exit);