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1/*
2 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips
3 *
4 * Author: Mike Lavender, mike@steroidmicros.com
5 *
6 * Copyright (c) 2005, Intec Automation Inc.
7 *
8 * Some parts are based on lart.c by Abraham Van Der Merwe
9 *
10 * Cleaned up and generalized based on mtd_dataflash.c
11 *
12 * This code is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18#include <linux/err.h>
19#include <linux/errno.h>
20#include <linux/module.h>
21#include <linux/device.h>
22#include <linux/interrupt.h>
23#include <linux/mutex.h>
24#include <linux/math64.h>
25#include <linux/slab.h>
26#include <linux/sched.h>
27#include <linux/mod_devicetable.h>
28
29#include <linux/mtd/cfi.h>
30#include <linux/mtd/mtd.h>
31#include <linux/mtd/partitions.h>
32#include <linux/of_platform.h>
33
34#include <linux/spi/spi.h>
35#include <linux/spi/flash.h>
36
37/* Flash opcodes. */
38#define OPCODE_WREN 0x06 /* Write enable */
39#define OPCODE_RDSR 0x05 /* Read status register */
40#define OPCODE_WRSR 0x01 /* Write status register 1 byte */
41#define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
42#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
43#define OPCODE_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */
44#define OPCODE_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */
45#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
46#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
47#define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
48#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
49#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
50#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
51#define OPCODE_RDID 0x9f /* Read JEDEC ID */
52#define OPCODE_RDCR 0x35 /* Read configuration register */
53
54/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
55#define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */
56#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
57#define OPCODE_DUAL_READ_4B 0x3c /* Read data bytes (Dual SPI) */
58#define OPCODE_QUAD_READ_4B 0x6c /* Read data bytes (Quad SPI) */
59#define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */
60#define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */
61
62/* Used for SST flashes only. */
63#define OPCODE_BP 0x02 /* Byte program */
64#define OPCODE_WRDI 0x04 /* Write disable */
65#define OPCODE_AAI_WP 0xad /* Auto address increment word program */
66
67/* Used for Macronix and Winbond flashes. */
68#define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */
69#define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */
70
71/* Used for Spansion flashes only. */
72#define OPCODE_BRWR 0x17 /* Bank register write */
73
74/* Status Register bits. */
75#define SR_WIP 1 /* Write in progress */
76#define SR_WEL 2 /* Write enable latch */
77/* meaning of other SR_* bits may differ between vendors */
78#define SR_BP0 4 /* Block protect 0 */
79#define SR_BP1 8 /* Block protect 1 */
80#define SR_BP2 0x10 /* Block protect 2 */
81#define SR_SRWD 0x80 /* SR write protect */
82
83#define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
84
85/* Configuration Register bits. */
86#define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */
87
88/* Define max times to check status register before we give up. */
89#define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
90#define MAX_CMD_SIZE 6
91
92#define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
93
94/****************************************************************************/
95
96enum read_type {
97 M25P80_NORMAL = 0,
98 M25P80_FAST,
99 M25P80_DUAL,
100 M25P80_QUAD,
101};
102
103struct m25p {
104 struct spi_device *spi;
105 struct mutex lock;
106 struct mtd_info mtd;
107 u16 page_size;
108 u16 addr_width;
109 u8 erase_opcode;
110 u8 read_opcode;
111 u8 program_opcode;
112 u8 *command;
113 enum read_type flash_read;
114};
115
116static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
117{
118 return container_of(mtd, struct m25p, mtd);
119}
120
121/****************************************************************************/
122
123/*
124 * Internal helper functions
125 */
126
127/*
128 * Read the status register, returning its value in the location
129 * Return the status register value.
130 * Returns negative if error occurred.
131 */
132static int read_sr(struct m25p *flash)
133{
134 ssize_t retval;
135 u8 code = OPCODE_RDSR;
136 u8 val;
137
138 retval = spi_write_then_read(flash->spi, &code, 1, &val, 1);
139
140 if (retval < 0) {
141 dev_err(&flash->spi->dev, "error %d reading SR\n",
142 (int) retval);
143 return retval;
144 }
145
146 return val;
147}
148
149/*
150 * Read configuration register, returning its value in the
151 * location. Return the configuration register value.
152 * Returns negative if error occured.
153 */
154static int read_cr(struct m25p *flash)
155{
156 u8 code = OPCODE_RDCR;
157 int ret;
158 u8 val;
159
160 ret = spi_write_then_read(flash->spi, &code, 1, &val, 1);
161 if (ret < 0) {
162 dev_err(&flash->spi->dev, "error %d reading CR\n", ret);
163 return ret;
164 }
165
166 return val;
167}
168
169/*
170 * Write status register 1 byte
171 * Returns negative if error occurred.
172 */
173static int write_sr(struct m25p *flash, u8 val)
174{
175 flash->command[0] = OPCODE_WRSR;
176 flash->command[1] = val;
177
178 return spi_write(flash->spi, flash->command, 2);
179}
180
181/*
182 * Set write enable latch with Write Enable command.
183 * Returns negative if error occurred.
184 */
185static inline int write_enable(struct m25p *flash)
186{
187 u8 code = OPCODE_WREN;
188
189 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
190}
191
192/*
193 * Send write disble instruction to the chip.
194 */
195static inline int write_disable(struct m25p *flash)
196{
197 u8 code = OPCODE_WRDI;
198
199 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
200}
201
202/*
203 * Enable/disable 4-byte addressing mode.
204 */
205static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable)
206{
207 int status;
208 bool need_wren = false;
209
210 switch (JEDEC_MFR(jedec_id)) {
211 case CFI_MFR_ST: /* Micron, actually */
212 /* Some Micron need WREN command; all will accept it */
213 need_wren = true;
214 case CFI_MFR_MACRONIX:
215 case 0xEF /* winbond */:
216 if (need_wren)
217 write_enable(flash);
218
219 flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B;
220 status = spi_write(flash->spi, flash->command, 1);
221
222 if (need_wren)
223 write_disable(flash);
224
225 return status;
226 default:
227 /* Spansion style */
228 flash->command[0] = OPCODE_BRWR;
229 flash->command[1] = enable << 7;
230 return spi_write(flash->spi, flash->command, 2);
231 }
232}
233
234/*
235 * Service routine to read status register until ready, or timeout occurs.
236 * Returns non-zero if error.
237 */
238static int wait_till_ready(struct m25p *flash)
239{
240 unsigned long deadline;
241 int sr;
242
243 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
244
245 do {
246 if ((sr = read_sr(flash)) < 0)
247 break;
248 else if (!(sr & SR_WIP))
249 return 0;
250
251 cond_resched();
252
253 } while (!time_after_eq(jiffies, deadline));
254
255 return 1;
256}
257
258/*
259 * Write status Register and configuration register with 2 bytes
260 * The first byte will be written to the status register, while the
261 * second byte will be written to the configuration register.
262 * Return negative if error occured.
263 */
264static int write_sr_cr(struct m25p *flash, u16 val)
265{
266 flash->command[0] = OPCODE_WRSR;
267 flash->command[1] = val & 0xff;
268 flash->command[2] = (val >> 8);
269
270 return spi_write(flash->spi, flash->command, 3);
271}
272
273static int macronix_quad_enable(struct m25p *flash)
274{
275 int ret, val;
276 u8 cmd[2];
277 cmd[0] = OPCODE_WRSR;
278
279 val = read_sr(flash);
280 cmd[1] = val | SR_QUAD_EN_MX;
281 write_enable(flash);
282
283 spi_write(flash->spi, &cmd, 2);
284
285 if (wait_till_ready(flash))
286 return 1;
287
288 ret = read_sr(flash);
289 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
290 dev_err(&flash->spi->dev, "Macronix Quad bit not set\n");
291 return -EINVAL;
292 }
293
294 return 0;
295}
296
297static int spansion_quad_enable(struct m25p *flash)
298{
299 int ret;
300 int quad_en = CR_QUAD_EN_SPAN << 8;
301
302 write_enable(flash);
303
304 ret = write_sr_cr(flash, quad_en);
305 if (ret < 0) {
306 dev_err(&flash->spi->dev,
307 "error while writing configuration register\n");
308 return -EINVAL;
309 }
310
311 /* read back and check it */
312 ret = read_cr(flash);
313 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
314 dev_err(&flash->spi->dev, "Spansion Quad bit not set\n");
315 return -EINVAL;
316 }
317
318 return 0;
319}
320
321static int set_quad_mode(struct m25p *flash, u32 jedec_id)
322{
323 int status;
324
325 switch (JEDEC_MFR(jedec_id)) {
326 case CFI_MFR_MACRONIX:
327 status = macronix_quad_enable(flash);
328 if (status) {
329 dev_err(&flash->spi->dev,
330 "Macronix quad-read not enabled\n");
331 return -EINVAL;
332 }
333 return status;
334 default:
335 status = spansion_quad_enable(flash);
336 if (status) {
337 dev_err(&flash->spi->dev,
338 "Spansion quad-read not enabled\n");
339 return -EINVAL;
340 }
341 return status;
342 }
343}
344
345/*
346 * Erase the whole flash memory
347 *
348 * Returns 0 if successful, non-zero otherwise.
349 */
350static int erase_chip(struct m25p *flash)
351{
352 pr_debug("%s: %s %lldKiB\n", dev_name(&flash->spi->dev), __func__,
353 (long long)(flash->mtd.size >> 10));
354
355 /* Wait until finished previous write command. */
356 if (wait_till_ready(flash))
357 return 1;
358
359 /* Send write enable, then erase commands. */
360 write_enable(flash);
361
362 /* Set up command buffer. */
363 flash->command[0] = OPCODE_CHIP_ERASE;
364
365 spi_write(flash->spi, flash->command, 1);
366
367 return 0;
368}
369
370static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd)
371{
372 /* opcode is in cmd[0] */
373 cmd[1] = addr >> (flash->addr_width * 8 - 8);
374 cmd[2] = addr >> (flash->addr_width * 8 - 16);
375 cmd[3] = addr >> (flash->addr_width * 8 - 24);
376 cmd[4] = addr >> (flash->addr_width * 8 - 32);
377}
378
379static int m25p_cmdsz(struct m25p *flash)
380{
381 return 1 + flash->addr_width;
382}
383
384/*
385 * Erase one sector of flash memory at offset ``offset'' which is any
386 * address within the sector which should be erased.
387 *
388 * Returns 0 if successful, non-zero otherwise.
389 */
390static int erase_sector(struct m25p *flash, u32 offset)
391{
392 pr_debug("%s: %s %dKiB at 0x%08x\n", dev_name(&flash->spi->dev),
393 __func__, flash->mtd.erasesize / 1024, offset);
394
395 /* Wait until finished previous write command. */
396 if (wait_till_ready(flash))
397 return 1;
398
399 /* Send write enable, then erase commands. */
400 write_enable(flash);
401
402 /* Set up command buffer. */
403 flash->command[0] = flash->erase_opcode;
404 m25p_addr2cmd(flash, offset, flash->command);
405
406 spi_write(flash->spi, flash->command, m25p_cmdsz(flash));
407
408 return 0;
409}
410
411/****************************************************************************/
412
413/*
414 * MTD implementation
415 */
416
417/*
418 * Erase an address range on the flash chip. The address range may extend
419 * one or more erase sectors. Return an error is there is a problem erasing.
420 */
421static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
422{
423 struct m25p *flash = mtd_to_m25p(mtd);
424 u32 addr,len;
425 uint32_t rem;
426
427 pr_debug("%s: %s at 0x%llx, len %lld\n", dev_name(&flash->spi->dev),
428 __func__, (long long)instr->addr,
429 (long long)instr->len);
430
431 div_u64_rem(instr->len, mtd->erasesize, &rem);
432 if (rem)
433 return -EINVAL;
434
435 addr = instr->addr;
436 len = instr->len;
437
438 mutex_lock(&flash->lock);
439
440 /* whole-chip erase? */
441 if (len == flash->mtd.size) {
442 if (erase_chip(flash)) {
443 instr->state = MTD_ERASE_FAILED;
444 mutex_unlock(&flash->lock);
445 return -EIO;
446 }
447
448 /* REVISIT in some cases we could speed up erasing large regions
449 * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up
450 * to use "small sector erase", but that's not always optimal.
451 */
452
453 /* "sector"-at-a-time erase */
454 } else {
455 while (len) {
456 if (erase_sector(flash, addr)) {
457 instr->state = MTD_ERASE_FAILED;
458 mutex_unlock(&flash->lock);
459 return -EIO;
460 }
461
462 addr += mtd->erasesize;
463 len -= mtd->erasesize;
464 }
465 }
466
467 mutex_unlock(&flash->lock);
468
469 instr->state = MTD_ERASE_DONE;
470 mtd_erase_callback(instr);
471
472 return 0;
473}
474
475/*
476 * Dummy Cycle calculation for different type of read.
477 * It can be used to support more commands with
478 * different dummy cycle requirements.
479 */
480static inline int m25p80_dummy_cycles_read(struct m25p *flash)
481{
482 switch (flash->flash_read) {
483 case M25P80_FAST:
484 case M25P80_DUAL:
485 case M25P80_QUAD:
486 return 1;
487 case M25P80_NORMAL:
488 return 0;
489 default:
490 dev_err(&flash->spi->dev, "No valid read type supported\n");
491 return -1;
492 }
493}
494
495static inline unsigned int m25p80_rx_nbits(const struct m25p *flash)
496{
497 switch (flash->flash_read) {
498 case M25P80_DUAL:
499 return 2;
500 case M25P80_QUAD:
501 return 4;
502 default:
503 return 0;
504 }
505}
506
507/*
508 * Read an address range from the flash chip. The address range
509 * may be any size provided it is within the physical boundaries.
510 */
511static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
512 size_t *retlen, u_char *buf)
513{
514 struct m25p *flash = mtd_to_m25p(mtd);
515 struct spi_transfer t[2];
516 struct spi_message m;
517 uint8_t opcode;
518 int dummy;
519
520 pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
521 __func__, (u32)from, len);
522
523 spi_message_init(&m);
524 memset(t, 0, (sizeof t));
525
526 dummy = m25p80_dummy_cycles_read(flash);
527 if (dummy < 0) {
528 dev_err(&flash->spi->dev, "No valid read command supported\n");
529 return -EINVAL;
530 }
531
532 t[0].tx_buf = flash->command;
533 t[0].len = m25p_cmdsz(flash) + dummy;
534 spi_message_add_tail(&t[0], &m);
535
536 t[1].rx_buf = buf;
537 t[1].rx_nbits = m25p80_rx_nbits(flash);
538 t[1].len = len;
539 spi_message_add_tail(&t[1], &m);
540
541 mutex_lock(&flash->lock);
542
543 /* Wait till previous write/erase is done. */
544 if (wait_till_ready(flash)) {
545 /* REVISIT status return?? */
546 mutex_unlock(&flash->lock);
547 return 1;
548 }
549
550 /* Set up the write data buffer. */
551 opcode = flash->read_opcode;
552 flash->command[0] = opcode;
553 m25p_addr2cmd(flash, from, flash->command);
554
555 spi_sync(flash->spi, &m);
556
557 *retlen = m.actual_length - m25p_cmdsz(flash) - dummy;
558
559 mutex_unlock(&flash->lock);
560
561 return 0;
562}
563
564/*
565 * Write an address range to the flash chip. Data must be written in
566 * FLASH_PAGESIZE chunks. The address range may be any size provided
567 * it is within the physical boundaries.
568 */
569static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len,
570 size_t *retlen, const u_char *buf)
571{
572 struct m25p *flash = mtd_to_m25p(mtd);
573 u32 page_offset, page_size;
574 struct spi_transfer t[2];
575 struct spi_message m;
576
577 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
578 __func__, (u32)to, len);
579
580 spi_message_init(&m);
581 memset(t, 0, (sizeof t));
582
583 t[0].tx_buf = flash->command;
584 t[0].len = m25p_cmdsz(flash);
585 spi_message_add_tail(&t[0], &m);
586
587 t[1].tx_buf = buf;
588 spi_message_add_tail(&t[1], &m);
589
590 mutex_lock(&flash->lock);
591
592 /* Wait until finished previous write command. */
593 if (wait_till_ready(flash)) {
594 mutex_unlock(&flash->lock);
595 return 1;
596 }
597
598 write_enable(flash);
599
600 /* Set up the opcode in the write buffer. */
601 flash->command[0] = flash->program_opcode;
602 m25p_addr2cmd(flash, to, flash->command);
603
604 page_offset = to & (flash->page_size - 1);
605
606 /* do all the bytes fit onto one page? */
607 if (page_offset + len <= flash->page_size) {
608 t[1].len = len;
609
610 spi_sync(flash->spi, &m);
611
612 *retlen = m.actual_length - m25p_cmdsz(flash);
613 } else {
614 u32 i;
615
616 /* the size of data remaining on the first page */
617 page_size = flash->page_size - page_offset;
618
619 t[1].len = page_size;
620 spi_sync(flash->spi, &m);
621
622 *retlen = m.actual_length - m25p_cmdsz(flash);
623
624 /* write everything in flash->page_size chunks */
625 for (i = page_size; i < len; i += page_size) {
626 page_size = len - i;
627 if (page_size > flash->page_size)
628 page_size = flash->page_size;
629
630 /* write the next page to flash */
631 m25p_addr2cmd(flash, to + i, flash->command);
632
633 t[1].tx_buf = buf + i;
634 t[1].len = page_size;
635
636 wait_till_ready(flash);
637
638 write_enable(flash);
639
640 spi_sync(flash->spi, &m);
641
642 *retlen += m.actual_length - m25p_cmdsz(flash);
643 }
644 }
645
646 mutex_unlock(&flash->lock);
647
648 return 0;
649}
650
651static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
652 size_t *retlen, const u_char *buf)
653{
654 struct m25p *flash = mtd_to_m25p(mtd);
655 struct spi_transfer t[2];
656 struct spi_message m;
657 size_t actual;
658 int cmd_sz, ret;
659
660 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
661 __func__, (u32)to, len);
662
663 spi_message_init(&m);
664 memset(t, 0, (sizeof t));
665
666 t[0].tx_buf = flash->command;
667 t[0].len = m25p_cmdsz(flash);
668 spi_message_add_tail(&t[0], &m);
669
670 t[1].tx_buf = buf;
671 spi_message_add_tail(&t[1], &m);
672
673 mutex_lock(&flash->lock);
674
675 /* Wait until finished previous write command. */
676 ret = wait_till_ready(flash);
677 if (ret)
678 goto time_out;
679
680 write_enable(flash);
681
682 actual = to % 2;
683 /* Start write from odd address. */
684 if (actual) {
685 flash->command[0] = OPCODE_BP;
686 m25p_addr2cmd(flash, to, flash->command);
687
688 /* write one byte. */
689 t[1].len = 1;
690 spi_sync(flash->spi, &m);
691 ret = wait_till_ready(flash);
692 if (ret)
693 goto time_out;
694 *retlen += m.actual_length - m25p_cmdsz(flash);
695 }
696 to += actual;
697
698 flash->command[0] = OPCODE_AAI_WP;
699 m25p_addr2cmd(flash, to, flash->command);
700
701 /* Write out most of the data here. */
702 cmd_sz = m25p_cmdsz(flash);
703 for (; actual < len - 1; actual += 2) {
704 t[0].len = cmd_sz;
705 /* write two bytes. */
706 t[1].len = 2;
707 t[1].tx_buf = buf + actual;
708
709 spi_sync(flash->spi, &m);
710 ret = wait_till_ready(flash);
711 if (ret)
712 goto time_out;
713 *retlen += m.actual_length - cmd_sz;
714 cmd_sz = 1;
715 to += 2;
716 }
717 write_disable(flash);
718 ret = wait_till_ready(flash);
719 if (ret)
720 goto time_out;
721
722 /* Write out trailing byte if it exists. */
723 if (actual != len) {
724 write_enable(flash);
725 flash->command[0] = OPCODE_BP;
726 m25p_addr2cmd(flash, to, flash->command);
727 t[0].len = m25p_cmdsz(flash);
728 t[1].len = 1;
729 t[1].tx_buf = buf + actual;
730
731 spi_sync(flash->spi, &m);
732 ret = wait_till_ready(flash);
733 if (ret)
734 goto time_out;
735 *retlen += m.actual_length - m25p_cmdsz(flash);
736 write_disable(flash);
737 }
738
739time_out:
740 mutex_unlock(&flash->lock);
741 return ret;
742}
743
744static int m25p80_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
745{
746 struct m25p *flash = mtd_to_m25p(mtd);
747 uint32_t offset = ofs;
748 uint8_t status_old, status_new;
749 int res = 0;
750
751 mutex_lock(&flash->lock);
752 /* Wait until finished previous command */
753 if (wait_till_ready(flash)) {
754 res = 1;
755 goto err;
756 }
757
758 status_old = read_sr(flash);
759
760 if (offset < flash->mtd.size-(flash->mtd.size/2))
761 status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
762 else if (offset < flash->mtd.size-(flash->mtd.size/4))
763 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
764 else if (offset < flash->mtd.size-(flash->mtd.size/8))
765 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
766 else if (offset < flash->mtd.size-(flash->mtd.size/16))
767 status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2;
768 else if (offset < flash->mtd.size-(flash->mtd.size/32))
769 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
770 else if (offset < flash->mtd.size-(flash->mtd.size/64))
771 status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1;
772 else
773 status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0;
774
775 /* Only modify protection if it will not unlock other areas */
776 if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) >
777 (status_old&(SR_BP2|SR_BP1|SR_BP0))) {
778 write_enable(flash);
779 if (write_sr(flash, status_new) < 0) {
780 res = 1;
781 goto err;
782 }
783 }
784
785err: mutex_unlock(&flash->lock);
786 return res;
787}
788
789static int m25p80_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
790{
791 struct m25p *flash = mtd_to_m25p(mtd);
792 uint32_t offset = ofs;
793 uint8_t status_old, status_new;
794 int res = 0;
795
796 mutex_lock(&flash->lock);
797 /* Wait until finished previous command */
798 if (wait_till_ready(flash)) {
799 res = 1;
800 goto err;
801 }
802
803 status_old = read_sr(flash);
804
805 if (offset+len > flash->mtd.size-(flash->mtd.size/64))
806 status_new = status_old & ~(SR_BP2|SR_BP1|SR_BP0);
807 else if (offset+len > flash->mtd.size-(flash->mtd.size/32))
808 status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0;
809 else if (offset+len > flash->mtd.size-(flash->mtd.size/16))
810 status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1;
811 else if (offset+len > flash->mtd.size-(flash->mtd.size/8))
812 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
813 else if (offset+len > flash->mtd.size-(flash->mtd.size/4))
814 status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2;
815 else if (offset+len > flash->mtd.size-(flash->mtd.size/2))
816 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
817 else
818 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
819
820 /* Only modify protection if it will not lock other areas */
821 if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) <
822 (status_old&(SR_BP2|SR_BP1|SR_BP0))) {
823 write_enable(flash);
824 if (write_sr(flash, status_new) < 0) {
825 res = 1;
826 goto err;
827 }
828 }
829
830err: mutex_unlock(&flash->lock);
831 return res;
832}
833
834/****************************************************************************/
835
836/*
837 * SPI device driver setup and teardown
838 */
839
840struct flash_info {
841 /* JEDEC id zero means "no ID" (most older chips); otherwise it has
842 * a high byte of zero plus three data bytes: the manufacturer id,
843 * then a two byte device id.
844 */
845 u32 jedec_id;
846 u16 ext_id;
847
848 /* The size listed here is what works with OPCODE_SE, which isn't
849 * necessarily called a "sector" by the vendor.
850 */
851 unsigned sector_size;
852 u16 n_sectors;
853
854 u16 page_size;
855 u16 addr_width;
856
857 u16 flags;
858#define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */
859#define M25P_NO_ERASE 0x02 /* No erase command needed */
860#define SST_WRITE 0x04 /* use SST byte programming */
861#define M25P_NO_FR 0x08 /* Can't do fastread */
862#define SECT_4K_PMC 0x10 /* OPCODE_BE_4K_PMC works uniformly */
863#define M25P80_DUAL_READ 0x20 /* Flash supports Dual Read */
864#define M25P80_QUAD_READ 0x40 /* Flash supports Quad Read */
865};
866
867#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
868 ((kernel_ulong_t)&(struct flash_info) { \
869 .jedec_id = (_jedec_id), \
870 .ext_id = (_ext_id), \
871 .sector_size = (_sector_size), \
872 .n_sectors = (_n_sectors), \
873 .page_size = 256, \
874 .flags = (_flags), \
875 })
876
877#define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
878 ((kernel_ulong_t)&(struct flash_info) { \
879 .sector_size = (_sector_size), \
880 .n_sectors = (_n_sectors), \
881 .page_size = (_page_size), \
882 .addr_width = (_addr_width), \
883 .flags = (_flags), \
884 })
885
886/* NOTE: double check command sets and memory organization when you add
887 * more flash chips. This current list focusses on newer chips, which
888 * have been converging on command sets which including JEDEC ID.
889 */
890static const struct spi_device_id m25p_ids[] = {
891 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
892 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
893 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
894
895 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
896 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
897 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
898
899 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
900 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
901 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
902 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
903
904 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
905
906 /* EON -- en25xxx */
907 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
908 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
909 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
910 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
911 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
912 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
913
914 /* ESMT */
915 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
916
917 /* Everspin */
918 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, M25P_NO_ERASE | M25P_NO_FR) },
919 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, M25P_NO_ERASE | M25P_NO_FR) },
920
921 /* GigaDevice */
922 { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
923 { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
924
925 /* Intel/Numonyx -- xxxs33b */
926 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
927 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
928 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
929
930 /* Macronix */
931 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
932 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
933 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
934 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
935 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
936 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
937 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
938 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
939 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
940 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
941 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
942 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, M25P80_QUAD_READ) },
943 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, M25P80_QUAD_READ) },
944
945 /* Micron */
946 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
947 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
948 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
949 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
950 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
951
952 /* PMC */
953 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
954 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
955 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
956
957 /* Spansion -- single (large) sector size only, at least
958 * for the chips listed here (without boot sectors).
959 */
960 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, 0) },
961 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) },
962 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
963 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, M25P80_DUAL_READ | M25P80_QUAD_READ) },
964 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, M25P80_DUAL_READ | M25P80_QUAD_READ) },
965 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
966 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
967 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
968 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
969 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
970 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
971 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
972 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
973 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
974 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
975 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
976 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
977 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
978
979 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
980 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
981 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
982 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
983 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
984 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
985 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
986 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
987 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
988 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
989
990 /* ST Microelectronics -- newer production may have feature updates */
991 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
992 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
993 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
994 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
995 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
996 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
997 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
998 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
999 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
1000 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) },
1001
1002 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
1003 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
1004 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
1005 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
1006 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
1007 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
1008 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
1009 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
1010 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
1011
1012 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
1013 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
1014 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
1015
1016 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
1017 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
1018 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
1019
1020 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
1021 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
1022 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
1023 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
1024 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
1025
1026 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
1027 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
1028 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
1029 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
1030 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
1031 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
1032 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
1033 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
1034 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
1035 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
1036 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
1037 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
1038 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
1039 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
1040 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
1041 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
1042
1043 /* Catalyst / On Semiconductor -- non-JEDEC */
1044 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, M25P_NO_ERASE | M25P_NO_FR) },
1045 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, M25P_NO_ERASE | M25P_NO_FR) },
1046 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, M25P_NO_ERASE | M25P_NO_FR) },
1047 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, M25P_NO_ERASE | M25P_NO_FR) },
1048 { "cat25128", CAT25_INFO(2048, 8, 64, 2, M25P_NO_ERASE | M25P_NO_FR) },
1049 { },
1050};
1051MODULE_DEVICE_TABLE(spi, m25p_ids);
1052
1053static const struct spi_device_id *jedec_probe(struct spi_device *spi)
1054{
1055 int tmp;
1056 u8 code = OPCODE_RDID;
1057 u8 id[5];
1058 u32 jedec;
1059 u16 ext_jedec;
1060 struct flash_info *info;
1061
1062 /* JEDEC also defines an optional "extended device information"
1063 * string for after vendor-specific data, after the three bytes
1064 * we use here. Supporting some chips might require using it.
1065 */
1066 tmp = spi_write_then_read(spi, &code, 1, id, 5);
1067 if (tmp < 0) {
1068 pr_debug("%s: error %d reading JEDEC ID\n",
1069 dev_name(&spi->dev), tmp);
1070 return ERR_PTR(tmp);
1071 }
1072 jedec = id[0];
1073 jedec = jedec << 8;
1074 jedec |= id[1];
1075 jedec = jedec << 8;
1076 jedec |= id[2];
1077
1078 ext_jedec = id[3] << 8 | id[4];
1079
1080 for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) {
1081 info = (void *)m25p_ids[tmp].driver_data;
1082 if (info->jedec_id == jedec) {
1083 if (info->ext_id == 0 || info->ext_id == ext_jedec)
1084 return &m25p_ids[tmp];
1085 }
1086 }
1087 dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec);
1088 return ERR_PTR(-ENODEV);
1089}
1090
1091
1092/*
1093 * board specific setup should have ensured the SPI clock used here
1094 * matches what the READ command supports, at least until this driver
1095 * understands FAST_READ (for clocks over 25 MHz).
1096 */
1097static int m25p_probe(struct spi_device *spi)
1098{
1099 const struct spi_device_id *id = spi_get_device_id(spi);
1100 struct flash_platform_data *data;
1101 struct m25p *flash;
1102 struct flash_info *info;
1103 unsigned i;
1104 struct mtd_part_parser_data ppdata;
1105 struct device_node *np = spi->dev.of_node;
1106 int ret;
1107
1108 /* Platform data helps sort out which chip type we have, as
1109 * well as how this board partitions it. If we don't have
1110 * a chip ID, try the JEDEC id commands; they'll work for most
1111 * newer chips, even if we don't recognize the particular chip.
1112 */
1113 data = dev_get_platdata(&spi->dev);
1114 if (data && data->type) {
1115 const struct spi_device_id *plat_id;
1116
1117 for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) {
1118 plat_id = &m25p_ids[i];
1119 if (strcmp(data->type, plat_id->name))
1120 continue;
1121 break;
1122 }
1123
1124 if (i < ARRAY_SIZE(m25p_ids) - 1)
1125 id = plat_id;
1126 else
1127 dev_warn(&spi->dev, "unrecognized id %s\n", data->type);
1128 }
1129
1130 info = (void *)id->driver_data;
1131
1132 if (info->jedec_id) {
1133 const struct spi_device_id *jid;
1134
1135 jid = jedec_probe(spi);
1136 if (IS_ERR(jid)) {
1137 return PTR_ERR(jid);
1138 } else if (jid != id) {
1139 /*
1140 * JEDEC knows better, so overwrite platform ID. We
1141 * can't trust partitions any longer, but we'll let
1142 * mtd apply them anyway, since some partitions may be
1143 * marked read-only, and we don't want to lose that
1144 * information, even if it's not 100% accurate.
1145 */
1146 dev_warn(&spi->dev, "found %s, expected %s\n",
1147 jid->name, id->name);
1148 id = jid;
1149 info = (void *)jid->driver_data;
1150 }
1151 }
1152
1153 flash = devm_kzalloc(&spi->dev, sizeof(*flash), GFP_KERNEL);
1154 if (!flash)
1155 return -ENOMEM;
1156
1157 flash->command = devm_kzalloc(&spi->dev, MAX_CMD_SIZE, GFP_KERNEL);
1158 if (!flash->command)
1159 return -ENOMEM;
1160
1161 flash->spi = spi;
1162 mutex_init(&flash->lock);
1163 spi_set_drvdata(spi, flash);
1164
1165 /*
1166 * Atmel, SST and Intel/Numonyx serial flash tend to power
1167 * up with the software protection bits set
1168 */
1169
1170 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
1171 JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
1172 JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
1173 write_enable(flash);
1174 write_sr(flash, 0);
1175 }
1176
1177 if (data && data->name)
1178 flash->mtd.name = data->name;
1179 else
1180 flash->mtd.name = dev_name(&spi->dev);
1181
1182 flash->mtd.type = MTD_NORFLASH;
1183 flash->mtd.writesize = 1;
1184 flash->mtd.flags = MTD_CAP_NORFLASH;
1185 flash->mtd.size = info->sector_size * info->n_sectors;
1186 flash->mtd._erase = m25p80_erase;
1187 flash->mtd._read = m25p80_read;
1188
1189 /* flash protection support for STmicro chips */
1190 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) {
1191 flash->mtd._lock = m25p80_lock;
1192 flash->mtd._unlock = m25p80_unlock;
1193 }
1194
1195 /* sst flash chips use AAI word program */
1196 if (info->flags & SST_WRITE)
1197 flash->mtd._write = sst_write;
1198 else
1199 flash->mtd._write = m25p80_write;
1200
1201 /* prefer "small sector" erase if possible */
1202 if (info->flags & SECT_4K) {
1203 flash->erase_opcode = OPCODE_BE_4K;
1204 flash->mtd.erasesize = 4096;
1205 } else if (info->flags & SECT_4K_PMC) {
1206 flash->erase_opcode = OPCODE_BE_4K_PMC;
1207 flash->mtd.erasesize = 4096;
1208 } else {
1209 flash->erase_opcode = OPCODE_SE;
1210 flash->mtd.erasesize = info->sector_size;
1211 }
1212
1213 if (info->flags & M25P_NO_ERASE)
1214 flash->mtd.flags |= MTD_NO_ERASE;
1215
1216 ppdata.of_node = spi->dev.of_node;
1217 flash->mtd.dev.parent = &spi->dev;
1218 flash->page_size = info->page_size;
1219 flash->mtd.writebufsize = flash->page_size;
1220
1221 if (np) {
1222 /* If we were instantiated by DT, use it */
1223 if (of_property_read_bool(np, "m25p,fast-read"))
1224 flash->flash_read = M25P80_FAST;
1225 else
1226 flash->flash_read = M25P80_NORMAL;
1227 } else {
1228 /* If we weren't instantiated by DT, default to fast-read */
1229 flash->flash_read = M25P80_FAST;
1230 }
1231
1232 /* Some devices cannot do fast-read, no matter what DT tells us */
1233 if (info->flags & M25P_NO_FR)
1234 flash->flash_read = M25P80_NORMAL;
1235
1236 /* Quad/Dual-read mode takes precedence over fast/normal */
1237 if (spi->mode & SPI_RX_QUAD && info->flags & M25P80_QUAD_READ) {
1238 ret = set_quad_mode(flash, info->jedec_id);
1239 if (ret) {
1240 dev_err(&flash->spi->dev, "quad mode not supported\n");
1241 return ret;
1242 }
1243 flash->flash_read = M25P80_QUAD;
1244 } else if (spi->mode & SPI_RX_DUAL && info->flags & M25P80_DUAL_READ) {
1245 flash->flash_read = M25P80_DUAL;
1246 }
1247
1248 /* Default commands */
1249 switch (flash->flash_read) {
1250 case M25P80_QUAD:
1251 flash->read_opcode = OPCODE_QUAD_READ;
1252 break;
1253 case M25P80_DUAL:
1254 flash->read_opcode = OPCODE_DUAL_READ;
1255 break;
1256 case M25P80_FAST:
1257 flash->read_opcode = OPCODE_FAST_READ;
1258 break;
1259 case M25P80_NORMAL:
1260 flash->read_opcode = OPCODE_NORM_READ;
1261 break;
1262 default:
1263 dev_err(&flash->spi->dev, "No Read opcode defined\n");
1264 return -EINVAL;
1265 }
1266
1267 flash->program_opcode = OPCODE_PP;
1268
1269 if (info->addr_width)
1270 flash->addr_width = info->addr_width;
1271 else if (flash->mtd.size > 0x1000000) {
1272 /* enable 4-byte addressing if the device exceeds 16MiB */
1273 flash->addr_width = 4;
1274 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) {
1275 /* Dedicated 4-byte command set */
1276 switch (flash->flash_read) {
1277 case M25P80_QUAD:
1278 flash->read_opcode = OPCODE_QUAD_READ_4B;
1279 break;
1280 case M25P80_DUAL:
1281 flash->read_opcode = OPCODE_DUAL_READ_4B;
1282 break;
1283 case M25P80_FAST:
1284 flash->read_opcode = OPCODE_FAST_READ_4B;
1285 break;
1286 case M25P80_NORMAL:
1287 flash->read_opcode = OPCODE_NORM_READ_4B;
1288 break;
1289 }
1290 flash->program_opcode = OPCODE_PP_4B;
1291 /* No small sector erase for 4-byte command set */
1292 flash->erase_opcode = OPCODE_SE_4B;
1293 flash->mtd.erasesize = info->sector_size;
1294 } else
1295 set_4byte(flash, info->jedec_id, 1);
1296 } else {
1297 flash->addr_width = 3;
1298 }
1299
1300 dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name,
1301 (long long)flash->mtd.size >> 10);
1302
1303 pr_debug("mtd .name = %s, .size = 0x%llx (%lldMiB) "
1304 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1305 flash->mtd.name,
1306 (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20),
1307 flash->mtd.erasesize, flash->mtd.erasesize / 1024,
1308 flash->mtd.numeraseregions);
1309
1310 if (flash->mtd.numeraseregions)
1311 for (i = 0; i < flash->mtd.numeraseregions; i++)
1312 pr_debug("mtd.eraseregions[%d] = { .offset = 0x%llx, "
1313 ".erasesize = 0x%.8x (%uKiB), "
1314 ".numblocks = %d }\n",
1315 i, (long long)flash->mtd.eraseregions[i].offset,
1316 flash->mtd.eraseregions[i].erasesize,
1317 flash->mtd.eraseregions[i].erasesize / 1024,
1318 flash->mtd.eraseregions[i].numblocks);
1319
1320
1321 /* partitions should match sector boundaries; and it may be good to
1322 * use readonly partitions for writeprotected sectors (BP2..BP0).
1323 */
1324 return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
1325 data ? data->parts : NULL,
1326 data ? data->nr_parts : 0);
1327}
1328
1329
1330static int m25p_remove(struct spi_device *spi)
1331{
1332 struct m25p *flash = spi_get_drvdata(spi);
1333
1334 /* Clean up MTD stuff. */
1335 return mtd_device_unregister(&flash->mtd);
1336}
1337
1338
1339static struct spi_driver m25p80_driver = {
1340 .driver = {
1341 .name = "m25p80",
1342 .owner = THIS_MODULE,
1343 },
1344 .id_table = m25p_ids,
1345 .probe = m25p_probe,
1346 .remove = m25p_remove,
1347
1348 /* REVISIT: many of these chips have deep power-down modes, which
1349 * should clearly be entered on suspend() to minimize power use.
1350 * And also when they're otherwise idle...
1351 */
1352};
1353
1354module_spi_driver(m25p80_driver);
1355
1356MODULE_LICENSE("GPL");
1357MODULE_AUTHOR("Mike Lavender");
1358MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");