1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * xHCI host controller driver
   4 *
   5 * Copyright (C) 2008 Intel Corp.
   6 *
   7 * Author: Sarah Sharp
   8 * Some code borrowed from the Linux EHCI driver.
 
 
 
 
 
 
 
 
 
 
 
 
 
   9 */
  10
  11#include <linux/pci.h>
  12#include <linux/iommu.h>
  13#include <linux/iopoll.h>
  14#include <linux/irq.h>
  15#include <linux/log2.h>
  16#include <linux/module.h>
  17#include <linux/moduleparam.h>
  18#include <linux/slab.h>
  19#include <linux/dmi.h>
  20#include <linux/dma-mapping.h>
  21
  22#include "xhci.h"
  23#include "xhci-trace.h"
  24#include "xhci-debugfs.h"
  25#include "xhci-dbgcap.h"
  26
  27#define DRIVER_AUTHOR "Sarah Sharp"
  28#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
  29
  30#define	PORT_WAKE_BITS	(PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  31
  32/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
  33static int link_quirk;
  34module_param(link_quirk, int, S_IRUGO | S_IWUSR);
  35MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
  36
  37static unsigned long long quirks;
  38module_param(quirks, ullong, S_IRUGO);
  39MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
  40
  41static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
  42{
  43	struct xhci_segment *seg = ring->first_seg;
  44
  45	if (!td || !td->start_seg)
  46		return false;
  47	do {
  48		if (seg == td->start_seg)
  49			return true;
  50		seg = seg->next;
  51	} while (seg && seg != ring->first_seg);
  52
  53	return false;
  54}
  55
  56/*
  57 * xhci_handshake - spin reading hc until handshake completes or fails
  58 * @ptr: address of hc register to be read
  59 * @mask: bits to look at in result of read
  60 * @done: value of those bits when handshake succeeds
  61 * @usec: timeout in microseconds
  62 *
  63 * Returns negative errno, or zero on success
  64 *
  65 * Success happens when the "mask" bits have the specified value (hardware
  66 * handshake done).  There are two failure modes:  "usec" have passed (major
  67 * hardware flakeout), or the register reads as all-ones (hardware removed).
  68 */
  69int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us)
 
  70{
  71	u32	result;
  72	int	ret;
  73
  74	ret = readl_poll_timeout_atomic(ptr, result,
  75					(result & mask) == done ||
  76					result == U32_MAX,
  77					1, timeout_us);
  78	if (result == U32_MAX)		/* card removed */
  79		return -ENODEV;
  80
  81	return ret;
  82}
  83
  84/*
  85 * xhci_handshake_check_state - same as xhci_handshake but takes an additional
  86 * exit_state parameter, and bails out with an error immediately when xhc_state
  87 * has exit_state flag set.
  88 */
  89int xhci_handshake_check_state(struct xhci_hcd *xhci, void __iomem *ptr,
  90		u32 mask, u32 done, int usec, unsigned int exit_state)
  91{
  92	u32	result;
  93	int	ret;
  94
  95	ret = readl_poll_timeout_atomic(ptr, result,
  96				(result & mask) == done ||
  97				result == U32_MAX ||
  98				xhci->xhc_state & exit_state,
  99				1, usec);
 100
 101	if (result == U32_MAX || xhci->xhc_state & exit_state)
 102		return -ENODEV;
 103
 104	return ret;
 105}
 106
 107/*
 108 * Disable interrupts and begin the xHCI halting process.
 109 */
 110void xhci_quiesce(struct xhci_hcd *xhci)
 111{
 112	u32 halted;
 113	u32 cmd;
 114	u32 mask;
 115
 116	mask = ~(XHCI_IRQS);
 117	halted = readl(&xhci->op_regs->status) & STS_HALT;
 118	if (!halted)
 119		mask &= ~CMD_RUN;
 120
 121	cmd = readl(&xhci->op_regs->command);
 122	cmd &= mask;
 123	writel(cmd, &xhci->op_regs->command);
 124}
 125
 126/*
 127 * Force HC into halt state.
 128 *
 129 * Disable any IRQs and clear the run/stop bit.
 130 * HC will complete any current and actively pipelined transactions, and
 131 * should halt within 16 ms of the run/stop bit being cleared.
 132 * Read HC Halted bit in the status register to see when the HC is finished.
 133 */
 134int xhci_halt(struct xhci_hcd *xhci)
 135{
 136	int ret;
 137
 138	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
 139	xhci_quiesce(xhci);
 140
 141	ret = xhci_handshake(&xhci->op_regs->status,
 142			STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
 143	if (ret) {
 144		xhci_warn(xhci, "Host halt failed, %d\n", ret);
 145		return ret;
 146	}
 147
 148	xhci->xhc_state |= XHCI_STATE_HALTED;
 149	xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
 150
 151	return ret;
 152}
 153
 154/*
 155 * Set the run bit and wait for the host to be running.
 156 */
 157int xhci_start(struct xhci_hcd *xhci)
 158{
 159	u32 temp;
 160	int ret;
 161
 162	temp = readl(&xhci->op_regs->command);
 163	temp |= (CMD_RUN);
 164	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
 165			temp);
 166	writel(temp, &xhci->op_regs->command);
 167
 168	/*
 169	 * Wait for the HCHalted Status bit to be 0 to indicate the host is
 170	 * running.
 171	 */
 172	ret = xhci_handshake(&xhci->op_regs->status,
 173			STS_HALT, 0, XHCI_MAX_HALT_USEC);
 174	if (ret == -ETIMEDOUT)
 175		xhci_err(xhci, "Host took too long to start, "
 176				"waited %u microseconds.\n",
 177				XHCI_MAX_HALT_USEC);
 178	if (!ret) {
 179		/* clear state flags. Including dying, halted or removing */
 180		xhci->xhc_state = 0;
 181		xhci->run_graceperiod = jiffies + msecs_to_jiffies(500);
 182	}
 183
 184	return ret;
 185}
 186
 187/*
 188 * Reset a halted HC.
 189 *
 190 * This resets pipelines, timers, counters, state machines, etc.
 191 * Transactions will be terminated immediately, and operational registers
 192 * will be set to their defaults.
 193 */
 194int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us)
 195{
 196	u32 command;
 197	u32 state;
 198	int ret;
 199
 200	state = readl(&xhci->op_regs->status);
 201
 202	if (state == ~(u32)0) {
 203		xhci_warn(xhci, "Host not accessible, reset failed.\n");
 204		return -ENODEV;
 205	}
 206
 207	if ((state & STS_HALT) == 0) {
 208		xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
 209		return 0;
 210	}
 211
 212	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
 213	command = readl(&xhci->op_regs->command);
 214	command |= CMD_RESET;
 215	writel(command, &xhci->op_regs->command);
 216
 217	/* Existing Intel xHCI controllers require a delay of 1 mS,
 218	 * after setting the CMD_RESET bit, and before accessing any
 219	 * HC registers. This allows the HC to complete the
 220	 * reset operation and be ready for HC register access.
 221	 * Without this delay, the subsequent HC register access,
 222	 * may result in a system hang very rarely.
 223	 */
 224	if (xhci->quirks & XHCI_INTEL_HOST)
 225		udelay(1000);
 226
 227	ret = xhci_handshake_check_state(xhci, &xhci->op_regs->command,
 228				CMD_RESET, 0, timeout_us, XHCI_STATE_REMOVING);
 229	if (ret)
 230		return ret;
 231
 232	if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
 233		usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
 234
 235	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
 236			 "Wait for controller to be ready for doorbell rings");
 237	/*
 238	 * xHCI cannot write to any doorbells or operational registers other
 239	 * than status until the "Controller Not Ready" flag is cleared.
 240	 */
 241	ret = xhci_handshake(&xhci->op_regs->status, STS_CNR, 0, timeout_us);
 
 242
 243	xhci->usb2_rhub.bus_state.port_c_suspend = 0;
 244	xhci->usb2_rhub.bus_state.suspended_ports = 0;
 245	xhci->usb2_rhub.bus_state.resuming_ports = 0;
 246	xhci->usb3_rhub.bus_state.port_c_suspend = 0;
 247	xhci->usb3_rhub.bus_state.suspended_ports = 0;
 248	xhci->usb3_rhub.bus_state.resuming_ports = 0;
 249
 250	return ret;
 251}
 252
 253static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
 
 254{
 255	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
 256	struct iommu_domain *domain;
 257	int err, i;
 258	u64 val;
 259	u32 intrs;
 260
 261	/*
 262	 * Some Renesas controllers get into a weird state if they are
 263	 * reset while programmed with 64bit addresses (they will preserve
 264	 * the top half of the address in internal, non visible
 265	 * registers). You end up with half the address coming from the
 266	 * kernel, and the other half coming from the firmware. Also,
 267	 * changing the programming leads to extra accesses even if the
 268	 * controller is supposed to be halted. The controller ends up with
 269	 * a fatal fault, and is then ripe for being properly reset.
 270	 *
 271	 * Special care is taken to only apply this if the device is behind
 272	 * an iommu. Doing anything when there is no iommu is definitely
 273	 * unsafe...
 274	 */
 275	domain = iommu_get_domain_for_dev(dev);
 276	if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !domain ||
 277	    domain->type == IOMMU_DOMAIN_IDENTITY)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 278		return;
 279
 280	xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
 
 
 
 
 281
 282	/* Clear HSEIE so that faults do not get signaled */
 283	val = readl(&xhci->op_regs->command);
 284	val &= ~CMD_HSEIE;
 285	writel(val, &xhci->op_regs->command);
 286
 287	/* Clear HSE (aka FATAL) */
 288	val = readl(&xhci->op_regs->status);
 289	val |= STS_FATAL;
 290	writel(val, &xhci->op_regs->status);
 291
 292	/* Now zero the registers, and brace for impact */
 293	val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
 294	if (upper_32_bits(val))
 295		xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
 296	val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 297	if (upper_32_bits(val))
 298		xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
 299
 300	intrs = min_t(u32, HCS_MAX_INTRS(xhci->hcs_params1),
 301		      ARRAY_SIZE(xhci->run_regs->ir_set));
 302
 303	for (i = 0; i < intrs; i++) {
 304		struct xhci_intr_reg __iomem *ir;
 305
 306		ir = &xhci->run_regs->ir_set[i];
 307		val = xhci_read_64(xhci, &ir->erst_base);
 308		if (upper_32_bits(val))
 309			xhci_write_64(xhci, 0, &ir->erst_base);
 310		val= xhci_read_64(xhci, &ir->erst_dequeue);
 311		if (upper_32_bits(val))
 312			xhci_write_64(xhci, 0, &ir->erst_dequeue);
 313	}
 314
 315	/* Wait for the fault to appear. It will be cleared on reset */
 316	err = xhci_handshake(&xhci->op_regs->status,
 317			     STS_FATAL, STS_FATAL,
 318			     XHCI_MAX_HALT_USEC);
 319	if (!err)
 320		xhci_info(xhci, "Fault detected\n");
 321}
 322
 323static int xhci_enable_interrupter(struct xhci_interrupter *ir)
 
 
 
 324{
 325	u32 iman;
 
 
 326
 327	if (!ir || !ir->ir_set)
 328		return -EINVAL;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 329
 330	iman = readl(&ir->ir_set->irq_pending);
 331	writel(ER_IRQ_ENABLE(iman), &ir->ir_set->irq_pending);
 
 
 332
 333	return 0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 334}
 335
 336static int xhci_disable_interrupter(struct xhci_interrupter *ir)
 337{
 338	u32 iman;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 339
 340	if (!ir || !ir->ir_set)
 
 
 
 
 
 
 
 
 
 
 341		return -EINVAL;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 342
 343	iman = readl(&ir->ir_set->irq_pending);
 344	writel(ER_IRQ_DISABLE(iman), &ir->ir_set->irq_pending);
 345
 
 
 346	return 0;
 347}
 348
 349static void compliance_mode_recovery(struct timer_list *t)
 
 
 
 
 
 
 
 
 
 
 350{
 351	struct xhci_hcd *xhci;
 352	struct usb_hcd *hcd;
 353	struct xhci_hub *rhub;
 354	u32 temp;
 355	int i;
 356
 357	xhci = from_timer(xhci, t, comp_mode_recovery_timer);
 358	rhub = &xhci->usb3_rhub;
 359	hcd = rhub->hcd;
 360
 361	if (!hcd)
 362		return;
 363
 364	for (i = 0; i < rhub->num_ports; i++) {
 365		temp = readl(rhub->ports[i]->addr);
 366		if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
 367			/*
 368			 * Compliance Mode Detected. Letting USB Core
 369			 * handle the Warm Reset
 370			 */
 371			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 372					"Compliance mode detected->port %d",
 373					i + 1);
 374			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 375					"Attempting compliance mode recovery");
 
 376
 377			if (hcd->state == HC_STATE_SUSPENDED)
 378				usb_hcd_resume_root_hub(hcd);
 379
 380			usb_hcd_poll_rh_status(hcd);
 381		}
 382	}
 383
 384	if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
 385		mod_timer(&xhci->comp_mode_recovery_timer,
 386			jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
 387}
 388
 389/*
 390 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
 391 * that causes ports behind that hardware to enter compliance mode sometimes.
 392 * The quirk creates a timer that polls every 2 seconds the link state of
 393 * each host controller's port and recovers it by issuing a Warm reset
 394 * if Compliance mode is detected, otherwise the port will become "dead" (no
 395 * device connections or disconnections will be detected anymore). Becasue no
 396 * status event is generated when entering compliance mode (per xhci spec),
 397 * this quirk is needed on systems that have the failing hardware installed.
 398 */
 399static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
 400{
 401	xhci->port_status_u0 = 0;
 402	timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
 403		    0);
 
 
 404	xhci->comp_mode_recovery_timer.expires = jiffies +
 405			msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
 406
 
 
 407	add_timer(&xhci->comp_mode_recovery_timer);
 408	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 409			"Compliance mode recovery timer initialized");
 410}
 411
 412/*
 413 * This function identifies the systems that have installed the SN65LVPE502CP
 414 * USB3.0 re-driver and that need the Compliance Mode Quirk.
 415 * Systems:
 416 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
 417 */
 418static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
 419{
 420	const char *dmi_product_name, *dmi_sys_vendor;
 421
 422	dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
 423	dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
 424	if (!dmi_product_name || !dmi_sys_vendor)
 425		return false;
 426
 427	if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
 428		return false;
 429
 430	if (strstr(dmi_product_name, "Z420") ||
 431			strstr(dmi_product_name, "Z620") ||
 432			strstr(dmi_product_name, "Z820") ||
 433			strstr(dmi_product_name, "Z1 Workstation"))
 434		return true;
 435
 436	return false;
 437}
 438
 439static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
 440{
 441	return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
 442}
 443
 444
 445/*
 446 * Initialize memory for HCD and xHC (one-time init).
 447 *
 448 * Program the PAGESIZE register, initialize the device context array, create
 449 * device contexts (?), set up a command ring segment (or two?), create event
 450 * ring (one for now).
 451 */
 452static int xhci_init(struct usb_hcd *hcd)
 453{
 454	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 455	int retval;
 456
 457	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
 458	spin_lock_init(&xhci->lock);
 459	if (xhci->hci_version == 0x95 && link_quirk) {
 460		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 461				"QUIRK: Not clearing Link TRB chain bits.");
 462		xhci->quirks |= XHCI_LINK_TRB_QUIRK;
 463	} else {
 464		xhci_dbg_trace(xhci, trace_xhci_dbg_init,
 465				"xHCI doesn't need link TRB QUIRK");
 466	}
 467	retval = xhci_mem_init(xhci, GFP_KERNEL);
 468	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
 469
 470	/* Initializing Compliance Mode Recovery Data If Needed */
 471	if (xhci_compliance_mode_recovery_timer_quirk_check()) {
 472		xhci->quirks |= XHCI_COMP_MODE_QUIRK;
 473		compliance_mode_recovery_timer_init(xhci);
 474	}
 475
 476	return retval;
 477}
 478
 479/*-------------------------------------------------------------------------*/
 480
 
 481static int xhci_run_finished(struct xhci_hcd *xhci)
 482{
 483	struct xhci_interrupter *ir = xhci->interrupters[0];
 484	unsigned long	flags;
 485	u32		temp;
 486
 487	/*
 488	 * Enable interrupts before starting the host (xhci 4.2 and 5.5.2).
 489	 * Protect the short window before host is running with a lock
 490	 */
 491	spin_lock_irqsave(&xhci->lock, flags);
 492
 493	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable interrupts");
 494	temp = readl(&xhci->op_regs->command);
 495	temp |= (CMD_EIE);
 496	writel(temp, &xhci->op_regs->command);
 497
 498	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable primary interrupter");
 499	xhci_enable_interrupter(ir);
 500
 501	if (xhci_start(xhci)) {
 502		xhci_halt(xhci);
 503		spin_unlock_irqrestore(&xhci->lock, flags);
 504		return -ENODEV;
 505	}
 506
 507	xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
 508
 509	if (xhci->quirks & XHCI_NEC_HOST)
 510		xhci_ring_cmd_db(xhci);
 511
 512	spin_unlock_irqrestore(&xhci->lock, flags);
 513
 514	return 0;
 515}
 516
 517/*
 518 * Start the HC after it was halted.
 519 *
 520 * This function is called by the USB core when the HC driver is added.
 521 * Its opposite is xhci_stop().
 522 *
 523 * xhci_init() must be called once before this function can be called.
 524 * Reset the HC, enable device slot contexts, program DCBAAP, and
 525 * set command ring pointer and event ring pointer.
 526 *
 527 * Setup MSI-X vectors and enable interrupts.
 528 */
 529int xhci_run(struct usb_hcd *hcd)
 530{
 531	u32 temp;
 532	u64 temp_64;
 533	int ret;
 534	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 535	struct xhci_interrupter *ir = xhci->interrupters[0];
 536	/* Start the xHCI host controller running only after the USB 2.0 roothub
 537	 * is setup.
 538	 */
 539
 540	hcd->uses_new_polling = 1;
 541	if (!usb_hcd_is_primary_hcd(hcd))
 542		return xhci_run_finished(xhci);
 543
 544	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
 545
 546	temp_64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
 547	temp_64 &= ERST_PTR_MASK;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 548	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
 549			"ERST deq = 64'h%0lx", (long unsigned int) temp_64);
 550
 551	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
 552			"// Set the interrupt modulation register");
 553	temp = readl(&ir->ir_set->irq_control);
 554	temp &= ~ER_IRQ_INTERVAL_MASK;
 555	temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
 556	writel(temp, &ir->ir_set->irq_control);
 557
 558	if (xhci->quirks & XHCI_NEC_HOST) {
 559		struct xhci_command *command;
 560
 561		command = xhci_alloc_command(xhci, false, GFP_KERNEL);
 562		if (!command)
 563			return -ENOMEM;
 
 
 
 564
 565		ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
 566				TRB_TYPE(TRB_NEC_GET_FW));
 567		if (ret)
 568			xhci_free_command(xhci, command);
 569	}
 570	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
 571			"Finished %s for main hcd", __func__);
 
 
 
 572
 573	xhci_create_dbc_dev(xhci);
 
 
 574
 575	xhci_debugfs_init(xhci);
 
 
 
 576
 577	if (xhci_has_one_roothub(xhci))
 578		return xhci_run_finished(xhci);
 
 579
 580	set_bit(HCD_FLAG_DEFER_RH_REGISTER, &hcd->flags);
 
 581
 582	return 0;
 
 
 
 
 
 583}
 584EXPORT_SYMBOL_GPL(xhci_run);
 585
 586/*
 587 * Stop xHCI driver.
 588 *
 589 * This function is called by the USB core when the HC driver is removed.
 590 * Its opposite is xhci_run().
 591 *
 592 * Disable device contexts, disable IRQs, and quiesce the HC.
 593 * Reset the HC, finish any completed transactions, and cleanup memory.
 594 */
 595void xhci_stop(struct usb_hcd *hcd)
 596{
 597	u32 temp;
 598	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 599	struct xhci_interrupter *ir = xhci->interrupters[0];
 600
 601	mutex_lock(&xhci->mutex);
 602
 603	/* Only halt host and free memory after both hcds are removed */
 604	if (!usb_hcd_is_primary_hcd(hcd)) {
 605		mutex_unlock(&xhci->mutex);
 606		return;
 607	}
 608
 609	xhci_remove_dbc_dev(xhci);
 610
 611	spin_lock_irq(&xhci->lock);
 612	xhci->xhc_state |= XHCI_STATE_HALTED;
 613	xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
 
 614	xhci_halt(xhci);
 615	xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
 616	spin_unlock_irq(&xhci->lock);
 617
 
 
 618	/* Deleting Compliance Mode Recovery Timer */
 619	if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 620			(!(xhci_all_ports_seen_u0(xhci)))) {
 621		del_timer_sync(&xhci->comp_mode_recovery_timer);
 622		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 623				"%s: compliance mode recovery timer deleted",
 624				__func__);
 625	}
 626
 627	if (xhci->quirks & XHCI_AMD_PLL_FIX)
 628		usb_amd_dev_put();
 629
 630	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
 631			"// Disabling event ring interrupts");
 632	temp = readl(&xhci->op_regs->status);
 633	writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
 634	xhci_disable_interrupter(ir);
 
 
 635
 636	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
 637	xhci_mem_cleanup(xhci);
 638	xhci_debugfs_exit(xhci);
 639	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
 640			"xhci_stop completed - status = %x",
 641			readl(&xhci->op_regs->status));
 642	mutex_unlock(&xhci->mutex);
 643}
 644EXPORT_SYMBOL_GPL(xhci_stop);
 645
 646/*
 647 * Shutdown HC (not bus-specific)
 648 *
 649 * This is called when the machine is rebooting or halting.  We assume that the
 650 * machine will be powered off, and the HC's internal state will be reset.
 651 * Don't bother to free memory.
 652 *
 653 * This will only ever be called with the main usb_hcd (the USB3 roothub).
 654 */
 655void xhci_shutdown(struct usb_hcd *hcd)
 656{
 657	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 658
 659	if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
 660		usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
 661
 662	/* Don't poll the roothubs after shutdown. */
 663	xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
 664			__func__, hcd->self.busnum);
 665	clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
 666	del_timer_sync(&hcd->rh_timer);
 667
 668	if (xhci->shared_hcd) {
 669		clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
 670		del_timer_sync(&xhci->shared_hcd->rh_timer);
 671	}
 672
 673	spin_lock_irq(&xhci->lock);
 674	xhci_halt(xhci);
 675
 676	/*
 677	 * Workaround for spurious wakeps at shutdown with HSW, and for boot
 678	 * firmware delay in ADL-P PCH if port are left in U3 at shutdown
 679	 */
 680	if (xhci->quirks & XHCI_SPURIOUS_WAKEUP ||
 681	    xhci->quirks & XHCI_RESET_TO_DEFAULT)
 682		xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
 683
 684	spin_unlock_irq(&xhci->lock);
 685
 
 
 686	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
 687			"xhci_shutdown completed - status = %x",
 688			readl(&xhci->op_regs->status));
 
 
 
 
 689}
 690EXPORT_SYMBOL_GPL(xhci_shutdown);
 691
 692#ifdef CONFIG_PM
 693static void xhci_save_registers(struct xhci_hcd *xhci)
 694{
 695	struct xhci_interrupter *ir;
 696	unsigned int i;
 697
 698	xhci->s3.command = readl(&xhci->op_regs->command);
 699	xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
 700	xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
 701	xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
 702
 703	/* save both primary and all secondary interrupters */
 704	/* fixme, shold we lock  to prevent race with remove secondary interrupter? */
 705	for (i = 0; i < xhci->max_interrupters; i++) {
 706		ir = xhci->interrupters[i];
 707		if (!ir)
 708			continue;
 709
 710		ir->s3_erst_size = readl(&ir->ir_set->erst_size);
 711		ir->s3_erst_base = xhci_read_64(xhci, &ir->ir_set->erst_base);
 712		ir->s3_erst_dequeue = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
 713		ir->s3_irq_pending = readl(&ir->ir_set->irq_pending);
 714		ir->s3_irq_control = readl(&ir->ir_set->irq_control);
 715	}
 716}
 717
 718static void xhci_restore_registers(struct xhci_hcd *xhci)
 719{
 720	struct xhci_interrupter *ir;
 721	unsigned int i;
 722
 723	writel(xhci->s3.command, &xhci->op_regs->command);
 724	writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
 725	xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
 726	writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
 727
 728	/* FIXME should we lock to protect against freeing of interrupters */
 729	for (i = 0; i < xhci->max_interrupters; i++) {
 730		ir = xhci->interrupters[i];
 731		if (!ir)
 732			continue;
 733
 734		writel(ir->s3_erst_size, &ir->ir_set->erst_size);
 735		xhci_write_64(xhci, ir->s3_erst_base, &ir->ir_set->erst_base);
 736		xhci_write_64(xhci, ir->s3_erst_dequeue, &ir->ir_set->erst_dequeue);
 737		writel(ir->s3_irq_pending, &ir->ir_set->irq_pending);
 738		writel(ir->s3_irq_control, &ir->ir_set->irq_control);
 739	}
 740}
 741
 742static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
 743{
 744	u64	val_64;
 745
 746	/* step 2: initialize command ring buffer */
 747	val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 748	val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
 749		(xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
 750				      xhci->cmd_ring->dequeue) &
 751		 (u64) ~CMD_RING_RSVD_BITS) |
 752		xhci->cmd_ring->cycle_state;
 753	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
 754			"// Setting command ring address to 0x%llx",
 755			(long unsigned long) val_64);
 756	xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
 757}
 758
 759/*
 760 * The whole command ring must be cleared to zero when we suspend the host.
 761 *
 762 * The host doesn't save the command ring pointer in the suspend well, so we
 763 * need to re-program it on resume.  Unfortunately, the pointer must be 64-byte
 764 * aligned, because of the reserved bits in the command ring dequeue pointer
 765 * register.  Therefore, we can't just set the dequeue pointer back in the
 766 * middle of the ring (TRBs are 16-byte aligned).
 767 */
 768static void xhci_clear_command_ring(struct xhci_hcd *xhci)
 769{
 770	struct xhci_ring *ring;
 771	struct xhci_segment *seg;
 772
 773	ring = xhci->cmd_ring;
 774	seg = ring->deq_seg;
 775	do {
 776		memset(seg->trbs, 0,
 777			sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
 778		seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
 779			cpu_to_le32(~TRB_CYCLE);
 780		seg = seg->next;
 781	} while (seg != ring->deq_seg);
 782
 783	/* Reset the software enqueue and dequeue pointers */
 784	ring->deq_seg = ring->first_seg;
 785	ring->dequeue = ring->first_seg->trbs;
 786	ring->enq_seg = ring->deq_seg;
 787	ring->enqueue = ring->dequeue;
 788
 789	ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
 790	/*
 791	 * Ring is now zeroed, so the HW should look for change of ownership
 792	 * when the cycle bit is set to 1.
 793	 */
 794	ring->cycle_state = 1;
 795
 796	/*
 797	 * Reset the hardware dequeue pointer.
 798	 * Yes, this will need to be re-written after resume, but we're paranoid
 799	 * and want to make sure the hardware doesn't access bogus memory
 800	 * because, say, the BIOS or an SMI started the host without changing
 801	 * the command ring pointers.
 802	 */
 803	xhci_set_cmd_ring_deq(xhci);
 804}
 805
 806/*
 807 * Disable port wake bits if do_wakeup is not set.
 808 *
 809 * Also clear a possible internal port wake state left hanging for ports that
 810 * detected termination but never successfully enumerated (trained to 0U).
 811 * Internal wake causes immediate xHCI wake after suspend. PORT_CSC write done
 812 * at enumeration clears this wake, force one here as well for unconnected ports
 813 */
 814
 815static void xhci_disable_hub_port_wake(struct xhci_hcd *xhci,
 816				       struct xhci_hub *rhub,
 817				       bool do_wakeup)
 818{
 819	unsigned long flags;
 820	u32 t1, t2, portsc;
 821	int i;
 822
 823	spin_lock_irqsave(&xhci->lock, flags);
 824
 825	for (i = 0; i < rhub->num_ports; i++) {
 826		portsc = readl(rhub->ports[i]->addr);
 827		t1 = xhci_port_state_to_neutral(portsc);
 828		t2 = t1;
 829
 830		/* clear wake bits if do_wake is not set */
 831		if (!do_wakeup)
 832			t2 &= ~PORT_WAKE_BITS;
 833
 834		/* Don't touch csc bit if connected or connect change is set */
 835		if (!(portsc & (PORT_CSC | PORT_CONNECT)))
 836			t2 |= PORT_CSC;
 837
 838		if (t1 != t2) {
 839			writel(t2, rhub->ports[i]->addr);
 840			xhci_dbg(xhci, "config port %d-%d wake bits, portsc: 0x%x, write: 0x%x\n",
 841				 rhub->hcd->self.busnum, i + 1, portsc, t2);
 842		}
 843	}
 844	spin_unlock_irqrestore(&xhci->lock, flags);
 845}
 846
 847static bool xhci_pending_portevent(struct xhci_hcd *xhci)
 848{
 849	struct xhci_port	**ports;
 850	int			port_index;
 851	u32			status;
 852	u32			portsc;
 853
 854	status = readl(&xhci->op_regs->status);
 855	if (status & STS_EINT)
 856		return true;
 857	/*
 858	 * Checking STS_EINT is not enough as there is a lag between a change
 859	 * bit being set and the Port Status Change Event that it generated
 860	 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
 861	 */
 862
 863	port_index = xhci->usb2_rhub.num_ports;
 864	ports = xhci->usb2_rhub.ports;
 865	while (port_index--) {
 866		portsc = readl(ports[port_index]->addr);
 867		if (portsc & PORT_CHANGE_MASK ||
 868		    (portsc & PORT_PLS_MASK) == XDEV_RESUME)
 869			return true;
 870	}
 871	port_index = xhci->usb3_rhub.num_ports;
 872	ports = xhci->usb3_rhub.ports;
 873	while (port_index--) {
 874		portsc = readl(ports[port_index]->addr);
 875		if (portsc & (PORT_CHANGE_MASK | PORT_CAS) ||
 876		    (portsc & PORT_PLS_MASK) == XDEV_RESUME)
 877			return true;
 878	}
 879	return false;
 880}
 881
 882/*
 883 * Stop HC (not bus-specific)
 884 *
 885 * This is called when the machine transition into S3/S4 mode.
 886 *
 887 */
 888int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
 889{
 890	int			rc = 0;
 891	unsigned int		delay = XHCI_MAX_HALT_USEC * 2;
 892	struct usb_hcd		*hcd = xhci_to_hcd(xhci);
 893	u32			command;
 894	u32			res;
 895
 896	if (!hcd->state)
 897		return 0;
 898
 899	if (hcd->state != HC_STATE_SUSPENDED ||
 900	    (xhci->shared_hcd && xhci->shared_hcd->state != HC_STATE_SUSPENDED))
 901		return -EINVAL;
 902
 903	/* Clear root port wake on bits if wakeup not allowed. */
 904	xhci_disable_hub_port_wake(xhci, &xhci->usb3_rhub, do_wakeup);
 905	xhci_disable_hub_port_wake(xhci, &xhci->usb2_rhub, do_wakeup);
 906
 907	if (!HCD_HW_ACCESSIBLE(hcd))
 908		return 0;
 909
 910	xhci_dbc_suspend(xhci);
 911
 912	/* Don't poll the roothubs on bus suspend. */
 913	xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
 914		 __func__, hcd->self.busnum);
 915	clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
 916	del_timer_sync(&hcd->rh_timer);
 917	if (xhci->shared_hcd) {
 918		clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
 919		del_timer_sync(&xhci->shared_hcd->rh_timer);
 920	}
 921
 922	if (xhci->quirks & XHCI_SUSPEND_DELAY)
 923		usleep_range(1000, 1500);
 924
 925	spin_lock_irq(&xhci->lock);
 926	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 927	if (xhci->shared_hcd)
 928		clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
 929	/* step 1: stop endpoint */
 930	/* skipped assuming that port suspend has done */
 931
 932	/* step 2: clear Run/Stop bit */
 933	command = readl(&xhci->op_regs->command);
 934	command &= ~CMD_RUN;
 935	writel(command, &xhci->op_regs->command);
 936
 937	/* Some chips from Fresco Logic need an extraordinary delay */
 938	delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
 939
 940	if (xhci_handshake(&xhci->op_regs->status,
 941		      STS_HALT, STS_HALT, delay)) {
 942		xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
 943		spin_unlock_irq(&xhci->lock);
 944		return -ETIMEDOUT;
 945	}
 946	xhci_clear_command_ring(xhci);
 947
 948	/* step 3: save registers */
 949	xhci_save_registers(xhci);
 950
 951	/* step 4: set CSS flag */
 952	command = readl(&xhci->op_regs->command);
 953	command |= CMD_CSS;
 954	writel(command, &xhci->op_regs->command);
 955	xhci->broken_suspend = 0;
 956	if (xhci_handshake(&xhci->op_regs->status,
 957				STS_SAVE, 0, 20 * 1000)) {
 958	/*
 959	 * AMD SNPS xHC 3.0 occasionally does not clear the
 960	 * SSS bit of USBSTS and when driver tries to poll
 961	 * to see if the xHC clears BIT(8) which never happens
 962	 * and driver assumes that controller is not responding
 963	 * and times out. To workaround this, its good to check
 964	 * if SRE and HCE bits are not set (as per xhci
 965	 * Section 5.4.2) and bypass the timeout.
 966	 */
 967		res = readl(&xhci->op_regs->status);
 968		if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
 969		    (((res & STS_SRE) == 0) &&
 970				((res & STS_HCE) == 0))) {
 971			xhci->broken_suspend = 1;
 972		} else {
 973			xhci_warn(xhci, "WARN: xHC save state timeout\n");
 974			spin_unlock_irq(&xhci->lock);
 975			return -ETIMEDOUT;
 976		}
 977	}
 978	spin_unlock_irq(&xhci->lock);
 979
 980	/*
 981	 * Deleting Compliance Mode Recovery Timer because the xHCI Host
 982	 * is about to be suspended.
 983	 */
 984	if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 985			(!(xhci_all_ports_seen_u0(xhci)))) {
 986		del_timer_sync(&xhci->comp_mode_recovery_timer);
 987		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 988				"%s: compliance mode recovery timer deleted",
 989				__func__);
 990	}
 991
 
 
 
 
 992	return rc;
 993}
 994EXPORT_SYMBOL_GPL(xhci_suspend);
 995
 996/*
 997 * start xHC (not bus-specific)
 998 *
 999 * This is called when the machine transition from S3/S4 mode.
1000 *
1001 */
1002int xhci_resume(struct xhci_hcd *xhci, pm_message_t msg)
1003{
1004	bool			hibernated = (msg.event == PM_EVENT_RESTORE);
1005	u32			command, temp = 0;
1006	struct usb_hcd		*hcd = xhci_to_hcd(xhci);
 
1007	int			retval = 0;
1008	bool			comp_timer_running = false;
1009	bool			pending_portevent = false;
1010	bool			suspended_usb3_devs = false;
1011	bool			reinit_xhc = false;
1012
1013	if (!hcd->state)
1014		return 0;
1015
1016	/* Wait a bit if either of the roothubs need to settle from the
1017	 * transition into bus suspend.
1018	 */
1019
1020	if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1021	    time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1022		msleep(100);
1023
1024	set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1025	if (xhci->shared_hcd)
1026		set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1027
1028	spin_lock_irq(&xhci->lock);
 
 
1029
1030	if (hibernated || xhci->quirks & XHCI_RESET_ON_RESUME || xhci->broken_suspend)
1031		reinit_xhc = true;
1032
1033	if (!reinit_xhc) {
1034		/*
1035		 * Some controllers might lose power during suspend, so wait
1036		 * for controller not ready bit to clear, just as in xHC init.
1037		 */
1038		retval = xhci_handshake(&xhci->op_regs->status,
1039					STS_CNR, 0, 10 * 1000 * 1000);
1040		if (retval) {
1041			xhci_warn(xhci, "Controller not ready at resume %d\n",
1042				  retval);
1043			spin_unlock_irq(&xhci->lock);
1044			return retval;
1045		}
1046		/* step 1: restore register */
1047		xhci_restore_registers(xhci);
1048		/* step 2: initialize command ring buffer */
1049		xhci_set_cmd_ring_deq(xhci);
1050		/* step 3: restore state and start state*/
1051		/* step 3: set CRS flag */
1052		command = readl(&xhci->op_regs->command);
1053		command |= CMD_CRS;
1054		writel(command, &xhci->op_regs->command);
1055		/*
1056		 * Some controllers take up to 55+ ms to complete the controller
1057		 * restore so setting the timeout to 100ms. Xhci specification
1058		 * doesn't mention any timeout value.
1059		 */
1060		if (xhci_handshake(&xhci->op_regs->status,
1061			      STS_RESTORE, 0, 100 * 1000)) {
1062			xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1063			spin_unlock_irq(&xhci->lock);
1064			return -ETIMEDOUT;
1065		}
 
1066	}
1067
1068	temp = readl(&xhci->op_regs->status);
 
1069
1070	/* re-initialize the HC on Restore Error, or Host Controller Error */
1071	if ((temp & (STS_SRE | STS_HCE)) &&
1072	    !(xhci->xhc_state & XHCI_STATE_REMOVING)) {
1073		reinit_xhc = true;
1074		if (!xhci->broken_suspend)
1075			xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
1076	}
1077
1078	if (reinit_xhc) {
1079		if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1080				!(xhci_all_ports_seen_u0(xhci))) {
1081			del_timer_sync(&xhci->comp_mode_recovery_timer);
1082			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1083				"Compliance Mode Recovery Timer deleted!");
1084		}
1085
1086		/* Let the USB core know _both_ roothubs lost power. */
1087		usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1088		if (xhci->shared_hcd)
1089			usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1090
1091		xhci_dbg(xhci, "Stop HCD\n");
1092		xhci_halt(xhci);
1093		xhci_zero_64b_regs(xhci);
1094		retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
1095		spin_unlock_irq(&xhci->lock);
1096		if (retval)
1097			return retval;
1098
1099		xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1100		temp = readl(&xhci->op_regs->status);
1101		writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1102		xhci_disable_interrupter(xhci->interrupters[0]);
 
 
1103
1104		xhci_dbg(xhci, "cleaning up memory\n");
1105		xhci_mem_cleanup(xhci);
1106		xhci_debugfs_exit(xhci);
1107		xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1108			    readl(&xhci->op_regs->status));
1109
1110		/* USB core calls the PCI reinit and start functions twice:
1111		 * first with the primary HCD, and then with the secondary HCD.
1112		 * If we don't do the same, the host will never be started.
1113		 */
 
 
 
 
 
1114		xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1115		retval = xhci_init(hcd);
1116		if (retval)
1117			return retval;
1118		comp_timer_running = true;
1119
1120		xhci_dbg(xhci, "Start the primary HCD\n");
1121		retval = xhci_run(hcd);
1122		if (!retval && xhci->shared_hcd) {
1123			xhci_dbg(xhci, "Start the secondary HCD\n");
1124			retval = xhci_run(xhci->shared_hcd);
1125		}
1126
1127		hcd->state = HC_STATE_SUSPENDED;
1128		if (xhci->shared_hcd)
1129			xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1130		goto done;
1131	}
1132
1133	/* step 4: set Run/Stop bit */
1134	command = readl(&xhci->op_regs->command);
1135	command |= CMD_RUN;
1136	writel(command, &xhci->op_regs->command);
1137	xhci_handshake(&xhci->op_regs->status, STS_HALT,
1138		  0, 250 * 1000);
1139
1140	/* step 5: walk topology and initialize portsc,
1141	 * portpmsc and portli
1142	 */
1143	/* this is done in bus_resume */
1144
1145	/* step 6: restart each of the previously
1146	 * Running endpoints by ringing their doorbells
1147	 */
1148
1149	spin_unlock_irq(&xhci->lock);
1150
1151	xhci_dbc_resume(xhci);
1152
1153 done:
1154	if (retval == 0) {
1155		/*
1156		 * Resume roothubs only if there are pending events.
1157		 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1158		 * the first wake signalling failed, give it that chance if
1159		 * there are suspended USB 3 devices.
1160		 */
1161		if (xhci->usb3_rhub.bus_state.suspended_ports ||
1162		    xhci->usb3_rhub.bus_state.bus_suspended)
1163			suspended_usb3_devs = true;
1164
1165		pending_portevent = xhci_pending_portevent(xhci);
1166
1167		if (suspended_usb3_devs && !pending_portevent &&
1168		    msg.event == PM_EVENT_AUTO_RESUME) {
1169			msleep(120);
1170			pending_portevent = xhci_pending_portevent(xhci);
1171		}
1172
1173		if (pending_portevent) {
1174			if (xhci->shared_hcd)
1175				usb_hcd_resume_root_hub(xhci->shared_hcd);
1176			usb_hcd_resume_root_hub(hcd);
1177		}
1178	}
 
1179	/*
1180	 * If system is subject to the Quirk, Compliance Mode Timer needs to
1181	 * be re-initialized Always after a system resume. Ports are subject
1182	 * to suffer the Compliance Mode issue again. It doesn't matter if
1183	 * ports have entered previously to U0 before system's suspension.
1184	 */
1185	if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1186		compliance_mode_recovery_timer_init(xhci);
1187
1188	if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1189		usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1190
1191	/* Re-enable port polling. */
1192	xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
1193		 __func__, hcd->self.busnum);
1194	if (xhci->shared_hcd) {
1195		set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1196		usb_hcd_poll_rh_status(xhci->shared_hcd);
1197	}
1198	set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1199	usb_hcd_poll_rh_status(hcd);
1200
1201	return retval;
1202}
1203EXPORT_SYMBOL_GPL(xhci_resume);
1204#endif	/* CONFIG_PM */
1205
1206/*-------------------------------------------------------------------------*/
1207
1208static int xhci_map_temp_buffer(struct usb_hcd *hcd, struct urb *urb)
1209{
1210	void *temp;
1211	int ret = 0;
1212	unsigned int buf_len;
1213	enum dma_data_direction dir;
1214
1215	dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1216	buf_len = urb->transfer_buffer_length;
1217
1218	temp = kzalloc_node(buf_len, GFP_ATOMIC,
1219			    dev_to_node(hcd->self.sysdev));
1220
1221	if (usb_urb_dir_out(urb))
1222		sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
1223				   temp, buf_len, 0);
1224
1225	urb->transfer_buffer = temp;
1226	urb->transfer_dma = dma_map_single(hcd->self.sysdev,
1227					   urb->transfer_buffer,
1228					   urb->transfer_buffer_length,
1229					   dir);
1230
1231	if (dma_mapping_error(hcd->self.sysdev,
1232			      urb->transfer_dma)) {
1233		ret = -EAGAIN;
1234		kfree(temp);
1235	} else {
1236		urb->transfer_flags |= URB_DMA_MAP_SINGLE;
1237	}
1238
1239	return ret;
1240}
1241
1242static bool xhci_urb_temp_buffer_required(struct usb_hcd *hcd,
1243					  struct urb *urb)
1244{
1245	bool ret = false;
1246	unsigned int i;
1247	unsigned int len = 0;
1248	unsigned int trb_size;
1249	unsigned int max_pkt;
1250	struct scatterlist *sg;
1251	struct scatterlist *tail_sg;
1252
1253	tail_sg = urb->sg;
1254	max_pkt = usb_endpoint_maxp(&urb->ep->desc);
1255
1256	if (!urb->num_sgs)
1257		return ret;
1258
1259	if (urb->dev->speed >= USB_SPEED_SUPER)
1260		trb_size = TRB_CACHE_SIZE_SS;
1261	else
1262		trb_size = TRB_CACHE_SIZE_HS;
1263
1264	if (urb->transfer_buffer_length != 0 &&
1265	    !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) {
1266		for_each_sg(urb->sg, sg, urb->num_sgs, i) {
1267			len = len + sg->length;
1268			if (i > trb_size - 2) {
1269				len = len - tail_sg->length;
1270				if (len < max_pkt) {
1271					ret = true;
1272					break;
1273				}
1274
1275				tail_sg = sg_next(tail_sg);
1276			}
1277		}
1278	}
1279	return ret;
1280}
1281
1282static void xhci_unmap_temp_buf(struct usb_hcd *hcd, struct urb *urb)
1283{
1284	unsigned int len;
1285	unsigned int buf_len;
1286	enum dma_data_direction dir;
1287
1288	dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1289
1290	buf_len = urb->transfer_buffer_length;
1291
1292	if (IS_ENABLED(CONFIG_HAS_DMA) &&
1293	    (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1294		dma_unmap_single(hcd->self.sysdev,
1295				 urb->transfer_dma,
1296				 urb->transfer_buffer_length,
1297				 dir);
1298
1299	if (usb_urb_dir_in(urb)) {
1300		len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs,
1301					   urb->transfer_buffer,
1302					   buf_len,
1303					   0);
1304		if (len != buf_len) {
1305			xhci_dbg(hcd_to_xhci(hcd),
1306				 "Copy from tmp buf to urb sg list failed\n");
1307			urb->actual_length = len;
1308		}
1309	}
1310	urb->transfer_flags &= ~URB_DMA_MAP_SINGLE;
1311	kfree(urb->transfer_buffer);
1312	urb->transfer_buffer = NULL;
1313}
1314
1315/*
1316 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1317 * we'll copy the actual data into the TRB address register. This is limited to
1318 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1319 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1320 */
1321static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1322				gfp_t mem_flags)
1323{
1324	struct xhci_hcd *xhci;
1325
1326	xhci = hcd_to_xhci(hcd);
1327
1328	if (xhci_urb_suitable_for_idt(urb))
1329		return 0;
1330
1331	if (xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) {
1332		if (xhci_urb_temp_buffer_required(hcd, urb))
1333			return xhci_map_temp_buffer(hcd, urb);
1334	}
1335	return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1336}
1337
1338static void xhci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
1339{
1340	struct xhci_hcd *xhci;
1341	bool unmap_temp_buf = false;
1342
1343	xhci = hcd_to_xhci(hcd);
1344
1345	if (urb->num_sgs && (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1346		unmap_temp_buf = true;
1347
1348	if ((xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) && unmap_temp_buf)
1349		xhci_unmap_temp_buf(hcd, urb);
1350	else
1351		usb_hcd_unmap_urb_for_dma(hcd, urb);
1352}
1353
1354/**
1355 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1356 * HCDs.  Find the index for an endpoint given its descriptor.  Use the return
1357 * value to right shift 1 for the bitmask.
1358 *
1359 * Index  = (epnum * 2) + direction - 1,
1360 * where direction = 0 for OUT, 1 for IN.
1361 * For control endpoints, the IN index is used (OUT index is unused), so
1362 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1363 */
1364unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1365{
1366	unsigned int index;
1367	if (usb_endpoint_xfer_control(desc))
1368		index = (unsigned int) (usb_endpoint_num(desc)*2);
1369	else
1370		index = (unsigned int) (usb_endpoint_num(desc)*2) +
1371			(usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1372	return index;
1373}
1374EXPORT_SYMBOL_GPL(xhci_get_endpoint_index);
1375
1376/* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1377 * address from the XHCI endpoint index.
1378 */
1379static unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1380{
1381	unsigned int number = DIV_ROUND_UP(ep_index, 2);
1382	unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1383	return direction | number;
1384}
1385
1386/* Find the flag for this endpoint (for use in the control context).  Use the
1387 * endpoint index to create a bitmask.  The slot context is bit 0, endpoint 0 is
1388 * bit 1, etc.
1389 */
1390static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1391{
1392	return 1 << (xhci_get_endpoint_index(desc) + 1);
1393}
1394
 
 
 
 
 
 
 
 
 
1395/* Compute the last valid endpoint context index.  Basically, this is the
1396 * endpoint index plus one.  For slot contexts with more than valid endpoint,
1397 * we find the most significant bit set in the added contexts flags.
1398 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1399 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1400 */
1401unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1402{
1403	return fls(added_ctxs) - 1;
1404}
1405
1406/* Returns 1 if the arguments are OK;
1407 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1408 */
1409static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1410		struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1411		const char *func) {
1412	struct xhci_hcd	*xhci;
1413	struct xhci_virt_device	*virt_dev;
1414
1415	if (!hcd || (check_ep && !ep) || !udev) {
1416		pr_debug("xHCI %s called with invalid args\n", func);
1417		return -EINVAL;
1418	}
1419	if (!udev->parent) {
1420		pr_debug("xHCI %s called for root hub\n", func);
1421		return 0;
1422	}
1423
1424	xhci = hcd_to_xhci(hcd);
1425	if (check_virt_dev) {
1426		if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1427			xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1428					func);
1429			return -EINVAL;
1430		}
1431
1432		virt_dev = xhci->devs[udev->slot_id];
1433		if (virt_dev->udev != udev) {
1434			xhci_dbg(xhci, "xHCI %s called with udev and "
1435					  "virt_dev does not match\n", func);
1436			return -EINVAL;
1437		}
1438	}
1439
1440	if (xhci->xhc_state & XHCI_STATE_HALTED)
1441		return -ENODEV;
1442
1443	return 1;
1444}
1445
1446static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1447		struct usb_device *udev, struct xhci_command *command,
1448		bool ctx_change, bool must_succeed);
1449
1450/*
1451 * Full speed devices may have a max packet size greater than 8 bytes, but the
1452 * USB core doesn't know that until it reads the first 8 bytes of the
1453 * descriptor.  If the usb_device's max packet size changes after that point,
1454 * we need to issue an evaluate context command and wait on it.
1455 */
1456static int xhci_check_ep0_maxpacket(struct xhci_hcd *xhci, struct xhci_virt_device *vdev)
 
1457{
 
 
1458	struct xhci_input_control_ctx *ctrl_ctx;
1459	struct xhci_ep_ctx *ep_ctx;
1460	struct xhci_command *command;
1461	int max_packet_size;
1462	int hw_max_packet_size;
1463	int ret = 0;
1464
1465	ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, 0);
 
1466	hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1467	max_packet_size = usb_endpoint_maxp(&vdev->udev->ep0.desc);
1468
1469	if (hw_max_packet_size == max_packet_size)
1470		return 0;
1471
1472	switch (max_packet_size) {
1473	case 8: case 16: case 32: case 64: case 9:
1474		xhci_dbg_trace(xhci,  trace_xhci_dbg_context_change,
1475				"Max Packet Size for ep 0 changed.");
1476		xhci_dbg_trace(xhci,  trace_xhci_dbg_context_change,
1477				"Max packet size in usb_device = %d",
1478				max_packet_size);
1479		xhci_dbg_trace(xhci,  trace_xhci_dbg_context_change,
1480				"Max packet size in xHCI HW = %d",
1481				hw_max_packet_size);
1482		xhci_dbg_trace(xhci,  trace_xhci_dbg_context_change,
1483				"Issuing evaluate context command.");
1484
1485		command = xhci_alloc_command(xhci, true, GFP_KERNEL);
1486		if (!command)
1487			return -ENOMEM;
1488
1489		command->in_ctx = vdev->in_ctx;
1490		ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1491		if (!ctrl_ctx) {
1492			xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1493					__func__);
1494			ret = -ENOMEM;
1495			break;
1496		}
1497		/* Set up the modified control endpoint 0 */
1498		xhci_endpoint_copy(xhci, vdev->in_ctx, vdev->out_ctx, 0);
 
1499
1500		ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, 0);
1501		ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1502		ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1503		ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1504
1505		ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1506		ctrl_ctx->drop_flags = 0;
1507
1508		ret = xhci_configure_endpoint(xhci, vdev->udev, command,
1509					      true, false);
1510		/* Clean up the input context for later use by bandwidth functions */
1511		ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1512		break;
1513	default:
1514		dev_dbg(&vdev->udev->dev, "incorrect max packet size %d for ep0\n",
1515			max_packet_size);
1516		return -EINVAL;
1517	}
1518
1519	kfree(command->completion);
1520	kfree(command);
1521
 
 
 
 
 
1522	return ret;
1523}
1524
1525/*
1526 * non-error returns are a promise to giveback() the urb later
1527 * we drop ownership so next owner (or urb unlink) can get it
1528 */
1529static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1530{
1531	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 
1532	unsigned long flags;
1533	int ret = 0;
1534	unsigned int slot_id, ep_index;
1535	unsigned int *ep_state;
1536	struct urb_priv	*urb_priv;
1537	int num_tds;
1538
 
 
 
 
 
1539	ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1540
 
 
 
 
 
 
 
1541	if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1542		num_tds = urb->number_of_packets;
1543	else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1544	    urb->transfer_buffer_length > 0 &&
1545	    urb->transfer_flags & URB_ZERO_PACKET &&
1546	    !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1547		num_tds = 2;
1548	else
1549		num_tds = 1;
1550
1551	urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
 
1552	if (!urb_priv)
1553		return -ENOMEM;
1554
1555	urb_priv->num_tds = num_tds;
1556	urb_priv->num_tds_done = 0;
1557	urb->hcpriv = urb_priv;
1558
1559	trace_xhci_urb_enqueue(urb);
1560
1561	spin_lock_irqsave(&xhci->lock, flags);
1562
1563	ret = xhci_check_args(hcd, urb->dev, urb->ep,
1564			      true, true, __func__);
1565	if (ret <= 0) {
1566		ret = ret ? ret : -EINVAL;
1567		goto free_priv;
1568	}
1569
1570	slot_id = urb->dev->slot_id;
1571
1572	if (!HCD_HW_ACCESSIBLE(hcd)) {
1573		ret = -ESHUTDOWN;
1574		goto free_priv;
1575	}
1576
1577	if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1578		xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1579		ret = -ENODEV;
1580		goto free_priv;
1581	}
1582
1583	if (xhci->xhc_state & XHCI_STATE_DYING) {
1584		xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1585			 urb->ep->desc.bEndpointAddress, urb);
1586		ret = -ESHUTDOWN;
1587		goto free_priv;
1588	}
1589
1590	ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1591
1592	if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1593		xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1594			  *ep_state);
1595		ret = -EINVAL;
1596		goto free_priv;
1597	}
1598	if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1599		xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1600		ret = -EINVAL;
1601		goto free_priv;
1602	}
1603
1604	switch (usb_endpoint_type(&urb->ep->desc)) {
 
 
 
 
 
 
 
 
 
 
 
 
1605
1606	case USB_ENDPOINT_XFER_CONTROL:
 
 
 
 
 
1607		ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1608					 slot_id, ep_index);
1609		break;
1610	case USB_ENDPOINT_XFER_BULK:
1611		ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1612					 slot_id, ep_index);
1613		break;
1614	case USB_ENDPOINT_XFER_INT:
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1615		ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1616				slot_id, ep_index);
1617		break;
1618	case USB_ENDPOINT_XFER_ISOC:
 
 
 
 
 
1619		ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1620				slot_id, ep_index);
 
 
 
1621	}
1622
1623	if (ret) {
 
 
 
 
 
1624free_priv:
1625		xhci_urb_free_priv(urb_priv);
1626		urb->hcpriv = NULL;
1627	}
1628	spin_unlock_irqrestore(&xhci->lock, flags);
1629	return ret;
1630}
1631
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1632/*
1633 * Remove the URB's TD from the endpoint ring.  This may cause the HC to stop
1634 * USB transfers, potentially stopping in the middle of a TRB buffer.  The HC
1635 * should pick up where it left off in the TD, unless a Set Transfer Ring
1636 * Dequeue Pointer is issued.
1637 *
1638 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1639 * the ring.  Since the ring is a contiguous structure, they can't be physically
1640 * removed.  Instead, there are two options:
1641 *
1642 *  1) If the HC is in the middle of processing the URB to be canceled, we
1643 *     simply move the ring's dequeue pointer past those TRBs using the Set
1644 *     Transfer Ring Dequeue Pointer command.  This will be the common case,
1645 *     when drivers timeout on the last submitted URB and attempt to cancel.
1646 *
1647 *  2) If the HC is in the middle of a different TD, we turn the TRBs into a
1648 *     series of 1-TRB transfer no-op TDs.  (No-ops shouldn't be chained.)  The
1649 *     HC will need to invalidate the any TRBs it has cached after the stop
1650 *     endpoint command, as noted in the xHCI 0.95 errata.
1651 *
1652 *  3) The TD may have completed by the time the Stop Endpoint Command
1653 *     completes, so software needs to handle that case too.
1654 *
1655 * This function should protect against the TD enqueueing code ringing the
1656 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1657 * It also needs to account for multiple cancellations on happening at the same
1658 * time for the same endpoint.
1659 *
1660 * Note that this function can be called in any context, or so says
1661 * usb_hcd_unlink_urb()
1662 */
1663static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1664{
1665	unsigned long flags;
1666	int ret, i;
1667	u32 temp;
1668	struct xhci_hcd *xhci;
1669	struct urb_priv	*urb_priv;
1670	struct xhci_td *td;
1671	unsigned int ep_index;
1672	struct xhci_ring *ep_ring;
1673	struct xhci_virt_ep *ep;
1674	struct xhci_command *command;
1675	struct xhci_virt_device *vdev;
1676
1677	xhci = hcd_to_xhci(hcd);
1678	spin_lock_irqsave(&xhci->lock, flags);
1679
1680	trace_xhci_urb_dequeue(urb);
1681
1682	/* Make sure the URB hasn't completed or been unlinked already */
1683	ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1684	if (ret)
1685		goto done;
1686
1687	/* give back URB now if we can't queue it for cancel */
1688	vdev = xhci->devs[urb->dev->slot_id];
1689	urb_priv = urb->hcpriv;
1690	if (!vdev || !urb_priv)
1691		goto err_giveback;
1692
1693	ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1694	ep = &vdev->eps[ep_index];
1695	ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1696	if (!ep || !ep_ring)
1697		goto err_giveback;
1698
1699	/* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1700	temp = readl(&xhci->op_regs->status);
1701	if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1702		xhci_hc_died(xhci);
1703		goto done;
1704	}
1705
1706	/*
1707	 * check ring is not re-allocated since URB was enqueued. If it is, then
1708	 * make sure none of the ring related pointers in this URB private data
1709	 * are touched, such as td_list, otherwise we overwrite freed data
1710	 */
1711	if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1712		xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1713		for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1714			td = &urb_priv->td[i];
1715			if (!list_empty(&td->cancelled_td_list))
1716				list_del_init(&td->cancelled_td_list);
1717		}
1718		goto err_giveback;
1719	}
1720
1721	if (xhci->xhc_state & XHCI_STATE_HALTED) {
1722		xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1723				"HC halted, freeing TD manually.");
1724		for (i = urb_priv->num_tds_done;
1725		     i < urb_priv->num_tds;
1726		     i++) {
1727			td = &urb_priv->td[i];
1728			if (!list_empty(&td->td_list))
1729				list_del_init(&td->td_list);
1730			if (!list_empty(&td->cancelled_td_list))
1731				list_del_init(&td->cancelled_td_list);
1732		}
1733		goto err_giveback;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1734	}
1735
1736	i = urb_priv->num_tds_done;
1737	if (i < urb_priv->num_tds)
 
1738		xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1739				"Cancel URB %p, dev %s, ep 0x%x, "
1740				"starting at offset 0x%llx",
1741				urb, urb->dev->devpath,
1742				urb->ep->desc.bEndpointAddress,
1743				(unsigned long long) xhci_trb_virt_to_dma(
1744					urb_priv->td[i].start_seg,
1745					urb_priv->td[i].first_trb));
1746
1747	for (; i < urb_priv->num_tds; i++) {
1748		td = &urb_priv->td[i];
1749		/* TD can already be on cancelled list if ep halted on it */
1750		if (list_empty(&td->cancelled_td_list)) {
1751			td->cancel_status = TD_DIRTY;
1752			list_add_tail(&td->cancelled_td_list,
1753				      &ep->cancelled_td_list);
1754		}
1755	}
1756
1757	/* Queue a stop endpoint command, but only if this is
1758	 * the first cancellation to be handled.
1759	 */
1760	if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1761		command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1762		if (!command) {
1763			ret = -ENOMEM;
1764			goto done;
1765		}
1766		ep->ep_state |= EP_STOP_CMD_PENDING;
1767		xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1768					 ep_index, 0);
1769		xhci_ring_cmd_db(xhci);
1770	}
1771done:
1772	spin_unlock_irqrestore(&xhci->lock, flags);
1773	return ret;
1774
1775err_giveback:
1776	if (urb_priv)
1777		xhci_urb_free_priv(urb_priv);
1778	usb_hcd_unlink_urb_from_ep(hcd, urb);
1779	spin_unlock_irqrestore(&xhci->lock, flags);
1780	usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1781	return ret;
1782}
1783
1784/* Drop an endpoint from a new bandwidth configuration for this device.
1785 * Only one call to this function is allowed per endpoint before
1786 * check_bandwidth() or reset_bandwidth() must be called.
1787 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1788 * add the endpoint to the schedule with possibly new parameters denoted by a
1789 * different endpoint descriptor in usb_host_endpoint.
1790 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1791 * not allowed.
1792 *
1793 * The USB core will not allow URBs to be queued to an endpoint that is being
1794 * disabled, so there's no need for mutual exclusion to protect
1795 * the xhci->devs[slot_id] structure.
1796 */
1797int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1798		       struct usb_host_endpoint *ep)
1799{
1800	struct xhci_hcd *xhci;
1801	struct xhci_container_ctx *in_ctx, *out_ctx;
1802	struct xhci_input_control_ctx *ctrl_ctx;
 
 
1803	unsigned int ep_index;
1804	struct xhci_ep_ctx *ep_ctx;
1805	u32 drop_flag;
1806	u32 new_add_flags, new_drop_flags;
1807	int ret;
1808
1809	ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1810	if (ret <= 0)
1811		return ret;
1812	xhci = hcd_to_xhci(hcd);
1813	if (xhci->xhc_state & XHCI_STATE_DYING)
1814		return -ENODEV;
1815
1816	xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1817	drop_flag = xhci_get_endpoint_flag(&ep->desc);
1818	if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1819		xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1820				__func__, drop_flag);
1821		return 0;
1822	}
1823
1824	in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1825	out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1826	ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1827	if (!ctrl_ctx) {
1828		xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1829				__func__);
1830		return 0;
1831	}
1832
1833	ep_index = xhci_get_endpoint_index(&ep->desc);
1834	ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1835	/* If the HC already knows the endpoint is disabled,
1836	 * or the HCD has noted it is disabled, ignore this request
1837	 */
1838	if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
 
1839	    le32_to_cpu(ctrl_ctx->drop_flags) &
1840	    xhci_get_endpoint_flag(&ep->desc)) {
1841		/* Do not warn when called after a usb_device_reset */
1842		if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1843			xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1844				  __func__, ep);
1845		return 0;
1846	}
1847
1848	ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1849	new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1850
1851	ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1852	new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1853
1854	xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
 
 
 
 
 
 
 
 
1855
1856	xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1857
1858	xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1859			(unsigned int) ep->desc.bEndpointAddress,
1860			udev->slot_id,
1861			(unsigned int) new_drop_flags,
1862			(unsigned int) new_add_flags);
 
1863	return 0;
1864}
1865EXPORT_SYMBOL_GPL(xhci_drop_endpoint);
1866
1867/* Add an endpoint to a new possible bandwidth configuration for this device.
1868 * Only one call to this function is allowed per endpoint before
1869 * check_bandwidth() or reset_bandwidth() must be called.
1870 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1871 * add the endpoint to the schedule with possibly new parameters denoted by a
1872 * different endpoint descriptor in usb_host_endpoint.
1873 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1874 * not allowed.
1875 *
1876 * The USB core will not allow URBs to be queued to an endpoint until the
1877 * configuration or alt setting is installed in the device, so there's no need
1878 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1879 */
1880int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1881		      struct usb_host_endpoint *ep)
1882{
1883	struct xhci_hcd *xhci;
1884	struct xhci_container_ctx *in_ctx;
1885	unsigned int ep_index;
 
1886	struct xhci_input_control_ctx *ctrl_ctx;
1887	struct xhci_ep_ctx *ep_ctx;
1888	u32 added_ctxs;
1889	u32 new_add_flags, new_drop_flags;
 
1890	struct xhci_virt_device *virt_dev;
1891	int ret = 0;
1892
1893	ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1894	if (ret <= 0) {
1895		/* So we won't queue a reset ep command for a root hub */
1896		ep->hcpriv = NULL;
1897		return ret;
1898	}
1899	xhci = hcd_to_xhci(hcd);
1900	if (xhci->xhc_state & XHCI_STATE_DYING)
1901		return -ENODEV;
1902
1903	added_ctxs = xhci_get_endpoint_flag(&ep->desc);
 
1904	if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1905		/* FIXME when we have to issue an evaluate endpoint command to
1906		 * deal with ep0 max packet size changing once we get the
1907		 * descriptors
1908		 */
1909		xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1910				__func__, added_ctxs);
1911		return 0;
1912	}
1913
1914	virt_dev = xhci->devs[udev->slot_id];
1915	in_ctx = virt_dev->in_ctx;
1916	ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
 
1917	if (!ctrl_ctx) {
1918		xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1919				__func__);
1920		return 0;
1921	}
1922
1923	ep_index = xhci_get_endpoint_index(&ep->desc);
1924	/* If this endpoint is already in use, and the upper layers are trying
1925	 * to add it again without dropping it, reject the addition.
1926	 */
1927	if (virt_dev->eps[ep_index].ring &&
1928			!(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
 
1929		xhci_warn(xhci, "Trying to add endpoint 0x%x "
1930				"without dropping it.\n",
1931				(unsigned int) ep->desc.bEndpointAddress);
1932		return -EINVAL;
1933	}
1934
1935	/* If the HCD has already noted the endpoint is enabled,
1936	 * ignore this request.
1937	 */
1938	if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
 
1939		xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1940				__func__, ep);
1941		return 0;
1942	}
1943
1944	/*
1945	 * Configuration and alternate setting changes must be done in
1946	 * process context, not interrupt context (or so documenation
1947	 * for usb_set_interface() and usb_set_configuration() claim).
1948	 */
1949	if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1950		dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1951				__func__, ep->desc.bEndpointAddress);
1952		return -ENOMEM;
1953	}
1954
1955	ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1956	new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1957
1958	/* If xhci_endpoint_disable() was called for this endpoint, but the
1959	 * xHC hasn't been notified yet through the check_bandwidth() call,
1960	 * this re-adds a new state for the endpoint from the new endpoint
1961	 * descriptors.  We must drop and re-add this endpoint, so we leave the
1962	 * drop flags alone.
1963	 */
1964	new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1965
 
 
 
 
 
 
 
 
 
1966	/* Store the usb_device pointer for later use */
1967	ep->hcpriv = udev;
1968
1969	ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1970	trace_xhci_add_endpoint(ep_ctx);
1971
1972	xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1973			(unsigned int) ep->desc.bEndpointAddress,
1974			udev->slot_id,
1975			(unsigned int) new_drop_flags,
1976			(unsigned int) new_add_flags);
 
1977	return 0;
1978}
1979EXPORT_SYMBOL_GPL(xhci_add_endpoint);
1980
1981static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1982{
1983	struct xhci_input_control_ctx *ctrl_ctx;
1984	struct xhci_ep_ctx *ep_ctx;
1985	struct xhci_slot_ctx *slot_ctx;
1986	int i;
1987
1988	ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1989	if (!ctrl_ctx) {
1990		xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1991				__func__);
1992		return;
1993	}
1994
1995	/* When a device's add flag and drop flag are zero, any subsequent
1996	 * configure endpoint command will leave that endpoint's state
1997	 * untouched.  Make sure we don't leave any old state in the input
1998	 * endpoint contexts.
1999	 */
2000	ctrl_ctx->drop_flags = 0;
2001	ctrl_ctx->add_flags = 0;
2002	slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2003	slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2004	/* Endpoint 0 is always valid */
2005	slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
2006	for (i = 1; i < 31; i++) {
2007		ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
2008		ep_ctx->ep_info = 0;
2009		ep_ctx->ep_info2 = 0;
2010		ep_ctx->deq = 0;
2011		ep_ctx->tx_info = 0;
2012	}
2013}
2014
2015static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
2016		struct usb_device *udev, u32 *cmd_status)
2017{
2018	int ret;
2019
2020	switch (*cmd_status) {
2021	case COMP_COMMAND_ABORTED:
2022	case COMP_COMMAND_RING_STOPPED:
2023		xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
2024		ret = -ETIME;
2025		break;
2026	case COMP_RESOURCE_ERROR:
2027		dev_warn(&udev->dev,
2028			 "Not enough host controller resources for new device state.\n");
2029		ret = -ENOMEM;
2030		/* FIXME: can we allocate more resources for the HC? */
2031		break;
2032	case COMP_BANDWIDTH_ERROR:
2033	case COMP_SECONDARY_BANDWIDTH_ERROR:
2034		dev_warn(&udev->dev,
2035			 "Not enough bandwidth for new device state.\n");
2036		ret = -ENOSPC;
2037		/* FIXME: can we go back to the old state? */
2038		break;
2039	case COMP_TRB_ERROR:
2040		/* the HCD set up something wrong */
2041		dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
2042				"add flag = 1, "
2043				"and endpoint is not disabled.\n");
2044		ret = -EINVAL;
2045		break;
2046	case COMP_INCOMPATIBLE_DEVICE_ERROR:
2047		dev_warn(&udev->dev,
2048			 "ERROR: Incompatible device for endpoint configure command.\n");
2049		ret = -ENODEV;
2050		break;
2051	case COMP_SUCCESS:
2052		xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2053				"Successful Endpoint Configure command");
2054		ret = 0;
2055		break;
2056	default:
2057		xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2058				*cmd_status);
2059		ret = -EINVAL;
2060		break;
2061	}
2062	return ret;
2063}
2064
2065static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2066		struct usb_device *udev, u32 *cmd_status)
2067{
2068	int ret;
 
2069
2070	switch (*cmd_status) {
2071	case COMP_COMMAND_ABORTED:
2072	case COMP_COMMAND_RING_STOPPED:
2073		xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2074		ret = -ETIME;
2075		break;
2076	case COMP_PARAMETER_ERROR:
2077		dev_warn(&udev->dev,
2078			 "WARN: xHCI driver setup invalid evaluate context command.\n");
2079		ret = -EINVAL;
2080		break;
2081	case COMP_SLOT_NOT_ENABLED_ERROR:
2082		dev_warn(&udev->dev,
2083			"WARN: slot not enabled for evaluate context command.\n");
2084		ret = -EINVAL;
2085		break;
2086	case COMP_CONTEXT_STATE_ERROR:
2087		dev_warn(&udev->dev,
2088			"WARN: invalid context state for evaluate context command.\n");
 
2089		ret = -EINVAL;
2090		break;
2091	case COMP_INCOMPATIBLE_DEVICE_ERROR:
2092		dev_warn(&udev->dev,
2093			"ERROR: Incompatible device for evaluate context command.\n");
2094		ret = -ENODEV;
2095		break;
2096	case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2097		/* Max Exit Latency too large error */
2098		dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2099		ret = -EINVAL;
2100		break;
2101	case COMP_SUCCESS:
2102		xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2103				"Successful evaluate context command");
2104		ret = 0;
2105		break;
2106	default:
2107		xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2108			*cmd_status);
2109		ret = -EINVAL;
2110		break;
2111	}
2112	return ret;
2113}
2114
2115static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2116		struct xhci_input_control_ctx *ctrl_ctx)
2117{
2118	u32 valid_add_flags;
2119	u32 valid_drop_flags;
2120
2121	/* Ignore the slot flag (bit 0), and the default control endpoint flag
2122	 * (bit 1).  The default control endpoint is added during the Address
2123	 * Device command and is never removed until the slot is disabled.
2124	 */
2125	valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2126	valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2127
2128	/* Use hweight32 to count the number of ones in the add flags, or
2129	 * number of endpoints added.  Don't count endpoints that are changed
2130	 * (both added and dropped).
2131	 */
2132	return hweight32(valid_add_flags) -
2133		hweight32(valid_add_flags & valid_drop_flags);
2134}
2135
2136static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2137		struct xhci_input_control_ctx *ctrl_ctx)
2138{
2139	u32 valid_add_flags;
2140	u32 valid_drop_flags;
2141
2142	valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2143	valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2144
2145	return hweight32(valid_drop_flags) -
2146		hweight32(valid_add_flags & valid_drop_flags);
2147}
2148
2149/*
2150 * We need to reserve the new number of endpoints before the configure endpoint
2151 * command completes.  We can't subtract the dropped endpoints from the number
2152 * of active endpoints until the command completes because we can oversubscribe
2153 * the host in this case:
2154 *
2155 *  - the first configure endpoint command drops more endpoints than it adds
2156 *  - a second configure endpoint command that adds more endpoints is queued
2157 *  - the first configure endpoint command fails, so the config is unchanged
2158 *  - the second command may succeed, even though there isn't enough resources
2159 *
2160 * Must be called with xhci->lock held.
2161 */
2162static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2163		struct xhci_input_control_ctx *ctrl_ctx)
2164{
2165	u32 added_eps;
2166
2167	added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2168	if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2169		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2170				"Not enough ep ctxs: "
2171				"%u active, need to add %u, limit is %u.",
2172				xhci->num_active_eps, added_eps,
2173				xhci->limit_active_eps);
2174		return -ENOMEM;
2175	}
2176	xhci->num_active_eps += added_eps;
2177	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2178			"Adding %u ep ctxs, %u now active.", added_eps,
2179			xhci->num_active_eps);
2180	return 0;
2181}
2182
2183/*
2184 * The configure endpoint was failed by the xHC for some other reason, so we
2185 * need to revert the resources that failed configuration would have used.
2186 *
2187 * Must be called with xhci->lock held.
2188 */
2189static void xhci_free_host_resources(struct xhci_hcd *xhci,
2190		struct xhci_input_control_ctx *ctrl_ctx)
2191{
2192	u32 num_failed_eps;
2193
2194	num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2195	xhci->num_active_eps -= num_failed_eps;
2196	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2197			"Removing %u failed ep ctxs, %u now active.",
2198			num_failed_eps,
2199			xhci->num_active_eps);
2200}
2201
2202/*
2203 * Now that the command has completed, clean up the active endpoint count by
2204 * subtracting out the endpoints that were dropped (but not changed).
2205 *
2206 * Must be called with xhci->lock held.
2207 */
2208static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2209		struct xhci_input_control_ctx *ctrl_ctx)
2210{
2211	u32 num_dropped_eps;
2212
2213	num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2214	xhci->num_active_eps -= num_dropped_eps;
2215	if (num_dropped_eps)
2216		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2217				"Removing %u dropped ep ctxs, %u now active.",
2218				num_dropped_eps,
2219				xhci->num_active_eps);
2220}
2221
2222static unsigned int xhci_get_block_size(struct usb_device *udev)
2223{
2224	switch (udev->speed) {
2225	case USB_SPEED_LOW:
2226	case USB_SPEED_FULL:
2227		return FS_BLOCK;
2228	case USB_SPEED_HIGH:
2229		return HS_BLOCK;
2230	case USB_SPEED_SUPER:
2231	case USB_SPEED_SUPER_PLUS:
2232		return SS_BLOCK;
2233	case USB_SPEED_UNKNOWN:
 
2234	default:
2235		/* Should never happen */
2236		return 1;
2237	}
2238}
2239
2240static unsigned int
2241xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2242{
2243	if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2244		return LS_OVERHEAD;
2245	if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2246		return FS_OVERHEAD;
2247	return HS_OVERHEAD;
2248}
2249
2250/* If we are changing a LS/FS device under a HS hub,
2251 * make sure (if we are activating a new TT) that the HS bus has enough
2252 * bandwidth for this new TT.
2253 */
2254static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2255		struct xhci_virt_device *virt_dev,
2256		int old_active_eps)
2257{
2258	struct xhci_interval_bw_table *bw_table;
2259	struct xhci_tt_bw_info *tt_info;
2260
2261	/* Find the bandwidth table for the root port this TT is attached to. */
2262	bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2263	tt_info = virt_dev->tt_info;
2264	/* If this TT already had active endpoints, the bandwidth for this TT
2265	 * has already been added.  Removing all periodic endpoints (and thus
2266	 * making the TT enactive) will only decrease the bandwidth used.
2267	 */
2268	if (old_active_eps)
2269		return 0;
2270	if (old_active_eps == 0 && tt_info->active_eps != 0) {
2271		if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2272			return -ENOMEM;
2273		return 0;
2274	}
2275	/* Not sure why we would have no new active endpoints...
2276	 *
2277	 * Maybe because of an Evaluate Context change for a hub update or a
2278	 * control endpoint 0 max packet size change?
2279	 * FIXME: skip the bandwidth calculation in that case.
2280	 */
2281	return 0;
2282}
2283
2284static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2285		struct xhci_virt_device *virt_dev)
2286{
2287	unsigned int bw_reserved;
2288
2289	bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2290	if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2291		return -ENOMEM;
2292
2293	bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2294	if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2295		return -ENOMEM;
2296
2297	return 0;
2298}
2299
2300/*
2301 * This algorithm is a very conservative estimate of the worst-case scheduling
2302 * scenario for any one interval.  The hardware dynamically schedules the
2303 * packets, so we can't tell which microframe could be the limiting factor in
2304 * the bandwidth scheduling.  This only takes into account periodic endpoints.
2305 *
2306 * Obviously, we can't solve an NP complete problem to find the minimum worst
2307 * case scenario.  Instead, we come up with an estimate that is no less than
2308 * the worst case bandwidth used for any one microframe, but may be an
2309 * over-estimate.
2310 *
2311 * We walk the requirements for each endpoint by interval, starting with the
2312 * smallest interval, and place packets in the schedule where there is only one
2313 * possible way to schedule packets for that interval.  In order to simplify
2314 * this algorithm, we record the largest max packet size for each interval, and
2315 * assume all packets will be that size.
2316 *
2317 * For interval 0, we obviously must schedule all packets for each interval.
2318 * The bandwidth for interval 0 is just the amount of data to be transmitted
2319 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2320 * the number of packets).
2321 *
2322 * For interval 1, we have two possible microframes to schedule those packets
2323 * in.  For this algorithm, if we can schedule the same number of packets for
2324 * each possible scheduling opportunity (each microframe), we will do so.  The
2325 * remaining number of packets will be saved to be transmitted in the gaps in
2326 * the next interval's scheduling sequence.
2327 *
2328 * As we move those remaining packets to be scheduled with interval 2 packets,
2329 * we have to double the number of remaining packets to transmit.  This is
2330 * because the intervals are actually powers of 2, and we would be transmitting
2331 * the previous interval's packets twice in this interval.  We also have to be
2332 * sure that when we look at the largest max packet size for this interval, we
2333 * also look at the largest max packet size for the remaining packets and take
2334 * the greater of the two.
2335 *
2336 * The algorithm continues to evenly distribute packets in each scheduling
2337 * opportunity, and push the remaining packets out, until we get to the last
2338 * interval.  Then those packets and their associated overhead are just added
2339 * to the bandwidth used.
2340 */
2341static int xhci_check_bw_table(struct xhci_hcd *xhci,
2342		struct xhci_virt_device *virt_dev,
2343		int old_active_eps)
2344{
2345	unsigned int bw_reserved;
2346	unsigned int max_bandwidth;
2347	unsigned int bw_used;
2348	unsigned int block_size;
2349	struct xhci_interval_bw_table *bw_table;
2350	unsigned int packet_size = 0;
2351	unsigned int overhead = 0;
2352	unsigned int packets_transmitted = 0;
2353	unsigned int packets_remaining = 0;
2354	unsigned int i;
2355
2356	if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2357		return xhci_check_ss_bw(xhci, virt_dev);
2358
2359	if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2360		max_bandwidth = HS_BW_LIMIT;
2361		/* Convert percent of bus BW reserved to blocks reserved */
2362		bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2363	} else {
2364		max_bandwidth = FS_BW_LIMIT;
2365		bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2366	}
2367
2368	bw_table = virt_dev->bw_table;
2369	/* We need to translate the max packet size and max ESIT payloads into
2370	 * the units the hardware uses.
2371	 */
2372	block_size = xhci_get_block_size(virt_dev->udev);
2373
2374	/* If we are manipulating a LS/FS device under a HS hub, double check
2375	 * that the HS bus has enough bandwidth if we are activing a new TT.
2376	 */
2377	if (virt_dev->tt_info) {
2378		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2379				"Recalculating BW for rootport %u",
2380				virt_dev->real_port);
2381		if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2382			xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2383					"newly activated TT.\n");
2384			return -ENOMEM;
2385		}
2386		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2387				"Recalculating BW for TT slot %u port %u",
2388				virt_dev->tt_info->slot_id,
2389				virt_dev->tt_info->ttport);
2390	} else {
2391		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2392				"Recalculating BW for rootport %u",
2393				virt_dev->real_port);
2394	}
2395
2396	/* Add in how much bandwidth will be used for interval zero, or the
2397	 * rounded max ESIT payload + number of packets * largest overhead.
2398	 */
2399	bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2400		bw_table->interval_bw[0].num_packets *
2401		xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2402
2403	for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2404		unsigned int bw_added;
2405		unsigned int largest_mps;
2406		unsigned int interval_overhead;
2407
2408		/*
2409		 * How many packets could we transmit in this interval?
2410		 * If packets didn't fit in the previous interval, we will need
2411		 * to transmit that many packets twice within this interval.
2412		 */
2413		packets_remaining = 2 * packets_remaining +
2414			bw_table->interval_bw[i].num_packets;
2415
2416		/* Find the largest max packet size of this or the previous
2417		 * interval.
2418		 */
2419		if (list_empty(&bw_table->interval_bw[i].endpoints))
2420			largest_mps = 0;
2421		else {
2422			struct xhci_virt_ep *virt_ep;
2423			struct list_head *ep_entry;
2424
2425			ep_entry = bw_table->interval_bw[i].endpoints.next;
2426			virt_ep = list_entry(ep_entry,
2427					struct xhci_virt_ep, bw_endpoint_list);
2428			/* Convert to blocks, rounding up */
2429			largest_mps = DIV_ROUND_UP(
2430					virt_ep->bw_info.max_packet_size,
2431					block_size);
2432		}
2433		if (largest_mps > packet_size)
2434			packet_size = largest_mps;
2435
2436		/* Use the larger overhead of this or the previous interval. */
2437		interval_overhead = xhci_get_largest_overhead(
2438				&bw_table->interval_bw[i]);
2439		if (interval_overhead > overhead)
2440			overhead = interval_overhead;
2441
2442		/* How many packets can we evenly distribute across
2443		 * (1 << (i + 1)) possible scheduling opportunities?
2444		 */
2445		packets_transmitted = packets_remaining >> (i + 1);
2446
2447		/* Add in the bandwidth used for those scheduled packets */
2448		bw_added = packets_transmitted * (overhead + packet_size);
2449
2450		/* How many packets do we have remaining to transmit? */
2451		packets_remaining = packets_remaining % (1 << (i + 1));
2452
2453		/* What largest max packet size should those packets have? */
2454		/* If we've transmitted all packets, don't carry over the
2455		 * largest packet size.
2456		 */
2457		if (packets_remaining == 0) {
2458			packet_size = 0;
2459			overhead = 0;
2460		} else if (packets_transmitted > 0) {
2461			/* Otherwise if we do have remaining packets, and we've
2462			 * scheduled some packets in this interval, take the
2463			 * largest max packet size from endpoints with this
2464			 * interval.
2465			 */
2466			packet_size = largest_mps;
2467			overhead = interval_overhead;
2468		}
2469		/* Otherwise carry over packet_size and overhead from the last
2470		 * time we had a remainder.
2471		 */
2472		bw_used += bw_added;
2473		if (bw_used > max_bandwidth) {
2474			xhci_warn(xhci, "Not enough bandwidth. "
2475					"Proposed: %u, Max: %u\n",
2476				bw_used, max_bandwidth);
2477			return -ENOMEM;
2478		}
2479	}
2480	/*
2481	 * Ok, we know we have some packets left over after even-handedly
2482	 * scheduling interval 15.  We don't know which microframes they will
2483	 * fit into, so we over-schedule and say they will be scheduled every
2484	 * microframe.
2485	 */
2486	if (packets_remaining > 0)
2487		bw_used += overhead + packet_size;
2488
2489	if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2490		unsigned int port_index = virt_dev->real_port - 1;
2491
2492		/* OK, we're manipulating a HS device attached to a
2493		 * root port bandwidth domain.  Include the number of active TTs
2494		 * in the bandwidth used.
2495		 */
2496		bw_used += TT_HS_OVERHEAD *
2497			xhci->rh_bw[port_index].num_active_tts;
2498	}
2499
2500	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2501		"Final bandwidth: %u, Limit: %u, Reserved: %u, "
2502		"Available: %u " "percent",
2503		bw_used, max_bandwidth, bw_reserved,
2504		(max_bandwidth - bw_used - bw_reserved) * 100 /
2505		max_bandwidth);
2506
2507	bw_used += bw_reserved;
2508	if (bw_used > max_bandwidth) {
2509		xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2510				bw_used, max_bandwidth);
2511		return -ENOMEM;
2512	}
2513
2514	bw_table->bw_used = bw_used;
2515	return 0;
2516}
2517
2518static bool xhci_is_async_ep(unsigned int ep_type)
2519{
2520	return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2521					ep_type != ISOC_IN_EP &&
2522					ep_type != INT_IN_EP);
2523}
2524
2525static bool xhci_is_sync_in_ep(unsigned int ep_type)
2526{
2527	return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2528}
2529
2530static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2531{
2532	unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2533
2534	if (ep_bw->ep_interval == 0)
2535		return SS_OVERHEAD_BURST +
2536			(ep_bw->mult * ep_bw->num_packets *
2537					(SS_OVERHEAD + mps));
2538	return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2539				(SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2540				1 << ep_bw->ep_interval);
2541
2542}
2543
2544static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2545		struct xhci_bw_info *ep_bw,
2546		struct xhci_interval_bw_table *bw_table,
2547		struct usb_device *udev,
2548		struct xhci_virt_ep *virt_ep,
2549		struct xhci_tt_bw_info *tt_info)
2550{
2551	struct xhci_interval_bw	*interval_bw;
2552	int normalized_interval;
2553
2554	if (xhci_is_async_ep(ep_bw->type))
2555		return;
2556
2557	if (udev->speed >= USB_SPEED_SUPER) {
2558		if (xhci_is_sync_in_ep(ep_bw->type))
2559			xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2560				xhci_get_ss_bw_consumed(ep_bw);
2561		else
2562			xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2563				xhci_get_ss_bw_consumed(ep_bw);
2564		return;
2565	}
2566
2567	/* SuperSpeed endpoints never get added to intervals in the table, so
2568	 * this check is only valid for HS/FS/LS devices.
2569	 */
2570	if (list_empty(&virt_ep->bw_endpoint_list))
2571		return;
2572	/* For LS/FS devices, we need to translate the interval expressed in
2573	 * microframes to frames.
2574	 */
2575	if (udev->speed == USB_SPEED_HIGH)
2576		normalized_interval = ep_bw->ep_interval;
2577	else
2578		normalized_interval = ep_bw->ep_interval - 3;
2579
2580	if (normalized_interval == 0)
2581		bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2582	interval_bw = &bw_table->interval_bw[normalized_interval];
2583	interval_bw->num_packets -= ep_bw->num_packets;
2584	switch (udev->speed) {
2585	case USB_SPEED_LOW:
2586		interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2587		break;
2588	case USB_SPEED_FULL:
2589		interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2590		break;
2591	case USB_SPEED_HIGH:
2592		interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2593		break;
2594	default:
 
 
2595		/* Should never happen because only LS/FS/HS endpoints will get
2596		 * added to the endpoint list.
2597		 */
2598		return;
2599	}
2600	if (tt_info)
2601		tt_info->active_eps -= 1;
2602	list_del_init(&virt_ep->bw_endpoint_list);
2603}
2604
2605static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2606		struct xhci_bw_info *ep_bw,
2607		struct xhci_interval_bw_table *bw_table,
2608		struct usb_device *udev,
2609		struct xhci_virt_ep *virt_ep,
2610		struct xhci_tt_bw_info *tt_info)
2611{
2612	struct xhci_interval_bw	*interval_bw;
2613	struct xhci_virt_ep *smaller_ep;
2614	int normalized_interval;
2615
2616	if (xhci_is_async_ep(ep_bw->type))
2617		return;
2618
2619	if (udev->speed == USB_SPEED_SUPER) {
2620		if (xhci_is_sync_in_ep(ep_bw->type))
2621			xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2622				xhci_get_ss_bw_consumed(ep_bw);
2623		else
2624			xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2625				xhci_get_ss_bw_consumed(ep_bw);
2626		return;
2627	}
2628
2629	/* For LS/FS devices, we need to translate the interval expressed in
2630	 * microframes to frames.
2631	 */
2632	if (udev->speed == USB_SPEED_HIGH)
2633		normalized_interval = ep_bw->ep_interval;
2634	else
2635		normalized_interval = ep_bw->ep_interval - 3;
2636
2637	if (normalized_interval == 0)
2638		bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2639	interval_bw = &bw_table->interval_bw[normalized_interval];
2640	interval_bw->num_packets += ep_bw->num_packets;
2641	switch (udev->speed) {
2642	case USB_SPEED_LOW:
2643		interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2644		break;
2645	case USB_SPEED_FULL:
2646		interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2647		break;
2648	case USB_SPEED_HIGH:
2649		interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2650		break;
2651	default:
 
 
2652		/* Should never happen because only LS/FS/HS endpoints will get
2653		 * added to the endpoint list.
2654		 */
2655		return;
2656	}
2657
2658	if (tt_info)
2659		tt_info->active_eps += 1;
2660	/* Insert the endpoint into the list, largest max packet size first. */
2661	list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2662			bw_endpoint_list) {
2663		if (ep_bw->max_packet_size >=
2664				smaller_ep->bw_info.max_packet_size) {
2665			/* Add the new ep before the smaller endpoint */
2666			list_add_tail(&virt_ep->bw_endpoint_list,
2667					&smaller_ep->bw_endpoint_list);
2668			return;
2669		}
2670	}
2671	/* Add the new endpoint at the end of the list. */
2672	list_add_tail(&virt_ep->bw_endpoint_list,
2673			&interval_bw->endpoints);
2674}
2675
2676void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2677		struct xhci_virt_device *virt_dev,
2678		int old_active_eps)
2679{
2680	struct xhci_root_port_bw_info *rh_bw_info;
2681	if (!virt_dev->tt_info)
2682		return;
2683
2684	rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2685	if (old_active_eps == 0 &&
2686				virt_dev->tt_info->active_eps != 0) {
2687		rh_bw_info->num_active_tts += 1;
2688		rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2689	} else if (old_active_eps != 0 &&
2690				virt_dev->tt_info->active_eps == 0) {
2691		rh_bw_info->num_active_tts -= 1;
2692		rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2693	}
2694}
2695
2696static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2697		struct xhci_virt_device *virt_dev,
2698		struct xhci_container_ctx *in_ctx)
2699{
2700	struct xhci_bw_info ep_bw_info[31];
2701	int i;
2702	struct xhci_input_control_ctx *ctrl_ctx;
2703	int old_active_eps = 0;
2704
2705	if (virt_dev->tt_info)
2706		old_active_eps = virt_dev->tt_info->active_eps;
2707
2708	ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2709	if (!ctrl_ctx) {
2710		xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2711				__func__);
2712		return -ENOMEM;
2713	}
2714
2715	for (i = 0; i < 31; i++) {
2716		if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2717			continue;
2718
2719		/* Make a copy of the BW info in case we need to revert this */
2720		memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2721				sizeof(ep_bw_info[i]));
2722		/* Drop the endpoint from the interval table if the endpoint is
2723		 * being dropped or changed.
2724		 */
2725		if (EP_IS_DROPPED(ctrl_ctx, i))
2726			xhci_drop_ep_from_interval_table(xhci,
2727					&virt_dev->eps[i].bw_info,
2728					virt_dev->bw_table,
2729					virt_dev->udev,
2730					&virt_dev->eps[i],
2731					virt_dev->tt_info);
2732	}
2733	/* Overwrite the information stored in the endpoints' bw_info */
2734	xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2735	for (i = 0; i < 31; i++) {
2736		/* Add any changed or added endpoints to the interval table */
2737		if (EP_IS_ADDED(ctrl_ctx, i))
2738			xhci_add_ep_to_interval_table(xhci,
2739					&virt_dev->eps[i].bw_info,
2740					virt_dev->bw_table,
2741					virt_dev->udev,
2742					&virt_dev->eps[i],
2743					virt_dev->tt_info);
2744	}
2745
2746	if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2747		/* Ok, this fits in the bandwidth we have.
2748		 * Update the number of active TTs.
2749		 */
2750		xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2751		return 0;
2752	}
2753
2754	/* We don't have enough bandwidth for this, revert the stored info. */
2755	for (i = 0; i < 31; i++) {
2756		if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2757			continue;
2758
2759		/* Drop the new copies of any added or changed endpoints from
2760		 * the interval table.
2761		 */
2762		if (EP_IS_ADDED(ctrl_ctx, i)) {
2763			xhci_drop_ep_from_interval_table(xhci,
2764					&virt_dev->eps[i].bw_info,
2765					virt_dev->bw_table,
2766					virt_dev->udev,
2767					&virt_dev->eps[i],
2768					virt_dev->tt_info);
2769		}
2770		/* Revert the endpoint back to its old information */
2771		memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2772				sizeof(ep_bw_info[i]));
2773		/* Add any changed or dropped endpoints back into the table */
2774		if (EP_IS_DROPPED(ctrl_ctx, i))
2775			xhci_add_ep_to_interval_table(xhci,
2776					&virt_dev->eps[i].bw_info,
2777					virt_dev->bw_table,
2778					virt_dev->udev,
2779					&virt_dev->eps[i],
2780					virt_dev->tt_info);
2781	}
2782	return -ENOMEM;
2783}
2784
2785
2786/* Issue a configure endpoint command or evaluate context command
2787 * and wait for it to finish.
2788 */
2789static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2790		struct usb_device *udev,
2791		struct xhci_command *command,
2792		bool ctx_change, bool must_succeed)
2793{
2794	int ret;
 
2795	unsigned long flags;
 
2796	struct xhci_input_control_ctx *ctrl_ctx;
 
 
2797	struct xhci_virt_device *virt_dev;
2798	struct xhci_slot_ctx *slot_ctx;
2799
2800	if (!command)
2801		return -EINVAL;
2802
2803	spin_lock_irqsave(&xhci->lock, flags);
2804
2805	if (xhci->xhc_state & XHCI_STATE_DYING) {
2806		spin_unlock_irqrestore(&xhci->lock, flags);
2807		return -ESHUTDOWN;
2808	}
2809
2810	virt_dev = xhci->devs[udev->slot_id];
2811
2812	ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
 
 
 
 
2813	if (!ctrl_ctx) {
2814		spin_unlock_irqrestore(&xhci->lock, flags);
2815		xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2816				__func__);
2817		return -ENOMEM;
2818	}
2819
2820	if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2821			xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2822		spin_unlock_irqrestore(&xhci->lock, flags);
2823		xhci_warn(xhci, "Not enough host resources, "
2824				"active endpoint contexts = %u\n",
2825				xhci->num_active_eps);
2826		return -ENOMEM;
2827	}
2828	if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2829	    xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2830		if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2831			xhci_free_host_resources(xhci, ctrl_ctx);
2832		spin_unlock_irqrestore(&xhci->lock, flags);
2833		xhci_warn(xhci, "Not enough bandwidth\n");
2834		return -ENOMEM;
2835	}
2836
2837	slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2838
2839	trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2840	trace_xhci_configure_endpoint(slot_ctx);
 
 
 
 
 
 
2841
 
2842	if (!ctx_change)
2843		ret = xhci_queue_configure_endpoint(xhci, command,
2844				command->in_ctx->dma,
2845				udev->slot_id, must_succeed);
2846	else
2847		ret = xhci_queue_evaluate_context(xhci, command,
2848				command->in_ctx->dma,
2849				udev->slot_id, must_succeed);
2850	if (ret < 0) {
 
 
2851		if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2852			xhci_free_host_resources(xhci, ctrl_ctx);
2853		spin_unlock_irqrestore(&xhci->lock, flags);
2854		xhci_dbg_trace(xhci,  trace_xhci_dbg_context_change,
2855				"FIXME allocate a new ring segment");
2856		return -ENOMEM;
2857	}
2858	xhci_ring_cmd_db(xhci);
2859	spin_unlock_irqrestore(&xhci->lock, flags);
2860
2861	/* Wait for the configure endpoint command to complete */
2862	wait_for_completion(command->completion);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2863
2864	if (!ctx_change)
2865		ret = xhci_configure_endpoint_result(xhci, udev,
2866						     &command->status);
2867	else
2868		ret = xhci_evaluate_context_result(xhci, udev,
2869						   &command->status);
2870
2871	if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2872		spin_lock_irqsave(&xhci->lock, flags);
2873		/* If the command failed, remove the reserved resources.
2874		 * Otherwise, clean up the estimate to include dropped eps.
2875		 */
2876		if (ret)
2877			xhci_free_host_resources(xhci, ctrl_ctx);
2878		else
2879			xhci_finish_resource_reservation(xhci, ctrl_ctx);
2880		spin_unlock_irqrestore(&xhci->lock, flags);
2881	}
2882	return ret;
2883}
2884
2885static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2886	struct xhci_virt_device *vdev, int i)
2887{
2888	struct xhci_virt_ep *ep = &vdev->eps[i];
2889
2890	if (ep->ep_state & EP_HAS_STREAMS) {
2891		xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2892				xhci_get_endpoint_address(i));
2893		xhci_free_stream_info(xhci, ep->stream_info);
2894		ep->stream_info = NULL;
2895		ep->ep_state &= ~EP_HAS_STREAMS;
2896	}
2897}
2898
2899/* Called after one or more calls to xhci_add_endpoint() or
2900 * xhci_drop_endpoint().  If this call fails, the USB core is expected
2901 * to call xhci_reset_bandwidth().
2902 *
2903 * Since we are in the middle of changing either configuration or
2904 * installing a new alt setting, the USB core won't allow URBs to be
2905 * enqueued for any endpoint on the old config or interface.  Nothing
2906 * else should be touching the xhci->devs[slot_id] structure, so we
2907 * don't need to take the xhci->lock for manipulating that.
2908 */
2909int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2910{
2911	int i;
2912	int ret = 0;
2913	struct xhci_hcd *xhci;
2914	struct xhci_virt_device	*virt_dev;
2915	struct xhci_input_control_ctx *ctrl_ctx;
2916	struct xhci_slot_ctx *slot_ctx;
2917	struct xhci_command *command;
2918
2919	ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2920	if (ret <= 0)
2921		return ret;
2922	xhci = hcd_to_xhci(hcd);
2923	if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2924		(xhci->xhc_state & XHCI_STATE_REMOVING))
2925		return -ENODEV;
2926
2927	xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2928	virt_dev = xhci->devs[udev->slot_id];
2929
2930	command = xhci_alloc_command(xhci, true, GFP_KERNEL);
2931	if (!command)
2932		return -ENOMEM;
2933
2934	command->in_ctx = virt_dev->in_ctx;
2935
2936	/* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2937	ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2938	if (!ctrl_ctx) {
2939		xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2940				__func__);
2941		ret = -ENOMEM;
2942		goto command_cleanup;
2943	}
2944	ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2945	ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2946	ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2947
2948	/* Don't issue the command if there's no endpoints to update. */
2949	if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2950	    ctrl_ctx->drop_flags == 0) {
2951		ret = 0;
2952		goto command_cleanup;
2953	}
2954	/* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2955	slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2956	for (i = 31; i >= 1; i--) {
2957		__le32 le32 = cpu_to_le32(BIT(i));
2958
2959		if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2960		    || (ctrl_ctx->add_flags & le32) || i == 1) {
2961			slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2962			slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2963			break;
2964		}
2965	}
2966
2967	ret = xhci_configure_endpoint(xhci, udev, command,
2968			false, false);
2969	if (ret)
2970		/* Callee should call reset_bandwidth() */
2971		goto command_cleanup;
 
 
 
 
 
2972
2973	/* Free any rings that were dropped, but not changed. */
2974	for (i = 1; i < 31; i++) {
2975		if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2976		    !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2977			xhci_free_endpoint_ring(xhci, virt_dev, i);
2978			xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2979		}
2980	}
2981	xhci_zero_in_ctx(xhci, virt_dev);
2982	/*
2983	 * Install any rings for completely new endpoints or changed endpoints,
2984	 * and free any old rings from changed endpoints.
2985	 */
2986	for (i = 1; i < 31; i++) {
2987		if (!virt_dev->eps[i].new_ring)
2988			continue;
2989		/* Only free the old ring if it exists.
2990		 * It may not if this is the first add of an endpoint.
2991		 */
2992		if (virt_dev->eps[i].ring) {
2993			xhci_free_endpoint_ring(xhci, virt_dev, i);
2994		}
2995		xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2996		virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2997		virt_dev->eps[i].new_ring = NULL;
2998		xhci_debugfs_create_endpoint(xhci, virt_dev, i);
2999	}
3000command_cleanup:
3001	kfree(command->completion);
3002	kfree(command);
3003
3004	return ret;
3005}
3006EXPORT_SYMBOL_GPL(xhci_check_bandwidth);
3007
3008void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3009{
3010	struct xhci_hcd *xhci;
3011	struct xhci_virt_device	*virt_dev;
3012	int i, ret;
3013
3014	ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3015	if (ret <= 0)
3016		return;
3017	xhci = hcd_to_xhci(hcd);
3018
3019	xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3020	virt_dev = xhci->devs[udev->slot_id];
3021	/* Free any rings allocated for added endpoints */
3022	for (i = 0; i < 31; i++) {
3023		if (virt_dev->eps[i].new_ring) {
3024			xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3025			xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
3026			virt_dev->eps[i].new_ring = NULL;
3027		}
3028	}
3029	xhci_zero_in_ctx(xhci, virt_dev);
3030}
3031EXPORT_SYMBOL_GPL(xhci_reset_bandwidth);
3032
3033static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
3034		struct xhci_container_ctx *in_ctx,
3035		struct xhci_container_ctx *out_ctx,
3036		struct xhci_input_control_ctx *ctrl_ctx,
3037		u32 add_flags, u32 drop_flags)
3038{
3039	ctrl_ctx->add_flags = cpu_to_le32(add_flags);
3040	ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
3041	xhci_slot_copy(xhci, in_ctx, out_ctx);
3042	ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
 
 
 
3043}
3044
3045static void xhci_endpoint_disable(struct usb_hcd *hcd,
3046				  struct usb_host_endpoint *host_ep)
 
3047{
3048	struct xhci_hcd		*xhci;
3049	struct xhci_virt_device	*vdev;
3050	struct xhci_virt_ep	*ep;
3051	struct usb_device	*udev;
3052	unsigned long		flags;
3053	unsigned int		ep_index;
3054
3055	xhci = hcd_to_xhci(hcd);
3056rescan:
3057	spin_lock_irqsave(&xhci->lock, flags);
 
 
 
 
3058
3059	udev = (struct usb_device *)host_ep->hcpriv;
3060	if (!udev || !udev->slot_id)
3061		goto done;
 
 
 
 
 
 
 
 
 
 
 
3062
3063	vdev = xhci->devs[udev->slot_id];
3064	if (!vdev)
3065		goto done;
 
 
3066
3067	ep_index = xhci_get_endpoint_index(&host_ep->desc);
3068	ep = &vdev->eps[ep_index];
 
 
 
3069
3070	/* wait for hub_tt_work to finish clearing hub TT */
3071	if (ep->ep_state & EP_CLEARING_TT) {
3072		spin_unlock_irqrestore(&xhci->lock, flags);
3073		schedule_timeout_uninterruptible(1);
3074		goto rescan;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
3075	}
3076
3077	if (ep->ep_state)
3078		xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3079			 ep->ep_state);
3080done:
3081	host_ep->hcpriv = NULL;
3082	spin_unlock_irqrestore(&xhci->lock, flags);
3083}
3084
3085/*
3086 * Called after usb core issues a clear halt control message.
3087 * The host side of the halt should already be cleared by a reset endpoint
3088 * command issued when the STALL event was received.
3089 *
3090 * The reset endpoint command may only be issued to endpoints in the halted
3091 * state. For software that wishes to reset the data toggle or sequence number
3092 * of an endpoint that isn't in the halted state this function will issue a
3093 * configure endpoint command with the Drop and Add bits set for the target
3094 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3095 *
3096 * vdev may be lost due to xHC restore error and re-initialization during S3/S4
3097 * resume. A new vdev will be allocated later by xhci_discover_or_reset_device()
3098 */
3099
3100static void xhci_endpoint_reset(struct usb_hcd *hcd,
3101		struct usb_host_endpoint *host_ep)
3102{
3103	struct xhci_hcd *xhci;
3104	struct usb_device *udev;
3105	struct xhci_virt_device *vdev;
3106	struct xhci_virt_ep *ep;
3107	struct xhci_input_control_ctx *ctrl_ctx;
3108	struct xhci_command *stop_cmd, *cfg_cmd;
3109	unsigned int ep_index;
3110	unsigned long flags;
3111	u32 ep_flag;
3112	int err;
3113
3114	xhci = hcd_to_xhci(hcd);
3115	ep_index = xhci_get_endpoint_index(&host_ep->desc);
3116
3117	/*
3118	 * Usb core assumes a max packet value for ep0 on FS devices until the
3119	 * real value is read from the descriptor. Core resets Ep0 if values
3120	 * mismatch. Reconfigure the xhci ep0 endpoint context here in that case
3121	 */
3122	if (usb_endpoint_xfer_control(&host_ep->desc) && ep_index == 0) {
3123
3124		udev = container_of(host_ep, struct usb_device, ep0);
3125		if (udev->speed != USB_SPEED_FULL || !udev->slot_id)
3126			return;
3127
3128		vdev = xhci->devs[udev->slot_id];
3129		if (!vdev || vdev->udev != udev)
3130			return;
3131
3132		xhci_check_ep0_maxpacket(xhci, vdev);
3133
3134		/* Nothing else should be done here for ep0 during ep reset */
3135		return;
3136	}
3137
3138	if (!host_ep->hcpriv)
3139		return;
3140	udev = (struct usb_device *) host_ep->hcpriv;
3141	vdev = xhci->devs[udev->slot_id];
3142
3143	if (!udev->slot_id || !vdev)
3144		return;
3145
3146	ep = &vdev->eps[ep_index];
3147
3148	/* Bail out if toggle is already being cleared by a endpoint reset */
3149	spin_lock_irqsave(&xhci->lock, flags);
3150	if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3151		ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3152		spin_unlock_irqrestore(&xhci->lock, flags);
3153		return;
3154	}
3155	spin_unlock_irqrestore(&xhci->lock, flags);
3156	/* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3157	if (usb_endpoint_xfer_control(&host_ep->desc) ||
3158	    usb_endpoint_xfer_isoc(&host_ep->desc))
3159		return;
3160
3161	ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3162
3163	if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3164		return;
3165
3166	stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3167	if (!stop_cmd)
3168		return;
 
3169
3170	cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3171	if (!cfg_cmd)
3172		goto cleanup;
3173
3174	spin_lock_irqsave(&xhci->lock, flags);
3175
3176	/* block queuing new trbs and ringing ep doorbell */
3177	ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3178
3179	/*
3180	 * Make sure endpoint ring is empty before resetting the toggle/seq.
3181	 * Driver is required to synchronously cancel all transfer request.
3182	 * Stop the endpoint to force xHC to update the output context
3183	 */
3184
3185	if (!list_empty(&ep->ring->td_list)) {
3186		dev_err(&udev->dev, "EP not empty, refuse reset\n");
3187		spin_unlock_irqrestore(&xhci->lock, flags);
3188		xhci_free_command(xhci, cfg_cmd);
3189		goto cleanup;
3190	}
3191
3192	err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3193					ep_index, 0);
3194	if (err < 0) {
3195		spin_unlock_irqrestore(&xhci->lock, flags);
3196		xhci_free_command(xhci, cfg_cmd);
3197		xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3198				__func__, err);
3199		goto cleanup;
3200	}
3201
3202	xhci_ring_cmd_db(xhci);
3203	spin_unlock_irqrestore(&xhci->lock, flags);
3204
3205	wait_for_completion(stop_cmd->completion);
3206
3207	spin_lock_irqsave(&xhci->lock, flags);
3208
3209	/* config ep command clears toggle if add and drop ep flags are set */
3210	ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3211	if (!ctrl_ctx) {
3212		spin_unlock_irqrestore(&xhci->lock, flags);
3213		xhci_free_command(xhci, cfg_cmd);
3214		xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3215				__func__);
3216		goto cleanup;
3217	}
3218
3219	xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3220					   ctrl_ctx, ep_flag, ep_flag);
3221	xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3222
3223	err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3224				      udev->slot_id, false);
3225	if (err < 0) {
3226		spin_unlock_irqrestore(&xhci->lock, flags);
3227		xhci_free_command(xhci, cfg_cmd);
3228		xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3229				__func__, err);
3230		goto cleanup;
3231	}
3232
3233	xhci_ring_cmd_db(xhci);
3234	spin_unlock_irqrestore(&xhci->lock, flags);
3235
3236	wait_for_completion(cfg_cmd->completion);
3237
3238	xhci_free_command(xhci, cfg_cmd);
3239cleanup:
3240	xhci_free_command(xhci, stop_cmd);
3241	spin_lock_irqsave(&xhci->lock, flags);
3242	if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
3243		ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3244	spin_unlock_irqrestore(&xhci->lock, flags);
3245}
3246
3247static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3248		struct usb_device *udev, struct usb_host_endpoint *ep,
3249		unsigned int slot_id)
3250{
3251	int ret;
3252	unsigned int ep_index;
3253	unsigned int ep_state;
3254
3255	if (!ep)
3256		return -EINVAL;
3257	ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3258	if (ret <= 0)
3259		return ret ? ret : -EINVAL;
3260	if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3261		xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3262				" descriptor for ep 0x%x does not support streams\n",
3263				ep->desc.bEndpointAddress);
3264		return -EINVAL;
3265	}
3266
3267	ep_index = xhci_get_endpoint_index(&ep->desc);
3268	ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3269	if (ep_state & EP_HAS_STREAMS ||
3270			ep_state & EP_GETTING_STREAMS) {
3271		xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3272				"already has streams set up.\n",
3273				ep->desc.bEndpointAddress);
3274		xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3275				"dynamic stream context array reallocation.\n");
3276		return -EINVAL;
3277	}
3278	if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3279		xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3280				"endpoint 0x%x; URBs are pending.\n",
3281				ep->desc.bEndpointAddress);
3282		return -EINVAL;
3283	}
3284	return 0;
3285}
3286
3287static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3288		unsigned int *num_streams, unsigned int *num_stream_ctxs)
3289{
3290	unsigned int max_streams;
3291
3292	/* The stream context array size must be a power of two */
3293	*num_stream_ctxs = roundup_pow_of_two(*num_streams);
3294	/*
3295	 * Find out how many primary stream array entries the host controller
3296	 * supports.  Later we may use secondary stream arrays (similar to 2nd
3297	 * level page entries), but that's an optional feature for xHCI host
3298	 * controllers. xHCs must support at least 4 stream IDs.
3299	 */
3300	max_streams = HCC_MAX_PSA(xhci->hcc_params);
3301	if (*num_stream_ctxs > max_streams) {
3302		xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3303				max_streams);
3304		*num_stream_ctxs = max_streams;
3305		*num_streams = max_streams;
3306	}
3307}
3308
3309/* Returns an error code if one of the endpoint already has streams.
3310 * This does not change any data structures, it only checks and gathers
3311 * information.
3312 */
3313static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3314		struct usb_device *udev,
3315		struct usb_host_endpoint **eps, unsigned int num_eps,
3316		unsigned int *num_streams, u32 *changed_ep_bitmask)
3317{
3318	unsigned int max_streams;
3319	unsigned int endpoint_flag;
3320	int i;
3321	int ret;
3322
3323	for (i = 0; i < num_eps; i++) {
3324		ret = xhci_check_streams_endpoint(xhci, udev,
3325				eps[i], udev->slot_id);
3326		if (ret < 0)
3327			return ret;
3328
3329		max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3330		if (max_streams < (*num_streams - 1)) {
3331			xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3332					eps[i]->desc.bEndpointAddress,
3333					max_streams);
3334			*num_streams = max_streams+1;
3335		}
3336
3337		endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3338		if (*changed_ep_bitmask & endpoint_flag)
3339			return -EINVAL;
3340		*changed_ep_bitmask |= endpoint_flag;
3341	}
3342	return 0;
3343}
3344
3345static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3346		struct usb_device *udev,
3347		struct usb_host_endpoint **eps, unsigned int num_eps)
3348{
3349	u32 changed_ep_bitmask = 0;
3350	unsigned int slot_id;
3351	unsigned int ep_index;
3352	unsigned int ep_state;
3353	int i;
3354
3355	slot_id = udev->slot_id;
3356	if (!xhci->devs[slot_id])
3357		return 0;
3358
3359	for (i = 0; i < num_eps; i++) {
3360		ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3361		ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3362		/* Are streams already being freed for the endpoint? */
3363		if (ep_state & EP_GETTING_NO_STREAMS) {
3364			xhci_warn(xhci, "WARN Can't disable streams for "
3365					"endpoint 0x%x, "
3366					"streams are being disabled already\n",
3367					eps[i]->desc.bEndpointAddress);
3368			return 0;
3369		}
3370		/* Are there actually any streams to free? */
3371		if (!(ep_state & EP_HAS_STREAMS) &&
3372				!(ep_state & EP_GETTING_STREAMS)) {
3373			xhci_warn(xhci, "WARN Can't disable streams for "
3374					"endpoint 0x%x, "
3375					"streams are already disabled!\n",
3376					eps[i]->desc.bEndpointAddress);
3377			xhci_warn(xhci, "WARN xhci_free_streams() called "
3378					"with non-streams endpoint\n");
3379			return 0;
3380		}
3381		changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3382	}
3383	return changed_ep_bitmask;
3384}
3385
3386/*
3387 * The USB device drivers use this function (through the HCD interface in USB
3388 * core) to prepare a set of bulk endpoints to use streams.  Streams are used to
3389 * coordinate mass storage command queueing across multiple endpoints (basically
3390 * a stream ID == a task ID).
3391 *
3392 * Setting up streams involves allocating the same size stream context array
3393 * for each endpoint and issuing a configure endpoint command for all endpoints.
3394 *
3395 * Don't allow the call to succeed if one endpoint only supports one stream
3396 * (which means it doesn't support streams at all).
3397 *
3398 * Drivers may get less stream IDs than they asked for, if the host controller
3399 * hardware or endpoints claim they can't support the number of requested
3400 * stream IDs.
3401 */
3402static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3403		struct usb_host_endpoint **eps, unsigned int num_eps,
3404		unsigned int num_streams, gfp_t mem_flags)
3405{
3406	int i, ret;
3407	struct xhci_hcd *xhci;
3408	struct xhci_virt_device *vdev;
3409	struct xhci_command *config_cmd;
3410	struct xhci_input_control_ctx *ctrl_ctx;
3411	unsigned int ep_index;
3412	unsigned int num_stream_ctxs;
3413	unsigned int max_packet;
3414	unsigned long flags;
3415	u32 changed_ep_bitmask = 0;
3416
3417	if (!eps)
3418		return -EINVAL;
3419
3420	/* Add one to the number of streams requested to account for
3421	 * stream 0 that is reserved for xHCI usage.
3422	 */
3423	num_streams += 1;
3424	xhci = hcd_to_xhci(hcd);
3425	xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3426			num_streams);
3427
3428	/* MaxPSASize value 0 (2 streams) means streams are not supported */
3429	if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3430			HCC_MAX_PSA(xhci->hcc_params) < 4) {
3431		xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3432		return -ENOSYS;
3433	}
3434
3435	config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3436	if (!config_cmd)
 
3437		return -ENOMEM;
3438
3439	ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3440	if (!ctrl_ctx) {
3441		xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3442				__func__);
3443		xhci_free_command(xhci, config_cmd);
3444		return -ENOMEM;
3445	}
3446
3447	/* Check to make sure all endpoints are not already configured for
3448	 * streams.  While we're at it, find the maximum number of streams that
3449	 * all the endpoints will support and check for duplicate endpoints.
3450	 */
3451	spin_lock_irqsave(&xhci->lock, flags);
3452	ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3453			num_eps, &num_streams, &changed_ep_bitmask);
3454	if (ret < 0) {
3455		xhci_free_command(xhci, config_cmd);
3456		spin_unlock_irqrestore(&xhci->lock, flags);
3457		return ret;
3458	}
3459	if (num_streams <= 1) {
3460		xhci_warn(xhci, "WARN: endpoints can't handle "
3461				"more than one stream.\n");
3462		xhci_free_command(xhci, config_cmd);
3463		spin_unlock_irqrestore(&xhci->lock, flags);
3464		return -EINVAL;
3465	}
3466	vdev = xhci->devs[udev->slot_id];
3467	/* Mark each endpoint as being in transition, so
3468	 * xhci_urb_enqueue() will reject all URBs.
3469	 */
3470	for (i = 0; i < num_eps; i++) {
3471		ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3472		vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3473	}
3474	spin_unlock_irqrestore(&xhci->lock, flags);
3475
3476	/* Setup internal data structures and allocate HW data structures for
3477	 * streams (but don't install the HW structures in the input context
3478	 * until we're sure all memory allocation succeeded).
3479	 */
3480	xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3481	xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3482			num_stream_ctxs, num_streams);
3483
3484	for (i = 0; i < num_eps; i++) {
3485		ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3486		max_packet = usb_endpoint_maxp(&eps[i]->desc);
3487		vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3488				num_stream_ctxs,
3489				num_streams,
3490				max_packet, mem_flags);
3491		if (!vdev->eps[ep_index].stream_info)
3492			goto cleanup;
3493		/* Set maxPstreams in endpoint context and update deq ptr to
3494		 * point to stream context array. FIXME
3495		 */
3496	}
3497
3498	/* Set up the input context for a configure endpoint command. */
3499	for (i = 0; i < num_eps; i++) {
3500		struct xhci_ep_ctx *ep_ctx;
3501
3502		ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3503		ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3504
3505		xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3506				vdev->out_ctx, ep_index);
3507		xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3508				vdev->eps[ep_index].stream_info);
3509	}
3510	/* Tell the HW to drop its old copy of the endpoint context info
3511	 * and add the updated copy from the input context.
3512	 */
3513	xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3514			vdev->out_ctx, ctrl_ctx,
3515			changed_ep_bitmask, changed_ep_bitmask);
3516
3517	/* Issue and wait for the configure endpoint command */
3518	ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3519			false, false);
3520
3521	/* xHC rejected the configure endpoint command for some reason, so we
3522	 * leave the old ring intact and free our internal streams data
3523	 * structure.
3524	 */
3525	if (ret < 0)
3526		goto cleanup;
3527
3528	spin_lock_irqsave(&xhci->lock, flags);
3529	for (i = 0; i < num_eps; i++) {
3530		ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3531		vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3532		xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3533			 udev->slot_id, ep_index);
3534		vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3535	}
3536	xhci_free_command(xhci, config_cmd);
3537	spin_unlock_irqrestore(&xhci->lock, flags);
3538
3539	for (i = 0; i < num_eps; i++) {
3540		ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3541		xhci_debugfs_create_stream_files(xhci, vdev, ep_index);
3542	}
3543	/* Subtract 1 for stream 0, which drivers can't use */
3544	return num_streams - 1;
3545
3546cleanup:
3547	/* If it didn't work, free the streams! */
3548	for (i = 0; i < num_eps; i++) {
3549		ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3550		xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3551		vdev->eps[ep_index].stream_info = NULL;
3552		/* FIXME Unset maxPstreams in endpoint context and
3553		 * update deq ptr to point to normal string ring.
3554		 */
3555		vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3556		vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3557		xhci_endpoint_zero(xhci, vdev, eps[i]);
3558	}
3559	xhci_free_command(xhci, config_cmd);
3560	return -ENOMEM;
3561}
3562
3563/* Transition the endpoint from using streams to being a "normal" endpoint
3564 * without streams.
3565 *
3566 * Modify the endpoint context state, submit a configure endpoint command,
3567 * and free all endpoint rings for streams if that completes successfully.
3568 */
3569static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3570		struct usb_host_endpoint **eps, unsigned int num_eps,
3571		gfp_t mem_flags)
3572{
3573	int i, ret;
3574	struct xhci_hcd *xhci;
3575	struct xhci_virt_device *vdev;
3576	struct xhci_command *command;
3577	struct xhci_input_control_ctx *ctrl_ctx;
3578	unsigned int ep_index;
3579	unsigned long flags;
3580	u32 changed_ep_bitmask;
3581
3582	xhci = hcd_to_xhci(hcd);
3583	vdev = xhci->devs[udev->slot_id];
3584
3585	/* Set up a configure endpoint command to remove the streams rings */
3586	spin_lock_irqsave(&xhci->lock, flags);
3587	changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3588			udev, eps, num_eps);
3589	if (changed_ep_bitmask == 0) {
3590		spin_unlock_irqrestore(&xhci->lock, flags);
3591		return -EINVAL;
3592	}
3593
3594	/* Use the xhci_command structure from the first endpoint.  We may have
3595	 * allocated too many, but the driver may call xhci_free_streams() for
3596	 * each endpoint it grouped into one call to xhci_alloc_streams().
3597	 */
3598	ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3599	command = vdev->eps[ep_index].stream_info->free_streams_command;
3600	ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3601	if (!ctrl_ctx) {
3602		spin_unlock_irqrestore(&xhci->lock, flags);
3603		xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3604				__func__);
3605		return -EINVAL;
3606	}
3607
3608	for (i = 0; i < num_eps; i++) {
3609		struct xhci_ep_ctx *ep_ctx;
3610
3611		ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3612		ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3613		xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3614			EP_GETTING_NO_STREAMS;
3615
3616		xhci_endpoint_copy(xhci, command->in_ctx,
3617				vdev->out_ctx, ep_index);
3618		xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3619				&vdev->eps[ep_index]);
3620	}
3621	xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3622			vdev->out_ctx, ctrl_ctx,
3623			changed_ep_bitmask, changed_ep_bitmask);
3624	spin_unlock_irqrestore(&xhci->lock, flags);
3625
3626	/* Issue and wait for the configure endpoint command,
3627	 * which must succeed.
3628	 */
3629	ret = xhci_configure_endpoint(xhci, udev, command,
3630			false, true);
3631
3632	/* xHC rejected the configure endpoint command for some reason, so we
3633	 * leave the streams rings intact.
3634	 */
3635	if (ret < 0)
3636		return ret;
3637
3638	spin_lock_irqsave(&xhci->lock, flags);
3639	for (i = 0; i < num_eps; i++) {
3640		ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3641		xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3642		vdev->eps[ep_index].stream_info = NULL;
3643		/* FIXME Unset maxPstreams in endpoint context and
3644		 * update deq ptr to point to normal string ring.
3645		 */
3646		vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3647		vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3648	}
3649	spin_unlock_irqrestore(&xhci->lock, flags);
3650
3651	return 0;
3652}
3653
3654/*
3655 * Deletes endpoint resources for endpoints that were active before a Reset
3656 * Device command, or a Disable Slot command.  The Reset Device command leaves
3657 * the control endpoint intact, whereas the Disable Slot command deletes it.
3658 *
3659 * Must be called with xhci->lock held.
3660 */
3661void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3662	struct xhci_virt_device *virt_dev, bool drop_control_ep)
3663{
3664	int i;
3665	unsigned int num_dropped_eps = 0;
3666	unsigned int drop_flags = 0;
3667
3668	for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3669		if (virt_dev->eps[i].ring) {
3670			drop_flags |= 1 << i;
3671			num_dropped_eps++;
3672		}
3673	}
3674	xhci->num_active_eps -= num_dropped_eps;
3675	if (num_dropped_eps)
3676		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3677				"Dropped %u ep ctxs, flags = 0x%x, "
3678				"%u now active.",
3679				num_dropped_eps, drop_flags,
3680				xhci->num_active_eps);
3681}
3682
3683/*
3684 * This submits a Reset Device Command, which will set the device state to 0,
3685 * set the device address to 0, and disable all the endpoints except the default
3686 * control endpoint.  The USB core should come back and call
3687 * xhci_address_device(), and then re-set up the configuration.  If this is
3688 * called because of a usb_reset_and_verify_device(), then the old alternate
3689 * settings will be re-installed through the normal bandwidth allocation
3690 * functions.
3691 *
3692 * Wait for the Reset Device command to finish.  Remove all structures
3693 * associated with the endpoints that were disabled.  Clear the input device
3694 * structure? Reset the control endpoint 0 max packet size?
3695 *
3696 * If the virt_dev to be reset does not exist or does not match the udev,
3697 * it means the device is lost, possibly due to the xHC restore error and
3698 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3699 * re-allocate the device.
3700 */
3701static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3702		struct usb_device *udev)
3703{
3704	int ret, i;
3705	unsigned long flags;
3706	struct xhci_hcd *xhci;
3707	unsigned int slot_id;
3708	struct xhci_virt_device *virt_dev;
3709	struct xhci_command *reset_device_cmd;
 
 
3710	struct xhci_slot_ctx *slot_ctx;
3711	int old_active_eps = 0;
3712
3713	ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3714	if (ret <= 0)
3715		return ret;
3716	xhci = hcd_to_xhci(hcd);
3717	slot_id = udev->slot_id;
3718	virt_dev = xhci->devs[slot_id];
3719	if (!virt_dev) {
3720		xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3721				"not exist. Re-allocate the device\n", slot_id);
3722		ret = xhci_alloc_dev(hcd, udev);
3723		if (ret == 1)
3724			return 0;
3725		else
3726			return -EINVAL;
3727	}
3728
3729	if (virt_dev->tt_info)
3730		old_active_eps = virt_dev->tt_info->active_eps;
3731
3732	if (virt_dev->udev != udev) {
3733		/* If the virt_dev and the udev does not match, this virt_dev
3734		 * may belong to another udev.
3735		 * Re-allocate the device.
3736		 */
3737		xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3738				"not match the udev. Re-allocate the device\n",
3739				slot_id);
3740		ret = xhci_alloc_dev(hcd, udev);
3741		if (ret == 1)
3742			return 0;
3743		else
3744			return -EINVAL;
3745	}
3746
3747	/* If device is not setup, there is no point in resetting it */
3748	slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3749	if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3750						SLOT_STATE_DISABLED)
3751		return 0;
3752
3753	trace_xhci_discover_or_reset_device(slot_ctx);
3754
3755	xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3756	/* Allocate the command structure that holds the struct completion.
3757	 * Assume we're in process context, since the normal device reset
3758	 * process has to wait for the device anyway.  Storage devices are
3759	 * reset as part of error handling, so use GFP_NOIO instead of
3760	 * GFP_KERNEL.
3761	 */
3762	reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3763	if (!reset_device_cmd) {
3764		xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3765		return -ENOMEM;
3766	}
3767
3768	/* Attempt to submit the Reset Device command to the command ring */
3769	spin_lock_irqsave(&xhci->lock, flags);
 
3770
3771	ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
 
3772	if (ret) {
3773		xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
 
3774		spin_unlock_irqrestore(&xhci->lock, flags);
3775		goto command_cleanup;
3776	}
3777	xhci_ring_cmd_db(xhci);
3778	spin_unlock_irqrestore(&xhci->lock, flags);
3779
3780	/* Wait for the Reset Device command to finish */
3781	wait_for_completion(reset_device_cmd->completion);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
3782
3783	/* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3784	 * unless we tried to reset a slot ID that wasn't enabled,
3785	 * or the device wasn't in the addressed or configured state.
3786	 */
3787	ret = reset_device_cmd->status;
3788	switch (ret) {
3789	case COMP_COMMAND_ABORTED:
3790	case COMP_COMMAND_RING_STOPPED:
3791		xhci_warn(xhci, "Timeout waiting for reset device command\n");
3792		ret = -ETIME;
3793		goto command_cleanup;
3794	case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3795	case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3796		xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3797				slot_id,
3798				xhci_get_slot_state(xhci, virt_dev->out_ctx));
3799		xhci_dbg(xhci, "Not freeing device rings.\n");
3800		/* Don't treat this as an error.  May change my mind later. */
3801		ret = 0;
3802		goto command_cleanup;
3803	case COMP_SUCCESS:
3804		xhci_dbg(xhci, "Successful reset device command.\n");
3805		break;
3806	default:
3807		if (xhci_is_vendor_info_code(xhci, ret))
3808			break;
3809		xhci_warn(xhci, "Unknown completion code %u for "
3810				"reset device command.\n", ret);
3811		ret = -EINVAL;
3812		goto command_cleanup;
3813	}
3814
3815	/* Free up host controller endpoint resources */
3816	if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3817		spin_lock_irqsave(&xhci->lock, flags);
3818		/* Don't delete the default control endpoint resources */
3819		xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3820		spin_unlock_irqrestore(&xhci->lock, flags);
3821	}
3822
3823	/* Everything but endpoint 0 is disabled, so free the rings. */
3824	for (i = 1; i < 31; i++) {
 
3825		struct xhci_virt_ep *ep = &virt_dev->eps[i];
3826
3827		if (ep->ep_state & EP_HAS_STREAMS) {
3828			xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3829					xhci_get_endpoint_address(i));
3830			xhci_free_stream_info(xhci, ep->stream_info);
3831			ep->stream_info = NULL;
3832			ep->ep_state &= ~EP_HAS_STREAMS;
3833		}
3834
3835		if (ep->ring) {
3836			xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3837			xhci_free_endpoint_ring(xhci, virt_dev, i);
3838		}
3839		if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3840			xhci_drop_ep_from_interval_table(xhci,
3841					&virt_dev->eps[i].bw_info,
3842					virt_dev->bw_table,
3843					udev,
3844					&virt_dev->eps[i],
3845					virt_dev->tt_info);
3846		xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3847	}
3848	/* If necessary, update the number of active TTs on this root port */
3849	xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3850	virt_dev->flags = 0;
 
 
3851	ret = 0;
3852
3853command_cleanup:
3854	xhci_free_command(xhci, reset_device_cmd);
3855	return ret;
3856}
3857
3858/*
3859 * At this point, the struct usb_device is about to go away, the device has
3860 * disconnected, and all traffic has been stopped and the endpoints have been
3861 * disabled.  Free any HC data structures associated with that device.
3862 */
3863static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3864{
3865	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3866	struct xhci_virt_device *virt_dev;
3867	struct xhci_slot_ctx *slot_ctx;
3868	unsigned long flags;
 
3869	int i, ret;
3870
 
3871	/*
3872	 * We called pm_runtime_get_noresume when the device was attached.
3873	 * Decrement the counter here to allow controller to runtime suspend
3874	 * if no devices remain.
3875	 */
3876	if (xhci->quirks & XHCI_RESET_ON_RESUME)
3877		pm_runtime_put_noidle(hcd->self.controller);
 
3878
3879	ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3880	/* If the host is halted due to driver unload, we still need to free the
3881	 * device.
3882	 */
3883	if (ret <= 0 && ret != -ENODEV)
3884		return;
3885
3886	virt_dev = xhci->devs[udev->slot_id];
3887	slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3888	trace_xhci_free_dev(slot_ctx);
3889
3890	/* Stop any wayward timer functions (which may grab the lock) */
3891	for (i = 0; i < 31; i++)
3892		virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3893	virt_dev->udev = NULL;
3894	xhci_disable_slot(xhci, udev->slot_id);
3895
3896	spin_lock_irqsave(&xhci->lock, flags);
3897	xhci_free_virt_device(xhci, udev->slot_id);
3898	spin_unlock_irqrestore(&xhci->lock, flags);
3899
3900}
3901
3902int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
3903{
3904	struct xhci_command *command;
3905	unsigned long flags;
3906	u32 state;
3907	int ret;
3908
3909	command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3910	if (!command)
3911		return -ENOMEM;
3912
3913	xhci_debugfs_remove_slot(xhci, slot_id);
3914
3915	spin_lock_irqsave(&xhci->lock, flags);
3916	/* Don't disable the slot if the host controller is dead. */
3917	state = readl(&xhci->op_regs->status);
3918	if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3919			(xhci->xhc_state & XHCI_STATE_HALTED)) {
 
3920		spin_unlock_irqrestore(&xhci->lock, flags);
3921		kfree(command);
3922		return -ENODEV;
3923	}
3924
3925	ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3926				slot_id);
3927	if (ret) {
3928		spin_unlock_irqrestore(&xhci->lock, flags);
3929		kfree(command);
3930		return ret;
3931	}
3932	xhci_ring_cmd_db(xhci);
3933	spin_unlock_irqrestore(&xhci->lock, flags);
3934
3935	wait_for_completion(command->completion);
3936
3937	if (command->status != COMP_SUCCESS)
3938		xhci_warn(xhci, "Unsuccessful disable slot %u command, status %d\n",
3939			  slot_id, command->status);
3940
3941	xhci_free_command(xhci, command);
3942
3943	return 0;
3944}
3945
3946/*
3947 * Checks if we have enough host controller resources for the default control
3948 * endpoint.
3949 *
3950 * Must be called with xhci->lock held.
3951 */
3952static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3953{
3954	if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3955		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3956				"Not enough ep ctxs: "
3957				"%u active, need to add 1, limit is %u.",
3958				xhci->num_active_eps, xhci->limit_active_eps);
3959		return -ENOMEM;
3960	}
3961	xhci->num_active_eps += 1;
3962	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3963			"Adding 1 ep ctx, %u now active.",
3964			xhci->num_active_eps);
3965	return 0;
3966}
3967
3968
3969/*
3970 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3971 * timed out, or allocating memory failed.  Returns 1 on success.
3972 */
3973int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3974{
3975	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3976	struct xhci_virt_device *vdev;
3977	struct xhci_slot_ctx *slot_ctx;
3978	unsigned long flags;
3979	int ret, slot_id;
3980	struct xhci_command *command;
3981
3982	command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3983	if (!command)
3984		return 0;
3985
3986	spin_lock_irqsave(&xhci->lock, flags);
3987	ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
 
3988	if (ret) {
3989		spin_unlock_irqrestore(&xhci->lock, flags);
3990		xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3991		xhci_free_command(xhci, command);
3992		return 0;
3993	}
3994	xhci_ring_cmd_db(xhci);
3995	spin_unlock_irqrestore(&xhci->lock, flags);
3996
3997	wait_for_completion(command->completion);
3998	slot_id = command->slot_id;
 
 
 
 
 
 
 
3999
4000	if (!slot_id || command->status != COMP_SUCCESS) {
4001		xhci_err(xhci, "Error while assigning device slot ID: %s\n",
4002			 xhci_trb_comp_code_string(command->status));
4003		xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
4004				HCS_MAX_SLOTS(
4005					readl(&xhci->cap_regs->hcs_params1)));
4006		xhci_free_command(xhci, command);
4007		return 0;
4008	}
4009
4010	xhci_free_command(xhci, command);
4011
4012	if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
4013		spin_lock_irqsave(&xhci->lock, flags);
4014		ret = xhci_reserve_host_control_ep_resources(xhci);
4015		if (ret) {
4016			spin_unlock_irqrestore(&xhci->lock, flags);
4017			xhci_warn(xhci, "Not enough host resources, "
4018					"active endpoint contexts = %u\n",
4019					xhci->num_active_eps);
4020			goto disable_slot;
4021		}
4022		spin_unlock_irqrestore(&xhci->lock, flags);
4023	}
4024	/* Use GFP_NOIO, since this function can be called from
4025	 * xhci_discover_or_reset_device(), which may be called as part of
4026	 * mass storage driver error handling.
4027	 */
4028	if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4029		xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4030		goto disable_slot;
4031	}
4032	vdev = xhci->devs[slot_id];
4033	slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4034	trace_xhci_alloc_dev(slot_ctx);
4035
4036	udev->slot_id = slot_id;
4037
4038	xhci_debugfs_create_slot(xhci, slot_id);
4039
 
4040	/*
4041	 * If resetting upon resume, we can't put the controller into runtime
4042	 * suspend if there is a device attached.
4043	 */
4044	if (xhci->quirks & XHCI_RESET_ON_RESUME)
4045		pm_runtime_get_noresume(hcd->self.controller);
 
4046
4047	/* Is this a LS or FS device under a HS hub? */
4048	/* Hub or peripherial? */
4049	return 1;
4050
4051disable_slot:
4052	xhci_disable_slot(xhci, udev->slot_id);
4053	xhci_free_virt_device(xhci, udev->slot_id);
4054
 
 
4055	return 0;
4056}
4057
4058/**
4059 * xhci_setup_device - issues an Address Device command to assign a unique
4060 *			USB bus address.
4061 * @hcd: USB host controller data structure.
4062 * @udev: USB dev structure representing the connected device.
4063 * @setup: Enum specifying setup mode: address only or with context.
4064 * @timeout_ms: Max wait time (ms) for the command operation to complete.
4065 *
4066 * Return: 0 if successful; otherwise, negative error code.
4067 */
4068static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4069			     enum xhci_setup_dev setup, unsigned int timeout_ms)
4070{
4071	const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4072	unsigned long flags;
 
4073	struct xhci_virt_device *virt_dev;
4074	int ret = 0;
4075	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4076	struct xhci_slot_ctx *slot_ctx;
4077	struct xhci_input_control_ctx *ctrl_ctx;
4078	u64 temp_64;
4079	struct xhci_command *command = NULL;
4080
4081	mutex_lock(&xhci->mutex);
4082
4083	if (xhci->xhc_state) {	/* dying, removing or halted */
4084		ret = -ESHUTDOWN;
4085		goto out;
4086	}
4087
4088	if (!udev->slot_id) {
4089		xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4090				"Bad Slot ID %d", udev->slot_id);
4091		ret = -EINVAL;
4092		goto out;
4093	}
4094
4095	virt_dev = xhci->devs[udev->slot_id];
4096
4097	if (WARN_ON(!virt_dev)) {
4098		/*
4099		 * In plug/unplug torture test with an NEC controller,
4100		 * a zero-dereference was observed once due to virt_dev = 0.
4101		 * Print useful debug rather than crash if it is observed again!
4102		 */
4103		xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4104			udev->slot_id);
4105		ret = -EINVAL;
4106		goto out;
4107	}
4108	slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4109	trace_xhci_setup_device_slot(slot_ctx);
4110
4111	if (setup == SETUP_CONTEXT_ONLY) {
4112		if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4113		    SLOT_STATE_DEFAULT) {
4114			xhci_dbg(xhci, "Slot already in default state\n");
4115			goto out;
4116		}
4117	}
4118
4119	command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4120	if (!command) {
4121		ret = -ENOMEM;
4122		goto out;
4123	}
4124
4125	command->in_ctx = virt_dev->in_ctx;
4126	command->timeout_ms = timeout_ms;
4127
4128	slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4129	ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4130	if (!ctrl_ctx) {
4131		xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4132				__func__);
4133		ret = -EINVAL;
4134		goto out;
4135	}
4136	/*
4137	 * If this is the first Set Address since device plug-in or
4138	 * virt_device realloaction after a resume with an xHCI power loss,
4139	 * then set up the slot context.
4140	 */
4141	if (!slot_ctx->dev_info)
4142		xhci_setup_addressable_virt_dev(xhci, udev);
4143	/* Otherwise, update the control endpoint ring enqueue pointer. */
4144	else
4145		xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4146	ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4147	ctrl_ctx->drop_flags = 0;
4148
 
 
4149	trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4150				le32_to_cpu(slot_ctx->dev_info) >> 27);
4151
4152	trace_xhci_address_ctrl_ctx(ctrl_ctx);
4153	spin_lock_irqsave(&xhci->lock, flags);
4154	trace_xhci_setup_device(virt_dev);
4155	ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4156					udev->slot_id, setup);
4157	if (ret) {
4158		spin_unlock_irqrestore(&xhci->lock, flags);
4159		xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4160				"FIXME: allocate a command ring segment");
4161		goto out;
4162	}
4163	xhci_ring_cmd_db(xhci);
4164	spin_unlock_irqrestore(&xhci->lock, flags);
4165
4166	/* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4167	wait_for_completion(command->completion);
4168
4169	/* FIXME: From section 4.3.4: "Software shall be responsible for timing
4170	 * the SetAddress() "recovery interval" required by USB and aborting the
4171	 * command on a timeout.
4172	 */
4173	switch (command->status) {
4174	case COMP_COMMAND_ABORTED:
4175	case COMP_COMMAND_RING_STOPPED:
4176		xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4177		ret = -ETIME;
4178		break;
4179	case COMP_CONTEXT_STATE_ERROR:
4180	case COMP_SLOT_NOT_ENABLED_ERROR:
 
 
 
 
 
4181		xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4182			 act, udev->slot_id);
4183		ret = -EINVAL;
4184		break;
4185	case COMP_USB_TRANSACTION_ERROR:
4186		dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4187
4188		mutex_unlock(&xhci->mutex);
4189		ret = xhci_disable_slot(xhci, udev->slot_id);
4190		xhci_free_virt_device(xhci, udev->slot_id);
4191		if (!ret)
4192			xhci_alloc_dev(hcd, udev);
4193		kfree(command->completion);
4194		kfree(command);
4195		return -EPROTO;
4196	case COMP_INCOMPATIBLE_DEVICE_ERROR:
4197		dev_warn(&udev->dev,
4198			 "ERROR: Incompatible device for setup %s command\n", act);
4199		ret = -ENODEV;
4200		break;
4201	case COMP_SUCCESS:
4202		xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4203			       "Successful setup %s command", act);
4204		break;
4205	default:
4206		xhci_err(xhci,
4207			 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4208			 act, command->status);
 
 
4209		trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4210		ret = -EINVAL;
4211		break;
4212	}
4213	if (ret)
4214		goto out;
 
4215	temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4216	xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4217			"Op regs DCBAA ptr = %#016llx", temp_64);
4218	xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4219		"Slot ID %d dcbaa entry @%p = %#016llx",
4220		udev->slot_id,
4221		&xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4222		(unsigned long long)
4223		le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4224	xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4225			"Output Context DMA address = %#08llx",
4226			(unsigned long long)virt_dev->out_ctx->dma);
 
 
4227	trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4228				le32_to_cpu(slot_ctx->dev_info) >> 27);
 
 
4229	/*
4230	 * USB core uses address 1 for the roothubs, so we add one to the
4231	 * address given back to us by the HC.
4232	 */
 
4233	trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4234				le32_to_cpu(slot_ctx->dev_info) >> 27);
4235	/* Zero the input context control for later use */
4236	ctrl_ctx->add_flags = 0;
4237	ctrl_ctx->drop_flags = 0;
4238	slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4239	udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4240
4241	xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4242		       "Internal device address = %d",
4243		       le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4244out:
4245	mutex_unlock(&xhci->mutex);
4246	if (command) {
4247		kfree(command->completion);
4248		kfree(command);
4249	}
4250	return ret;
4251}
4252
4253static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev,
4254			       unsigned int timeout_ms)
4255{
4256	return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS, timeout_ms);
4257}
4258
4259static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4260{
4261	return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY,
4262				 XHCI_CMD_DEFAULT_TIMEOUT);
4263}
4264
4265/*
4266 * Transfer the port index into real index in the HW port status
4267 * registers. Caculate offset between the port's PORTSC register
4268 * and port status base. Divide the number of per port register
4269 * to get the real index. The raw port number bases 1.
4270 */
4271int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4272{
4273	struct xhci_hub *rhub;
 
 
 
 
 
 
 
 
4274
4275	rhub = xhci_get_rhub(hcd);
4276	return rhub->ports[port1 - 1]->hw_portnum + 1;
4277}
4278
4279/*
4280 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4281 * slot context.  If that succeeds, store the new MEL in the xhci_virt_device.
4282 */
4283static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4284			struct usb_device *udev, u16 max_exit_latency)
4285{
4286	struct xhci_virt_device *virt_dev;
4287	struct xhci_command *command;
4288	struct xhci_input_control_ctx *ctrl_ctx;
4289	struct xhci_slot_ctx *slot_ctx;
4290	unsigned long flags;
4291	int ret;
4292
4293	command = xhci_alloc_command_with_ctx(xhci, true, GFP_KERNEL);
4294	if (!command)
4295		return -ENOMEM;
4296
4297	spin_lock_irqsave(&xhci->lock, flags);
4298
4299	virt_dev = xhci->devs[udev->slot_id];
4300
4301	/*
4302	 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4303	 * xHC was re-initialized. Exit latency will be set later after
4304	 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4305	 */
4306
4307	if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4308		spin_unlock_irqrestore(&xhci->lock, flags);
4309		xhci_free_command(xhci, command);
4310		return 0;
4311	}
4312
4313	/* Attempt to issue an Evaluate Context command to change the MEL. */
4314	ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
 
 
4315	if (!ctrl_ctx) {
4316		spin_unlock_irqrestore(&xhci->lock, flags);
4317		xhci_free_command(xhci, command);
4318		xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4319				__func__);
4320		return -ENOMEM;
4321	}
4322
4323	xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4324	spin_unlock_irqrestore(&xhci->lock, flags);
4325
4326	ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4327	slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4328	slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4329	slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4330	slot_ctx->dev_state = 0;
4331
4332	xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4333			"Set up evaluate context for LPM MEL change.");
 
 
4334
4335	/* Issue and wait for the evaluate context command. */
4336	ret = xhci_configure_endpoint(xhci, udev, command,
4337			true, true);
 
 
4338
4339	if (!ret) {
4340		spin_lock_irqsave(&xhci->lock, flags);
4341		virt_dev->current_mel = max_exit_latency;
4342		spin_unlock_irqrestore(&xhci->lock, flags);
4343	}
4344
4345	xhci_free_command(xhci, command);
4346
4347	return ret;
4348}
4349
4350#ifdef CONFIG_PM
4351
4352/* BESL to HIRD Encoding array for USB2 LPM */
4353static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4354	3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4355
4356/* Calculate HIRD/BESL for USB2 PORTPMSC*/
4357static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4358					struct usb_device *udev)
4359{
4360	int u2del, besl, besl_host;
4361	int besl_device = 0;
4362	u32 field;
4363
4364	u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4365	field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4366
4367	if (field & USB_BESL_SUPPORT) {
4368		for (besl_host = 0; besl_host < 16; besl_host++) {
4369			if (xhci_besl_encoding[besl_host] >= u2del)
4370				break;
4371		}
4372		/* Use baseline BESL value as default */
4373		if (field & USB_BESL_BASELINE_VALID)
4374			besl_device = USB_GET_BESL_BASELINE(field);
4375		else if (field & USB_BESL_DEEP_VALID)
4376			besl_device = USB_GET_BESL_DEEP(field);
4377	} else {
4378		if (u2del <= 50)
4379			besl_host = 0;
4380		else
4381			besl_host = (u2del - 51) / 75 + 1;
4382	}
4383
4384	besl = besl_host + besl_device;
4385	if (besl > 15)
4386		besl = 15;
4387
4388	return besl;
4389}
4390
4391/* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4392static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4393{
4394	u32 field;
4395	int l1;
4396	int besld = 0;
4397	int hirdm = 0;
4398
4399	field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4400
4401	/* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4402	l1 = udev->l1_params.timeout / 256;
4403
4404	/* device has preferred BESLD */
4405	if (field & USB_BESL_DEEP_VALID) {
4406		besld = USB_GET_BESL_DEEP(field);
4407		hirdm = 1;
4408	}
4409
4410	return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4411}
4412
4413static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4414			struct usb_device *udev, int enable)
4415{
4416	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
4417	struct xhci_port **ports;
4418	__le32 __iomem	*pm_addr, *hlpm_addr;
4419	u32		pm_val, hlpm_val, field;
4420	unsigned int	port_num;
4421	unsigned long	flags;
4422	int		hird, exit_latency;
4423	int		ret;
4424
4425	if (xhci->quirks & XHCI_HW_LPM_DISABLE)
4426		return -EPERM;
4427
4428	if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4429			!udev->lpm_capable)
4430		return -EPERM;
4431
4432	if (!udev->parent || udev->parent->parent ||
4433			udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4434		return -EPERM;
4435
4436	if (udev->usb2_hw_lpm_capable != 1)
4437		return -EPERM;
4438
4439	spin_lock_irqsave(&xhci->lock, flags);
4440
4441	ports = xhci->usb2_rhub.ports;
4442	port_num = udev->portnum - 1;
4443	pm_addr = ports[port_num]->addr + PORTPMSC;
4444	pm_val = readl(pm_addr);
4445	hlpm_addr = ports[port_num]->addr + PORTHLPMC;
 
4446
4447	xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4448			enable ? "enable" : "disable", port_num + 1);
4449
4450	if (enable) {
4451		/* Host supports BESL timeout instead of HIRD */
4452		if (udev->usb2_hw_lpm_besl_capable) {
4453			/* if device doesn't have a preferred BESL value use a
4454			 * default one which works with mixed HIRD and BESL
4455			 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4456			 */
4457			field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4458			if ((field & USB_BESL_SUPPORT) &&
4459			    (field & USB_BESL_BASELINE_VALID))
4460				hird = USB_GET_BESL_BASELINE(field);
4461			else
4462				hird = udev->l1_params.besl;
4463
4464			exit_latency = xhci_besl_encoding[hird];
4465			spin_unlock_irqrestore(&xhci->lock, flags);
4466
 
 
 
 
 
 
 
 
4467			ret = xhci_change_max_exit_latency(xhci, udev,
4468							   exit_latency);
 
 
4469			if (ret < 0)
4470				return ret;
4471			spin_lock_irqsave(&xhci->lock, flags);
4472
4473			hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4474			writel(hlpm_val, hlpm_addr);
4475			/* flush write */
4476			readl(hlpm_addr);
4477		} else {
4478			hird = xhci_calculate_hird_besl(xhci, udev);
4479		}
4480
4481		pm_val &= ~PORT_HIRD_MASK;
4482		pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4483		writel(pm_val, pm_addr);
4484		pm_val = readl(pm_addr);
4485		pm_val |= PORT_HLE;
4486		writel(pm_val, pm_addr);
4487		/* flush write */
4488		readl(pm_addr);
4489	} else {
4490		pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4491		writel(pm_val, pm_addr);
4492		/* flush write */
4493		readl(pm_addr);
4494		if (udev->usb2_hw_lpm_besl_capable) {
4495			spin_unlock_irqrestore(&xhci->lock, flags);
 
4496			xhci_change_max_exit_latency(xhci, udev, 0);
4497			readl_poll_timeout(ports[port_num]->addr, pm_val,
4498					   (pm_val & PORT_PLS_MASK) == XDEV_U0,
4499					   100, 10000);
4500			return 0;
4501		}
4502	}
4503
4504	spin_unlock_irqrestore(&xhci->lock, flags);
4505	return 0;
4506}
4507
4508/* check if a usb2 port supports a given extened capability protocol
4509 * only USB2 ports extended protocol capability values are cached.
4510 * Return 1 if capability is supported
4511 */
4512static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4513					   unsigned capability)
4514{
4515	u32 port_offset, port_count;
4516	int i;
4517
4518	for (i = 0; i < xhci->num_ext_caps; i++) {
4519		if (xhci->ext_caps[i] & capability) {
4520			/* port offsets starts at 1 */
4521			port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4522			port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4523			if (port >= port_offset &&
4524			    port < port_offset + port_count)
4525				return 1;
4526		}
4527	}
4528	return 0;
4529}
4530
4531static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4532{
4533	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
4534	int		portnum = udev->portnum - 1;
4535
4536	if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
 
4537		return 0;
4538
4539	/* we only support lpm for non-hub device connected to root hub yet */
4540	if (!udev->parent || udev->parent->parent ||
4541			udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4542		return 0;
4543
4544	if (xhci->hw_lpm_support == 1 &&
4545			xhci_check_usb2_port_capability(
4546				xhci, portnum, XHCI_HLC)) {
4547		udev->usb2_hw_lpm_capable = 1;
4548		udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4549		udev->l1_params.besl = XHCI_DEFAULT_BESL;
4550		if (xhci_check_usb2_port_capability(xhci, portnum,
4551					XHCI_BLC))
4552			udev->usb2_hw_lpm_besl_capable = 1;
4553	}
4554
4555	return 0;
4556}
4557
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
4558/*---------------------- USB 3.0 Link PM functions ------------------------*/
4559
 
4560/* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4561static unsigned long long xhci_service_interval_to_ns(
4562		struct usb_endpoint_descriptor *desc)
4563{
4564	return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4565}
4566
4567static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4568		enum usb3_link_state state)
4569{
4570	unsigned long long sel;
4571	unsigned long long pel;
4572	unsigned int max_sel_pel;
4573	char *state_name;
4574
4575	switch (state) {
4576	case USB3_LPM_U1:
4577		/* Convert SEL and PEL stored in nanoseconds to microseconds */
4578		sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4579		pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4580		max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4581		state_name = "U1";
4582		break;
4583	case USB3_LPM_U2:
4584		sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4585		pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4586		max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4587		state_name = "U2";
4588		break;
4589	default:
4590		dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4591				__func__);
4592		return USB3_LPM_DISABLED;
4593	}
4594
4595	if (sel <= max_sel_pel && pel <= max_sel_pel)
4596		return USB3_LPM_DEVICE_INITIATED;
4597
4598	if (sel > max_sel_pel)
4599		dev_dbg(&udev->dev, "Device-initiated %s disabled "
4600				"due to long SEL %llu ms\n",
4601				state_name, sel);
4602	else
4603		dev_dbg(&udev->dev, "Device-initiated %s disabled "
4604				"due to long PEL %llu ms\n",
4605				state_name, pel);
4606	return USB3_LPM_DISABLED;
4607}
4608
4609/* The U1 timeout should be the maximum of the following values:
 
4610 *  - For control endpoints, U1 system exit latency (SEL) * 3
4611 *  - For bulk endpoints, U1 SEL * 5
4612 *  - For interrupt endpoints:
4613 *    - Notification EPs, U1 SEL * 3
4614 *    - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4615 *  - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4616 */
4617static unsigned long long xhci_calculate_intel_u1_timeout(
4618		struct usb_device *udev,
4619		struct usb_endpoint_descriptor *desc)
4620{
4621	unsigned long long timeout_ns;
4622	int ep_type;
4623	int intr_type;
4624
4625	ep_type = usb_endpoint_type(desc);
4626	switch (ep_type) {
4627	case USB_ENDPOINT_XFER_CONTROL:
4628		timeout_ns = udev->u1_params.sel * 3;
4629		break;
4630	case USB_ENDPOINT_XFER_BULK:
4631		timeout_ns = udev->u1_params.sel * 5;
4632		break;
4633	case USB_ENDPOINT_XFER_INT:
4634		intr_type = usb_endpoint_interrupt_type(desc);
4635		if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4636			timeout_ns = udev->u1_params.sel * 3;
4637			break;
4638		}
4639		/* Otherwise the calculation is the same as isoc eps */
4640		fallthrough;
4641	case USB_ENDPOINT_XFER_ISOC:
4642		timeout_ns = xhci_service_interval_to_ns(desc);
4643		timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4644		if (timeout_ns < udev->u1_params.sel * 2)
4645			timeout_ns = udev->u1_params.sel * 2;
4646		break;
4647	default:
4648		return 0;
4649	}
4650
4651	return timeout_ns;
4652}
4653
4654/* Returns the hub-encoded U1 timeout value. */
4655static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4656		struct usb_device *udev,
4657		struct usb_endpoint_descriptor *desc)
4658{
4659	unsigned long long timeout_ns;
4660
4661	/* Prevent U1 if service interval is shorter than U1 exit latency */
4662	if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4663		if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4664			dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4665			return USB3_LPM_DISABLED;
4666		}
4667	}
4668
4669	if (xhci->quirks & (XHCI_INTEL_HOST | XHCI_ZHAOXIN_HOST))
4670		timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4671	else
4672		timeout_ns = udev->u1_params.sel;
4673
4674	/* The U1 timeout is encoded in 1us intervals.
4675	 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4676	 */
4677	if (timeout_ns == USB3_LPM_DISABLED)
4678		timeout_ns = 1;
4679	else
4680		timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4681
4682	/* If the necessary timeout value is bigger than what we can set in the
4683	 * USB 3.0 hub, we have to disable hub-initiated U1.
4684	 */
4685	if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4686		return timeout_ns;
4687	dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4688			"due to long timeout %llu ms\n", timeout_ns);
4689	return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4690}
4691
4692/* The U2 timeout should be the maximum of:
 
4693 *  - 10 ms (to avoid the bandwidth impact on the scheduler)
4694 *  - largest bInterval of any active periodic endpoint (to avoid going
4695 *    into lower power link states between intervals).
4696 *  - the U2 Exit Latency of the device
4697 */
4698static unsigned long long xhci_calculate_intel_u2_timeout(
4699		struct usb_device *udev,
4700		struct usb_endpoint_descriptor *desc)
4701{
4702	unsigned long long timeout_ns;
4703	unsigned long long u2_del_ns;
4704
4705	timeout_ns = 10 * 1000 * 1000;
4706
4707	if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4708			(xhci_service_interval_to_ns(desc) > timeout_ns))
4709		timeout_ns = xhci_service_interval_to_ns(desc);
4710
4711	u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4712	if (u2_del_ns > timeout_ns)
4713		timeout_ns = u2_del_ns;
4714
4715	return timeout_ns;
4716}
4717
4718/* Returns the hub-encoded U2 timeout value. */
4719static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4720		struct usb_device *udev,
4721		struct usb_endpoint_descriptor *desc)
4722{
4723	unsigned long long timeout_ns;
4724
4725	/* Prevent U2 if service interval is shorter than U2 exit latency */
4726	if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4727		if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4728			dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4729			return USB3_LPM_DISABLED;
4730		}
4731	}
4732
4733	if (xhci->quirks & (XHCI_INTEL_HOST | XHCI_ZHAOXIN_HOST))
4734		timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4735	else
4736		timeout_ns = udev->u2_params.sel;
4737
4738	/* The U2 timeout is encoded in 256us intervals */
4739	timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4740	/* If the necessary timeout value is bigger than what we can set in the
4741	 * USB 3.0 hub, we have to disable hub-initiated U2.
4742	 */
4743	if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4744		return timeout_ns;
4745	dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4746			"due to long timeout %llu ms\n", timeout_ns);
4747	return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4748}
4749
4750static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4751		struct usb_device *udev,
4752		struct usb_endpoint_descriptor *desc,
4753		enum usb3_link_state state,
4754		u16 *timeout)
4755{
4756	if (state == USB3_LPM_U1)
4757		return xhci_calculate_u1_timeout(xhci, udev, desc);
4758	else if (state == USB3_LPM_U2)
4759		return xhci_calculate_u2_timeout(xhci, udev, desc);
 
 
 
4760
4761	return USB3_LPM_DISABLED;
4762}
4763
4764static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4765		struct usb_device *udev,
4766		struct usb_endpoint_descriptor *desc,
4767		enum usb3_link_state state,
4768		u16 *timeout)
4769{
4770	u16 alt_timeout;
4771
4772	alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4773		desc, state, timeout);
4774
4775	/* If we found we can't enable hub-initiated LPM, and
4776	 * the U1 or U2 exit latency was too high to allow
4777	 * device-initiated LPM as well, then we will disable LPM
4778	 * for this device, so stop searching any further.
4779	 */
4780	if (alt_timeout == USB3_LPM_DISABLED) {
 
4781		*timeout = alt_timeout;
4782		return -E2BIG;
4783	}
4784	if (alt_timeout > *timeout)
4785		*timeout = alt_timeout;
4786	return 0;
4787}
4788
4789static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4790		struct usb_device *udev,
4791		struct usb_host_interface *alt,
4792		enum usb3_link_state state,
4793		u16 *timeout)
4794{
4795	int j;
4796
4797	for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4798		if (xhci_update_timeout_for_endpoint(xhci, udev,
4799					&alt->endpoint[j].desc, state, timeout))
4800			return -E2BIG;
 
4801	}
4802	return 0;
4803}
4804
4805static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4806		struct usb_device *udev,
4807		enum usb3_link_state state)
4808{
4809	struct usb_device *parent = udev->parent;
4810	int tier = 1; /* roothub is tier1 */
4811
4812	while (parent) {
4813		parent = parent->parent;
4814		tier++;
4815	}
4816
4817	if (xhci->quirks & XHCI_INTEL_HOST && tier > 3)
4818		goto fail;
4819	if (xhci->quirks & XHCI_ZHAOXIN_HOST && tier > 2)
4820		goto fail;
4821
4822	return 0;
4823fail:
4824	dev_dbg(&udev->dev, "Tier policy prevents U1/U2 LPM states for devices at tier %d\n",
4825			tier);
 
 
 
4826	return -E2BIG;
4827}
4828
 
 
 
 
 
 
 
 
 
4829/* Returns the U1 or U2 timeout that should be enabled.
4830 * If the tier check or timeout setting functions return with a non-zero exit
4831 * code, that means the timeout value has been finalized and we shouldn't look
4832 * at any more endpoints.
4833 */
4834static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4835			struct usb_device *udev, enum usb3_link_state state)
4836{
4837	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4838	struct usb_host_config *config;
4839	char *state_name;
4840	int i;
4841	u16 timeout = USB3_LPM_DISABLED;
4842
4843	if (state == USB3_LPM_U1)
4844		state_name = "U1";
4845	else if (state == USB3_LPM_U2)
4846		state_name = "U2";
4847	else {
4848		dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4849				state);
4850		return timeout;
4851	}
4852
 
 
 
4853	/* Gather some information about the currently installed configuration
4854	 * and alternate interface settings.
4855	 */
4856	if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4857			state, &timeout))
4858		return timeout;
4859
4860	config = udev->actconfig;
4861	if (!config)
4862		return timeout;
4863
4864	for (i = 0; i < config->desc.bNumInterfaces; i++) {
4865		struct usb_driver *driver;
4866		struct usb_interface *intf = config->interface[i];
4867
4868		if (!intf)
4869			continue;
4870
4871		/* Check if any currently bound drivers want hub-initiated LPM
4872		 * disabled.
4873		 */
4874		if (intf->dev.driver) {
4875			driver = to_usb_driver(intf->dev.driver);
4876			if (driver && driver->disable_hub_initiated_lpm) {
4877				dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4878					state_name, driver->name);
4879				timeout = xhci_get_timeout_no_hub_lpm(udev,
4880								      state);
4881				if (timeout == USB3_LPM_DISABLED)
4882					return timeout;
4883			}
4884		}
4885
4886		/* Not sure how this could happen... */
4887		if (!intf->cur_altsetting)
4888			continue;
4889
4890		if (xhci_update_timeout_for_interface(xhci, udev,
4891					intf->cur_altsetting,
4892					state, &timeout))
4893			return timeout;
4894	}
4895	return timeout;
4896}
4897
4898static int calculate_max_exit_latency(struct usb_device *udev,
4899		enum usb3_link_state state_changed,
4900		u16 hub_encoded_timeout)
4901{
4902	unsigned long long u1_mel_us = 0;
4903	unsigned long long u2_mel_us = 0;
4904	unsigned long long mel_us = 0;
4905	bool disabling_u1;
4906	bool disabling_u2;
4907	bool enabling_u1;
4908	bool enabling_u2;
4909
4910	disabling_u1 = (state_changed == USB3_LPM_U1 &&
4911			hub_encoded_timeout == USB3_LPM_DISABLED);
4912	disabling_u2 = (state_changed == USB3_LPM_U2 &&
4913			hub_encoded_timeout == USB3_LPM_DISABLED);
4914
4915	enabling_u1 = (state_changed == USB3_LPM_U1 &&
4916			hub_encoded_timeout != USB3_LPM_DISABLED);
4917	enabling_u2 = (state_changed == USB3_LPM_U2 &&
4918			hub_encoded_timeout != USB3_LPM_DISABLED);
4919
4920	/* If U1 was already enabled and we're not disabling it,
4921	 * or we're going to enable U1, account for the U1 max exit latency.
4922	 */
4923	if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4924			enabling_u1)
4925		u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4926	if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4927			enabling_u2)
4928		u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4929
4930	mel_us = max(u1_mel_us, u2_mel_us);
4931
 
 
4932	/* xHCI host controller max exit latency field is only 16 bits wide. */
4933	if (mel_us > MAX_EXIT) {
4934		dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4935				"is too big.\n", mel_us);
4936		return -E2BIG;
4937	}
4938	return mel_us;
4939}
4940
4941/* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4942static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4943			struct usb_device *udev, enum usb3_link_state state)
4944{
4945	struct xhci_hcd	*xhci;
4946	struct xhci_port *port;
4947	u16 hub_encoded_timeout;
4948	int mel;
4949	int ret;
4950
4951	xhci = hcd_to_xhci(hcd);
4952	/* The LPM timeout values are pretty host-controller specific, so don't
4953	 * enable hub-initiated timeouts unless the vendor has provided
4954	 * information about their timeout algorithm.
4955	 */
4956	if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4957			!xhci->devs[udev->slot_id])
4958		return USB3_LPM_DISABLED;
4959
4960	if (xhci_check_tier_policy(xhci, udev, state) < 0)
4961		return USB3_LPM_DISABLED;
4962
4963	/* If connected to root port then check port can handle lpm */
4964	if (udev->parent && !udev->parent->parent) {
4965		port = xhci->usb3_rhub.ports[udev->portnum - 1];
4966		if (port->lpm_incapable)
4967			return USB3_LPM_DISABLED;
4968	}
4969
4970	hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4971	mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4972	if (mel < 0) {
4973		/* Max Exit Latency is too big, disable LPM. */
4974		hub_encoded_timeout = USB3_LPM_DISABLED;
4975		mel = 0;
4976	}
4977
4978	ret = xhci_change_max_exit_latency(xhci, udev, mel);
4979	if (ret)
4980		return ret;
4981	return hub_encoded_timeout;
4982}
4983
4984static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4985			struct usb_device *udev, enum usb3_link_state state)
4986{
4987	struct xhci_hcd	*xhci;
4988	u16 mel;
 
4989
4990	xhci = hcd_to_xhci(hcd);
4991	if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4992			!xhci->devs[udev->slot_id])
4993		return 0;
4994
4995	mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4996	return xhci_change_max_exit_latency(xhci, udev, mel);
4997}
4998#else /* CONFIG_PM */
4999
5000static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
5001				struct usb_device *udev, int enable)
5002{
5003	return 0;
5004}
5005
5006static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
5007{
5008	return 0;
5009}
 
5010
5011static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5012			struct usb_device *udev, enum usb3_link_state state)
5013{
5014	return USB3_LPM_DISABLED;
5015}
5016
5017static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5018			struct usb_device *udev, enum usb3_link_state state)
5019{
5020	return 0;
5021}
5022#endif	/* CONFIG_PM */
5023
5024/*-------------------------------------------------------------------------*/
5025
5026/* Once a hub descriptor is fetched for a device, we need to update the xHC's
5027 * internal data structures for the device.
5028 */
5029int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5030			struct usb_tt *tt, gfp_t mem_flags)
5031{
5032	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5033	struct xhci_virt_device *vdev;
5034	struct xhci_command *config_cmd;
5035	struct xhci_input_control_ctx *ctrl_ctx;
5036	struct xhci_slot_ctx *slot_ctx;
5037	unsigned long flags;
5038	unsigned think_time;
5039	int ret;
5040
5041	/* Ignore root hubs */
5042	if (!hdev->parent)
5043		return 0;
5044
5045	vdev = xhci->devs[hdev->slot_id];
5046	if (!vdev) {
5047		xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5048		return -EINVAL;
5049	}
5050
5051	config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5052	if (!config_cmd)
5053		return -ENOMEM;
5054
5055	ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5056	if (!ctrl_ctx) {
5057		xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5058				__func__);
5059		xhci_free_command(xhci, config_cmd);
5060		return -ENOMEM;
5061	}
5062
5063	spin_lock_irqsave(&xhci->lock, flags);
5064	if (hdev->speed == USB_SPEED_HIGH &&
5065			xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5066		xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5067		xhci_free_command(xhci, config_cmd);
5068		spin_unlock_irqrestore(&xhci->lock, flags);
5069		return -ENOMEM;
5070	}
5071
5072	xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5073	ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5074	slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5075	slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5076	/*
5077	 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5078	 * but it may be already set to 1 when setup an xHCI virtual
5079	 * device, so clear it anyway.
5080	 */
5081	if (tt->multi)
5082		slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5083	else if (hdev->speed == USB_SPEED_FULL)
5084		slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5085
5086	if (xhci->hci_version > 0x95) {
5087		xhci_dbg(xhci, "xHCI version %x needs hub "
5088				"TT think time and number of ports\n",
5089				(unsigned int) xhci->hci_version);
5090		slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5091		/* Set TT think time - convert from ns to FS bit times.
5092		 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5093		 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5094		 *
5095		 * xHCI 1.0: this field shall be 0 if the device is not a
5096		 * High-spped hub.
5097		 */
5098		think_time = tt->think_time;
5099		if (think_time != 0)
5100			think_time = (think_time / 666) - 1;
5101		if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5102			slot_ctx->tt_info |=
5103				cpu_to_le32(TT_THINK_TIME(think_time));
5104	} else {
5105		xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5106				"TT think time or number of ports\n",
5107				(unsigned int) xhci->hci_version);
5108	}
5109	slot_ctx->dev_state = 0;
5110	spin_unlock_irqrestore(&xhci->lock, flags);
5111
5112	xhci_dbg(xhci, "Set up %s for hub device.\n",
5113			(xhci->hci_version > 0x95) ?
5114			"configure endpoint" : "evaluate context");
 
 
5115
5116	/* Issue and wait for the configure endpoint or
5117	 * evaluate context command.
5118	 */
5119	if (xhci->hci_version > 0x95)
5120		ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5121				false, false);
5122	else
5123		ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5124				true, false);
5125
 
 
 
5126	xhci_free_command(xhci, config_cmd);
5127	return ret;
5128}
5129EXPORT_SYMBOL_GPL(xhci_update_hub_device);
5130
5131static int xhci_get_frame(struct usb_hcd *hcd)
5132{
5133	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5134	/* EHCI mods by the periodic size.  Why? */
5135	return readl(&xhci->run_regs->microframe_index) >> 3;
5136}
5137
5138static void xhci_hcd_init_usb2_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5139{
5140	xhci->usb2_rhub.hcd = hcd;
5141	hcd->speed = HCD_USB2;
5142	hcd->self.root_hub->speed = USB_SPEED_HIGH;
5143	/*
5144	 * USB 2.0 roothub under xHCI has an integrated TT,
5145	 * (rate matching hub) as opposed to having an OHCI/UHCI
5146	 * companion controller.
5147	 */
5148	hcd->has_tt = 1;
5149}
5150
5151static void xhci_hcd_init_usb3_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5152{
5153	unsigned int minor_rev;
5154
5155	/*
5156	 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5157	 * should return 0x31 for sbrn, or that the minor revision
5158	 * is a two digit BCD containig minor and sub-minor numbers.
5159	 * This was later clarified in xHCI 1.2.
5160	 *
5161	 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5162	 * minor revision set to 0x1 instead of 0x10.
5163	 */
5164	if (xhci->usb3_rhub.min_rev == 0x1)
5165		minor_rev = 1;
5166	else
5167		minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5168
5169	switch (minor_rev) {
5170	case 2:
5171		hcd->speed = HCD_USB32;
5172		hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5173		hcd->self.root_hub->rx_lanes = 2;
5174		hcd->self.root_hub->tx_lanes = 2;
5175		hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x2;
5176		break;
5177	case 1:
5178		hcd->speed = HCD_USB31;
5179		hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5180		hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x1;
5181		break;
5182	}
5183	xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5184		  minor_rev, minor_rev ? "Enhanced " : "");
5185
5186	xhci->usb3_rhub.hcd = hcd;
5187}
5188
5189int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5190{
5191	struct xhci_hcd		*xhci;
5192	/*
5193	 * TODO: Check with DWC3 clients for sysdev according to
5194	 * quirks
5195	 */
5196	struct device		*dev = hcd->self.sysdev;
5197	int			retval;
5198
5199	/* Accept arbitrarily long scatter-gather lists */
5200	hcd->self.sg_tablesize = ~0;
5201
5202	/* support to build packet from discontinuous buffers */
5203	hcd->self.no_sg_constraint = 1;
5204
5205	/* XHCI controllers don't stop the ep queue on short packets :| */
5206	hcd->self.no_stop_on_short = 1;
5207
5208	xhci = hcd_to_xhci(hcd);
5209
5210	if (!usb_hcd_is_primary_hcd(hcd)) {
5211		xhci_hcd_init_usb3_data(xhci, hcd);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
5212		return 0;
5213	}
5214
5215	mutex_init(&xhci->mutex);
5216	xhci->main_hcd = hcd;
5217	xhci->cap_regs = hcd->regs;
5218	xhci->op_regs = hcd->regs +
5219		HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5220	xhci->run_regs = hcd->regs +
5221		(readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5222	/* Cache read-only capability registers */
5223	xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5224	xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5225	xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5226	xhci->hci_version = HC_VERSION(readl(&xhci->cap_regs->hc_capbase));
 
5227	xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5228	if (xhci->hci_version > 0x100)
5229		xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5230
5231	/* xhci-plat or xhci-pci might have set max_interrupters already */
5232	if ((!xhci->max_interrupters) ||
5233	    xhci->max_interrupters > HCS_MAX_INTRS(xhci->hcs_params1))
5234		xhci->max_interrupters = HCS_MAX_INTRS(xhci->hcs_params1);
5235
5236	xhci->quirks |= quirks;
5237
5238	if (get_quirks)
5239		get_quirks(dev, xhci);
5240
5241	/* In xhci controllers which follow xhci 1.0 spec gives a spurious
5242	 * success event after a short transfer. This quirk will ignore such
5243	 * spurious event.
5244	 */
5245	if (xhci->hci_version > 0x96)
5246		xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5247
5248	/* Make sure the HC is halted. */
5249	retval = xhci_halt(xhci);
5250	if (retval)
5251		return retval;
5252
5253	xhci_zero_64b_regs(xhci);
5254
5255	xhci_dbg(xhci, "Resetting HCD\n");
5256	/* Reset the internal HC memory state and registers. */
5257	retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
5258	if (retval)
5259		return retval;
5260	xhci_dbg(xhci, "Reset complete\n");
5261
5262	/*
5263	 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5264	 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5265	 * address memory pointers actually. So, this driver clears the AC64
5266	 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5267	 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5268	 */
5269	if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5270		xhci->hcc_params &= ~BIT(0);
5271
5272	/* Set dma_mask and coherent_dma_mask to 64-bits,
5273	 * if xHC supports 64-bit addressing */
5274	if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5275			!dma_set_mask(dev, DMA_BIT_MASK(64))) {
5276		xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5277		dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5278	} else {
5279		/*
5280		 * This is to avoid error in cases where a 32-bit USB
5281		 * controller is used on a 64-bit capable system.
5282		 */
5283		retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5284		if (retval)
5285			return retval;
5286		xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5287		dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5288	}
5289
5290	xhci_dbg(xhci, "Calling HCD init\n");
5291	/* Initialize HCD and host controller data structures. */
5292	retval = xhci_init(hcd);
5293	if (retval)
5294		return retval;
5295	xhci_dbg(xhci, "Called HCD init\n");
5296
5297	if (xhci_hcd_is_usb3(hcd))
5298		xhci_hcd_init_usb3_data(xhci, hcd);
5299	else
5300		xhci_hcd_init_usb2_data(xhci, hcd);
5301
5302	xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5303		  xhci->hcc_params, xhci->hci_version, xhci->quirks);
5304
5305	return 0;
 
 
 
5306}
5307EXPORT_SYMBOL_GPL(xhci_gen_setup);
5308
5309static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5310		struct usb_host_endpoint *ep)
5311{
5312	struct xhci_hcd *xhci;
5313	struct usb_device *udev;
5314	unsigned int slot_id;
5315	unsigned int ep_index;
5316	unsigned long flags;
5317
5318	xhci = hcd_to_xhci(hcd);
5319
5320	spin_lock_irqsave(&xhci->lock, flags);
5321	udev = (struct usb_device *)ep->hcpriv;
5322	slot_id = udev->slot_id;
5323	ep_index = xhci_get_endpoint_index(&ep->desc);
5324
5325	xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5326	xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5327	spin_unlock_irqrestore(&xhci->lock, flags);
5328}
5329
5330static const struct hc_driver xhci_hc_driver = {
5331	.description =		"xhci-hcd",
5332	.product_desc =		"xHCI Host Controller",
5333	.hcd_priv_size =	sizeof(struct xhci_hcd),
5334
5335	/*
5336	 * generic hardware linkage
5337	 */
5338	.irq =			xhci_irq,
5339	.flags =		HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
5340				HCD_BH,
5341
5342	/*
5343	 * basic lifecycle operations
5344	 */
5345	.reset =		NULL, /* set in xhci_init_driver() */
5346	.start =		xhci_run,
5347	.stop =			xhci_stop,
5348	.shutdown =		xhci_shutdown,
5349
5350	/*
5351	 * managing i/o requests and associated device resources
5352	 */
5353	.map_urb_for_dma =      xhci_map_urb_for_dma,
5354	.unmap_urb_for_dma =    xhci_unmap_urb_for_dma,
5355	.urb_enqueue =		xhci_urb_enqueue,
5356	.urb_dequeue =		xhci_urb_dequeue,
5357	.alloc_dev =		xhci_alloc_dev,
5358	.free_dev =		xhci_free_dev,
5359	.alloc_streams =	xhci_alloc_streams,
5360	.free_streams =		xhci_free_streams,
5361	.add_endpoint =		xhci_add_endpoint,
5362	.drop_endpoint =	xhci_drop_endpoint,
5363	.endpoint_disable =	xhci_endpoint_disable,
5364	.endpoint_reset =	xhci_endpoint_reset,
5365	.check_bandwidth =	xhci_check_bandwidth,
5366	.reset_bandwidth =	xhci_reset_bandwidth,
5367	.address_device =	xhci_address_device,
5368	.enable_device =	xhci_enable_device,
5369	.update_hub_device =	xhci_update_hub_device,
5370	.reset_device =		xhci_discover_or_reset_device,
5371
5372	/*
5373	 * scheduling support
5374	 */
5375	.get_frame_number =	xhci_get_frame,
5376
5377	/*
5378	 * root hub support
5379	 */
5380	.hub_control =		xhci_hub_control,
5381	.hub_status_data =	xhci_hub_status_data,
5382	.bus_suspend =		xhci_bus_suspend,
5383	.bus_resume =		xhci_bus_resume,
5384	.get_resuming_ports =	xhci_get_resuming_ports,
5385
5386	/*
5387	 * call back when device connected and addressed
5388	 */
5389	.update_device =        xhci_update_device,
5390	.set_usb2_hw_lpm =	xhci_set_usb2_hardware_lpm,
5391	.enable_usb3_lpm_timeout =	xhci_enable_usb3_lpm_timeout,
5392	.disable_usb3_lpm_timeout =	xhci_disable_usb3_lpm_timeout,
5393	.find_raw_port_number =	xhci_find_raw_port_number,
5394	.clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5395};
5396
5397void xhci_init_driver(struct hc_driver *drv,
5398		      const struct xhci_driver_overrides *over)
5399{
5400	BUG_ON(!over);
5401
5402	/* Copy the generic table to drv then apply the overrides */
5403	*drv = xhci_hc_driver;
5404
5405	if (over) {
5406		drv->hcd_priv_size += over->extra_priv_size;
5407		if (over->reset)
5408			drv->reset = over->reset;
5409		if (over->start)
5410			drv->start = over->start;
5411		if (over->add_endpoint)
5412			drv->add_endpoint = over->add_endpoint;
5413		if (over->drop_endpoint)
5414			drv->drop_endpoint = over->drop_endpoint;
5415		if (over->check_bandwidth)
5416			drv->check_bandwidth = over->check_bandwidth;
5417		if (over->reset_bandwidth)
5418			drv->reset_bandwidth = over->reset_bandwidth;
5419		if (over->update_hub_device)
5420			drv->update_hub_device = over->update_hub_device;
5421		if (over->hub_control)
5422			drv->hub_control = over->hub_control;
5423	}
5424}
5425EXPORT_SYMBOL_GPL(xhci_init_driver);
5426
5427MODULE_DESCRIPTION(DRIVER_DESC);
5428MODULE_AUTHOR(DRIVER_AUTHOR);
5429MODULE_LICENSE("GPL");
5430
5431static int __init xhci_hcd_init(void)
5432{
 
 
 
 
 
 
 
 
 
 
 
 
5433	/*
5434	 * Check the compiler generated sizes of structures that must be laid
5435	 * out in specific ways for hardware access.
5436	 */
5437	BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5438	BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5439	BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5440	/* xhci_device_control has eight fields, and also
5441	 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5442	 */
5443	BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5444	BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5445	BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5446	BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5447	BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5448	/* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5449	BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5450
5451	if (usb_disabled())
5452		return -ENODEV;
5453
5454	xhci_debugfs_create_root();
5455	xhci_dbc_init();
5456
5457	return 0;
 
 
 
5458}
 
5459
5460/*
5461 * If an init function is provided, an exit function must also be provided
5462 * to allow module unload.
5463 */
5464static void __exit xhci_hcd_fini(void)
5465{
5466	xhci_debugfs_remove_root();
5467	xhci_dbc_exit();
5468}
5469
5470module_init(xhci_hcd_init);
5471module_exit(xhci_hcd_fini);