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1// SPDX-License-Identifier: GPL-2.0-only
2#include <linux/init.h>
3
4#include <linux/mm.h>
5#include <linux/spinlock.h>
6#include <linux/smp.h>
7#include <linux/interrupt.h>
8#include <linux/export.h>
9#include <linux/cpu.h>
10#include <linux/debugfs.h>
11#include <linux/sched/smt.h>
12#include <linux/task_work.h>
13
14#include <asm/tlbflush.h>
15#include <asm/mmu_context.h>
16#include <asm/nospec-branch.h>
17#include <asm/cache.h>
18#include <asm/cacheflush.h>
19#include <asm/apic.h>
20#include <asm/perf_event.h>
21
22#include "mm_internal.h"
23
24#ifdef CONFIG_PARAVIRT
25# define STATIC_NOPV
26#else
27# define STATIC_NOPV static
28# define __flush_tlb_local native_flush_tlb_local
29# define __flush_tlb_global native_flush_tlb_global
30# define __flush_tlb_one_user(addr) native_flush_tlb_one_user(addr)
31# define __flush_tlb_multi(msk, info) native_flush_tlb_multi(msk, info)
32#endif
33
34/*
35 * TLB flushing, formerly SMP-only
36 * c/o Linus Torvalds.
37 *
38 * These mean you can really definitely utterly forget about
39 * writing to user space from interrupts. (Its not allowed anyway).
40 *
41 * Optimizations Manfred Spraul <manfred@colorfullife.com>
42 *
43 * More scalable flush, from Andi Kleen
44 *
45 * Implement flush IPI by CALL_FUNCTION_VECTOR, Alex Shi
46 */
47
48/*
49 * Bits to mangle the TIF_SPEC_* state into the mm pointer which is
50 * stored in cpu_tlb_state.last_user_mm_spec.
51 */
52#define LAST_USER_MM_IBPB 0x1UL
53#define LAST_USER_MM_L1D_FLUSH 0x2UL
54#define LAST_USER_MM_SPEC_MASK (LAST_USER_MM_IBPB | LAST_USER_MM_L1D_FLUSH)
55
56/* Bits to set when tlbstate and flush is (re)initialized */
57#define LAST_USER_MM_INIT LAST_USER_MM_IBPB
58
59/*
60 * The x86 feature is called PCID (Process Context IDentifier). It is similar
61 * to what is traditionally called ASID on the RISC processors.
62 *
63 * We don't use the traditional ASID implementation, where each process/mm gets
64 * its own ASID and flush/restart when we run out of ASID space.
65 *
66 * Instead we have a small per-cpu array of ASIDs and cache the last few mm's
67 * that came by on this CPU, allowing cheaper switch_mm between processes on
68 * this CPU.
69 *
70 * We end up with different spaces for different things. To avoid confusion we
71 * use different names for each of them:
72 *
73 * ASID - [0, TLB_NR_DYN_ASIDS-1]
74 * the canonical identifier for an mm
75 *
76 * kPCID - [1, TLB_NR_DYN_ASIDS]
77 * the value we write into the PCID part of CR3; corresponds to the
78 * ASID+1, because PCID 0 is special.
79 *
80 * uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS]
81 * for KPTI each mm has two address spaces and thus needs two
82 * PCID values, but we can still do with a single ASID denomination
83 * for each mm. Corresponds to kPCID + 2048.
84 *
85 */
86
87/* There are 12 bits of space for ASIDS in CR3 */
88#define CR3_HW_ASID_BITS 12
89
90/*
91 * When enabled, PAGE_TABLE_ISOLATION consumes a single bit for
92 * user/kernel switches
93 */
94#ifdef CONFIG_PAGE_TABLE_ISOLATION
95# define PTI_CONSUMED_PCID_BITS 1
96#else
97# define PTI_CONSUMED_PCID_BITS 0
98#endif
99
100#define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
101
102/*
103 * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid. -1 below to account
104 * for them being zero-based. Another -1 is because PCID 0 is reserved for
105 * use by non-PCID-aware users.
106 */
107#define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)
108
109/*
110 * Given @asid, compute kPCID
111 */
112static inline u16 kern_pcid(u16 asid)
113{
114 VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
115
116#ifdef CONFIG_PAGE_TABLE_ISOLATION
117 /*
118 * Make sure that the dynamic ASID space does not conflict with the
119 * bit we are using to switch between user and kernel ASIDs.
120 */
121 BUILD_BUG_ON(TLB_NR_DYN_ASIDS >= (1 << X86_CR3_PTI_PCID_USER_BIT));
122
123 /*
124 * The ASID being passed in here should have respected the
125 * MAX_ASID_AVAILABLE and thus never have the switch bit set.
126 */
127 VM_WARN_ON_ONCE(asid & (1 << X86_CR3_PTI_PCID_USER_BIT));
128#endif
129 /*
130 * The dynamically-assigned ASIDs that get passed in are small
131 * (<TLB_NR_DYN_ASIDS). They never have the high switch bit set,
132 * so do not bother to clear it.
133 *
134 * If PCID is on, ASID-aware code paths put the ASID+1 into the
135 * PCID bits. This serves two purposes. It prevents a nasty
136 * situation in which PCID-unaware code saves CR3, loads some other
137 * value (with PCID == 0), and then restores CR3, thus corrupting
138 * the TLB for ASID 0 if the saved ASID was nonzero. It also means
139 * that any bugs involving loading a PCID-enabled CR3 with
140 * CR4.PCIDE off will trigger deterministically.
141 */
142 return asid + 1;
143}
144
145/*
146 * Given @asid, compute uPCID
147 */
148static inline u16 user_pcid(u16 asid)
149{
150 u16 ret = kern_pcid(asid);
151#ifdef CONFIG_PAGE_TABLE_ISOLATION
152 ret |= 1 << X86_CR3_PTI_PCID_USER_BIT;
153#endif
154 return ret;
155}
156
157static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)
158{
159 if (static_cpu_has(X86_FEATURE_PCID)) {
160 return __sme_pa(pgd) | kern_pcid(asid);
161 } else {
162 VM_WARN_ON_ONCE(asid != 0);
163 return __sme_pa(pgd);
164 }
165}
166
167static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
168{
169 VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
170 /*
171 * Use boot_cpu_has() instead of this_cpu_has() as this function
172 * might be called during early boot. This should work even after
173 * boot because all CPU's the have same capabilities:
174 */
175 VM_WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_PCID));
176 return __sme_pa(pgd) | kern_pcid(asid) | CR3_NOFLUSH;
177}
178
179/*
180 * We get here when we do something requiring a TLB invalidation
181 * but could not go invalidate all of the contexts. We do the
182 * necessary invalidation by clearing out the 'ctx_id' which
183 * forces a TLB flush when the context is loaded.
184 */
185static void clear_asid_other(void)
186{
187 u16 asid;
188
189 /*
190 * This is only expected to be set if we have disabled
191 * kernel _PAGE_GLOBAL pages.
192 */
193 if (!static_cpu_has(X86_FEATURE_PTI)) {
194 WARN_ON_ONCE(1);
195 return;
196 }
197
198 for (asid = 0; asid < TLB_NR_DYN_ASIDS; asid++) {
199 /* Do not need to flush the current asid */
200 if (asid == this_cpu_read(cpu_tlbstate.loaded_mm_asid))
201 continue;
202 /*
203 * Make sure the next time we go to switch to
204 * this asid, we do a flush:
205 */
206 this_cpu_write(cpu_tlbstate.ctxs[asid].ctx_id, 0);
207 }
208 this_cpu_write(cpu_tlbstate.invalidate_other, false);
209}
210
211atomic64_t last_mm_ctx_id = ATOMIC64_INIT(1);
212
213
214static void choose_new_asid(struct mm_struct *next, u64 next_tlb_gen,
215 u16 *new_asid, bool *need_flush)
216{
217 u16 asid;
218
219 if (!static_cpu_has(X86_FEATURE_PCID)) {
220 *new_asid = 0;
221 *need_flush = true;
222 return;
223 }
224
225 if (this_cpu_read(cpu_tlbstate.invalidate_other))
226 clear_asid_other();
227
228 for (asid = 0; asid < TLB_NR_DYN_ASIDS; asid++) {
229 if (this_cpu_read(cpu_tlbstate.ctxs[asid].ctx_id) !=
230 next->context.ctx_id)
231 continue;
232
233 *new_asid = asid;
234 *need_flush = (this_cpu_read(cpu_tlbstate.ctxs[asid].tlb_gen) <
235 next_tlb_gen);
236 return;
237 }
238
239 /*
240 * We don't currently own an ASID slot on this CPU.
241 * Allocate a slot.
242 */
243 *new_asid = this_cpu_add_return(cpu_tlbstate.next_asid, 1) - 1;
244 if (*new_asid >= TLB_NR_DYN_ASIDS) {
245 *new_asid = 0;
246 this_cpu_write(cpu_tlbstate.next_asid, 1);
247 }
248 *need_flush = true;
249}
250
251/*
252 * Given an ASID, flush the corresponding user ASID. We can delay this
253 * until the next time we switch to it.
254 *
255 * See SWITCH_TO_USER_CR3.
256 */
257static inline void invalidate_user_asid(u16 asid)
258{
259 /* There is no user ASID if address space separation is off */
260 if (!IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION))
261 return;
262
263 /*
264 * We only have a single ASID if PCID is off and the CR3
265 * write will have flushed it.
266 */
267 if (!cpu_feature_enabled(X86_FEATURE_PCID))
268 return;
269
270 if (!static_cpu_has(X86_FEATURE_PTI))
271 return;
272
273 __set_bit(kern_pcid(asid),
274 (unsigned long *)this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask));
275}
276
277static void load_new_mm_cr3(pgd_t *pgdir, u16 new_asid, bool need_flush)
278{
279 unsigned long new_mm_cr3;
280
281 if (need_flush) {
282 invalidate_user_asid(new_asid);
283 new_mm_cr3 = build_cr3(pgdir, new_asid);
284 } else {
285 new_mm_cr3 = build_cr3_noflush(pgdir, new_asid);
286 }
287
288 /*
289 * Caution: many callers of this function expect
290 * that load_cr3() is serializing and orders TLB
291 * fills with respect to the mm_cpumask writes.
292 */
293 write_cr3(new_mm_cr3);
294}
295
296void leave_mm(int cpu)
297{
298 struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
299
300 /*
301 * It's plausible that we're in lazy TLB mode while our mm is init_mm.
302 * If so, our callers still expect us to flush the TLB, but there
303 * aren't any user TLB entries in init_mm to worry about.
304 *
305 * This needs to happen before any other sanity checks due to
306 * intel_idle's shenanigans.
307 */
308 if (loaded_mm == &init_mm)
309 return;
310
311 /* Warn if we're not lazy. */
312 WARN_ON(!this_cpu_read(cpu_tlbstate_shared.is_lazy));
313
314 switch_mm(NULL, &init_mm, NULL);
315}
316EXPORT_SYMBOL_GPL(leave_mm);
317
318void switch_mm(struct mm_struct *prev, struct mm_struct *next,
319 struct task_struct *tsk)
320{
321 unsigned long flags;
322
323 local_irq_save(flags);
324 switch_mm_irqs_off(prev, next, tsk);
325 local_irq_restore(flags);
326}
327
328/*
329 * Invoked from return to user/guest by a task that opted-in to L1D
330 * flushing but ended up running on an SMT enabled core due to wrong
331 * affinity settings or CPU hotplug. This is part of the paranoid L1D flush
332 * contract which this task requested.
333 */
334static void l1d_flush_force_sigbus(struct callback_head *ch)
335{
336 force_sig(SIGBUS);
337}
338
339static void l1d_flush_evaluate(unsigned long prev_mm, unsigned long next_mm,
340 struct task_struct *next)
341{
342 /* Flush L1D if the outgoing task requests it */
343 if (prev_mm & LAST_USER_MM_L1D_FLUSH)
344 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
345
346 /* Check whether the incoming task opted in for L1D flush */
347 if (likely(!(next_mm & LAST_USER_MM_L1D_FLUSH)))
348 return;
349
350 /*
351 * Validate that it is not running on an SMT sibling as this would
352 * make the excercise pointless because the siblings share L1D. If
353 * it runs on a SMT sibling, notify it with SIGBUS on return to
354 * user/guest
355 */
356 if (this_cpu_read(cpu_info.smt_active)) {
357 clear_ti_thread_flag(&next->thread_info, TIF_SPEC_L1D_FLUSH);
358 next->l1d_flush_kill.func = l1d_flush_force_sigbus;
359 task_work_add(next, &next->l1d_flush_kill, TWA_RESUME);
360 }
361}
362
363static unsigned long mm_mangle_tif_spec_bits(struct task_struct *next)
364{
365 unsigned long next_tif = read_task_thread_flags(next);
366 unsigned long spec_bits = (next_tif >> TIF_SPEC_IB) & LAST_USER_MM_SPEC_MASK;
367
368 /*
369 * Ensure that the bit shift above works as expected and the two flags
370 * end up in bit 0 and 1.
371 */
372 BUILD_BUG_ON(TIF_SPEC_L1D_FLUSH != TIF_SPEC_IB + 1);
373
374 return (unsigned long)next->mm | spec_bits;
375}
376
377static void cond_mitigation(struct task_struct *next)
378{
379 unsigned long prev_mm, next_mm;
380
381 if (!next || !next->mm)
382 return;
383
384 next_mm = mm_mangle_tif_spec_bits(next);
385 prev_mm = this_cpu_read(cpu_tlbstate.last_user_mm_spec);
386
387 /*
388 * Avoid user/user BTB poisoning by flushing the branch predictor
389 * when switching between processes. This stops one process from
390 * doing Spectre-v2 attacks on another.
391 *
392 * Both, the conditional and the always IBPB mode use the mm
393 * pointer to avoid the IBPB when switching between tasks of the
394 * same process. Using the mm pointer instead of mm->context.ctx_id
395 * opens a hypothetical hole vs. mm_struct reuse, which is more or
396 * less impossible to control by an attacker. Aside of that it
397 * would only affect the first schedule so the theoretically
398 * exposed data is not really interesting.
399 */
400 if (static_branch_likely(&switch_mm_cond_ibpb)) {
401 /*
402 * This is a bit more complex than the always mode because
403 * it has to handle two cases:
404 *
405 * 1) Switch from a user space task (potential attacker)
406 * which has TIF_SPEC_IB set to a user space task
407 * (potential victim) which has TIF_SPEC_IB not set.
408 *
409 * 2) Switch from a user space task (potential attacker)
410 * which has TIF_SPEC_IB not set to a user space task
411 * (potential victim) which has TIF_SPEC_IB set.
412 *
413 * This could be done by unconditionally issuing IBPB when
414 * a task which has TIF_SPEC_IB set is either scheduled in
415 * or out. Though that results in two flushes when:
416 *
417 * - the same user space task is scheduled out and later
418 * scheduled in again and only a kernel thread ran in
419 * between.
420 *
421 * - a user space task belonging to the same process is
422 * scheduled in after a kernel thread ran in between
423 *
424 * - a user space task belonging to the same process is
425 * scheduled in immediately.
426 *
427 * Optimize this with reasonably small overhead for the
428 * above cases. Mangle the TIF_SPEC_IB bit into the mm
429 * pointer of the incoming task which is stored in
430 * cpu_tlbstate.last_user_mm_spec for comparison.
431 *
432 * Issue IBPB only if the mm's are different and one or
433 * both have the IBPB bit set.
434 */
435 if (next_mm != prev_mm &&
436 (next_mm | prev_mm) & LAST_USER_MM_IBPB)
437 indirect_branch_prediction_barrier();
438 }
439
440 if (static_branch_unlikely(&switch_mm_always_ibpb)) {
441 /*
442 * Only flush when switching to a user space task with a
443 * different context than the user space task which ran
444 * last on this CPU.
445 */
446 if ((prev_mm & ~LAST_USER_MM_SPEC_MASK) !=
447 (unsigned long)next->mm)
448 indirect_branch_prediction_barrier();
449 }
450
451 if (static_branch_unlikely(&switch_mm_cond_l1d_flush)) {
452 /*
453 * Flush L1D when the outgoing task requested it and/or
454 * check whether the incoming task requested L1D flushing
455 * and ended up on an SMT sibling.
456 */
457 if (unlikely((prev_mm | next_mm) & LAST_USER_MM_L1D_FLUSH))
458 l1d_flush_evaluate(prev_mm, next_mm, next);
459 }
460
461 this_cpu_write(cpu_tlbstate.last_user_mm_spec, next_mm);
462}
463
464#ifdef CONFIG_PERF_EVENTS
465static inline void cr4_update_pce_mm(struct mm_struct *mm)
466{
467 if (static_branch_unlikely(&rdpmc_always_available_key) ||
468 (!static_branch_unlikely(&rdpmc_never_available_key) &&
469 atomic_read(&mm->context.perf_rdpmc_allowed))) {
470 /*
471 * Clear the existing dirty counters to
472 * prevent the leak for an RDPMC task.
473 */
474 perf_clear_dirty_counters();
475 cr4_set_bits_irqsoff(X86_CR4_PCE);
476 } else
477 cr4_clear_bits_irqsoff(X86_CR4_PCE);
478}
479
480void cr4_update_pce(void *ignored)
481{
482 cr4_update_pce_mm(this_cpu_read(cpu_tlbstate.loaded_mm));
483}
484
485#else
486static inline void cr4_update_pce_mm(struct mm_struct *mm) { }
487#endif
488
489void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
490 struct task_struct *tsk)
491{
492 struct mm_struct *real_prev = this_cpu_read(cpu_tlbstate.loaded_mm);
493 u16 prev_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
494 bool was_lazy = this_cpu_read(cpu_tlbstate_shared.is_lazy);
495 unsigned cpu = smp_processor_id();
496 u64 next_tlb_gen;
497 bool need_flush;
498 u16 new_asid;
499
500 /*
501 * NB: The scheduler will call us with prev == next when switching
502 * from lazy TLB mode to normal mode if active_mm isn't changing.
503 * When this happens, we don't assume that CR3 (and hence
504 * cpu_tlbstate.loaded_mm) matches next.
505 *
506 * NB: leave_mm() calls us with prev == NULL and tsk == NULL.
507 */
508
509 /* We don't want flush_tlb_func() to run concurrently with us. */
510 if (IS_ENABLED(CONFIG_PROVE_LOCKING))
511 WARN_ON_ONCE(!irqs_disabled());
512
513 /*
514 * Verify that CR3 is what we think it is. This will catch
515 * hypothetical buggy code that directly switches to swapper_pg_dir
516 * without going through leave_mm() / switch_mm_irqs_off() or that
517 * does something like write_cr3(read_cr3_pa()).
518 *
519 * Only do this check if CONFIG_DEBUG_VM=y because __read_cr3()
520 * isn't free.
521 */
522#ifdef CONFIG_DEBUG_VM
523 if (WARN_ON_ONCE(__read_cr3() != build_cr3(real_prev->pgd, prev_asid))) {
524 /*
525 * If we were to BUG here, we'd be very likely to kill
526 * the system so hard that we don't see the call trace.
527 * Try to recover instead by ignoring the error and doing
528 * a global flush to minimize the chance of corruption.
529 *
530 * (This is far from being a fully correct recovery.
531 * Architecturally, the CPU could prefetch something
532 * back into an incorrect ASID slot and leave it there
533 * to cause trouble down the road. It's better than
534 * nothing, though.)
535 */
536 __flush_tlb_all();
537 }
538#endif
539 if (was_lazy)
540 this_cpu_write(cpu_tlbstate_shared.is_lazy, false);
541
542 /*
543 * The membarrier system call requires a full memory barrier and
544 * core serialization before returning to user-space, after
545 * storing to rq->curr, when changing mm. This is because
546 * membarrier() sends IPIs to all CPUs that are in the target mm
547 * to make them issue memory barriers. However, if another CPU
548 * switches to/from the target mm concurrently with
549 * membarrier(), it can cause that CPU not to receive an IPI
550 * when it really should issue a memory barrier. Writing to CR3
551 * provides that full memory barrier and core serializing
552 * instruction.
553 */
554 if (real_prev == next) {
555 VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) !=
556 next->context.ctx_id);
557
558 /*
559 * Even in lazy TLB mode, the CPU should stay set in the
560 * mm_cpumask. The TLB shootdown code can figure out from
561 * cpu_tlbstate_shared.is_lazy whether or not to send an IPI.
562 */
563 if (WARN_ON_ONCE(real_prev != &init_mm &&
564 !cpumask_test_cpu(cpu, mm_cpumask(next))))
565 cpumask_set_cpu(cpu, mm_cpumask(next));
566
567 /*
568 * If the CPU is not in lazy TLB mode, we are just switching
569 * from one thread in a process to another thread in the same
570 * process. No TLB flush required.
571 */
572 if (!was_lazy)
573 return;
574
575 /*
576 * Read the tlb_gen to check whether a flush is needed.
577 * If the TLB is up to date, just use it.
578 * The barrier synchronizes with the tlb_gen increment in
579 * the TLB shootdown code.
580 */
581 smp_mb();
582 next_tlb_gen = atomic64_read(&next->context.tlb_gen);
583 if (this_cpu_read(cpu_tlbstate.ctxs[prev_asid].tlb_gen) ==
584 next_tlb_gen)
585 return;
586
587 /*
588 * TLB contents went out of date while we were in lazy
589 * mode. Fall through to the TLB switching code below.
590 */
591 new_asid = prev_asid;
592 need_flush = true;
593 } else {
594 /*
595 * Apply process to process speculation vulnerability
596 * mitigations if applicable.
597 */
598 cond_mitigation(tsk);
599
600 /*
601 * Stop remote flushes for the previous mm.
602 * Skip kernel threads; we never send init_mm TLB flushing IPIs,
603 * but the bitmap manipulation can cause cache line contention.
604 */
605 if (real_prev != &init_mm) {
606 VM_WARN_ON_ONCE(!cpumask_test_cpu(cpu,
607 mm_cpumask(real_prev)));
608 cpumask_clear_cpu(cpu, mm_cpumask(real_prev));
609 }
610
611 /*
612 * Start remote flushes and then read tlb_gen.
613 */
614 if (next != &init_mm)
615 cpumask_set_cpu(cpu, mm_cpumask(next));
616 next_tlb_gen = atomic64_read(&next->context.tlb_gen);
617
618 choose_new_asid(next, next_tlb_gen, &new_asid, &need_flush);
619
620 /* Let nmi_uaccess_okay() know that we're changing CR3. */
621 this_cpu_write(cpu_tlbstate.loaded_mm, LOADED_MM_SWITCHING);
622 barrier();
623 }
624
625 if (need_flush) {
626 this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id);
627 this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen);
628 load_new_mm_cr3(next->pgd, new_asid, true);
629
630 trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
631 } else {
632 /* The new ASID is already up to date. */
633 load_new_mm_cr3(next->pgd, new_asid, false);
634
635 trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, 0);
636 }
637
638 /* Make sure we write CR3 before loaded_mm. */
639 barrier();
640
641 this_cpu_write(cpu_tlbstate.loaded_mm, next);
642 this_cpu_write(cpu_tlbstate.loaded_mm_asid, new_asid);
643
644 if (next != real_prev) {
645 cr4_update_pce_mm(next);
646 switch_ldt(real_prev, next);
647 }
648}
649
650/*
651 * Please ignore the name of this function. It should be called
652 * switch_to_kernel_thread().
653 *
654 * enter_lazy_tlb() is a hint from the scheduler that we are entering a
655 * kernel thread or other context without an mm. Acceptable implementations
656 * include doing nothing whatsoever, switching to init_mm, or various clever
657 * lazy tricks to try to minimize TLB flushes.
658 *
659 * The scheduler reserves the right to call enter_lazy_tlb() several times
660 * in a row. It will notify us that we're going back to a real mm by
661 * calling switch_mm_irqs_off().
662 */
663void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
664{
665 if (this_cpu_read(cpu_tlbstate.loaded_mm) == &init_mm)
666 return;
667
668 this_cpu_write(cpu_tlbstate_shared.is_lazy, true);
669}
670
671/*
672 * Call this when reinitializing a CPU. It fixes the following potential
673 * problems:
674 *
675 * - The ASID changed from what cpu_tlbstate thinks it is (most likely
676 * because the CPU was taken down and came back up with CR3's PCID
677 * bits clear. CPU hotplug can do this.
678 *
679 * - The TLB contains junk in slots corresponding to inactive ASIDs.
680 *
681 * - The CPU went so far out to lunch that it may have missed a TLB
682 * flush.
683 */
684void initialize_tlbstate_and_flush(void)
685{
686 int i;
687 struct mm_struct *mm = this_cpu_read(cpu_tlbstate.loaded_mm);
688 u64 tlb_gen = atomic64_read(&init_mm.context.tlb_gen);
689 unsigned long cr3 = __read_cr3();
690
691 /* Assert that CR3 already references the right mm. */
692 WARN_ON((cr3 & CR3_ADDR_MASK) != __pa(mm->pgd));
693
694 /*
695 * Assert that CR4.PCIDE is set if needed. (CR4.PCIDE initialization
696 * doesn't work like other CR4 bits because it can only be set from
697 * long mode.)
698 */
699 WARN_ON(boot_cpu_has(X86_FEATURE_PCID) &&
700 !(cr4_read_shadow() & X86_CR4_PCIDE));
701
702 /* Force ASID 0 and force a TLB flush. */
703 write_cr3(build_cr3(mm->pgd, 0));
704
705 /* Reinitialize tlbstate. */
706 this_cpu_write(cpu_tlbstate.last_user_mm_spec, LAST_USER_MM_INIT);
707 this_cpu_write(cpu_tlbstate.loaded_mm_asid, 0);
708 this_cpu_write(cpu_tlbstate.next_asid, 1);
709 this_cpu_write(cpu_tlbstate.ctxs[0].ctx_id, mm->context.ctx_id);
710 this_cpu_write(cpu_tlbstate.ctxs[0].tlb_gen, tlb_gen);
711
712 for (i = 1; i < TLB_NR_DYN_ASIDS; i++)
713 this_cpu_write(cpu_tlbstate.ctxs[i].ctx_id, 0);
714}
715
716/*
717 * flush_tlb_func()'s memory ordering requirement is that any
718 * TLB fills that happen after we flush the TLB are ordered after we
719 * read active_mm's tlb_gen. We don't need any explicit barriers
720 * because all x86 flush operations are serializing and the
721 * atomic64_read operation won't be reordered by the compiler.
722 */
723static void flush_tlb_func(void *info)
724{
725 /*
726 * We have three different tlb_gen values in here. They are:
727 *
728 * - mm_tlb_gen: the latest generation.
729 * - local_tlb_gen: the generation that this CPU has already caught
730 * up to.
731 * - f->new_tlb_gen: the generation that the requester of the flush
732 * wants us to catch up to.
733 */
734 const struct flush_tlb_info *f = info;
735 struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
736 u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
737 u64 local_tlb_gen = this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen);
738 bool local = smp_processor_id() == f->initiating_cpu;
739 unsigned long nr_invalidate = 0;
740 u64 mm_tlb_gen;
741
742 /* This code cannot presently handle being reentered. */
743 VM_WARN_ON(!irqs_disabled());
744
745 if (!local) {
746 inc_irq_stat(irq_tlb_count);
747 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
748
749 /* Can only happen on remote CPUs */
750 if (f->mm && f->mm != loaded_mm)
751 return;
752 }
753
754 if (unlikely(loaded_mm == &init_mm))
755 return;
756
757 VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].ctx_id) !=
758 loaded_mm->context.ctx_id);
759
760 if (this_cpu_read(cpu_tlbstate_shared.is_lazy)) {
761 /*
762 * We're in lazy mode. We need to at least flush our
763 * paging-structure cache to avoid speculatively reading
764 * garbage into our TLB. Since switching to init_mm is barely
765 * slower than a minimal flush, just switch to init_mm.
766 *
767 * This should be rare, with native_flush_tlb_multi() skipping
768 * IPIs to lazy TLB mode CPUs.
769 */
770 switch_mm_irqs_off(NULL, &init_mm, NULL);
771 return;
772 }
773
774 if (unlikely(f->new_tlb_gen != TLB_GENERATION_INVALID &&
775 f->new_tlb_gen <= local_tlb_gen)) {
776 /*
777 * The TLB is already up to date in respect to f->new_tlb_gen.
778 * While the core might be still behind mm_tlb_gen, checking
779 * mm_tlb_gen unnecessarily would have negative caching effects
780 * so avoid it.
781 */
782 return;
783 }
784
785 /*
786 * Defer mm_tlb_gen reading as long as possible to avoid cache
787 * contention.
788 */
789 mm_tlb_gen = atomic64_read(&loaded_mm->context.tlb_gen);
790
791 if (unlikely(local_tlb_gen == mm_tlb_gen)) {
792 /*
793 * There's nothing to do: we're already up to date. This can
794 * happen if two concurrent flushes happen -- the first flush to
795 * be handled can catch us all the way up, leaving no work for
796 * the second flush.
797 */
798 goto done;
799 }
800
801 WARN_ON_ONCE(local_tlb_gen > mm_tlb_gen);
802 WARN_ON_ONCE(f->new_tlb_gen > mm_tlb_gen);
803
804 /*
805 * If we get to this point, we know that our TLB is out of date.
806 * This does not strictly imply that we need to flush (it's
807 * possible that f->new_tlb_gen <= local_tlb_gen), but we're
808 * going to need to flush in the very near future, so we might
809 * as well get it over with.
810 *
811 * The only question is whether to do a full or partial flush.
812 *
813 * We do a partial flush if requested and two extra conditions
814 * are met:
815 *
816 * 1. f->new_tlb_gen == local_tlb_gen + 1. We have an invariant that
817 * we've always done all needed flushes to catch up to
818 * local_tlb_gen. If, for example, local_tlb_gen == 2 and
819 * f->new_tlb_gen == 3, then we know that the flush needed to bring
820 * us up to date for tlb_gen 3 is the partial flush we're
821 * processing.
822 *
823 * As an example of why this check is needed, suppose that there
824 * are two concurrent flushes. The first is a full flush that
825 * changes context.tlb_gen from 1 to 2. The second is a partial
826 * flush that changes context.tlb_gen from 2 to 3. If they get
827 * processed on this CPU in reverse order, we'll see
828 * local_tlb_gen == 1, mm_tlb_gen == 3, and end != TLB_FLUSH_ALL.
829 * If we were to use __flush_tlb_one_user() and set local_tlb_gen to
830 * 3, we'd be break the invariant: we'd update local_tlb_gen above
831 * 1 without the full flush that's needed for tlb_gen 2.
832 *
833 * 2. f->new_tlb_gen == mm_tlb_gen. This is purely an optimization.
834 * Partial TLB flushes are not all that much cheaper than full TLB
835 * flushes, so it seems unlikely that it would be a performance win
836 * to do a partial flush if that won't bring our TLB fully up to
837 * date. By doing a full flush instead, we can increase
838 * local_tlb_gen all the way to mm_tlb_gen and we can probably
839 * avoid another flush in the very near future.
840 */
841 if (f->end != TLB_FLUSH_ALL &&
842 f->new_tlb_gen == local_tlb_gen + 1 &&
843 f->new_tlb_gen == mm_tlb_gen) {
844 /* Partial flush */
845 unsigned long addr = f->start;
846
847 /* Partial flush cannot have invalid generations */
848 VM_WARN_ON(f->new_tlb_gen == TLB_GENERATION_INVALID);
849
850 /* Partial flush must have valid mm */
851 VM_WARN_ON(f->mm == NULL);
852
853 nr_invalidate = (f->end - f->start) >> f->stride_shift;
854
855 while (addr < f->end) {
856 flush_tlb_one_user(addr);
857 addr += 1UL << f->stride_shift;
858 }
859 if (local)
860 count_vm_tlb_events(NR_TLB_LOCAL_FLUSH_ONE, nr_invalidate);
861 } else {
862 /* Full flush. */
863 nr_invalidate = TLB_FLUSH_ALL;
864
865 flush_tlb_local();
866 if (local)
867 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
868 }
869
870 /* Both paths above update our state to mm_tlb_gen. */
871 this_cpu_write(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen, mm_tlb_gen);
872
873 /* Tracing is done in a unified manner to reduce the code size */
874done:
875 trace_tlb_flush(!local ? TLB_REMOTE_SHOOTDOWN :
876 (f->mm == NULL) ? TLB_LOCAL_SHOOTDOWN :
877 TLB_LOCAL_MM_SHOOTDOWN,
878 nr_invalidate);
879}
880
881static bool tlb_is_not_lazy(int cpu, void *data)
882{
883 return !per_cpu(cpu_tlbstate_shared.is_lazy, cpu);
884}
885
886DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state_shared, cpu_tlbstate_shared);
887EXPORT_PER_CPU_SYMBOL(cpu_tlbstate_shared);
888
889STATIC_NOPV void native_flush_tlb_multi(const struct cpumask *cpumask,
890 const struct flush_tlb_info *info)
891{
892 /*
893 * Do accounting and tracing. Note that there are (and have always been)
894 * cases in which a remote TLB flush will be traced, but eventually
895 * would not happen.
896 */
897 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
898 if (info->end == TLB_FLUSH_ALL)
899 trace_tlb_flush(TLB_REMOTE_SEND_IPI, TLB_FLUSH_ALL);
900 else
901 trace_tlb_flush(TLB_REMOTE_SEND_IPI,
902 (info->end - info->start) >> PAGE_SHIFT);
903
904 /*
905 * If no page tables were freed, we can skip sending IPIs to
906 * CPUs in lazy TLB mode. They will flush the CPU themselves
907 * at the next context switch.
908 *
909 * However, if page tables are getting freed, we need to send the
910 * IPI everywhere, to prevent CPUs in lazy TLB mode from tripping
911 * up on the new contents of what used to be page tables, while
912 * doing a speculative memory access.
913 */
914 if (info->freed_tables)
915 on_each_cpu_mask(cpumask, flush_tlb_func, (void *)info, true);
916 else
917 on_each_cpu_cond_mask(tlb_is_not_lazy, flush_tlb_func,
918 (void *)info, 1, cpumask);
919}
920
921void flush_tlb_multi(const struct cpumask *cpumask,
922 const struct flush_tlb_info *info)
923{
924 __flush_tlb_multi(cpumask, info);
925}
926
927/*
928 * See Documentation/x86/tlb.rst for details. We choose 33
929 * because it is large enough to cover the vast majority (at
930 * least 95%) of allocations, and is small enough that we are
931 * confident it will not cause too much overhead. Each single
932 * flush is about 100 ns, so this caps the maximum overhead at
933 * _about_ 3,000 ns.
934 *
935 * This is in units of pages.
936 */
937unsigned long tlb_single_page_flush_ceiling __read_mostly = 33;
938
939static DEFINE_PER_CPU_SHARED_ALIGNED(struct flush_tlb_info, flush_tlb_info);
940
941#ifdef CONFIG_DEBUG_VM
942static DEFINE_PER_CPU(unsigned int, flush_tlb_info_idx);
943#endif
944
945static struct flush_tlb_info *get_flush_tlb_info(struct mm_struct *mm,
946 unsigned long start, unsigned long end,
947 unsigned int stride_shift, bool freed_tables,
948 u64 new_tlb_gen)
949{
950 struct flush_tlb_info *info = this_cpu_ptr(&flush_tlb_info);
951
952#ifdef CONFIG_DEBUG_VM
953 /*
954 * Ensure that the following code is non-reentrant and flush_tlb_info
955 * is not overwritten. This means no TLB flushing is initiated by
956 * interrupt handlers and machine-check exception handlers.
957 */
958 BUG_ON(this_cpu_inc_return(flush_tlb_info_idx) != 1);
959#endif
960
961 info->start = start;
962 info->end = end;
963 info->mm = mm;
964 info->stride_shift = stride_shift;
965 info->freed_tables = freed_tables;
966 info->new_tlb_gen = new_tlb_gen;
967 info->initiating_cpu = smp_processor_id();
968
969 return info;
970}
971
972static void put_flush_tlb_info(void)
973{
974#ifdef CONFIG_DEBUG_VM
975 /* Complete reentrancy prevention checks */
976 barrier();
977 this_cpu_dec(flush_tlb_info_idx);
978#endif
979}
980
981void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
982 unsigned long end, unsigned int stride_shift,
983 bool freed_tables)
984{
985 struct flush_tlb_info *info;
986 u64 new_tlb_gen;
987 int cpu;
988
989 cpu = get_cpu();
990
991 /* Should we flush just the requested range? */
992 if ((end == TLB_FLUSH_ALL) ||
993 ((end - start) >> stride_shift) > tlb_single_page_flush_ceiling) {
994 start = 0;
995 end = TLB_FLUSH_ALL;
996 }
997
998 /* This is also a barrier that synchronizes with switch_mm(). */
999 new_tlb_gen = inc_mm_tlb_gen(mm);
1000
1001 info = get_flush_tlb_info(mm, start, end, stride_shift, freed_tables,
1002 new_tlb_gen);
1003
1004 /*
1005 * flush_tlb_multi() is not optimized for the common case in which only
1006 * a local TLB flush is needed. Optimize this use-case by calling
1007 * flush_tlb_func_local() directly in this case.
1008 */
1009 if (cpumask_any_but(mm_cpumask(mm), cpu) < nr_cpu_ids) {
1010 flush_tlb_multi(mm_cpumask(mm), info);
1011 } else if (mm == this_cpu_read(cpu_tlbstate.loaded_mm)) {
1012 lockdep_assert_irqs_enabled();
1013 local_irq_disable();
1014 flush_tlb_func(info);
1015 local_irq_enable();
1016 }
1017
1018 put_flush_tlb_info();
1019 put_cpu();
1020}
1021
1022
1023static void do_flush_tlb_all(void *info)
1024{
1025 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
1026 __flush_tlb_all();
1027}
1028
1029void flush_tlb_all(void)
1030{
1031 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
1032 on_each_cpu(do_flush_tlb_all, NULL, 1);
1033}
1034
1035static void do_kernel_range_flush(void *info)
1036{
1037 struct flush_tlb_info *f = info;
1038 unsigned long addr;
1039
1040 /* flush range by one by one 'invlpg' */
1041 for (addr = f->start; addr < f->end; addr += PAGE_SIZE)
1042 flush_tlb_one_kernel(addr);
1043}
1044
1045void flush_tlb_kernel_range(unsigned long start, unsigned long end)
1046{
1047 /* Balance as user space task's flush, a bit conservative */
1048 if (end == TLB_FLUSH_ALL ||
1049 (end - start) > tlb_single_page_flush_ceiling << PAGE_SHIFT) {
1050 on_each_cpu(do_flush_tlb_all, NULL, 1);
1051 } else {
1052 struct flush_tlb_info *info;
1053
1054 preempt_disable();
1055 info = get_flush_tlb_info(NULL, start, end, 0, false,
1056 TLB_GENERATION_INVALID);
1057
1058 on_each_cpu(do_kernel_range_flush, info, 1);
1059
1060 put_flush_tlb_info();
1061 preempt_enable();
1062 }
1063}
1064
1065/*
1066 * This can be used from process context to figure out what the value of
1067 * CR3 is without needing to do a (slow) __read_cr3().
1068 *
1069 * It's intended to be used for code like KVM that sneakily changes CR3
1070 * and needs to restore it. It needs to be used very carefully.
1071 */
1072unsigned long __get_current_cr3_fast(void)
1073{
1074 unsigned long cr3 = build_cr3(this_cpu_read(cpu_tlbstate.loaded_mm)->pgd,
1075 this_cpu_read(cpu_tlbstate.loaded_mm_asid));
1076
1077 /* For now, be very restrictive about when this can be called. */
1078 VM_WARN_ON(in_nmi() || preemptible());
1079
1080 VM_BUG_ON(cr3 != __read_cr3());
1081 return cr3;
1082}
1083EXPORT_SYMBOL_GPL(__get_current_cr3_fast);
1084
1085/*
1086 * Flush one page in the kernel mapping
1087 */
1088void flush_tlb_one_kernel(unsigned long addr)
1089{
1090 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
1091
1092 /*
1093 * If PTI is off, then __flush_tlb_one_user() is just INVLPG or its
1094 * paravirt equivalent. Even with PCID, this is sufficient: we only
1095 * use PCID if we also use global PTEs for the kernel mapping, and
1096 * INVLPG flushes global translations across all address spaces.
1097 *
1098 * If PTI is on, then the kernel is mapped with non-global PTEs, and
1099 * __flush_tlb_one_user() will flush the given address for the current
1100 * kernel address space and for its usermode counterpart, but it does
1101 * not flush it for other address spaces.
1102 */
1103 flush_tlb_one_user(addr);
1104
1105 if (!static_cpu_has(X86_FEATURE_PTI))
1106 return;
1107
1108 /*
1109 * See above. We need to propagate the flush to all other address
1110 * spaces. In principle, we only need to propagate it to kernelmode
1111 * address spaces, but the extra bookkeeping we would need is not
1112 * worth it.
1113 */
1114 this_cpu_write(cpu_tlbstate.invalidate_other, true);
1115}
1116
1117/*
1118 * Flush one page in the user mapping
1119 */
1120STATIC_NOPV void native_flush_tlb_one_user(unsigned long addr)
1121{
1122 u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
1123
1124 asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
1125
1126 if (!static_cpu_has(X86_FEATURE_PTI))
1127 return;
1128
1129 /*
1130 * Some platforms #GP if we call invpcid(type=1/2) before CR4.PCIDE=1.
1131 * Just use invalidate_user_asid() in case we are called early.
1132 */
1133 if (!this_cpu_has(X86_FEATURE_INVPCID_SINGLE))
1134 invalidate_user_asid(loaded_mm_asid);
1135 else
1136 invpcid_flush_one(user_pcid(loaded_mm_asid), addr);
1137}
1138
1139void flush_tlb_one_user(unsigned long addr)
1140{
1141 __flush_tlb_one_user(addr);
1142}
1143
1144/*
1145 * Flush everything
1146 */
1147STATIC_NOPV void native_flush_tlb_global(void)
1148{
1149 unsigned long flags;
1150
1151 if (static_cpu_has(X86_FEATURE_INVPCID)) {
1152 /*
1153 * Using INVPCID is considerably faster than a pair of writes
1154 * to CR4 sandwiched inside an IRQ flag save/restore.
1155 *
1156 * Note, this works with CR4.PCIDE=0 or 1.
1157 */
1158 invpcid_flush_all();
1159 return;
1160 }
1161
1162 /*
1163 * Read-modify-write to CR4 - protect it from preemption and
1164 * from interrupts. (Use the raw variant because this code can
1165 * be called from deep inside debugging code.)
1166 */
1167 raw_local_irq_save(flags);
1168
1169 __native_tlb_flush_global(this_cpu_read(cpu_tlbstate.cr4));
1170
1171 raw_local_irq_restore(flags);
1172}
1173
1174/*
1175 * Flush the entire current user mapping
1176 */
1177STATIC_NOPV void native_flush_tlb_local(void)
1178{
1179 /*
1180 * Preemption or interrupts must be disabled to protect the access
1181 * to the per CPU variable and to prevent being preempted between
1182 * read_cr3() and write_cr3().
1183 */
1184 WARN_ON_ONCE(preemptible());
1185
1186 invalidate_user_asid(this_cpu_read(cpu_tlbstate.loaded_mm_asid));
1187
1188 /* If current->mm == NULL then the read_cr3() "borrows" an mm */
1189 native_write_cr3(__native_read_cr3());
1190}
1191
1192void flush_tlb_local(void)
1193{
1194 __flush_tlb_local();
1195}
1196
1197/*
1198 * Flush everything
1199 */
1200void __flush_tlb_all(void)
1201{
1202 /*
1203 * This is to catch users with enabled preemption and the PGE feature
1204 * and don't trigger the warning in __native_flush_tlb().
1205 */
1206 VM_WARN_ON_ONCE(preemptible());
1207
1208 if (boot_cpu_has(X86_FEATURE_PGE)) {
1209 __flush_tlb_global();
1210 } else {
1211 /*
1212 * !PGE -> !PCID (setup_pcid()), thus every flush is total.
1213 */
1214 flush_tlb_local();
1215 }
1216}
1217EXPORT_SYMBOL_GPL(__flush_tlb_all);
1218
1219void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch)
1220{
1221 struct flush_tlb_info *info;
1222
1223 int cpu = get_cpu();
1224
1225 info = get_flush_tlb_info(NULL, 0, TLB_FLUSH_ALL, 0, false,
1226 TLB_GENERATION_INVALID);
1227 /*
1228 * flush_tlb_multi() is not optimized for the common case in which only
1229 * a local TLB flush is needed. Optimize this use-case by calling
1230 * flush_tlb_func_local() directly in this case.
1231 */
1232 if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) {
1233 flush_tlb_multi(&batch->cpumask, info);
1234 } else if (cpumask_test_cpu(cpu, &batch->cpumask)) {
1235 lockdep_assert_irqs_enabled();
1236 local_irq_disable();
1237 flush_tlb_func(info);
1238 local_irq_enable();
1239 }
1240
1241 cpumask_clear(&batch->cpumask);
1242
1243 put_flush_tlb_info();
1244 put_cpu();
1245}
1246
1247/*
1248 * Blindly accessing user memory from NMI context can be dangerous
1249 * if we're in the middle of switching the current user task or
1250 * switching the loaded mm. It can also be dangerous if we
1251 * interrupted some kernel code that was temporarily using a
1252 * different mm.
1253 */
1254bool nmi_uaccess_okay(void)
1255{
1256 struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
1257 struct mm_struct *current_mm = current->mm;
1258
1259 VM_WARN_ON_ONCE(!loaded_mm);
1260
1261 /*
1262 * The condition we want to check is
1263 * current_mm->pgd == __va(read_cr3_pa()). This may be slow, though,
1264 * if we're running in a VM with shadow paging, and nmi_uaccess_okay()
1265 * is supposed to be reasonably fast.
1266 *
1267 * Instead, we check the almost equivalent but somewhat conservative
1268 * condition below, and we rely on the fact that switch_mm_irqs_off()
1269 * sets loaded_mm to LOADED_MM_SWITCHING before writing to CR3.
1270 */
1271 if (loaded_mm != current_mm)
1272 return false;
1273
1274 VM_WARN_ON_ONCE(current_mm->pgd != __va(read_cr3_pa()));
1275
1276 return true;
1277}
1278
1279static ssize_t tlbflush_read_file(struct file *file, char __user *user_buf,
1280 size_t count, loff_t *ppos)
1281{
1282 char buf[32];
1283 unsigned int len;
1284
1285 len = sprintf(buf, "%ld\n", tlb_single_page_flush_ceiling);
1286 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1287}
1288
1289static ssize_t tlbflush_write_file(struct file *file,
1290 const char __user *user_buf, size_t count, loff_t *ppos)
1291{
1292 char buf[32];
1293 ssize_t len;
1294 int ceiling;
1295
1296 len = min(count, sizeof(buf) - 1);
1297 if (copy_from_user(buf, user_buf, len))
1298 return -EFAULT;
1299
1300 buf[len] = '\0';
1301 if (kstrtoint(buf, 0, &ceiling))
1302 return -EINVAL;
1303
1304 if (ceiling < 0)
1305 return -EINVAL;
1306
1307 tlb_single_page_flush_ceiling = ceiling;
1308 return count;
1309}
1310
1311static const struct file_operations fops_tlbflush = {
1312 .read = tlbflush_read_file,
1313 .write = tlbflush_write_file,
1314 .llseek = default_llseek,
1315};
1316
1317static int __init create_tlb_single_page_flush_ceiling(void)
1318{
1319 debugfs_create_file("tlb_single_page_flush_ceiling", S_IRUSR | S_IWUSR,
1320 arch_debugfs_dir, NULL, &fops_tlbflush);
1321 return 0;
1322}
1323late_initcall(create_tlb_single_page_flush_ceiling);
1// SPDX-License-Identifier: GPL-2.0-only
2#include <linux/init.h>
3
4#include <linux/mm.h>
5#include <linux/spinlock.h>
6#include <linux/smp.h>
7#include <linux/interrupt.h>
8#include <linux/export.h>
9#include <linux/cpu.h>
10#include <linux/debugfs.h>
11#include <linux/sched/smt.h>
12#include <linux/task_work.h>
13#include <linux/mmu_notifier.h>
14#include <linux/mmu_context.h>
15
16#include <asm/tlbflush.h>
17#include <asm/mmu_context.h>
18#include <asm/nospec-branch.h>
19#include <asm/cache.h>
20#include <asm/cacheflush.h>
21#include <asm/apic.h>
22#include <asm/perf_event.h>
23#include <asm/tlb.h>
24
25#include "mm_internal.h"
26
27#ifdef CONFIG_PARAVIRT
28# define STATIC_NOPV
29#else
30# define STATIC_NOPV static
31# define __flush_tlb_local native_flush_tlb_local
32# define __flush_tlb_global native_flush_tlb_global
33# define __flush_tlb_one_user(addr) native_flush_tlb_one_user(addr)
34# define __flush_tlb_multi(msk, info) native_flush_tlb_multi(msk, info)
35#endif
36
37/*
38 * TLB flushing, formerly SMP-only
39 * c/o Linus Torvalds.
40 *
41 * These mean you can really definitely utterly forget about
42 * writing to user space from interrupts. (Its not allowed anyway).
43 *
44 * Optimizations Manfred Spraul <manfred@colorfullife.com>
45 *
46 * More scalable flush, from Andi Kleen
47 *
48 * Implement flush IPI by CALL_FUNCTION_VECTOR, Alex Shi
49 */
50
51/*
52 * Bits to mangle the TIF_SPEC_* state into the mm pointer which is
53 * stored in cpu_tlb_state.last_user_mm_spec.
54 */
55#define LAST_USER_MM_IBPB 0x1UL
56#define LAST_USER_MM_L1D_FLUSH 0x2UL
57#define LAST_USER_MM_SPEC_MASK (LAST_USER_MM_IBPB | LAST_USER_MM_L1D_FLUSH)
58
59/* Bits to set when tlbstate and flush is (re)initialized */
60#define LAST_USER_MM_INIT LAST_USER_MM_IBPB
61
62/*
63 * The x86 feature is called PCID (Process Context IDentifier). It is similar
64 * to what is traditionally called ASID on the RISC processors.
65 *
66 * We don't use the traditional ASID implementation, where each process/mm gets
67 * its own ASID and flush/restart when we run out of ASID space.
68 *
69 * Instead we have a small per-cpu array of ASIDs and cache the last few mm's
70 * that came by on this CPU, allowing cheaper switch_mm between processes on
71 * this CPU.
72 *
73 * We end up with different spaces for different things. To avoid confusion we
74 * use different names for each of them:
75 *
76 * ASID - [0, TLB_NR_DYN_ASIDS-1]
77 * the canonical identifier for an mm
78 *
79 * kPCID - [1, TLB_NR_DYN_ASIDS]
80 * the value we write into the PCID part of CR3; corresponds to the
81 * ASID+1, because PCID 0 is special.
82 *
83 * uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS]
84 * for KPTI each mm has two address spaces and thus needs two
85 * PCID values, but we can still do with a single ASID denomination
86 * for each mm. Corresponds to kPCID + 2048.
87 *
88 */
89
90/*
91 * When enabled, MITIGATION_PAGE_TABLE_ISOLATION consumes a single bit for
92 * user/kernel switches
93 */
94#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
95# define PTI_CONSUMED_PCID_BITS 1
96#else
97# define PTI_CONSUMED_PCID_BITS 0
98#endif
99
100#define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
101
102/*
103 * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid. -1 below to account
104 * for them being zero-based. Another -1 is because PCID 0 is reserved for
105 * use by non-PCID-aware users.
106 */
107#define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)
108
109/*
110 * Given @asid, compute kPCID
111 */
112static inline u16 kern_pcid(u16 asid)
113{
114 VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
115
116#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
117 /*
118 * Make sure that the dynamic ASID space does not conflict with the
119 * bit we are using to switch between user and kernel ASIDs.
120 */
121 BUILD_BUG_ON(TLB_NR_DYN_ASIDS >= (1 << X86_CR3_PTI_PCID_USER_BIT));
122
123 /*
124 * The ASID being passed in here should have respected the
125 * MAX_ASID_AVAILABLE and thus never have the switch bit set.
126 */
127 VM_WARN_ON_ONCE(asid & (1 << X86_CR3_PTI_PCID_USER_BIT));
128#endif
129 /*
130 * The dynamically-assigned ASIDs that get passed in are small
131 * (<TLB_NR_DYN_ASIDS). They never have the high switch bit set,
132 * so do not bother to clear it.
133 *
134 * If PCID is on, ASID-aware code paths put the ASID+1 into the
135 * PCID bits. This serves two purposes. It prevents a nasty
136 * situation in which PCID-unaware code saves CR3, loads some other
137 * value (with PCID == 0), and then restores CR3, thus corrupting
138 * the TLB for ASID 0 if the saved ASID was nonzero. It also means
139 * that any bugs involving loading a PCID-enabled CR3 with
140 * CR4.PCIDE off will trigger deterministically.
141 */
142 return asid + 1;
143}
144
145/*
146 * Given @asid, compute uPCID
147 */
148static inline u16 user_pcid(u16 asid)
149{
150 u16 ret = kern_pcid(asid);
151#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
152 ret |= 1 << X86_CR3_PTI_PCID_USER_BIT;
153#endif
154 return ret;
155}
156
157static inline unsigned long build_cr3(pgd_t *pgd, u16 asid, unsigned long lam)
158{
159 unsigned long cr3 = __sme_pa(pgd) | lam;
160
161 if (static_cpu_has(X86_FEATURE_PCID)) {
162 cr3 |= kern_pcid(asid);
163 } else {
164 VM_WARN_ON_ONCE(asid != 0);
165 }
166
167 return cr3;
168}
169
170static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid,
171 unsigned long lam)
172{
173 /*
174 * Use boot_cpu_has() instead of this_cpu_has() as this function
175 * might be called during early boot. This should work even after
176 * boot because all CPU's the have same capabilities:
177 */
178 VM_WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_PCID));
179 return build_cr3(pgd, asid, lam) | CR3_NOFLUSH;
180}
181
182/*
183 * We get here when we do something requiring a TLB invalidation
184 * but could not go invalidate all of the contexts. We do the
185 * necessary invalidation by clearing out the 'ctx_id' which
186 * forces a TLB flush when the context is loaded.
187 */
188static void clear_asid_other(void)
189{
190 u16 asid;
191
192 /*
193 * This is only expected to be set if we have disabled
194 * kernel _PAGE_GLOBAL pages.
195 */
196 if (!static_cpu_has(X86_FEATURE_PTI)) {
197 WARN_ON_ONCE(1);
198 return;
199 }
200
201 for (asid = 0; asid < TLB_NR_DYN_ASIDS; asid++) {
202 /* Do not need to flush the current asid */
203 if (asid == this_cpu_read(cpu_tlbstate.loaded_mm_asid))
204 continue;
205 /*
206 * Make sure the next time we go to switch to
207 * this asid, we do a flush:
208 */
209 this_cpu_write(cpu_tlbstate.ctxs[asid].ctx_id, 0);
210 }
211 this_cpu_write(cpu_tlbstate.invalidate_other, false);
212}
213
214atomic64_t last_mm_ctx_id = ATOMIC64_INIT(1);
215
216
217static void choose_new_asid(struct mm_struct *next, u64 next_tlb_gen,
218 u16 *new_asid, bool *need_flush)
219{
220 u16 asid;
221
222 if (!static_cpu_has(X86_FEATURE_PCID)) {
223 *new_asid = 0;
224 *need_flush = true;
225 return;
226 }
227
228 if (this_cpu_read(cpu_tlbstate.invalidate_other))
229 clear_asid_other();
230
231 for (asid = 0; asid < TLB_NR_DYN_ASIDS; asid++) {
232 if (this_cpu_read(cpu_tlbstate.ctxs[asid].ctx_id) !=
233 next->context.ctx_id)
234 continue;
235
236 *new_asid = asid;
237 *need_flush = (this_cpu_read(cpu_tlbstate.ctxs[asid].tlb_gen) <
238 next_tlb_gen);
239 return;
240 }
241
242 /*
243 * We don't currently own an ASID slot on this CPU.
244 * Allocate a slot.
245 */
246 *new_asid = this_cpu_add_return(cpu_tlbstate.next_asid, 1) - 1;
247 if (*new_asid >= TLB_NR_DYN_ASIDS) {
248 *new_asid = 0;
249 this_cpu_write(cpu_tlbstate.next_asid, 1);
250 }
251 *need_flush = true;
252}
253
254/*
255 * Given an ASID, flush the corresponding user ASID. We can delay this
256 * until the next time we switch to it.
257 *
258 * See SWITCH_TO_USER_CR3.
259 */
260static inline void invalidate_user_asid(u16 asid)
261{
262 /* There is no user ASID if address space separation is off */
263 if (!IS_ENABLED(CONFIG_MITIGATION_PAGE_TABLE_ISOLATION))
264 return;
265
266 /*
267 * We only have a single ASID if PCID is off and the CR3
268 * write will have flushed it.
269 */
270 if (!cpu_feature_enabled(X86_FEATURE_PCID))
271 return;
272
273 if (!static_cpu_has(X86_FEATURE_PTI))
274 return;
275
276 __set_bit(kern_pcid(asid),
277 (unsigned long *)this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask));
278}
279
280static void load_new_mm_cr3(pgd_t *pgdir, u16 new_asid, unsigned long lam,
281 bool need_flush)
282{
283 unsigned long new_mm_cr3;
284
285 if (need_flush) {
286 invalidate_user_asid(new_asid);
287 new_mm_cr3 = build_cr3(pgdir, new_asid, lam);
288 } else {
289 new_mm_cr3 = build_cr3_noflush(pgdir, new_asid, lam);
290 }
291
292 /*
293 * Caution: many callers of this function expect
294 * that load_cr3() is serializing and orders TLB
295 * fills with respect to the mm_cpumask writes.
296 */
297 write_cr3(new_mm_cr3);
298}
299
300void leave_mm(void)
301{
302 struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
303
304 /*
305 * It's plausible that we're in lazy TLB mode while our mm is init_mm.
306 * If so, our callers still expect us to flush the TLB, but there
307 * aren't any user TLB entries in init_mm to worry about.
308 *
309 * This needs to happen before any other sanity checks due to
310 * intel_idle's shenanigans.
311 */
312 if (loaded_mm == &init_mm)
313 return;
314
315 /* Warn if we're not lazy. */
316 WARN_ON(!this_cpu_read(cpu_tlbstate_shared.is_lazy));
317
318 switch_mm(NULL, &init_mm, NULL);
319}
320EXPORT_SYMBOL_GPL(leave_mm);
321
322void switch_mm(struct mm_struct *prev, struct mm_struct *next,
323 struct task_struct *tsk)
324{
325 unsigned long flags;
326
327 local_irq_save(flags);
328 switch_mm_irqs_off(NULL, next, tsk);
329 local_irq_restore(flags);
330}
331
332/*
333 * Invoked from return to user/guest by a task that opted-in to L1D
334 * flushing but ended up running on an SMT enabled core due to wrong
335 * affinity settings or CPU hotplug. This is part of the paranoid L1D flush
336 * contract which this task requested.
337 */
338static void l1d_flush_force_sigbus(struct callback_head *ch)
339{
340 force_sig(SIGBUS);
341}
342
343static void l1d_flush_evaluate(unsigned long prev_mm, unsigned long next_mm,
344 struct task_struct *next)
345{
346 /* Flush L1D if the outgoing task requests it */
347 if (prev_mm & LAST_USER_MM_L1D_FLUSH)
348 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
349
350 /* Check whether the incoming task opted in for L1D flush */
351 if (likely(!(next_mm & LAST_USER_MM_L1D_FLUSH)))
352 return;
353
354 /*
355 * Validate that it is not running on an SMT sibling as this would
356 * make the exercise pointless because the siblings share L1D. If
357 * it runs on a SMT sibling, notify it with SIGBUS on return to
358 * user/guest
359 */
360 if (this_cpu_read(cpu_info.smt_active)) {
361 clear_ti_thread_flag(&next->thread_info, TIF_SPEC_L1D_FLUSH);
362 next->l1d_flush_kill.func = l1d_flush_force_sigbus;
363 task_work_add(next, &next->l1d_flush_kill, TWA_RESUME);
364 }
365}
366
367static unsigned long mm_mangle_tif_spec_bits(struct task_struct *next)
368{
369 unsigned long next_tif = read_task_thread_flags(next);
370 unsigned long spec_bits = (next_tif >> TIF_SPEC_IB) & LAST_USER_MM_SPEC_MASK;
371
372 /*
373 * Ensure that the bit shift above works as expected and the two flags
374 * end up in bit 0 and 1.
375 */
376 BUILD_BUG_ON(TIF_SPEC_L1D_FLUSH != TIF_SPEC_IB + 1);
377
378 return (unsigned long)next->mm | spec_bits;
379}
380
381static void cond_mitigation(struct task_struct *next)
382{
383 unsigned long prev_mm, next_mm;
384
385 if (!next || !next->mm)
386 return;
387
388 next_mm = mm_mangle_tif_spec_bits(next);
389 prev_mm = this_cpu_read(cpu_tlbstate.last_user_mm_spec);
390
391 /*
392 * Avoid user/user BTB poisoning by flushing the branch predictor
393 * when switching between processes. This stops one process from
394 * doing Spectre-v2 attacks on another.
395 *
396 * Both, the conditional and the always IBPB mode use the mm
397 * pointer to avoid the IBPB when switching between tasks of the
398 * same process. Using the mm pointer instead of mm->context.ctx_id
399 * opens a hypothetical hole vs. mm_struct reuse, which is more or
400 * less impossible to control by an attacker. Aside of that it
401 * would only affect the first schedule so the theoretically
402 * exposed data is not really interesting.
403 */
404 if (static_branch_likely(&switch_mm_cond_ibpb)) {
405 /*
406 * This is a bit more complex than the always mode because
407 * it has to handle two cases:
408 *
409 * 1) Switch from a user space task (potential attacker)
410 * which has TIF_SPEC_IB set to a user space task
411 * (potential victim) which has TIF_SPEC_IB not set.
412 *
413 * 2) Switch from a user space task (potential attacker)
414 * which has TIF_SPEC_IB not set to a user space task
415 * (potential victim) which has TIF_SPEC_IB set.
416 *
417 * This could be done by unconditionally issuing IBPB when
418 * a task which has TIF_SPEC_IB set is either scheduled in
419 * or out. Though that results in two flushes when:
420 *
421 * - the same user space task is scheduled out and later
422 * scheduled in again and only a kernel thread ran in
423 * between.
424 *
425 * - a user space task belonging to the same process is
426 * scheduled in after a kernel thread ran in between
427 *
428 * - a user space task belonging to the same process is
429 * scheduled in immediately.
430 *
431 * Optimize this with reasonably small overhead for the
432 * above cases. Mangle the TIF_SPEC_IB bit into the mm
433 * pointer of the incoming task which is stored in
434 * cpu_tlbstate.last_user_mm_spec for comparison.
435 *
436 * Issue IBPB only if the mm's are different and one or
437 * both have the IBPB bit set.
438 */
439 if (next_mm != prev_mm &&
440 (next_mm | prev_mm) & LAST_USER_MM_IBPB)
441 indirect_branch_prediction_barrier();
442 }
443
444 if (static_branch_unlikely(&switch_mm_always_ibpb)) {
445 /*
446 * Only flush when switching to a user space task with a
447 * different context than the user space task which ran
448 * last on this CPU.
449 */
450 if ((prev_mm & ~LAST_USER_MM_SPEC_MASK) !=
451 (unsigned long)next->mm)
452 indirect_branch_prediction_barrier();
453 }
454
455 if (static_branch_unlikely(&switch_mm_cond_l1d_flush)) {
456 /*
457 * Flush L1D when the outgoing task requested it and/or
458 * check whether the incoming task requested L1D flushing
459 * and ended up on an SMT sibling.
460 */
461 if (unlikely((prev_mm | next_mm) & LAST_USER_MM_L1D_FLUSH))
462 l1d_flush_evaluate(prev_mm, next_mm, next);
463 }
464
465 this_cpu_write(cpu_tlbstate.last_user_mm_spec, next_mm);
466}
467
468#ifdef CONFIG_PERF_EVENTS
469static inline void cr4_update_pce_mm(struct mm_struct *mm)
470{
471 if (static_branch_unlikely(&rdpmc_always_available_key) ||
472 (!static_branch_unlikely(&rdpmc_never_available_key) &&
473 atomic_read(&mm->context.perf_rdpmc_allowed))) {
474 /*
475 * Clear the existing dirty counters to
476 * prevent the leak for an RDPMC task.
477 */
478 perf_clear_dirty_counters();
479 cr4_set_bits_irqsoff(X86_CR4_PCE);
480 } else
481 cr4_clear_bits_irqsoff(X86_CR4_PCE);
482}
483
484void cr4_update_pce(void *ignored)
485{
486 cr4_update_pce_mm(this_cpu_read(cpu_tlbstate.loaded_mm));
487}
488
489#else
490static inline void cr4_update_pce_mm(struct mm_struct *mm) { }
491#endif
492
493/*
494 * This optimizes when not actually switching mm's. Some architectures use the
495 * 'unused' argument for this optimization, but x86 must use
496 * 'cpu_tlbstate.loaded_mm' instead because it does not always keep
497 * 'current->active_mm' up to date.
498 */
499void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next,
500 struct task_struct *tsk)
501{
502 struct mm_struct *prev = this_cpu_read(cpu_tlbstate.loaded_mm);
503 u16 prev_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
504 bool was_lazy = this_cpu_read(cpu_tlbstate_shared.is_lazy);
505 unsigned cpu = smp_processor_id();
506 unsigned long new_lam;
507 u64 next_tlb_gen;
508 bool need_flush;
509 u16 new_asid;
510
511 /* We don't want flush_tlb_func() to run concurrently with us. */
512 if (IS_ENABLED(CONFIG_PROVE_LOCKING))
513 WARN_ON_ONCE(!irqs_disabled());
514
515 /*
516 * Verify that CR3 is what we think it is. This will catch
517 * hypothetical buggy code that directly switches to swapper_pg_dir
518 * without going through leave_mm() / switch_mm_irqs_off() or that
519 * does something like write_cr3(read_cr3_pa()).
520 *
521 * Only do this check if CONFIG_DEBUG_VM=y because __read_cr3()
522 * isn't free.
523 */
524#ifdef CONFIG_DEBUG_VM
525 if (WARN_ON_ONCE(__read_cr3() != build_cr3(prev->pgd, prev_asid,
526 tlbstate_lam_cr3_mask()))) {
527 /*
528 * If we were to BUG here, we'd be very likely to kill
529 * the system so hard that we don't see the call trace.
530 * Try to recover instead by ignoring the error and doing
531 * a global flush to minimize the chance of corruption.
532 *
533 * (This is far from being a fully correct recovery.
534 * Architecturally, the CPU could prefetch something
535 * back into an incorrect ASID slot and leave it there
536 * to cause trouble down the road. It's better than
537 * nothing, though.)
538 */
539 __flush_tlb_all();
540 }
541#endif
542 if (was_lazy)
543 this_cpu_write(cpu_tlbstate_shared.is_lazy, false);
544
545 /*
546 * The membarrier system call requires a full memory barrier and
547 * core serialization before returning to user-space, after
548 * storing to rq->curr, when changing mm. This is because
549 * membarrier() sends IPIs to all CPUs that are in the target mm
550 * to make them issue memory barriers. However, if another CPU
551 * switches to/from the target mm concurrently with
552 * membarrier(), it can cause that CPU not to receive an IPI
553 * when it really should issue a memory barrier. Writing to CR3
554 * provides that full memory barrier and core serializing
555 * instruction.
556 */
557 if (prev == next) {
558 /* Not actually switching mm's */
559 VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) !=
560 next->context.ctx_id);
561
562 /*
563 * If this races with another thread that enables lam, 'new_lam'
564 * might not match tlbstate_lam_cr3_mask().
565 */
566
567 /*
568 * Even in lazy TLB mode, the CPU should stay set in the
569 * mm_cpumask. The TLB shootdown code can figure out from
570 * cpu_tlbstate_shared.is_lazy whether or not to send an IPI.
571 */
572 if (IS_ENABLED(CONFIG_DEBUG_VM) && WARN_ON_ONCE(prev != &init_mm &&
573 !cpumask_test_cpu(cpu, mm_cpumask(next))))
574 cpumask_set_cpu(cpu, mm_cpumask(next));
575
576 /*
577 * If the CPU is not in lazy TLB mode, we are just switching
578 * from one thread in a process to another thread in the same
579 * process. No TLB flush required.
580 */
581 if (!was_lazy)
582 return;
583
584 /*
585 * Read the tlb_gen to check whether a flush is needed.
586 * If the TLB is up to date, just use it.
587 * The barrier synchronizes with the tlb_gen increment in
588 * the TLB shootdown code.
589 */
590 smp_mb();
591 next_tlb_gen = atomic64_read(&next->context.tlb_gen);
592 if (this_cpu_read(cpu_tlbstate.ctxs[prev_asid].tlb_gen) ==
593 next_tlb_gen)
594 return;
595
596 /*
597 * TLB contents went out of date while we were in lazy
598 * mode. Fall through to the TLB switching code below.
599 */
600 new_asid = prev_asid;
601 need_flush = true;
602 } else {
603 /*
604 * Apply process to process speculation vulnerability
605 * mitigations if applicable.
606 */
607 cond_mitigation(tsk);
608
609 /*
610 * Stop remote flushes for the previous mm.
611 * Skip kernel threads; we never send init_mm TLB flushing IPIs,
612 * but the bitmap manipulation can cause cache line contention.
613 */
614 if (prev != &init_mm) {
615 VM_WARN_ON_ONCE(!cpumask_test_cpu(cpu,
616 mm_cpumask(prev)));
617 cpumask_clear_cpu(cpu, mm_cpumask(prev));
618 }
619
620 /* Start receiving IPIs and then read tlb_gen (and LAM below) */
621 if (next != &init_mm)
622 cpumask_set_cpu(cpu, mm_cpumask(next));
623 next_tlb_gen = atomic64_read(&next->context.tlb_gen);
624
625 choose_new_asid(next, next_tlb_gen, &new_asid, &need_flush);
626
627 /* Let nmi_uaccess_okay() know that we're changing CR3. */
628 this_cpu_write(cpu_tlbstate.loaded_mm, LOADED_MM_SWITCHING);
629 barrier();
630 }
631
632 new_lam = mm_lam_cr3_mask(next);
633 if (need_flush) {
634 this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id);
635 this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen);
636 load_new_mm_cr3(next->pgd, new_asid, new_lam, true);
637
638 trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
639 } else {
640 /* The new ASID is already up to date. */
641 load_new_mm_cr3(next->pgd, new_asid, new_lam, false);
642
643 trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, 0);
644 }
645
646 /* Make sure we write CR3 before loaded_mm. */
647 barrier();
648
649 this_cpu_write(cpu_tlbstate.loaded_mm, next);
650 this_cpu_write(cpu_tlbstate.loaded_mm_asid, new_asid);
651 cpu_tlbstate_update_lam(new_lam, mm_untag_mask(next));
652
653 if (next != prev) {
654 cr4_update_pce_mm(next);
655 switch_ldt(prev, next);
656 }
657}
658
659/*
660 * Please ignore the name of this function. It should be called
661 * switch_to_kernel_thread().
662 *
663 * enter_lazy_tlb() is a hint from the scheduler that we are entering a
664 * kernel thread or other context without an mm. Acceptable implementations
665 * include doing nothing whatsoever, switching to init_mm, or various clever
666 * lazy tricks to try to minimize TLB flushes.
667 *
668 * The scheduler reserves the right to call enter_lazy_tlb() several times
669 * in a row. It will notify us that we're going back to a real mm by
670 * calling switch_mm_irqs_off().
671 */
672void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
673{
674 if (this_cpu_read(cpu_tlbstate.loaded_mm) == &init_mm)
675 return;
676
677 this_cpu_write(cpu_tlbstate_shared.is_lazy, true);
678}
679
680/*
681 * Call this when reinitializing a CPU. It fixes the following potential
682 * problems:
683 *
684 * - The ASID changed from what cpu_tlbstate thinks it is (most likely
685 * because the CPU was taken down and came back up with CR3's PCID
686 * bits clear. CPU hotplug can do this.
687 *
688 * - The TLB contains junk in slots corresponding to inactive ASIDs.
689 *
690 * - The CPU went so far out to lunch that it may have missed a TLB
691 * flush.
692 */
693void initialize_tlbstate_and_flush(void)
694{
695 int i;
696 struct mm_struct *mm = this_cpu_read(cpu_tlbstate.loaded_mm);
697 u64 tlb_gen = atomic64_read(&init_mm.context.tlb_gen);
698 unsigned long lam = mm_lam_cr3_mask(mm);
699 unsigned long cr3 = __read_cr3();
700
701 /* Assert that CR3 already references the right mm. */
702 WARN_ON((cr3 & CR3_ADDR_MASK) != __pa(mm->pgd));
703
704 /* LAM expected to be disabled */
705 WARN_ON(cr3 & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57));
706 WARN_ON(lam);
707
708 /*
709 * Assert that CR4.PCIDE is set if needed. (CR4.PCIDE initialization
710 * doesn't work like other CR4 bits because it can only be set from
711 * long mode.)
712 */
713 WARN_ON(boot_cpu_has(X86_FEATURE_PCID) &&
714 !(cr4_read_shadow() & X86_CR4_PCIDE));
715
716 /* Disable LAM, force ASID 0 and force a TLB flush. */
717 write_cr3(build_cr3(mm->pgd, 0, 0));
718
719 /* Reinitialize tlbstate. */
720 this_cpu_write(cpu_tlbstate.last_user_mm_spec, LAST_USER_MM_INIT);
721 this_cpu_write(cpu_tlbstate.loaded_mm_asid, 0);
722 this_cpu_write(cpu_tlbstate.next_asid, 1);
723 this_cpu_write(cpu_tlbstate.ctxs[0].ctx_id, mm->context.ctx_id);
724 this_cpu_write(cpu_tlbstate.ctxs[0].tlb_gen, tlb_gen);
725 cpu_tlbstate_update_lam(lam, mm_untag_mask(mm));
726
727 for (i = 1; i < TLB_NR_DYN_ASIDS; i++)
728 this_cpu_write(cpu_tlbstate.ctxs[i].ctx_id, 0);
729}
730
731/*
732 * flush_tlb_func()'s memory ordering requirement is that any
733 * TLB fills that happen after we flush the TLB are ordered after we
734 * read active_mm's tlb_gen. We don't need any explicit barriers
735 * because all x86 flush operations are serializing and the
736 * atomic64_read operation won't be reordered by the compiler.
737 */
738static void flush_tlb_func(void *info)
739{
740 /*
741 * We have three different tlb_gen values in here. They are:
742 *
743 * - mm_tlb_gen: the latest generation.
744 * - local_tlb_gen: the generation that this CPU has already caught
745 * up to.
746 * - f->new_tlb_gen: the generation that the requester of the flush
747 * wants us to catch up to.
748 */
749 const struct flush_tlb_info *f = info;
750 struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
751 u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
752 u64 local_tlb_gen = this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen);
753 bool local = smp_processor_id() == f->initiating_cpu;
754 unsigned long nr_invalidate = 0;
755 u64 mm_tlb_gen;
756
757 /* This code cannot presently handle being reentered. */
758 VM_WARN_ON(!irqs_disabled());
759
760 if (!local) {
761 inc_irq_stat(irq_tlb_count);
762 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
763
764 /* Can only happen on remote CPUs */
765 if (f->mm && f->mm != loaded_mm)
766 return;
767 }
768
769 if (unlikely(loaded_mm == &init_mm))
770 return;
771
772 VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].ctx_id) !=
773 loaded_mm->context.ctx_id);
774
775 if (this_cpu_read(cpu_tlbstate_shared.is_lazy)) {
776 /*
777 * We're in lazy mode. We need to at least flush our
778 * paging-structure cache to avoid speculatively reading
779 * garbage into our TLB. Since switching to init_mm is barely
780 * slower than a minimal flush, just switch to init_mm.
781 *
782 * This should be rare, with native_flush_tlb_multi() skipping
783 * IPIs to lazy TLB mode CPUs.
784 */
785 switch_mm_irqs_off(NULL, &init_mm, NULL);
786 return;
787 }
788
789 if (unlikely(f->new_tlb_gen != TLB_GENERATION_INVALID &&
790 f->new_tlb_gen <= local_tlb_gen)) {
791 /*
792 * The TLB is already up to date in respect to f->new_tlb_gen.
793 * While the core might be still behind mm_tlb_gen, checking
794 * mm_tlb_gen unnecessarily would have negative caching effects
795 * so avoid it.
796 */
797 return;
798 }
799
800 /*
801 * Defer mm_tlb_gen reading as long as possible to avoid cache
802 * contention.
803 */
804 mm_tlb_gen = atomic64_read(&loaded_mm->context.tlb_gen);
805
806 if (unlikely(local_tlb_gen == mm_tlb_gen)) {
807 /*
808 * There's nothing to do: we're already up to date. This can
809 * happen if two concurrent flushes happen -- the first flush to
810 * be handled can catch us all the way up, leaving no work for
811 * the second flush.
812 */
813 goto done;
814 }
815
816 WARN_ON_ONCE(local_tlb_gen > mm_tlb_gen);
817 WARN_ON_ONCE(f->new_tlb_gen > mm_tlb_gen);
818
819 /*
820 * If we get to this point, we know that our TLB is out of date.
821 * This does not strictly imply that we need to flush (it's
822 * possible that f->new_tlb_gen <= local_tlb_gen), but we're
823 * going to need to flush in the very near future, so we might
824 * as well get it over with.
825 *
826 * The only question is whether to do a full or partial flush.
827 *
828 * We do a partial flush if requested and two extra conditions
829 * are met:
830 *
831 * 1. f->new_tlb_gen == local_tlb_gen + 1. We have an invariant that
832 * we've always done all needed flushes to catch up to
833 * local_tlb_gen. If, for example, local_tlb_gen == 2 and
834 * f->new_tlb_gen == 3, then we know that the flush needed to bring
835 * us up to date for tlb_gen 3 is the partial flush we're
836 * processing.
837 *
838 * As an example of why this check is needed, suppose that there
839 * are two concurrent flushes. The first is a full flush that
840 * changes context.tlb_gen from 1 to 2. The second is a partial
841 * flush that changes context.tlb_gen from 2 to 3. If they get
842 * processed on this CPU in reverse order, we'll see
843 * local_tlb_gen == 1, mm_tlb_gen == 3, and end != TLB_FLUSH_ALL.
844 * If we were to use __flush_tlb_one_user() and set local_tlb_gen to
845 * 3, we'd be break the invariant: we'd update local_tlb_gen above
846 * 1 without the full flush that's needed for tlb_gen 2.
847 *
848 * 2. f->new_tlb_gen == mm_tlb_gen. This is purely an optimization.
849 * Partial TLB flushes are not all that much cheaper than full TLB
850 * flushes, so it seems unlikely that it would be a performance win
851 * to do a partial flush if that won't bring our TLB fully up to
852 * date. By doing a full flush instead, we can increase
853 * local_tlb_gen all the way to mm_tlb_gen and we can probably
854 * avoid another flush in the very near future.
855 */
856 if (f->end != TLB_FLUSH_ALL &&
857 f->new_tlb_gen == local_tlb_gen + 1 &&
858 f->new_tlb_gen == mm_tlb_gen) {
859 /* Partial flush */
860 unsigned long addr = f->start;
861
862 /* Partial flush cannot have invalid generations */
863 VM_WARN_ON(f->new_tlb_gen == TLB_GENERATION_INVALID);
864
865 /* Partial flush must have valid mm */
866 VM_WARN_ON(f->mm == NULL);
867
868 nr_invalidate = (f->end - f->start) >> f->stride_shift;
869
870 while (addr < f->end) {
871 flush_tlb_one_user(addr);
872 addr += 1UL << f->stride_shift;
873 }
874 if (local)
875 count_vm_tlb_events(NR_TLB_LOCAL_FLUSH_ONE, nr_invalidate);
876 } else {
877 /* Full flush. */
878 nr_invalidate = TLB_FLUSH_ALL;
879
880 flush_tlb_local();
881 if (local)
882 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
883 }
884
885 /* Both paths above update our state to mm_tlb_gen. */
886 this_cpu_write(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen, mm_tlb_gen);
887
888 /* Tracing is done in a unified manner to reduce the code size */
889done:
890 trace_tlb_flush(!local ? TLB_REMOTE_SHOOTDOWN :
891 (f->mm == NULL) ? TLB_LOCAL_SHOOTDOWN :
892 TLB_LOCAL_MM_SHOOTDOWN,
893 nr_invalidate);
894}
895
896static bool should_flush_tlb(int cpu, void *data)
897{
898 struct flush_tlb_info *info = data;
899
900 /* Lazy TLB will get flushed at the next context switch. */
901 if (per_cpu(cpu_tlbstate_shared.is_lazy, cpu))
902 return false;
903
904 /* No mm means kernel memory flush. */
905 if (!info->mm)
906 return true;
907
908 /* The target mm is loaded, and the CPU is not lazy. */
909 if (per_cpu(cpu_tlbstate.loaded_mm, cpu) == info->mm)
910 return true;
911
912 /* In cpumask, but not the loaded mm? Periodically remove by flushing. */
913 if (info->trim_cpumask)
914 return true;
915
916 return false;
917}
918
919static bool should_trim_cpumask(struct mm_struct *mm)
920{
921 if (time_after(jiffies, READ_ONCE(mm->context.next_trim_cpumask))) {
922 WRITE_ONCE(mm->context.next_trim_cpumask, jiffies + HZ);
923 return true;
924 }
925 return false;
926}
927
928DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state_shared, cpu_tlbstate_shared);
929EXPORT_PER_CPU_SYMBOL(cpu_tlbstate_shared);
930
931STATIC_NOPV void native_flush_tlb_multi(const struct cpumask *cpumask,
932 const struct flush_tlb_info *info)
933{
934 /*
935 * Do accounting and tracing. Note that there are (and have always been)
936 * cases in which a remote TLB flush will be traced, but eventually
937 * would not happen.
938 */
939 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
940 if (info->end == TLB_FLUSH_ALL)
941 trace_tlb_flush(TLB_REMOTE_SEND_IPI, TLB_FLUSH_ALL);
942 else
943 trace_tlb_flush(TLB_REMOTE_SEND_IPI,
944 (info->end - info->start) >> PAGE_SHIFT);
945
946 /*
947 * If no page tables were freed, we can skip sending IPIs to
948 * CPUs in lazy TLB mode. They will flush the CPU themselves
949 * at the next context switch.
950 *
951 * However, if page tables are getting freed, we need to send the
952 * IPI everywhere, to prevent CPUs in lazy TLB mode from tripping
953 * up on the new contents of what used to be page tables, while
954 * doing a speculative memory access.
955 */
956 if (info->freed_tables)
957 on_each_cpu_mask(cpumask, flush_tlb_func, (void *)info, true);
958 else
959 on_each_cpu_cond_mask(should_flush_tlb, flush_tlb_func,
960 (void *)info, 1, cpumask);
961}
962
963void flush_tlb_multi(const struct cpumask *cpumask,
964 const struct flush_tlb_info *info)
965{
966 __flush_tlb_multi(cpumask, info);
967}
968
969/*
970 * See Documentation/arch/x86/tlb.rst for details. We choose 33
971 * because it is large enough to cover the vast majority (at
972 * least 95%) of allocations, and is small enough that we are
973 * confident it will not cause too much overhead. Each single
974 * flush is about 100 ns, so this caps the maximum overhead at
975 * _about_ 3,000 ns.
976 *
977 * This is in units of pages.
978 */
979unsigned long tlb_single_page_flush_ceiling __read_mostly = 33;
980
981static DEFINE_PER_CPU_SHARED_ALIGNED(struct flush_tlb_info, flush_tlb_info);
982
983#ifdef CONFIG_DEBUG_VM
984static DEFINE_PER_CPU(unsigned int, flush_tlb_info_idx);
985#endif
986
987static struct flush_tlb_info *get_flush_tlb_info(struct mm_struct *mm,
988 unsigned long start, unsigned long end,
989 unsigned int stride_shift, bool freed_tables,
990 u64 new_tlb_gen)
991{
992 struct flush_tlb_info *info = this_cpu_ptr(&flush_tlb_info);
993
994#ifdef CONFIG_DEBUG_VM
995 /*
996 * Ensure that the following code is non-reentrant and flush_tlb_info
997 * is not overwritten. This means no TLB flushing is initiated by
998 * interrupt handlers and machine-check exception handlers.
999 */
1000 BUG_ON(this_cpu_inc_return(flush_tlb_info_idx) != 1);
1001#endif
1002
1003 info->start = start;
1004 info->end = end;
1005 info->mm = mm;
1006 info->stride_shift = stride_shift;
1007 info->freed_tables = freed_tables;
1008 info->new_tlb_gen = new_tlb_gen;
1009 info->initiating_cpu = smp_processor_id();
1010 info->trim_cpumask = 0;
1011
1012 return info;
1013}
1014
1015static void put_flush_tlb_info(void)
1016{
1017#ifdef CONFIG_DEBUG_VM
1018 /* Complete reentrancy prevention checks */
1019 barrier();
1020 this_cpu_dec(flush_tlb_info_idx);
1021#endif
1022}
1023
1024void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
1025 unsigned long end, unsigned int stride_shift,
1026 bool freed_tables)
1027{
1028 struct flush_tlb_info *info;
1029 u64 new_tlb_gen;
1030 int cpu;
1031
1032 cpu = get_cpu();
1033
1034 /* Should we flush just the requested range? */
1035 if ((end == TLB_FLUSH_ALL) ||
1036 ((end - start) >> stride_shift) > tlb_single_page_flush_ceiling) {
1037 start = 0;
1038 end = TLB_FLUSH_ALL;
1039 }
1040
1041 /* This is also a barrier that synchronizes with switch_mm(). */
1042 new_tlb_gen = inc_mm_tlb_gen(mm);
1043
1044 info = get_flush_tlb_info(mm, start, end, stride_shift, freed_tables,
1045 new_tlb_gen);
1046
1047 /*
1048 * flush_tlb_multi() is not optimized for the common case in which only
1049 * a local TLB flush is needed. Optimize this use-case by calling
1050 * flush_tlb_func_local() directly in this case.
1051 */
1052 if (cpumask_any_but(mm_cpumask(mm), cpu) < nr_cpu_ids) {
1053 info->trim_cpumask = should_trim_cpumask(mm);
1054 flush_tlb_multi(mm_cpumask(mm), info);
1055 } else if (mm == this_cpu_read(cpu_tlbstate.loaded_mm)) {
1056 lockdep_assert_irqs_enabled();
1057 local_irq_disable();
1058 flush_tlb_func(info);
1059 local_irq_enable();
1060 }
1061
1062 put_flush_tlb_info();
1063 put_cpu();
1064 mmu_notifier_arch_invalidate_secondary_tlbs(mm, start, end);
1065}
1066
1067
1068static void do_flush_tlb_all(void *info)
1069{
1070 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
1071 __flush_tlb_all();
1072}
1073
1074void flush_tlb_all(void)
1075{
1076 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
1077 on_each_cpu(do_flush_tlb_all, NULL, 1);
1078}
1079
1080static void do_kernel_range_flush(void *info)
1081{
1082 struct flush_tlb_info *f = info;
1083 unsigned long addr;
1084
1085 /* flush range by one by one 'invlpg' */
1086 for (addr = f->start; addr < f->end; addr += PAGE_SIZE)
1087 flush_tlb_one_kernel(addr);
1088}
1089
1090void flush_tlb_kernel_range(unsigned long start, unsigned long end)
1091{
1092 /* Balance as user space task's flush, a bit conservative */
1093 if (end == TLB_FLUSH_ALL ||
1094 (end - start) > tlb_single_page_flush_ceiling << PAGE_SHIFT) {
1095 on_each_cpu(do_flush_tlb_all, NULL, 1);
1096 } else {
1097 struct flush_tlb_info *info;
1098
1099 preempt_disable();
1100 info = get_flush_tlb_info(NULL, start, end, 0, false,
1101 TLB_GENERATION_INVALID);
1102
1103 on_each_cpu(do_kernel_range_flush, info, 1);
1104
1105 put_flush_tlb_info();
1106 preempt_enable();
1107 }
1108}
1109
1110/*
1111 * This can be used from process context to figure out what the value of
1112 * CR3 is without needing to do a (slow) __read_cr3().
1113 *
1114 * It's intended to be used for code like KVM that sneakily changes CR3
1115 * and needs to restore it. It needs to be used very carefully.
1116 */
1117unsigned long __get_current_cr3_fast(void)
1118{
1119 unsigned long cr3 =
1120 build_cr3(this_cpu_read(cpu_tlbstate.loaded_mm)->pgd,
1121 this_cpu_read(cpu_tlbstate.loaded_mm_asid),
1122 tlbstate_lam_cr3_mask());
1123
1124 /* For now, be very restrictive about when this can be called. */
1125 VM_WARN_ON(in_nmi() || preemptible());
1126
1127 VM_BUG_ON(cr3 != __read_cr3());
1128 return cr3;
1129}
1130EXPORT_SYMBOL_GPL(__get_current_cr3_fast);
1131
1132/*
1133 * Flush one page in the kernel mapping
1134 */
1135void flush_tlb_one_kernel(unsigned long addr)
1136{
1137 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
1138
1139 /*
1140 * If PTI is off, then __flush_tlb_one_user() is just INVLPG or its
1141 * paravirt equivalent. Even with PCID, this is sufficient: we only
1142 * use PCID if we also use global PTEs for the kernel mapping, and
1143 * INVLPG flushes global translations across all address spaces.
1144 *
1145 * If PTI is on, then the kernel is mapped with non-global PTEs, and
1146 * __flush_tlb_one_user() will flush the given address for the current
1147 * kernel address space and for its usermode counterpart, but it does
1148 * not flush it for other address spaces.
1149 */
1150 flush_tlb_one_user(addr);
1151
1152 if (!static_cpu_has(X86_FEATURE_PTI))
1153 return;
1154
1155 /*
1156 * See above. We need to propagate the flush to all other address
1157 * spaces. In principle, we only need to propagate it to kernelmode
1158 * address spaces, but the extra bookkeeping we would need is not
1159 * worth it.
1160 */
1161 this_cpu_write(cpu_tlbstate.invalidate_other, true);
1162}
1163
1164/*
1165 * Flush one page in the user mapping
1166 */
1167STATIC_NOPV void native_flush_tlb_one_user(unsigned long addr)
1168{
1169 u32 loaded_mm_asid;
1170 bool cpu_pcide;
1171
1172 /* Flush 'addr' from the kernel PCID: */
1173 invlpg(addr);
1174
1175 /* If PTI is off there is no user PCID and nothing to flush. */
1176 if (!static_cpu_has(X86_FEATURE_PTI))
1177 return;
1178
1179 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
1180 cpu_pcide = this_cpu_read(cpu_tlbstate.cr4) & X86_CR4_PCIDE;
1181
1182 /*
1183 * invpcid_flush_one(pcid>0) will #GP if CR4.PCIDE==0. Check
1184 * 'cpu_pcide' to ensure that *this* CPU will not trigger those
1185 * #GP's even if called before CR4.PCIDE has been initialized.
1186 */
1187 if (boot_cpu_has(X86_FEATURE_INVPCID) && cpu_pcide)
1188 invpcid_flush_one(user_pcid(loaded_mm_asid), addr);
1189 else
1190 invalidate_user_asid(loaded_mm_asid);
1191}
1192
1193void flush_tlb_one_user(unsigned long addr)
1194{
1195 __flush_tlb_one_user(addr);
1196}
1197
1198/*
1199 * Flush everything
1200 */
1201STATIC_NOPV void native_flush_tlb_global(void)
1202{
1203 unsigned long flags;
1204
1205 if (static_cpu_has(X86_FEATURE_INVPCID)) {
1206 /*
1207 * Using INVPCID is considerably faster than a pair of writes
1208 * to CR4 sandwiched inside an IRQ flag save/restore.
1209 *
1210 * Note, this works with CR4.PCIDE=0 or 1.
1211 */
1212 invpcid_flush_all();
1213 return;
1214 }
1215
1216 /*
1217 * Read-modify-write to CR4 - protect it from preemption and
1218 * from interrupts. (Use the raw variant because this code can
1219 * be called from deep inside debugging code.)
1220 */
1221 raw_local_irq_save(flags);
1222
1223 __native_tlb_flush_global(this_cpu_read(cpu_tlbstate.cr4));
1224
1225 raw_local_irq_restore(flags);
1226}
1227
1228/*
1229 * Flush the entire current user mapping
1230 */
1231STATIC_NOPV void native_flush_tlb_local(void)
1232{
1233 /*
1234 * Preemption or interrupts must be disabled to protect the access
1235 * to the per CPU variable and to prevent being preempted between
1236 * read_cr3() and write_cr3().
1237 */
1238 WARN_ON_ONCE(preemptible());
1239
1240 invalidate_user_asid(this_cpu_read(cpu_tlbstate.loaded_mm_asid));
1241
1242 /* If current->mm == NULL then the read_cr3() "borrows" an mm */
1243 native_write_cr3(__native_read_cr3());
1244}
1245
1246void flush_tlb_local(void)
1247{
1248 __flush_tlb_local();
1249}
1250
1251/*
1252 * Flush everything
1253 */
1254void __flush_tlb_all(void)
1255{
1256 /*
1257 * This is to catch users with enabled preemption and the PGE feature
1258 * and don't trigger the warning in __native_flush_tlb().
1259 */
1260 VM_WARN_ON_ONCE(preemptible());
1261
1262 if (cpu_feature_enabled(X86_FEATURE_PGE)) {
1263 __flush_tlb_global();
1264 } else {
1265 /*
1266 * !PGE -> !PCID (setup_pcid()), thus every flush is total.
1267 */
1268 flush_tlb_local();
1269 }
1270}
1271EXPORT_SYMBOL_GPL(__flush_tlb_all);
1272
1273void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch)
1274{
1275 struct flush_tlb_info *info;
1276
1277 int cpu = get_cpu();
1278
1279 info = get_flush_tlb_info(NULL, 0, TLB_FLUSH_ALL, 0, false,
1280 TLB_GENERATION_INVALID);
1281 /*
1282 * flush_tlb_multi() is not optimized for the common case in which only
1283 * a local TLB flush is needed. Optimize this use-case by calling
1284 * flush_tlb_func_local() directly in this case.
1285 */
1286 if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) {
1287 flush_tlb_multi(&batch->cpumask, info);
1288 } else if (cpumask_test_cpu(cpu, &batch->cpumask)) {
1289 lockdep_assert_irqs_enabled();
1290 local_irq_disable();
1291 flush_tlb_func(info);
1292 local_irq_enable();
1293 }
1294
1295 cpumask_clear(&batch->cpumask);
1296
1297 put_flush_tlb_info();
1298 put_cpu();
1299}
1300
1301/*
1302 * Blindly accessing user memory from NMI context can be dangerous
1303 * if we're in the middle of switching the current user task or
1304 * switching the loaded mm. It can also be dangerous if we
1305 * interrupted some kernel code that was temporarily using a
1306 * different mm.
1307 */
1308bool nmi_uaccess_okay(void)
1309{
1310 struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
1311 struct mm_struct *current_mm = current->mm;
1312
1313 VM_WARN_ON_ONCE(!loaded_mm);
1314
1315 /*
1316 * The condition we want to check is
1317 * current_mm->pgd == __va(read_cr3_pa()). This may be slow, though,
1318 * if we're running in a VM with shadow paging, and nmi_uaccess_okay()
1319 * is supposed to be reasonably fast.
1320 *
1321 * Instead, we check the almost equivalent but somewhat conservative
1322 * condition below, and we rely on the fact that switch_mm_irqs_off()
1323 * sets loaded_mm to LOADED_MM_SWITCHING before writing to CR3.
1324 */
1325 if (loaded_mm != current_mm)
1326 return false;
1327
1328 VM_WARN_ON_ONCE(current_mm->pgd != __va(read_cr3_pa()));
1329
1330 return true;
1331}
1332
1333static ssize_t tlbflush_read_file(struct file *file, char __user *user_buf,
1334 size_t count, loff_t *ppos)
1335{
1336 char buf[32];
1337 unsigned int len;
1338
1339 len = sprintf(buf, "%ld\n", tlb_single_page_flush_ceiling);
1340 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1341}
1342
1343static ssize_t tlbflush_write_file(struct file *file,
1344 const char __user *user_buf, size_t count, loff_t *ppos)
1345{
1346 char buf[32];
1347 ssize_t len;
1348 int ceiling;
1349
1350 len = min(count, sizeof(buf) - 1);
1351 if (copy_from_user(buf, user_buf, len))
1352 return -EFAULT;
1353
1354 buf[len] = '\0';
1355 if (kstrtoint(buf, 0, &ceiling))
1356 return -EINVAL;
1357
1358 if (ceiling < 0)
1359 return -EINVAL;
1360
1361 tlb_single_page_flush_ceiling = ceiling;
1362 return count;
1363}
1364
1365static const struct file_operations fops_tlbflush = {
1366 .read = tlbflush_read_file,
1367 .write = tlbflush_write_file,
1368 .llseek = default_llseek,
1369};
1370
1371static int __init create_tlb_single_page_flush_ceiling(void)
1372{
1373 debugfs_create_file("tlb_single_page_flush_ceiling", S_IRUSR | S_IWUSR,
1374 arch_debugfs_dir, NULL, &fops_tlbflush);
1375 return 0;
1376}
1377late_initcall(create_tlb_single_page_flush_ceiling);