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1// SPDX-License-Identifier: GPL-2.0-only
2#include <linux/init.h>
3
4#include <linux/mm.h>
5#include <linux/spinlock.h>
6#include <linux/smp.h>
7#include <linux/interrupt.h>
8#include <linux/export.h>
9#include <linux/cpu.h>
10#include <linux/debugfs.h>
11#include <linux/sched/smt.h>
12#include <linux/task_work.h>
13
14#include <asm/tlbflush.h>
15#include <asm/mmu_context.h>
16#include <asm/nospec-branch.h>
17#include <asm/cache.h>
18#include <asm/cacheflush.h>
19#include <asm/apic.h>
20#include <asm/perf_event.h>
21
22#include "mm_internal.h"
23
24#ifdef CONFIG_PARAVIRT
25# define STATIC_NOPV
26#else
27# define STATIC_NOPV static
28# define __flush_tlb_local native_flush_tlb_local
29# define __flush_tlb_global native_flush_tlb_global
30# define __flush_tlb_one_user(addr) native_flush_tlb_one_user(addr)
31# define __flush_tlb_multi(msk, info) native_flush_tlb_multi(msk, info)
32#endif
33
34/*
35 * TLB flushing, formerly SMP-only
36 * c/o Linus Torvalds.
37 *
38 * These mean you can really definitely utterly forget about
39 * writing to user space from interrupts. (Its not allowed anyway).
40 *
41 * Optimizations Manfred Spraul <manfred@colorfullife.com>
42 *
43 * More scalable flush, from Andi Kleen
44 *
45 * Implement flush IPI by CALL_FUNCTION_VECTOR, Alex Shi
46 */
47
48/*
49 * Bits to mangle the TIF_SPEC_* state into the mm pointer which is
50 * stored in cpu_tlb_state.last_user_mm_spec.
51 */
52#define LAST_USER_MM_IBPB 0x1UL
53#define LAST_USER_MM_L1D_FLUSH 0x2UL
54#define LAST_USER_MM_SPEC_MASK (LAST_USER_MM_IBPB | LAST_USER_MM_L1D_FLUSH)
55
56/* Bits to set when tlbstate and flush is (re)initialized */
57#define LAST_USER_MM_INIT LAST_USER_MM_IBPB
58
59/*
60 * The x86 feature is called PCID (Process Context IDentifier). It is similar
61 * to what is traditionally called ASID on the RISC processors.
62 *
63 * We don't use the traditional ASID implementation, where each process/mm gets
64 * its own ASID and flush/restart when we run out of ASID space.
65 *
66 * Instead we have a small per-cpu array of ASIDs and cache the last few mm's
67 * that came by on this CPU, allowing cheaper switch_mm between processes on
68 * this CPU.
69 *
70 * We end up with different spaces for different things. To avoid confusion we
71 * use different names for each of them:
72 *
73 * ASID - [0, TLB_NR_DYN_ASIDS-1]
74 * the canonical identifier for an mm
75 *
76 * kPCID - [1, TLB_NR_DYN_ASIDS]
77 * the value we write into the PCID part of CR3; corresponds to the
78 * ASID+1, because PCID 0 is special.
79 *
80 * uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS]
81 * for KPTI each mm has two address spaces and thus needs two
82 * PCID values, but we can still do with a single ASID denomination
83 * for each mm. Corresponds to kPCID + 2048.
84 *
85 */
86
87/* There are 12 bits of space for ASIDS in CR3 */
88#define CR3_HW_ASID_BITS 12
89
90/*
91 * When enabled, PAGE_TABLE_ISOLATION consumes a single bit for
92 * user/kernel switches
93 */
94#ifdef CONFIG_PAGE_TABLE_ISOLATION
95# define PTI_CONSUMED_PCID_BITS 1
96#else
97# define PTI_CONSUMED_PCID_BITS 0
98#endif
99
100#define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
101
102/*
103 * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid. -1 below to account
104 * for them being zero-based. Another -1 is because PCID 0 is reserved for
105 * use by non-PCID-aware users.
106 */
107#define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)
108
109/*
110 * Given @asid, compute kPCID
111 */
112static inline u16 kern_pcid(u16 asid)
113{
114 VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
115
116#ifdef CONFIG_PAGE_TABLE_ISOLATION
117 /*
118 * Make sure that the dynamic ASID space does not conflict with the
119 * bit we are using to switch between user and kernel ASIDs.
120 */
121 BUILD_BUG_ON(TLB_NR_DYN_ASIDS >= (1 << X86_CR3_PTI_PCID_USER_BIT));
122
123 /*
124 * The ASID being passed in here should have respected the
125 * MAX_ASID_AVAILABLE and thus never have the switch bit set.
126 */
127 VM_WARN_ON_ONCE(asid & (1 << X86_CR3_PTI_PCID_USER_BIT));
128#endif
129 /*
130 * The dynamically-assigned ASIDs that get passed in are small
131 * (<TLB_NR_DYN_ASIDS). They never have the high switch bit set,
132 * so do not bother to clear it.
133 *
134 * If PCID is on, ASID-aware code paths put the ASID+1 into the
135 * PCID bits. This serves two purposes. It prevents a nasty
136 * situation in which PCID-unaware code saves CR3, loads some other
137 * value (with PCID == 0), and then restores CR3, thus corrupting
138 * the TLB for ASID 0 if the saved ASID was nonzero. It also means
139 * that any bugs involving loading a PCID-enabled CR3 with
140 * CR4.PCIDE off will trigger deterministically.
141 */
142 return asid + 1;
143}
144
145/*
146 * Given @asid, compute uPCID
147 */
148static inline u16 user_pcid(u16 asid)
149{
150 u16 ret = kern_pcid(asid);
151#ifdef CONFIG_PAGE_TABLE_ISOLATION
152 ret |= 1 << X86_CR3_PTI_PCID_USER_BIT;
153#endif
154 return ret;
155}
156
157static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)
158{
159 if (static_cpu_has(X86_FEATURE_PCID)) {
160 return __sme_pa(pgd) | kern_pcid(asid);
161 } else {
162 VM_WARN_ON_ONCE(asid != 0);
163 return __sme_pa(pgd);
164 }
165}
166
167static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
168{
169 VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
170 /*
171 * Use boot_cpu_has() instead of this_cpu_has() as this function
172 * might be called during early boot. This should work even after
173 * boot because all CPU's the have same capabilities:
174 */
175 VM_WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_PCID));
176 return __sme_pa(pgd) | kern_pcid(asid) | CR3_NOFLUSH;
177}
178
179/*
180 * We get here when we do something requiring a TLB invalidation
181 * but could not go invalidate all of the contexts. We do the
182 * necessary invalidation by clearing out the 'ctx_id' which
183 * forces a TLB flush when the context is loaded.
184 */
185static void clear_asid_other(void)
186{
187 u16 asid;
188
189 /*
190 * This is only expected to be set if we have disabled
191 * kernel _PAGE_GLOBAL pages.
192 */
193 if (!static_cpu_has(X86_FEATURE_PTI)) {
194 WARN_ON_ONCE(1);
195 return;
196 }
197
198 for (asid = 0; asid < TLB_NR_DYN_ASIDS; asid++) {
199 /* Do not need to flush the current asid */
200 if (asid == this_cpu_read(cpu_tlbstate.loaded_mm_asid))
201 continue;
202 /*
203 * Make sure the next time we go to switch to
204 * this asid, we do a flush:
205 */
206 this_cpu_write(cpu_tlbstate.ctxs[asid].ctx_id, 0);
207 }
208 this_cpu_write(cpu_tlbstate.invalidate_other, false);
209}
210
211atomic64_t last_mm_ctx_id = ATOMIC64_INIT(1);
212
213
214static void choose_new_asid(struct mm_struct *next, u64 next_tlb_gen,
215 u16 *new_asid, bool *need_flush)
216{
217 u16 asid;
218
219 if (!static_cpu_has(X86_FEATURE_PCID)) {
220 *new_asid = 0;
221 *need_flush = true;
222 return;
223 }
224
225 if (this_cpu_read(cpu_tlbstate.invalidate_other))
226 clear_asid_other();
227
228 for (asid = 0; asid < TLB_NR_DYN_ASIDS; asid++) {
229 if (this_cpu_read(cpu_tlbstate.ctxs[asid].ctx_id) !=
230 next->context.ctx_id)
231 continue;
232
233 *new_asid = asid;
234 *need_flush = (this_cpu_read(cpu_tlbstate.ctxs[asid].tlb_gen) <
235 next_tlb_gen);
236 return;
237 }
238
239 /*
240 * We don't currently own an ASID slot on this CPU.
241 * Allocate a slot.
242 */
243 *new_asid = this_cpu_add_return(cpu_tlbstate.next_asid, 1) - 1;
244 if (*new_asid >= TLB_NR_DYN_ASIDS) {
245 *new_asid = 0;
246 this_cpu_write(cpu_tlbstate.next_asid, 1);
247 }
248 *need_flush = true;
249}
250
251/*
252 * Given an ASID, flush the corresponding user ASID. We can delay this
253 * until the next time we switch to it.
254 *
255 * See SWITCH_TO_USER_CR3.
256 */
257static inline void invalidate_user_asid(u16 asid)
258{
259 /* There is no user ASID if address space separation is off */
260 if (!IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION))
261 return;
262
263 /*
264 * We only have a single ASID if PCID is off and the CR3
265 * write will have flushed it.
266 */
267 if (!cpu_feature_enabled(X86_FEATURE_PCID))
268 return;
269
270 if (!static_cpu_has(X86_FEATURE_PTI))
271 return;
272
273 __set_bit(kern_pcid(asid),
274 (unsigned long *)this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask));
275}
276
277static void load_new_mm_cr3(pgd_t *pgdir, u16 new_asid, bool need_flush)
278{
279 unsigned long new_mm_cr3;
280
281 if (need_flush) {
282 invalidate_user_asid(new_asid);
283 new_mm_cr3 = build_cr3(pgdir, new_asid);
284 } else {
285 new_mm_cr3 = build_cr3_noflush(pgdir, new_asid);
286 }
287
288 /*
289 * Caution: many callers of this function expect
290 * that load_cr3() is serializing and orders TLB
291 * fills with respect to the mm_cpumask writes.
292 */
293 write_cr3(new_mm_cr3);
294}
295
296void leave_mm(int cpu)
297{
298 struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
299
300 /*
301 * It's plausible that we're in lazy TLB mode while our mm is init_mm.
302 * If so, our callers still expect us to flush the TLB, but there
303 * aren't any user TLB entries in init_mm to worry about.
304 *
305 * This needs to happen before any other sanity checks due to
306 * intel_idle's shenanigans.
307 */
308 if (loaded_mm == &init_mm)
309 return;
310
311 /* Warn if we're not lazy. */
312 WARN_ON(!this_cpu_read(cpu_tlbstate_shared.is_lazy));
313
314 switch_mm(NULL, &init_mm, NULL);
315}
316EXPORT_SYMBOL_GPL(leave_mm);
317
318void switch_mm(struct mm_struct *prev, struct mm_struct *next,
319 struct task_struct *tsk)
320{
321 unsigned long flags;
322
323 local_irq_save(flags);
324 switch_mm_irqs_off(prev, next, tsk);
325 local_irq_restore(flags);
326}
327
328/*
329 * Invoked from return to user/guest by a task that opted-in to L1D
330 * flushing but ended up running on an SMT enabled core due to wrong
331 * affinity settings or CPU hotplug. This is part of the paranoid L1D flush
332 * contract which this task requested.
333 */
334static void l1d_flush_force_sigbus(struct callback_head *ch)
335{
336 force_sig(SIGBUS);
337}
338
339static void l1d_flush_evaluate(unsigned long prev_mm, unsigned long next_mm,
340 struct task_struct *next)
341{
342 /* Flush L1D if the outgoing task requests it */
343 if (prev_mm & LAST_USER_MM_L1D_FLUSH)
344 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
345
346 /* Check whether the incoming task opted in for L1D flush */
347 if (likely(!(next_mm & LAST_USER_MM_L1D_FLUSH)))
348 return;
349
350 /*
351 * Validate that it is not running on an SMT sibling as this would
352 * make the excercise pointless because the siblings share L1D. If
353 * it runs on a SMT sibling, notify it with SIGBUS on return to
354 * user/guest
355 */
356 if (this_cpu_read(cpu_info.smt_active)) {
357 clear_ti_thread_flag(&next->thread_info, TIF_SPEC_L1D_FLUSH);
358 next->l1d_flush_kill.func = l1d_flush_force_sigbus;
359 task_work_add(next, &next->l1d_flush_kill, TWA_RESUME);
360 }
361}
362
363static unsigned long mm_mangle_tif_spec_bits(struct task_struct *next)
364{
365 unsigned long next_tif = read_task_thread_flags(next);
366 unsigned long spec_bits = (next_tif >> TIF_SPEC_IB) & LAST_USER_MM_SPEC_MASK;
367
368 /*
369 * Ensure that the bit shift above works as expected and the two flags
370 * end up in bit 0 and 1.
371 */
372 BUILD_BUG_ON(TIF_SPEC_L1D_FLUSH != TIF_SPEC_IB + 1);
373
374 return (unsigned long)next->mm | spec_bits;
375}
376
377static void cond_mitigation(struct task_struct *next)
378{
379 unsigned long prev_mm, next_mm;
380
381 if (!next || !next->mm)
382 return;
383
384 next_mm = mm_mangle_tif_spec_bits(next);
385 prev_mm = this_cpu_read(cpu_tlbstate.last_user_mm_spec);
386
387 /*
388 * Avoid user/user BTB poisoning by flushing the branch predictor
389 * when switching between processes. This stops one process from
390 * doing Spectre-v2 attacks on another.
391 *
392 * Both, the conditional and the always IBPB mode use the mm
393 * pointer to avoid the IBPB when switching between tasks of the
394 * same process. Using the mm pointer instead of mm->context.ctx_id
395 * opens a hypothetical hole vs. mm_struct reuse, which is more or
396 * less impossible to control by an attacker. Aside of that it
397 * would only affect the first schedule so the theoretically
398 * exposed data is not really interesting.
399 */
400 if (static_branch_likely(&switch_mm_cond_ibpb)) {
401 /*
402 * This is a bit more complex than the always mode because
403 * it has to handle two cases:
404 *
405 * 1) Switch from a user space task (potential attacker)
406 * which has TIF_SPEC_IB set to a user space task
407 * (potential victim) which has TIF_SPEC_IB not set.
408 *
409 * 2) Switch from a user space task (potential attacker)
410 * which has TIF_SPEC_IB not set to a user space task
411 * (potential victim) which has TIF_SPEC_IB set.
412 *
413 * This could be done by unconditionally issuing IBPB when
414 * a task which has TIF_SPEC_IB set is either scheduled in
415 * or out. Though that results in two flushes when:
416 *
417 * - the same user space task is scheduled out and later
418 * scheduled in again and only a kernel thread ran in
419 * between.
420 *
421 * - a user space task belonging to the same process is
422 * scheduled in after a kernel thread ran in between
423 *
424 * - a user space task belonging to the same process is
425 * scheduled in immediately.
426 *
427 * Optimize this with reasonably small overhead for the
428 * above cases. Mangle the TIF_SPEC_IB bit into the mm
429 * pointer of the incoming task which is stored in
430 * cpu_tlbstate.last_user_mm_spec for comparison.
431 *
432 * Issue IBPB only if the mm's are different and one or
433 * both have the IBPB bit set.
434 */
435 if (next_mm != prev_mm &&
436 (next_mm | prev_mm) & LAST_USER_MM_IBPB)
437 indirect_branch_prediction_barrier();
438 }
439
440 if (static_branch_unlikely(&switch_mm_always_ibpb)) {
441 /*
442 * Only flush when switching to a user space task with a
443 * different context than the user space task which ran
444 * last on this CPU.
445 */
446 if ((prev_mm & ~LAST_USER_MM_SPEC_MASK) !=
447 (unsigned long)next->mm)
448 indirect_branch_prediction_barrier();
449 }
450
451 if (static_branch_unlikely(&switch_mm_cond_l1d_flush)) {
452 /*
453 * Flush L1D when the outgoing task requested it and/or
454 * check whether the incoming task requested L1D flushing
455 * and ended up on an SMT sibling.
456 */
457 if (unlikely((prev_mm | next_mm) & LAST_USER_MM_L1D_FLUSH))
458 l1d_flush_evaluate(prev_mm, next_mm, next);
459 }
460
461 this_cpu_write(cpu_tlbstate.last_user_mm_spec, next_mm);
462}
463
464#ifdef CONFIG_PERF_EVENTS
465static inline void cr4_update_pce_mm(struct mm_struct *mm)
466{
467 if (static_branch_unlikely(&rdpmc_always_available_key) ||
468 (!static_branch_unlikely(&rdpmc_never_available_key) &&
469 atomic_read(&mm->context.perf_rdpmc_allowed))) {
470 /*
471 * Clear the existing dirty counters to
472 * prevent the leak for an RDPMC task.
473 */
474 perf_clear_dirty_counters();
475 cr4_set_bits_irqsoff(X86_CR4_PCE);
476 } else
477 cr4_clear_bits_irqsoff(X86_CR4_PCE);
478}
479
480void cr4_update_pce(void *ignored)
481{
482 cr4_update_pce_mm(this_cpu_read(cpu_tlbstate.loaded_mm));
483}
484
485#else
486static inline void cr4_update_pce_mm(struct mm_struct *mm) { }
487#endif
488
489void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
490 struct task_struct *tsk)
491{
492 struct mm_struct *real_prev = this_cpu_read(cpu_tlbstate.loaded_mm);
493 u16 prev_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
494 bool was_lazy = this_cpu_read(cpu_tlbstate_shared.is_lazy);
495 unsigned cpu = smp_processor_id();
496 u64 next_tlb_gen;
497 bool need_flush;
498 u16 new_asid;
499
500 /*
501 * NB: The scheduler will call us with prev == next when switching
502 * from lazy TLB mode to normal mode if active_mm isn't changing.
503 * When this happens, we don't assume that CR3 (and hence
504 * cpu_tlbstate.loaded_mm) matches next.
505 *
506 * NB: leave_mm() calls us with prev == NULL and tsk == NULL.
507 */
508
509 /* We don't want flush_tlb_func() to run concurrently with us. */
510 if (IS_ENABLED(CONFIG_PROVE_LOCKING))
511 WARN_ON_ONCE(!irqs_disabled());
512
513 /*
514 * Verify that CR3 is what we think it is. This will catch
515 * hypothetical buggy code that directly switches to swapper_pg_dir
516 * without going through leave_mm() / switch_mm_irqs_off() or that
517 * does something like write_cr3(read_cr3_pa()).
518 *
519 * Only do this check if CONFIG_DEBUG_VM=y because __read_cr3()
520 * isn't free.
521 */
522#ifdef CONFIG_DEBUG_VM
523 if (WARN_ON_ONCE(__read_cr3() != build_cr3(real_prev->pgd, prev_asid))) {
524 /*
525 * If we were to BUG here, we'd be very likely to kill
526 * the system so hard that we don't see the call trace.
527 * Try to recover instead by ignoring the error and doing
528 * a global flush to minimize the chance of corruption.
529 *
530 * (This is far from being a fully correct recovery.
531 * Architecturally, the CPU could prefetch something
532 * back into an incorrect ASID slot and leave it there
533 * to cause trouble down the road. It's better than
534 * nothing, though.)
535 */
536 __flush_tlb_all();
537 }
538#endif
539 if (was_lazy)
540 this_cpu_write(cpu_tlbstate_shared.is_lazy, false);
541
542 /*
543 * The membarrier system call requires a full memory barrier and
544 * core serialization before returning to user-space, after
545 * storing to rq->curr, when changing mm. This is because
546 * membarrier() sends IPIs to all CPUs that are in the target mm
547 * to make them issue memory barriers. However, if another CPU
548 * switches to/from the target mm concurrently with
549 * membarrier(), it can cause that CPU not to receive an IPI
550 * when it really should issue a memory barrier. Writing to CR3
551 * provides that full memory barrier and core serializing
552 * instruction.
553 */
554 if (real_prev == next) {
555 VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) !=
556 next->context.ctx_id);
557
558 /*
559 * Even in lazy TLB mode, the CPU should stay set in the
560 * mm_cpumask. The TLB shootdown code can figure out from
561 * cpu_tlbstate_shared.is_lazy whether or not to send an IPI.
562 */
563 if (WARN_ON_ONCE(real_prev != &init_mm &&
564 !cpumask_test_cpu(cpu, mm_cpumask(next))))
565 cpumask_set_cpu(cpu, mm_cpumask(next));
566
567 /*
568 * If the CPU is not in lazy TLB mode, we are just switching
569 * from one thread in a process to another thread in the same
570 * process. No TLB flush required.
571 */
572 if (!was_lazy)
573 return;
574
575 /*
576 * Read the tlb_gen to check whether a flush is needed.
577 * If the TLB is up to date, just use it.
578 * The barrier synchronizes with the tlb_gen increment in
579 * the TLB shootdown code.
580 */
581 smp_mb();
582 next_tlb_gen = atomic64_read(&next->context.tlb_gen);
583 if (this_cpu_read(cpu_tlbstate.ctxs[prev_asid].tlb_gen) ==
584 next_tlb_gen)
585 return;
586
587 /*
588 * TLB contents went out of date while we were in lazy
589 * mode. Fall through to the TLB switching code below.
590 */
591 new_asid = prev_asid;
592 need_flush = true;
593 } else {
594 /*
595 * Apply process to process speculation vulnerability
596 * mitigations if applicable.
597 */
598 cond_mitigation(tsk);
599
600 /*
601 * Stop remote flushes for the previous mm.
602 * Skip kernel threads; we never send init_mm TLB flushing IPIs,
603 * but the bitmap manipulation can cause cache line contention.
604 */
605 if (real_prev != &init_mm) {
606 VM_WARN_ON_ONCE(!cpumask_test_cpu(cpu,
607 mm_cpumask(real_prev)));
608 cpumask_clear_cpu(cpu, mm_cpumask(real_prev));
609 }
610
611 /*
612 * Start remote flushes and then read tlb_gen.
613 */
614 if (next != &init_mm)
615 cpumask_set_cpu(cpu, mm_cpumask(next));
616 next_tlb_gen = atomic64_read(&next->context.tlb_gen);
617
618 choose_new_asid(next, next_tlb_gen, &new_asid, &need_flush);
619
620 /* Let nmi_uaccess_okay() know that we're changing CR3. */
621 this_cpu_write(cpu_tlbstate.loaded_mm, LOADED_MM_SWITCHING);
622 barrier();
623 }
624
625 if (need_flush) {
626 this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id);
627 this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen);
628 load_new_mm_cr3(next->pgd, new_asid, true);
629
630 trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
631 } else {
632 /* The new ASID is already up to date. */
633 load_new_mm_cr3(next->pgd, new_asid, false);
634
635 trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, 0);
636 }
637
638 /* Make sure we write CR3 before loaded_mm. */
639 barrier();
640
641 this_cpu_write(cpu_tlbstate.loaded_mm, next);
642 this_cpu_write(cpu_tlbstate.loaded_mm_asid, new_asid);
643
644 if (next != real_prev) {
645 cr4_update_pce_mm(next);
646 switch_ldt(real_prev, next);
647 }
648}
649
650/*
651 * Please ignore the name of this function. It should be called
652 * switch_to_kernel_thread().
653 *
654 * enter_lazy_tlb() is a hint from the scheduler that we are entering a
655 * kernel thread or other context without an mm. Acceptable implementations
656 * include doing nothing whatsoever, switching to init_mm, or various clever
657 * lazy tricks to try to minimize TLB flushes.
658 *
659 * The scheduler reserves the right to call enter_lazy_tlb() several times
660 * in a row. It will notify us that we're going back to a real mm by
661 * calling switch_mm_irqs_off().
662 */
663void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
664{
665 if (this_cpu_read(cpu_tlbstate.loaded_mm) == &init_mm)
666 return;
667
668 this_cpu_write(cpu_tlbstate_shared.is_lazy, true);
669}
670
671/*
672 * Call this when reinitializing a CPU. It fixes the following potential
673 * problems:
674 *
675 * - The ASID changed from what cpu_tlbstate thinks it is (most likely
676 * because the CPU was taken down and came back up with CR3's PCID
677 * bits clear. CPU hotplug can do this.
678 *
679 * - The TLB contains junk in slots corresponding to inactive ASIDs.
680 *
681 * - The CPU went so far out to lunch that it may have missed a TLB
682 * flush.
683 */
684void initialize_tlbstate_and_flush(void)
685{
686 int i;
687 struct mm_struct *mm = this_cpu_read(cpu_tlbstate.loaded_mm);
688 u64 tlb_gen = atomic64_read(&init_mm.context.tlb_gen);
689 unsigned long cr3 = __read_cr3();
690
691 /* Assert that CR3 already references the right mm. */
692 WARN_ON((cr3 & CR3_ADDR_MASK) != __pa(mm->pgd));
693
694 /*
695 * Assert that CR4.PCIDE is set if needed. (CR4.PCIDE initialization
696 * doesn't work like other CR4 bits because it can only be set from
697 * long mode.)
698 */
699 WARN_ON(boot_cpu_has(X86_FEATURE_PCID) &&
700 !(cr4_read_shadow() & X86_CR4_PCIDE));
701
702 /* Force ASID 0 and force a TLB flush. */
703 write_cr3(build_cr3(mm->pgd, 0));
704
705 /* Reinitialize tlbstate. */
706 this_cpu_write(cpu_tlbstate.last_user_mm_spec, LAST_USER_MM_INIT);
707 this_cpu_write(cpu_tlbstate.loaded_mm_asid, 0);
708 this_cpu_write(cpu_tlbstate.next_asid, 1);
709 this_cpu_write(cpu_tlbstate.ctxs[0].ctx_id, mm->context.ctx_id);
710 this_cpu_write(cpu_tlbstate.ctxs[0].tlb_gen, tlb_gen);
711
712 for (i = 1; i < TLB_NR_DYN_ASIDS; i++)
713 this_cpu_write(cpu_tlbstate.ctxs[i].ctx_id, 0);
714}
715
716/*
717 * flush_tlb_func()'s memory ordering requirement is that any
718 * TLB fills that happen after we flush the TLB are ordered after we
719 * read active_mm's tlb_gen. We don't need any explicit barriers
720 * because all x86 flush operations are serializing and the
721 * atomic64_read operation won't be reordered by the compiler.
722 */
723static void flush_tlb_func(void *info)
724{
725 /*
726 * We have three different tlb_gen values in here. They are:
727 *
728 * - mm_tlb_gen: the latest generation.
729 * - local_tlb_gen: the generation that this CPU has already caught
730 * up to.
731 * - f->new_tlb_gen: the generation that the requester of the flush
732 * wants us to catch up to.
733 */
734 const struct flush_tlb_info *f = info;
735 struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
736 u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
737 u64 local_tlb_gen = this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen);
738 bool local = smp_processor_id() == f->initiating_cpu;
739 unsigned long nr_invalidate = 0;
740 u64 mm_tlb_gen;
741
742 /* This code cannot presently handle being reentered. */
743 VM_WARN_ON(!irqs_disabled());
744
745 if (!local) {
746 inc_irq_stat(irq_tlb_count);
747 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
748
749 /* Can only happen on remote CPUs */
750 if (f->mm && f->mm != loaded_mm)
751 return;
752 }
753
754 if (unlikely(loaded_mm == &init_mm))
755 return;
756
757 VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].ctx_id) !=
758 loaded_mm->context.ctx_id);
759
760 if (this_cpu_read(cpu_tlbstate_shared.is_lazy)) {
761 /*
762 * We're in lazy mode. We need to at least flush our
763 * paging-structure cache to avoid speculatively reading
764 * garbage into our TLB. Since switching to init_mm is barely
765 * slower than a minimal flush, just switch to init_mm.
766 *
767 * This should be rare, with native_flush_tlb_multi() skipping
768 * IPIs to lazy TLB mode CPUs.
769 */
770 switch_mm_irqs_off(NULL, &init_mm, NULL);
771 return;
772 }
773
774 if (unlikely(f->new_tlb_gen != TLB_GENERATION_INVALID &&
775 f->new_tlb_gen <= local_tlb_gen)) {
776 /*
777 * The TLB is already up to date in respect to f->new_tlb_gen.
778 * While the core might be still behind mm_tlb_gen, checking
779 * mm_tlb_gen unnecessarily would have negative caching effects
780 * so avoid it.
781 */
782 return;
783 }
784
785 /*
786 * Defer mm_tlb_gen reading as long as possible to avoid cache
787 * contention.
788 */
789 mm_tlb_gen = atomic64_read(&loaded_mm->context.tlb_gen);
790
791 if (unlikely(local_tlb_gen == mm_tlb_gen)) {
792 /*
793 * There's nothing to do: we're already up to date. This can
794 * happen if two concurrent flushes happen -- the first flush to
795 * be handled can catch us all the way up, leaving no work for
796 * the second flush.
797 */
798 goto done;
799 }
800
801 WARN_ON_ONCE(local_tlb_gen > mm_tlb_gen);
802 WARN_ON_ONCE(f->new_tlb_gen > mm_tlb_gen);
803
804 /*
805 * If we get to this point, we know that our TLB is out of date.
806 * This does not strictly imply that we need to flush (it's
807 * possible that f->new_tlb_gen <= local_tlb_gen), but we're
808 * going to need to flush in the very near future, so we might
809 * as well get it over with.
810 *
811 * The only question is whether to do a full or partial flush.
812 *
813 * We do a partial flush if requested and two extra conditions
814 * are met:
815 *
816 * 1. f->new_tlb_gen == local_tlb_gen + 1. We have an invariant that
817 * we've always done all needed flushes to catch up to
818 * local_tlb_gen. If, for example, local_tlb_gen == 2 and
819 * f->new_tlb_gen == 3, then we know that the flush needed to bring
820 * us up to date for tlb_gen 3 is the partial flush we're
821 * processing.
822 *
823 * As an example of why this check is needed, suppose that there
824 * are two concurrent flushes. The first is a full flush that
825 * changes context.tlb_gen from 1 to 2. The second is a partial
826 * flush that changes context.tlb_gen from 2 to 3. If they get
827 * processed on this CPU in reverse order, we'll see
828 * local_tlb_gen == 1, mm_tlb_gen == 3, and end != TLB_FLUSH_ALL.
829 * If we were to use __flush_tlb_one_user() and set local_tlb_gen to
830 * 3, we'd be break the invariant: we'd update local_tlb_gen above
831 * 1 without the full flush that's needed for tlb_gen 2.
832 *
833 * 2. f->new_tlb_gen == mm_tlb_gen. This is purely an optimization.
834 * Partial TLB flushes are not all that much cheaper than full TLB
835 * flushes, so it seems unlikely that it would be a performance win
836 * to do a partial flush if that won't bring our TLB fully up to
837 * date. By doing a full flush instead, we can increase
838 * local_tlb_gen all the way to mm_tlb_gen and we can probably
839 * avoid another flush in the very near future.
840 */
841 if (f->end != TLB_FLUSH_ALL &&
842 f->new_tlb_gen == local_tlb_gen + 1 &&
843 f->new_tlb_gen == mm_tlb_gen) {
844 /* Partial flush */
845 unsigned long addr = f->start;
846
847 /* Partial flush cannot have invalid generations */
848 VM_WARN_ON(f->new_tlb_gen == TLB_GENERATION_INVALID);
849
850 /* Partial flush must have valid mm */
851 VM_WARN_ON(f->mm == NULL);
852
853 nr_invalidate = (f->end - f->start) >> f->stride_shift;
854
855 while (addr < f->end) {
856 flush_tlb_one_user(addr);
857 addr += 1UL << f->stride_shift;
858 }
859 if (local)
860 count_vm_tlb_events(NR_TLB_LOCAL_FLUSH_ONE, nr_invalidate);
861 } else {
862 /* Full flush. */
863 nr_invalidate = TLB_FLUSH_ALL;
864
865 flush_tlb_local();
866 if (local)
867 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
868 }
869
870 /* Both paths above update our state to mm_tlb_gen. */
871 this_cpu_write(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen, mm_tlb_gen);
872
873 /* Tracing is done in a unified manner to reduce the code size */
874done:
875 trace_tlb_flush(!local ? TLB_REMOTE_SHOOTDOWN :
876 (f->mm == NULL) ? TLB_LOCAL_SHOOTDOWN :
877 TLB_LOCAL_MM_SHOOTDOWN,
878 nr_invalidate);
879}
880
881static bool tlb_is_not_lazy(int cpu, void *data)
882{
883 return !per_cpu(cpu_tlbstate_shared.is_lazy, cpu);
884}
885
886DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state_shared, cpu_tlbstate_shared);
887EXPORT_PER_CPU_SYMBOL(cpu_tlbstate_shared);
888
889STATIC_NOPV void native_flush_tlb_multi(const struct cpumask *cpumask,
890 const struct flush_tlb_info *info)
891{
892 /*
893 * Do accounting and tracing. Note that there are (and have always been)
894 * cases in which a remote TLB flush will be traced, but eventually
895 * would not happen.
896 */
897 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
898 if (info->end == TLB_FLUSH_ALL)
899 trace_tlb_flush(TLB_REMOTE_SEND_IPI, TLB_FLUSH_ALL);
900 else
901 trace_tlb_flush(TLB_REMOTE_SEND_IPI,
902 (info->end - info->start) >> PAGE_SHIFT);
903
904 /*
905 * If no page tables were freed, we can skip sending IPIs to
906 * CPUs in lazy TLB mode. They will flush the CPU themselves
907 * at the next context switch.
908 *
909 * However, if page tables are getting freed, we need to send the
910 * IPI everywhere, to prevent CPUs in lazy TLB mode from tripping
911 * up on the new contents of what used to be page tables, while
912 * doing a speculative memory access.
913 */
914 if (info->freed_tables)
915 on_each_cpu_mask(cpumask, flush_tlb_func, (void *)info, true);
916 else
917 on_each_cpu_cond_mask(tlb_is_not_lazy, flush_tlb_func,
918 (void *)info, 1, cpumask);
919}
920
921void flush_tlb_multi(const struct cpumask *cpumask,
922 const struct flush_tlb_info *info)
923{
924 __flush_tlb_multi(cpumask, info);
925}
926
927/*
928 * See Documentation/x86/tlb.rst for details. We choose 33
929 * because it is large enough to cover the vast majority (at
930 * least 95%) of allocations, and is small enough that we are
931 * confident it will not cause too much overhead. Each single
932 * flush is about 100 ns, so this caps the maximum overhead at
933 * _about_ 3,000 ns.
934 *
935 * This is in units of pages.
936 */
937unsigned long tlb_single_page_flush_ceiling __read_mostly = 33;
938
939static DEFINE_PER_CPU_SHARED_ALIGNED(struct flush_tlb_info, flush_tlb_info);
940
941#ifdef CONFIG_DEBUG_VM
942static DEFINE_PER_CPU(unsigned int, flush_tlb_info_idx);
943#endif
944
945static struct flush_tlb_info *get_flush_tlb_info(struct mm_struct *mm,
946 unsigned long start, unsigned long end,
947 unsigned int stride_shift, bool freed_tables,
948 u64 new_tlb_gen)
949{
950 struct flush_tlb_info *info = this_cpu_ptr(&flush_tlb_info);
951
952#ifdef CONFIG_DEBUG_VM
953 /*
954 * Ensure that the following code is non-reentrant and flush_tlb_info
955 * is not overwritten. This means no TLB flushing is initiated by
956 * interrupt handlers and machine-check exception handlers.
957 */
958 BUG_ON(this_cpu_inc_return(flush_tlb_info_idx) != 1);
959#endif
960
961 info->start = start;
962 info->end = end;
963 info->mm = mm;
964 info->stride_shift = stride_shift;
965 info->freed_tables = freed_tables;
966 info->new_tlb_gen = new_tlb_gen;
967 info->initiating_cpu = smp_processor_id();
968
969 return info;
970}
971
972static void put_flush_tlb_info(void)
973{
974#ifdef CONFIG_DEBUG_VM
975 /* Complete reentrancy prevention checks */
976 barrier();
977 this_cpu_dec(flush_tlb_info_idx);
978#endif
979}
980
981void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
982 unsigned long end, unsigned int stride_shift,
983 bool freed_tables)
984{
985 struct flush_tlb_info *info;
986 u64 new_tlb_gen;
987 int cpu;
988
989 cpu = get_cpu();
990
991 /* Should we flush just the requested range? */
992 if ((end == TLB_FLUSH_ALL) ||
993 ((end - start) >> stride_shift) > tlb_single_page_flush_ceiling) {
994 start = 0;
995 end = TLB_FLUSH_ALL;
996 }
997
998 /* This is also a barrier that synchronizes with switch_mm(). */
999 new_tlb_gen = inc_mm_tlb_gen(mm);
1000
1001 info = get_flush_tlb_info(mm, start, end, stride_shift, freed_tables,
1002 new_tlb_gen);
1003
1004 /*
1005 * flush_tlb_multi() is not optimized for the common case in which only
1006 * a local TLB flush is needed. Optimize this use-case by calling
1007 * flush_tlb_func_local() directly in this case.
1008 */
1009 if (cpumask_any_but(mm_cpumask(mm), cpu) < nr_cpu_ids) {
1010 flush_tlb_multi(mm_cpumask(mm), info);
1011 } else if (mm == this_cpu_read(cpu_tlbstate.loaded_mm)) {
1012 lockdep_assert_irqs_enabled();
1013 local_irq_disable();
1014 flush_tlb_func(info);
1015 local_irq_enable();
1016 }
1017
1018 put_flush_tlb_info();
1019 put_cpu();
1020}
1021
1022
1023static void do_flush_tlb_all(void *info)
1024{
1025 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
1026 __flush_tlb_all();
1027}
1028
1029void flush_tlb_all(void)
1030{
1031 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
1032 on_each_cpu(do_flush_tlb_all, NULL, 1);
1033}
1034
1035static void do_kernel_range_flush(void *info)
1036{
1037 struct flush_tlb_info *f = info;
1038 unsigned long addr;
1039
1040 /* flush range by one by one 'invlpg' */
1041 for (addr = f->start; addr < f->end; addr += PAGE_SIZE)
1042 flush_tlb_one_kernel(addr);
1043}
1044
1045void flush_tlb_kernel_range(unsigned long start, unsigned long end)
1046{
1047 /* Balance as user space task's flush, a bit conservative */
1048 if (end == TLB_FLUSH_ALL ||
1049 (end - start) > tlb_single_page_flush_ceiling << PAGE_SHIFT) {
1050 on_each_cpu(do_flush_tlb_all, NULL, 1);
1051 } else {
1052 struct flush_tlb_info *info;
1053
1054 preempt_disable();
1055 info = get_flush_tlb_info(NULL, start, end, 0, false,
1056 TLB_GENERATION_INVALID);
1057
1058 on_each_cpu(do_kernel_range_flush, info, 1);
1059
1060 put_flush_tlb_info();
1061 preempt_enable();
1062 }
1063}
1064
1065/*
1066 * This can be used from process context to figure out what the value of
1067 * CR3 is without needing to do a (slow) __read_cr3().
1068 *
1069 * It's intended to be used for code like KVM that sneakily changes CR3
1070 * and needs to restore it. It needs to be used very carefully.
1071 */
1072unsigned long __get_current_cr3_fast(void)
1073{
1074 unsigned long cr3 = build_cr3(this_cpu_read(cpu_tlbstate.loaded_mm)->pgd,
1075 this_cpu_read(cpu_tlbstate.loaded_mm_asid));
1076
1077 /* For now, be very restrictive about when this can be called. */
1078 VM_WARN_ON(in_nmi() || preemptible());
1079
1080 VM_BUG_ON(cr3 != __read_cr3());
1081 return cr3;
1082}
1083EXPORT_SYMBOL_GPL(__get_current_cr3_fast);
1084
1085/*
1086 * Flush one page in the kernel mapping
1087 */
1088void flush_tlb_one_kernel(unsigned long addr)
1089{
1090 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
1091
1092 /*
1093 * If PTI is off, then __flush_tlb_one_user() is just INVLPG or its
1094 * paravirt equivalent. Even with PCID, this is sufficient: we only
1095 * use PCID if we also use global PTEs for the kernel mapping, and
1096 * INVLPG flushes global translations across all address spaces.
1097 *
1098 * If PTI is on, then the kernel is mapped with non-global PTEs, and
1099 * __flush_tlb_one_user() will flush the given address for the current
1100 * kernel address space and for its usermode counterpart, but it does
1101 * not flush it for other address spaces.
1102 */
1103 flush_tlb_one_user(addr);
1104
1105 if (!static_cpu_has(X86_FEATURE_PTI))
1106 return;
1107
1108 /*
1109 * See above. We need to propagate the flush to all other address
1110 * spaces. In principle, we only need to propagate it to kernelmode
1111 * address spaces, but the extra bookkeeping we would need is not
1112 * worth it.
1113 */
1114 this_cpu_write(cpu_tlbstate.invalidate_other, true);
1115}
1116
1117/*
1118 * Flush one page in the user mapping
1119 */
1120STATIC_NOPV void native_flush_tlb_one_user(unsigned long addr)
1121{
1122 u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
1123
1124 asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
1125
1126 if (!static_cpu_has(X86_FEATURE_PTI))
1127 return;
1128
1129 /*
1130 * Some platforms #GP if we call invpcid(type=1/2) before CR4.PCIDE=1.
1131 * Just use invalidate_user_asid() in case we are called early.
1132 */
1133 if (!this_cpu_has(X86_FEATURE_INVPCID_SINGLE))
1134 invalidate_user_asid(loaded_mm_asid);
1135 else
1136 invpcid_flush_one(user_pcid(loaded_mm_asid), addr);
1137}
1138
1139void flush_tlb_one_user(unsigned long addr)
1140{
1141 __flush_tlb_one_user(addr);
1142}
1143
1144/*
1145 * Flush everything
1146 */
1147STATIC_NOPV void native_flush_tlb_global(void)
1148{
1149 unsigned long flags;
1150
1151 if (static_cpu_has(X86_FEATURE_INVPCID)) {
1152 /*
1153 * Using INVPCID is considerably faster than a pair of writes
1154 * to CR4 sandwiched inside an IRQ flag save/restore.
1155 *
1156 * Note, this works with CR4.PCIDE=0 or 1.
1157 */
1158 invpcid_flush_all();
1159 return;
1160 }
1161
1162 /*
1163 * Read-modify-write to CR4 - protect it from preemption and
1164 * from interrupts. (Use the raw variant because this code can
1165 * be called from deep inside debugging code.)
1166 */
1167 raw_local_irq_save(flags);
1168
1169 __native_tlb_flush_global(this_cpu_read(cpu_tlbstate.cr4));
1170
1171 raw_local_irq_restore(flags);
1172}
1173
1174/*
1175 * Flush the entire current user mapping
1176 */
1177STATIC_NOPV void native_flush_tlb_local(void)
1178{
1179 /*
1180 * Preemption or interrupts must be disabled to protect the access
1181 * to the per CPU variable and to prevent being preempted between
1182 * read_cr3() and write_cr3().
1183 */
1184 WARN_ON_ONCE(preemptible());
1185
1186 invalidate_user_asid(this_cpu_read(cpu_tlbstate.loaded_mm_asid));
1187
1188 /* If current->mm == NULL then the read_cr3() "borrows" an mm */
1189 native_write_cr3(__native_read_cr3());
1190}
1191
1192void flush_tlb_local(void)
1193{
1194 __flush_tlb_local();
1195}
1196
1197/*
1198 * Flush everything
1199 */
1200void __flush_tlb_all(void)
1201{
1202 /*
1203 * This is to catch users with enabled preemption and the PGE feature
1204 * and don't trigger the warning in __native_flush_tlb().
1205 */
1206 VM_WARN_ON_ONCE(preemptible());
1207
1208 if (boot_cpu_has(X86_FEATURE_PGE)) {
1209 __flush_tlb_global();
1210 } else {
1211 /*
1212 * !PGE -> !PCID (setup_pcid()), thus every flush is total.
1213 */
1214 flush_tlb_local();
1215 }
1216}
1217EXPORT_SYMBOL_GPL(__flush_tlb_all);
1218
1219void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch)
1220{
1221 struct flush_tlb_info *info;
1222
1223 int cpu = get_cpu();
1224
1225 info = get_flush_tlb_info(NULL, 0, TLB_FLUSH_ALL, 0, false,
1226 TLB_GENERATION_INVALID);
1227 /*
1228 * flush_tlb_multi() is not optimized for the common case in which only
1229 * a local TLB flush is needed. Optimize this use-case by calling
1230 * flush_tlb_func_local() directly in this case.
1231 */
1232 if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) {
1233 flush_tlb_multi(&batch->cpumask, info);
1234 } else if (cpumask_test_cpu(cpu, &batch->cpumask)) {
1235 lockdep_assert_irqs_enabled();
1236 local_irq_disable();
1237 flush_tlb_func(info);
1238 local_irq_enable();
1239 }
1240
1241 cpumask_clear(&batch->cpumask);
1242
1243 put_flush_tlb_info();
1244 put_cpu();
1245}
1246
1247/*
1248 * Blindly accessing user memory from NMI context can be dangerous
1249 * if we're in the middle of switching the current user task or
1250 * switching the loaded mm. It can also be dangerous if we
1251 * interrupted some kernel code that was temporarily using a
1252 * different mm.
1253 */
1254bool nmi_uaccess_okay(void)
1255{
1256 struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
1257 struct mm_struct *current_mm = current->mm;
1258
1259 VM_WARN_ON_ONCE(!loaded_mm);
1260
1261 /*
1262 * The condition we want to check is
1263 * current_mm->pgd == __va(read_cr3_pa()). This may be slow, though,
1264 * if we're running in a VM with shadow paging, and nmi_uaccess_okay()
1265 * is supposed to be reasonably fast.
1266 *
1267 * Instead, we check the almost equivalent but somewhat conservative
1268 * condition below, and we rely on the fact that switch_mm_irqs_off()
1269 * sets loaded_mm to LOADED_MM_SWITCHING before writing to CR3.
1270 */
1271 if (loaded_mm != current_mm)
1272 return false;
1273
1274 VM_WARN_ON_ONCE(current_mm->pgd != __va(read_cr3_pa()));
1275
1276 return true;
1277}
1278
1279static ssize_t tlbflush_read_file(struct file *file, char __user *user_buf,
1280 size_t count, loff_t *ppos)
1281{
1282 char buf[32];
1283 unsigned int len;
1284
1285 len = sprintf(buf, "%ld\n", tlb_single_page_flush_ceiling);
1286 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1287}
1288
1289static ssize_t tlbflush_write_file(struct file *file,
1290 const char __user *user_buf, size_t count, loff_t *ppos)
1291{
1292 char buf[32];
1293 ssize_t len;
1294 int ceiling;
1295
1296 len = min(count, sizeof(buf) - 1);
1297 if (copy_from_user(buf, user_buf, len))
1298 return -EFAULT;
1299
1300 buf[len] = '\0';
1301 if (kstrtoint(buf, 0, &ceiling))
1302 return -EINVAL;
1303
1304 if (ceiling < 0)
1305 return -EINVAL;
1306
1307 tlb_single_page_flush_ceiling = ceiling;
1308 return count;
1309}
1310
1311static const struct file_operations fops_tlbflush = {
1312 .read = tlbflush_read_file,
1313 .write = tlbflush_write_file,
1314 .llseek = default_llseek,
1315};
1316
1317static int __init create_tlb_single_page_flush_ceiling(void)
1318{
1319 debugfs_create_file("tlb_single_page_flush_ceiling", S_IRUSR | S_IWUSR,
1320 arch_debugfs_dir, NULL, &fops_tlbflush);
1321 return 0;
1322}
1323late_initcall(create_tlb_single_page_flush_ceiling);
1#include <linux/init.h>
2
3#include <linux/mm.h>
4#include <linux/spinlock.h>
5#include <linux/smp.h>
6#include <linux/interrupt.h>
7#include <linux/module.h>
8#include <linux/cpu.h>
9
10#include <asm/tlbflush.h>
11#include <asm/mmu_context.h>
12#include <asm/cache.h>
13#include <asm/apic.h>
14#include <asm/uv/uv.h>
15
16DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate)
17 = { &init_mm, 0, };
18
19/*
20 * Smarter SMP flushing macros.
21 * c/o Linus Torvalds.
22 *
23 * These mean you can really definitely utterly forget about
24 * writing to user space from interrupts. (Its not allowed anyway).
25 *
26 * Optimizations Manfred Spraul <manfred@colorfullife.com>
27 *
28 * More scalable flush, from Andi Kleen
29 *
30 * To avoid global state use 8 different call vectors.
31 * Each CPU uses a specific vector to trigger flushes on other
32 * CPUs. Depending on the received vector the target CPUs look into
33 * the right array slot for the flush data.
34 *
35 * With more than 8 CPUs they are hashed to the 8 available
36 * vectors. The limited global vector space forces us to this right now.
37 * In future when interrupts are split into per CPU domains this could be
38 * fixed, at the cost of triggering multiple IPIs in some cases.
39 */
40
41union smp_flush_state {
42 struct {
43 struct mm_struct *flush_mm;
44 unsigned long flush_va;
45 raw_spinlock_t tlbstate_lock;
46 DECLARE_BITMAP(flush_cpumask, NR_CPUS);
47 };
48 char pad[INTERNODE_CACHE_BYTES];
49} ____cacheline_internodealigned_in_smp;
50
51/* State is put into the per CPU data section, but padded
52 to a full cache line because other CPUs can access it and we don't
53 want false sharing in the per cpu data segment. */
54static union smp_flush_state flush_state[NUM_INVALIDATE_TLB_VECTORS];
55
56static DEFINE_PER_CPU_READ_MOSTLY(int, tlb_vector_offset);
57
58/*
59 * We cannot call mmdrop() because we are in interrupt context,
60 * instead update mm->cpu_vm_mask.
61 */
62void leave_mm(int cpu)
63{
64 if (percpu_read(cpu_tlbstate.state) == TLBSTATE_OK)
65 BUG();
66 cpumask_clear_cpu(cpu,
67 mm_cpumask(percpu_read(cpu_tlbstate.active_mm)));
68 load_cr3(swapper_pg_dir);
69}
70EXPORT_SYMBOL_GPL(leave_mm);
71
72/*
73 *
74 * The flush IPI assumes that a thread switch happens in this order:
75 * [cpu0: the cpu that switches]
76 * 1) switch_mm() either 1a) or 1b)
77 * 1a) thread switch to a different mm
78 * 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
79 * Stop ipi delivery for the old mm. This is not synchronized with
80 * the other cpus, but smp_invalidate_interrupt ignore flush ipis
81 * for the wrong mm, and in the worst case we perform a superfluous
82 * tlb flush.
83 * 1a2) set cpu mmu_state to TLBSTATE_OK
84 * Now the smp_invalidate_interrupt won't call leave_mm if cpu0
85 * was in lazy tlb mode.
86 * 1a3) update cpu active_mm
87 * Now cpu0 accepts tlb flushes for the new mm.
88 * 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
89 * Now the other cpus will send tlb flush ipis.
90 * 1a4) change cr3.
91 * 1b) thread switch without mm change
92 * cpu active_mm is correct, cpu0 already handles
93 * flush ipis.
94 * 1b1) set cpu mmu_state to TLBSTATE_OK
95 * 1b2) test_and_set the cpu bit in cpu_vm_mask.
96 * Atomically set the bit [other cpus will start sending flush ipis],
97 * and test the bit.
98 * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
99 * 2) switch %%esp, ie current
100 *
101 * The interrupt must handle 2 special cases:
102 * - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
103 * - the cpu performs speculative tlb reads, i.e. even if the cpu only
104 * runs in kernel space, the cpu could load tlb entries for user space
105 * pages.
106 *
107 * The good news is that cpu mmu_state is local to each cpu, no
108 * write/read ordering problems.
109 */
110
111/*
112 * TLB flush IPI:
113 *
114 * 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
115 * 2) Leave the mm if we are in the lazy tlb mode.
116 *
117 * Interrupts are disabled.
118 */
119
120/*
121 * FIXME: use of asmlinkage is not consistent. On x86_64 it's noop
122 * but still used for documentation purpose but the usage is slightly
123 * inconsistent. On x86_32, asmlinkage is regparm(0) but interrupt
124 * entry calls in with the first parameter in %eax. Maybe define
125 * intrlinkage?
126 */
127#ifdef CONFIG_X86_64
128asmlinkage
129#endif
130void smp_invalidate_interrupt(struct pt_regs *regs)
131{
132 unsigned int cpu;
133 unsigned int sender;
134 union smp_flush_state *f;
135
136 cpu = smp_processor_id();
137 /*
138 * orig_rax contains the negated interrupt vector.
139 * Use that to determine where the sender put the data.
140 */
141 sender = ~regs->orig_ax - INVALIDATE_TLB_VECTOR_START;
142 f = &flush_state[sender];
143
144 if (!cpumask_test_cpu(cpu, to_cpumask(f->flush_cpumask)))
145 goto out;
146 /*
147 * This was a BUG() but until someone can quote me the
148 * line from the intel manual that guarantees an IPI to
149 * multiple CPUs is retried _only_ on the erroring CPUs
150 * its staying as a return
151 *
152 * BUG();
153 */
154
155 if (f->flush_mm == percpu_read(cpu_tlbstate.active_mm)) {
156 if (percpu_read(cpu_tlbstate.state) == TLBSTATE_OK) {
157 if (f->flush_va == TLB_FLUSH_ALL)
158 local_flush_tlb();
159 else
160 __flush_tlb_one(f->flush_va);
161 } else
162 leave_mm(cpu);
163 }
164out:
165 ack_APIC_irq();
166 smp_mb__before_clear_bit();
167 cpumask_clear_cpu(cpu, to_cpumask(f->flush_cpumask));
168 smp_mb__after_clear_bit();
169 inc_irq_stat(irq_tlb_count);
170}
171
172static void flush_tlb_others_ipi(const struct cpumask *cpumask,
173 struct mm_struct *mm, unsigned long va)
174{
175 unsigned int sender;
176 union smp_flush_state *f;
177
178 /* Caller has disabled preemption */
179 sender = this_cpu_read(tlb_vector_offset);
180 f = &flush_state[sender];
181
182 if (nr_cpu_ids > NUM_INVALIDATE_TLB_VECTORS)
183 raw_spin_lock(&f->tlbstate_lock);
184
185 f->flush_mm = mm;
186 f->flush_va = va;
187 if (cpumask_andnot(to_cpumask(f->flush_cpumask), cpumask, cpumask_of(smp_processor_id()))) {
188 /*
189 * We have to send the IPI only to
190 * CPUs affected.
191 */
192 apic->send_IPI_mask(to_cpumask(f->flush_cpumask),
193 INVALIDATE_TLB_VECTOR_START + sender);
194
195 while (!cpumask_empty(to_cpumask(f->flush_cpumask)))
196 cpu_relax();
197 }
198
199 f->flush_mm = NULL;
200 f->flush_va = 0;
201 if (nr_cpu_ids > NUM_INVALIDATE_TLB_VECTORS)
202 raw_spin_unlock(&f->tlbstate_lock);
203}
204
205void native_flush_tlb_others(const struct cpumask *cpumask,
206 struct mm_struct *mm, unsigned long va)
207{
208 if (is_uv_system()) {
209 unsigned int cpu;
210
211 cpu = smp_processor_id();
212 cpumask = uv_flush_tlb_others(cpumask, mm, va, cpu);
213 if (cpumask)
214 flush_tlb_others_ipi(cpumask, mm, va);
215 return;
216 }
217 flush_tlb_others_ipi(cpumask, mm, va);
218}
219
220static void __cpuinit calculate_tlb_offset(void)
221{
222 int cpu, node, nr_node_vecs, idx = 0;
223 /*
224 * we are changing tlb_vector_offset for each CPU in runtime, but this
225 * will not cause inconsistency, as the write is atomic under X86. we
226 * might see more lock contentions in a short time, but after all CPU's
227 * tlb_vector_offset are changed, everything should go normal
228 *
229 * Note: if NUM_INVALIDATE_TLB_VECTORS % nr_online_nodes !=0, we might
230 * waste some vectors.
231 **/
232 if (nr_online_nodes > NUM_INVALIDATE_TLB_VECTORS)
233 nr_node_vecs = 1;
234 else
235 nr_node_vecs = NUM_INVALIDATE_TLB_VECTORS/nr_online_nodes;
236
237 for_each_online_node(node) {
238 int node_offset = (idx % NUM_INVALIDATE_TLB_VECTORS) *
239 nr_node_vecs;
240 int cpu_offset = 0;
241 for_each_cpu(cpu, cpumask_of_node(node)) {
242 per_cpu(tlb_vector_offset, cpu) = node_offset +
243 cpu_offset;
244 cpu_offset++;
245 cpu_offset = cpu_offset % nr_node_vecs;
246 }
247 idx++;
248 }
249}
250
251static int __cpuinit tlb_cpuhp_notify(struct notifier_block *n,
252 unsigned long action, void *hcpu)
253{
254 switch (action & 0xf) {
255 case CPU_ONLINE:
256 case CPU_DEAD:
257 calculate_tlb_offset();
258 }
259 return NOTIFY_OK;
260}
261
262static int __cpuinit init_smp_flush(void)
263{
264 int i;
265
266 for (i = 0; i < ARRAY_SIZE(flush_state); i++)
267 raw_spin_lock_init(&flush_state[i].tlbstate_lock);
268
269 calculate_tlb_offset();
270 hotcpu_notifier(tlb_cpuhp_notify, 0);
271 return 0;
272}
273core_initcall(init_smp_flush);
274
275void flush_tlb_current_task(void)
276{
277 struct mm_struct *mm = current->mm;
278
279 preempt_disable();
280
281 local_flush_tlb();
282 if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
283 flush_tlb_others(mm_cpumask(mm), mm, TLB_FLUSH_ALL);
284 preempt_enable();
285}
286
287void flush_tlb_mm(struct mm_struct *mm)
288{
289 preempt_disable();
290
291 if (current->active_mm == mm) {
292 if (current->mm)
293 local_flush_tlb();
294 else
295 leave_mm(smp_processor_id());
296 }
297 if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
298 flush_tlb_others(mm_cpumask(mm), mm, TLB_FLUSH_ALL);
299
300 preempt_enable();
301}
302
303void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
304{
305 struct mm_struct *mm = vma->vm_mm;
306
307 preempt_disable();
308
309 if (current->active_mm == mm) {
310 if (current->mm)
311 __flush_tlb_one(va);
312 else
313 leave_mm(smp_processor_id());
314 }
315
316 if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
317 flush_tlb_others(mm_cpumask(mm), mm, va);
318
319 preempt_enable();
320}
321
322static void do_flush_tlb_all(void *info)
323{
324 __flush_tlb_all();
325 if (percpu_read(cpu_tlbstate.state) == TLBSTATE_LAZY)
326 leave_mm(smp_processor_id());
327}
328
329void flush_tlb_all(void)
330{
331 on_each_cpu(do_flush_tlb_all, NULL, 1);
332}