Loading...
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Processor capabilities determination functions.
4 *
5 * Copyright (C) xxxx the Anonymous
6 * Copyright (C) 1994 - 2006 Ralf Baechle
7 * Copyright (C) 2003, 2004 Maciej W. Rozycki
8 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 */
10#include <linux/init.h>
11#include <linux/kernel.h>
12#include <linux/ptrace.h>
13#include <linux/smp.h>
14#include <linux/stddef.h>
15#include <linux/export.h>
16
17#include <asm/bugs.h>
18#include <asm/cpu.h>
19#include <asm/cpu-features.h>
20#include <asm/cpu-type.h>
21#include <asm/fpu.h>
22#include <asm/mipsregs.h>
23#include <asm/mipsmtregs.h>
24#include <asm/msa.h>
25#include <asm/watch.h>
26#include <asm/elf.h>
27#include <asm/pgtable-bits.h>
28#include <asm/spram.h>
29#include <asm/traps.h>
30#include <linux/uaccess.h>
31
32#include "fpu-probe.h"
33
34#include <asm/mach-loongson64/cpucfg-emul.h>
35
36/* Hardware capabilities */
37unsigned int elf_hwcap __read_mostly;
38EXPORT_SYMBOL_GPL(elf_hwcap);
39
40static inline unsigned long cpu_get_msa_id(void)
41{
42 unsigned long status, msa_id;
43
44 status = read_c0_status();
45 __enable_fpu(FPU_64BIT);
46 enable_msa();
47 msa_id = read_msa_ir();
48 disable_msa();
49 write_c0_status(status);
50 return msa_id;
51}
52
53static int mips_dsp_disabled;
54
55static int __init dsp_disable(char *s)
56{
57 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
58 mips_dsp_disabled = 1;
59
60 return 1;
61}
62
63__setup("nodsp", dsp_disable);
64
65static int mips_htw_disabled;
66
67static int __init htw_disable(char *s)
68{
69 mips_htw_disabled = 1;
70 cpu_data[0].options &= ~MIPS_CPU_HTW;
71 write_c0_pwctl(read_c0_pwctl() &
72 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
73
74 return 1;
75}
76
77__setup("nohtw", htw_disable);
78
79static int mips_ftlb_disabled;
80static int mips_has_ftlb_configured;
81
82enum ftlb_flags {
83 FTLB_EN = 1 << 0,
84 FTLB_SET_PROB = 1 << 1,
85};
86
87static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
88
89static int __init ftlb_disable(char *s)
90{
91 unsigned int config4, mmuextdef;
92
93 /*
94 * If the core hasn't done any FTLB configuration, there is nothing
95 * for us to do here.
96 */
97 if (!mips_has_ftlb_configured)
98 return 1;
99
100 /* Disable it in the boot cpu */
101 if (set_ftlb_enable(&cpu_data[0], 0)) {
102 pr_warn("Can't turn FTLB off\n");
103 return 1;
104 }
105
106 config4 = read_c0_config4();
107
108 /* Check that FTLB has been disabled */
109 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
110 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
111 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
112 /* This should never happen */
113 pr_warn("FTLB could not be disabled!\n");
114 return 1;
115 }
116
117 mips_ftlb_disabled = 1;
118 mips_has_ftlb_configured = 0;
119
120 /*
121 * noftlb is mainly used for debug purposes so print
122 * an informative message instead of using pr_debug()
123 */
124 pr_info("FTLB has been disabled\n");
125
126 /*
127 * Some of these bits are duplicated in the decode_config4.
128 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
129 * once FTLB has been disabled so undo what decode_config4 did.
130 */
131 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
132 cpu_data[0].tlbsizeftlbsets;
133 cpu_data[0].tlbsizeftlbsets = 0;
134 cpu_data[0].tlbsizeftlbways = 0;
135
136 return 1;
137}
138
139__setup("noftlb", ftlb_disable);
140
141/*
142 * Check if the CPU has per tc perf counters
143 */
144static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c)
145{
146 if (read_c0_config7() & MTI_CONF7_PTC)
147 c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS;
148}
149
150static inline void check_errata(void)
151{
152 struct cpuinfo_mips *c = ¤t_cpu_data;
153
154 switch (current_cpu_type()) {
155 case CPU_34K:
156 /*
157 * Erratum "RPS May Cause Incorrect Instruction Execution"
158 * This code only handles VPE0, any SMP/RTOS code
159 * making use of VPE1 will be responsible for that VPE.
160 */
161 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
162 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
163 break;
164 default:
165 break;
166 }
167}
168
169void __init check_bugs32(void)
170{
171 check_errata();
172}
173
174/*
175 * Probe whether cpu has config register by trying to play with
176 * alternate cache bit and see whether it matters.
177 * It's used by cpu_probe to distinguish between R3000A and R3081.
178 */
179static inline int cpu_has_confreg(void)
180{
181#ifdef CONFIG_CPU_R3000
182 extern unsigned long r3k_cache_size(unsigned long);
183 unsigned long size1, size2;
184 unsigned long cfg = read_c0_conf();
185
186 size1 = r3k_cache_size(ST0_ISC);
187 write_c0_conf(cfg ^ R30XX_CONF_AC);
188 size2 = r3k_cache_size(ST0_ISC);
189 write_c0_conf(cfg);
190 return size1 != size2;
191#else
192 return 0;
193#endif
194}
195
196static inline void set_elf_platform(int cpu, const char *plat)
197{
198 if (cpu == 0)
199 __elf_platform = plat;
200}
201
202static inline void set_elf_base_platform(const char *plat)
203{
204 if (__elf_base_platform == NULL) {
205 __elf_base_platform = plat;
206 }
207}
208
209static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
210{
211#ifdef __NEED_VMBITS_PROBE
212 write_c0_entryhi(0x3fffffffffffe000ULL);
213 back_to_back_c0_hazard();
214 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
215#endif
216}
217
218static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
219{
220 switch (isa) {
221 case MIPS_CPU_ISA_M64R5:
222 c->isa_level |= MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5;
223 set_elf_base_platform("mips64r5");
224 fallthrough;
225 case MIPS_CPU_ISA_M64R2:
226 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
227 set_elf_base_platform("mips64r2");
228 fallthrough;
229 case MIPS_CPU_ISA_M64R1:
230 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
231 set_elf_base_platform("mips64");
232 fallthrough;
233 case MIPS_CPU_ISA_V:
234 c->isa_level |= MIPS_CPU_ISA_V;
235 set_elf_base_platform("mips5");
236 fallthrough;
237 case MIPS_CPU_ISA_IV:
238 c->isa_level |= MIPS_CPU_ISA_IV;
239 set_elf_base_platform("mips4");
240 fallthrough;
241 case MIPS_CPU_ISA_III:
242 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
243 set_elf_base_platform("mips3");
244 break;
245
246 /* R6 incompatible with everything else */
247 case MIPS_CPU_ISA_M64R6:
248 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
249 set_elf_base_platform("mips64r6");
250 fallthrough;
251 case MIPS_CPU_ISA_M32R6:
252 c->isa_level |= MIPS_CPU_ISA_M32R6;
253 set_elf_base_platform("mips32r6");
254 /* Break here so we don't add incompatible ISAs */
255 break;
256 case MIPS_CPU_ISA_M32R5:
257 c->isa_level |= MIPS_CPU_ISA_M32R5;
258 set_elf_base_platform("mips32r5");
259 fallthrough;
260 case MIPS_CPU_ISA_M32R2:
261 c->isa_level |= MIPS_CPU_ISA_M32R2;
262 set_elf_base_platform("mips32r2");
263 fallthrough;
264 case MIPS_CPU_ISA_M32R1:
265 c->isa_level |= MIPS_CPU_ISA_M32R1;
266 set_elf_base_platform("mips32");
267 fallthrough;
268 case MIPS_CPU_ISA_II:
269 c->isa_level |= MIPS_CPU_ISA_II;
270 set_elf_base_platform("mips2");
271 break;
272 }
273}
274
275static char unknown_isa[] = KERN_ERR \
276 "Unsupported ISA type, c0.config0: %d.";
277
278static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
279{
280
281 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
282
283 /*
284 * 0 = All TLBWR instructions go to FTLB
285 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
286 * FTLB and 1 goes to the VTLB.
287 * 2 = 7:1: As above with 7:1 ratio.
288 * 3 = 3:1: As above with 3:1 ratio.
289 *
290 * Use the linear midpoint as the probability threshold.
291 */
292 if (probability >= 12)
293 return 1;
294 else if (probability >= 6)
295 return 2;
296 else
297 /*
298 * So FTLB is less than 4 times bigger than VTLB.
299 * A 3:1 ratio can still be useful though.
300 */
301 return 3;
302}
303
304static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
305{
306 unsigned int config;
307
308 /* It's implementation dependent how the FTLB can be enabled */
309 switch (c->cputype) {
310 case CPU_PROAPTIV:
311 case CPU_P5600:
312 case CPU_P6600:
313 /* proAptiv & related cores use Config6 to enable the FTLB */
314 config = read_c0_config6();
315
316 if (flags & FTLB_EN)
317 config |= MTI_CONF6_FTLBEN;
318 else
319 config &= ~MTI_CONF6_FTLBEN;
320
321 if (flags & FTLB_SET_PROB) {
322 config &= ~(3 << MTI_CONF6_FTLBP_SHIFT);
323 config |= calculate_ftlb_probability(c)
324 << MTI_CONF6_FTLBP_SHIFT;
325 }
326
327 write_c0_config6(config);
328 back_to_back_c0_hazard();
329 break;
330 case CPU_I6400:
331 case CPU_I6500:
332 /* There's no way to disable the FTLB */
333 if (!(flags & FTLB_EN))
334 return 1;
335 return 0;
336 case CPU_LOONGSON64:
337 /* Flush ITLB, DTLB, VTLB and FTLB */
338 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
339 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
340 /* Loongson-3 cores use Config6 to enable the FTLB */
341 config = read_c0_config6();
342 if (flags & FTLB_EN)
343 /* Enable FTLB */
344 write_c0_config6(config & ~LOONGSON_CONF6_FTLBDIS);
345 else
346 /* Disable FTLB */
347 write_c0_config6(config | LOONGSON_CONF6_FTLBDIS);
348 break;
349 default:
350 return 1;
351 }
352
353 return 0;
354}
355
356static int mm_config(struct cpuinfo_mips *c)
357{
358 unsigned int config0, update, mm;
359
360 config0 = read_c0_config();
361 mm = config0 & MIPS_CONF_MM;
362
363 /*
364 * It's implementation dependent what type of write-merge is supported
365 * and whether it can be enabled/disabled. If it is settable lets make
366 * the merging allowed by default. Some platforms might have
367 * write-through caching unsupported. In this case just ignore the
368 * CP0.Config.MM bit field value.
369 */
370 switch (c->cputype) {
371 case CPU_24K:
372 case CPU_34K:
373 case CPU_74K:
374 case CPU_P5600:
375 case CPU_P6600:
376 c->options |= MIPS_CPU_MM_FULL;
377 update = MIPS_CONF_MM_FULL;
378 break;
379 case CPU_1004K:
380 case CPU_1074K:
381 case CPU_INTERAPTIV:
382 case CPU_PROAPTIV:
383 mm = 0;
384 fallthrough;
385 default:
386 update = 0;
387 break;
388 }
389
390 if (update) {
391 config0 = (config0 & ~MIPS_CONF_MM) | update;
392 write_c0_config(config0);
393 } else if (mm == MIPS_CONF_MM_SYSAD) {
394 c->options |= MIPS_CPU_MM_SYSAD;
395 } else if (mm == MIPS_CONF_MM_FULL) {
396 c->options |= MIPS_CPU_MM_FULL;
397 }
398
399 return 0;
400}
401
402static inline unsigned int decode_config0(struct cpuinfo_mips *c)
403{
404 unsigned int config0;
405 int isa, mt;
406
407 config0 = read_c0_config();
408
409 /*
410 * Look for Standard TLB or Dual VTLB and FTLB
411 */
412 mt = config0 & MIPS_CONF_MT;
413 if (mt == MIPS_CONF_MT_TLB)
414 c->options |= MIPS_CPU_TLB;
415 else if (mt == MIPS_CONF_MT_FTLB)
416 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
417
418 isa = (config0 & MIPS_CONF_AT) >> 13;
419 switch (isa) {
420 case 0:
421 switch ((config0 & MIPS_CONF_AR) >> 10) {
422 case 0:
423 set_isa(c, MIPS_CPU_ISA_M32R1);
424 break;
425 case 1:
426 set_isa(c, MIPS_CPU_ISA_M32R2);
427 break;
428 case 2:
429 set_isa(c, MIPS_CPU_ISA_M32R6);
430 break;
431 default:
432 goto unknown;
433 }
434 break;
435 case 2:
436 switch ((config0 & MIPS_CONF_AR) >> 10) {
437 case 0:
438 set_isa(c, MIPS_CPU_ISA_M64R1);
439 break;
440 case 1:
441 set_isa(c, MIPS_CPU_ISA_M64R2);
442 break;
443 case 2:
444 set_isa(c, MIPS_CPU_ISA_M64R6);
445 break;
446 default:
447 goto unknown;
448 }
449 break;
450 default:
451 goto unknown;
452 }
453
454 return config0 & MIPS_CONF_M;
455
456unknown:
457 panic(unknown_isa, config0);
458}
459
460static inline unsigned int decode_config1(struct cpuinfo_mips *c)
461{
462 unsigned int config1;
463
464 config1 = read_c0_config1();
465
466 if (config1 & MIPS_CONF1_MD)
467 c->ases |= MIPS_ASE_MDMX;
468 if (config1 & MIPS_CONF1_PC)
469 c->options |= MIPS_CPU_PERF;
470 if (config1 & MIPS_CONF1_WR)
471 c->options |= MIPS_CPU_WATCH;
472 if (config1 & MIPS_CONF1_CA)
473 c->ases |= MIPS_ASE_MIPS16;
474 if (config1 & MIPS_CONF1_EP)
475 c->options |= MIPS_CPU_EJTAG;
476 if (config1 & MIPS_CONF1_FP) {
477 c->options |= MIPS_CPU_FPU;
478 c->options |= MIPS_CPU_32FPR;
479 }
480 if (cpu_has_tlb) {
481 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
482 c->tlbsizevtlb = c->tlbsize;
483 c->tlbsizeftlbsets = 0;
484 }
485
486 return config1 & MIPS_CONF_M;
487}
488
489static inline unsigned int decode_config2(struct cpuinfo_mips *c)
490{
491 unsigned int config2;
492
493 config2 = read_c0_config2();
494
495 if (config2 & MIPS_CONF2_SL)
496 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
497
498 return config2 & MIPS_CONF_M;
499}
500
501static inline unsigned int decode_config3(struct cpuinfo_mips *c)
502{
503 unsigned int config3;
504
505 config3 = read_c0_config3();
506
507 if (config3 & MIPS_CONF3_SM) {
508 c->ases |= MIPS_ASE_SMARTMIPS;
509 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
510 }
511 if (config3 & MIPS_CONF3_RXI)
512 c->options |= MIPS_CPU_RIXI;
513 if (config3 & MIPS_CONF3_CTXTC)
514 c->options |= MIPS_CPU_CTXTC;
515 if (config3 & MIPS_CONF3_DSP)
516 c->ases |= MIPS_ASE_DSP;
517 if (config3 & MIPS_CONF3_DSP2P) {
518 c->ases |= MIPS_ASE_DSP2P;
519 if (cpu_has_mips_r6)
520 c->ases |= MIPS_ASE_DSP3;
521 }
522 if (config3 & MIPS_CONF3_VINT)
523 c->options |= MIPS_CPU_VINT;
524 if (config3 & MIPS_CONF3_VEIC)
525 c->options |= MIPS_CPU_VEIC;
526 if (config3 & MIPS_CONF3_LPA)
527 c->options |= MIPS_CPU_LPA;
528 if (config3 & MIPS_CONF3_MT)
529 c->ases |= MIPS_ASE_MIPSMT;
530 if (config3 & MIPS_CONF3_ULRI)
531 c->options |= MIPS_CPU_ULRI;
532 if (config3 & MIPS_CONF3_ISA)
533 c->options |= MIPS_CPU_MICROMIPS;
534 if (config3 & MIPS_CONF3_VZ)
535 c->ases |= MIPS_ASE_VZ;
536 if (config3 & MIPS_CONF3_SC)
537 c->options |= MIPS_CPU_SEGMENTS;
538 if (config3 & MIPS_CONF3_BI)
539 c->options |= MIPS_CPU_BADINSTR;
540 if (config3 & MIPS_CONF3_BP)
541 c->options |= MIPS_CPU_BADINSTRP;
542 if (config3 & MIPS_CONF3_MSA)
543 c->ases |= MIPS_ASE_MSA;
544 if (config3 & MIPS_CONF3_PW) {
545 c->htw_seq = 0;
546 c->options |= MIPS_CPU_HTW;
547 }
548 if (config3 & MIPS_CONF3_CDMM)
549 c->options |= MIPS_CPU_CDMM;
550 if (config3 & MIPS_CONF3_SP)
551 c->options |= MIPS_CPU_SP;
552
553 return config3 & MIPS_CONF_M;
554}
555
556static inline unsigned int decode_config4(struct cpuinfo_mips *c)
557{
558 unsigned int config4;
559 unsigned int newcf4;
560 unsigned int mmuextdef;
561 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
562 unsigned long asid_mask;
563
564 config4 = read_c0_config4();
565
566 if (cpu_has_tlb) {
567 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
568 c->options |= MIPS_CPU_TLBINV;
569
570 /*
571 * R6 has dropped the MMUExtDef field from config4.
572 * On R6 the fields always describe the FTLB, and only if it is
573 * present according to Config.MT.
574 */
575 if (!cpu_has_mips_r6)
576 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
577 else if (cpu_has_ftlb)
578 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
579 else
580 mmuextdef = 0;
581
582 switch (mmuextdef) {
583 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
584 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
585 c->tlbsizevtlb = c->tlbsize;
586 break;
587 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
588 c->tlbsizevtlb +=
589 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
590 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
591 c->tlbsize = c->tlbsizevtlb;
592 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
593 fallthrough;
594 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
595 if (mips_ftlb_disabled)
596 break;
597 newcf4 = (config4 & ~ftlb_page) |
598 (page_size_ftlb(mmuextdef) <<
599 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
600 write_c0_config4(newcf4);
601 back_to_back_c0_hazard();
602 config4 = read_c0_config4();
603 if (config4 != newcf4) {
604 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
605 PAGE_SIZE, config4);
606 /* Switch FTLB off */
607 set_ftlb_enable(c, 0);
608 mips_ftlb_disabled = 1;
609 break;
610 }
611 c->tlbsizeftlbsets = 1 <<
612 ((config4 & MIPS_CONF4_FTLBSETS) >>
613 MIPS_CONF4_FTLBSETS_SHIFT);
614 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
615 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
616 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
617 mips_has_ftlb_configured = 1;
618 break;
619 }
620 }
621
622 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
623 >> MIPS_CONF4_KSCREXIST_SHIFT;
624
625 asid_mask = MIPS_ENTRYHI_ASID;
626 if (config4 & MIPS_CONF4_AE)
627 asid_mask |= MIPS_ENTRYHI_ASIDX;
628 set_cpu_asid_mask(c, asid_mask);
629
630 /*
631 * Warn if the computed ASID mask doesn't match the mask the kernel
632 * is built for. This may indicate either a serious problem or an
633 * easy optimisation opportunity, but either way should be addressed.
634 */
635 WARN_ON(asid_mask != cpu_asid_mask(c));
636
637 return config4 & MIPS_CONF_M;
638}
639
640static inline unsigned int decode_config5(struct cpuinfo_mips *c)
641{
642 unsigned int config5, max_mmid_width;
643 unsigned long asid_mask;
644
645 config5 = read_c0_config5();
646 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
647
648 if (cpu_has_mips_r6) {
649 if (!__builtin_constant_p(cpu_has_mmid) || cpu_has_mmid)
650 config5 |= MIPS_CONF5_MI;
651 else
652 config5 &= ~MIPS_CONF5_MI;
653 }
654
655 write_c0_config5(config5);
656
657 if (config5 & MIPS_CONF5_EVA)
658 c->options |= MIPS_CPU_EVA;
659 if (config5 & MIPS_CONF5_MRP)
660 c->options |= MIPS_CPU_MAAR;
661 if (config5 & MIPS_CONF5_LLB)
662 c->options |= MIPS_CPU_RW_LLB;
663 if (config5 & MIPS_CONF5_MVH)
664 c->options |= MIPS_CPU_MVH;
665 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
666 c->options |= MIPS_CPU_VP;
667 if (config5 & MIPS_CONF5_CA2)
668 c->ases |= MIPS_ASE_MIPS16E2;
669
670 if (config5 & MIPS_CONF5_CRCP)
671 elf_hwcap |= HWCAP_MIPS_CRC32;
672
673 if (cpu_has_mips_r6) {
674 /* Ensure the write to config5 above takes effect */
675 back_to_back_c0_hazard();
676
677 /* Check whether we successfully enabled MMID support */
678 config5 = read_c0_config5();
679 if (config5 & MIPS_CONF5_MI)
680 c->options |= MIPS_CPU_MMID;
681
682 /*
683 * Warn if we've hardcoded cpu_has_mmid to a value unsuitable
684 * for the CPU we're running on, or if CPUs in an SMP system
685 * have inconsistent MMID support.
686 */
687 WARN_ON(!!cpu_has_mmid != !!(config5 & MIPS_CONF5_MI));
688
689 if (cpu_has_mmid) {
690 write_c0_memorymapid(~0ul);
691 back_to_back_c0_hazard();
692 asid_mask = read_c0_memorymapid();
693
694 /*
695 * We maintain a bitmap to track MMID allocation, and
696 * need a sensible upper bound on the size of that
697 * bitmap. The initial CPU with MMID support (I6500)
698 * supports 16 bit MMIDs, which gives us an 8KiB
699 * bitmap. The architecture recommends that hardware
700 * support 32 bit MMIDs, which would give us a 512MiB
701 * bitmap - that's too big in most cases.
702 *
703 * Cap MMID width at 16 bits for now & we can revisit
704 * this if & when hardware supports anything wider.
705 */
706 max_mmid_width = 16;
707 if (asid_mask > GENMASK(max_mmid_width - 1, 0)) {
708 pr_info("Capping MMID width at %d bits",
709 max_mmid_width);
710 asid_mask = GENMASK(max_mmid_width - 1, 0);
711 }
712
713 set_cpu_asid_mask(c, asid_mask);
714 }
715 }
716
717 return config5 & MIPS_CONF_M;
718}
719
720static void decode_configs(struct cpuinfo_mips *c)
721{
722 int ok;
723
724 /* MIPS32 or MIPS64 compliant CPU. */
725 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
726 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
727
728 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
729
730 /* Enable FTLB if present and not disabled */
731 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
732
733 ok = decode_config0(c); /* Read Config registers. */
734 BUG_ON(!ok); /* Arch spec violation! */
735 if (ok)
736 ok = decode_config1(c);
737 if (ok)
738 ok = decode_config2(c);
739 if (ok)
740 ok = decode_config3(c);
741 if (ok)
742 ok = decode_config4(c);
743 if (ok)
744 ok = decode_config5(c);
745
746 /* Probe the EBase.WG bit */
747 if (cpu_has_mips_r2_r6) {
748 u64 ebase;
749 unsigned int status;
750
751 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
752 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
753 : (s32)read_c0_ebase();
754 if (ebase & MIPS_EBASE_WG) {
755 /* WG bit already set, we can avoid the clumsy probe */
756 c->options |= MIPS_CPU_EBASE_WG;
757 } else {
758 /* Its UNDEFINED to change EBase while BEV=0 */
759 status = read_c0_status();
760 write_c0_status(status | ST0_BEV);
761 irq_enable_hazard();
762 /*
763 * On pre-r6 cores, this may well clobber the upper bits
764 * of EBase. This is hard to avoid without potentially
765 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
766 */
767 if (cpu_has_mips64r6)
768 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
769 else
770 write_c0_ebase(ebase | MIPS_EBASE_WG);
771 back_to_back_c0_hazard();
772 /* Restore BEV */
773 write_c0_status(status);
774 if (read_c0_ebase() & MIPS_EBASE_WG) {
775 c->options |= MIPS_CPU_EBASE_WG;
776 write_c0_ebase(ebase);
777 }
778 }
779 }
780
781 /* configure the FTLB write probability */
782 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
783
784 mips_probe_watch_registers(c);
785
786#ifndef CONFIG_MIPS_CPS
787 if (cpu_has_mips_r2_r6) {
788 unsigned int core;
789
790 core = get_ebase_cpunum();
791 if (cpu_has_mipsmt)
792 core >>= fls(core_nvpes()) - 1;
793 cpu_set_core(c, core);
794 }
795#endif
796}
797
798/*
799 * Probe for certain guest capabilities by writing config bits and reading back.
800 * Finally write back the original value.
801 */
802#define probe_gc0_config(name, maxconf, bits) \
803do { \
804 unsigned int tmp; \
805 tmp = read_gc0_##name(); \
806 write_gc0_##name(tmp | (bits)); \
807 back_to_back_c0_hazard(); \
808 maxconf = read_gc0_##name(); \
809 write_gc0_##name(tmp); \
810} while (0)
811
812/*
813 * Probe for dynamic guest capabilities by changing certain config bits and
814 * reading back to see if they change. Finally write back the original value.
815 */
816#define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \
817do { \
818 maxconf = read_gc0_##name(); \
819 write_gc0_##name(maxconf ^ (bits)); \
820 back_to_back_c0_hazard(); \
821 dynconf = maxconf ^ read_gc0_##name(); \
822 write_gc0_##name(maxconf); \
823 maxconf |= dynconf; \
824} while (0)
825
826static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
827{
828 unsigned int config0;
829
830 probe_gc0_config(config, config0, MIPS_CONF_M);
831
832 if (config0 & MIPS_CONF_M)
833 c->guest.conf |= BIT(1);
834 return config0 & MIPS_CONF_M;
835}
836
837static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
838{
839 unsigned int config1, config1_dyn;
840
841 probe_gc0_config_dyn(config1, config1, config1_dyn,
842 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
843 MIPS_CONF1_FP);
844
845 if (config1 & MIPS_CONF1_FP)
846 c->guest.options |= MIPS_CPU_FPU;
847 if (config1_dyn & MIPS_CONF1_FP)
848 c->guest.options_dyn |= MIPS_CPU_FPU;
849
850 if (config1 & MIPS_CONF1_WR)
851 c->guest.options |= MIPS_CPU_WATCH;
852 if (config1_dyn & MIPS_CONF1_WR)
853 c->guest.options_dyn |= MIPS_CPU_WATCH;
854
855 if (config1 & MIPS_CONF1_PC)
856 c->guest.options |= MIPS_CPU_PERF;
857 if (config1_dyn & MIPS_CONF1_PC)
858 c->guest.options_dyn |= MIPS_CPU_PERF;
859
860 if (config1 & MIPS_CONF_M)
861 c->guest.conf |= BIT(2);
862 return config1 & MIPS_CONF_M;
863}
864
865static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
866{
867 unsigned int config2;
868
869 probe_gc0_config(config2, config2, MIPS_CONF_M);
870
871 if (config2 & MIPS_CONF_M)
872 c->guest.conf |= BIT(3);
873 return config2 & MIPS_CONF_M;
874}
875
876static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
877{
878 unsigned int config3, config3_dyn;
879
880 probe_gc0_config_dyn(config3, config3, config3_dyn,
881 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI |
882 MIPS_CONF3_CTXTC);
883
884 if (config3 & MIPS_CONF3_CTXTC)
885 c->guest.options |= MIPS_CPU_CTXTC;
886 if (config3_dyn & MIPS_CONF3_CTXTC)
887 c->guest.options_dyn |= MIPS_CPU_CTXTC;
888
889 if (config3 & MIPS_CONF3_PW)
890 c->guest.options |= MIPS_CPU_HTW;
891
892 if (config3 & MIPS_CONF3_ULRI)
893 c->guest.options |= MIPS_CPU_ULRI;
894
895 if (config3 & MIPS_CONF3_SC)
896 c->guest.options |= MIPS_CPU_SEGMENTS;
897
898 if (config3 & MIPS_CONF3_BI)
899 c->guest.options |= MIPS_CPU_BADINSTR;
900 if (config3 & MIPS_CONF3_BP)
901 c->guest.options |= MIPS_CPU_BADINSTRP;
902
903 if (config3 & MIPS_CONF3_MSA)
904 c->guest.ases |= MIPS_ASE_MSA;
905 if (config3_dyn & MIPS_CONF3_MSA)
906 c->guest.ases_dyn |= MIPS_ASE_MSA;
907
908 if (config3 & MIPS_CONF_M)
909 c->guest.conf |= BIT(4);
910 return config3 & MIPS_CONF_M;
911}
912
913static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
914{
915 unsigned int config4;
916
917 probe_gc0_config(config4, config4,
918 MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
919
920 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
921 >> MIPS_CONF4_KSCREXIST_SHIFT;
922
923 if (config4 & MIPS_CONF_M)
924 c->guest.conf |= BIT(5);
925 return config4 & MIPS_CONF_M;
926}
927
928static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
929{
930 unsigned int config5, config5_dyn;
931
932 probe_gc0_config_dyn(config5, config5, config5_dyn,
933 MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP);
934
935 if (config5 & MIPS_CONF5_MRP)
936 c->guest.options |= MIPS_CPU_MAAR;
937 if (config5_dyn & MIPS_CONF5_MRP)
938 c->guest.options_dyn |= MIPS_CPU_MAAR;
939
940 if (config5 & MIPS_CONF5_LLB)
941 c->guest.options |= MIPS_CPU_RW_LLB;
942
943 if (config5 & MIPS_CONF5_MVH)
944 c->guest.options |= MIPS_CPU_MVH;
945
946 if (config5 & MIPS_CONF_M)
947 c->guest.conf |= BIT(6);
948 return config5 & MIPS_CONF_M;
949}
950
951static inline void decode_guest_configs(struct cpuinfo_mips *c)
952{
953 unsigned int ok;
954
955 ok = decode_guest_config0(c);
956 if (ok)
957 ok = decode_guest_config1(c);
958 if (ok)
959 ok = decode_guest_config2(c);
960 if (ok)
961 ok = decode_guest_config3(c);
962 if (ok)
963 ok = decode_guest_config4(c);
964 if (ok)
965 decode_guest_config5(c);
966}
967
968static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
969{
970 unsigned int guestctl0, temp;
971
972 guestctl0 = read_c0_guestctl0();
973
974 if (guestctl0 & MIPS_GCTL0_G0E)
975 c->options |= MIPS_CPU_GUESTCTL0EXT;
976 if (guestctl0 & MIPS_GCTL0_G1)
977 c->options |= MIPS_CPU_GUESTCTL1;
978 if (guestctl0 & MIPS_GCTL0_G2)
979 c->options |= MIPS_CPU_GUESTCTL2;
980 if (!(guestctl0 & MIPS_GCTL0_RAD)) {
981 c->options |= MIPS_CPU_GUESTID;
982
983 /*
984 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
985 * first, otherwise all data accesses will be fully virtualised
986 * as if they were performed by guest mode.
987 */
988 write_c0_guestctl1(0);
989 tlbw_use_hazard();
990
991 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
992 back_to_back_c0_hazard();
993 temp = read_c0_guestctl0();
994
995 if (temp & MIPS_GCTL0_DRG) {
996 write_c0_guestctl0(guestctl0);
997 c->options |= MIPS_CPU_DRG;
998 }
999 }
1000}
1001
1002static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1003{
1004 if (cpu_has_guestid) {
1005 /* determine the number of bits of GuestID available */
1006 write_c0_guestctl1(MIPS_GCTL1_ID);
1007 back_to_back_c0_hazard();
1008 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1009 >> MIPS_GCTL1_ID_SHIFT;
1010 write_c0_guestctl1(0);
1011 }
1012}
1013
1014static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1015{
1016 /* determine the number of bits of GTOffset available */
1017 write_c0_gtoffset(0xffffffff);
1018 back_to_back_c0_hazard();
1019 c->gtoffset_mask = read_c0_gtoffset();
1020 write_c0_gtoffset(0);
1021}
1022
1023static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1024{
1025 cpu_probe_guestctl0(c);
1026 if (cpu_has_guestctl1)
1027 cpu_probe_guestctl1(c);
1028
1029 cpu_probe_gtoffset(c);
1030
1031 decode_guest_configs(c);
1032}
1033
1034#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1035 | MIPS_CPU_COUNTER)
1036
1037static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1038{
1039 switch (c->processor_id & PRID_IMP_MASK) {
1040 case PRID_IMP_R2000:
1041 c->cputype = CPU_R2000;
1042 __cpu_name[cpu] = "R2000";
1043 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1044 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1045 MIPS_CPU_NOFPUEX;
1046 if (__cpu_has_fpu())
1047 c->options |= MIPS_CPU_FPU;
1048 c->tlbsize = 64;
1049 break;
1050 case PRID_IMP_R3000:
1051 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
1052 if (cpu_has_confreg()) {
1053 c->cputype = CPU_R3081E;
1054 __cpu_name[cpu] = "R3081";
1055 } else {
1056 c->cputype = CPU_R3000A;
1057 __cpu_name[cpu] = "R3000A";
1058 }
1059 } else {
1060 c->cputype = CPU_R3000;
1061 __cpu_name[cpu] = "R3000";
1062 }
1063 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1064 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1065 MIPS_CPU_NOFPUEX;
1066 if (__cpu_has_fpu())
1067 c->options |= MIPS_CPU_FPU;
1068 c->tlbsize = 64;
1069 break;
1070 case PRID_IMP_R4000:
1071 if (read_c0_config() & CONF_SC) {
1072 if ((c->processor_id & PRID_REV_MASK) >=
1073 PRID_REV_R4400) {
1074 c->cputype = CPU_R4400PC;
1075 __cpu_name[cpu] = "R4400PC";
1076 } else {
1077 c->cputype = CPU_R4000PC;
1078 __cpu_name[cpu] = "R4000PC";
1079 }
1080 } else {
1081 int cca = read_c0_config() & CONF_CM_CMASK;
1082 int mc;
1083
1084 /*
1085 * SC and MC versions can't be reliably told apart,
1086 * but only the latter support coherent caching
1087 * modes so assume the firmware has set the KSEG0
1088 * coherency attribute reasonably (if uncached, we
1089 * assume SC).
1090 */
1091 switch (cca) {
1092 case CONF_CM_CACHABLE_CE:
1093 case CONF_CM_CACHABLE_COW:
1094 case CONF_CM_CACHABLE_CUW:
1095 mc = 1;
1096 break;
1097 default:
1098 mc = 0;
1099 break;
1100 }
1101 if ((c->processor_id & PRID_REV_MASK) >=
1102 PRID_REV_R4400) {
1103 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1104 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
1105 } else {
1106 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1107 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
1108 }
1109 }
1110
1111 set_isa(c, MIPS_CPU_ISA_III);
1112 c->fpu_msk31 |= FPU_CSR_CONDX;
1113 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1114 MIPS_CPU_WATCH | MIPS_CPU_VCE |
1115 MIPS_CPU_LLSC;
1116 c->tlbsize = 48;
1117 break;
1118 case PRID_IMP_R4300:
1119 c->cputype = CPU_R4300;
1120 __cpu_name[cpu] = "R4300";
1121 set_isa(c, MIPS_CPU_ISA_III);
1122 c->fpu_msk31 |= FPU_CSR_CONDX;
1123 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1124 MIPS_CPU_LLSC;
1125 c->tlbsize = 32;
1126 break;
1127 case PRID_IMP_R4600:
1128 c->cputype = CPU_R4600;
1129 __cpu_name[cpu] = "R4600";
1130 set_isa(c, MIPS_CPU_ISA_III);
1131 c->fpu_msk31 |= FPU_CSR_CONDX;
1132 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1133 MIPS_CPU_LLSC;
1134 c->tlbsize = 48;
1135 break;
1136 #if 0
1137 case PRID_IMP_R4650:
1138 /*
1139 * This processor doesn't have an MMU, so it's not
1140 * "real easy" to run Linux on it. It is left purely
1141 * for documentation. Commented out because it shares
1142 * it's c0_prid id number with the TX3900.
1143 */
1144 c->cputype = CPU_R4650;
1145 __cpu_name[cpu] = "R4650";
1146 set_isa(c, MIPS_CPU_ISA_III);
1147 c->fpu_msk31 |= FPU_CSR_CONDX;
1148 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1149 c->tlbsize = 48;
1150 break;
1151 #endif
1152 case PRID_IMP_R4700:
1153 c->cputype = CPU_R4700;
1154 __cpu_name[cpu] = "R4700";
1155 set_isa(c, MIPS_CPU_ISA_III);
1156 c->fpu_msk31 |= FPU_CSR_CONDX;
1157 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1158 MIPS_CPU_LLSC;
1159 c->tlbsize = 48;
1160 break;
1161 case PRID_IMP_TX49:
1162 c->cputype = CPU_TX49XX;
1163 __cpu_name[cpu] = "R49XX";
1164 set_isa(c, MIPS_CPU_ISA_III);
1165 c->fpu_msk31 |= FPU_CSR_CONDX;
1166 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1167 if (!(c->processor_id & 0x08))
1168 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1169 c->tlbsize = 48;
1170 break;
1171 case PRID_IMP_R5000:
1172 c->cputype = CPU_R5000;
1173 __cpu_name[cpu] = "R5000";
1174 set_isa(c, MIPS_CPU_ISA_IV);
1175 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1176 MIPS_CPU_LLSC;
1177 c->tlbsize = 48;
1178 break;
1179 case PRID_IMP_R5500:
1180 c->cputype = CPU_R5500;
1181 __cpu_name[cpu] = "R5500";
1182 set_isa(c, MIPS_CPU_ISA_IV);
1183 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1184 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1185 c->tlbsize = 48;
1186 break;
1187 case PRID_IMP_NEVADA:
1188 c->cputype = CPU_NEVADA;
1189 __cpu_name[cpu] = "Nevada";
1190 set_isa(c, MIPS_CPU_ISA_IV);
1191 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1192 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1193 c->tlbsize = 48;
1194 break;
1195 case PRID_IMP_RM7000:
1196 c->cputype = CPU_RM7000;
1197 __cpu_name[cpu] = "RM7000";
1198 set_isa(c, MIPS_CPU_ISA_IV);
1199 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1200 MIPS_CPU_LLSC;
1201 /*
1202 * Undocumented RM7000: Bit 29 in the info register of
1203 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1204 * entries.
1205 *
1206 * 29 1 => 64 entry JTLB
1207 * 0 => 48 entry JTLB
1208 */
1209 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1210 break;
1211 case PRID_IMP_R10000:
1212 c->cputype = CPU_R10000;
1213 __cpu_name[cpu] = "R10000";
1214 set_isa(c, MIPS_CPU_ISA_IV);
1215 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1216 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1217 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1218 MIPS_CPU_LLSC;
1219 c->tlbsize = 64;
1220 break;
1221 case PRID_IMP_R12000:
1222 c->cputype = CPU_R12000;
1223 __cpu_name[cpu] = "R12000";
1224 set_isa(c, MIPS_CPU_ISA_IV);
1225 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1226 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1227 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1228 MIPS_CPU_LLSC;
1229 c->tlbsize = 64;
1230 write_c0_r10k_diag(read_c0_r10k_diag() | R10K_DIAG_E_GHIST);
1231 break;
1232 case PRID_IMP_R14000:
1233 if (((c->processor_id >> 4) & 0x0f) > 2) {
1234 c->cputype = CPU_R16000;
1235 __cpu_name[cpu] = "R16000";
1236 } else {
1237 c->cputype = CPU_R14000;
1238 __cpu_name[cpu] = "R14000";
1239 }
1240 set_isa(c, MIPS_CPU_ISA_IV);
1241 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1242 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1243 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1244 MIPS_CPU_LLSC;
1245 c->tlbsize = 64;
1246 write_c0_r10k_diag(read_c0_r10k_diag() | R10K_DIAG_E_GHIST);
1247 break;
1248 case PRID_IMP_LOONGSON_64C: /* Loongson-2/3 */
1249 switch (c->processor_id & PRID_REV_MASK) {
1250 case PRID_REV_LOONGSON2E:
1251 c->cputype = CPU_LOONGSON2EF;
1252 __cpu_name[cpu] = "ICT Loongson-2";
1253 set_elf_platform(cpu, "loongson2e");
1254 set_isa(c, MIPS_CPU_ISA_III);
1255 c->fpu_msk31 |= FPU_CSR_CONDX;
1256 break;
1257 case PRID_REV_LOONGSON2F:
1258 c->cputype = CPU_LOONGSON2EF;
1259 __cpu_name[cpu] = "ICT Loongson-2";
1260 set_elf_platform(cpu, "loongson2f");
1261 set_isa(c, MIPS_CPU_ISA_III);
1262 c->fpu_msk31 |= FPU_CSR_CONDX;
1263 break;
1264 case PRID_REV_LOONGSON3A_R1:
1265 c->cputype = CPU_LOONGSON64;
1266 __cpu_name[cpu] = "ICT Loongson-3";
1267 set_elf_platform(cpu, "loongson3a");
1268 set_isa(c, MIPS_CPU_ISA_M64R1);
1269 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1270 MIPS_ASE_LOONGSON_EXT);
1271 break;
1272 case PRID_REV_LOONGSON3B_R1:
1273 case PRID_REV_LOONGSON3B_R2:
1274 c->cputype = CPU_LOONGSON64;
1275 __cpu_name[cpu] = "ICT Loongson-3";
1276 set_elf_platform(cpu, "loongson3b");
1277 set_isa(c, MIPS_CPU_ISA_M64R1);
1278 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1279 MIPS_ASE_LOONGSON_EXT);
1280 break;
1281 }
1282
1283 c->options = R4K_OPTS |
1284 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1285 MIPS_CPU_32FPR;
1286 c->tlbsize = 64;
1287 set_cpu_asid_mask(c, MIPS_ENTRYHI_ASID);
1288 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1289 break;
1290 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1291 decode_configs(c);
1292
1293 c->cputype = CPU_LOONGSON32;
1294
1295 switch (c->processor_id & PRID_REV_MASK) {
1296 case PRID_REV_LOONGSON1B:
1297 __cpu_name[cpu] = "Loongson 1B";
1298 break;
1299 }
1300
1301 break;
1302 }
1303}
1304
1305static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1306{
1307 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1308 switch (c->processor_id & PRID_IMP_MASK) {
1309 case PRID_IMP_QEMU_GENERIC:
1310 c->writecombine = _CACHE_UNCACHED;
1311 c->cputype = CPU_QEMU_GENERIC;
1312 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1313 break;
1314 case PRID_IMP_4KC:
1315 c->cputype = CPU_4KC;
1316 c->writecombine = _CACHE_UNCACHED;
1317 __cpu_name[cpu] = "MIPS 4Kc";
1318 break;
1319 case PRID_IMP_4KEC:
1320 case PRID_IMP_4KECR2:
1321 c->cputype = CPU_4KEC;
1322 c->writecombine = _CACHE_UNCACHED;
1323 __cpu_name[cpu] = "MIPS 4KEc";
1324 break;
1325 case PRID_IMP_4KSC:
1326 case PRID_IMP_4KSD:
1327 c->cputype = CPU_4KSC;
1328 c->writecombine = _CACHE_UNCACHED;
1329 __cpu_name[cpu] = "MIPS 4KSc";
1330 break;
1331 case PRID_IMP_5KC:
1332 c->cputype = CPU_5KC;
1333 c->writecombine = _CACHE_UNCACHED;
1334 __cpu_name[cpu] = "MIPS 5Kc";
1335 break;
1336 case PRID_IMP_5KE:
1337 c->cputype = CPU_5KE;
1338 c->writecombine = _CACHE_UNCACHED;
1339 __cpu_name[cpu] = "MIPS 5KE";
1340 break;
1341 case PRID_IMP_20KC:
1342 c->cputype = CPU_20KC;
1343 c->writecombine = _CACHE_UNCACHED;
1344 __cpu_name[cpu] = "MIPS 20Kc";
1345 break;
1346 case PRID_IMP_24K:
1347 c->cputype = CPU_24K;
1348 c->writecombine = _CACHE_UNCACHED;
1349 __cpu_name[cpu] = "MIPS 24Kc";
1350 break;
1351 case PRID_IMP_24KE:
1352 c->cputype = CPU_24K;
1353 c->writecombine = _CACHE_UNCACHED;
1354 __cpu_name[cpu] = "MIPS 24KEc";
1355 break;
1356 case PRID_IMP_25KF:
1357 c->cputype = CPU_25KF;
1358 c->writecombine = _CACHE_UNCACHED;
1359 __cpu_name[cpu] = "MIPS 25Kc";
1360 break;
1361 case PRID_IMP_34K:
1362 c->cputype = CPU_34K;
1363 c->writecombine = _CACHE_UNCACHED;
1364 __cpu_name[cpu] = "MIPS 34Kc";
1365 cpu_set_mt_per_tc_perf(c);
1366 break;
1367 case PRID_IMP_74K:
1368 c->cputype = CPU_74K;
1369 c->writecombine = _CACHE_UNCACHED;
1370 __cpu_name[cpu] = "MIPS 74Kc";
1371 break;
1372 case PRID_IMP_M14KC:
1373 c->cputype = CPU_M14KC;
1374 c->writecombine = _CACHE_UNCACHED;
1375 __cpu_name[cpu] = "MIPS M14Kc";
1376 break;
1377 case PRID_IMP_M14KEC:
1378 c->cputype = CPU_M14KEC;
1379 c->writecombine = _CACHE_UNCACHED;
1380 __cpu_name[cpu] = "MIPS M14KEc";
1381 break;
1382 case PRID_IMP_1004K:
1383 c->cputype = CPU_1004K;
1384 c->writecombine = _CACHE_UNCACHED;
1385 __cpu_name[cpu] = "MIPS 1004Kc";
1386 cpu_set_mt_per_tc_perf(c);
1387 break;
1388 case PRID_IMP_1074K:
1389 c->cputype = CPU_1074K;
1390 c->writecombine = _CACHE_UNCACHED;
1391 __cpu_name[cpu] = "MIPS 1074Kc";
1392 break;
1393 case PRID_IMP_INTERAPTIV_UP:
1394 c->cputype = CPU_INTERAPTIV;
1395 __cpu_name[cpu] = "MIPS interAptiv";
1396 cpu_set_mt_per_tc_perf(c);
1397 break;
1398 case PRID_IMP_INTERAPTIV_MP:
1399 c->cputype = CPU_INTERAPTIV;
1400 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1401 cpu_set_mt_per_tc_perf(c);
1402 break;
1403 case PRID_IMP_PROAPTIV_UP:
1404 c->cputype = CPU_PROAPTIV;
1405 __cpu_name[cpu] = "MIPS proAptiv";
1406 break;
1407 case PRID_IMP_PROAPTIV_MP:
1408 c->cputype = CPU_PROAPTIV;
1409 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1410 break;
1411 case PRID_IMP_P5600:
1412 c->cputype = CPU_P5600;
1413 __cpu_name[cpu] = "MIPS P5600";
1414 break;
1415 case PRID_IMP_P6600:
1416 c->cputype = CPU_P6600;
1417 __cpu_name[cpu] = "MIPS P6600";
1418 break;
1419 case PRID_IMP_I6400:
1420 c->cputype = CPU_I6400;
1421 __cpu_name[cpu] = "MIPS I6400";
1422 break;
1423 case PRID_IMP_I6500:
1424 c->cputype = CPU_I6500;
1425 __cpu_name[cpu] = "MIPS I6500";
1426 break;
1427 case PRID_IMP_M5150:
1428 c->cputype = CPU_M5150;
1429 __cpu_name[cpu] = "MIPS M5150";
1430 break;
1431 case PRID_IMP_M6250:
1432 c->cputype = CPU_M6250;
1433 __cpu_name[cpu] = "MIPS M6250";
1434 break;
1435 }
1436
1437 decode_configs(c);
1438
1439 spram_config();
1440
1441 mm_config(c);
1442
1443 switch (__get_cpu_type(c->cputype)) {
1444 case CPU_M5150:
1445 case CPU_P5600:
1446 set_isa(c, MIPS_CPU_ISA_M32R5);
1447 break;
1448 case CPU_I6500:
1449 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES;
1450 fallthrough;
1451 case CPU_I6400:
1452 c->options |= MIPS_CPU_SHARED_FTLB_RAM;
1453 fallthrough;
1454 default:
1455 break;
1456 }
1457
1458 /* Recent MIPS cores use the implementation-dependent ExcCode 16 for
1459 * cache/FTLB parity exceptions.
1460 */
1461 switch (__get_cpu_type(c->cputype)) {
1462 case CPU_PROAPTIV:
1463 case CPU_P5600:
1464 case CPU_P6600:
1465 case CPU_I6400:
1466 case CPU_I6500:
1467 c->options |= MIPS_CPU_FTLBPAREX;
1468 break;
1469 }
1470}
1471
1472static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1473{
1474 decode_configs(c);
1475 switch (c->processor_id & PRID_IMP_MASK) {
1476 case PRID_IMP_AU1_REV1:
1477 case PRID_IMP_AU1_REV2:
1478 c->cputype = CPU_ALCHEMY;
1479 switch ((c->processor_id >> 24) & 0xff) {
1480 case 0:
1481 __cpu_name[cpu] = "Au1000";
1482 break;
1483 case 1:
1484 __cpu_name[cpu] = "Au1500";
1485 break;
1486 case 2:
1487 __cpu_name[cpu] = "Au1100";
1488 break;
1489 case 3:
1490 __cpu_name[cpu] = "Au1550";
1491 break;
1492 case 4:
1493 __cpu_name[cpu] = "Au1200";
1494 if ((c->processor_id & PRID_REV_MASK) == 2)
1495 __cpu_name[cpu] = "Au1250";
1496 break;
1497 case 5:
1498 __cpu_name[cpu] = "Au1210";
1499 break;
1500 default:
1501 __cpu_name[cpu] = "Au1xxx";
1502 break;
1503 }
1504 break;
1505 }
1506}
1507
1508static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1509{
1510 decode_configs(c);
1511
1512 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1513 switch (c->processor_id & PRID_IMP_MASK) {
1514 case PRID_IMP_SB1:
1515 c->cputype = CPU_SB1;
1516 __cpu_name[cpu] = "SiByte SB1";
1517 /* FPU in pass1 is known to have issues. */
1518 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1519 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1520 break;
1521 case PRID_IMP_SB1A:
1522 c->cputype = CPU_SB1A;
1523 __cpu_name[cpu] = "SiByte SB1A";
1524 break;
1525 }
1526}
1527
1528static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1529{
1530 decode_configs(c);
1531 switch (c->processor_id & PRID_IMP_MASK) {
1532 case PRID_IMP_SR71000:
1533 c->cputype = CPU_SR71000;
1534 __cpu_name[cpu] = "Sandcraft SR71000";
1535 c->scache.ways = 8;
1536 c->tlbsize = 64;
1537 break;
1538 }
1539}
1540
1541static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1542{
1543 decode_configs(c);
1544 switch (c->processor_id & PRID_IMP_MASK) {
1545 case PRID_IMP_PR4450:
1546 c->cputype = CPU_PR4450;
1547 __cpu_name[cpu] = "Philips PR4450";
1548 set_isa(c, MIPS_CPU_ISA_M32R1);
1549 break;
1550 }
1551}
1552
1553static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1554{
1555 decode_configs(c);
1556 switch (c->processor_id & PRID_IMP_MASK) {
1557 case PRID_IMP_BMIPS32_REV4:
1558 case PRID_IMP_BMIPS32_REV8:
1559 c->cputype = CPU_BMIPS32;
1560 __cpu_name[cpu] = "Broadcom BMIPS32";
1561 set_elf_platform(cpu, "bmips32");
1562 break;
1563 case PRID_IMP_BMIPS3300:
1564 case PRID_IMP_BMIPS3300_ALT:
1565 case PRID_IMP_BMIPS3300_BUG:
1566 c->cputype = CPU_BMIPS3300;
1567 __cpu_name[cpu] = "Broadcom BMIPS3300";
1568 set_elf_platform(cpu, "bmips3300");
1569 reserve_exception_space(0x400, VECTORSPACING * 64);
1570 break;
1571 case PRID_IMP_BMIPS43XX: {
1572 int rev = c->processor_id & PRID_REV_MASK;
1573
1574 if (rev >= PRID_REV_BMIPS4380_LO &&
1575 rev <= PRID_REV_BMIPS4380_HI) {
1576 c->cputype = CPU_BMIPS4380;
1577 __cpu_name[cpu] = "Broadcom BMIPS4380";
1578 set_elf_platform(cpu, "bmips4380");
1579 c->options |= MIPS_CPU_RIXI;
1580 reserve_exception_space(0x400, VECTORSPACING * 64);
1581 } else {
1582 c->cputype = CPU_BMIPS4350;
1583 __cpu_name[cpu] = "Broadcom BMIPS4350";
1584 set_elf_platform(cpu, "bmips4350");
1585 }
1586 break;
1587 }
1588 case PRID_IMP_BMIPS5000:
1589 case PRID_IMP_BMIPS5200:
1590 c->cputype = CPU_BMIPS5000;
1591 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1592 __cpu_name[cpu] = "Broadcom BMIPS5200";
1593 else
1594 __cpu_name[cpu] = "Broadcom BMIPS5000";
1595 set_elf_platform(cpu, "bmips5000");
1596 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
1597 reserve_exception_space(0x1000, VECTORSPACING * 64);
1598 break;
1599 }
1600}
1601
1602static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1603{
1604 decode_configs(c);
1605 switch (c->processor_id & PRID_IMP_MASK) {
1606 case PRID_IMP_CAVIUM_CN38XX:
1607 case PRID_IMP_CAVIUM_CN31XX:
1608 case PRID_IMP_CAVIUM_CN30XX:
1609 c->cputype = CPU_CAVIUM_OCTEON;
1610 __cpu_name[cpu] = "Cavium Octeon";
1611 goto platform;
1612 case PRID_IMP_CAVIUM_CN58XX:
1613 case PRID_IMP_CAVIUM_CN56XX:
1614 case PRID_IMP_CAVIUM_CN50XX:
1615 case PRID_IMP_CAVIUM_CN52XX:
1616 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1617 __cpu_name[cpu] = "Cavium Octeon+";
1618platform:
1619 set_elf_platform(cpu, "octeon");
1620 break;
1621 case PRID_IMP_CAVIUM_CN61XX:
1622 case PRID_IMP_CAVIUM_CN63XX:
1623 case PRID_IMP_CAVIUM_CN66XX:
1624 case PRID_IMP_CAVIUM_CN68XX:
1625 case PRID_IMP_CAVIUM_CNF71XX:
1626 c->cputype = CPU_CAVIUM_OCTEON2;
1627 __cpu_name[cpu] = "Cavium Octeon II";
1628 set_elf_platform(cpu, "octeon2");
1629 break;
1630 case PRID_IMP_CAVIUM_CN70XX:
1631 case PRID_IMP_CAVIUM_CN73XX:
1632 case PRID_IMP_CAVIUM_CNF75XX:
1633 case PRID_IMP_CAVIUM_CN78XX:
1634 c->cputype = CPU_CAVIUM_OCTEON3;
1635 __cpu_name[cpu] = "Cavium Octeon III";
1636 set_elf_platform(cpu, "octeon3");
1637 break;
1638 default:
1639 printk(KERN_INFO "Unknown Octeon chip!\n");
1640 c->cputype = CPU_UNKNOWN;
1641 break;
1642 }
1643}
1644
1645#ifdef CONFIG_CPU_LOONGSON64
1646#include <loongson_regs.h>
1647
1648static inline void decode_cpucfg(struct cpuinfo_mips *c)
1649{
1650 u32 cfg1 = read_cpucfg(LOONGSON_CFG1);
1651 u32 cfg2 = read_cpucfg(LOONGSON_CFG2);
1652 u32 cfg3 = read_cpucfg(LOONGSON_CFG3);
1653
1654 if (cfg1 & LOONGSON_CFG1_MMI)
1655 c->ases |= MIPS_ASE_LOONGSON_MMI;
1656
1657 if (cfg2 & LOONGSON_CFG2_LEXT1)
1658 c->ases |= MIPS_ASE_LOONGSON_EXT;
1659
1660 if (cfg2 & LOONGSON_CFG2_LEXT2)
1661 c->ases |= MIPS_ASE_LOONGSON_EXT2;
1662
1663 if (cfg2 & LOONGSON_CFG2_LSPW) {
1664 c->options |= MIPS_CPU_LDPTE;
1665 c->guest.options |= MIPS_CPU_LDPTE;
1666 }
1667
1668 if (cfg3 & LOONGSON_CFG3_LCAMP)
1669 c->ases |= MIPS_ASE_LOONGSON_CAM;
1670}
1671
1672static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1673{
1674 /* All Loongson processors covered here define ExcCode 16 as GSExc. */
1675 c->options |= MIPS_CPU_GSEXCEX;
1676
1677 switch (c->processor_id & PRID_IMP_MASK) {
1678 case PRID_IMP_LOONGSON_64R: /* Loongson-64 Reduced */
1679 switch (c->processor_id & PRID_REV_MASK) {
1680 case PRID_REV_LOONGSON2K_R1_0:
1681 case PRID_REV_LOONGSON2K_R1_1:
1682 case PRID_REV_LOONGSON2K_R1_2:
1683 case PRID_REV_LOONGSON2K_R1_3:
1684 c->cputype = CPU_LOONGSON64;
1685 __cpu_name[cpu] = "Loongson-2K";
1686 set_elf_platform(cpu, "gs264e");
1687 set_isa(c, MIPS_CPU_ISA_M64R2);
1688 break;
1689 }
1690 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_EXT |
1691 MIPS_ASE_LOONGSON_EXT2);
1692 break;
1693 case PRID_IMP_LOONGSON_64C: /* Loongson-3 Classic */
1694 switch (c->processor_id & PRID_REV_MASK) {
1695 case PRID_REV_LOONGSON3A_R2_0:
1696 case PRID_REV_LOONGSON3A_R2_1:
1697 c->cputype = CPU_LOONGSON64;
1698 __cpu_name[cpu] = "ICT Loongson-3";
1699 set_elf_platform(cpu, "loongson3a");
1700 set_isa(c, MIPS_CPU_ISA_M64R2);
1701 break;
1702 case PRID_REV_LOONGSON3A_R3_0:
1703 case PRID_REV_LOONGSON3A_R3_1:
1704 c->cputype = CPU_LOONGSON64;
1705 __cpu_name[cpu] = "ICT Loongson-3";
1706 set_elf_platform(cpu, "loongson3a");
1707 set_isa(c, MIPS_CPU_ISA_M64R2);
1708 break;
1709 }
1710 /*
1711 * Loongson-3 Classic did not implement MIPS standard TLBINV
1712 * but implemented TLBINVF and EHINV. As currently we're only
1713 * using these two features, enable MIPS_CPU_TLBINV as well.
1714 *
1715 * Also some early Loongson-3A2000 had wrong TLB type in Config
1716 * register, we correct it here.
1717 */
1718 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
1719 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1720 MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
1721 c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */
1722 break;
1723 case PRID_IMP_LOONGSON_64G:
1724 c->cputype = CPU_LOONGSON64;
1725 __cpu_name[cpu] = "ICT Loongson-3";
1726 set_elf_platform(cpu, "loongson3a");
1727 set_isa(c, MIPS_CPU_ISA_M64R2);
1728 decode_cpucfg(c);
1729 break;
1730 default:
1731 panic("Unknown Loongson Processor ID!");
1732 break;
1733 }
1734
1735 decode_configs(c);
1736}
1737#else
1738static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { }
1739#endif
1740
1741static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1742{
1743 decode_configs(c);
1744
1745 /*
1746 * XBurst misses a config2 register, so config3 decode was skipped in
1747 * decode_configs().
1748 */
1749 decode_config3(c);
1750
1751 /* XBurst does not implement the CP0 counter. */
1752 c->options &= ~MIPS_CPU_COUNTER;
1753 BUG_ON(__builtin_constant_p(cpu_has_counter) && cpu_has_counter);
1754
1755 /* XBurst has virtually tagged icache */
1756 c->icache.flags |= MIPS_CACHE_VTAG;
1757
1758 switch (c->processor_id & PRID_IMP_MASK) {
1759
1760 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
1761 case PRID_IMP_XBURST_REV1:
1762
1763 /*
1764 * The XBurst core by default attempts to avoid branch target
1765 * buffer lookups by detecting & special casing loops. This
1766 * feature will cause BogoMIPS and lpj calculate in error.
1767 * Set cp0 config7 bit 4 to disable this feature.
1768 */
1769 set_c0_config7(MIPS_CONF7_BTB_LOOP_EN);
1770
1771 switch (c->processor_id & PRID_COMP_MASK) {
1772
1773 /*
1774 * The config0 register in the XBurst CPUs with a processor ID of
1775 * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
1776 * but they don't actually support this ISA.
1777 */
1778 case PRID_COMP_INGENIC_D0:
1779 c->isa_level &= ~MIPS_CPU_ISA_M32R2;
1780
1781 /* FPU is not properly detected on JZ4760(B). */
1782 if (c->processor_id == 0x2ed0024f)
1783 c->options |= MIPS_CPU_FPU;
1784
1785 fallthrough;
1786
1787 /*
1788 * The config0 register in the XBurst CPUs with a processor ID of
1789 * PRID_COMP_INGENIC_D0 or PRID_COMP_INGENIC_D1 has an abandoned
1790 * huge page tlb mode, this mode is not compatible with the MIPS
1791 * standard, it will cause tlbmiss and into an infinite loop
1792 * (line 21 in the tlb-funcs.S) when starting the init process.
1793 * After chip reset, the default is HPTLB mode, Write 0xa9000000
1794 * to cp0 register 5 sel 4 to switch back to VTLB mode to prevent
1795 * getting stuck.
1796 */
1797 case PRID_COMP_INGENIC_D1:
1798 write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS);
1799 break;
1800
1801 default:
1802 break;
1803 }
1804 fallthrough;
1805
1806 /* XBurst®1 with MXU2.0 SIMD ISA */
1807 case PRID_IMP_XBURST_REV2:
1808 /* Ingenic uses the WA bit to achieve write-combine memory writes */
1809 c->writecombine = _CACHE_CACHABLE_WA;
1810 c->cputype = CPU_XBURST;
1811 __cpu_name[cpu] = "Ingenic XBurst";
1812 break;
1813
1814 /* XBurst®2 with MXU2.1 SIMD ISA */
1815 case PRID_IMP_XBURST2:
1816 c->cputype = CPU_XBURST;
1817 __cpu_name[cpu] = "Ingenic XBurst II";
1818 break;
1819
1820 default:
1821 panic("Unknown Ingenic Processor ID!");
1822 break;
1823 }
1824}
1825
1826#ifdef CONFIG_64BIT
1827/* For use by uaccess.h */
1828u64 __ua_limit;
1829EXPORT_SYMBOL(__ua_limit);
1830#endif
1831
1832const char *__cpu_name[NR_CPUS];
1833const char *__elf_platform;
1834const char *__elf_base_platform;
1835
1836void cpu_probe(void)
1837{
1838 struct cpuinfo_mips *c = ¤t_cpu_data;
1839 unsigned int cpu = smp_processor_id();
1840
1841 /*
1842 * Set a default elf platform, cpu probe may later
1843 * overwrite it with a more precise value
1844 */
1845 set_elf_platform(cpu, "mips");
1846
1847 c->processor_id = PRID_IMP_UNKNOWN;
1848 c->fpu_id = FPIR_IMP_NONE;
1849 c->cputype = CPU_UNKNOWN;
1850 c->writecombine = _CACHE_UNCACHED;
1851
1852 c->fpu_csr31 = FPU_CSR_RN;
1853 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1854
1855 c->processor_id = read_c0_prid();
1856 switch (c->processor_id & PRID_COMP_MASK) {
1857 case PRID_COMP_LEGACY:
1858 cpu_probe_legacy(c, cpu);
1859 break;
1860 case PRID_COMP_MIPS:
1861 cpu_probe_mips(c, cpu);
1862 break;
1863 case PRID_COMP_ALCHEMY:
1864 cpu_probe_alchemy(c, cpu);
1865 break;
1866 case PRID_COMP_SIBYTE:
1867 cpu_probe_sibyte(c, cpu);
1868 break;
1869 case PRID_COMP_BROADCOM:
1870 cpu_probe_broadcom(c, cpu);
1871 break;
1872 case PRID_COMP_SANDCRAFT:
1873 cpu_probe_sandcraft(c, cpu);
1874 break;
1875 case PRID_COMP_NXP:
1876 cpu_probe_nxp(c, cpu);
1877 break;
1878 case PRID_COMP_CAVIUM:
1879 cpu_probe_cavium(c, cpu);
1880 break;
1881 case PRID_COMP_LOONGSON:
1882 cpu_probe_loongson(c, cpu);
1883 break;
1884 case PRID_COMP_INGENIC_13:
1885 case PRID_COMP_INGENIC_D0:
1886 case PRID_COMP_INGENIC_D1:
1887 case PRID_COMP_INGENIC_E1:
1888 cpu_probe_ingenic(c, cpu);
1889 break;
1890 }
1891
1892 BUG_ON(!__cpu_name[cpu]);
1893 BUG_ON(c->cputype == CPU_UNKNOWN);
1894
1895 /*
1896 * Platform code can force the cpu type to optimize code
1897 * generation. In that case be sure the cpu type is correctly
1898 * manually setup otherwise it could trigger some nasty bugs.
1899 */
1900 BUG_ON(current_cpu_type() != c->cputype);
1901
1902 if (cpu_has_rixi) {
1903 /* Enable the RIXI exceptions */
1904 set_c0_pagegrain(PG_IEC);
1905 back_to_back_c0_hazard();
1906 /* Verify the IEC bit is set */
1907 if (read_c0_pagegrain() & PG_IEC)
1908 c->options |= MIPS_CPU_RIXIEX;
1909 }
1910
1911 if (mips_fpu_disabled)
1912 c->options &= ~MIPS_CPU_FPU;
1913
1914 if (mips_dsp_disabled)
1915 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1916
1917 if (mips_htw_disabled) {
1918 c->options &= ~MIPS_CPU_HTW;
1919 write_c0_pwctl(read_c0_pwctl() &
1920 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1921 }
1922
1923 if (c->options & MIPS_CPU_FPU)
1924 cpu_set_fpu_opts(c);
1925 else
1926 cpu_set_nofpu_opts(c);
1927
1928 if (cpu_has_mips_r2_r6) {
1929 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1930 /* R2 has Performance Counter Interrupt indicator */
1931 c->options |= MIPS_CPU_PCI;
1932 }
1933 else
1934 c->srsets = 1;
1935
1936 if (cpu_has_mips_r6)
1937 elf_hwcap |= HWCAP_MIPS_R6;
1938
1939 if (cpu_has_msa) {
1940 c->msa_id = cpu_get_msa_id();
1941 WARN(c->msa_id & MSA_IR_WRPF,
1942 "Vector register partitioning unimplemented!");
1943 elf_hwcap |= HWCAP_MIPS_MSA;
1944 }
1945
1946 if (cpu_has_mips16)
1947 elf_hwcap |= HWCAP_MIPS_MIPS16;
1948
1949 if (cpu_has_mdmx)
1950 elf_hwcap |= HWCAP_MIPS_MDMX;
1951
1952 if (cpu_has_mips3d)
1953 elf_hwcap |= HWCAP_MIPS_MIPS3D;
1954
1955 if (cpu_has_smartmips)
1956 elf_hwcap |= HWCAP_MIPS_SMARTMIPS;
1957
1958 if (cpu_has_dsp)
1959 elf_hwcap |= HWCAP_MIPS_DSP;
1960
1961 if (cpu_has_dsp2)
1962 elf_hwcap |= HWCAP_MIPS_DSP2;
1963
1964 if (cpu_has_dsp3)
1965 elf_hwcap |= HWCAP_MIPS_DSP3;
1966
1967 if (cpu_has_mips16e2)
1968 elf_hwcap |= HWCAP_MIPS_MIPS16E2;
1969
1970 if (cpu_has_loongson_mmi)
1971 elf_hwcap |= HWCAP_LOONGSON_MMI;
1972
1973 if (cpu_has_loongson_ext)
1974 elf_hwcap |= HWCAP_LOONGSON_EXT;
1975
1976 if (cpu_has_loongson_ext2)
1977 elf_hwcap |= HWCAP_LOONGSON_EXT2;
1978
1979 if (cpu_has_vz)
1980 cpu_probe_vz(c);
1981
1982 cpu_probe_vmbits(c);
1983
1984 /* Synthesize CPUCFG data if running on Loongson processors;
1985 * no-op otherwise.
1986 *
1987 * This looks at previously probed features, so keep this at bottom.
1988 */
1989 loongson3_cpucfg_synthesize_data(c);
1990
1991#ifdef CONFIG_64BIT
1992 if (cpu == 0)
1993 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1994#endif
1995
1996 reserve_exception_space(0, 0x1000);
1997}
1998
1999void cpu_report(void)
2000{
2001 struct cpuinfo_mips *c = ¤t_cpu_data;
2002
2003 pr_info("CPU%d revision is: %08x (%s)\n",
2004 smp_processor_id(), c->processor_id, cpu_name_string());
2005 if (c->options & MIPS_CPU_FPU)
2006 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
2007 if (cpu_has_msa)
2008 pr_info("MSA revision is: %08x\n", c->msa_id);
2009}
2010
2011void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster)
2012{
2013 /* Ensure the core number fits in the field */
2014 WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >>
2015 MIPS_GLOBALNUMBER_CLUSTER_SHF));
2016
2017 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER;
2018 cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF;
2019}
2020
2021void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core)
2022{
2023 /* Ensure the core number fits in the field */
2024 WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF));
2025
2026 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE;
2027 cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF;
2028}
2029
2030void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe)
2031{
2032 /* Ensure the VP(E) ID fits in the field */
2033 WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF));
2034
2035 /* Ensure we're not using VP(E)s without support */
2036 WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) &&
2037 !IS_ENABLED(CONFIG_CPU_MIPSR6));
2038
2039 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP;
2040 cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF;
2041}
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Processor capabilities determination functions.
4 *
5 * Copyright (C) xxxx the Anonymous
6 * Copyright (C) 1994 - 2006 Ralf Baechle
7 * Copyright (C) 2003, 2004 Maciej W. Rozycki
8 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 */
10#include <linux/init.h>
11#include <linux/kernel.h>
12#include <linux/ptrace.h>
13#include <linux/smp.h>
14#include <linux/stddef.h>
15#include <linux/export.h>
16
17#include <asm/bugs.h>
18#include <asm/cpu.h>
19#include <asm/cpu-features.h>
20#include <asm/cpu-type.h>
21#include <asm/fpu.h>
22#include <asm/mipsregs.h>
23#include <asm/mipsmtregs.h>
24#include <asm/msa.h>
25#include <asm/watch.h>
26#include <asm/elf.h>
27#include <asm/pgtable-bits.h>
28#include <asm/spram.h>
29#include <asm/traps.h>
30#include <linux/uaccess.h>
31
32#include "fpu-probe.h"
33
34#include <asm/mach-loongson64/cpucfg-emul.h>
35
36/* Hardware capabilities */
37unsigned int elf_hwcap __read_mostly;
38EXPORT_SYMBOL_GPL(elf_hwcap);
39
40static inline unsigned long cpu_get_msa_id(void)
41{
42 unsigned long status, msa_id;
43
44 status = read_c0_status();
45 __enable_fpu(FPU_64BIT);
46 enable_msa();
47 msa_id = read_msa_ir();
48 disable_msa();
49 write_c0_status(status);
50 return msa_id;
51}
52
53static int mips_dsp_disabled;
54
55static int __init dsp_disable(char *s)
56{
57 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
58 mips_dsp_disabled = 1;
59
60 return 1;
61}
62
63__setup("nodsp", dsp_disable);
64
65static int mips_htw_disabled;
66
67static int __init htw_disable(char *s)
68{
69 mips_htw_disabled = 1;
70 cpu_data[0].options &= ~MIPS_CPU_HTW;
71 write_c0_pwctl(read_c0_pwctl() &
72 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
73
74 return 1;
75}
76
77__setup("nohtw", htw_disable);
78
79static int mips_ftlb_disabled;
80static int mips_has_ftlb_configured;
81
82enum ftlb_flags {
83 FTLB_EN = 1 << 0,
84 FTLB_SET_PROB = 1 << 1,
85};
86
87static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
88
89static int __init ftlb_disable(char *s)
90{
91 unsigned int config4, mmuextdef;
92
93 /*
94 * If the core hasn't done any FTLB configuration, there is nothing
95 * for us to do here.
96 */
97 if (!mips_has_ftlb_configured)
98 return 1;
99
100 /* Disable it in the boot cpu */
101 if (set_ftlb_enable(&cpu_data[0], 0)) {
102 pr_warn("Can't turn FTLB off\n");
103 return 1;
104 }
105
106 config4 = read_c0_config4();
107
108 /* Check that FTLB has been disabled */
109 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
110 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
111 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
112 /* This should never happen */
113 pr_warn("FTLB could not be disabled!\n");
114 return 1;
115 }
116
117 mips_ftlb_disabled = 1;
118 mips_has_ftlb_configured = 0;
119
120 /*
121 * noftlb is mainly used for debug purposes so print
122 * an informative message instead of using pr_debug()
123 */
124 pr_info("FTLB has been disabled\n");
125
126 /*
127 * Some of these bits are duplicated in the decode_config4.
128 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
129 * once FTLB has been disabled so undo what decode_config4 did.
130 */
131 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
132 cpu_data[0].tlbsizeftlbsets;
133 cpu_data[0].tlbsizeftlbsets = 0;
134 cpu_data[0].tlbsizeftlbways = 0;
135
136 return 1;
137}
138
139__setup("noftlb", ftlb_disable);
140
141/*
142 * Check if the CPU has per tc perf counters
143 */
144static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c)
145{
146 if (read_c0_config7() & MTI_CONF7_PTC)
147 c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS;
148}
149
150static inline void check_errata(void)
151{
152 struct cpuinfo_mips *c = ¤t_cpu_data;
153
154 switch (current_cpu_type()) {
155 case CPU_34K:
156 /*
157 * Erratum "RPS May Cause Incorrect Instruction Execution"
158 * This code only handles VPE0, any SMP/RTOS code
159 * making use of VPE1 will be responsible for that VPE.
160 */
161 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
162 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
163 break;
164 default:
165 break;
166 }
167}
168
169void __init check_bugs32(void)
170{
171 check_errata();
172}
173
174/*
175 * Probe whether cpu has config register by trying to play with
176 * alternate cache bit and see whether it matters.
177 * It's used by cpu_probe to distinguish between R3000A and R3081.
178 */
179static inline int cpu_has_confreg(void)
180{
181#ifdef CONFIG_CPU_R3000
182 unsigned long size1, size2;
183 unsigned long cfg = read_c0_conf();
184
185 size1 = r3k_cache_size(ST0_ISC);
186 write_c0_conf(cfg ^ R30XX_CONF_AC);
187 size2 = r3k_cache_size(ST0_ISC);
188 write_c0_conf(cfg);
189 return size1 != size2;
190#else
191 return 0;
192#endif
193}
194
195static inline void set_elf_platform(int cpu, const char *plat)
196{
197 if (cpu == 0)
198 __elf_platform = plat;
199}
200
201static inline void set_elf_base_platform(const char *plat)
202{
203 if (__elf_base_platform == NULL) {
204 __elf_base_platform = plat;
205 }
206}
207
208static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
209{
210#ifdef __NEED_VMBITS_PROBE
211 write_c0_entryhi(0x3fffffffffffe000ULL);
212 back_to_back_c0_hazard();
213 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
214#endif
215}
216
217static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
218{
219 switch (isa) {
220 case MIPS_CPU_ISA_M64R5:
221 c->isa_level |= MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5;
222 set_elf_base_platform("mips64r5");
223 fallthrough;
224 case MIPS_CPU_ISA_M64R2:
225 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
226 set_elf_base_platform("mips64r2");
227 fallthrough;
228 case MIPS_CPU_ISA_M64R1:
229 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
230 set_elf_base_platform("mips64");
231 fallthrough;
232 case MIPS_CPU_ISA_V:
233 c->isa_level |= MIPS_CPU_ISA_V;
234 set_elf_base_platform("mips5");
235 fallthrough;
236 case MIPS_CPU_ISA_IV:
237 c->isa_level |= MIPS_CPU_ISA_IV;
238 set_elf_base_platform("mips4");
239 fallthrough;
240 case MIPS_CPU_ISA_III:
241 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
242 set_elf_base_platform("mips3");
243 break;
244
245 /* R6 incompatible with everything else */
246 case MIPS_CPU_ISA_M64R6:
247 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
248 set_elf_base_platform("mips64r6");
249 fallthrough;
250 case MIPS_CPU_ISA_M32R6:
251 c->isa_level |= MIPS_CPU_ISA_M32R6;
252 set_elf_base_platform("mips32r6");
253 /* Break here so we don't add incompatible ISAs */
254 break;
255 case MIPS_CPU_ISA_M32R5:
256 c->isa_level |= MIPS_CPU_ISA_M32R5;
257 set_elf_base_platform("mips32r5");
258 fallthrough;
259 case MIPS_CPU_ISA_M32R2:
260 c->isa_level |= MIPS_CPU_ISA_M32R2;
261 set_elf_base_platform("mips32r2");
262 fallthrough;
263 case MIPS_CPU_ISA_M32R1:
264 c->isa_level |= MIPS_CPU_ISA_M32R1;
265 set_elf_base_platform("mips32");
266 fallthrough;
267 case MIPS_CPU_ISA_II:
268 c->isa_level |= MIPS_CPU_ISA_II;
269 set_elf_base_platform("mips2");
270 break;
271 }
272}
273
274static char unknown_isa[] = KERN_ERR \
275 "Unsupported ISA type, c0.config0: %d.";
276
277static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
278{
279
280 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
281
282 /*
283 * 0 = All TLBWR instructions go to FTLB
284 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
285 * FTLB and 1 goes to the VTLB.
286 * 2 = 7:1: As above with 7:1 ratio.
287 * 3 = 3:1: As above with 3:1 ratio.
288 *
289 * Use the linear midpoint as the probability threshold.
290 */
291 if (probability >= 12)
292 return 1;
293 else if (probability >= 6)
294 return 2;
295 else
296 /*
297 * So FTLB is less than 4 times bigger than VTLB.
298 * A 3:1 ratio can still be useful though.
299 */
300 return 3;
301}
302
303static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
304{
305 unsigned int config;
306
307 /* It's implementation dependent how the FTLB can be enabled */
308 switch (c->cputype) {
309 case CPU_PROAPTIV:
310 case CPU_P5600:
311 case CPU_P6600:
312 /* proAptiv & related cores use Config6 to enable the FTLB */
313 config = read_c0_config6();
314
315 if (flags & FTLB_EN)
316 config |= MTI_CONF6_FTLBEN;
317 else
318 config &= ~MTI_CONF6_FTLBEN;
319
320 if (flags & FTLB_SET_PROB) {
321 config &= ~(3 << MTI_CONF6_FTLBP_SHIFT);
322 config |= calculate_ftlb_probability(c)
323 << MTI_CONF6_FTLBP_SHIFT;
324 }
325
326 write_c0_config6(config);
327 back_to_back_c0_hazard();
328 break;
329 case CPU_I6400:
330 case CPU_I6500:
331 /* There's no way to disable the FTLB */
332 if (!(flags & FTLB_EN))
333 return 1;
334 return 0;
335 case CPU_LOONGSON64:
336 /* Flush ITLB, DTLB, VTLB and FTLB */
337 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
338 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
339 /* Loongson-3 cores use Config6 to enable the FTLB */
340 config = read_c0_config6();
341 if (flags & FTLB_EN)
342 /* Enable FTLB */
343 write_c0_config6(config & ~LOONGSON_CONF6_FTLBDIS);
344 else
345 /* Disable FTLB */
346 write_c0_config6(config | LOONGSON_CONF6_FTLBDIS);
347 break;
348 default:
349 return 1;
350 }
351
352 return 0;
353}
354
355static int mm_config(struct cpuinfo_mips *c)
356{
357 unsigned int config0, update, mm;
358
359 config0 = read_c0_config();
360 mm = config0 & MIPS_CONF_MM;
361
362 /*
363 * It's implementation dependent what type of write-merge is supported
364 * and whether it can be enabled/disabled. If it is settable lets make
365 * the merging allowed by default. Some platforms might have
366 * write-through caching unsupported. In this case just ignore the
367 * CP0.Config.MM bit field value.
368 */
369 switch (c->cputype) {
370 case CPU_24K:
371 case CPU_34K:
372 case CPU_74K:
373 case CPU_P5600:
374 case CPU_P6600:
375 c->options |= MIPS_CPU_MM_FULL;
376 update = MIPS_CONF_MM_FULL;
377 break;
378 case CPU_1004K:
379 case CPU_1074K:
380 case CPU_INTERAPTIV:
381 case CPU_PROAPTIV:
382 mm = 0;
383 fallthrough;
384 default:
385 update = 0;
386 break;
387 }
388
389 if (update) {
390 config0 = (config0 & ~MIPS_CONF_MM) | update;
391 write_c0_config(config0);
392 } else if (mm == MIPS_CONF_MM_SYSAD) {
393 c->options |= MIPS_CPU_MM_SYSAD;
394 } else if (mm == MIPS_CONF_MM_FULL) {
395 c->options |= MIPS_CPU_MM_FULL;
396 }
397
398 return 0;
399}
400
401static inline unsigned int decode_config0(struct cpuinfo_mips *c)
402{
403 unsigned int config0;
404 int isa, mt;
405
406 config0 = read_c0_config();
407
408 /*
409 * Look for Standard TLB or Dual VTLB and FTLB
410 */
411 mt = config0 & MIPS_CONF_MT;
412 if (mt == MIPS_CONF_MT_TLB)
413 c->options |= MIPS_CPU_TLB;
414 else if (mt == MIPS_CONF_MT_FTLB)
415 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
416
417 isa = (config0 & MIPS_CONF_AT) >> 13;
418 switch (isa) {
419 case 0:
420 switch ((config0 & MIPS_CONF_AR) >> 10) {
421 case 0:
422 set_isa(c, MIPS_CPU_ISA_M32R1);
423 break;
424 case 1:
425 set_isa(c, MIPS_CPU_ISA_M32R2);
426 break;
427 case 2:
428 set_isa(c, MIPS_CPU_ISA_M32R6);
429 break;
430 default:
431 goto unknown;
432 }
433 break;
434 case 2:
435 switch ((config0 & MIPS_CONF_AR) >> 10) {
436 case 0:
437 set_isa(c, MIPS_CPU_ISA_M64R1);
438 break;
439 case 1:
440 set_isa(c, MIPS_CPU_ISA_M64R2);
441 break;
442 case 2:
443 set_isa(c, MIPS_CPU_ISA_M64R6);
444 break;
445 default:
446 goto unknown;
447 }
448 break;
449 default:
450 goto unknown;
451 }
452
453 return config0 & MIPS_CONF_M;
454
455unknown:
456 panic(unknown_isa, config0);
457}
458
459static inline unsigned int decode_config1(struct cpuinfo_mips *c)
460{
461 unsigned int config1;
462
463 config1 = read_c0_config1();
464
465 if (config1 & MIPS_CONF1_MD)
466 c->ases |= MIPS_ASE_MDMX;
467 if (config1 & MIPS_CONF1_PC)
468 c->options |= MIPS_CPU_PERF;
469 if (config1 & MIPS_CONF1_WR)
470 c->options |= MIPS_CPU_WATCH;
471 if (config1 & MIPS_CONF1_CA)
472 c->ases |= MIPS_ASE_MIPS16;
473 if (config1 & MIPS_CONF1_EP)
474 c->options |= MIPS_CPU_EJTAG;
475 if (config1 & MIPS_CONF1_FP) {
476 c->options |= MIPS_CPU_FPU;
477 c->options |= MIPS_CPU_32FPR;
478 }
479 if (cpu_has_tlb) {
480 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
481 c->tlbsizevtlb = c->tlbsize;
482 c->tlbsizeftlbsets = 0;
483 }
484
485 return config1 & MIPS_CONF_M;
486}
487
488static inline unsigned int decode_config2(struct cpuinfo_mips *c)
489{
490 unsigned int config2;
491
492 config2 = read_c0_config2();
493
494 if (config2 & MIPS_CONF2_SL)
495 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
496
497 return config2 & MIPS_CONF_M;
498}
499
500static inline unsigned int decode_config3(struct cpuinfo_mips *c)
501{
502 unsigned int config3;
503
504 config3 = read_c0_config3();
505
506 if (config3 & MIPS_CONF3_SM) {
507 c->ases |= MIPS_ASE_SMARTMIPS;
508 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
509 }
510 if (config3 & MIPS_CONF3_RXI)
511 c->options |= MIPS_CPU_RIXI;
512 if (config3 & MIPS_CONF3_CTXTC)
513 c->options |= MIPS_CPU_CTXTC;
514 if (config3 & MIPS_CONF3_DSP)
515 c->ases |= MIPS_ASE_DSP;
516 if (config3 & MIPS_CONF3_DSP2P) {
517 c->ases |= MIPS_ASE_DSP2P;
518 if (cpu_has_mips_r6)
519 c->ases |= MIPS_ASE_DSP3;
520 }
521 if (config3 & MIPS_CONF3_VINT)
522 c->options |= MIPS_CPU_VINT;
523 if (config3 & MIPS_CONF3_VEIC)
524 c->options |= MIPS_CPU_VEIC;
525 if (config3 & MIPS_CONF3_LPA)
526 c->options |= MIPS_CPU_LPA;
527 if (config3 & MIPS_CONF3_MT)
528 c->ases |= MIPS_ASE_MIPSMT;
529 if (config3 & MIPS_CONF3_ULRI)
530 c->options |= MIPS_CPU_ULRI;
531 if (config3 & MIPS_CONF3_ISA)
532 c->options |= MIPS_CPU_MICROMIPS;
533 if (config3 & MIPS_CONF3_VZ)
534 c->ases |= MIPS_ASE_VZ;
535 if (config3 & MIPS_CONF3_SC)
536 c->options |= MIPS_CPU_SEGMENTS;
537 if (config3 & MIPS_CONF3_BI)
538 c->options |= MIPS_CPU_BADINSTR;
539 if (config3 & MIPS_CONF3_BP)
540 c->options |= MIPS_CPU_BADINSTRP;
541 if (config3 & MIPS_CONF3_MSA)
542 c->ases |= MIPS_ASE_MSA;
543 if (config3 & MIPS_CONF3_PW) {
544 c->htw_seq = 0;
545 c->options |= MIPS_CPU_HTW;
546 }
547 if (config3 & MIPS_CONF3_CDMM)
548 c->options |= MIPS_CPU_CDMM;
549 if (config3 & MIPS_CONF3_SP)
550 c->options |= MIPS_CPU_SP;
551
552 return config3 & MIPS_CONF_M;
553}
554
555static inline unsigned int decode_config4(struct cpuinfo_mips *c)
556{
557 unsigned int config4;
558 unsigned int newcf4;
559 unsigned int mmuextdef;
560 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
561 unsigned long asid_mask;
562
563 config4 = read_c0_config4();
564
565 if (cpu_has_tlb) {
566 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
567 c->options |= MIPS_CPU_TLBINV;
568
569 /*
570 * R6 has dropped the MMUExtDef field from config4.
571 * On R6 the fields always describe the FTLB, and only if it is
572 * present according to Config.MT.
573 */
574 if (!cpu_has_mips_r6)
575 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
576 else if (cpu_has_ftlb)
577 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
578 else
579 mmuextdef = 0;
580
581 switch (mmuextdef) {
582 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
583 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
584 c->tlbsizevtlb = c->tlbsize;
585 break;
586 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
587 c->tlbsizevtlb +=
588 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
589 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
590 c->tlbsize = c->tlbsizevtlb;
591 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
592 fallthrough;
593 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
594 if (mips_ftlb_disabled)
595 break;
596 newcf4 = (config4 & ~ftlb_page) |
597 (page_size_ftlb(mmuextdef) <<
598 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
599 write_c0_config4(newcf4);
600 back_to_back_c0_hazard();
601 config4 = read_c0_config4();
602 if (config4 != newcf4) {
603 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
604 PAGE_SIZE, config4);
605 /* Switch FTLB off */
606 set_ftlb_enable(c, 0);
607 mips_ftlb_disabled = 1;
608 break;
609 }
610 c->tlbsizeftlbsets = 1 <<
611 ((config4 & MIPS_CONF4_FTLBSETS) >>
612 MIPS_CONF4_FTLBSETS_SHIFT);
613 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
614 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
615 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
616 mips_has_ftlb_configured = 1;
617 break;
618 }
619 }
620
621 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
622 >> MIPS_CONF4_KSCREXIST_SHIFT;
623
624 asid_mask = MIPS_ENTRYHI_ASID;
625 if (config4 & MIPS_CONF4_AE)
626 asid_mask |= MIPS_ENTRYHI_ASIDX;
627 set_cpu_asid_mask(c, asid_mask);
628
629 /*
630 * Warn if the computed ASID mask doesn't match the mask the kernel
631 * is built for. This may indicate either a serious problem or an
632 * easy optimisation opportunity, but either way should be addressed.
633 */
634 WARN_ON(asid_mask != cpu_asid_mask(c));
635
636 return config4 & MIPS_CONF_M;
637}
638
639static inline unsigned int decode_config5(struct cpuinfo_mips *c)
640{
641 unsigned int config5, max_mmid_width;
642 unsigned long asid_mask;
643
644 config5 = read_c0_config5();
645 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
646
647 if (cpu_has_mips_r6) {
648 if (!__builtin_constant_p(cpu_has_mmid) || cpu_has_mmid)
649 config5 |= MIPS_CONF5_MI;
650 else
651 config5 &= ~MIPS_CONF5_MI;
652 }
653
654 write_c0_config5(config5);
655
656 if (config5 & MIPS_CONF5_EVA)
657 c->options |= MIPS_CPU_EVA;
658 if (config5 & MIPS_CONF5_MRP)
659 c->options |= MIPS_CPU_MAAR;
660 if (config5 & MIPS_CONF5_LLB)
661 c->options |= MIPS_CPU_RW_LLB;
662 if (config5 & MIPS_CONF5_MVH)
663 c->options |= MIPS_CPU_MVH;
664 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
665 c->options |= MIPS_CPU_VP;
666 if (config5 & MIPS_CONF5_CA2)
667 c->ases |= MIPS_ASE_MIPS16E2;
668
669 if (config5 & MIPS_CONF5_CRCP)
670 elf_hwcap |= HWCAP_MIPS_CRC32;
671
672 if (cpu_has_mips_r6) {
673 /* Ensure the write to config5 above takes effect */
674 back_to_back_c0_hazard();
675
676 /* Check whether we successfully enabled MMID support */
677 config5 = read_c0_config5();
678 if (config5 & MIPS_CONF5_MI)
679 c->options |= MIPS_CPU_MMID;
680
681 /*
682 * Warn if we've hardcoded cpu_has_mmid to a value unsuitable
683 * for the CPU we're running on, or if CPUs in an SMP system
684 * have inconsistent MMID support.
685 */
686 WARN_ON(!!cpu_has_mmid != !!(config5 & MIPS_CONF5_MI));
687
688 if (cpu_has_mmid) {
689 write_c0_memorymapid(~0ul);
690 back_to_back_c0_hazard();
691 asid_mask = read_c0_memorymapid();
692
693 /*
694 * We maintain a bitmap to track MMID allocation, and
695 * need a sensible upper bound on the size of that
696 * bitmap. The initial CPU with MMID support (I6500)
697 * supports 16 bit MMIDs, which gives us an 8KiB
698 * bitmap. The architecture recommends that hardware
699 * support 32 bit MMIDs, which would give us a 512MiB
700 * bitmap - that's too big in most cases.
701 *
702 * Cap MMID width at 16 bits for now & we can revisit
703 * this if & when hardware supports anything wider.
704 */
705 max_mmid_width = 16;
706 if (asid_mask > GENMASK(max_mmid_width - 1, 0)) {
707 pr_info("Capping MMID width at %d bits",
708 max_mmid_width);
709 asid_mask = GENMASK(max_mmid_width - 1, 0);
710 }
711
712 set_cpu_asid_mask(c, asid_mask);
713 }
714 }
715
716 return config5 & MIPS_CONF_M;
717}
718
719static void decode_configs(struct cpuinfo_mips *c)
720{
721 int ok;
722
723 /* MIPS32 or MIPS64 compliant CPU. */
724 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
725 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
726
727 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
728
729 /* Enable FTLB if present and not disabled */
730 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
731
732 ok = decode_config0(c); /* Read Config registers. */
733 BUG_ON(!ok); /* Arch spec violation! */
734 if (ok)
735 ok = decode_config1(c);
736 if (ok)
737 ok = decode_config2(c);
738 if (ok)
739 ok = decode_config3(c);
740 if (ok)
741 ok = decode_config4(c);
742 if (ok)
743 ok = decode_config5(c);
744
745 /* Probe the EBase.WG bit */
746 if (cpu_has_mips_r2_r6) {
747 u64 ebase;
748 unsigned int status;
749
750 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
751 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
752 : (s32)read_c0_ebase();
753 if (ebase & MIPS_EBASE_WG) {
754 /* WG bit already set, we can avoid the clumsy probe */
755 c->options |= MIPS_CPU_EBASE_WG;
756 } else {
757 /* Its UNDEFINED to change EBase while BEV=0 */
758 status = read_c0_status();
759 write_c0_status(status | ST0_BEV);
760 irq_enable_hazard();
761 /*
762 * On pre-r6 cores, this may well clobber the upper bits
763 * of EBase. This is hard to avoid without potentially
764 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
765 */
766 if (cpu_has_mips64r6)
767 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
768 else
769 write_c0_ebase(ebase | MIPS_EBASE_WG);
770 back_to_back_c0_hazard();
771 /* Restore BEV */
772 write_c0_status(status);
773 if (read_c0_ebase() & MIPS_EBASE_WG) {
774 c->options |= MIPS_CPU_EBASE_WG;
775 write_c0_ebase(ebase);
776 }
777 }
778 }
779
780 /* configure the FTLB write probability */
781 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
782
783 mips_probe_watch_registers(c);
784
785#ifndef CONFIG_MIPS_CPS
786 if (cpu_has_mips_r2_r6) {
787 unsigned int core;
788
789 core = get_ebase_cpunum();
790 if (cpu_has_mipsmt)
791 core >>= fls(core_nvpes()) - 1;
792 cpu_set_core(c, core);
793 }
794#endif
795}
796
797/*
798 * Probe for certain guest capabilities by writing config bits and reading back.
799 * Finally write back the original value.
800 */
801#define probe_gc0_config(name, maxconf, bits) \
802do { \
803 unsigned int tmp; \
804 tmp = read_gc0_##name(); \
805 write_gc0_##name(tmp | (bits)); \
806 back_to_back_c0_hazard(); \
807 maxconf = read_gc0_##name(); \
808 write_gc0_##name(tmp); \
809} while (0)
810
811/*
812 * Probe for dynamic guest capabilities by changing certain config bits and
813 * reading back to see if they change. Finally write back the original value.
814 */
815#define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \
816do { \
817 maxconf = read_gc0_##name(); \
818 write_gc0_##name(maxconf ^ (bits)); \
819 back_to_back_c0_hazard(); \
820 dynconf = maxconf ^ read_gc0_##name(); \
821 write_gc0_##name(maxconf); \
822 maxconf |= dynconf; \
823} while (0)
824
825static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
826{
827 unsigned int config0;
828
829 probe_gc0_config(config, config0, MIPS_CONF_M);
830
831 if (config0 & MIPS_CONF_M)
832 c->guest.conf |= BIT(1);
833 return config0 & MIPS_CONF_M;
834}
835
836static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
837{
838 unsigned int config1, config1_dyn;
839
840 probe_gc0_config_dyn(config1, config1, config1_dyn,
841 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
842 MIPS_CONF1_FP);
843
844 if (config1 & MIPS_CONF1_FP)
845 c->guest.options |= MIPS_CPU_FPU;
846 if (config1_dyn & MIPS_CONF1_FP)
847 c->guest.options_dyn |= MIPS_CPU_FPU;
848
849 if (config1 & MIPS_CONF1_WR)
850 c->guest.options |= MIPS_CPU_WATCH;
851 if (config1_dyn & MIPS_CONF1_WR)
852 c->guest.options_dyn |= MIPS_CPU_WATCH;
853
854 if (config1 & MIPS_CONF1_PC)
855 c->guest.options |= MIPS_CPU_PERF;
856 if (config1_dyn & MIPS_CONF1_PC)
857 c->guest.options_dyn |= MIPS_CPU_PERF;
858
859 if (config1 & MIPS_CONF_M)
860 c->guest.conf |= BIT(2);
861 return config1 & MIPS_CONF_M;
862}
863
864static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
865{
866 unsigned int config2;
867
868 probe_gc0_config(config2, config2, MIPS_CONF_M);
869
870 if (config2 & MIPS_CONF_M)
871 c->guest.conf |= BIT(3);
872 return config2 & MIPS_CONF_M;
873}
874
875static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
876{
877 unsigned int config3, config3_dyn;
878
879 probe_gc0_config_dyn(config3, config3, config3_dyn,
880 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI |
881 MIPS_CONF3_CTXTC);
882
883 if (config3 & MIPS_CONF3_CTXTC)
884 c->guest.options |= MIPS_CPU_CTXTC;
885 if (config3_dyn & MIPS_CONF3_CTXTC)
886 c->guest.options_dyn |= MIPS_CPU_CTXTC;
887
888 if (config3 & MIPS_CONF3_PW)
889 c->guest.options |= MIPS_CPU_HTW;
890
891 if (config3 & MIPS_CONF3_ULRI)
892 c->guest.options |= MIPS_CPU_ULRI;
893
894 if (config3 & MIPS_CONF3_SC)
895 c->guest.options |= MIPS_CPU_SEGMENTS;
896
897 if (config3 & MIPS_CONF3_BI)
898 c->guest.options |= MIPS_CPU_BADINSTR;
899 if (config3 & MIPS_CONF3_BP)
900 c->guest.options |= MIPS_CPU_BADINSTRP;
901
902 if (config3 & MIPS_CONF3_MSA)
903 c->guest.ases |= MIPS_ASE_MSA;
904 if (config3_dyn & MIPS_CONF3_MSA)
905 c->guest.ases_dyn |= MIPS_ASE_MSA;
906
907 if (config3 & MIPS_CONF_M)
908 c->guest.conf |= BIT(4);
909 return config3 & MIPS_CONF_M;
910}
911
912static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
913{
914 unsigned int config4;
915
916 probe_gc0_config(config4, config4,
917 MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
918
919 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
920 >> MIPS_CONF4_KSCREXIST_SHIFT;
921
922 if (config4 & MIPS_CONF_M)
923 c->guest.conf |= BIT(5);
924 return config4 & MIPS_CONF_M;
925}
926
927static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
928{
929 unsigned int config5, config5_dyn;
930
931 probe_gc0_config_dyn(config5, config5, config5_dyn,
932 MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP);
933
934 if (config5 & MIPS_CONF5_MRP)
935 c->guest.options |= MIPS_CPU_MAAR;
936 if (config5_dyn & MIPS_CONF5_MRP)
937 c->guest.options_dyn |= MIPS_CPU_MAAR;
938
939 if (config5 & MIPS_CONF5_LLB)
940 c->guest.options |= MIPS_CPU_RW_LLB;
941
942 if (config5 & MIPS_CONF5_MVH)
943 c->guest.options |= MIPS_CPU_MVH;
944
945 if (config5 & MIPS_CONF_M)
946 c->guest.conf |= BIT(6);
947 return config5 & MIPS_CONF_M;
948}
949
950static inline void decode_guest_configs(struct cpuinfo_mips *c)
951{
952 unsigned int ok;
953
954 ok = decode_guest_config0(c);
955 if (ok)
956 ok = decode_guest_config1(c);
957 if (ok)
958 ok = decode_guest_config2(c);
959 if (ok)
960 ok = decode_guest_config3(c);
961 if (ok)
962 ok = decode_guest_config4(c);
963 if (ok)
964 decode_guest_config5(c);
965}
966
967static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
968{
969 unsigned int guestctl0, temp;
970
971 guestctl0 = read_c0_guestctl0();
972
973 if (guestctl0 & MIPS_GCTL0_G0E)
974 c->options |= MIPS_CPU_GUESTCTL0EXT;
975 if (guestctl0 & MIPS_GCTL0_G1)
976 c->options |= MIPS_CPU_GUESTCTL1;
977 if (guestctl0 & MIPS_GCTL0_G2)
978 c->options |= MIPS_CPU_GUESTCTL2;
979 if (!(guestctl0 & MIPS_GCTL0_RAD)) {
980 c->options |= MIPS_CPU_GUESTID;
981
982 /*
983 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
984 * first, otherwise all data accesses will be fully virtualised
985 * as if they were performed by guest mode.
986 */
987 write_c0_guestctl1(0);
988 tlbw_use_hazard();
989
990 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
991 back_to_back_c0_hazard();
992 temp = read_c0_guestctl0();
993
994 if (temp & MIPS_GCTL0_DRG) {
995 write_c0_guestctl0(guestctl0);
996 c->options |= MIPS_CPU_DRG;
997 }
998 }
999}
1000
1001static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1002{
1003 if (cpu_has_guestid) {
1004 /* determine the number of bits of GuestID available */
1005 write_c0_guestctl1(MIPS_GCTL1_ID);
1006 back_to_back_c0_hazard();
1007 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1008 >> MIPS_GCTL1_ID_SHIFT;
1009 write_c0_guestctl1(0);
1010 }
1011}
1012
1013static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1014{
1015 /* determine the number of bits of GTOffset available */
1016 write_c0_gtoffset(0xffffffff);
1017 back_to_back_c0_hazard();
1018 c->gtoffset_mask = read_c0_gtoffset();
1019 write_c0_gtoffset(0);
1020}
1021
1022static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1023{
1024 cpu_probe_guestctl0(c);
1025 if (cpu_has_guestctl1)
1026 cpu_probe_guestctl1(c);
1027
1028 cpu_probe_gtoffset(c);
1029
1030 decode_guest_configs(c);
1031}
1032
1033#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1034 | MIPS_CPU_COUNTER)
1035
1036static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1037{
1038 switch (c->processor_id & PRID_IMP_MASK) {
1039 case PRID_IMP_R2000:
1040 c->cputype = CPU_R2000;
1041 __cpu_name[cpu] = "R2000";
1042 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1043 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1044 MIPS_CPU_NOFPUEX;
1045 if (__cpu_has_fpu())
1046 c->options |= MIPS_CPU_FPU;
1047 c->tlbsize = 64;
1048 break;
1049 case PRID_IMP_R3000:
1050 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
1051 if (cpu_has_confreg()) {
1052 c->cputype = CPU_R3081E;
1053 __cpu_name[cpu] = "R3081";
1054 } else {
1055 c->cputype = CPU_R3000A;
1056 __cpu_name[cpu] = "R3000A";
1057 }
1058 } else {
1059 c->cputype = CPU_R3000;
1060 __cpu_name[cpu] = "R3000";
1061 }
1062 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1063 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1064 MIPS_CPU_NOFPUEX;
1065 if (__cpu_has_fpu())
1066 c->options |= MIPS_CPU_FPU;
1067 c->tlbsize = 64;
1068 break;
1069 case PRID_IMP_R4000:
1070 if (read_c0_config() & CONF_SC) {
1071 if ((c->processor_id & PRID_REV_MASK) >=
1072 PRID_REV_R4400) {
1073 c->cputype = CPU_R4400PC;
1074 __cpu_name[cpu] = "R4400PC";
1075 } else {
1076 c->cputype = CPU_R4000PC;
1077 __cpu_name[cpu] = "R4000PC";
1078 }
1079 } else {
1080 int cca = read_c0_config() & CONF_CM_CMASK;
1081 int mc;
1082
1083 /*
1084 * SC and MC versions can't be reliably told apart,
1085 * but only the latter support coherent caching
1086 * modes so assume the firmware has set the KSEG0
1087 * coherency attribute reasonably (if uncached, we
1088 * assume SC).
1089 */
1090 switch (cca) {
1091 case CONF_CM_CACHABLE_CE:
1092 case CONF_CM_CACHABLE_COW:
1093 case CONF_CM_CACHABLE_CUW:
1094 mc = 1;
1095 break;
1096 default:
1097 mc = 0;
1098 break;
1099 }
1100 if ((c->processor_id & PRID_REV_MASK) >=
1101 PRID_REV_R4400) {
1102 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1103 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
1104 } else {
1105 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1106 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
1107 }
1108 }
1109
1110 set_isa(c, MIPS_CPU_ISA_III);
1111 c->fpu_msk31 |= FPU_CSR_CONDX;
1112 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1113 MIPS_CPU_WATCH | MIPS_CPU_VCE |
1114 MIPS_CPU_LLSC;
1115 c->tlbsize = 48;
1116 break;
1117 case PRID_IMP_R4300:
1118 c->cputype = CPU_R4300;
1119 __cpu_name[cpu] = "R4300";
1120 set_isa(c, MIPS_CPU_ISA_III);
1121 c->fpu_msk31 |= FPU_CSR_CONDX;
1122 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1123 MIPS_CPU_LLSC;
1124 c->tlbsize = 32;
1125 break;
1126 case PRID_IMP_R4600:
1127 c->cputype = CPU_R4600;
1128 __cpu_name[cpu] = "R4600";
1129 set_isa(c, MIPS_CPU_ISA_III);
1130 c->fpu_msk31 |= FPU_CSR_CONDX;
1131 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1132 MIPS_CPU_LLSC;
1133 c->tlbsize = 48;
1134 break;
1135 #if 0
1136 case PRID_IMP_R4650:
1137 /*
1138 * This processor doesn't have an MMU, so it's not
1139 * "real easy" to run Linux on it. It is left purely
1140 * for documentation. Commented out because it shares
1141 * its c0_prid id number with the TX3900.
1142 */
1143 c->cputype = CPU_R4650;
1144 __cpu_name[cpu] = "R4650";
1145 set_isa(c, MIPS_CPU_ISA_III);
1146 c->fpu_msk31 |= FPU_CSR_CONDX;
1147 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1148 c->tlbsize = 48;
1149 break;
1150 #endif
1151 case PRID_IMP_R4700:
1152 c->cputype = CPU_R4700;
1153 __cpu_name[cpu] = "R4700";
1154 set_isa(c, MIPS_CPU_ISA_III);
1155 c->fpu_msk31 |= FPU_CSR_CONDX;
1156 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1157 MIPS_CPU_LLSC;
1158 c->tlbsize = 48;
1159 break;
1160 case PRID_IMP_TX49:
1161 c->cputype = CPU_TX49XX;
1162 __cpu_name[cpu] = "R49XX";
1163 set_isa(c, MIPS_CPU_ISA_III);
1164 c->fpu_msk31 |= FPU_CSR_CONDX;
1165 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1166 if (!(c->processor_id & 0x08))
1167 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1168 c->tlbsize = 48;
1169 break;
1170 case PRID_IMP_R5000:
1171 c->cputype = CPU_R5000;
1172 __cpu_name[cpu] = "R5000";
1173 set_isa(c, MIPS_CPU_ISA_IV);
1174 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1175 MIPS_CPU_LLSC;
1176 c->tlbsize = 48;
1177 break;
1178 case PRID_IMP_R5500:
1179 c->cputype = CPU_R5500;
1180 __cpu_name[cpu] = "R5500";
1181 set_isa(c, MIPS_CPU_ISA_IV);
1182 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1183 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1184 c->tlbsize = 48;
1185 break;
1186 case PRID_IMP_NEVADA:
1187 c->cputype = CPU_NEVADA;
1188 __cpu_name[cpu] = "Nevada";
1189 set_isa(c, MIPS_CPU_ISA_IV);
1190 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1191 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1192 c->tlbsize = 48;
1193 break;
1194 case PRID_IMP_RM7000:
1195 c->cputype = CPU_RM7000;
1196 __cpu_name[cpu] = "RM7000";
1197 set_isa(c, MIPS_CPU_ISA_IV);
1198 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1199 MIPS_CPU_LLSC;
1200 /*
1201 * Undocumented RM7000: Bit 29 in the info register of
1202 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1203 * entries.
1204 *
1205 * 29 1 => 64 entry JTLB
1206 * 0 => 48 entry JTLB
1207 */
1208 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1209 break;
1210 case PRID_IMP_R10000:
1211 c->cputype = CPU_R10000;
1212 __cpu_name[cpu] = "R10000";
1213 set_isa(c, MIPS_CPU_ISA_IV);
1214 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1215 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1216 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1217 MIPS_CPU_LLSC;
1218 c->tlbsize = 64;
1219 break;
1220 case PRID_IMP_R12000:
1221 c->cputype = CPU_R12000;
1222 __cpu_name[cpu] = "R12000";
1223 set_isa(c, MIPS_CPU_ISA_IV);
1224 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1225 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1226 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1227 MIPS_CPU_LLSC;
1228 c->tlbsize = 64;
1229 write_c0_r10k_diag(read_c0_r10k_diag() | R10K_DIAG_E_GHIST);
1230 break;
1231 case PRID_IMP_R14000:
1232 if (((c->processor_id >> 4) & 0x0f) > 2) {
1233 c->cputype = CPU_R16000;
1234 __cpu_name[cpu] = "R16000";
1235 } else {
1236 c->cputype = CPU_R14000;
1237 __cpu_name[cpu] = "R14000";
1238 }
1239 set_isa(c, MIPS_CPU_ISA_IV);
1240 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1241 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1242 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1243 MIPS_CPU_LLSC;
1244 c->tlbsize = 64;
1245 write_c0_r10k_diag(read_c0_r10k_diag() | R10K_DIAG_E_GHIST);
1246 break;
1247 case PRID_IMP_LOONGSON_64C: /* Loongson-2/3 */
1248 switch (c->processor_id & PRID_REV_MASK) {
1249 case PRID_REV_LOONGSON2E:
1250 c->cputype = CPU_LOONGSON2EF;
1251 __cpu_name[cpu] = "ICT Loongson-2";
1252 set_elf_platform(cpu, "loongson2e");
1253 set_isa(c, MIPS_CPU_ISA_III);
1254 c->fpu_msk31 |= FPU_CSR_CONDX;
1255 break;
1256 case PRID_REV_LOONGSON2F:
1257 c->cputype = CPU_LOONGSON2EF;
1258 __cpu_name[cpu] = "ICT Loongson-2";
1259 set_elf_platform(cpu, "loongson2f");
1260 set_isa(c, MIPS_CPU_ISA_III);
1261 c->fpu_msk31 |= FPU_CSR_CONDX;
1262 break;
1263 case PRID_REV_LOONGSON3A_R1:
1264 c->cputype = CPU_LOONGSON64;
1265 __cpu_name[cpu] = "ICT Loongson-3";
1266 set_elf_platform(cpu, "loongson3a");
1267 set_isa(c, MIPS_CPU_ISA_M64R1);
1268 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1269 MIPS_ASE_LOONGSON_EXT);
1270 break;
1271 case PRID_REV_LOONGSON3B_R1:
1272 case PRID_REV_LOONGSON3B_R2:
1273 c->cputype = CPU_LOONGSON64;
1274 __cpu_name[cpu] = "ICT Loongson-3";
1275 set_elf_platform(cpu, "loongson3b");
1276 set_isa(c, MIPS_CPU_ISA_M64R1);
1277 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1278 MIPS_ASE_LOONGSON_EXT);
1279 break;
1280 }
1281
1282 c->options = R4K_OPTS |
1283 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1284 MIPS_CPU_32FPR;
1285 c->tlbsize = 64;
1286 set_cpu_asid_mask(c, MIPS_ENTRYHI_ASID);
1287 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1288 break;
1289 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1290 decode_configs(c);
1291
1292 c->cputype = CPU_LOONGSON32;
1293
1294 switch (c->processor_id & PRID_REV_MASK) {
1295 case PRID_REV_LOONGSON1B:
1296 __cpu_name[cpu] = "Loongson 1B";
1297 break;
1298 }
1299
1300 break;
1301 }
1302}
1303
1304static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1305{
1306 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1307 switch (c->processor_id & PRID_IMP_MASK) {
1308 case PRID_IMP_QEMU_GENERIC:
1309 c->writecombine = _CACHE_UNCACHED;
1310 c->cputype = CPU_QEMU_GENERIC;
1311 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1312 break;
1313 case PRID_IMP_4KC:
1314 c->cputype = CPU_4KC;
1315 c->writecombine = _CACHE_UNCACHED;
1316 __cpu_name[cpu] = "MIPS 4Kc";
1317 break;
1318 case PRID_IMP_4KEC:
1319 case PRID_IMP_4KECR2:
1320 c->cputype = CPU_4KEC;
1321 c->writecombine = _CACHE_UNCACHED;
1322 __cpu_name[cpu] = "MIPS 4KEc";
1323 break;
1324 case PRID_IMP_4KSC:
1325 case PRID_IMP_4KSD:
1326 c->cputype = CPU_4KSC;
1327 c->writecombine = _CACHE_UNCACHED;
1328 __cpu_name[cpu] = "MIPS 4KSc";
1329 break;
1330 case PRID_IMP_5KC:
1331 c->cputype = CPU_5KC;
1332 c->writecombine = _CACHE_UNCACHED;
1333 __cpu_name[cpu] = "MIPS 5Kc";
1334 break;
1335 case PRID_IMP_5KE:
1336 c->cputype = CPU_5KE;
1337 c->writecombine = _CACHE_UNCACHED;
1338 __cpu_name[cpu] = "MIPS 5KE";
1339 break;
1340 case PRID_IMP_20KC:
1341 c->cputype = CPU_20KC;
1342 c->writecombine = _CACHE_UNCACHED;
1343 __cpu_name[cpu] = "MIPS 20Kc";
1344 break;
1345 case PRID_IMP_24K:
1346 c->cputype = CPU_24K;
1347 c->writecombine = _CACHE_UNCACHED;
1348 __cpu_name[cpu] = "MIPS 24Kc";
1349 break;
1350 case PRID_IMP_24KE:
1351 c->cputype = CPU_24K;
1352 c->writecombine = _CACHE_UNCACHED;
1353 __cpu_name[cpu] = "MIPS 24KEc";
1354 break;
1355 case PRID_IMP_25KF:
1356 c->cputype = CPU_25KF;
1357 c->writecombine = _CACHE_UNCACHED;
1358 __cpu_name[cpu] = "MIPS 25Kc";
1359 break;
1360 case PRID_IMP_34K:
1361 c->cputype = CPU_34K;
1362 c->writecombine = _CACHE_UNCACHED;
1363 __cpu_name[cpu] = "MIPS 34Kc";
1364 cpu_set_mt_per_tc_perf(c);
1365 break;
1366 case PRID_IMP_74K:
1367 c->cputype = CPU_74K;
1368 c->writecombine = _CACHE_UNCACHED;
1369 __cpu_name[cpu] = "MIPS 74Kc";
1370 break;
1371 case PRID_IMP_M14KC:
1372 c->cputype = CPU_M14KC;
1373 c->writecombine = _CACHE_UNCACHED;
1374 __cpu_name[cpu] = "MIPS M14Kc";
1375 break;
1376 case PRID_IMP_M14KEC:
1377 c->cputype = CPU_M14KEC;
1378 c->writecombine = _CACHE_UNCACHED;
1379 __cpu_name[cpu] = "MIPS M14KEc";
1380 break;
1381 case PRID_IMP_1004K:
1382 c->cputype = CPU_1004K;
1383 c->writecombine = _CACHE_UNCACHED;
1384 __cpu_name[cpu] = "MIPS 1004Kc";
1385 cpu_set_mt_per_tc_perf(c);
1386 break;
1387 case PRID_IMP_1074K:
1388 c->cputype = CPU_1074K;
1389 c->writecombine = _CACHE_UNCACHED;
1390 __cpu_name[cpu] = "MIPS 1074Kc";
1391 break;
1392 case PRID_IMP_INTERAPTIV_UP:
1393 c->cputype = CPU_INTERAPTIV;
1394 __cpu_name[cpu] = "MIPS interAptiv";
1395 cpu_set_mt_per_tc_perf(c);
1396 break;
1397 case PRID_IMP_INTERAPTIV_MP:
1398 c->cputype = CPU_INTERAPTIV;
1399 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1400 cpu_set_mt_per_tc_perf(c);
1401 break;
1402 case PRID_IMP_PROAPTIV_UP:
1403 c->cputype = CPU_PROAPTIV;
1404 __cpu_name[cpu] = "MIPS proAptiv";
1405 break;
1406 case PRID_IMP_PROAPTIV_MP:
1407 c->cputype = CPU_PROAPTIV;
1408 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1409 break;
1410 case PRID_IMP_P5600:
1411 c->cputype = CPU_P5600;
1412 __cpu_name[cpu] = "MIPS P5600";
1413 break;
1414 case PRID_IMP_P6600:
1415 c->cputype = CPU_P6600;
1416 __cpu_name[cpu] = "MIPS P6600";
1417 break;
1418 case PRID_IMP_I6400:
1419 c->cputype = CPU_I6400;
1420 __cpu_name[cpu] = "MIPS I6400";
1421 break;
1422 case PRID_IMP_I6500:
1423 c->cputype = CPU_I6500;
1424 __cpu_name[cpu] = "MIPS I6500";
1425 break;
1426 case PRID_IMP_M5150:
1427 c->cputype = CPU_M5150;
1428 __cpu_name[cpu] = "MIPS M5150";
1429 break;
1430 case PRID_IMP_M6250:
1431 c->cputype = CPU_M6250;
1432 __cpu_name[cpu] = "MIPS M6250";
1433 break;
1434 }
1435
1436 decode_configs(c);
1437
1438 spram_config();
1439
1440 mm_config(c);
1441
1442 switch (__get_cpu_type(c->cputype)) {
1443 case CPU_M5150:
1444 case CPU_P5600:
1445 set_isa(c, MIPS_CPU_ISA_M32R5);
1446 break;
1447 case CPU_I6500:
1448 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES;
1449 fallthrough;
1450 case CPU_I6400:
1451 c->options |= MIPS_CPU_SHARED_FTLB_RAM;
1452 fallthrough;
1453 default:
1454 break;
1455 }
1456
1457 /* Recent MIPS cores use the implementation-dependent ExcCode 16 for
1458 * cache/FTLB parity exceptions.
1459 */
1460 switch (__get_cpu_type(c->cputype)) {
1461 case CPU_PROAPTIV:
1462 case CPU_P5600:
1463 case CPU_P6600:
1464 case CPU_I6400:
1465 case CPU_I6500:
1466 c->options |= MIPS_CPU_FTLBPAREX;
1467 break;
1468 }
1469}
1470
1471static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1472{
1473 decode_configs(c);
1474 switch (c->processor_id & PRID_IMP_MASK) {
1475 case PRID_IMP_AU1_REV1:
1476 case PRID_IMP_AU1_REV2:
1477 c->cputype = CPU_ALCHEMY;
1478 switch ((c->processor_id >> 24) & 0xff) {
1479 case 0:
1480 __cpu_name[cpu] = "Au1000";
1481 break;
1482 case 1:
1483 __cpu_name[cpu] = "Au1500";
1484 break;
1485 case 2:
1486 __cpu_name[cpu] = "Au1100";
1487 break;
1488 case 3:
1489 __cpu_name[cpu] = "Au1550";
1490 break;
1491 case 4:
1492 __cpu_name[cpu] = "Au1200";
1493 if ((c->processor_id & PRID_REV_MASK) == 2)
1494 __cpu_name[cpu] = "Au1250";
1495 break;
1496 case 5:
1497 __cpu_name[cpu] = "Au1210";
1498 break;
1499 default:
1500 __cpu_name[cpu] = "Au1xxx";
1501 break;
1502 }
1503 break;
1504 case PRID_IMP_NETLOGIC_AU13XX:
1505 c->cputype = CPU_ALCHEMY;
1506 __cpu_name[cpu] = "Au1300";
1507 break;
1508 }
1509}
1510
1511static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1512{
1513 decode_configs(c);
1514
1515 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1516 switch (c->processor_id & PRID_IMP_MASK) {
1517 case PRID_IMP_SB1:
1518 c->cputype = CPU_SB1;
1519 __cpu_name[cpu] = "SiByte SB1";
1520 /* FPU in pass1 is known to have issues. */
1521 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1522 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1523 break;
1524 case PRID_IMP_SB1A:
1525 c->cputype = CPU_SB1A;
1526 __cpu_name[cpu] = "SiByte SB1A";
1527 break;
1528 }
1529}
1530
1531static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1532{
1533 decode_configs(c);
1534 switch (c->processor_id & PRID_IMP_MASK) {
1535 case PRID_IMP_SR71000:
1536 c->cputype = CPU_SR71000;
1537 __cpu_name[cpu] = "Sandcraft SR71000";
1538 c->scache.ways = 8;
1539 c->tlbsize = 64;
1540 break;
1541 }
1542}
1543
1544static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1545{
1546 decode_configs(c);
1547 switch (c->processor_id & PRID_IMP_MASK) {
1548 case PRID_IMP_PR4450:
1549 c->cputype = CPU_PR4450;
1550 __cpu_name[cpu] = "Philips PR4450";
1551 set_isa(c, MIPS_CPU_ISA_M32R1);
1552 break;
1553 }
1554}
1555
1556static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1557{
1558 decode_configs(c);
1559 switch (c->processor_id & PRID_IMP_MASK) {
1560 case PRID_IMP_BMIPS32_REV4:
1561 case PRID_IMP_BMIPS32_REV8:
1562 c->cputype = CPU_BMIPS32;
1563 __cpu_name[cpu] = "Broadcom BMIPS32";
1564 set_elf_platform(cpu, "bmips32");
1565 break;
1566 case PRID_IMP_BMIPS3300:
1567 case PRID_IMP_BMIPS3300_ALT:
1568 case PRID_IMP_BMIPS3300_BUG:
1569 c->cputype = CPU_BMIPS3300;
1570 __cpu_name[cpu] = "Broadcom BMIPS3300";
1571 set_elf_platform(cpu, "bmips3300");
1572 reserve_exception_space(0x400, VECTORSPACING * 64);
1573 break;
1574 case PRID_IMP_BMIPS43XX: {
1575 int rev = c->processor_id & PRID_REV_MASK;
1576
1577 if (rev >= PRID_REV_BMIPS4380_LO &&
1578 rev <= PRID_REV_BMIPS4380_HI) {
1579 c->cputype = CPU_BMIPS4380;
1580 __cpu_name[cpu] = "Broadcom BMIPS4380";
1581 set_elf_platform(cpu, "bmips4380");
1582 c->options |= MIPS_CPU_RIXI;
1583 reserve_exception_space(0x400, VECTORSPACING * 64);
1584 } else {
1585 c->cputype = CPU_BMIPS4350;
1586 __cpu_name[cpu] = "Broadcom BMIPS4350";
1587 set_elf_platform(cpu, "bmips4350");
1588 }
1589 break;
1590 }
1591 case PRID_IMP_BMIPS5000:
1592 case PRID_IMP_BMIPS5200:
1593 c->cputype = CPU_BMIPS5000;
1594 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1595 __cpu_name[cpu] = "Broadcom BMIPS5200";
1596 else
1597 __cpu_name[cpu] = "Broadcom BMIPS5000";
1598 set_elf_platform(cpu, "bmips5000");
1599 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
1600 reserve_exception_space(0x1000, VECTORSPACING * 64);
1601 break;
1602 }
1603}
1604
1605static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1606{
1607 decode_configs(c);
1608 /* Octeon has different cache interface */
1609 c->options &= ~MIPS_CPU_4K_CACHE;
1610 switch (c->processor_id & PRID_IMP_MASK) {
1611 case PRID_IMP_CAVIUM_CN38XX:
1612 case PRID_IMP_CAVIUM_CN31XX:
1613 case PRID_IMP_CAVIUM_CN30XX:
1614 c->cputype = CPU_CAVIUM_OCTEON;
1615 __cpu_name[cpu] = "Cavium Octeon";
1616 goto platform;
1617 case PRID_IMP_CAVIUM_CN58XX:
1618 case PRID_IMP_CAVIUM_CN56XX:
1619 case PRID_IMP_CAVIUM_CN50XX:
1620 case PRID_IMP_CAVIUM_CN52XX:
1621 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1622 __cpu_name[cpu] = "Cavium Octeon+";
1623platform:
1624 set_elf_platform(cpu, "octeon");
1625 break;
1626 case PRID_IMP_CAVIUM_CN61XX:
1627 case PRID_IMP_CAVIUM_CN63XX:
1628 case PRID_IMP_CAVIUM_CN66XX:
1629 case PRID_IMP_CAVIUM_CN68XX:
1630 case PRID_IMP_CAVIUM_CNF71XX:
1631 c->cputype = CPU_CAVIUM_OCTEON2;
1632 __cpu_name[cpu] = "Cavium Octeon II";
1633 set_elf_platform(cpu, "octeon2");
1634 break;
1635 case PRID_IMP_CAVIUM_CN70XX:
1636 case PRID_IMP_CAVIUM_CN73XX:
1637 case PRID_IMP_CAVIUM_CNF75XX:
1638 case PRID_IMP_CAVIUM_CN78XX:
1639 c->cputype = CPU_CAVIUM_OCTEON3;
1640 __cpu_name[cpu] = "Cavium Octeon III";
1641 set_elf_platform(cpu, "octeon3");
1642 break;
1643 default:
1644 printk(KERN_INFO "Unknown Octeon chip!\n");
1645 c->cputype = CPU_UNKNOWN;
1646 break;
1647 }
1648}
1649
1650#ifdef CONFIG_CPU_LOONGSON64
1651#include <loongson_regs.h>
1652
1653static inline void decode_cpucfg(struct cpuinfo_mips *c)
1654{
1655 u32 cfg1 = read_cpucfg(LOONGSON_CFG1);
1656 u32 cfg2 = read_cpucfg(LOONGSON_CFG2);
1657 u32 cfg3 = read_cpucfg(LOONGSON_CFG3);
1658
1659 if (cfg1 & LOONGSON_CFG1_MMI)
1660 c->ases |= MIPS_ASE_LOONGSON_MMI;
1661
1662 if (cfg2 & LOONGSON_CFG2_LEXT1)
1663 c->ases |= MIPS_ASE_LOONGSON_EXT;
1664
1665 if (cfg2 & LOONGSON_CFG2_LEXT2)
1666 c->ases |= MIPS_ASE_LOONGSON_EXT2;
1667
1668 if (cfg2 & LOONGSON_CFG2_LSPW) {
1669 c->options |= MIPS_CPU_LDPTE;
1670 c->guest.options |= MIPS_CPU_LDPTE;
1671 }
1672
1673 if (cfg3 & LOONGSON_CFG3_LCAMP)
1674 c->ases |= MIPS_ASE_LOONGSON_CAM;
1675}
1676
1677static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1678{
1679 c->cputype = CPU_LOONGSON64;
1680
1681 /* All Loongson processors covered here define ExcCode 16 as GSExc. */
1682 decode_configs(c);
1683 c->options |= MIPS_CPU_GSEXCEX;
1684
1685 switch (c->processor_id & PRID_IMP_MASK) {
1686 case PRID_IMP_LOONGSON_64R: /* Loongson-64 Reduced */
1687 switch (c->processor_id & PRID_REV_MASK) {
1688 case PRID_REV_LOONGSON2K_R1_0:
1689 case PRID_REV_LOONGSON2K_R1_1:
1690 case PRID_REV_LOONGSON2K_R1_2:
1691 case PRID_REV_LOONGSON2K_R1_3:
1692 __cpu_name[cpu] = "Loongson-2K";
1693 set_elf_platform(cpu, "gs264e");
1694 set_isa(c, MIPS_CPU_ISA_M64R2);
1695 break;
1696 }
1697 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_EXT |
1698 MIPS_ASE_LOONGSON_EXT2);
1699 break;
1700 case PRID_IMP_LOONGSON_64C: /* Loongson-3 Classic */
1701 switch (c->processor_id & PRID_REV_MASK) {
1702 case PRID_REV_LOONGSON3A_R2_0:
1703 case PRID_REV_LOONGSON3A_R2_1:
1704 __cpu_name[cpu] = "ICT Loongson-3";
1705 set_elf_platform(cpu, "loongson3a");
1706 set_isa(c, MIPS_CPU_ISA_M64R2);
1707 break;
1708 case PRID_REV_LOONGSON3A_R3_0:
1709 case PRID_REV_LOONGSON3A_R3_1:
1710 __cpu_name[cpu] = "ICT Loongson-3";
1711 set_elf_platform(cpu, "loongson3a");
1712 set_isa(c, MIPS_CPU_ISA_M64R2);
1713 break;
1714 }
1715 /*
1716 * Loongson-3 Classic did not implement MIPS standard TLBINV
1717 * but implemented TLBINVF and EHINV. As currently we're only
1718 * using these two features, enable MIPS_CPU_TLBINV as well.
1719 *
1720 * Also some early Loongson-3A2000 had wrong TLB type in Config
1721 * register, we correct it here.
1722 */
1723 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
1724 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1725 MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
1726 c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */
1727 change_c0_config6(LOONGSON_CONF6_EXTIMER | LOONGSON_CONF6_INTIMER,
1728 LOONGSON_CONF6_INTIMER);
1729 break;
1730 case PRID_IMP_LOONGSON_64G:
1731 __cpu_name[cpu] = "ICT Loongson-3";
1732 set_elf_platform(cpu, "loongson3a");
1733 set_isa(c, MIPS_CPU_ISA_M64R2);
1734 decode_cpucfg(c);
1735 change_c0_config6(LOONGSON_CONF6_EXTIMER | LOONGSON_CONF6_INTIMER,
1736 LOONGSON_CONF6_INTIMER);
1737 break;
1738 default:
1739 panic("Unknown Loongson Processor ID!");
1740 break;
1741 }
1742}
1743#else
1744static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { }
1745#endif
1746
1747static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1748{
1749 decode_configs(c);
1750
1751 /*
1752 * XBurst misses a config2 register, so config3 decode was skipped in
1753 * decode_configs().
1754 */
1755 decode_config3(c);
1756
1757 /* XBurst does not implement the CP0 counter. */
1758 c->options &= ~MIPS_CPU_COUNTER;
1759 BUG_ON(__builtin_constant_p(cpu_has_counter) && cpu_has_counter);
1760
1761 /* XBurst has virtually tagged icache */
1762 c->icache.flags |= MIPS_CACHE_VTAG;
1763
1764 switch (c->processor_id & PRID_IMP_MASK) {
1765
1766 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
1767 case PRID_IMP_XBURST_REV1:
1768
1769 /*
1770 * The XBurst core by default attempts to avoid branch target
1771 * buffer lookups by detecting & special casing loops. This
1772 * feature will cause BogoMIPS and lpj calculate in error.
1773 * Set cp0 config7 bit 4 to disable this feature.
1774 */
1775 set_c0_config7(MIPS_CONF7_BTB_LOOP_EN);
1776
1777 switch (c->processor_id & PRID_COMP_MASK) {
1778
1779 /*
1780 * The config0 register in the XBurst CPUs with a processor ID of
1781 * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
1782 * but they don't actually support this ISA.
1783 */
1784 case PRID_COMP_INGENIC_D0:
1785 c->isa_level &= ~MIPS_CPU_ISA_M32R2;
1786
1787 /* FPU is not properly detected on JZ4760(B). */
1788 if (c->processor_id == 0x2ed0024f)
1789 c->options |= MIPS_CPU_FPU;
1790
1791 fallthrough;
1792
1793 /*
1794 * The config0 register in the XBurst CPUs with a processor ID of
1795 * PRID_COMP_INGENIC_D0 or PRID_COMP_INGENIC_D1 has an abandoned
1796 * huge page tlb mode, this mode is not compatible with the MIPS
1797 * standard, it will cause tlbmiss and into an infinite loop
1798 * (line 21 in the tlb-funcs.S) when starting the init process.
1799 * After chip reset, the default is HPTLB mode, Write 0xa9000000
1800 * to cp0 register 5 sel 4 to switch back to VTLB mode to prevent
1801 * getting stuck.
1802 */
1803 case PRID_COMP_INGENIC_D1:
1804 write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS);
1805 break;
1806
1807 default:
1808 break;
1809 }
1810 fallthrough;
1811
1812 /* XBurst®1 with MXU2.0 SIMD ISA */
1813 case PRID_IMP_XBURST_REV2:
1814 /* Ingenic uses the WA bit to achieve write-combine memory writes */
1815 c->writecombine = _CACHE_CACHABLE_WA;
1816 c->cputype = CPU_XBURST;
1817 __cpu_name[cpu] = "Ingenic XBurst";
1818 break;
1819
1820 /* XBurst®2 with MXU2.1 SIMD ISA */
1821 case PRID_IMP_XBURST2:
1822 c->cputype = CPU_XBURST;
1823 __cpu_name[cpu] = "Ingenic XBurst II";
1824 break;
1825
1826 default:
1827 panic("Unknown Ingenic Processor ID!");
1828 break;
1829 }
1830}
1831
1832#ifdef CONFIG_64BIT
1833/* For use by uaccess.h */
1834u64 __ua_limit;
1835EXPORT_SYMBOL(__ua_limit);
1836#endif
1837
1838const char *__cpu_name[NR_CPUS];
1839const char *__elf_platform;
1840const char *__elf_base_platform;
1841
1842void cpu_probe(void)
1843{
1844 struct cpuinfo_mips *c = ¤t_cpu_data;
1845 unsigned int cpu = smp_processor_id();
1846
1847 /*
1848 * Set a default elf platform, cpu probe may later
1849 * overwrite it with a more precise value
1850 */
1851 set_elf_platform(cpu, "mips");
1852
1853 c->processor_id = PRID_IMP_UNKNOWN;
1854 c->fpu_id = FPIR_IMP_NONE;
1855 c->cputype = CPU_UNKNOWN;
1856 c->writecombine = _CACHE_UNCACHED;
1857
1858 c->fpu_csr31 = FPU_CSR_RN;
1859 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1860
1861 c->processor_id = read_c0_prid();
1862 switch (c->processor_id & PRID_COMP_MASK) {
1863 case PRID_COMP_LEGACY:
1864 cpu_probe_legacy(c, cpu);
1865 break;
1866 case PRID_COMP_MIPS:
1867 cpu_probe_mips(c, cpu);
1868 break;
1869 case PRID_COMP_ALCHEMY:
1870 case PRID_COMP_NETLOGIC:
1871 cpu_probe_alchemy(c, cpu);
1872 break;
1873 case PRID_COMP_SIBYTE:
1874 cpu_probe_sibyte(c, cpu);
1875 break;
1876 case PRID_COMP_BROADCOM:
1877 cpu_probe_broadcom(c, cpu);
1878 break;
1879 case PRID_COMP_SANDCRAFT:
1880 cpu_probe_sandcraft(c, cpu);
1881 break;
1882 case PRID_COMP_NXP:
1883 cpu_probe_nxp(c, cpu);
1884 break;
1885 case PRID_COMP_CAVIUM:
1886 cpu_probe_cavium(c, cpu);
1887 break;
1888 case PRID_COMP_LOONGSON:
1889 cpu_probe_loongson(c, cpu);
1890 break;
1891 case PRID_COMP_INGENIC_13:
1892 case PRID_COMP_INGENIC_D0:
1893 case PRID_COMP_INGENIC_D1:
1894 case PRID_COMP_INGENIC_E1:
1895 cpu_probe_ingenic(c, cpu);
1896 break;
1897 }
1898
1899 BUG_ON(!__cpu_name[cpu]);
1900 BUG_ON(c->cputype == CPU_UNKNOWN);
1901
1902 /*
1903 * Platform code can force the cpu type to optimize code
1904 * generation. In that case be sure the cpu type is correctly
1905 * manually setup otherwise it could trigger some nasty bugs.
1906 */
1907 BUG_ON(current_cpu_type() != c->cputype);
1908
1909 if (cpu_has_rixi) {
1910 /* Enable the RIXI exceptions */
1911 set_c0_pagegrain(PG_IEC);
1912 back_to_back_c0_hazard();
1913 /* Verify the IEC bit is set */
1914 if (read_c0_pagegrain() & PG_IEC)
1915 c->options |= MIPS_CPU_RIXIEX;
1916 }
1917
1918 if (mips_fpu_disabled)
1919 c->options &= ~MIPS_CPU_FPU;
1920
1921 if (mips_dsp_disabled)
1922 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1923
1924 if (mips_htw_disabled) {
1925 c->options &= ~MIPS_CPU_HTW;
1926 write_c0_pwctl(read_c0_pwctl() &
1927 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1928 }
1929
1930 if (c->options & MIPS_CPU_FPU)
1931 cpu_set_fpu_opts(c);
1932 else
1933 cpu_set_nofpu_opts(c);
1934
1935 if (cpu_has_mips_r2_r6) {
1936 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1937 /* R2 has Performance Counter Interrupt indicator */
1938 c->options |= MIPS_CPU_PCI;
1939 }
1940 else
1941 c->srsets = 1;
1942
1943 if (cpu_has_mips_r6)
1944 elf_hwcap |= HWCAP_MIPS_R6;
1945
1946 if (cpu_has_msa) {
1947 c->msa_id = cpu_get_msa_id();
1948 WARN(c->msa_id & MSA_IR_WRPF,
1949 "Vector register partitioning unimplemented!");
1950 elf_hwcap |= HWCAP_MIPS_MSA;
1951 }
1952
1953 if (cpu_has_mips16)
1954 elf_hwcap |= HWCAP_MIPS_MIPS16;
1955
1956 if (cpu_has_mdmx)
1957 elf_hwcap |= HWCAP_MIPS_MDMX;
1958
1959 if (cpu_has_mips3d)
1960 elf_hwcap |= HWCAP_MIPS_MIPS3D;
1961
1962 if (cpu_has_smartmips)
1963 elf_hwcap |= HWCAP_MIPS_SMARTMIPS;
1964
1965 if (cpu_has_dsp)
1966 elf_hwcap |= HWCAP_MIPS_DSP;
1967
1968 if (cpu_has_dsp2)
1969 elf_hwcap |= HWCAP_MIPS_DSP2;
1970
1971 if (cpu_has_dsp3)
1972 elf_hwcap |= HWCAP_MIPS_DSP3;
1973
1974 if (cpu_has_mips16e2)
1975 elf_hwcap |= HWCAP_MIPS_MIPS16E2;
1976
1977 if (cpu_has_loongson_mmi)
1978 elf_hwcap |= HWCAP_LOONGSON_MMI;
1979
1980 if (cpu_has_loongson_ext)
1981 elf_hwcap |= HWCAP_LOONGSON_EXT;
1982
1983 if (cpu_has_loongson_ext2)
1984 elf_hwcap |= HWCAP_LOONGSON_EXT2;
1985
1986 if (cpu_has_vz)
1987 cpu_probe_vz(c);
1988
1989 cpu_probe_vmbits(c);
1990
1991 /* Synthesize CPUCFG data if running on Loongson processors;
1992 * no-op otherwise.
1993 *
1994 * This looks at previously probed features, so keep this at bottom.
1995 */
1996 loongson3_cpucfg_synthesize_data(c);
1997
1998#ifdef CONFIG_64BIT
1999 if (cpu == 0)
2000 __ua_limit = ~((1ull << cpu_vmbits) - 1);
2001#endif
2002
2003 reserve_exception_space(0, 0x1000);
2004}
2005
2006void cpu_report(void)
2007{
2008 struct cpuinfo_mips *c = ¤t_cpu_data;
2009
2010 pr_info("CPU%d revision is: %08x (%s)\n",
2011 smp_processor_id(), c->processor_id, cpu_name_string());
2012 if (c->options & MIPS_CPU_FPU)
2013 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
2014 if (cpu_has_msa)
2015 pr_info("MSA revision is: %08x\n", c->msa_id);
2016}
2017
2018void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster)
2019{
2020 /* Ensure the core number fits in the field */
2021 WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >>
2022 MIPS_GLOBALNUMBER_CLUSTER_SHF));
2023
2024 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER;
2025 cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF;
2026}
2027
2028void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core)
2029{
2030 /* Ensure the core number fits in the field */
2031 WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF));
2032
2033 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE;
2034 cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF;
2035}
2036
2037void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe)
2038{
2039 /* Ensure the VP(E) ID fits in the field */
2040 WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF));
2041
2042 /* Ensure we're not using VP(E)s without support */
2043 WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) &&
2044 !IS_ENABLED(CONFIG_CPU_MIPSR6));
2045
2046 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP;
2047 cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF;
2048}