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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for Atmel AT32 and AT91 SPI Controllers
4 *
5 * Copyright (C) 2006 Atmel Corporation
6 */
7
8#include <linux/kernel.h>
9#include <linux/clk.h>
10#include <linux/module.h>
11#include <linux/platform_device.h>
12#include <linux/delay.h>
13#include <linux/dma-mapping.h>
14#include <linux/dmaengine.h>
15#include <linux/err.h>
16#include <linux/interrupt.h>
17#include <linux/spi/spi.h>
18#include <linux/slab.h>
19#include <linux/of.h>
20
21#include <linux/io.h>
22#include <linux/gpio/consumer.h>
23#include <linux/pinctrl/consumer.h>
24#include <linux/pm_runtime.h>
25#include <trace/events/spi.h>
26
27/* SPI register offsets */
28#define SPI_CR 0x0000
29#define SPI_MR 0x0004
30#define SPI_RDR 0x0008
31#define SPI_TDR 0x000c
32#define SPI_SR 0x0010
33#define SPI_IER 0x0014
34#define SPI_IDR 0x0018
35#define SPI_IMR 0x001c
36#define SPI_CSR0 0x0030
37#define SPI_CSR1 0x0034
38#define SPI_CSR2 0x0038
39#define SPI_CSR3 0x003c
40#define SPI_FMR 0x0040
41#define SPI_FLR 0x0044
42#define SPI_VERSION 0x00fc
43#define SPI_RPR 0x0100
44#define SPI_RCR 0x0104
45#define SPI_TPR 0x0108
46#define SPI_TCR 0x010c
47#define SPI_RNPR 0x0110
48#define SPI_RNCR 0x0114
49#define SPI_TNPR 0x0118
50#define SPI_TNCR 0x011c
51#define SPI_PTCR 0x0120
52#define SPI_PTSR 0x0124
53
54/* Bitfields in CR */
55#define SPI_SPIEN_OFFSET 0
56#define SPI_SPIEN_SIZE 1
57#define SPI_SPIDIS_OFFSET 1
58#define SPI_SPIDIS_SIZE 1
59#define SPI_SWRST_OFFSET 7
60#define SPI_SWRST_SIZE 1
61#define SPI_LASTXFER_OFFSET 24
62#define SPI_LASTXFER_SIZE 1
63#define SPI_TXFCLR_OFFSET 16
64#define SPI_TXFCLR_SIZE 1
65#define SPI_RXFCLR_OFFSET 17
66#define SPI_RXFCLR_SIZE 1
67#define SPI_FIFOEN_OFFSET 30
68#define SPI_FIFOEN_SIZE 1
69#define SPI_FIFODIS_OFFSET 31
70#define SPI_FIFODIS_SIZE 1
71
72/* Bitfields in MR */
73#define SPI_MSTR_OFFSET 0
74#define SPI_MSTR_SIZE 1
75#define SPI_PS_OFFSET 1
76#define SPI_PS_SIZE 1
77#define SPI_PCSDEC_OFFSET 2
78#define SPI_PCSDEC_SIZE 1
79#define SPI_FDIV_OFFSET 3
80#define SPI_FDIV_SIZE 1
81#define SPI_MODFDIS_OFFSET 4
82#define SPI_MODFDIS_SIZE 1
83#define SPI_WDRBT_OFFSET 5
84#define SPI_WDRBT_SIZE 1
85#define SPI_LLB_OFFSET 7
86#define SPI_LLB_SIZE 1
87#define SPI_PCS_OFFSET 16
88#define SPI_PCS_SIZE 4
89#define SPI_DLYBCS_OFFSET 24
90#define SPI_DLYBCS_SIZE 8
91
92/* Bitfields in RDR */
93#define SPI_RD_OFFSET 0
94#define SPI_RD_SIZE 16
95
96/* Bitfields in TDR */
97#define SPI_TD_OFFSET 0
98#define SPI_TD_SIZE 16
99
100/* Bitfields in SR */
101#define SPI_RDRF_OFFSET 0
102#define SPI_RDRF_SIZE 1
103#define SPI_TDRE_OFFSET 1
104#define SPI_TDRE_SIZE 1
105#define SPI_MODF_OFFSET 2
106#define SPI_MODF_SIZE 1
107#define SPI_OVRES_OFFSET 3
108#define SPI_OVRES_SIZE 1
109#define SPI_ENDRX_OFFSET 4
110#define SPI_ENDRX_SIZE 1
111#define SPI_ENDTX_OFFSET 5
112#define SPI_ENDTX_SIZE 1
113#define SPI_RXBUFF_OFFSET 6
114#define SPI_RXBUFF_SIZE 1
115#define SPI_TXBUFE_OFFSET 7
116#define SPI_TXBUFE_SIZE 1
117#define SPI_NSSR_OFFSET 8
118#define SPI_NSSR_SIZE 1
119#define SPI_TXEMPTY_OFFSET 9
120#define SPI_TXEMPTY_SIZE 1
121#define SPI_SPIENS_OFFSET 16
122#define SPI_SPIENS_SIZE 1
123#define SPI_TXFEF_OFFSET 24
124#define SPI_TXFEF_SIZE 1
125#define SPI_TXFFF_OFFSET 25
126#define SPI_TXFFF_SIZE 1
127#define SPI_TXFTHF_OFFSET 26
128#define SPI_TXFTHF_SIZE 1
129#define SPI_RXFEF_OFFSET 27
130#define SPI_RXFEF_SIZE 1
131#define SPI_RXFFF_OFFSET 28
132#define SPI_RXFFF_SIZE 1
133#define SPI_RXFTHF_OFFSET 29
134#define SPI_RXFTHF_SIZE 1
135#define SPI_TXFPTEF_OFFSET 30
136#define SPI_TXFPTEF_SIZE 1
137#define SPI_RXFPTEF_OFFSET 31
138#define SPI_RXFPTEF_SIZE 1
139
140/* Bitfields in CSR0 */
141#define SPI_CPOL_OFFSET 0
142#define SPI_CPOL_SIZE 1
143#define SPI_NCPHA_OFFSET 1
144#define SPI_NCPHA_SIZE 1
145#define SPI_CSAAT_OFFSET 3
146#define SPI_CSAAT_SIZE 1
147#define SPI_BITS_OFFSET 4
148#define SPI_BITS_SIZE 4
149#define SPI_SCBR_OFFSET 8
150#define SPI_SCBR_SIZE 8
151#define SPI_DLYBS_OFFSET 16
152#define SPI_DLYBS_SIZE 8
153#define SPI_DLYBCT_OFFSET 24
154#define SPI_DLYBCT_SIZE 8
155
156/* Bitfields in RCR */
157#define SPI_RXCTR_OFFSET 0
158#define SPI_RXCTR_SIZE 16
159
160/* Bitfields in TCR */
161#define SPI_TXCTR_OFFSET 0
162#define SPI_TXCTR_SIZE 16
163
164/* Bitfields in RNCR */
165#define SPI_RXNCR_OFFSET 0
166#define SPI_RXNCR_SIZE 16
167
168/* Bitfields in TNCR */
169#define SPI_TXNCR_OFFSET 0
170#define SPI_TXNCR_SIZE 16
171
172/* Bitfields in PTCR */
173#define SPI_RXTEN_OFFSET 0
174#define SPI_RXTEN_SIZE 1
175#define SPI_RXTDIS_OFFSET 1
176#define SPI_RXTDIS_SIZE 1
177#define SPI_TXTEN_OFFSET 8
178#define SPI_TXTEN_SIZE 1
179#define SPI_TXTDIS_OFFSET 9
180#define SPI_TXTDIS_SIZE 1
181
182/* Bitfields in FMR */
183#define SPI_TXRDYM_OFFSET 0
184#define SPI_TXRDYM_SIZE 2
185#define SPI_RXRDYM_OFFSET 4
186#define SPI_RXRDYM_SIZE 2
187#define SPI_TXFTHRES_OFFSET 16
188#define SPI_TXFTHRES_SIZE 6
189#define SPI_RXFTHRES_OFFSET 24
190#define SPI_RXFTHRES_SIZE 6
191
192/* Bitfields in FLR */
193#define SPI_TXFL_OFFSET 0
194#define SPI_TXFL_SIZE 6
195#define SPI_RXFL_OFFSET 16
196#define SPI_RXFL_SIZE 6
197
198/* Constants for BITS */
199#define SPI_BITS_8_BPT 0
200#define SPI_BITS_9_BPT 1
201#define SPI_BITS_10_BPT 2
202#define SPI_BITS_11_BPT 3
203#define SPI_BITS_12_BPT 4
204#define SPI_BITS_13_BPT 5
205#define SPI_BITS_14_BPT 6
206#define SPI_BITS_15_BPT 7
207#define SPI_BITS_16_BPT 8
208#define SPI_ONE_DATA 0
209#define SPI_TWO_DATA 1
210#define SPI_FOUR_DATA 2
211
212/* Bit manipulation macros */
213#define SPI_BIT(name) \
214 (1 << SPI_##name##_OFFSET)
215#define SPI_BF(name, value) \
216 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
217#define SPI_BFEXT(name, value) \
218 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
219#define SPI_BFINS(name, value, old) \
220 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
221 | SPI_BF(name, value))
222
223/* Register access macros */
224#define spi_readl(port, reg) \
225 readl_relaxed((port)->regs + SPI_##reg)
226#define spi_writel(port, reg, value) \
227 writel_relaxed((value), (port)->regs + SPI_##reg)
228#define spi_writew(port, reg, value) \
229 writew_relaxed((value), (port)->regs + SPI_##reg)
230
231/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
232 * cache operations; better heuristics consider wordsize and bitrate.
233 */
234#define DMA_MIN_BYTES 16
235
236#define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
237
238#define AUTOSUSPEND_TIMEOUT 2000
239
240struct atmel_spi_caps {
241 bool is_spi2;
242 bool has_wdrbt;
243 bool has_dma_support;
244 bool has_pdc_support;
245};
246
247/*
248 * The core SPI transfer engine just talks to a register bank to set up
249 * DMA transfers; transfer queue progress is driven by IRQs. The clock
250 * framework provides the base clock, subdivided for each spi_device.
251 */
252struct atmel_spi {
253 spinlock_t lock;
254 unsigned long flags;
255
256 phys_addr_t phybase;
257 void __iomem *regs;
258 int irq;
259 struct clk *clk;
260 struct platform_device *pdev;
261 unsigned long spi_clk;
262
263 struct spi_transfer *current_transfer;
264 int current_remaining_bytes;
265 int done_status;
266 dma_addr_t dma_addr_rx_bbuf;
267 dma_addr_t dma_addr_tx_bbuf;
268 void *addr_rx_bbuf;
269 void *addr_tx_bbuf;
270
271 struct completion xfer_completion;
272
273 struct atmel_spi_caps caps;
274
275 bool use_dma;
276 bool use_pdc;
277
278 bool keep_cs;
279
280 u32 fifo_size;
281 u8 native_cs_free;
282 u8 native_cs_for_gpio;
283};
284
285/* Controller-specific per-slave state */
286struct atmel_spi_device {
287 u32 csr;
288};
289
290#define SPI_MAX_DMA_XFER 65535 /* true for both PDC and DMA */
291#define INVALID_DMA_ADDRESS 0xffffffff
292
293/*
294 * Version 2 of the SPI controller has
295 * - CR.LASTXFER
296 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
297 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
298 * - SPI_CSRx.CSAAT
299 * - SPI_CSRx.SBCR allows faster clocking
300 */
301static bool atmel_spi_is_v2(struct atmel_spi *as)
302{
303 return as->caps.is_spi2;
304}
305
306/*
307 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
308 * they assume that spi slave device state will not change on deselect, so
309 * that automagic deselection is OK. ("NPCSx rises if no data is to be
310 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
311 * controllers have CSAAT and friends.
312 *
313 * Even controller newer than ar91rm9200, using GPIOs can make sens as
314 * it lets us support active-high chipselects despite the controller's
315 * belief that only active-low devices/systems exists.
316 *
317 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
318 * right when driven with GPIO. ("Mode Fault does not allow more than one
319 * Master on Chip Select 0.") No workaround exists for that ... so for
320 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
321 * and (c) will trigger that first erratum in some cases.
322 */
323
324static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
325{
326 struct atmel_spi_device *asd = spi->controller_state;
327 int chip_select;
328 u32 mr;
329
330 if (spi->cs_gpiod)
331 chip_select = as->native_cs_for_gpio;
332 else
333 chip_select = spi->chip_select;
334
335 if (atmel_spi_is_v2(as)) {
336 spi_writel(as, CSR0 + 4 * chip_select, asd->csr);
337 /* For the low SPI version, there is a issue that PDC transfer
338 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
339 */
340 spi_writel(as, CSR0, asd->csr);
341 if (as->caps.has_wdrbt) {
342 spi_writel(as, MR,
343 SPI_BF(PCS, ~(0x01 << chip_select))
344 | SPI_BIT(WDRBT)
345 | SPI_BIT(MODFDIS)
346 | SPI_BIT(MSTR));
347 } else {
348 spi_writel(as, MR,
349 SPI_BF(PCS, ~(0x01 << chip_select))
350 | SPI_BIT(MODFDIS)
351 | SPI_BIT(MSTR));
352 }
353
354 mr = spi_readl(as, MR);
355 } else {
356 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
357 int i;
358 u32 csr;
359
360 /* Make sure clock polarity is correct */
361 for (i = 0; i < spi->master->num_chipselect; i++) {
362 csr = spi_readl(as, CSR0 + 4 * i);
363 if ((csr ^ cpol) & SPI_BIT(CPOL))
364 spi_writel(as, CSR0 + 4 * i,
365 csr ^ SPI_BIT(CPOL));
366 }
367
368 mr = spi_readl(as, MR);
369 mr = SPI_BFINS(PCS, ~(1 << chip_select), mr);
370 spi_writel(as, MR, mr);
371 }
372
373 dev_dbg(&spi->dev, "activate NPCS, mr %08x\n", mr);
374}
375
376static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
377{
378 int chip_select;
379 u32 mr;
380
381 if (spi->cs_gpiod)
382 chip_select = as->native_cs_for_gpio;
383 else
384 chip_select = spi->chip_select;
385
386 /* only deactivate *this* device; sometimes transfers to
387 * another device may be active when this routine is called.
388 */
389 mr = spi_readl(as, MR);
390 if (~SPI_BFEXT(PCS, mr) & (1 << chip_select)) {
391 mr = SPI_BFINS(PCS, 0xf, mr);
392 spi_writel(as, MR, mr);
393 }
394
395 dev_dbg(&spi->dev, "DEactivate NPCS, mr %08x\n", mr);
396
397 if (!spi->cs_gpiod)
398 spi_writel(as, CR, SPI_BIT(LASTXFER));
399}
400
401static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
402{
403 spin_lock_irqsave(&as->lock, as->flags);
404}
405
406static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
407{
408 spin_unlock_irqrestore(&as->lock, as->flags);
409}
410
411static inline bool atmel_spi_is_vmalloc_xfer(struct spi_transfer *xfer)
412{
413 return is_vmalloc_addr(xfer->tx_buf) || is_vmalloc_addr(xfer->rx_buf);
414}
415
416static inline bool atmel_spi_use_dma(struct atmel_spi *as,
417 struct spi_transfer *xfer)
418{
419 return as->use_dma && xfer->len >= DMA_MIN_BYTES;
420}
421
422static bool atmel_spi_can_dma(struct spi_master *master,
423 struct spi_device *spi,
424 struct spi_transfer *xfer)
425{
426 struct atmel_spi *as = spi_master_get_devdata(master);
427
428 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5))
429 return atmel_spi_use_dma(as, xfer) &&
430 !atmel_spi_is_vmalloc_xfer(xfer);
431 else
432 return atmel_spi_use_dma(as, xfer);
433
434}
435
436static int atmel_spi_dma_slave_config(struct atmel_spi *as, u8 bits_per_word)
437{
438 struct spi_master *master = platform_get_drvdata(as->pdev);
439 struct dma_slave_config slave_config;
440 int err = 0;
441
442 if (bits_per_word > 8) {
443 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
444 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
445 } else {
446 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
447 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
448 }
449
450 slave_config.dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
451 slave_config.src_addr = (dma_addr_t)as->phybase + SPI_RDR;
452 slave_config.src_maxburst = 1;
453 slave_config.dst_maxburst = 1;
454 slave_config.device_fc = false;
455
456 /*
457 * This driver uses fixed peripheral select mode (PS bit set to '0' in
458 * the Mode Register).
459 * So according to the datasheet, when FIFOs are available (and
460 * enabled), the Transmit FIFO operates in Multiple Data Mode.
461 * In this mode, up to 2 data, not 4, can be written into the Transmit
462 * Data Register in a single access.
463 * However, the first data has to be written into the lowest 16 bits and
464 * the second data into the highest 16 bits of the Transmit
465 * Data Register. For 8bit data (the most frequent case), it would
466 * require to rework tx_buf so each data would actually fit 16 bits.
467 * So we'd rather write only one data at the time. Hence the transmit
468 * path works the same whether FIFOs are available (and enabled) or not.
469 */
470 if (dmaengine_slave_config(master->dma_tx, &slave_config)) {
471 dev_err(&as->pdev->dev,
472 "failed to configure tx dma channel\n");
473 err = -EINVAL;
474 }
475
476 /*
477 * This driver configures the spi controller for master mode (MSTR bit
478 * set to '1' in the Mode Register).
479 * So according to the datasheet, when FIFOs are available (and
480 * enabled), the Receive FIFO operates in Single Data Mode.
481 * So the receive path works the same whether FIFOs are available (and
482 * enabled) or not.
483 */
484 if (dmaengine_slave_config(master->dma_rx, &slave_config)) {
485 dev_err(&as->pdev->dev,
486 "failed to configure rx dma channel\n");
487 err = -EINVAL;
488 }
489
490 return err;
491}
492
493static int atmel_spi_configure_dma(struct spi_master *master,
494 struct atmel_spi *as)
495{
496 struct device *dev = &as->pdev->dev;
497 int err;
498
499 master->dma_tx = dma_request_chan(dev, "tx");
500 if (IS_ERR(master->dma_tx)) {
501 err = PTR_ERR(master->dma_tx);
502 dev_dbg(dev, "No TX DMA channel, DMA is disabled\n");
503 goto error_clear;
504 }
505
506 master->dma_rx = dma_request_chan(dev, "rx");
507 if (IS_ERR(master->dma_rx)) {
508 err = PTR_ERR(master->dma_rx);
509 /*
510 * No reason to check EPROBE_DEFER here since we have already
511 * requested tx channel.
512 */
513 dev_dbg(dev, "No RX DMA channel, DMA is disabled\n");
514 goto error;
515 }
516
517 err = atmel_spi_dma_slave_config(as, 8);
518 if (err)
519 goto error;
520
521 dev_info(&as->pdev->dev,
522 "Using %s (tx) and %s (rx) for DMA transfers\n",
523 dma_chan_name(master->dma_tx),
524 dma_chan_name(master->dma_rx));
525
526 return 0;
527error:
528 if (!IS_ERR(master->dma_rx))
529 dma_release_channel(master->dma_rx);
530 if (!IS_ERR(master->dma_tx))
531 dma_release_channel(master->dma_tx);
532error_clear:
533 master->dma_tx = master->dma_rx = NULL;
534 return err;
535}
536
537static void atmel_spi_stop_dma(struct spi_master *master)
538{
539 if (master->dma_rx)
540 dmaengine_terminate_all(master->dma_rx);
541 if (master->dma_tx)
542 dmaengine_terminate_all(master->dma_tx);
543}
544
545static void atmel_spi_release_dma(struct spi_master *master)
546{
547 if (master->dma_rx) {
548 dma_release_channel(master->dma_rx);
549 master->dma_rx = NULL;
550 }
551 if (master->dma_tx) {
552 dma_release_channel(master->dma_tx);
553 master->dma_tx = NULL;
554 }
555}
556
557/* This function is called by the DMA driver from tasklet context */
558static void dma_callback(void *data)
559{
560 struct spi_master *master = data;
561 struct atmel_spi *as = spi_master_get_devdata(master);
562
563 if (is_vmalloc_addr(as->current_transfer->rx_buf) &&
564 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
565 memcpy(as->current_transfer->rx_buf, as->addr_rx_bbuf,
566 as->current_transfer->len);
567 }
568 complete(&as->xfer_completion);
569}
570
571/*
572 * Next transfer using PIO without FIFO.
573 */
574static void atmel_spi_next_xfer_single(struct spi_master *master,
575 struct spi_transfer *xfer)
576{
577 struct atmel_spi *as = spi_master_get_devdata(master);
578 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
579
580 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
581
582 /* Make sure data is not remaining in RDR */
583 spi_readl(as, RDR);
584 while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
585 spi_readl(as, RDR);
586 cpu_relax();
587 }
588
589 if (xfer->bits_per_word > 8)
590 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
591 else
592 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
593
594 dev_dbg(master->dev.parent,
595 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
596 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
597 xfer->bits_per_word);
598
599 /* Enable relevant interrupts */
600 spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
601}
602
603/*
604 * Next transfer using PIO with FIFO.
605 */
606static void atmel_spi_next_xfer_fifo(struct spi_master *master,
607 struct spi_transfer *xfer)
608{
609 struct atmel_spi *as = spi_master_get_devdata(master);
610 u32 current_remaining_data, num_data;
611 u32 offset = xfer->len - as->current_remaining_bytes;
612 const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset);
613 const u8 *bytes = (const u8 *)((u8 *)xfer->tx_buf + offset);
614 u16 td0, td1;
615 u32 fifomr;
616
617 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_fifo\n");
618
619 /* Compute the number of data to transfer in the current iteration */
620 current_remaining_data = ((xfer->bits_per_word > 8) ?
621 ((u32)as->current_remaining_bytes >> 1) :
622 (u32)as->current_remaining_bytes);
623 num_data = min(current_remaining_data, as->fifo_size);
624
625 /* Flush RX and TX FIFOs */
626 spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR));
627 while (spi_readl(as, FLR))
628 cpu_relax();
629
630 /* Set RX FIFO Threshold to the number of data to transfer */
631 fifomr = spi_readl(as, FMR);
632 spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr));
633
634 /* Clear FIFO flags in the Status Register, especially RXFTHF */
635 (void)spi_readl(as, SR);
636
637 /* Fill TX FIFO */
638 while (num_data >= 2) {
639 if (xfer->bits_per_word > 8) {
640 td0 = *words++;
641 td1 = *words++;
642 } else {
643 td0 = *bytes++;
644 td1 = *bytes++;
645 }
646
647 spi_writel(as, TDR, (td1 << 16) | td0);
648 num_data -= 2;
649 }
650
651 if (num_data) {
652 if (xfer->bits_per_word > 8)
653 td0 = *words++;
654 else
655 td0 = *bytes++;
656
657 spi_writew(as, TDR, td0);
658 num_data--;
659 }
660
661 dev_dbg(master->dev.parent,
662 " start fifo xfer %p: len %u tx %p rx %p bitpw %d\n",
663 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
664 xfer->bits_per_word);
665
666 /*
667 * Enable RX FIFO Threshold Flag interrupt to be notified about
668 * transfer completion.
669 */
670 spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES));
671}
672
673/*
674 * Next transfer using PIO.
675 */
676static void atmel_spi_next_xfer_pio(struct spi_master *master,
677 struct spi_transfer *xfer)
678{
679 struct atmel_spi *as = spi_master_get_devdata(master);
680
681 if (as->fifo_size)
682 atmel_spi_next_xfer_fifo(master, xfer);
683 else
684 atmel_spi_next_xfer_single(master, xfer);
685}
686
687/*
688 * Submit next transfer for DMA.
689 */
690static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
691 struct spi_transfer *xfer,
692 u32 *plen)
693{
694 struct atmel_spi *as = spi_master_get_devdata(master);
695 struct dma_chan *rxchan = master->dma_rx;
696 struct dma_chan *txchan = master->dma_tx;
697 struct dma_async_tx_descriptor *rxdesc;
698 struct dma_async_tx_descriptor *txdesc;
699 dma_cookie_t cookie;
700
701 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
702
703 /* Check that the channels are available */
704 if (!rxchan || !txchan)
705 return -ENODEV;
706
707
708 *plen = xfer->len;
709
710 if (atmel_spi_dma_slave_config(as, xfer->bits_per_word))
711 goto err_exit;
712
713 /* Send both scatterlists */
714 if (atmel_spi_is_vmalloc_xfer(xfer) &&
715 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
716 rxdesc = dmaengine_prep_slave_single(rxchan,
717 as->dma_addr_rx_bbuf,
718 xfer->len,
719 DMA_DEV_TO_MEM,
720 DMA_PREP_INTERRUPT |
721 DMA_CTRL_ACK);
722 } else {
723 rxdesc = dmaengine_prep_slave_sg(rxchan,
724 xfer->rx_sg.sgl,
725 xfer->rx_sg.nents,
726 DMA_DEV_TO_MEM,
727 DMA_PREP_INTERRUPT |
728 DMA_CTRL_ACK);
729 }
730 if (!rxdesc)
731 goto err_dma;
732
733 if (atmel_spi_is_vmalloc_xfer(xfer) &&
734 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
735 memcpy(as->addr_tx_bbuf, xfer->tx_buf, xfer->len);
736 txdesc = dmaengine_prep_slave_single(txchan,
737 as->dma_addr_tx_bbuf,
738 xfer->len, DMA_MEM_TO_DEV,
739 DMA_PREP_INTERRUPT |
740 DMA_CTRL_ACK);
741 } else {
742 txdesc = dmaengine_prep_slave_sg(txchan,
743 xfer->tx_sg.sgl,
744 xfer->tx_sg.nents,
745 DMA_MEM_TO_DEV,
746 DMA_PREP_INTERRUPT |
747 DMA_CTRL_ACK);
748 }
749 if (!txdesc)
750 goto err_dma;
751
752 dev_dbg(master->dev.parent,
753 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
754 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
755 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
756
757 /* Enable relevant interrupts */
758 spi_writel(as, IER, SPI_BIT(OVRES));
759
760 /* Put the callback on the RX transfer only, that should finish last */
761 rxdesc->callback = dma_callback;
762 rxdesc->callback_param = master;
763
764 /* Submit and fire RX and TX with TX last so we're ready to read! */
765 cookie = rxdesc->tx_submit(rxdesc);
766 if (dma_submit_error(cookie))
767 goto err_dma;
768 cookie = txdesc->tx_submit(txdesc);
769 if (dma_submit_error(cookie))
770 goto err_dma;
771 rxchan->device->device_issue_pending(rxchan);
772 txchan->device->device_issue_pending(txchan);
773
774 return 0;
775
776err_dma:
777 spi_writel(as, IDR, SPI_BIT(OVRES));
778 atmel_spi_stop_dma(master);
779err_exit:
780 return -ENOMEM;
781}
782
783static void atmel_spi_next_xfer_data(struct spi_master *master,
784 struct spi_transfer *xfer,
785 dma_addr_t *tx_dma,
786 dma_addr_t *rx_dma,
787 u32 *plen)
788{
789 *rx_dma = xfer->rx_dma + xfer->len - *plen;
790 *tx_dma = xfer->tx_dma + xfer->len - *plen;
791 if (*plen > master->max_dma_len)
792 *plen = master->max_dma_len;
793}
794
795static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
796 struct spi_device *spi,
797 struct spi_transfer *xfer)
798{
799 u32 scbr, csr;
800 unsigned long bus_hz;
801 int chip_select;
802
803 if (spi->cs_gpiod)
804 chip_select = as->native_cs_for_gpio;
805 else
806 chip_select = spi->chip_select;
807
808 /* v1 chips start out at half the peripheral bus speed. */
809 bus_hz = as->spi_clk;
810 if (!atmel_spi_is_v2(as))
811 bus_hz /= 2;
812
813 /*
814 * Calculate the lowest divider that satisfies the
815 * constraint, assuming div32/fdiv/mbz == 0.
816 */
817 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
818
819 /*
820 * If the resulting divider doesn't fit into the
821 * register bitfield, we can't satisfy the constraint.
822 */
823 if (scbr >= (1 << SPI_SCBR_SIZE)) {
824 dev_err(&spi->dev,
825 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
826 xfer->speed_hz, scbr, bus_hz/255);
827 return -EINVAL;
828 }
829 if (scbr == 0) {
830 dev_err(&spi->dev,
831 "setup: %d Hz too high, scbr %u; max %ld Hz\n",
832 xfer->speed_hz, scbr, bus_hz);
833 return -EINVAL;
834 }
835 csr = spi_readl(as, CSR0 + 4 * chip_select);
836 csr = SPI_BFINS(SCBR, scbr, csr);
837 spi_writel(as, CSR0 + 4 * chip_select, csr);
838 xfer->effective_speed_hz = bus_hz / scbr;
839
840 return 0;
841}
842
843/*
844 * Submit next transfer for PDC.
845 * lock is held, spi irq is blocked
846 */
847static void atmel_spi_pdc_next_xfer(struct spi_master *master,
848 struct spi_transfer *xfer)
849{
850 struct atmel_spi *as = spi_master_get_devdata(master);
851 u32 len;
852 dma_addr_t tx_dma, rx_dma;
853
854 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
855
856 len = as->current_remaining_bytes;
857 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
858 as->current_remaining_bytes -= len;
859
860 spi_writel(as, RPR, rx_dma);
861 spi_writel(as, TPR, tx_dma);
862
863 if (xfer->bits_per_word > 8)
864 len >>= 1;
865 spi_writel(as, RCR, len);
866 spi_writel(as, TCR, len);
867
868 dev_dbg(&master->dev,
869 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
870 xfer, xfer->len, xfer->tx_buf,
871 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
872 (unsigned long long)xfer->rx_dma);
873
874 if (as->current_remaining_bytes) {
875 len = as->current_remaining_bytes;
876 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
877 as->current_remaining_bytes -= len;
878
879 spi_writel(as, RNPR, rx_dma);
880 spi_writel(as, TNPR, tx_dma);
881
882 if (xfer->bits_per_word > 8)
883 len >>= 1;
884 spi_writel(as, RNCR, len);
885 spi_writel(as, TNCR, len);
886
887 dev_dbg(&master->dev,
888 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
889 xfer, xfer->len, xfer->tx_buf,
890 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
891 (unsigned long long)xfer->rx_dma);
892 }
893
894 /* REVISIT: We're waiting for RXBUFF before we start the next
895 * transfer because we need to handle some difficult timing
896 * issues otherwise. If we wait for TXBUFE in one transfer and
897 * then starts waiting for RXBUFF in the next, it's difficult
898 * to tell the difference between the RXBUFF interrupt we're
899 * actually waiting for and the RXBUFF interrupt of the
900 * previous transfer.
901 *
902 * It should be doable, though. Just not now...
903 */
904 spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
905 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
906}
907
908/*
909 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
910 * - The buffer is either valid for CPU access, else NULL
911 * - If the buffer is valid, so is its DMA address
912 *
913 * This driver manages the dma address unless message->is_dma_mapped.
914 */
915static int
916atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
917{
918 struct device *dev = &as->pdev->dev;
919
920 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
921 if (xfer->tx_buf) {
922 /* tx_buf is a const void* where we need a void * for the dma
923 * mapping */
924 void *nonconst_tx = (void *)xfer->tx_buf;
925
926 xfer->tx_dma = dma_map_single(dev,
927 nonconst_tx, xfer->len,
928 DMA_TO_DEVICE);
929 if (dma_mapping_error(dev, xfer->tx_dma))
930 return -ENOMEM;
931 }
932 if (xfer->rx_buf) {
933 xfer->rx_dma = dma_map_single(dev,
934 xfer->rx_buf, xfer->len,
935 DMA_FROM_DEVICE);
936 if (dma_mapping_error(dev, xfer->rx_dma)) {
937 if (xfer->tx_buf)
938 dma_unmap_single(dev,
939 xfer->tx_dma, xfer->len,
940 DMA_TO_DEVICE);
941 return -ENOMEM;
942 }
943 }
944 return 0;
945}
946
947static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
948 struct spi_transfer *xfer)
949{
950 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
951 dma_unmap_single(master->dev.parent, xfer->tx_dma,
952 xfer->len, DMA_TO_DEVICE);
953 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
954 dma_unmap_single(master->dev.parent, xfer->rx_dma,
955 xfer->len, DMA_FROM_DEVICE);
956}
957
958static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
959{
960 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
961}
962
963static void
964atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer)
965{
966 u8 *rxp;
967 u16 *rxp16;
968 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
969
970 if (xfer->bits_per_word > 8) {
971 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
972 *rxp16 = spi_readl(as, RDR);
973 } else {
974 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
975 *rxp = spi_readl(as, RDR);
976 }
977 if (xfer->bits_per_word > 8) {
978 if (as->current_remaining_bytes > 2)
979 as->current_remaining_bytes -= 2;
980 else
981 as->current_remaining_bytes = 0;
982 } else {
983 as->current_remaining_bytes--;
984 }
985}
986
987static void
988atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer)
989{
990 u32 fifolr = spi_readl(as, FLR);
991 u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr);
992 u32 offset = xfer->len - as->current_remaining_bytes;
993 u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset);
994 u8 *bytes = (u8 *)((u8 *)xfer->rx_buf + offset);
995 u16 rd; /* RD field is the lowest 16 bits of RDR */
996
997 /* Update the number of remaining bytes to transfer */
998 num_bytes = ((xfer->bits_per_word > 8) ?
999 (num_data << 1) :
1000 num_data);
1001
1002 if (as->current_remaining_bytes > num_bytes)
1003 as->current_remaining_bytes -= num_bytes;
1004 else
1005 as->current_remaining_bytes = 0;
1006
1007 /* Handle odd number of bytes when data are more than 8bit width */
1008 if (xfer->bits_per_word > 8)
1009 as->current_remaining_bytes &= ~0x1;
1010
1011 /* Read data */
1012 while (num_data) {
1013 rd = spi_readl(as, RDR);
1014 if (xfer->bits_per_word > 8)
1015 *words++ = rd;
1016 else
1017 *bytes++ = rd;
1018 num_data--;
1019 }
1020}
1021
1022/* Called from IRQ
1023 *
1024 * Must update "current_remaining_bytes" to keep track of data
1025 * to transfer.
1026 */
1027static void
1028atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
1029{
1030 if (as->fifo_size)
1031 atmel_spi_pump_fifo_data(as, xfer);
1032 else
1033 atmel_spi_pump_single_data(as, xfer);
1034}
1035
1036/* Interrupt
1037 *
1038 */
1039static irqreturn_t
1040atmel_spi_pio_interrupt(int irq, void *dev_id)
1041{
1042 struct spi_master *master = dev_id;
1043 struct atmel_spi *as = spi_master_get_devdata(master);
1044 u32 status, pending, imr;
1045 struct spi_transfer *xfer;
1046 int ret = IRQ_NONE;
1047
1048 imr = spi_readl(as, IMR);
1049 status = spi_readl(as, SR);
1050 pending = status & imr;
1051
1052 if (pending & SPI_BIT(OVRES)) {
1053 ret = IRQ_HANDLED;
1054 spi_writel(as, IDR, SPI_BIT(OVRES));
1055 dev_warn(master->dev.parent, "overrun\n");
1056
1057 /*
1058 * When we get an overrun, we disregard the current
1059 * transfer. Data will not be copied back from any
1060 * bounce buffer and msg->actual_len will not be
1061 * updated with the last xfer.
1062 *
1063 * We will also not process any remaning transfers in
1064 * the message.
1065 */
1066 as->done_status = -EIO;
1067 smp_wmb();
1068
1069 /* Clear any overrun happening while cleaning up */
1070 spi_readl(as, SR);
1071
1072 complete(&as->xfer_completion);
1073
1074 } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) {
1075 atmel_spi_lock(as);
1076
1077 if (as->current_remaining_bytes) {
1078 ret = IRQ_HANDLED;
1079 xfer = as->current_transfer;
1080 atmel_spi_pump_pio_data(as, xfer);
1081 if (!as->current_remaining_bytes)
1082 spi_writel(as, IDR, pending);
1083
1084 complete(&as->xfer_completion);
1085 }
1086
1087 atmel_spi_unlock(as);
1088 } else {
1089 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
1090 ret = IRQ_HANDLED;
1091 spi_writel(as, IDR, pending);
1092 }
1093
1094 return ret;
1095}
1096
1097static irqreturn_t
1098atmel_spi_pdc_interrupt(int irq, void *dev_id)
1099{
1100 struct spi_master *master = dev_id;
1101 struct atmel_spi *as = spi_master_get_devdata(master);
1102 u32 status, pending, imr;
1103 int ret = IRQ_NONE;
1104
1105 imr = spi_readl(as, IMR);
1106 status = spi_readl(as, SR);
1107 pending = status & imr;
1108
1109 if (pending & SPI_BIT(OVRES)) {
1110
1111 ret = IRQ_HANDLED;
1112
1113 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
1114 | SPI_BIT(OVRES)));
1115
1116 /* Clear any overrun happening while cleaning up */
1117 spi_readl(as, SR);
1118
1119 as->done_status = -EIO;
1120
1121 complete(&as->xfer_completion);
1122
1123 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
1124 ret = IRQ_HANDLED;
1125
1126 spi_writel(as, IDR, pending);
1127
1128 complete(&as->xfer_completion);
1129 }
1130
1131 return ret;
1132}
1133
1134static int atmel_word_delay_csr(struct spi_device *spi, struct atmel_spi *as)
1135{
1136 struct spi_delay *delay = &spi->word_delay;
1137 u32 value = delay->value;
1138
1139 switch (delay->unit) {
1140 case SPI_DELAY_UNIT_NSECS:
1141 value /= 1000;
1142 break;
1143 case SPI_DELAY_UNIT_USECS:
1144 break;
1145 default:
1146 return -EINVAL;
1147 }
1148
1149 return (as->spi_clk / 1000000 * value) >> 5;
1150}
1151
1152static void initialize_native_cs_for_gpio(struct atmel_spi *as)
1153{
1154 int i;
1155 struct spi_master *master = platform_get_drvdata(as->pdev);
1156
1157 if (!as->native_cs_free)
1158 return; /* already initialized */
1159
1160 if (!master->cs_gpiods)
1161 return; /* No CS GPIO */
1162
1163 /*
1164 * On the first version of the controller (AT91RM9200), CS0
1165 * can't be used associated with GPIO
1166 */
1167 if (atmel_spi_is_v2(as))
1168 i = 0;
1169 else
1170 i = 1;
1171
1172 for (; i < 4; i++)
1173 if (master->cs_gpiods[i])
1174 as->native_cs_free |= BIT(i);
1175
1176 if (as->native_cs_free)
1177 as->native_cs_for_gpio = ffs(as->native_cs_free);
1178}
1179
1180static int atmel_spi_setup(struct spi_device *spi)
1181{
1182 struct atmel_spi *as;
1183 struct atmel_spi_device *asd;
1184 u32 csr;
1185 unsigned int bits = spi->bits_per_word;
1186 int chip_select;
1187 int word_delay_csr;
1188
1189 as = spi_master_get_devdata(spi->master);
1190
1191 /* see notes above re chipselect */
1192 if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH)) {
1193 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
1194 return -EINVAL;
1195 }
1196
1197 /* Setup() is called during spi_register_controller(aka
1198 * spi_register_master) but after all membmers of the cs_gpiod
1199 * array have been filled, so we can looked for which native
1200 * CS will be free for using with GPIO
1201 */
1202 initialize_native_cs_for_gpio(as);
1203
1204 if (spi->cs_gpiod && as->native_cs_free) {
1205 dev_err(&spi->dev,
1206 "No native CS available to support this GPIO CS\n");
1207 return -EBUSY;
1208 }
1209
1210 if (spi->cs_gpiod)
1211 chip_select = as->native_cs_for_gpio;
1212 else
1213 chip_select = spi->chip_select;
1214
1215 csr = SPI_BF(BITS, bits - 8);
1216 if (spi->mode & SPI_CPOL)
1217 csr |= SPI_BIT(CPOL);
1218 if (!(spi->mode & SPI_CPHA))
1219 csr |= SPI_BIT(NCPHA);
1220
1221 if (!spi->cs_gpiod)
1222 csr |= SPI_BIT(CSAAT);
1223 csr |= SPI_BF(DLYBS, 0);
1224
1225 word_delay_csr = atmel_word_delay_csr(spi, as);
1226 if (word_delay_csr < 0)
1227 return word_delay_csr;
1228
1229 /* DLYBCT adds delays between words. This is useful for slow devices
1230 * that need a bit of time to setup the next transfer.
1231 */
1232 csr |= SPI_BF(DLYBCT, word_delay_csr);
1233
1234 asd = spi->controller_state;
1235 if (!asd) {
1236 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1237 if (!asd)
1238 return -ENOMEM;
1239
1240 spi->controller_state = asd;
1241 }
1242
1243 asd->csr = csr;
1244
1245 dev_dbg(&spi->dev,
1246 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1247 bits, spi->mode, spi->chip_select, csr);
1248
1249 if (!atmel_spi_is_v2(as))
1250 spi_writel(as, CSR0 + 4 * chip_select, csr);
1251
1252 return 0;
1253}
1254
1255static void atmel_spi_set_cs(struct spi_device *spi, bool enable)
1256{
1257 struct atmel_spi *as = spi_master_get_devdata(spi->master);
1258 /* the core doesn't really pass us enable/disable, but CS HIGH vs CS LOW
1259 * since we already have routines for activate/deactivate translate
1260 * high/low to active/inactive
1261 */
1262 enable = (!!(spi->mode & SPI_CS_HIGH) == enable);
1263
1264 if (enable) {
1265 cs_activate(as, spi);
1266 } else {
1267 cs_deactivate(as, spi);
1268 }
1269
1270}
1271
1272static int atmel_spi_one_transfer(struct spi_master *master,
1273 struct spi_device *spi,
1274 struct spi_transfer *xfer)
1275{
1276 struct atmel_spi *as;
1277 u8 bits;
1278 u32 len;
1279 struct atmel_spi_device *asd;
1280 int timeout;
1281 int ret;
1282 unsigned long dma_timeout;
1283
1284 as = spi_master_get_devdata(master);
1285
1286 asd = spi->controller_state;
1287 bits = (asd->csr >> 4) & 0xf;
1288 if (bits != xfer->bits_per_word - 8) {
1289 dev_dbg(&spi->dev,
1290 "you can't yet change bits_per_word in transfers\n");
1291 return -ENOPROTOOPT;
1292 }
1293
1294 /*
1295 * DMA map early, for performance (empties dcache ASAP) and
1296 * better fault reporting.
1297 */
1298 if ((!master->cur_msg->is_dma_mapped)
1299 && as->use_pdc) {
1300 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1301 return -ENOMEM;
1302 }
1303
1304 atmel_spi_set_xfer_speed(as, spi, xfer);
1305
1306 as->done_status = 0;
1307 as->current_transfer = xfer;
1308 as->current_remaining_bytes = xfer->len;
1309 while (as->current_remaining_bytes) {
1310 reinit_completion(&as->xfer_completion);
1311
1312 if (as->use_pdc) {
1313 atmel_spi_lock(as);
1314 atmel_spi_pdc_next_xfer(master, xfer);
1315 atmel_spi_unlock(as);
1316 } else if (atmel_spi_use_dma(as, xfer)) {
1317 len = as->current_remaining_bytes;
1318 ret = atmel_spi_next_xfer_dma_submit(master,
1319 xfer, &len);
1320 if (ret) {
1321 dev_err(&spi->dev,
1322 "unable to use DMA, fallback to PIO\n");
1323 as->done_status = ret;
1324 break;
1325 } else {
1326 as->current_remaining_bytes -= len;
1327 if (as->current_remaining_bytes < 0)
1328 as->current_remaining_bytes = 0;
1329 }
1330 } else {
1331 atmel_spi_lock(as);
1332 atmel_spi_next_xfer_pio(master, xfer);
1333 atmel_spi_unlock(as);
1334 }
1335
1336 dma_timeout = wait_for_completion_timeout(&as->xfer_completion,
1337 SPI_DMA_TIMEOUT);
1338 if (WARN_ON(dma_timeout == 0)) {
1339 dev_err(&spi->dev, "spi transfer timeout\n");
1340 as->done_status = -EIO;
1341 }
1342
1343 if (as->done_status)
1344 break;
1345 }
1346
1347 if (as->done_status) {
1348 if (as->use_pdc) {
1349 dev_warn(master->dev.parent,
1350 "overrun (%u/%u remaining)\n",
1351 spi_readl(as, TCR), spi_readl(as, RCR));
1352
1353 /*
1354 * Clean up DMA registers and make sure the data
1355 * registers are empty.
1356 */
1357 spi_writel(as, RNCR, 0);
1358 spi_writel(as, TNCR, 0);
1359 spi_writel(as, RCR, 0);
1360 spi_writel(as, TCR, 0);
1361 for (timeout = 1000; timeout; timeout--)
1362 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1363 break;
1364 if (!timeout)
1365 dev_warn(master->dev.parent,
1366 "timeout waiting for TXEMPTY");
1367 while (spi_readl(as, SR) & SPI_BIT(RDRF))
1368 spi_readl(as, RDR);
1369
1370 /* Clear any overrun happening while cleaning up */
1371 spi_readl(as, SR);
1372
1373 } else if (atmel_spi_use_dma(as, xfer)) {
1374 atmel_spi_stop_dma(master);
1375 }
1376 }
1377
1378 if (!master->cur_msg->is_dma_mapped
1379 && as->use_pdc)
1380 atmel_spi_dma_unmap_xfer(master, xfer);
1381
1382 if (as->use_pdc)
1383 atmel_spi_disable_pdc_transfer(as);
1384
1385 return as->done_status;
1386}
1387
1388static void atmel_spi_cleanup(struct spi_device *spi)
1389{
1390 struct atmel_spi_device *asd = spi->controller_state;
1391
1392 if (!asd)
1393 return;
1394
1395 spi->controller_state = NULL;
1396 kfree(asd);
1397}
1398
1399static inline unsigned int atmel_get_version(struct atmel_spi *as)
1400{
1401 return spi_readl(as, VERSION) & 0x00000fff;
1402}
1403
1404static void atmel_get_caps(struct atmel_spi *as)
1405{
1406 unsigned int version;
1407
1408 version = atmel_get_version(as);
1409
1410 as->caps.is_spi2 = version > 0x121;
1411 as->caps.has_wdrbt = version >= 0x210;
1412 as->caps.has_dma_support = version >= 0x212;
1413 as->caps.has_pdc_support = version < 0x212;
1414}
1415
1416static void atmel_spi_init(struct atmel_spi *as)
1417{
1418 spi_writel(as, CR, SPI_BIT(SWRST));
1419 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1420
1421 /* It is recommended to enable FIFOs first thing after reset */
1422 if (as->fifo_size)
1423 spi_writel(as, CR, SPI_BIT(FIFOEN));
1424
1425 if (as->caps.has_wdrbt) {
1426 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1427 | SPI_BIT(MSTR));
1428 } else {
1429 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1430 }
1431
1432 if (as->use_pdc)
1433 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1434 spi_writel(as, CR, SPI_BIT(SPIEN));
1435}
1436
1437static int atmel_spi_probe(struct platform_device *pdev)
1438{
1439 struct resource *regs;
1440 int irq;
1441 struct clk *clk;
1442 int ret;
1443 struct spi_master *master;
1444 struct atmel_spi *as;
1445
1446 /* Select default pin state */
1447 pinctrl_pm_select_default_state(&pdev->dev);
1448
1449 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1450 if (!regs)
1451 return -ENXIO;
1452
1453 irq = platform_get_irq(pdev, 0);
1454 if (irq < 0)
1455 return irq;
1456
1457 clk = devm_clk_get(&pdev->dev, "spi_clk");
1458 if (IS_ERR(clk))
1459 return PTR_ERR(clk);
1460
1461 /* setup spi core then atmel-specific driver state */
1462 master = spi_alloc_master(&pdev->dev, sizeof(*as));
1463 if (!master)
1464 return -ENOMEM;
1465
1466 /* the spi->mode bits understood by this driver: */
1467 master->use_gpio_descriptors = true;
1468 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1469 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1470 master->dev.of_node = pdev->dev.of_node;
1471 master->bus_num = pdev->id;
1472 master->num_chipselect = 4;
1473 master->setup = atmel_spi_setup;
1474 master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX |
1475 SPI_MASTER_GPIO_SS);
1476 master->transfer_one = atmel_spi_one_transfer;
1477 master->set_cs = atmel_spi_set_cs;
1478 master->cleanup = atmel_spi_cleanup;
1479 master->auto_runtime_pm = true;
1480 master->max_dma_len = SPI_MAX_DMA_XFER;
1481 master->can_dma = atmel_spi_can_dma;
1482 platform_set_drvdata(pdev, master);
1483
1484 as = spi_master_get_devdata(master);
1485
1486 spin_lock_init(&as->lock);
1487
1488 as->pdev = pdev;
1489 as->regs = devm_ioremap_resource(&pdev->dev, regs);
1490 if (IS_ERR(as->regs)) {
1491 ret = PTR_ERR(as->regs);
1492 goto out_unmap_regs;
1493 }
1494 as->phybase = regs->start;
1495 as->irq = irq;
1496 as->clk = clk;
1497
1498 init_completion(&as->xfer_completion);
1499
1500 atmel_get_caps(as);
1501
1502 as->use_dma = false;
1503 as->use_pdc = false;
1504 if (as->caps.has_dma_support) {
1505 ret = atmel_spi_configure_dma(master, as);
1506 if (ret == 0) {
1507 as->use_dma = true;
1508 } else if (ret == -EPROBE_DEFER) {
1509 goto out_unmap_regs;
1510 }
1511 } else if (as->caps.has_pdc_support) {
1512 as->use_pdc = true;
1513 }
1514
1515 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
1516 as->addr_rx_bbuf = dma_alloc_coherent(&pdev->dev,
1517 SPI_MAX_DMA_XFER,
1518 &as->dma_addr_rx_bbuf,
1519 GFP_KERNEL | GFP_DMA);
1520 if (!as->addr_rx_bbuf) {
1521 as->use_dma = false;
1522 } else {
1523 as->addr_tx_bbuf = dma_alloc_coherent(&pdev->dev,
1524 SPI_MAX_DMA_XFER,
1525 &as->dma_addr_tx_bbuf,
1526 GFP_KERNEL | GFP_DMA);
1527 if (!as->addr_tx_bbuf) {
1528 as->use_dma = false;
1529 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1530 as->addr_rx_bbuf,
1531 as->dma_addr_rx_bbuf);
1532 }
1533 }
1534 if (!as->use_dma)
1535 dev_info(master->dev.parent,
1536 " can not allocate dma coherent memory\n");
1537 }
1538
1539 if (as->caps.has_dma_support && !as->use_dma)
1540 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1541
1542 if (as->use_pdc) {
1543 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1544 0, dev_name(&pdev->dev), master);
1545 } else {
1546 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1547 0, dev_name(&pdev->dev), master);
1548 }
1549 if (ret)
1550 goto out_unmap_regs;
1551
1552 /* Initialize the hardware */
1553 ret = clk_prepare_enable(clk);
1554 if (ret)
1555 goto out_free_irq;
1556
1557 as->spi_clk = clk_get_rate(clk);
1558
1559 as->fifo_size = 0;
1560 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
1561 &as->fifo_size)) {
1562 dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size);
1563 }
1564
1565 atmel_spi_init(as);
1566
1567 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1568 pm_runtime_use_autosuspend(&pdev->dev);
1569 pm_runtime_set_active(&pdev->dev);
1570 pm_runtime_enable(&pdev->dev);
1571
1572 ret = devm_spi_register_master(&pdev->dev, master);
1573 if (ret)
1574 goto out_free_dma;
1575
1576 /* go! */
1577 dev_info(&pdev->dev, "Atmel SPI Controller version 0x%x at 0x%08lx (irq %d)\n",
1578 atmel_get_version(as), (unsigned long)regs->start,
1579 irq);
1580
1581 return 0;
1582
1583out_free_dma:
1584 pm_runtime_disable(&pdev->dev);
1585 pm_runtime_set_suspended(&pdev->dev);
1586
1587 if (as->use_dma)
1588 atmel_spi_release_dma(master);
1589
1590 spi_writel(as, CR, SPI_BIT(SWRST));
1591 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1592 clk_disable_unprepare(clk);
1593out_free_irq:
1594out_unmap_regs:
1595 spi_master_put(master);
1596 return ret;
1597}
1598
1599static int atmel_spi_remove(struct platform_device *pdev)
1600{
1601 struct spi_master *master = platform_get_drvdata(pdev);
1602 struct atmel_spi *as = spi_master_get_devdata(master);
1603
1604 pm_runtime_get_sync(&pdev->dev);
1605
1606 /* reset the hardware and block queue progress */
1607 if (as->use_dma) {
1608 atmel_spi_stop_dma(master);
1609 atmel_spi_release_dma(master);
1610 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
1611 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1612 as->addr_tx_bbuf,
1613 as->dma_addr_tx_bbuf);
1614 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1615 as->addr_rx_bbuf,
1616 as->dma_addr_rx_bbuf);
1617 }
1618 }
1619
1620 spin_lock_irq(&as->lock);
1621 spi_writel(as, CR, SPI_BIT(SWRST));
1622 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1623 spi_readl(as, SR);
1624 spin_unlock_irq(&as->lock);
1625
1626 clk_disable_unprepare(as->clk);
1627
1628 pm_runtime_put_noidle(&pdev->dev);
1629 pm_runtime_disable(&pdev->dev);
1630
1631 return 0;
1632}
1633
1634static int atmel_spi_runtime_suspend(struct device *dev)
1635{
1636 struct spi_master *master = dev_get_drvdata(dev);
1637 struct atmel_spi *as = spi_master_get_devdata(master);
1638
1639 clk_disable_unprepare(as->clk);
1640 pinctrl_pm_select_sleep_state(dev);
1641
1642 return 0;
1643}
1644
1645static int atmel_spi_runtime_resume(struct device *dev)
1646{
1647 struct spi_master *master = dev_get_drvdata(dev);
1648 struct atmel_spi *as = spi_master_get_devdata(master);
1649
1650 pinctrl_pm_select_default_state(dev);
1651
1652 return clk_prepare_enable(as->clk);
1653}
1654
1655static int atmel_spi_suspend(struct device *dev)
1656{
1657 struct spi_master *master = dev_get_drvdata(dev);
1658 int ret;
1659
1660 /* Stop the queue running */
1661 ret = spi_master_suspend(master);
1662 if (ret)
1663 return ret;
1664
1665 if (!pm_runtime_suspended(dev))
1666 atmel_spi_runtime_suspend(dev);
1667
1668 return 0;
1669}
1670
1671static int atmel_spi_resume(struct device *dev)
1672{
1673 struct spi_master *master = dev_get_drvdata(dev);
1674 struct atmel_spi *as = spi_master_get_devdata(master);
1675 int ret;
1676
1677 ret = clk_prepare_enable(as->clk);
1678 if (ret)
1679 return ret;
1680
1681 atmel_spi_init(as);
1682
1683 clk_disable_unprepare(as->clk);
1684
1685 if (!pm_runtime_suspended(dev)) {
1686 ret = atmel_spi_runtime_resume(dev);
1687 if (ret)
1688 return ret;
1689 }
1690
1691 /* Start the queue running */
1692 return spi_master_resume(master);
1693}
1694
1695static const struct dev_pm_ops atmel_spi_pm_ops = {
1696 SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
1697 RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
1698 atmel_spi_runtime_resume, NULL)
1699};
1700
1701static const struct of_device_id atmel_spi_dt_ids[] = {
1702 { .compatible = "atmel,at91rm9200-spi" },
1703 { /* sentinel */ }
1704};
1705
1706MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1707
1708static struct platform_driver atmel_spi_driver = {
1709 .driver = {
1710 .name = "atmel_spi",
1711 .pm = pm_ptr(&atmel_spi_pm_ops),
1712 .of_match_table = atmel_spi_dt_ids,
1713 },
1714 .probe = atmel_spi_probe,
1715 .remove = atmel_spi_remove,
1716};
1717module_platform_driver(atmel_spi_driver);
1718
1719MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1720MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1721MODULE_LICENSE("GPL");
1722MODULE_ALIAS("platform:atmel_spi");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for Atmel AT32 and AT91 SPI Controllers
4 *
5 * Copyright (C) 2006 Atmel Corporation
6 */
7
8#include <linux/kernel.h>
9#include <linux/clk.h>
10#include <linux/module.h>
11#include <linux/platform_device.h>
12#include <linux/delay.h>
13#include <linux/dma-mapping.h>
14#include <linux/dmaengine.h>
15#include <linux/err.h>
16#include <linux/interrupt.h>
17#include <linux/spi/spi.h>
18#include <linux/slab.h>
19#include <linux/platform_data/dma-atmel.h>
20#include <linux/of.h>
21
22#include <linux/io.h>
23#include <linux/gpio/consumer.h>
24#include <linux/pinctrl/consumer.h>
25#include <linux/pm_runtime.h>
26#include <trace/events/spi.h>
27
28/* SPI register offsets */
29#define SPI_CR 0x0000
30#define SPI_MR 0x0004
31#define SPI_RDR 0x0008
32#define SPI_TDR 0x000c
33#define SPI_SR 0x0010
34#define SPI_IER 0x0014
35#define SPI_IDR 0x0018
36#define SPI_IMR 0x001c
37#define SPI_CSR0 0x0030
38#define SPI_CSR1 0x0034
39#define SPI_CSR2 0x0038
40#define SPI_CSR3 0x003c
41#define SPI_FMR 0x0040
42#define SPI_FLR 0x0044
43#define SPI_VERSION 0x00fc
44#define SPI_RPR 0x0100
45#define SPI_RCR 0x0104
46#define SPI_TPR 0x0108
47#define SPI_TCR 0x010c
48#define SPI_RNPR 0x0110
49#define SPI_RNCR 0x0114
50#define SPI_TNPR 0x0118
51#define SPI_TNCR 0x011c
52#define SPI_PTCR 0x0120
53#define SPI_PTSR 0x0124
54
55/* Bitfields in CR */
56#define SPI_SPIEN_OFFSET 0
57#define SPI_SPIEN_SIZE 1
58#define SPI_SPIDIS_OFFSET 1
59#define SPI_SPIDIS_SIZE 1
60#define SPI_SWRST_OFFSET 7
61#define SPI_SWRST_SIZE 1
62#define SPI_LASTXFER_OFFSET 24
63#define SPI_LASTXFER_SIZE 1
64#define SPI_TXFCLR_OFFSET 16
65#define SPI_TXFCLR_SIZE 1
66#define SPI_RXFCLR_OFFSET 17
67#define SPI_RXFCLR_SIZE 1
68#define SPI_FIFOEN_OFFSET 30
69#define SPI_FIFOEN_SIZE 1
70#define SPI_FIFODIS_OFFSET 31
71#define SPI_FIFODIS_SIZE 1
72
73/* Bitfields in MR */
74#define SPI_MSTR_OFFSET 0
75#define SPI_MSTR_SIZE 1
76#define SPI_PS_OFFSET 1
77#define SPI_PS_SIZE 1
78#define SPI_PCSDEC_OFFSET 2
79#define SPI_PCSDEC_SIZE 1
80#define SPI_FDIV_OFFSET 3
81#define SPI_FDIV_SIZE 1
82#define SPI_MODFDIS_OFFSET 4
83#define SPI_MODFDIS_SIZE 1
84#define SPI_WDRBT_OFFSET 5
85#define SPI_WDRBT_SIZE 1
86#define SPI_LLB_OFFSET 7
87#define SPI_LLB_SIZE 1
88#define SPI_PCS_OFFSET 16
89#define SPI_PCS_SIZE 4
90#define SPI_DLYBCS_OFFSET 24
91#define SPI_DLYBCS_SIZE 8
92
93/* Bitfields in RDR */
94#define SPI_RD_OFFSET 0
95#define SPI_RD_SIZE 16
96
97/* Bitfields in TDR */
98#define SPI_TD_OFFSET 0
99#define SPI_TD_SIZE 16
100
101/* Bitfields in SR */
102#define SPI_RDRF_OFFSET 0
103#define SPI_RDRF_SIZE 1
104#define SPI_TDRE_OFFSET 1
105#define SPI_TDRE_SIZE 1
106#define SPI_MODF_OFFSET 2
107#define SPI_MODF_SIZE 1
108#define SPI_OVRES_OFFSET 3
109#define SPI_OVRES_SIZE 1
110#define SPI_ENDRX_OFFSET 4
111#define SPI_ENDRX_SIZE 1
112#define SPI_ENDTX_OFFSET 5
113#define SPI_ENDTX_SIZE 1
114#define SPI_RXBUFF_OFFSET 6
115#define SPI_RXBUFF_SIZE 1
116#define SPI_TXBUFE_OFFSET 7
117#define SPI_TXBUFE_SIZE 1
118#define SPI_NSSR_OFFSET 8
119#define SPI_NSSR_SIZE 1
120#define SPI_TXEMPTY_OFFSET 9
121#define SPI_TXEMPTY_SIZE 1
122#define SPI_SPIENS_OFFSET 16
123#define SPI_SPIENS_SIZE 1
124#define SPI_TXFEF_OFFSET 24
125#define SPI_TXFEF_SIZE 1
126#define SPI_TXFFF_OFFSET 25
127#define SPI_TXFFF_SIZE 1
128#define SPI_TXFTHF_OFFSET 26
129#define SPI_TXFTHF_SIZE 1
130#define SPI_RXFEF_OFFSET 27
131#define SPI_RXFEF_SIZE 1
132#define SPI_RXFFF_OFFSET 28
133#define SPI_RXFFF_SIZE 1
134#define SPI_RXFTHF_OFFSET 29
135#define SPI_RXFTHF_SIZE 1
136#define SPI_TXFPTEF_OFFSET 30
137#define SPI_TXFPTEF_SIZE 1
138#define SPI_RXFPTEF_OFFSET 31
139#define SPI_RXFPTEF_SIZE 1
140
141/* Bitfields in CSR0 */
142#define SPI_CPOL_OFFSET 0
143#define SPI_CPOL_SIZE 1
144#define SPI_NCPHA_OFFSET 1
145#define SPI_NCPHA_SIZE 1
146#define SPI_CSAAT_OFFSET 3
147#define SPI_CSAAT_SIZE 1
148#define SPI_BITS_OFFSET 4
149#define SPI_BITS_SIZE 4
150#define SPI_SCBR_OFFSET 8
151#define SPI_SCBR_SIZE 8
152#define SPI_DLYBS_OFFSET 16
153#define SPI_DLYBS_SIZE 8
154#define SPI_DLYBCT_OFFSET 24
155#define SPI_DLYBCT_SIZE 8
156
157/* Bitfields in RCR */
158#define SPI_RXCTR_OFFSET 0
159#define SPI_RXCTR_SIZE 16
160
161/* Bitfields in TCR */
162#define SPI_TXCTR_OFFSET 0
163#define SPI_TXCTR_SIZE 16
164
165/* Bitfields in RNCR */
166#define SPI_RXNCR_OFFSET 0
167#define SPI_RXNCR_SIZE 16
168
169/* Bitfields in TNCR */
170#define SPI_TXNCR_OFFSET 0
171#define SPI_TXNCR_SIZE 16
172
173/* Bitfields in PTCR */
174#define SPI_RXTEN_OFFSET 0
175#define SPI_RXTEN_SIZE 1
176#define SPI_RXTDIS_OFFSET 1
177#define SPI_RXTDIS_SIZE 1
178#define SPI_TXTEN_OFFSET 8
179#define SPI_TXTEN_SIZE 1
180#define SPI_TXTDIS_OFFSET 9
181#define SPI_TXTDIS_SIZE 1
182
183/* Bitfields in FMR */
184#define SPI_TXRDYM_OFFSET 0
185#define SPI_TXRDYM_SIZE 2
186#define SPI_RXRDYM_OFFSET 4
187#define SPI_RXRDYM_SIZE 2
188#define SPI_TXFTHRES_OFFSET 16
189#define SPI_TXFTHRES_SIZE 6
190#define SPI_RXFTHRES_OFFSET 24
191#define SPI_RXFTHRES_SIZE 6
192
193/* Bitfields in FLR */
194#define SPI_TXFL_OFFSET 0
195#define SPI_TXFL_SIZE 6
196#define SPI_RXFL_OFFSET 16
197#define SPI_RXFL_SIZE 6
198
199/* Constants for BITS */
200#define SPI_BITS_8_BPT 0
201#define SPI_BITS_9_BPT 1
202#define SPI_BITS_10_BPT 2
203#define SPI_BITS_11_BPT 3
204#define SPI_BITS_12_BPT 4
205#define SPI_BITS_13_BPT 5
206#define SPI_BITS_14_BPT 6
207#define SPI_BITS_15_BPT 7
208#define SPI_BITS_16_BPT 8
209#define SPI_ONE_DATA 0
210#define SPI_TWO_DATA 1
211#define SPI_FOUR_DATA 2
212
213/* Bit manipulation macros */
214#define SPI_BIT(name) \
215 (1 << SPI_##name##_OFFSET)
216#define SPI_BF(name, value) \
217 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
218#define SPI_BFEXT(name, value) \
219 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
220#define SPI_BFINS(name, value, old) \
221 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
222 | SPI_BF(name, value))
223
224/* Register access macros */
225#define spi_readl(port, reg) \
226 readl_relaxed((port)->regs + SPI_##reg)
227#define spi_writel(port, reg, value) \
228 writel_relaxed((value), (port)->regs + SPI_##reg)
229#define spi_writew(port, reg, value) \
230 writew_relaxed((value), (port)->regs + SPI_##reg)
231
232/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
233 * cache operations; better heuristics consider wordsize and bitrate.
234 */
235#define DMA_MIN_BYTES 16
236
237#define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
238
239#define AUTOSUSPEND_TIMEOUT 2000
240
241struct atmel_spi_caps {
242 bool is_spi2;
243 bool has_wdrbt;
244 bool has_dma_support;
245 bool has_pdc_support;
246};
247
248/*
249 * The core SPI transfer engine just talks to a register bank to set up
250 * DMA transfers; transfer queue progress is driven by IRQs. The clock
251 * framework provides the base clock, subdivided for each spi_device.
252 */
253struct atmel_spi {
254 spinlock_t lock;
255 unsigned long flags;
256
257 phys_addr_t phybase;
258 void __iomem *regs;
259 int irq;
260 struct clk *clk;
261 struct platform_device *pdev;
262 unsigned long spi_clk;
263
264 struct spi_transfer *current_transfer;
265 int current_remaining_bytes;
266 int done_status;
267 dma_addr_t dma_addr_rx_bbuf;
268 dma_addr_t dma_addr_tx_bbuf;
269 void *addr_rx_bbuf;
270 void *addr_tx_bbuf;
271
272 struct completion xfer_completion;
273
274 struct atmel_spi_caps caps;
275
276 bool use_dma;
277 bool use_pdc;
278
279 bool keep_cs;
280
281 u32 fifo_size;
282 u8 native_cs_free;
283 u8 native_cs_for_gpio;
284};
285
286/* Controller-specific per-slave state */
287struct atmel_spi_device {
288 u32 csr;
289};
290
291#define SPI_MAX_DMA_XFER 65535 /* true for both PDC and DMA */
292#define INVALID_DMA_ADDRESS 0xffffffff
293
294/*
295 * Version 2 of the SPI controller has
296 * - CR.LASTXFER
297 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
298 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
299 * - SPI_CSRx.CSAAT
300 * - SPI_CSRx.SBCR allows faster clocking
301 */
302static bool atmel_spi_is_v2(struct atmel_spi *as)
303{
304 return as->caps.is_spi2;
305}
306
307/*
308 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
309 * they assume that spi slave device state will not change on deselect, so
310 * that automagic deselection is OK. ("NPCSx rises if no data is to be
311 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
312 * controllers have CSAAT and friends.
313 *
314 * Even controller newer than ar91rm9200, using GPIOs can make sens as
315 * it lets us support active-high chipselects despite the controller's
316 * belief that only active-low devices/systems exists.
317 *
318 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
319 * right when driven with GPIO. ("Mode Fault does not allow more than one
320 * Master on Chip Select 0.") No workaround exists for that ... so for
321 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
322 * and (c) will trigger that first erratum in some cases.
323 */
324
325static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
326{
327 struct atmel_spi_device *asd = spi->controller_state;
328 int chip_select;
329 u32 mr;
330
331 if (spi->cs_gpiod)
332 chip_select = as->native_cs_for_gpio;
333 else
334 chip_select = spi->chip_select;
335
336 if (atmel_spi_is_v2(as)) {
337 spi_writel(as, CSR0 + 4 * chip_select, asd->csr);
338 /* For the low SPI version, there is a issue that PDC transfer
339 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
340 */
341 spi_writel(as, CSR0, asd->csr);
342 if (as->caps.has_wdrbt) {
343 spi_writel(as, MR,
344 SPI_BF(PCS, ~(0x01 << chip_select))
345 | SPI_BIT(WDRBT)
346 | SPI_BIT(MODFDIS)
347 | SPI_BIT(MSTR));
348 } else {
349 spi_writel(as, MR,
350 SPI_BF(PCS, ~(0x01 << chip_select))
351 | SPI_BIT(MODFDIS)
352 | SPI_BIT(MSTR));
353 }
354
355 mr = spi_readl(as, MR);
356 if (spi->cs_gpiod)
357 gpiod_set_value(spi->cs_gpiod, 1);
358 } else {
359 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
360 int i;
361 u32 csr;
362
363 /* Make sure clock polarity is correct */
364 for (i = 0; i < spi->master->num_chipselect; i++) {
365 csr = spi_readl(as, CSR0 + 4 * i);
366 if ((csr ^ cpol) & SPI_BIT(CPOL))
367 spi_writel(as, CSR0 + 4 * i,
368 csr ^ SPI_BIT(CPOL));
369 }
370
371 mr = spi_readl(as, MR);
372 mr = SPI_BFINS(PCS, ~(1 << chip_select), mr);
373 if (spi->cs_gpiod)
374 gpiod_set_value(spi->cs_gpiod, 1);
375 spi_writel(as, MR, mr);
376 }
377
378 dev_dbg(&spi->dev, "activate NPCS, mr %08x\n", mr);
379}
380
381static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
382{
383 int chip_select;
384 u32 mr;
385
386 if (spi->cs_gpiod)
387 chip_select = as->native_cs_for_gpio;
388 else
389 chip_select = spi->chip_select;
390
391 /* only deactivate *this* device; sometimes transfers to
392 * another device may be active when this routine is called.
393 */
394 mr = spi_readl(as, MR);
395 if (~SPI_BFEXT(PCS, mr) & (1 << chip_select)) {
396 mr = SPI_BFINS(PCS, 0xf, mr);
397 spi_writel(as, MR, mr);
398 }
399
400 dev_dbg(&spi->dev, "DEactivate NPCS, mr %08x\n", mr);
401
402 if (!spi->cs_gpiod)
403 spi_writel(as, CR, SPI_BIT(LASTXFER));
404 else
405 gpiod_set_value(spi->cs_gpiod, 0);
406}
407
408static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
409{
410 spin_lock_irqsave(&as->lock, as->flags);
411}
412
413static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
414{
415 spin_unlock_irqrestore(&as->lock, as->flags);
416}
417
418static inline bool atmel_spi_is_vmalloc_xfer(struct spi_transfer *xfer)
419{
420 return is_vmalloc_addr(xfer->tx_buf) || is_vmalloc_addr(xfer->rx_buf);
421}
422
423static inline bool atmel_spi_use_dma(struct atmel_spi *as,
424 struct spi_transfer *xfer)
425{
426 return as->use_dma && xfer->len >= DMA_MIN_BYTES;
427}
428
429static bool atmel_spi_can_dma(struct spi_master *master,
430 struct spi_device *spi,
431 struct spi_transfer *xfer)
432{
433 struct atmel_spi *as = spi_master_get_devdata(master);
434
435 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5))
436 return atmel_spi_use_dma(as, xfer) &&
437 !atmel_spi_is_vmalloc_xfer(xfer);
438 else
439 return atmel_spi_use_dma(as, xfer);
440
441}
442
443static int atmel_spi_dma_slave_config(struct atmel_spi *as,
444 struct dma_slave_config *slave_config,
445 u8 bits_per_word)
446{
447 struct spi_master *master = platform_get_drvdata(as->pdev);
448 int err = 0;
449
450 if (bits_per_word > 8) {
451 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
452 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
453 } else {
454 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
455 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
456 }
457
458 slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
459 slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
460 slave_config->src_maxburst = 1;
461 slave_config->dst_maxburst = 1;
462 slave_config->device_fc = false;
463
464 /*
465 * This driver uses fixed peripheral select mode (PS bit set to '0' in
466 * the Mode Register).
467 * So according to the datasheet, when FIFOs are available (and
468 * enabled), the Transmit FIFO operates in Multiple Data Mode.
469 * In this mode, up to 2 data, not 4, can be written into the Transmit
470 * Data Register in a single access.
471 * However, the first data has to be written into the lowest 16 bits and
472 * the second data into the highest 16 bits of the Transmit
473 * Data Register. For 8bit data (the most frequent case), it would
474 * require to rework tx_buf so each data would actualy fit 16 bits.
475 * So we'd rather write only one data at the time. Hence the transmit
476 * path works the same whether FIFOs are available (and enabled) or not.
477 */
478 slave_config->direction = DMA_MEM_TO_DEV;
479 if (dmaengine_slave_config(master->dma_tx, slave_config)) {
480 dev_err(&as->pdev->dev,
481 "failed to configure tx dma channel\n");
482 err = -EINVAL;
483 }
484
485 /*
486 * This driver configures the spi controller for master mode (MSTR bit
487 * set to '1' in the Mode Register).
488 * So according to the datasheet, when FIFOs are available (and
489 * enabled), the Receive FIFO operates in Single Data Mode.
490 * So the receive path works the same whether FIFOs are available (and
491 * enabled) or not.
492 */
493 slave_config->direction = DMA_DEV_TO_MEM;
494 if (dmaengine_slave_config(master->dma_rx, slave_config)) {
495 dev_err(&as->pdev->dev,
496 "failed to configure rx dma channel\n");
497 err = -EINVAL;
498 }
499
500 return err;
501}
502
503static int atmel_spi_configure_dma(struct spi_master *master,
504 struct atmel_spi *as)
505{
506 struct dma_slave_config slave_config;
507 struct device *dev = &as->pdev->dev;
508 int err;
509
510 dma_cap_mask_t mask;
511 dma_cap_zero(mask);
512 dma_cap_set(DMA_SLAVE, mask);
513
514 master->dma_tx = dma_request_chan(dev, "tx");
515 if (IS_ERR(master->dma_tx)) {
516 err = PTR_ERR(master->dma_tx);
517 if (err != -EPROBE_DEFER)
518 dev_err(dev, "No TX DMA channel, DMA is disabled\n");
519 goto error_clear;
520 }
521
522 master->dma_rx = dma_request_chan(dev, "rx");
523 if (IS_ERR(master->dma_rx)) {
524 err = PTR_ERR(master->dma_rx);
525 /*
526 * No reason to check EPROBE_DEFER here since we have already
527 * requested tx channel.
528 */
529 dev_err(dev, "No RX DMA channel, DMA is disabled\n");
530 goto error;
531 }
532
533 err = atmel_spi_dma_slave_config(as, &slave_config, 8);
534 if (err)
535 goto error;
536
537 dev_info(&as->pdev->dev,
538 "Using %s (tx) and %s (rx) for DMA transfers\n",
539 dma_chan_name(master->dma_tx),
540 dma_chan_name(master->dma_rx));
541
542 return 0;
543error:
544 if (!IS_ERR(master->dma_rx))
545 dma_release_channel(master->dma_rx);
546 if (!IS_ERR(master->dma_tx))
547 dma_release_channel(master->dma_tx);
548error_clear:
549 master->dma_tx = master->dma_rx = NULL;
550 return err;
551}
552
553static void atmel_spi_stop_dma(struct spi_master *master)
554{
555 if (master->dma_rx)
556 dmaengine_terminate_all(master->dma_rx);
557 if (master->dma_tx)
558 dmaengine_terminate_all(master->dma_tx);
559}
560
561static void atmel_spi_release_dma(struct spi_master *master)
562{
563 if (master->dma_rx) {
564 dma_release_channel(master->dma_rx);
565 master->dma_rx = NULL;
566 }
567 if (master->dma_tx) {
568 dma_release_channel(master->dma_tx);
569 master->dma_tx = NULL;
570 }
571}
572
573/* This function is called by the DMA driver from tasklet context */
574static void dma_callback(void *data)
575{
576 struct spi_master *master = data;
577 struct atmel_spi *as = spi_master_get_devdata(master);
578
579 if (is_vmalloc_addr(as->current_transfer->rx_buf) &&
580 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
581 memcpy(as->current_transfer->rx_buf, as->addr_rx_bbuf,
582 as->current_transfer->len);
583 }
584 complete(&as->xfer_completion);
585}
586
587/*
588 * Next transfer using PIO without FIFO.
589 */
590static void atmel_spi_next_xfer_single(struct spi_master *master,
591 struct spi_transfer *xfer)
592{
593 struct atmel_spi *as = spi_master_get_devdata(master);
594 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
595
596 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
597
598 /* Make sure data is not remaining in RDR */
599 spi_readl(as, RDR);
600 while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
601 spi_readl(as, RDR);
602 cpu_relax();
603 }
604
605 if (xfer->bits_per_word > 8)
606 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
607 else
608 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
609
610 dev_dbg(master->dev.parent,
611 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
612 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
613 xfer->bits_per_word);
614
615 /* Enable relevant interrupts */
616 spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
617}
618
619/*
620 * Next transfer using PIO with FIFO.
621 */
622static void atmel_spi_next_xfer_fifo(struct spi_master *master,
623 struct spi_transfer *xfer)
624{
625 struct atmel_spi *as = spi_master_get_devdata(master);
626 u32 current_remaining_data, num_data;
627 u32 offset = xfer->len - as->current_remaining_bytes;
628 const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset);
629 const u8 *bytes = (const u8 *)((u8 *)xfer->tx_buf + offset);
630 u16 td0, td1;
631 u32 fifomr;
632
633 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_fifo\n");
634
635 /* Compute the number of data to transfer in the current iteration */
636 current_remaining_data = ((xfer->bits_per_word > 8) ?
637 ((u32)as->current_remaining_bytes >> 1) :
638 (u32)as->current_remaining_bytes);
639 num_data = min(current_remaining_data, as->fifo_size);
640
641 /* Flush RX and TX FIFOs */
642 spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR));
643 while (spi_readl(as, FLR))
644 cpu_relax();
645
646 /* Set RX FIFO Threshold to the number of data to transfer */
647 fifomr = spi_readl(as, FMR);
648 spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr));
649
650 /* Clear FIFO flags in the Status Register, especially RXFTHF */
651 (void)spi_readl(as, SR);
652
653 /* Fill TX FIFO */
654 while (num_data >= 2) {
655 if (xfer->bits_per_word > 8) {
656 td0 = *words++;
657 td1 = *words++;
658 } else {
659 td0 = *bytes++;
660 td1 = *bytes++;
661 }
662
663 spi_writel(as, TDR, (td1 << 16) | td0);
664 num_data -= 2;
665 }
666
667 if (num_data) {
668 if (xfer->bits_per_word > 8)
669 td0 = *words++;
670 else
671 td0 = *bytes++;
672
673 spi_writew(as, TDR, td0);
674 num_data--;
675 }
676
677 dev_dbg(master->dev.parent,
678 " start fifo xfer %p: len %u tx %p rx %p bitpw %d\n",
679 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
680 xfer->bits_per_word);
681
682 /*
683 * Enable RX FIFO Threshold Flag interrupt to be notified about
684 * transfer completion.
685 */
686 spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES));
687}
688
689/*
690 * Next transfer using PIO.
691 */
692static void atmel_spi_next_xfer_pio(struct spi_master *master,
693 struct spi_transfer *xfer)
694{
695 struct atmel_spi *as = spi_master_get_devdata(master);
696
697 if (as->fifo_size)
698 atmel_spi_next_xfer_fifo(master, xfer);
699 else
700 atmel_spi_next_xfer_single(master, xfer);
701}
702
703/*
704 * Submit next transfer for DMA.
705 */
706static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
707 struct spi_transfer *xfer,
708 u32 *plen)
709 __must_hold(&as->lock)
710{
711 struct atmel_spi *as = spi_master_get_devdata(master);
712 struct dma_chan *rxchan = master->dma_rx;
713 struct dma_chan *txchan = master->dma_tx;
714 struct dma_async_tx_descriptor *rxdesc;
715 struct dma_async_tx_descriptor *txdesc;
716 struct dma_slave_config slave_config;
717 dma_cookie_t cookie;
718
719 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
720
721 /* Check that the channels are available */
722 if (!rxchan || !txchan)
723 return -ENODEV;
724
725 /* release lock for DMA operations */
726 atmel_spi_unlock(as);
727
728 *plen = xfer->len;
729
730 if (atmel_spi_dma_slave_config(as, &slave_config,
731 xfer->bits_per_word))
732 goto err_exit;
733
734 /* Send both scatterlists */
735 if (atmel_spi_is_vmalloc_xfer(xfer) &&
736 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
737 rxdesc = dmaengine_prep_slave_single(rxchan,
738 as->dma_addr_rx_bbuf,
739 xfer->len,
740 DMA_DEV_TO_MEM,
741 DMA_PREP_INTERRUPT |
742 DMA_CTRL_ACK);
743 } else {
744 rxdesc = dmaengine_prep_slave_sg(rxchan,
745 xfer->rx_sg.sgl,
746 xfer->rx_sg.nents,
747 DMA_DEV_TO_MEM,
748 DMA_PREP_INTERRUPT |
749 DMA_CTRL_ACK);
750 }
751 if (!rxdesc)
752 goto err_dma;
753
754 if (atmel_spi_is_vmalloc_xfer(xfer) &&
755 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
756 memcpy(as->addr_tx_bbuf, xfer->tx_buf, xfer->len);
757 txdesc = dmaengine_prep_slave_single(txchan,
758 as->dma_addr_tx_bbuf,
759 xfer->len, DMA_MEM_TO_DEV,
760 DMA_PREP_INTERRUPT |
761 DMA_CTRL_ACK);
762 } else {
763 txdesc = dmaengine_prep_slave_sg(txchan,
764 xfer->tx_sg.sgl,
765 xfer->tx_sg.nents,
766 DMA_MEM_TO_DEV,
767 DMA_PREP_INTERRUPT |
768 DMA_CTRL_ACK);
769 }
770 if (!txdesc)
771 goto err_dma;
772
773 dev_dbg(master->dev.parent,
774 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
775 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
776 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
777
778 /* Enable relevant interrupts */
779 spi_writel(as, IER, SPI_BIT(OVRES));
780
781 /* Put the callback on the RX transfer only, that should finish last */
782 rxdesc->callback = dma_callback;
783 rxdesc->callback_param = master;
784
785 /* Submit and fire RX and TX with TX last so we're ready to read! */
786 cookie = rxdesc->tx_submit(rxdesc);
787 if (dma_submit_error(cookie))
788 goto err_dma;
789 cookie = txdesc->tx_submit(txdesc);
790 if (dma_submit_error(cookie))
791 goto err_dma;
792 rxchan->device->device_issue_pending(rxchan);
793 txchan->device->device_issue_pending(txchan);
794
795 /* take back lock */
796 atmel_spi_lock(as);
797 return 0;
798
799err_dma:
800 spi_writel(as, IDR, SPI_BIT(OVRES));
801 atmel_spi_stop_dma(master);
802err_exit:
803 atmel_spi_lock(as);
804 return -ENOMEM;
805}
806
807static void atmel_spi_next_xfer_data(struct spi_master *master,
808 struct spi_transfer *xfer,
809 dma_addr_t *tx_dma,
810 dma_addr_t *rx_dma,
811 u32 *plen)
812{
813 *rx_dma = xfer->rx_dma + xfer->len - *plen;
814 *tx_dma = xfer->tx_dma + xfer->len - *plen;
815 if (*plen > master->max_dma_len)
816 *plen = master->max_dma_len;
817}
818
819static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
820 struct spi_device *spi,
821 struct spi_transfer *xfer)
822{
823 u32 scbr, csr;
824 unsigned long bus_hz;
825 int chip_select;
826
827 if (spi->cs_gpiod)
828 chip_select = as->native_cs_for_gpio;
829 else
830 chip_select = spi->chip_select;
831
832 /* v1 chips start out at half the peripheral bus speed. */
833 bus_hz = as->spi_clk;
834 if (!atmel_spi_is_v2(as))
835 bus_hz /= 2;
836
837 /*
838 * Calculate the lowest divider that satisfies the
839 * constraint, assuming div32/fdiv/mbz == 0.
840 */
841 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
842
843 /*
844 * If the resulting divider doesn't fit into the
845 * register bitfield, we can't satisfy the constraint.
846 */
847 if (scbr >= (1 << SPI_SCBR_SIZE)) {
848 dev_err(&spi->dev,
849 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
850 xfer->speed_hz, scbr, bus_hz/255);
851 return -EINVAL;
852 }
853 if (scbr == 0) {
854 dev_err(&spi->dev,
855 "setup: %d Hz too high, scbr %u; max %ld Hz\n",
856 xfer->speed_hz, scbr, bus_hz);
857 return -EINVAL;
858 }
859 csr = spi_readl(as, CSR0 + 4 * chip_select);
860 csr = SPI_BFINS(SCBR, scbr, csr);
861 spi_writel(as, CSR0 + 4 * chip_select, csr);
862
863 return 0;
864}
865
866/*
867 * Submit next transfer for PDC.
868 * lock is held, spi irq is blocked
869 */
870static void atmel_spi_pdc_next_xfer(struct spi_master *master,
871 struct spi_message *msg,
872 struct spi_transfer *xfer)
873{
874 struct atmel_spi *as = spi_master_get_devdata(master);
875 u32 len;
876 dma_addr_t tx_dma, rx_dma;
877
878 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
879
880 len = as->current_remaining_bytes;
881 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
882 as->current_remaining_bytes -= len;
883
884 spi_writel(as, RPR, rx_dma);
885 spi_writel(as, TPR, tx_dma);
886
887 if (msg->spi->bits_per_word > 8)
888 len >>= 1;
889 spi_writel(as, RCR, len);
890 spi_writel(as, TCR, len);
891
892 dev_dbg(&msg->spi->dev,
893 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
894 xfer, xfer->len, xfer->tx_buf,
895 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
896 (unsigned long long)xfer->rx_dma);
897
898 if (as->current_remaining_bytes) {
899 len = as->current_remaining_bytes;
900 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
901 as->current_remaining_bytes -= len;
902
903 spi_writel(as, RNPR, rx_dma);
904 spi_writel(as, TNPR, tx_dma);
905
906 if (msg->spi->bits_per_word > 8)
907 len >>= 1;
908 spi_writel(as, RNCR, len);
909 spi_writel(as, TNCR, len);
910
911 dev_dbg(&msg->spi->dev,
912 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
913 xfer, xfer->len, xfer->tx_buf,
914 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
915 (unsigned long long)xfer->rx_dma);
916 }
917
918 /* REVISIT: We're waiting for RXBUFF before we start the next
919 * transfer because we need to handle some difficult timing
920 * issues otherwise. If we wait for TXBUFE in one transfer and
921 * then starts waiting for RXBUFF in the next, it's difficult
922 * to tell the difference between the RXBUFF interrupt we're
923 * actually waiting for and the RXBUFF interrupt of the
924 * previous transfer.
925 *
926 * It should be doable, though. Just not now...
927 */
928 spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
929 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
930}
931
932/*
933 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
934 * - The buffer is either valid for CPU access, else NULL
935 * - If the buffer is valid, so is its DMA address
936 *
937 * This driver manages the dma address unless message->is_dma_mapped.
938 */
939static int
940atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
941{
942 struct device *dev = &as->pdev->dev;
943
944 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
945 if (xfer->tx_buf) {
946 /* tx_buf is a const void* where we need a void * for the dma
947 * mapping */
948 void *nonconst_tx = (void *)xfer->tx_buf;
949
950 xfer->tx_dma = dma_map_single(dev,
951 nonconst_tx, xfer->len,
952 DMA_TO_DEVICE);
953 if (dma_mapping_error(dev, xfer->tx_dma))
954 return -ENOMEM;
955 }
956 if (xfer->rx_buf) {
957 xfer->rx_dma = dma_map_single(dev,
958 xfer->rx_buf, xfer->len,
959 DMA_FROM_DEVICE);
960 if (dma_mapping_error(dev, xfer->rx_dma)) {
961 if (xfer->tx_buf)
962 dma_unmap_single(dev,
963 xfer->tx_dma, xfer->len,
964 DMA_TO_DEVICE);
965 return -ENOMEM;
966 }
967 }
968 return 0;
969}
970
971static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
972 struct spi_transfer *xfer)
973{
974 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
975 dma_unmap_single(master->dev.parent, xfer->tx_dma,
976 xfer->len, DMA_TO_DEVICE);
977 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
978 dma_unmap_single(master->dev.parent, xfer->rx_dma,
979 xfer->len, DMA_FROM_DEVICE);
980}
981
982static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
983{
984 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
985}
986
987static void
988atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer)
989{
990 u8 *rxp;
991 u16 *rxp16;
992 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
993
994 if (xfer->bits_per_word > 8) {
995 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
996 *rxp16 = spi_readl(as, RDR);
997 } else {
998 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
999 *rxp = spi_readl(as, RDR);
1000 }
1001 if (xfer->bits_per_word > 8) {
1002 if (as->current_remaining_bytes > 2)
1003 as->current_remaining_bytes -= 2;
1004 else
1005 as->current_remaining_bytes = 0;
1006 } else {
1007 as->current_remaining_bytes--;
1008 }
1009}
1010
1011static void
1012atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer)
1013{
1014 u32 fifolr = spi_readl(as, FLR);
1015 u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr);
1016 u32 offset = xfer->len - as->current_remaining_bytes;
1017 u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset);
1018 u8 *bytes = (u8 *)((u8 *)xfer->rx_buf + offset);
1019 u16 rd; /* RD field is the lowest 16 bits of RDR */
1020
1021 /* Update the number of remaining bytes to transfer */
1022 num_bytes = ((xfer->bits_per_word > 8) ?
1023 (num_data << 1) :
1024 num_data);
1025
1026 if (as->current_remaining_bytes > num_bytes)
1027 as->current_remaining_bytes -= num_bytes;
1028 else
1029 as->current_remaining_bytes = 0;
1030
1031 /* Handle odd number of bytes when data are more than 8bit width */
1032 if (xfer->bits_per_word > 8)
1033 as->current_remaining_bytes &= ~0x1;
1034
1035 /* Read data */
1036 while (num_data) {
1037 rd = spi_readl(as, RDR);
1038 if (xfer->bits_per_word > 8)
1039 *words++ = rd;
1040 else
1041 *bytes++ = rd;
1042 num_data--;
1043 }
1044}
1045
1046/* Called from IRQ
1047 *
1048 * Must update "current_remaining_bytes" to keep track of data
1049 * to transfer.
1050 */
1051static void
1052atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
1053{
1054 if (as->fifo_size)
1055 atmel_spi_pump_fifo_data(as, xfer);
1056 else
1057 atmel_spi_pump_single_data(as, xfer);
1058}
1059
1060/* Interrupt
1061 *
1062 * No need for locking in this Interrupt handler: done_status is the
1063 * only information modified.
1064 */
1065static irqreturn_t
1066atmel_spi_pio_interrupt(int irq, void *dev_id)
1067{
1068 struct spi_master *master = dev_id;
1069 struct atmel_spi *as = spi_master_get_devdata(master);
1070 u32 status, pending, imr;
1071 struct spi_transfer *xfer;
1072 int ret = IRQ_NONE;
1073
1074 imr = spi_readl(as, IMR);
1075 status = spi_readl(as, SR);
1076 pending = status & imr;
1077
1078 if (pending & SPI_BIT(OVRES)) {
1079 ret = IRQ_HANDLED;
1080 spi_writel(as, IDR, SPI_BIT(OVRES));
1081 dev_warn(master->dev.parent, "overrun\n");
1082
1083 /*
1084 * When we get an overrun, we disregard the current
1085 * transfer. Data will not be copied back from any
1086 * bounce buffer and msg->actual_len will not be
1087 * updated with the last xfer.
1088 *
1089 * We will also not process any remaning transfers in
1090 * the message.
1091 */
1092 as->done_status = -EIO;
1093 smp_wmb();
1094
1095 /* Clear any overrun happening while cleaning up */
1096 spi_readl(as, SR);
1097
1098 complete(&as->xfer_completion);
1099
1100 } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) {
1101 atmel_spi_lock(as);
1102
1103 if (as->current_remaining_bytes) {
1104 ret = IRQ_HANDLED;
1105 xfer = as->current_transfer;
1106 atmel_spi_pump_pio_data(as, xfer);
1107 if (!as->current_remaining_bytes)
1108 spi_writel(as, IDR, pending);
1109
1110 complete(&as->xfer_completion);
1111 }
1112
1113 atmel_spi_unlock(as);
1114 } else {
1115 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
1116 ret = IRQ_HANDLED;
1117 spi_writel(as, IDR, pending);
1118 }
1119
1120 return ret;
1121}
1122
1123static irqreturn_t
1124atmel_spi_pdc_interrupt(int irq, void *dev_id)
1125{
1126 struct spi_master *master = dev_id;
1127 struct atmel_spi *as = spi_master_get_devdata(master);
1128 u32 status, pending, imr;
1129 int ret = IRQ_NONE;
1130
1131 imr = spi_readl(as, IMR);
1132 status = spi_readl(as, SR);
1133 pending = status & imr;
1134
1135 if (pending & SPI_BIT(OVRES)) {
1136
1137 ret = IRQ_HANDLED;
1138
1139 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
1140 | SPI_BIT(OVRES)));
1141
1142 /* Clear any overrun happening while cleaning up */
1143 spi_readl(as, SR);
1144
1145 as->done_status = -EIO;
1146
1147 complete(&as->xfer_completion);
1148
1149 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
1150 ret = IRQ_HANDLED;
1151
1152 spi_writel(as, IDR, pending);
1153
1154 complete(&as->xfer_completion);
1155 }
1156
1157 return ret;
1158}
1159
1160static int atmel_word_delay_csr(struct spi_device *spi, struct atmel_spi *as)
1161{
1162 struct spi_delay *delay = &spi->word_delay;
1163 u32 value = delay->value;
1164
1165 switch (delay->unit) {
1166 case SPI_DELAY_UNIT_NSECS:
1167 value /= 1000;
1168 break;
1169 case SPI_DELAY_UNIT_USECS:
1170 break;
1171 default:
1172 return -EINVAL;
1173 }
1174
1175 return (as->spi_clk / 1000000 * value) >> 5;
1176}
1177
1178static void initialize_native_cs_for_gpio(struct atmel_spi *as)
1179{
1180 int i;
1181 struct spi_master *master = platform_get_drvdata(as->pdev);
1182
1183 if (!as->native_cs_free)
1184 return; /* already initialized */
1185
1186 if (!master->cs_gpiods)
1187 return; /* No CS GPIO */
1188
1189 /*
1190 * On the first version of the controller (AT91RM9200), CS0
1191 * can't be used associated with GPIO
1192 */
1193 if (atmel_spi_is_v2(as))
1194 i = 0;
1195 else
1196 i = 1;
1197
1198 for (; i < 4; i++)
1199 if (master->cs_gpiods[i])
1200 as->native_cs_free |= BIT(i);
1201
1202 if (as->native_cs_free)
1203 as->native_cs_for_gpio = ffs(as->native_cs_free);
1204}
1205
1206static int atmel_spi_setup(struct spi_device *spi)
1207{
1208 struct atmel_spi *as;
1209 struct atmel_spi_device *asd;
1210 u32 csr;
1211 unsigned int bits = spi->bits_per_word;
1212 int chip_select;
1213 int word_delay_csr;
1214
1215 as = spi_master_get_devdata(spi->master);
1216
1217 /* see notes above re chipselect */
1218 if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH)) {
1219 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
1220 return -EINVAL;
1221 }
1222
1223 /* Setup() is called during spi_register_controller(aka
1224 * spi_register_master) but after all membmers of the cs_gpiod
1225 * array have been filled, so we can looked for which native
1226 * CS will be free for using with GPIO
1227 */
1228 initialize_native_cs_for_gpio(as);
1229
1230 if (spi->cs_gpiod && as->native_cs_free) {
1231 dev_err(&spi->dev,
1232 "No native CS available to support this GPIO CS\n");
1233 return -EBUSY;
1234 }
1235
1236 if (spi->cs_gpiod)
1237 chip_select = as->native_cs_for_gpio;
1238 else
1239 chip_select = spi->chip_select;
1240
1241 csr = SPI_BF(BITS, bits - 8);
1242 if (spi->mode & SPI_CPOL)
1243 csr |= SPI_BIT(CPOL);
1244 if (!(spi->mode & SPI_CPHA))
1245 csr |= SPI_BIT(NCPHA);
1246
1247 if (!spi->cs_gpiod)
1248 csr |= SPI_BIT(CSAAT);
1249 csr |= SPI_BF(DLYBS, 0);
1250
1251 word_delay_csr = atmel_word_delay_csr(spi, as);
1252 if (word_delay_csr < 0)
1253 return word_delay_csr;
1254
1255 /* DLYBCT adds delays between words. This is useful for slow devices
1256 * that need a bit of time to setup the next transfer.
1257 */
1258 csr |= SPI_BF(DLYBCT, word_delay_csr);
1259
1260 asd = spi->controller_state;
1261 if (!asd) {
1262 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1263 if (!asd)
1264 return -ENOMEM;
1265
1266 spi->controller_state = asd;
1267 }
1268
1269 asd->csr = csr;
1270
1271 dev_dbg(&spi->dev,
1272 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1273 bits, spi->mode, spi->chip_select, csr);
1274
1275 if (!atmel_spi_is_v2(as))
1276 spi_writel(as, CSR0 + 4 * chip_select, csr);
1277
1278 return 0;
1279}
1280
1281static int atmel_spi_one_transfer(struct spi_master *master,
1282 struct spi_message *msg,
1283 struct spi_transfer *xfer)
1284{
1285 struct atmel_spi *as;
1286 struct spi_device *spi = msg->spi;
1287 u8 bits;
1288 u32 len;
1289 struct atmel_spi_device *asd;
1290 int timeout;
1291 int ret;
1292 unsigned long dma_timeout;
1293
1294 as = spi_master_get_devdata(master);
1295
1296 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1297 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1298 return -EINVAL;
1299 }
1300
1301 asd = spi->controller_state;
1302 bits = (asd->csr >> 4) & 0xf;
1303 if (bits != xfer->bits_per_word - 8) {
1304 dev_dbg(&spi->dev,
1305 "you can't yet change bits_per_word in transfers\n");
1306 return -ENOPROTOOPT;
1307 }
1308
1309 /*
1310 * DMA map early, for performance (empties dcache ASAP) and
1311 * better fault reporting.
1312 */
1313 if ((!msg->is_dma_mapped)
1314 && as->use_pdc) {
1315 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1316 return -ENOMEM;
1317 }
1318
1319 atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1320
1321 as->done_status = 0;
1322 as->current_transfer = xfer;
1323 as->current_remaining_bytes = xfer->len;
1324 while (as->current_remaining_bytes) {
1325 reinit_completion(&as->xfer_completion);
1326
1327 if (as->use_pdc) {
1328 atmel_spi_pdc_next_xfer(master, msg, xfer);
1329 } else if (atmel_spi_use_dma(as, xfer)) {
1330 len = as->current_remaining_bytes;
1331 ret = atmel_spi_next_xfer_dma_submit(master,
1332 xfer, &len);
1333 if (ret) {
1334 dev_err(&spi->dev,
1335 "unable to use DMA, fallback to PIO\n");
1336 atmel_spi_next_xfer_pio(master, xfer);
1337 } else {
1338 as->current_remaining_bytes -= len;
1339 if (as->current_remaining_bytes < 0)
1340 as->current_remaining_bytes = 0;
1341 }
1342 } else {
1343 atmel_spi_next_xfer_pio(master, xfer);
1344 }
1345
1346 /* interrupts are disabled, so free the lock for schedule */
1347 atmel_spi_unlock(as);
1348 dma_timeout = wait_for_completion_timeout(&as->xfer_completion,
1349 SPI_DMA_TIMEOUT);
1350 atmel_spi_lock(as);
1351 if (WARN_ON(dma_timeout == 0)) {
1352 dev_err(&spi->dev, "spi transfer timeout\n");
1353 as->done_status = -EIO;
1354 }
1355
1356 if (as->done_status)
1357 break;
1358 }
1359
1360 if (as->done_status) {
1361 if (as->use_pdc) {
1362 dev_warn(master->dev.parent,
1363 "overrun (%u/%u remaining)\n",
1364 spi_readl(as, TCR), spi_readl(as, RCR));
1365
1366 /*
1367 * Clean up DMA registers and make sure the data
1368 * registers are empty.
1369 */
1370 spi_writel(as, RNCR, 0);
1371 spi_writel(as, TNCR, 0);
1372 spi_writel(as, RCR, 0);
1373 spi_writel(as, TCR, 0);
1374 for (timeout = 1000; timeout; timeout--)
1375 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1376 break;
1377 if (!timeout)
1378 dev_warn(master->dev.parent,
1379 "timeout waiting for TXEMPTY");
1380 while (spi_readl(as, SR) & SPI_BIT(RDRF))
1381 spi_readl(as, RDR);
1382
1383 /* Clear any overrun happening while cleaning up */
1384 spi_readl(as, SR);
1385
1386 } else if (atmel_spi_use_dma(as, xfer)) {
1387 atmel_spi_stop_dma(master);
1388 }
1389
1390 if (!msg->is_dma_mapped
1391 && as->use_pdc)
1392 atmel_spi_dma_unmap_xfer(master, xfer);
1393
1394 return 0;
1395
1396 } else {
1397 /* only update length if no error */
1398 msg->actual_length += xfer->len;
1399 }
1400
1401 if (!msg->is_dma_mapped
1402 && as->use_pdc)
1403 atmel_spi_dma_unmap_xfer(master, xfer);
1404
1405 spi_transfer_delay_exec(xfer);
1406
1407 if (xfer->cs_change) {
1408 if (list_is_last(&xfer->transfer_list,
1409 &msg->transfers)) {
1410 as->keep_cs = true;
1411 } else {
1412 cs_deactivate(as, msg->spi);
1413 udelay(10);
1414 cs_activate(as, msg->spi);
1415 }
1416 }
1417
1418 return 0;
1419}
1420
1421static int atmel_spi_transfer_one_message(struct spi_master *master,
1422 struct spi_message *msg)
1423{
1424 struct atmel_spi *as;
1425 struct spi_transfer *xfer;
1426 struct spi_device *spi = msg->spi;
1427 int ret = 0;
1428
1429 as = spi_master_get_devdata(master);
1430
1431 dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1432 msg, dev_name(&spi->dev));
1433
1434 atmel_spi_lock(as);
1435 cs_activate(as, spi);
1436
1437 as->keep_cs = false;
1438
1439 msg->status = 0;
1440 msg->actual_length = 0;
1441
1442 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1443 trace_spi_transfer_start(msg, xfer);
1444
1445 ret = atmel_spi_one_transfer(master, msg, xfer);
1446 if (ret)
1447 goto msg_done;
1448
1449 trace_spi_transfer_stop(msg, xfer);
1450 }
1451
1452 if (as->use_pdc)
1453 atmel_spi_disable_pdc_transfer(as);
1454
1455 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1456 dev_dbg(&spi->dev,
1457 " xfer %p: len %u tx %p/%pad rx %p/%pad\n",
1458 xfer, xfer->len,
1459 xfer->tx_buf, &xfer->tx_dma,
1460 xfer->rx_buf, &xfer->rx_dma);
1461 }
1462
1463msg_done:
1464 if (!as->keep_cs)
1465 cs_deactivate(as, msg->spi);
1466
1467 atmel_spi_unlock(as);
1468
1469 msg->status = as->done_status;
1470 spi_finalize_current_message(spi->master);
1471
1472 return ret;
1473}
1474
1475static void atmel_spi_cleanup(struct spi_device *spi)
1476{
1477 struct atmel_spi_device *asd = spi->controller_state;
1478
1479 if (!asd)
1480 return;
1481
1482 spi->controller_state = NULL;
1483 kfree(asd);
1484}
1485
1486static inline unsigned int atmel_get_version(struct atmel_spi *as)
1487{
1488 return spi_readl(as, VERSION) & 0x00000fff;
1489}
1490
1491static void atmel_get_caps(struct atmel_spi *as)
1492{
1493 unsigned int version;
1494
1495 version = atmel_get_version(as);
1496
1497 as->caps.is_spi2 = version > 0x121;
1498 as->caps.has_wdrbt = version >= 0x210;
1499 as->caps.has_dma_support = version >= 0x212;
1500 as->caps.has_pdc_support = version < 0x212;
1501}
1502
1503static void atmel_spi_init(struct atmel_spi *as)
1504{
1505 spi_writel(as, CR, SPI_BIT(SWRST));
1506 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1507
1508 /* It is recommended to enable FIFOs first thing after reset */
1509 if (as->fifo_size)
1510 spi_writel(as, CR, SPI_BIT(FIFOEN));
1511
1512 if (as->caps.has_wdrbt) {
1513 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1514 | SPI_BIT(MSTR));
1515 } else {
1516 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1517 }
1518
1519 if (as->use_pdc)
1520 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1521 spi_writel(as, CR, SPI_BIT(SPIEN));
1522}
1523
1524static int atmel_spi_probe(struct platform_device *pdev)
1525{
1526 struct resource *regs;
1527 int irq;
1528 struct clk *clk;
1529 int ret;
1530 struct spi_master *master;
1531 struct atmel_spi *as;
1532
1533 /* Select default pin state */
1534 pinctrl_pm_select_default_state(&pdev->dev);
1535
1536 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1537 if (!regs)
1538 return -ENXIO;
1539
1540 irq = platform_get_irq(pdev, 0);
1541 if (irq < 0)
1542 return irq;
1543
1544 clk = devm_clk_get(&pdev->dev, "spi_clk");
1545 if (IS_ERR(clk))
1546 return PTR_ERR(clk);
1547
1548 /* setup spi core then atmel-specific driver state */
1549 master = spi_alloc_master(&pdev->dev, sizeof(*as));
1550 if (!master)
1551 return -ENOMEM;
1552
1553 /* the spi->mode bits understood by this driver: */
1554 master->use_gpio_descriptors = true;
1555 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1556 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1557 master->dev.of_node = pdev->dev.of_node;
1558 master->bus_num = pdev->id;
1559 master->num_chipselect = 4;
1560 master->setup = atmel_spi_setup;
1561 master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
1562 master->transfer_one_message = atmel_spi_transfer_one_message;
1563 master->cleanup = atmel_spi_cleanup;
1564 master->auto_runtime_pm = true;
1565 master->max_dma_len = SPI_MAX_DMA_XFER;
1566 master->can_dma = atmel_spi_can_dma;
1567 platform_set_drvdata(pdev, master);
1568
1569 as = spi_master_get_devdata(master);
1570
1571 spin_lock_init(&as->lock);
1572
1573 as->pdev = pdev;
1574 as->regs = devm_ioremap_resource(&pdev->dev, regs);
1575 if (IS_ERR(as->regs)) {
1576 ret = PTR_ERR(as->regs);
1577 goto out_unmap_regs;
1578 }
1579 as->phybase = regs->start;
1580 as->irq = irq;
1581 as->clk = clk;
1582
1583 init_completion(&as->xfer_completion);
1584
1585 atmel_get_caps(as);
1586
1587 as->use_dma = false;
1588 as->use_pdc = false;
1589 if (as->caps.has_dma_support) {
1590 ret = atmel_spi_configure_dma(master, as);
1591 if (ret == 0) {
1592 as->use_dma = true;
1593 } else if (ret == -EPROBE_DEFER) {
1594 return ret;
1595 }
1596 } else if (as->caps.has_pdc_support) {
1597 as->use_pdc = true;
1598 }
1599
1600 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
1601 as->addr_rx_bbuf = dma_alloc_coherent(&pdev->dev,
1602 SPI_MAX_DMA_XFER,
1603 &as->dma_addr_rx_bbuf,
1604 GFP_KERNEL | GFP_DMA);
1605 if (!as->addr_rx_bbuf) {
1606 as->use_dma = false;
1607 } else {
1608 as->addr_tx_bbuf = dma_alloc_coherent(&pdev->dev,
1609 SPI_MAX_DMA_XFER,
1610 &as->dma_addr_tx_bbuf,
1611 GFP_KERNEL | GFP_DMA);
1612 if (!as->addr_tx_bbuf) {
1613 as->use_dma = false;
1614 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1615 as->addr_rx_bbuf,
1616 as->dma_addr_rx_bbuf);
1617 }
1618 }
1619 if (!as->use_dma)
1620 dev_info(master->dev.parent,
1621 " can not allocate dma coherent memory\n");
1622 }
1623
1624 if (as->caps.has_dma_support && !as->use_dma)
1625 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1626
1627 if (as->use_pdc) {
1628 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1629 0, dev_name(&pdev->dev), master);
1630 } else {
1631 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1632 0, dev_name(&pdev->dev), master);
1633 }
1634 if (ret)
1635 goto out_unmap_regs;
1636
1637 /* Initialize the hardware */
1638 ret = clk_prepare_enable(clk);
1639 if (ret)
1640 goto out_free_irq;
1641
1642 as->spi_clk = clk_get_rate(clk);
1643
1644 as->fifo_size = 0;
1645 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
1646 &as->fifo_size)) {
1647 dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size);
1648 }
1649
1650 atmel_spi_init(as);
1651
1652 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1653 pm_runtime_use_autosuspend(&pdev->dev);
1654 pm_runtime_set_active(&pdev->dev);
1655 pm_runtime_enable(&pdev->dev);
1656
1657 ret = devm_spi_register_master(&pdev->dev, master);
1658 if (ret)
1659 goto out_free_dma;
1660
1661 /* go! */
1662 dev_info(&pdev->dev, "Atmel SPI Controller version 0x%x at 0x%08lx (irq %d)\n",
1663 atmel_get_version(as), (unsigned long)regs->start,
1664 irq);
1665
1666 return 0;
1667
1668out_free_dma:
1669 pm_runtime_disable(&pdev->dev);
1670 pm_runtime_set_suspended(&pdev->dev);
1671
1672 if (as->use_dma)
1673 atmel_spi_release_dma(master);
1674
1675 spi_writel(as, CR, SPI_BIT(SWRST));
1676 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1677 clk_disable_unprepare(clk);
1678out_free_irq:
1679out_unmap_regs:
1680 spi_master_put(master);
1681 return ret;
1682}
1683
1684static int atmel_spi_remove(struct platform_device *pdev)
1685{
1686 struct spi_master *master = platform_get_drvdata(pdev);
1687 struct atmel_spi *as = spi_master_get_devdata(master);
1688
1689 pm_runtime_get_sync(&pdev->dev);
1690
1691 /* reset the hardware and block queue progress */
1692 if (as->use_dma) {
1693 atmel_spi_stop_dma(master);
1694 atmel_spi_release_dma(master);
1695 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
1696 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1697 as->addr_tx_bbuf,
1698 as->dma_addr_tx_bbuf);
1699 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1700 as->addr_rx_bbuf,
1701 as->dma_addr_rx_bbuf);
1702 }
1703 }
1704
1705 spin_lock_irq(&as->lock);
1706 spi_writel(as, CR, SPI_BIT(SWRST));
1707 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1708 spi_readl(as, SR);
1709 spin_unlock_irq(&as->lock);
1710
1711 clk_disable_unprepare(as->clk);
1712
1713 pm_runtime_put_noidle(&pdev->dev);
1714 pm_runtime_disable(&pdev->dev);
1715
1716 return 0;
1717}
1718
1719#ifdef CONFIG_PM
1720static int atmel_spi_runtime_suspend(struct device *dev)
1721{
1722 struct spi_master *master = dev_get_drvdata(dev);
1723 struct atmel_spi *as = spi_master_get_devdata(master);
1724
1725 clk_disable_unprepare(as->clk);
1726 pinctrl_pm_select_sleep_state(dev);
1727
1728 return 0;
1729}
1730
1731static int atmel_spi_runtime_resume(struct device *dev)
1732{
1733 struct spi_master *master = dev_get_drvdata(dev);
1734 struct atmel_spi *as = spi_master_get_devdata(master);
1735
1736 pinctrl_pm_select_default_state(dev);
1737
1738 return clk_prepare_enable(as->clk);
1739}
1740
1741#ifdef CONFIG_PM_SLEEP
1742static int atmel_spi_suspend(struct device *dev)
1743{
1744 struct spi_master *master = dev_get_drvdata(dev);
1745 int ret;
1746
1747 /* Stop the queue running */
1748 ret = spi_master_suspend(master);
1749 if (ret)
1750 return ret;
1751
1752 if (!pm_runtime_suspended(dev))
1753 atmel_spi_runtime_suspend(dev);
1754
1755 return 0;
1756}
1757
1758static int atmel_spi_resume(struct device *dev)
1759{
1760 struct spi_master *master = dev_get_drvdata(dev);
1761 struct atmel_spi *as = spi_master_get_devdata(master);
1762 int ret;
1763
1764 ret = clk_prepare_enable(as->clk);
1765 if (ret)
1766 return ret;
1767
1768 atmel_spi_init(as);
1769
1770 clk_disable_unprepare(as->clk);
1771
1772 if (!pm_runtime_suspended(dev)) {
1773 ret = atmel_spi_runtime_resume(dev);
1774 if (ret)
1775 return ret;
1776 }
1777
1778 /* Start the queue running */
1779 return spi_master_resume(master);
1780}
1781#endif
1782
1783static const struct dev_pm_ops atmel_spi_pm_ops = {
1784 SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
1785 SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
1786 atmel_spi_runtime_resume, NULL)
1787};
1788#define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops)
1789#else
1790#define ATMEL_SPI_PM_OPS NULL
1791#endif
1792
1793static const struct of_device_id atmel_spi_dt_ids[] = {
1794 { .compatible = "atmel,at91rm9200-spi" },
1795 { /* sentinel */ }
1796};
1797
1798MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1799
1800static struct platform_driver atmel_spi_driver = {
1801 .driver = {
1802 .name = "atmel_spi",
1803 .pm = ATMEL_SPI_PM_OPS,
1804 .of_match_table = atmel_spi_dt_ids,
1805 },
1806 .probe = atmel_spi_probe,
1807 .remove = atmel_spi_remove,
1808};
1809module_platform_driver(atmel_spi_driver);
1810
1811MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1812MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1813MODULE_LICENSE("GPL");
1814MODULE_ALIAS("platform:atmel_spi");