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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Kernel-based Virtual Machine driver for Linux
4 * cpuid support routines
5 *
6 * derived from arch/x86/kvm/x86.c
7 *
8 * Copyright 2011 Red Hat, Inc. and/or its affiliates.
9 * Copyright IBM Corporation, 2008
10 */
11
12#include <linux/kvm_host.h>
13#include <linux/export.h>
14#include <linux/vmalloc.h>
15#include <linux/uaccess.h>
16#include <linux/sched/stat.h>
17
18#include <asm/processor.h>
19#include <asm/user.h>
20#include <asm/fpu/xstate.h>
21#include <asm/sgx.h>
22#include <asm/cpuid.h>
23#include "cpuid.h"
24#include "lapic.h"
25#include "mmu.h"
26#include "trace.h"
27#include "pmu.h"
28
29/*
30 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be
31 * aligned to sizeof(unsigned long) because it's not accessed via bitops.
32 */
33u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly;
34EXPORT_SYMBOL_GPL(kvm_cpu_caps);
35
36u32 xstate_required_size(u64 xstate_bv, bool compacted)
37{
38 int feature_bit = 0;
39 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
40
41 xstate_bv &= XFEATURE_MASK_EXTEND;
42 while (xstate_bv) {
43 if (xstate_bv & 0x1) {
44 u32 eax, ebx, ecx, edx, offset;
45 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx);
46 /* ECX[1]: 64B alignment in compacted form */
47 if (compacted)
48 offset = (ecx & 0x2) ? ALIGN(ret, 64) : ret;
49 else
50 offset = ebx;
51 ret = max(ret, offset + eax);
52 }
53
54 xstate_bv >>= 1;
55 feature_bit++;
56 }
57
58 return ret;
59}
60
61/*
62 * This one is tied to SSB in the user API, and not
63 * visible in /proc/cpuinfo.
64 */
65#define KVM_X86_FEATURE_AMD_PSFD (13*32+28) /* Predictive Store Forwarding Disable */
66
67#define F feature_bit
68
69/* Scattered Flag - For features that are scattered by cpufeatures.h. */
70#define SF(name) \
71({ \
72 BUILD_BUG_ON(X86_FEATURE_##name >= MAX_CPU_FEATURES); \
73 (boot_cpu_has(X86_FEATURE_##name) ? F(name) : 0); \
74})
75
76/*
77 * Magic value used by KVM when querying userspace-provided CPUID entries and
78 * doesn't care about the CPIUD index because the index of the function in
79 * question is not significant. Note, this magic value must have at least one
80 * bit set in bits[63:32] and must be consumed as a u64 by cpuid_entry2_find()
81 * to avoid false positives when processing guest CPUID input.
82 */
83#define KVM_CPUID_INDEX_NOT_SIGNIFICANT -1ull
84
85static inline struct kvm_cpuid_entry2 *cpuid_entry2_find(
86 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u64 index)
87{
88 struct kvm_cpuid_entry2 *e;
89 int i;
90
91 for (i = 0; i < nent; i++) {
92 e = &entries[i];
93
94 if (e->function != function)
95 continue;
96
97 /*
98 * If the index isn't significant, use the first entry with a
99 * matching function. It's userspace's responsibilty to not
100 * provide "duplicate" entries in all cases.
101 */
102 if (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index)
103 return e;
104
105
106 /*
107 * Similarly, use the first matching entry if KVM is doing a
108 * lookup (as opposed to emulating CPUID) for a function that's
109 * architecturally defined as not having a significant index.
110 */
111 if (index == KVM_CPUID_INDEX_NOT_SIGNIFICANT) {
112 /*
113 * Direct lookups from KVM should not diverge from what
114 * KVM defines internally (the architectural behavior).
115 */
116 WARN_ON_ONCE(cpuid_function_is_indexed(function));
117 return e;
118 }
119 }
120
121 return NULL;
122}
123
124static int kvm_check_cpuid(struct kvm_vcpu *vcpu,
125 struct kvm_cpuid_entry2 *entries,
126 int nent)
127{
128 struct kvm_cpuid_entry2 *best;
129 u64 xfeatures;
130
131 /*
132 * The existing code assumes virtual address is 48-bit or 57-bit in the
133 * canonical address checks; exit if it is ever changed.
134 */
135 best = cpuid_entry2_find(entries, nent, 0x80000008,
136 KVM_CPUID_INDEX_NOT_SIGNIFICANT);
137 if (best) {
138 int vaddr_bits = (best->eax & 0xff00) >> 8;
139
140 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0)
141 return -EINVAL;
142 }
143
144 /*
145 * Exposing dynamic xfeatures to the guest requires additional
146 * enabling in the FPU, e.g. to expand the guest XSAVE state size.
147 */
148 best = cpuid_entry2_find(entries, nent, 0xd, 0);
149 if (!best)
150 return 0;
151
152 xfeatures = best->eax | ((u64)best->edx << 32);
153 xfeatures &= XFEATURE_MASK_USER_DYNAMIC;
154 if (!xfeatures)
155 return 0;
156
157 return fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, xfeatures);
158}
159
160/* Check whether the supplied CPUID data is equal to what is already set for the vCPU. */
161static int kvm_cpuid_check_equal(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2,
162 int nent)
163{
164 struct kvm_cpuid_entry2 *orig;
165 int i;
166
167 if (nent != vcpu->arch.cpuid_nent)
168 return -EINVAL;
169
170 for (i = 0; i < nent; i++) {
171 orig = &vcpu->arch.cpuid_entries[i];
172 if (e2[i].function != orig->function ||
173 e2[i].index != orig->index ||
174 e2[i].flags != orig->flags ||
175 e2[i].eax != orig->eax || e2[i].ebx != orig->ebx ||
176 e2[i].ecx != orig->ecx || e2[i].edx != orig->edx)
177 return -EINVAL;
178 }
179
180 return 0;
181}
182
183static void kvm_update_kvm_cpuid_base(struct kvm_vcpu *vcpu)
184{
185 u32 function;
186 struct kvm_cpuid_entry2 *entry;
187
188 vcpu->arch.kvm_cpuid_base = 0;
189
190 for_each_possible_hypervisor_cpuid_base(function) {
191 entry = kvm_find_cpuid_entry(vcpu, function);
192
193 if (entry) {
194 u32 signature[3];
195
196 signature[0] = entry->ebx;
197 signature[1] = entry->ecx;
198 signature[2] = entry->edx;
199
200 BUILD_BUG_ON(sizeof(signature) > sizeof(KVM_SIGNATURE));
201 if (!memcmp(signature, KVM_SIGNATURE, sizeof(signature))) {
202 vcpu->arch.kvm_cpuid_base = function;
203 break;
204 }
205 }
206 }
207}
208
209static struct kvm_cpuid_entry2 *__kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu,
210 struct kvm_cpuid_entry2 *entries, int nent)
211{
212 u32 base = vcpu->arch.kvm_cpuid_base;
213
214 if (!base)
215 return NULL;
216
217 return cpuid_entry2_find(entries, nent, base | KVM_CPUID_FEATURES,
218 KVM_CPUID_INDEX_NOT_SIGNIFICANT);
219}
220
221static struct kvm_cpuid_entry2 *kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu)
222{
223 return __kvm_find_kvm_cpuid_features(vcpu, vcpu->arch.cpuid_entries,
224 vcpu->arch.cpuid_nent);
225}
226
227void kvm_update_pv_runtime(struct kvm_vcpu *vcpu)
228{
229 struct kvm_cpuid_entry2 *best = kvm_find_kvm_cpuid_features(vcpu);
230
231 /*
232 * save the feature bitmap to avoid cpuid lookup for every PV
233 * operation
234 */
235 if (best)
236 vcpu->arch.pv_cpuid.features = best->eax;
237}
238
239/*
240 * Calculate guest's supported XCR0 taking into account guest CPUID data and
241 * KVM's supported XCR0 (comprised of host's XCR0 and KVM_SUPPORTED_XCR0).
242 */
243static u64 cpuid_get_supported_xcr0(struct kvm_cpuid_entry2 *entries, int nent)
244{
245 struct kvm_cpuid_entry2 *best;
246
247 best = cpuid_entry2_find(entries, nent, 0xd, 0);
248 if (!best)
249 return 0;
250
251 return (best->eax | ((u64)best->edx << 32)) & kvm_caps.supported_xcr0;
252}
253
254static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *entries,
255 int nent)
256{
257 struct kvm_cpuid_entry2 *best;
258 u64 guest_supported_xcr0 = cpuid_get_supported_xcr0(entries, nent);
259
260 best = cpuid_entry2_find(entries, nent, 1, KVM_CPUID_INDEX_NOT_SIGNIFICANT);
261 if (best) {
262 /* Update OSXSAVE bit */
263 if (boot_cpu_has(X86_FEATURE_XSAVE))
264 cpuid_entry_change(best, X86_FEATURE_OSXSAVE,
265 kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE));
266
267 cpuid_entry_change(best, X86_FEATURE_APIC,
268 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE);
269 }
270
271 best = cpuid_entry2_find(entries, nent, 7, 0);
272 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7)
273 cpuid_entry_change(best, X86_FEATURE_OSPKE,
274 kvm_read_cr4_bits(vcpu, X86_CR4_PKE));
275
276 best = cpuid_entry2_find(entries, nent, 0xD, 0);
277 if (best)
278 best->ebx = xstate_required_size(vcpu->arch.xcr0, false);
279
280 best = cpuid_entry2_find(entries, nent, 0xD, 1);
281 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) ||
282 cpuid_entry_has(best, X86_FEATURE_XSAVEC)))
283 best->ebx = xstate_required_size(vcpu->arch.xcr0, true);
284
285 best = __kvm_find_kvm_cpuid_features(vcpu, entries, nent);
286 if (kvm_hlt_in_guest(vcpu->kvm) && best &&
287 (best->eax & (1 << KVM_FEATURE_PV_UNHALT)))
288 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT);
289
290 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) {
291 best = cpuid_entry2_find(entries, nent, 0x1, KVM_CPUID_INDEX_NOT_SIGNIFICANT);
292 if (best)
293 cpuid_entry_change(best, X86_FEATURE_MWAIT,
294 vcpu->arch.ia32_misc_enable_msr &
295 MSR_IA32_MISC_ENABLE_MWAIT);
296 }
297
298 /*
299 * Bits 127:0 of the allowed SECS.ATTRIBUTES (CPUID.0x12.0x1) enumerate
300 * the supported XSAVE Feature Request Mask (XFRM), i.e. the enclave's
301 * requested XCR0 value. The enclave's XFRM must be a subset of XCRO
302 * at the time of EENTER, thus adjust the allowed XFRM by the guest's
303 * supported XCR0. Similar to XCR0 handling, FP and SSE are forced to
304 * '1' even on CPUs that don't support XSAVE.
305 */
306 best = cpuid_entry2_find(entries, nent, 0x12, 0x1);
307 if (best) {
308 best->ecx &= guest_supported_xcr0 & 0xffffffff;
309 best->edx &= guest_supported_xcr0 >> 32;
310 best->ecx |= XFEATURE_MASK_FPSSE;
311 }
312}
313
314void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu)
315{
316 __kvm_update_cpuid_runtime(vcpu, vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent);
317}
318EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime);
319
320static bool kvm_cpuid_has_hyperv(struct kvm_cpuid_entry2 *entries, int nent)
321{
322 struct kvm_cpuid_entry2 *entry;
323
324 entry = cpuid_entry2_find(entries, nent, HYPERV_CPUID_INTERFACE,
325 KVM_CPUID_INDEX_NOT_SIGNIFICANT);
326 return entry && entry->eax == HYPERV_CPUID_SIGNATURE_EAX;
327}
328
329static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
330{
331 struct kvm_lapic *apic = vcpu->arch.apic;
332 struct kvm_cpuid_entry2 *best;
333
334 best = kvm_find_cpuid_entry(vcpu, 1);
335 if (best && apic) {
336 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER))
337 apic->lapic_timer.timer_mode_mask = 3 << 17;
338 else
339 apic->lapic_timer.timer_mode_mask = 1 << 17;
340
341 kvm_apic_set_version(vcpu);
342 }
343
344 vcpu->arch.guest_supported_xcr0 =
345 cpuid_get_supported_xcr0(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent);
346
347 /*
348 * FP+SSE can always be saved/restored via KVM_{G,S}ET_XSAVE, even if
349 * XSAVE/XCRO are not exposed to the guest, and even if XSAVE isn't
350 * supported by the host.
351 */
352 vcpu->arch.guest_fpu.fpstate->user_xfeatures = vcpu->arch.guest_supported_xcr0 |
353 XFEATURE_MASK_FPSSE;
354
355 kvm_update_pv_runtime(vcpu);
356
357 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
358 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
359
360 kvm_pmu_refresh(vcpu);
361 vcpu->arch.cr4_guest_rsvd_bits =
362 __cr4_reserved_bits(guest_cpuid_has, vcpu);
363
364 kvm_hv_set_cpuid(vcpu, kvm_cpuid_has_hyperv(vcpu->arch.cpuid_entries,
365 vcpu->arch.cpuid_nent));
366
367 /* Invoke the vendor callback only after the above state is updated. */
368 static_call(kvm_x86_vcpu_after_set_cpuid)(vcpu);
369
370 /*
371 * Except for the MMU, which needs to do its thing any vendor specific
372 * adjustments to the reserved GPA bits.
373 */
374 kvm_mmu_after_set_cpuid(vcpu);
375}
376
377int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu)
378{
379 struct kvm_cpuid_entry2 *best;
380
381 best = kvm_find_cpuid_entry(vcpu, 0x80000000);
382 if (!best || best->eax < 0x80000008)
383 goto not_found;
384 best = kvm_find_cpuid_entry(vcpu, 0x80000008);
385 if (best)
386 return best->eax & 0xff;
387not_found:
388 return 36;
389}
390
391/*
392 * This "raw" version returns the reserved GPA bits without any adjustments for
393 * encryption technologies that usurp bits. The raw mask should be used if and
394 * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs.
395 */
396u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu)
397{
398 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63);
399}
400
401static int kvm_set_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2,
402 int nent)
403{
404 int r;
405
406 __kvm_update_cpuid_runtime(vcpu, e2, nent);
407
408 /*
409 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as
410 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't
411 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page
412 * faults due to reusing SPs/SPTEs. In practice no sane VMM mucks with
413 * the core vCPU model on the fly. It would've been better to forbid any
414 * KVM_SET_CPUID{,2} calls after KVM_RUN altogether but unfortunately
415 * some VMMs (e.g. QEMU) reuse vCPU fds for CPU hotplug/unplug and do
416 * KVM_SET_CPUID{,2} again. To support this legacy behavior, check
417 * whether the supplied CPUID data is equal to what's already set.
418 */
419 if (vcpu->arch.last_vmentry_cpu != -1) {
420 r = kvm_cpuid_check_equal(vcpu, e2, nent);
421 if (r)
422 return r;
423
424 kvfree(e2);
425 return 0;
426 }
427
428 if (kvm_cpuid_has_hyperv(e2, nent)) {
429 r = kvm_hv_vcpu_init(vcpu);
430 if (r)
431 return r;
432 }
433
434 r = kvm_check_cpuid(vcpu, e2, nent);
435 if (r)
436 return r;
437
438 kvfree(vcpu->arch.cpuid_entries);
439 vcpu->arch.cpuid_entries = e2;
440 vcpu->arch.cpuid_nent = nent;
441
442 kvm_update_kvm_cpuid_base(vcpu);
443 kvm_vcpu_after_set_cpuid(vcpu);
444
445 return 0;
446}
447
448/* when an old userspace process fills a new kernel module */
449int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
450 struct kvm_cpuid *cpuid,
451 struct kvm_cpuid_entry __user *entries)
452{
453 int r, i;
454 struct kvm_cpuid_entry *e = NULL;
455 struct kvm_cpuid_entry2 *e2 = NULL;
456
457 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
458 return -E2BIG;
459
460 if (cpuid->nent) {
461 e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent));
462 if (IS_ERR(e))
463 return PTR_ERR(e);
464
465 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT);
466 if (!e2) {
467 r = -ENOMEM;
468 goto out_free_cpuid;
469 }
470 }
471 for (i = 0; i < cpuid->nent; i++) {
472 e2[i].function = e[i].function;
473 e2[i].eax = e[i].eax;
474 e2[i].ebx = e[i].ebx;
475 e2[i].ecx = e[i].ecx;
476 e2[i].edx = e[i].edx;
477 e2[i].index = 0;
478 e2[i].flags = 0;
479 e2[i].padding[0] = 0;
480 e2[i].padding[1] = 0;
481 e2[i].padding[2] = 0;
482 }
483
484 r = kvm_set_cpuid(vcpu, e2, cpuid->nent);
485 if (r)
486 kvfree(e2);
487
488out_free_cpuid:
489 kvfree(e);
490
491 return r;
492}
493
494int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
495 struct kvm_cpuid2 *cpuid,
496 struct kvm_cpuid_entry2 __user *entries)
497{
498 struct kvm_cpuid_entry2 *e2 = NULL;
499 int r;
500
501 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
502 return -E2BIG;
503
504 if (cpuid->nent) {
505 e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent));
506 if (IS_ERR(e2))
507 return PTR_ERR(e2);
508 }
509
510 r = kvm_set_cpuid(vcpu, e2, cpuid->nent);
511 if (r)
512 kvfree(e2);
513
514 return r;
515}
516
517int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
518 struct kvm_cpuid2 *cpuid,
519 struct kvm_cpuid_entry2 __user *entries)
520{
521 int r;
522
523 r = -E2BIG;
524 if (cpuid->nent < vcpu->arch.cpuid_nent)
525 goto out;
526 r = -EFAULT;
527 if (copy_to_user(entries, vcpu->arch.cpuid_entries,
528 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
529 goto out;
530 return 0;
531
532out:
533 cpuid->nent = vcpu->arch.cpuid_nent;
534 return r;
535}
536
537/* Mask kvm_cpu_caps for @leaf with the raw CPUID capabilities of this CPU. */
538static __always_inline void __kvm_cpu_cap_mask(unsigned int leaf)
539{
540 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32);
541 struct kvm_cpuid_entry2 entry;
542
543 reverse_cpuid_check(leaf);
544
545 cpuid_count(cpuid.function, cpuid.index,
546 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx);
547
548 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg);
549}
550
551static __always_inline
552void kvm_cpu_cap_init_kvm_defined(enum kvm_only_cpuid_leafs leaf, u32 mask)
553{
554 /* Use kvm_cpu_cap_mask for leafs that aren't KVM-only. */
555 BUILD_BUG_ON(leaf < NCAPINTS);
556
557 kvm_cpu_caps[leaf] = mask;
558
559 __kvm_cpu_cap_mask(leaf);
560}
561
562static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask)
563{
564 /* Use kvm_cpu_cap_init_kvm_defined for KVM-only leafs. */
565 BUILD_BUG_ON(leaf >= NCAPINTS);
566
567 kvm_cpu_caps[leaf] &= mask;
568
569 __kvm_cpu_cap_mask(leaf);
570}
571
572void kvm_set_cpu_caps(void)
573{
574#ifdef CONFIG_X86_64
575 unsigned int f_gbpages = F(GBPAGES);
576 unsigned int f_lm = F(LM);
577 unsigned int f_xfd = F(XFD);
578#else
579 unsigned int f_gbpages = 0;
580 unsigned int f_lm = 0;
581 unsigned int f_xfd = 0;
582#endif
583 memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps));
584
585 BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)) >
586 sizeof(boot_cpu_data.x86_capability));
587
588 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability,
589 sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)));
590
591 kvm_cpu_cap_mask(CPUID_1_ECX,
592 /*
593 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not*
594 * advertised to guests via CPUID!
595 */
596 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
597 0 /* DS-CPL, VMX, SMX, EST */ |
598 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
599 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) |
600 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) |
601 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
602 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
603 F(F16C) | F(RDRAND)
604 );
605 /* KVM emulates x2apic in software irrespective of host support. */
606 kvm_cpu_cap_set(X86_FEATURE_X2APIC);
607
608 kvm_cpu_cap_mask(CPUID_1_EDX,
609 F(FPU) | F(VME) | F(DE) | F(PSE) |
610 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
611 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
612 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
613 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) |
614 0 /* Reserved, DS, ACPI */ | F(MMX) |
615 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
616 0 /* HTT, TM, Reserved, PBE */
617 );
618
619 kvm_cpu_cap_mask(CPUID_7_0_EBX,
620 F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) |
621 F(FDP_EXCPTN_ONLY) | F(SMEP) | F(BMI2) | F(ERMS) | F(INVPCID) |
622 F(RTM) | F(ZERO_FCS_FDS) | 0 /*MPX*/ | F(AVX512F) |
623 F(AVX512DQ) | F(RDSEED) | F(ADX) | F(SMAP) | F(AVX512IFMA) |
624 F(CLFLUSHOPT) | F(CLWB) | 0 /*INTEL_PT*/ | F(AVX512PF) |
625 F(AVX512ER) | F(AVX512CD) | F(SHA_NI) | F(AVX512BW) |
626 F(AVX512VL));
627
628 kvm_cpu_cap_mask(CPUID_7_ECX,
629 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) |
630 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) |
631 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) |
632 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ |
633 F(SGX_LC) | F(BUS_LOCK_DETECT)
634 );
635 /* Set LA57 based on hardware capability. */
636 if (cpuid_ecx(7) & F(LA57))
637 kvm_cpu_cap_set(X86_FEATURE_LA57);
638
639 /*
640 * PKU not yet implemented for shadow paging and requires OSPKE
641 * to be set on the host. Clear it if that is not the case
642 */
643 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE))
644 kvm_cpu_cap_clear(X86_FEATURE_PKU);
645
646 kvm_cpu_cap_mask(CPUID_7_EDX,
647 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
648 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
649 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
650 F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) |
651 F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16)
652 );
653
654 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
655 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST);
656 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES);
657
658 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS))
659 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL);
660 if (boot_cpu_has(X86_FEATURE_STIBP))
661 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP);
662 if (boot_cpu_has(X86_FEATURE_AMD_SSBD))
663 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
664
665 kvm_cpu_cap_mask(CPUID_7_1_EAX,
666 F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | F(AMX_FP16) |
667 F(AVX_IFMA)
668 );
669
670 kvm_cpu_cap_init_kvm_defined(CPUID_7_1_EDX,
671 F(AVX_VNNI_INT8) | F(AVX_NE_CONVERT) | F(PREFETCHITI)
672 );
673
674 kvm_cpu_cap_mask(CPUID_D_1_EAX,
675 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd
676 );
677
678 kvm_cpu_cap_init_kvm_defined(CPUID_12_EAX,
679 SF(SGX1) | SF(SGX2) | SF(SGX_EDECCSSA)
680 );
681
682 kvm_cpu_cap_mask(CPUID_8000_0001_ECX,
683 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
684 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
685 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) |
686 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) |
687 F(TOPOEXT) | 0 /* PERFCTR_CORE */
688 );
689
690 kvm_cpu_cap_mask(CPUID_8000_0001_EDX,
691 F(FPU) | F(VME) | F(DE) | F(PSE) |
692 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
693 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
694 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
695 F(PAT) | F(PSE36) | 0 /* Reserved */ |
696 F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
697 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) |
698 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW)
699 );
700
701 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64))
702 kvm_cpu_cap_set(X86_FEATURE_GBPAGES);
703
704 kvm_cpu_cap_mask(CPUID_8000_0008_EBX,
705 F(CLZERO) | F(XSAVEERPTR) |
706 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) |
707 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) |
708 __feature_bit(KVM_X86_FEATURE_AMD_PSFD)
709 );
710
711 /*
712 * AMD has separate bits for each SPEC_CTRL bit.
713 * arch/x86/kernel/cpu/bugs.c is kind enough to
714 * record that in cpufeatures so use them.
715 */
716 if (boot_cpu_has(X86_FEATURE_IBPB))
717 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB);
718 if (boot_cpu_has(X86_FEATURE_IBRS))
719 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS);
720 if (boot_cpu_has(X86_FEATURE_STIBP))
721 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP);
722 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
723 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD);
724 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
725 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO);
726 /*
727 * The preference is to use SPEC CTRL MSR instead of the
728 * VIRT_SPEC MSR.
729 */
730 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
731 !boot_cpu_has(X86_FEATURE_AMD_SSBD))
732 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
733
734 /*
735 * Hide all SVM features by default, SVM will set the cap bits for
736 * features it emulates and/or exposes for L1.
737 */
738 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0);
739
740 kvm_cpu_cap_mask(CPUID_8000_001F_EAX,
741 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) |
742 F(SME_COHERENT));
743
744 kvm_cpu_cap_mask(CPUID_C000_0001_EDX,
745 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
746 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
747 F(PMM) | F(PMM_EN)
748 );
749
750 /*
751 * Hide RDTSCP and RDPID if either feature is reported as supported but
752 * probing MSR_TSC_AUX failed. This is purely a sanity check and
753 * should never happen, but the guest will likely crash if RDTSCP or
754 * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in
755 * the past. For example, the sanity check may fire if this instance of
756 * KVM is running as L1 on top of an older, broken KVM.
757 */
758 if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) ||
759 kvm_cpu_cap_has(X86_FEATURE_RDPID)) &&
760 !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) {
761 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
762 kvm_cpu_cap_clear(X86_FEATURE_RDPID);
763 }
764}
765EXPORT_SYMBOL_GPL(kvm_set_cpu_caps);
766
767struct kvm_cpuid_array {
768 struct kvm_cpuid_entry2 *entries;
769 int maxnent;
770 int nent;
771};
772
773static struct kvm_cpuid_entry2 *get_next_cpuid(struct kvm_cpuid_array *array)
774{
775 if (array->nent >= array->maxnent)
776 return NULL;
777
778 return &array->entries[array->nent++];
779}
780
781static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array,
782 u32 function, u32 index)
783{
784 struct kvm_cpuid_entry2 *entry = get_next_cpuid(array);
785
786 if (!entry)
787 return NULL;
788
789 memset(entry, 0, sizeof(*entry));
790 entry->function = function;
791 entry->index = index;
792 switch (function & 0xC0000000) {
793 case 0x40000000:
794 /* Hypervisor leaves are always synthesized by __do_cpuid_func. */
795 return entry;
796
797 case 0x80000000:
798 /*
799 * 0x80000021 is sometimes synthesized by __do_cpuid_func, which
800 * would result in out-of-bounds calls to do_host_cpuid.
801 */
802 {
803 static int max_cpuid_80000000;
804 if (!READ_ONCE(max_cpuid_80000000))
805 WRITE_ONCE(max_cpuid_80000000, cpuid_eax(0x80000000));
806 if (function > READ_ONCE(max_cpuid_80000000))
807 return entry;
808 }
809 break;
810
811 default:
812 break;
813 }
814
815 cpuid_count(entry->function, entry->index,
816 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
817
818 if (cpuid_function_is_indexed(function))
819 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
820
821 return entry;
822}
823
824static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func)
825{
826 struct kvm_cpuid_entry2 *entry;
827
828 if (array->nent >= array->maxnent)
829 return -E2BIG;
830
831 entry = &array->entries[array->nent];
832 entry->function = func;
833 entry->index = 0;
834 entry->flags = 0;
835
836 switch (func) {
837 case 0:
838 entry->eax = 7;
839 ++array->nent;
840 break;
841 case 1:
842 entry->ecx = F(MOVBE);
843 ++array->nent;
844 break;
845 case 7:
846 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
847 entry->eax = 0;
848 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
849 entry->ecx = F(RDPID);
850 ++array->nent;
851 break;
852 default:
853 break;
854 }
855
856 return 0;
857}
858
859static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
860{
861 struct kvm_cpuid_entry2 *entry;
862 int r, i, max_idx;
863
864 /* all calls to cpuid_count() should be made on the same cpu */
865 get_cpu();
866
867 r = -E2BIG;
868
869 entry = do_host_cpuid(array, function, 0);
870 if (!entry)
871 goto out;
872
873 switch (function) {
874 case 0:
875 /* Limited to the highest leaf implemented in KVM. */
876 entry->eax = min(entry->eax, 0x1fU);
877 break;
878 case 1:
879 cpuid_entry_override(entry, CPUID_1_EDX);
880 cpuid_entry_override(entry, CPUID_1_ECX);
881 break;
882 case 2:
883 /*
884 * On ancient CPUs, function 2 entries are STATEFUL. That is,
885 * CPUID(function=2, index=0) may return different results each
886 * time, with the least-significant byte in EAX enumerating the
887 * number of times software should do CPUID(2, 0).
888 *
889 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less
890 * idiotic. Intel's SDM states that EAX & 0xff "will always
891 * return 01H. Software should ignore this value and not
892 * interpret it as an informational descriptor", while AMD's
893 * APM states that CPUID(2) is reserved.
894 *
895 * WARN if a frankenstein CPU that supports virtualization and
896 * a stateful CPUID.0x2 is encountered.
897 */
898 WARN_ON_ONCE((entry->eax & 0xff) > 1);
899 break;
900 /* functions 4 and 0x8000001d have additional index. */
901 case 4:
902 case 0x8000001d:
903 /*
904 * Read entries until the cache type in the previous entry is
905 * zero, i.e. indicates an invalid entry.
906 */
907 for (i = 1; entry->eax & 0x1f; ++i) {
908 entry = do_host_cpuid(array, function, i);
909 if (!entry)
910 goto out;
911 }
912 break;
913 case 6: /* Thermal management */
914 entry->eax = 0x4; /* allow ARAT */
915 entry->ebx = 0;
916 entry->ecx = 0;
917 entry->edx = 0;
918 break;
919 /* function 7 has additional index. */
920 case 7:
921 entry->eax = min(entry->eax, 1u);
922 cpuid_entry_override(entry, CPUID_7_0_EBX);
923 cpuid_entry_override(entry, CPUID_7_ECX);
924 cpuid_entry_override(entry, CPUID_7_EDX);
925
926 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */
927 if (entry->eax == 1) {
928 entry = do_host_cpuid(array, function, 1);
929 if (!entry)
930 goto out;
931
932 cpuid_entry_override(entry, CPUID_7_1_EAX);
933 cpuid_entry_override(entry, CPUID_7_1_EDX);
934 entry->ebx = 0;
935 entry->ecx = 0;
936 }
937 break;
938 case 0xa: { /* Architectural Performance Monitoring */
939 union cpuid10_eax eax;
940 union cpuid10_edx edx;
941
942 if (!static_cpu_has(X86_FEATURE_ARCH_PERFMON)) {
943 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
944 break;
945 }
946
947 eax.split.version_id = kvm_pmu_cap.version;
948 eax.split.num_counters = kvm_pmu_cap.num_counters_gp;
949 eax.split.bit_width = kvm_pmu_cap.bit_width_gp;
950 eax.split.mask_length = kvm_pmu_cap.events_mask_len;
951 edx.split.num_counters_fixed = kvm_pmu_cap.num_counters_fixed;
952 edx.split.bit_width_fixed = kvm_pmu_cap.bit_width_fixed;
953
954 if (kvm_pmu_cap.version)
955 edx.split.anythread_deprecated = 1;
956 edx.split.reserved1 = 0;
957 edx.split.reserved2 = 0;
958
959 entry->eax = eax.full;
960 entry->ebx = kvm_pmu_cap.events_mask;
961 entry->ecx = 0;
962 entry->edx = edx.full;
963 break;
964 }
965 case 0x1f:
966 case 0xb:
967 /*
968 * No topology; a valid topology is indicated by the presence
969 * of subleaf 1.
970 */
971 entry->eax = entry->ebx = entry->ecx = 0;
972 break;
973 case 0xd: {
974 u64 permitted_xcr0 = kvm_caps.supported_xcr0 & xstate_get_guest_group_perm();
975 u64 permitted_xss = kvm_caps.supported_xss;
976
977 entry->eax &= permitted_xcr0;
978 entry->ebx = xstate_required_size(permitted_xcr0, false);
979 entry->ecx = entry->ebx;
980 entry->edx &= permitted_xcr0 >> 32;
981 if (!permitted_xcr0)
982 break;
983
984 entry = do_host_cpuid(array, function, 1);
985 if (!entry)
986 goto out;
987
988 cpuid_entry_override(entry, CPUID_D_1_EAX);
989 if (entry->eax & (F(XSAVES)|F(XSAVEC)))
990 entry->ebx = xstate_required_size(permitted_xcr0 | permitted_xss,
991 true);
992 else {
993 WARN_ON_ONCE(permitted_xss != 0);
994 entry->ebx = 0;
995 }
996 entry->ecx &= permitted_xss;
997 entry->edx &= permitted_xss >> 32;
998
999 for (i = 2; i < 64; ++i) {
1000 bool s_state;
1001 if (permitted_xcr0 & BIT_ULL(i))
1002 s_state = false;
1003 else if (permitted_xss & BIT_ULL(i))
1004 s_state = true;
1005 else
1006 continue;
1007
1008 entry = do_host_cpuid(array, function, i);
1009 if (!entry)
1010 goto out;
1011
1012 /*
1013 * The supported check above should have filtered out
1014 * invalid sub-leafs. Only valid sub-leafs should
1015 * reach this point, and they should have a non-zero
1016 * save state size. Furthermore, check whether the
1017 * processor agrees with permitted_xcr0/permitted_xss
1018 * on whether this is an XCR0- or IA32_XSS-managed area.
1019 */
1020 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) {
1021 --array->nent;
1022 continue;
1023 }
1024
1025 if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
1026 entry->ecx &= ~BIT_ULL(2);
1027 entry->edx = 0;
1028 }
1029 break;
1030 }
1031 case 0x12:
1032 /* Intel SGX */
1033 if (!kvm_cpu_cap_has(X86_FEATURE_SGX)) {
1034 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1035 break;
1036 }
1037
1038 /*
1039 * Index 0: Sub-features, MISCSELECT (a.k.a extended features)
1040 * and max enclave sizes. The SGX sub-features and MISCSELECT
1041 * are restricted by kernel and KVM capabilities (like most
1042 * feature flags), while enclave size is unrestricted.
1043 */
1044 cpuid_entry_override(entry, CPUID_12_EAX);
1045 entry->ebx &= SGX_MISC_EXINFO;
1046
1047 entry = do_host_cpuid(array, function, 1);
1048 if (!entry)
1049 goto out;
1050
1051 /*
1052 * Index 1: SECS.ATTRIBUTES. ATTRIBUTES are restricted a la
1053 * feature flags. Advertise all supported flags, including
1054 * privileged attributes that require explicit opt-in from
1055 * userspace. ATTRIBUTES.XFRM is not adjusted as userspace is
1056 * expected to derive it from supported XCR0.
1057 */
1058 entry->eax &= SGX_ATTR_PRIV_MASK | SGX_ATTR_UNPRIV_MASK;
1059 entry->ebx &= 0;
1060 break;
1061 /* Intel PT */
1062 case 0x14:
1063 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) {
1064 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1065 break;
1066 }
1067
1068 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) {
1069 if (!do_host_cpuid(array, function, i))
1070 goto out;
1071 }
1072 break;
1073 /* Intel AMX TILE */
1074 case 0x1d:
1075 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) {
1076 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1077 break;
1078 }
1079
1080 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) {
1081 if (!do_host_cpuid(array, function, i))
1082 goto out;
1083 }
1084 break;
1085 case 0x1e: /* TMUL information */
1086 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) {
1087 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1088 break;
1089 }
1090 break;
1091 case KVM_CPUID_SIGNATURE: {
1092 const u32 *sigptr = (const u32 *)KVM_SIGNATURE;
1093 entry->eax = KVM_CPUID_FEATURES;
1094 entry->ebx = sigptr[0];
1095 entry->ecx = sigptr[1];
1096 entry->edx = sigptr[2];
1097 break;
1098 }
1099 case KVM_CPUID_FEATURES:
1100 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
1101 (1 << KVM_FEATURE_NOP_IO_DELAY) |
1102 (1 << KVM_FEATURE_CLOCKSOURCE2) |
1103 (1 << KVM_FEATURE_ASYNC_PF) |
1104 (1 << KVM_FEATURE_PV_EOI) |
1105 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) |
1106 (1 << KVM_FEATURE_PV_UNHALT) |
1107 (1 << KVM_FEATURE_PV_TLB_FLUSH) |
1108 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) |
1109 (1 << KVM_FEATURE_PV_SEND_IPI) |
1110 (1 << KVM_FEATURE_POLL_CONTROL) |
1111 (1 << KVM_FEATURE_PV_SCHED_YIELD) |
1112 (1 << KVM_FEATURE_ASYNC_PF_INT);
1113
1114 if (sched_info_on())
1115 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
1116
1117 entry->ebx = 0;
1118 entry->ecx = 0;
1119 entry->edx = 0;
1120 break;
1121 case 0x80000000:
1122 entry->eax = min(entry->eax, 0x80000021);
1123 /*
1124 * Serializing LFENCE is reported in a multitude of ways, and
1125 * NullSegClearsBase is not reported in CPUID on Zen2; help
1126 * userspace by providing the CPUID leaf ourselves.
1127 *
1128 * However, only do it if the host has CPUID leaf 0x8000001d.
1129 * QEMU thinks that it can query the host blindly for that
1130 * CPUID leaf if KVM reports that it supports 0x8000001d or
1131 * above. The processor merrily returns values from the
1132 * highest Intel leaf which QEMU tries to use as the guest's
1133 * 0x8000001d. Even worse, this can result in an infinite
1134 * loop if said highest leaf has no subleaves indexed by ECX.
1135 */
1136 if (entry->eax >= 0x8000001d &&
1137 (static_cpu_has(X86_FEATURE_LFENCE_RDTSC)
1138 || !static_cpu_has_bug(X86_BUG_NULL_SEG)))
1139 entry->eax = max(entry->eax, 0x80000021);
1140 break;
1141 case 0x80000001:
1142 entry->ebx &= ~GENMASK(27, 16);
1143 cpuid_entry_override(entry, CPUID_8000_0001_EDX);
1144 cpuid_entry_override(entry, CPUID_8000_0001_ECX);
1145 break;
1146 case 0x80000006:
1147 /* Drop reserved bits, pass host L2 cache and TLB info. */
1148 entry->edx &= ~GENMASK(17, 16);
1149 break;
1150 case 0x80000007: /* Advanced power management */
1151 /* invariant TSC is CPUID.80000007H:EDX[8] */
1152 entry->edx &= (1 << 8);
1153 /* mask against host */
1154 entry->edx &= boot_cpu_data.x86_power;
1155 entry->eax = entry->ebx = entry->ecx = 0;
1156 break;
1157 case 0x80000008: {
1158 unsigned g_phys_as = (entry->eax >> 16) & 0xff;
1159 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
1160 unsigned phys_as = entry->eax & 0xff;
1161
1162 /*
1163 * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as
1164 * the guest operates in the same PA space as the host, i.e.
1165 * reductions in MAXPHYADDR for memory encryption affect shadow
1166 * paging, too.
1167 *
1168 * If TDP is enabled but an explicit guest MAXPHYADDR is not
1169 * provided, use the raw bare metal MAXPHYADDR as reductions to
1170 * the HPAs do not affect GPAs.
1171 */
1172 if (!tdp_enabled)
1173 g_phys_as = boot_cpu_data.x86_phys_bits;
1174 else if (!g_phys_as)
1175 g_phys_as = phys_as;
1176
1177 entry->eax = g_phys_as | (virt_as << 8);
1178 entry->ecx &= ~(GENMASK(31, 16) | GENMASK(11, 8));
1179 entry->edx = 0;
1180 cpuid_entry_override(entry, CPUID_8000_0008_EBX);
1181 break;
1182 }
1183 case 0x8000000A:
1184 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) {
1185 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1186 break;
1187 }
1188 entry->eax = 1; /* SVM revision 1 */
1189 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
1190 ASID emulation to nested SVM */
1191 entry->ecx = 0; /* Reserved */
1192 cpuid_entry_override(entry, CPUID_8000_000A_EDX);
1193 break;
1194 case 0x80000019:
1195 entry->ecx = entry->edx = 0;
1196 break;
1197 case 0x8000001a:
1198 entry->eax &= GENMASK(2, 0);
1199 entry->ebx = entry->ecx = entry->edx = 0;
1200 break;
1201 case 0x8000001e:
1202 /* Do not return host topology information. */
1203 entry->eax = entry->ebx = entry->ecx = 0;
1204 entry->edx = 0; /* reserved */
1205 break;
1206 case 0x8000001F:
1207 if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) {
1208 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1209 } else {
1210 cpuid_entry_override(entry, CPUID_8000_001F_EAX);
1211 /* Clear NumVMPL since KVM does not support VMPL. */
1212 entry->ebx &= ~GENMASK(31, 12);
1213 /*
1214 * Enumerate '0' for "PA bits reduction", the adjusted
1215 * MAXPHYADDR is enumerated directly (see 0x80000008).
1216 */
1217 entry->ebx &= ~GENMASK(11, 6);
1218 }
1219 break;
1220 case 0x80000020:
1221 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1222 break;
1223 case 0x80000021:
1224 entry->ebx = entry->ecx = entry->edx = 0;
1225 /*
1226 * Pass down these bits:
1227 * EAX 0 NNDBP, Processor ignores nested data breakpoints
1228 * EAX 2 LAS, LFENCE always serializing
1229 * EAX 6 NSCB, Null selector clear base
1230 *
1231 * Other defined bits are for MSRs that KVM does not expose:
1232 * EAX 3 SPCL, SMM page configuration lock
1233 * EAX 13 PCMSR, Prefetch control MSR
1234 *
1235 * KVM doesn't support SMM_CTL.
1236 * EAX 9 SMM_CTL MSR is not supported
1237 */
1238 entry->eax &= BIT(0) | BIT(2) | BIT(6);
1239 entry->eax |= BIT(9);
1240 if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC))
1241 entry->eax |= BIT(2);
1242 if (!static_cpu_has_bug(X86_BUG_NULL_SEG))
1243 entry->eax |= BIT(6);
1244 break;
1245 /*Add support for Centaur's CPUID instruction*/
1246 case 0xC0000000:
1247 /*Just support up to 0xC0000004 now*/
1248 entry->eax = min(entry->eax, 0xC0000004);
1249 break;
1250 case 0xC0000001:
1251 cpuid_entry_override(entry, CPUID_C000_0001_EDX);
1252 break;
1253 case 3: /* Processor serial number */
1254 case 5: /* MONITOR/MWAIT */
1255 case 0xC0000002:
1256 case 0xC0000003:
1257 case 0xC0000004:
1258 default:
1259 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1260 break;
1261 }
1262
1263 r = 0;
1264
1265out:
1266 put_cpu();
1267
1268 return r;
1269}
1270
1271static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func,
1272 unsigned int type)
1273{
1274 if (type == KVM_GET_EMULATED_CPUID)
1275 return __do_cpuid_func_emulated(array, func);
1276
1277 return __do_cpuid_func(array, func);
1278}
1279
1280#define CENTAUR_CPUID_SIGNATURE 0xC0000000
1281
1282static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func,
1283 unsigned int type)
1284{
1285 u32 limit;
1286 int r;
1287
1288 if (func == CENTAUR_CPUID_SIGNATURE &&
1289 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR)
1290 return 0;
1291
1292 r = do_cpuid_func(array, func, type);
1293 if (r)
1294 return r;
1295
1296 limit = array->entries[array->nent - 1].eax;
1297 for (func = func + 1; func <= limit; ++func) {
1298 r = do_cpuid_func(array, func, type);
1299 if (r)
1300 break;
1301 }
1302
1303 return r;
1304}
1305
1306static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries,
1307 __u32 num_entries, unsigned int ioctl_type)
1308{
1309 int i;
1310 __u32 pad[3];
1311
1312 if (ioctl_type != KVM_GET_EMULATED_CPUID)
1313 return false;
1314
1315 /*
1316 * We want to make sure that ->padding is being passed clean from
1317 * userspace in case we want to use it for something in the future.
1318 *
1319 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we
1320 * have to give ourselves satisfied only with the emulated side. /me
1321 * sheds a tear.
1322 */
1323 for (i = 0; i < num_entries; i++) {
1324 if (copy_from_user(pad, entries[i].padding, sizeof(pad)))
1325 return true;
1326
1327 if (pad[0] || pad[1] || pad[2])
1328 return true;
1329 }
1330 return false;
1331}
1332
1333int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid,
1334 struct kvm_cpuid_entry2 __user *entries,
1335 unsigned int type)
1336{
1337 static const u32 funcs[] = {
1338 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE,
1339 };
1340
1341 struct kvm_cpuid_array array = {
1342 .nent = 0,
1343 };
1344 int r, i;
1345
1346 if (cpuid->nent < 1)
1347 return -E2BIG;
1348 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1349 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
1350
1351 if (sanity_check_entries(entries, cpuid->nent, type))
1352 return -EINVAL;
1353
1354 array.entries = kvcalloc(cpuid->nent, sizeof(struct kvm_cpuid_entry2), GFP_KERNEL);
1355 if (!array.entries)
1356 return -ENOMEM;
1357
1358 array.maxnent = cpuid->nent;
1359
1360 for (i = 0; i < ARRAY_SIZE(funcs); i++) {
1361 r = get_cpuid_func(&array, funcs[i], type);
1362 if (r)
1363 goto out_free;
1364 }
1365 cpuid->nent = array.nent;
1366
1367 if (copy_to_user(entries, array.entries,
1368 array.nent * sizeof(struct kvm_cpuid_entry2)))
1369 r = -EFAULT;
1370
1371out_free:
1372 kvfree(array.entries);
1373 return r;
1374}
1375
1376struct kvm_cpuid_entry2 *kvm_find_cpuid_entry_index(struct kvm_vcpu *vcpu,
1377 u32 function, u32 index)
1378{
1379 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent,
1380 function, index);
1381}
1382EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry_index);
1383
1384struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
1385 u32 function)
1386{
1387 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent,
1388 function, KVM_CPUID_INDEX_NOT_SIGNIFICANT);
1389}
1390EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
1391
1392/*
1393 * Intel CPUID semantics treats any query for an out-of-range leaf as if the
1394 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics
1395 * returns all zeroes for any undefined leaf, whether or not the leaf is in
1396 * range. Centaur/VIA follows Intel semantics.
1397 *
1398 * A leaf is considered out-of-range if its function is higher than the maximum
1399 * supported leaf of its associated class or if its associated class does not
1400 * exist.
1401 *
1402 * There are three primary classes to be considered, with their respective
1403 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary
1404 * class exists if a guest CPUID entry for its <base> leaf exists. For a given
1405 * class, CPUID.<base>.EAX contains the max supported leaf for the class.
1406 *
1407 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff
1408 * - Hypervisor: 0x40000000 - 0x4fffffff
1409 * - Extended: 0x80000000 - 0xbfffffff
1410 * - Centaur: 0xc0000000 - 0xcfffffff
1411 *
1412 * The Hypervisor class is further subdivided into sub-classes that each act as
1413 * their own independent class associated with a 0x100 byte range. E.g. if Qemu
1414 * is advertising support for both HyperV and KVM, the resulting Hypervisor
1415 * CPUID sub-classes are:
1416 *
1417 * - HyperV: 0x40000000 - 0x400000ff
1418 * - KVM: 0x40000100 - 0x400001ff
1419 */
1420static struct kvm_cpuid_entry2 *
1421get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index)
1422{
1423 struct kvm_cpuid_entry2 *basic, *class;
1424 u32 function = *fn_ptr;
1425
1426 basic = kvm_find_cpuid_entry(vcpu, 0);
1427 if (!basic)
1428 return NULL;
1429
1430 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) ||
1431 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx))
1432 return NULL;
1433
1434 if (function >= 0x40000000 && function <= 0x4fffffff)
1435 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00);
1436 else if (function >= 0xc0000000)
1437 class = kvm_find_cpuid_entry(vcpu, 0xc0000000);
1438 else
1439 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000);
1440
1441 if (class && function <= class->eax)
1442 return NULL;
1443
1444 /*
1445 * Leaf specific adjustments are also applied when redirecting to the
1446 * max basic entry, e.g. if the max basic leaf is 0xb but there is no
1447 * entry for CPUID.0xb.index (see below), then the output value for EDX
1448 * needs to be pulled from CPUID.0xb.1.
1449 */
1450 *fn_ptr = basic->eax;
1451
1452 /*
1453 * The class does not exist or the requested function is out of range;
1454 * the effective CPUID entry is the max basic leaf. Note, the index of
1455 * the original requested leaf is observed!
1456 */
1457 return kvm_find_cpuid_entry_index(vcpu, basic->eax, index);
1458}
1459
1460bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx,
1461 u32 *ecx, u32 *edx, bool exact_only)
1462{
1463 u32 orig_function = *eax, function = *eax, index = *ecx;
1464 struct kvm_cpuid_entry2 *entry;
1465 bool exact, used_max_basic = false;
1466
1467 entry = kvm_find_cpuid_entry_index(vcpu, function, index);
1468 exact = !!entry;
1469
1470 if (!entry && !exact_only) {
1471 entry = get_out_of_range_cpuid_entry(vcpu, &function, index);
1472 used_max_basic = !!entry;
1473 }
1474
1475 if (entry) {
1476 *eax = entry->eax;
1477 *ebx = entry->ebx;
1478 *ecx = entry->ecx;
1479 *edx = entry->edx;
1480 if (function == 7 && index == 0) {
1481 u64 data;
1482 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) &&
1483 (data & TSX_CTRL_CPUID_CLEAR))
1484 *ebx &= ~(F(RTM) | F(HLE));
1485 }
1486 } else {
1487 *eax = *ebx = *ecx = *edx = 0;
1488 /*
1489 * When leaf 0BH or 1FH is defined, CL is pass-through
1490 * and EDX is always the x2APIC ID, even for undefined
1491 * subleaves. Index 1 will exist iff the leaf is
1492 * implemented, so we pass through CL iff leaf 1
1493 * exists. EDX can be copied from any existing index.
1494 */
1495 if (function == 0xb || function == 0x1f) {
1496 entry = kvm_find_cpuid_entry_index(vcpu, function, 1);
1497 if (entry) {
1498 *ecx = index & 0xff;
1499 *edx = entry->edx;
1500 }
1501 }
1502 }
1503 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact,
1504 used_max_basic);
1505 return exact;
1506}
1507EXPORT_SYMBOL_GPL(kvm_cpuid);
1508
1509int kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
1510{
1511 u32 eax, ebx, ecx, edx;
1512
1513 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0))
1514 return 1;
1515
1516 eax = kvm_rax_read(vcpu);
1517 ecx = kvm_rcx_read(vcpu);
1518 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false);
1519 kvm_rax_write(vcpu, eax);
1520 kvm_rbx_write(vcpu, ebx);
1521 kvm_rcx_write(vcpu, ecx);
1522 kvm_rdx_write(vcpu, edx);
1523 return kvm_skip_emulated_instruction(vcpu);
1524}
1525EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Kernel-based Virtual Machine driver for Linux
4 * cpuid support routines
5 *
6 * derived from arch/x86/kvm/x86.c
7 *
8 * Copyright 2011 Red Hat, Inc. and/or its affiliates.
9 * Copyright IBM Corporation, 2008
10 */
11
12#include <linux/kvm_host.h>
13#include <linux/export.h>
14#include <linux/vmalloc.h>
15#include <linux/uaccess.h>
16#include <linux/sched/stat.h>
17
18#include <asm/processor.h>
19#include <asm/user.h>
20#include <asm/fpu/xstate.h>
21#include "cpuid.h"
22#include "lapic.h"
23#include "mmu.h"
24#include "trace.h"
25#include "pmu.h"
26
27/*
28 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be
29 * aligned to sizeof(unsigned long) because it's not accessed via bitops.
30 */
31u32 kvm_cpu_caps[NCAPINTS] __read_mostly;
32EXPORT_SYMBOL_GPL(kvm_cpu_caps);
33
34static u32 xstate_required_size(u64 xstate_bv, bool compacted)
35{
36 int feature_bit = 0;
37 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
38
39 xstate_bv &= XFEATURE_MASK_EXTEND;
40 while (xstate_bv) {
41 if (xstate_bv & 0x1) {
42 u32 eax, ebx, ecx, edx, offset;
43 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx);
44 offset = compacted ? ret : ebx;
45 ret = max(ret, offset + eax);
46 }
47
48 xstate_bv >>= 1;
49 feature_bit++;
50 }
51
52 return ret;
53}
54
55#define F feature_bit
56
57static int kvm_check_cpuid(struct kvm_vcpu *vcpu)
58{
59 struct kvm_cpuid_entry2 *best;
60
61 /*
62 * The existing code assumes virtual address is 48-bit or 57-bit in the
63 * canonical address checks; exit if it is ever changed.
64 */
65 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
66 if (best) {
67 int vaddr_bits = (best->eax & 0xff00) >> 8;
68
69 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0)
70 return -EINVAL;
71 }
72
73 return 0;
74}
75
76void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu)
77{
78 struct kvm_cpuid_entry2 *best;
79
80 best = kvm_find_cpuid_entry(vcpu, 1, 0);
81 if (best) {
82 /* Update OSXSAVE bit */
83 if (boot_cpu_has(X86_FEATURE_XSAVE))
84 cpuid_entry_change(best, X86_FEATURE_OSXSAVE,
85 kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE));
86
87 cpuid_entry_change(best, X86_FEATURE_APIC,
88 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE);
89 }
90
91 best = kvm_find_cpuid_entry(vcpu, 7, 0);
92 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7)
93 cpuid_entry_change(best, X86_FEATURE_OSPKE,
94 kvm_read_cr4_bits(vcpu, X86_CR4_PKE));
95
96 best = kvm_find_cpuid_entry(vcpu, 0xD, 0);
97 if (best)
98 best->ebx = xstate_required_size(vcpu->arch.xcr0, false);
99
100 best = kvm_find_cpuid_entry(vcpu, 0xD, 1);
101 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) ||
102 cpuid_entry_has(best, X86_FEATURE_XSAVEC)))
103 best->ebx = xstate_required_size(vcpu->arch.xcr0, true);
104
105 best = kvm_find_cpuid_entry(vcpu, KVM_CPUID_FEATURES, 0);
106 if (kvm_hlt_in_guest(vcpu->kvm) && best &&
107 (best->eax & (1 << KVM_FEATURE_PV_UNHALT)))
108 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT);
109
110 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) {
111 best = kvm_find_cpuid_entry(vcpu, 0x1, 0);
112 if (best)
113 cpuid_entry_change(best, X86_FEATURE_MWAIT,
114 vcpu->arch.ia32_misc_enable_msr &
115 MSR_IA32_MISC_ENABLE_MWAIT);
116 }
117}
118
119static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
120{
121 struct kvm_lapic *apic = vcpu->arch.apic;
122 struct kvm_cpuid_entry2 *best;
123
124 kvm_x86_ops.vcpu_after_set_cpuid(vcpu);
125
126 best = kvm_find_cpuid_entry(vcpu, 1, 0);
127 if (best && apic) {
128 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER))
129 apic->lapic_timer.timer_mode_mask = 3 << 17;
130 else
131 apic->lapic_timer.timer_mode_mask = 1 << 17;
132
133 kvm_apic_set_version(vcpu);
134 }
135
136 best = kvm_find_cpuid_entry(vcpu, 0xD, 0);
137 if (!best)
138 vcpu->arch.guest_supported_xcr0 = 0;
139 else
140 vcpu->arch.guest_supported_xcr0 =
141 (best->eax | ((u64)best->edx << 32)) & supported_xcr0;
142
143 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
144 kvm_mmu_reset_context(vcpu);
145
146 kvm_pmu_refresh(vcpu);
147 vcpu->arch.cr4_guest_rsvd_bits =
148 __cr4_reserved_bits(guest_cpuid_has, vcpu);
149 kvm_x86_ops.update_exception_bitmap(vcpu);
150}
151
152static int is_efer_nx(void)
153{
154 return host_efer & EFER_NX;
155}
156
157static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
158{
159 int i;
160 struct kvm_cpuid_entry2 *e, *entry;
161
162 entry = NULL;
163 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
164 e = &vcpu->arch.cpuid_entries[i];
165 if (e->function == 0x80000001) {
166 entry = e;
167 break;
168 }
169 }
170 if (entry && cpuid_entry_has(entry, X86_FEATURE_NX) && !is_efer_nx()) {
171 cpuid_entry_clear(entry, X86_FEATURE_NX);
172 printk(KERN_INFO "kvm: guest NX capability removed\n");
173 }
174}
175
176int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu)
177{
178 struct kvm_cpuid_entry2 *best;
179
180 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
181 if (!best || best->eax < 0x80000008)
182 goto not_found;
183 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
184 if (best)
185 return best->eax & 0xff;
186not_found:
187 return 36;
188}
189EXPORT_SYMBOL_GPL(cpuid_query_maxphyaddr);
190
191/* when an old userspace process fills a new kernel module */
192int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
193 struct kvm_cpuid *cpuid,
194 struct kvm_cpuid_entry __user *entries)
195{
196 int r, i;
197 struct kvm_cpuid_entry *cpuid_entries = NULL;
198
199 r = -E2BIG;
200 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
201 goto out;
202 if (cpuid->nent) {
203 cpuid_entries = vmemdup_user(entries,
204 array_size(sizeof(struct kvm_cpuid_entry),
205 cpuid->nent));
206 if (IS_ERR(cpuid_entries)) {
207 r = PTR_ERR(cpuid_entries);
208 goto out;
209 }
210 }
211 for (i = 0; i < cpuid->nent; i++) {
212 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
213 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
214 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
215 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
216 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
217 vcpu->arch.cpuid_entries[i].index = 0;
218 vcpu->arch.cpuid_entries[i].flags = 0;
219 vcpu->arch.cpuid_entries[i].padding[0] = 0;
220 vcpu->arch.cpuid_entries[i].padding[1] = 0;
221 vcpu->arch.cpuid_entries[i].padding[2] = 0;
222 }
223 vcpu->arch.cpuid_nent = cpuid->nent;
224 r = kvm_check_cpuid(vcpu);
225 if (r) {
226 vcpu->arch.cpuid_nent = 0;
227 kvfree(cpuid_entries);
228 goto out;
229 }
230
231 cpuid_fix_nx_cap(vcpu);
232 kvm_update_cpuid_runtime(vcpu);
233 kvm_vcpu_after_set_cpuid(vcpu);
234
235 kvfree(cpuid_entries);
236out:
237 return r;
238}
239
240int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
241 struct kvm_cpuid2 *cpuid,
242 struct kvm_cpuid_entry2 __user *entries)
243{
244 int r;
245
246 r = -E2BIG;
247 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
248 goto out;
249 r = -EFAULT;
250 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
251 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
252 goto out;
253 vcpu->arch.cpuid_nent = cpuid->nent;
254 r = kvm_check_cpuid(vcpu);
255 if (r) {
256 vcpu->arch.cpuid_nent = 0;
257 goto out;
258 }
259
260 kvm_update_cpuid_runtime(vcpu);
261 kvm_vcpu_after_set_cpuid(vcpu);
262out:
263 return r;
264}
265
266int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
267 struct kvm_cpuid2 *cpuid,
268 struct kvm_cpuid_entry2 __user *entries)
269{
270 int r;
271
272 r = -E2BIG;
273 if (cpuid->nent < vcpu->arch.cpuid_nent)
274 goto out;
275 r = -EFAULT;
276 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
277 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
278 goto out;
279 return 0;
280
281out:
282 cpuid->nent = vcpu->arch.cpuid_nent;
283 return r;
284}
285
286static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask)
287{
288 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32);
289 struct kvm_cpuid_entry2 entry;
290
291 reverse_cpuid_check(leaf);
292 kvm_cpu_caps[leaf] &= mask;
293
294 cpuid_count(cpuid.function, cpuid.index,
295 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx);
296
297 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg);
298}
299
300void kvm_set_cpu_caps(void)
301{
302 unsigned int f_nx = is_efer_nx() ? F(NX) : 0;
303#ifdef CONFIG_X86_64
304 unsigned int f_gbpages = F(GBPAGES);
305 unsigned int f_lm = F(LM);
306#else
307 unsigned int f_gbpages = 0;
308 unsigned int f_lm = 0;
309#endif
310
311 BUILD_BUG_ON(sizeof(kvm_cpu_caps) >
312 sizeof(boot_cpu_data.x86_capability));
313
314 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability,
315 sizeof(kvm_cpu_caps));
316
317 kvm_cpu_cap_mask(CPUID_1_ECX,
318 /*
319 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not*
320 * advertised to guests via CPUID!
321 */
322 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
323 0 /* DS-CPL, VMX, SMX, EST */ |
324 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
325 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) |
326 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) |
327 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
328 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
329 F(F16C) | F(RDRAND)
330 );
331 /* KVM emulates x2apic in software irrespective of host support. */
332 kvm_cpu_cap_set(X86_FEATURE_X2APIC);
333
334 kvm_cpu_cap_mask(CPUID_1_EDX,
335 F(FPU) | F(VME) | F(DE) | F(PSE) |
336 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
337 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
338 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
339 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) |
340 0 /* Reserved, DS, ACPI */ | F(MMX) |
341 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
342 0 /* HTT, TM, Reserved, PBE */
343 );
344
345 kvm_cpu_cap_mask(CPUID_7_0_EBX,
346 F(FSGSBASE) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) |
347 F(BMI2) | F(ERMS) | 0 /*INVPCID*/ | F(RTM) | 0 /*MPX*/ | F(RDSEED) |
348 F(ADX) | F(SMAP) | F(AVX512IFMA) | F(AVX512F) | F(AVX512PF) |
349 F(AVX512ER) | F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(AVX512DQ) |
350 F(SHA_NI) | F(AVX512BW) | F(AVX512VL) | 0 /*INTEL_PT*/
351 );
352
353 kvm_cpu_cap_mask(CPUID_7_ECX,
354 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) |
355 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) |
356 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) |
357 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/
358 );
359 /* Set LA57 based on hardware capability. */
360 if (cpuid_ecx(7) & F(LA57))
361 kvm_cpu_cap_set(X86_FEATURE_LA57);
362
363 /*
364 * PKU not yet implemented for shadow paging and requires OSPKE
365 * to be set on the host. Clear it if that is not the case
366 */
367 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE))
368 kvm_cpu_cap_clear(X86_FEATURE_PKU);
369
370 kvm_cpu_cap_mask(CPUID_7_EDX,
371 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
372 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
373 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
374 F(SERIALIZE)
375 );
376
377 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
378 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST);
379 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES);
380
381 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS))
382 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL);
383 if (boot_cpu_has(X86_FEATURE_STIBP))
384 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP);
385 if (boot_cpu_has(X86_FEATURE_AMD_SSBD))
386 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
387
388 kvm_cpu_cap_mask(CPUID_7_1_EAX,
389 F(AVX512_BF16)
390 );
391
392 kvm_cpu_cap_mask(CPUID_D_1_EAX,
393 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES)
394 );
395
396 kvm_cpu_cap_mask(CPUID_8000_0001_ECX,
397 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
398 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
399 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) |
400 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) |
401 F(TOPOEXT) | F(PERFCTR_CORE)
402 );
403
404 kvm_cpu_cap_mask(CPUID_8000_0001_EDX,
405 F(FPU) | F(VME) | F(DE) | F(PSE) |
406 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
407 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
408 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
409 F(PAT) | F(PSE36) | 0 /* Reserved */ |
410 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
411 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) |
412 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW)
413 );
414
415 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64))
416 kvm_cpu_cap_set(X86_FEATURE_GBPAGES);
417
418 kvm_cpu_cap_mask(CPUID_8000_0008_EBX,
419 F(CLZERO) | F(XSAVEERPTR) |
420 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) |
421 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON)
422 );
423
424 /*
425 * AMD has separate bits for each SPEC_CTRL bit.
426 * arch/x86/kernel/cpu/bugs.c is kind enough to
427 * record that in cpufeatures so use them.
428 */
429 if (boot_cpu_has(X86_FEATURE_IBPB))
430 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB);
431 if (boot_cpu_has(X86_FEATURE_IBRS))
432 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS);
433 if (boot_cpu_has(X86_FEATURE_STIBP))
434 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP);
435 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
436 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD);
437 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
438 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO);
439 /*
440 * The preference is to use SPEC CTRL MSR instead of the
441 * VIRT_SPEC MSR.
442 */
443 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
444 !boot_cpu_has(X86_FEATURE_AMD_SSBD))
445 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
446
447 /*
448 * Hide all SVM features by default, SVM will set the cap bits for
449 * features it emulates and/or exposes for L1.
450 */
451 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0);
452
453 kvm_cpu_cap_mask(CPUID_C000_0001_EDX,
454 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
455 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
456 F(PMM) | F(PMM_EN)
457 );
458}
459EXPORT_SYMBOL_GPL(kvm_set_cpu_caps);
460
461struct kvm_cpuid_array {
462 struct kvm_cpuid_entry2 *entries;
463 int maxnent;
464 int nent;
465};
466
467static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array,
468 u32 function, u32 index)
469{
470 struct kvm_cpuid_entry2 *entry;
471
472 if (array->nent >= array->maxnent)
473 return NULL;
474
475 entry = &array->entries[array->nent++];
476
477 entry->function = function;
478 entry->index = index;
479 entry->flags = 0;
480
481 cpuid_count(entry->function, entry->index,
482 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
483
484 switch (function) {
485 case 4:
486 case 7:
487 case 0xb:
488 case 0xd:
489 case 0xf:
490 case 0x10:
491 case 0x12:
492 case 0x14:
493 case 0x17:
494 case 0x18:
495 case 0x1f:
496 case 0x8000001d:
497 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
498 break;
499 }
500
501 return entry;
502}
503
504static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func)
505{
506 struct kvm_cpuid_entry2 *entry;
507
508 if (array->nent >= array->maxnent)
509 return -E2BIG;
510
511 entry = &array->entries[array->nent];
512 entry->function = func;
513 entry->index = 0;
514 entry->flags = 0;
515
516 switch (func) {
517 case 0:
518 entry->eax = 7;
519 ++array->nent;
520 break;
521 case 1:
522 entry->ecx = F(MOVBE);
523 ++array->nent;
524 break;
525 case 7:
526 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
527 entry->eax = 0;
528 entry->ecx = F(RDPID);
529 ++array->nent;
530 default:
531 break;
532 }
533
534 return 0;
535}
536
537static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
538{
539 struct kvm_cpuid_entry2 *entry;
540 int r, i, max_idx;
541
542 /* all calls to cpuid_count() should be made on the same cpu */
543 get_cpu();
544
545 r = -E2BIG;
546
547 entry = do_host_cpuid(array, function, 0);
548 if (!entry)
549 goto out;
550
551 switch (function) {
552 case 0:
553 /* Limited to the highest leaf implemented in KVM. */
554 entry->eax = min(entry->eax, 0x1fU);
555 break;
556 case 1:
557 cpuid_entry_override(entry, CPUID_1_EDX);
558 cpuid_entry_override(entry, CPUID_1_ECX);
559 break;
560 case 2:
561 /*
562 * On ancient CPUs, function 2 entries are STATEFUL. That is,
563 * CPUID(function=2, index=0) may return different results each
564 * time, with the least-significant byte in EAX enumerating the
565 * number of times software should do CPUID(2, 0).
566 *
567 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less
568 * idiotic. Intel's SDM states that EAX & 0xff "will always
569 * return 01H. Software should ignore this value and not
570 * interpret it as an informational descriptor", while AMD's
571 * APM states that CPUID(2) is reserved.
572 *
573 * WARN if a frankenstein CPU that supports virtualization and
574 * a stateful CPUID.0x2 is encountered.
575 */
576 WARN_ON_ONCE((entry->eax & 0xff) > 1);
577 break;
578 /* functions 4 and 0x8000001d have additional index. */
579 case 4:
580 case 0x8000001d:
581 /*
582 * Read entries until the cache type in the previous entry is
583 * zero, i.e. indicates an invalid entry.
584 */
585 for (i = 1; entry->eax & 0x1f; ++i) {
586 entry = do_host_cpuid(array, function, i);
587 if (!entry)
588 goto out;
589 }
590 break;
591 case 6: /* Thermal management */
592 entry->eax = 0x4; /* allow ARAT */
593 entry->ebx = 0;
594 entry->ecx = 0;
595 entry->edx = 0;
596 break;
597 /* function 7 has additional index. */
598 case 7:
599 entry->eax = min(entry->eax, 1u);
600 cpuid_entry_override(entry, CPUID_7_0_EBX);
601 cpuid_entry_override(entry, CPUID_7_ECX);
602 cpuid_entry_override(entry, CPUID_7_EDX);
603
604 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */
605 if (entry->eax == 1) {
606 entry = do_host_cpuid(array, function, 1);
607 if (!entry)
608 goto out;
609
610 cpuid_entry_override(entry, CPUID_7_1_EAX);
611 entry->ebx = 0;
612 entry->ecx = 0;
613 entry->edx = 0;
614 }
615 break;
616 case 9:
617 break;
618 case 0xa: { /* Architectural Performance Monitoring */
619 struct x86_pmu_capability cap;
620 union cpuid10_eax eax;
621 union cpuid10_edx edx;
622
623 perf_get_x86_pmu_capability(&cap);
624
625 /*
626 * Only support guest architectural pmu on a host
627 * with architectural pmu.
628 */
629 if (!cap.version)
630 memset(&cap, 0, sizeof(cap));
631
632 eax.split.version_id = min(cap.version, 2);
633 eax.split.num_counters = cap.num_counters_gp;
634 eax.split.bit_width = cap.bit_width_gp;
635 eax.split.mask_length = cap.events_mask_len;
636
637 edx.split.num_counters_fixed = min(cap.num_counters_fixed, MAX_FIXED_COUNTERS);
638 edx.split.bit_width_fixed = cap.bit_width_fixed;
639 edx.split.reserved = 0;
640
641 entry->eax = eax.full;
642 entry->ebx = cap.events_mask;
643 entry->ecx = 0;
644 entry->edx = edx.full;
645 break;
646 }
647 /*
648 * Per Intel's SDM, the 0x1f is a superset of 0xb,
649 * thus they can be handled by common code.
650 */
651 case 0x1f:
652 case 0xb:
653 /*
654 * Populate entries until the level type (ECX[15:8]) of the
655 * previous entry is zero. Note, CPUID EAX.{0x1f,0xb}.0 is
656 * the starting entry, filled by the primary do_host_cpuid().
657 */
658 for (i = 1; entry->ecx & 0xff00; ++i) {
659 entry = do_host_cpuid(array, function, i);
660 if (!entry)
661 goto out;
662 }
663 break;
664 case 0xd:
665 entry->eax &= supported_xcr0;
666 entry->ebx = xstate_required_size(supported_xcr0, false);
667 entry->ecx = entry->ebx;
668 entry->edx &= supported_xcr0 >> 32;
669 if (!supported_xcr0)
670 break;
671
672 entry = do_host_cpuid(array, function, 1);
673 if (!entry)
674 goto out;
675
676 cpuid_entry_override(entry, CPUID_D_1_EAX);
677 if (entry->eax & (F(XSAVES)|F(XSAVEC)))
678 entry->ebx = xstate_required_size(supported_xcr0 | supported_xss,
679 true);
680 else {
681 WARN_ON_ONCE(supported_xss != 0);
682 entry->ebx = 0;
683 }
684 entry->ecx &= supported_xss;
685 entry->edx &= supported_xss >> 32;
686
687 for (i = 2; i < 64; ++i) {
688 bool s_state;
689 if (supported_xcr0 & BIT_ULL(i))
690 s_state = false;
691 else if (supported_xss & BIT_ULL(i))
692 s_state = true;
693 else
694 continue;
695
696 entry = do_host_cpuid(array, function, i);
697 if (!entry)
698 goto out;
699
700 /*
701 * The supported check above should have filtered out
702 * invalid sub-leafs. Only valid sub-leafs should
703 * reach this point, and they should have a non-zero
704 * save state size. Furthermore, check whether the
705 * processor agrees with supported_xcr0/supported_xss
706 * on whether this is an XCR0- or IA32_XSS-managed area.
707 */
708 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) {
709 --array->nent;
710 continue;
711 }
712 entry->edx = 0;
713 }
714 break;
715 /* Intel PT */
716 case 0x14:
717 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) {
718 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
719 break;
720 }
721
722 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) {
723 if (!do_host_cpuid(array, function, i))
724 goto out;
725 }
726 break;
727 case KVM_CPUID_SIGNATURE: {
728 static const char signature[12] = "KVMKVMKVM\0\0";
729 const u32 *sigptr = (const u32 *)signature;
730 entry->eax = KVM_CPUID_FEATURES;
731 entry->ebx = sigptr[0];
732 entry->ecx = sigptr[1];
733 entry->edx = sigptr[2];
734 break;
735 }
736 case KVM_CPUID_FEATURES:
737 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
738 (1 << KVM_FEATURE_NOP_IO_DELAY) |
739 (1 << KVM_FEATURE_CLOCKSOURCE2) |
740 (1 << KVM_FEATURE_ASYNC_PF) |
741 (1 << KVM_FEATURE_PV_EOI) |
742 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) |
743 (1 << KVM_FEATURE_PV_UNHALT) |
744 (1 << KVM_FEATURE_PV_TLB_FLUSH) |
745 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) |
746 (1 << KVM_FEATURE_PV_SEND_IPI) |
747 (1 << KVM_FEATURE_POLL_CONTROL) |
748 (1 << KVM_FEATURE_PV_SCHED_YIELD) |
749 (1 << KVM_FEATURE_ASYNC_PF_INT);
750
751 if (sched_info_on())
752 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
753
754 entry->ebx = 0;
755 entry->ecx = 0;
756 entry->edx = 0;
757 break;
758 case 0x80000000:
759 entry->eax = min(entry->eax, 0x8000001f);
760 break;
761 case 0x80000001:
762 cpuid_entry_override(entry, CPUID_8000_0001_EDX);
763 cpuid_entry_override(entry, CPUID_8000_0001_ECX);
764 break;
765 case 0x80000006:
766 /* L2 cache and TLB: pass through host info. */
767 break;
768 case 0x80000007: /* Advanced power management */
769 /* invariant TSC is CPUID.80000007H:EDX[8] */
770 entry->edx &= (1 << 8);
771 /* mask against host */
772 entry->edx &= boot_cpu_data.x86_power;
773 entry->eax = entry->ebx = entry->ecx = 0;
774 break;
775 case 0x80000008: {
776 unsigned g_phys_as = (entry->eax >> 16) & 0xff;
777 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
778 unsigned phys_as = entry->eax & 0xff;
779
780 if (!g_phys_as)
781 g_phys_as = phys_as;
782 entry->eax = g_phys_as | (virt_as << 8);
783 entry->edx = 0;
784 cpuid_entry_override(entry, CPUID_8000_0008_EBX);
785 break;
786 }
787 case 0x8000000A:
788 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) {
789 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
790 break;
791 }
792 entry->eax = 1; /* SVM revision 1 */
793 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
794 ASID emulation to nested SVM */
795 entry->ecx = 0; /* Reserved */
796 cpuid_entry_override(entry, CPUID_8000_000A_EDX);
797 break;
798 case 0x80000019:
799 entry->ecx = entry->edx = 0;
800 break;
801 case 0x8000001a:
802 case 0x8000001e:
803 break;
804 /* Support memory encryption cpuid if host supports it */
805 case 0x8000001F:
806 if (!boot_cpu_has(X86_FEATURE_SEV))
807 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
808 break;
809 /*Add support for Centaur's CPUID instruction*/
810 case 0xC0000000:
811 /*Just support up to 0xC0000004 now*/
812 entry->eax = min(entry->eax, 0xC0000004);
813 break;
814 case 0xC0000001:
815 cpuid_entry_override(entry, CPUID_C000_0001_EDX);
816 break;
817 case 3: /* Processor serial number */
818 case 5: /* MONITOR/MWAIT */
819 case 0xC0000002:
820 case 0xC0000003:
821 case 0xC0000004:
822 default:
823 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
824 break;
825 }
826
827 r = 0;
828
829out:
830 put_cpu();
831
832 return r;
833}
834
835static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func,
836 unsigned int type)
837{
838 if (type == KVM_GET_EMULATED_CPUID)
839 return __do_cpuid_func_emulated(array, func);
840
841 return __do_cpuid_func(array, func);
842}
843
844#define CENTAUR_CPUID_SIGNATURE 0xC0000000
845
846static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func,
847 unsigned int type)
848{
849 u32 limit;
850 int r;
851
852 if (func == CENTAUR_CPUID_SIGNATURE &&
853 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR)
854 return 0;
855
856 r = do_cpuid_func(array, func, type);
857 if (r)
858 return r;
859
860 limit = array->entries[array->nent - 1].eax;
861 for (func = func + 1; func <= limit; ++func) {
862 r = do_cpuid_func(array, func, type);
863 if (r)
864 break;
865 }
866
867 return r;
868}
869
870static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries,
871 __u32 num_entries, unsigned int ioctl_type)
872{
873 int i;
874 __u32 pad[3];
875
876 if (ioctl_type != KVM_GET_EMULATED_CPUID)
877 return false;
878
879 /*
880 * We want to make sure that ->padding is being passed clean from
881 * userspace in case we want to use it for something in the future.
882 *
883 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we
884 * have to give ourselves satisfied only with the emulated side. /me
885 * sheds a tear.
886 */
887 for (i = 0; i < num_entries; i++) {
888 if (copy_from_user(pad, entries[i].padding, sizeof(pad)))
889 return true;
890
891 if (pad[0] || pad[1] || pad[2])
892 return true;
893 }
894 return false;
895}
896
897int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid,
898 struct kvm_cpuid_entry2 __user *entries,
899 unsigned int type)
900{
901 static const u32 funcs[] = {
902 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE,
903 };
904
905 struct kvm_cpuid_array array = {
906 .nent = 0,
907 };
908 int r, i;
909
910 if (cpuid->nent < 1)
911 return -E2BIG;
912 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
913 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
914
915 if (sanity_check_entries(entries, cpuid->nent, type))
916 return -EINVAL;
917
918 array.entries = vzalloc(array_size(sizeof(struct kvm_cpuid_entry2),
919 cpuid->nent));
920 if (!array.entries)
921 return -ENOMEM;
922
923 array.maxnent = cpuid->nent;
924
925 for (i = 0; i < ARRAY_SIZE(funcs); i++) {
926 r = get_cpuid_func(&array, funcs[i], type);
927 if (r)
928 goto out_free;
929 }
930 cpuid->nent = array.nent;
931
932 if (copy_to_user(entries, array.entries,
933 array.nent * sizeof(struct kvm_cpuid_entry2)))
934 r = -EFAULT;
935
936out_free:
937 vfree(array.entries);
938 return r;
939}
940
941struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
942 u32 function, u32 index)
943{
944 struct kvm_cpuid_entry2 *e;
945 int i;
946
947 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
948 e = &vcpu->arch.cpuid_entries[i];
949
950 if (e->function == function && (e->index == index ||
951 !(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX)))
952 return e;
953 }
954 return NULL;
955}
956EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
957
958/*
959 * Intel CPUID semantics treats any query for an out-of-range leaf as if the
960 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics
961 * returns all zeroes for any undefined leaf, whether or not the leaf is in
962 * range. Centaur/VIA follows Intel semantics.
963 *
964 * A leaf is considered out-of-range if its function is higher than the maximum
965 * supported leaf of its associated class or if its associated class does not
966 * exist.
967 *
968 * There are three primary classes to be considered, with their respective
969 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary
970 * class exists if a guest CPUID entry for its <base> leaf exists. For a given
971 * class, CPUID.<base>.EAX contains the max supported leaf for the class.
972 *
973 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff
974 * - Hypervisor: 0x40000000 - 0x4fffffff
975 * - Extended: 0x80000000 - 0xbfffffff
976 * - Centaur: 0xc0000000 - 0xcfffffff
977 *
978 * The Hypervisor class is further subdivided into sub-classes that each act as
979 * their own indepdent class associated with a 0x100 byte range. E.g. if Qemu
980 * is advertising support for both HyperV and KVM, the resulting Hypervisor
981 * CPUID sub-classes are:
982 *
983 * - HyperV: 0x40000000 - 0x400000ff
984 * - KVM: 0x40000100 - 0x400001ff
985 */
986static struct kvm_cpuid_entry2 *
987get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index)
988{
989 struct kvm_cpuid_entry2 *basic, *class;
990 u32 function = *fn_ptr;
991
992 basic = kvm_find_cpuid_entry(vcpu, 0, 0);
993 if (!basic)
994 return NULL;
995
996 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) ||
997 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx))
998 return NULL;
999
1000 if (function >= 0x40000000 && function <= 0x4fffffff)
1001 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00, 0);
1002 else if (function >= 0xc0000000)
1003 class = kvm_find_cpuid_entry(vcpu, 0xc0000000, 0);
1004 else
1005 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
1006
1007 if (class && function <= class->eax)
1008 return NULL;
1009
1010 /*
1011 * Leaf specific adjustments are also applied when redirecting to the
1012 * max basic entry, e.g. if the max basic leaf is 0xb but there is no
1013 * entry for CPUID.0xb.index (see below), then the output value for EDX
1014 * needs to be pulled from CPUID.0xb.1.
1015 */
1016 *fn_ptr = basic->eax;
1017
1018 /*
1019 * The class does not exist or the requested function is out of range;
1020 * the effective CPUID entry is the max basic leaf. Note, the index of
1021 * the original requested leaf is observed!
1022 */
1023 return kvm_find_cpuid_entry(vcpu, basic->eax, index);
1024}
1025
1026bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx,
1027 u32 *ecx, u32 *edx, bool exact_only)
1028{
1029 u32 orig_function = *eax, function = *eax, index = *ecx;
1030 struct kvm_cpuid_entry2 *entry;
1031 bool exact, used_max_basic = false;
1032
1033 entry = kvm_find_cpuid_entry(vcpu, function, index);
1034 exact = !!entry;
1035
1036 if (!entry && !exact_only) {
1037 entry = get_out_of_range_cpuid_entry(vcpu, &function, index);
1038 used_max_basic = !!entry;
1039 }
1040
1041 if (entry) {
1042 *eax = entry->eax;
1043 *ebx = entry->ebx;
1044 *ecx = entry->ecx;
1045 *edx = entry->edx;
1046 if (function == 7 && index == 0) {
1047 u64 data;
1048 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) &&
1049 (data & TSX_CTRL_CPUID_CLEAR))
1050 *ebx &= ~(F(RTM) | F(HLE));
1051 }
1052 } else {
1053 *eax = *ebx = *ecx = *edx = 0;
1054 /*
1055 * When leaf 0BH or 1FH is defined, CL is pass-through
1056 * and EDX is always the x2APIC ID, even for undefined
1057 * subleaves. Index 1 will exist iff the leaf is
1058 * implemented, so we pass through CL iff leaf 1
1059 * exists. EDX can be copied from any existing index.
1060 */
1061 if (function == 0xb || function == 0x1f) {
1062 entry = kvm_find_cpuid_entry(vcpu, function, 1);
1063 if (entry) {
1064 *ecx = index & 0xff;
1065 *edx = entry->edx;
1066 }
1067 }
1068 }
1069 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact,
1070 used_max_basic);
1071 return exact;
1072}
1073EXPORT_SYMBOL_GPL(kvm_cpuid);
1074
1075int kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
1076{
1077 u32 eax, ebx, ecx, edx;
1078
1079 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0))
1080 return 1;
1081
1082 eax = kvm_rax_read(vcpu);
1083 ecx = kvm_rcx_read(vcpu);
1084 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false);
1085 kvm_rax_write(vcpu, eax);
1086 kvm_rbx_write(vcpu, ebx);
1087 kvm_rcx_write(vcpu, ecx);
1088 kvm_rdx_write(vcpu, edx);
1089 return kvm_skip_emulated_instruction(vcpu);
1090}
1091EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);