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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 *
5 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 *
7 * Thanks to the following companies for their support:
8 *
9 * - JMicron (hardware and technical support)
10 */
11
12#include <linux/bitfield.h>
13#include <linux/delay.h>
14#include <linux/dmaengine.h>
15#include <linux/ktime.h>
16#include <linux/highmem.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/dma-mapping.h>
20#include <linux/slab.h>
21#include <linux/scatterlist.h>
22#include <linux/sizes.h>
23#include <linux/regulator/consumer.h>
24#include <linux/pm_runtime.h>
25#include <linux/of.h>
26
27#include <linux/leds.h>
28
29#include <linux/mmc/mmc.h>
30#include <linux/mmc/host.h>
31#include <linux/mmc/card.h>
32#include <linux/mmc/sdio.h>
33#include <linux/mmc/slot-gpio.h>
34
35#include "sdhci.h"
36
37#define DRIVER_NAME "sdhci"
38
39#define DBG(f, x...) \
40 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
41
42#define SDHCI_DUMP(f, x...) \
43 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
44
45#define MAX_TUNING_LOOP 40
46
47static unsigned int debug_quirks = 0;
48static unsigned int debug_quirks2;
49
50static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
51
52static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
53
54void sdhci_dumpregs(struct sdhci_host *host)
55{
56 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
57
58 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
59 sdhci_readl(host, SDHCI_DMA_ADDRESS),
60 sdhci_readw(host, SDHCI_HOST_VERSION));
61 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
62 sdhci_readw(host, SDHCI_BLOCK_SIZE),
63 sdhci_readw(host, SDHCI_BLOCK_COUNT));
64 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
65 sdhci_readl(host, SDHCI_ARGUMENT),
66 sdhci_readw(host, SDHCI_TRANSFER_MODE));
67 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
68 sdhci_readl(host, SDHCI_PRESENT_STATE),
69 sdhci_readb(host, SDHCI_HOST_CONTROL));
70 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
71 sdhci_readb(host, SDHCI_POWER_CONTROL),
72 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
73 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
74 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
75 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
76 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
77 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
78 sdhci_readl(host, SDHCI_INT_STATUS));
79 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
80 sdhci_readl(host, SDHCI_INT_ENABLE),
81 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
82 SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
83 sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
84 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
85 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
86 sdhci_readl(host, SDHCI_CAPABILITIES),
87 sdhci_readl(host, SDHCI_CAPABILITIES_1));
88 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
89 sdhci_readw(host, SDHCI_COMMAND),
90 sdhci_readl(host, SDHCI_MAX_CURRENT));
91 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
92 sdhci_readl(host, SDHCI_RESPONSE),
93 sdhci_readl(host, SDHCI_RESPONSE + 4));
94 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
95 sdhci_readl(host, SDHCI_RESPONSE + 8),
96 sdhci_readl(host, SDHCI_RESPONSE + 12));
97 SDHCI_DUMP("Host ctl2: 0x%08x\n",
98 sdhci_readw(host, SDHCI_HOST_CONTROL2));
99
100 if (host->flags & SDHCI_USE_ADMA) {
101 if (host->flags & SDHCI_USE_64_BIT_DMA) {
102 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
103 sdhci_readl(host, SDHCI_ADMA_ERROR),
104 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
105 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
106 } else {
107 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
108 sdhci_readl(host, SDHCI_ADMA_ERROR),
109 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
110 }
111 }
112
113 if (host->ops->dump_vendor_regs)
114 host->ops->dump_vendor_regs(host);
115
116 SDHCI_DUMP("============================================\n");
117}
118EXPORT_SYMBOL_GPL(sdhci_dumpregs);
119
120/*****************************************************************************\
121 * *
122 * Low level functions *
123 * *
124\*****************************************************************************/
125
126static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
127{
128 u16 ctrl2;
129
130 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
131 if (ctrl2 & SDHCI_CTRL_V4_MODE)
132 return;
133
134 ctrl2 |= SDHCI_CTRL_V4_MODE;
135 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
136}
137
138/*
139 * This can be called before sdhci_add_host() by Vendor's host controller
140 * driver to enable v4 mode if supported.
141 */
142void sdhci_enable_v4_mode(struct sdhci_host *host)
143{
144 host->v4_mode = true;
145 sdhci_do_enable_v4_mode(host);
146}
147EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
148
149static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
150{
151 return cmd->data || cmd->flags & MMC_RSP_BUSY;
152}
153
154static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
155{
156 u32 present;
157
158 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
159 !mmc_card_is_removable(host->mmc) || mmc_can_gpio_cd(host->mmc))
160 return;
161
162 if (enable) {
163 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
164 SDHCI_CARD_PRESENT;
165
166 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
167 SDHCI_INT_CARD_INSERT;
168 } else {
169 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
170 }
171
172 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
173 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
174}
175
176static void sdhci_enable_card_detection(struct sdhci_host *host)
177{
178 sdhci_set_card_detection(host, true);
179}
180
181static void sdhci_disable_card_detection(struct sdhci_host *host)
182{
183 sdhci_set_card_detection(host, false);
184}
185
186static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
187{
188 if (host->bus_on)
189 return;
190 host->bus_on = true;
191 pm_runtime_get_noresume(mmc_dev(host->mmc));
192}
193
194static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
195{
196 if (!host->bus_on)
197 return;
198 host->bus_on = false;
199 pm_runtime_put_noidle(mmc_dev(host->mmc));
200}
201
202void sdhci_reset(struct sdhci_host *host, u8 mask)
203{
204 ktime_t timeout;
205
206 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
207
208 if (mask & SDHCI_RESET_ALL) {
209 host->clock = 0;
210 /* Reset-all turns off SD Bus Power */
211 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
212 sdhci_runtime_pm_bus_off(host);
213 }
214
215 /* Wait max 100 ms */
216 timeout = ktime_add_ms(ktime_get(), 100);
217
218 /* hw clears the bit when it's done */
219 while (1) {
220 bool timedout = ktime_after(ktime_get(), timeout);
221
222 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
223 break;
224 if (timedout) {
225 pr_err("%s: Reset 0x%x never completed.\n",
226 mmc_hostname(host->mmc), (int)mask);
227 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
228 sdhci_dumpregs(host);
229 return;
230 }
231 udelay(10);
232 }
233}
234EXPORT_SYMBOL_GPL(sdhci_reset);
235
236static bool sdhci_do_reset(struct sdhci_host *host, u8 mask)
237{
238 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
239 struct mmc_host *mmc = host->mmc;
240
241 if (!mmc->ops->get_cd(mmc))
242 return false;
243 }
244
245 host->ops->reset(host, mask);
246
247 return true;
248}
249
250static void sdhci_reset_for_all(struct sdhci_host *host)
251{
252 if (sdhci_do_reset(host, SDHCI_RESET_ALL)) {
253 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
254 if (host->ops->enable_dma)
255 host->ops->enable_dma(host);
256 }
257 /* Resetting the controller clears many */
258 host->preset_enabled = false;
259 }
260}
261
262enum sdhci_reset_reason {
263 SDHCI_RESET_FOR_INIT,
264 SDHCI_RESET_FOR_REQUEST_ERROR,
265 SDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY,
266 SDHCI_RESET_FOR_TUNING_ABORT,
267 SDHCI_RESET_FOR_CARD_REMOVED,
268 SDHCI_RESET_FOR_CQE_RECOVERY,
269};
270
271static void sdhci_reset_for_reason(struct sdhci_host *host, enum sdhci_reset_reason reason)
272{
273 if (host->quirks2 & SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER) {
274 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
275 return;
276 }
277
278 switch (reason) {
279 case SDHCI_RESET_FOR_INIT:
280 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
281 break;
282 case SDHCI_RESET_FOR_REQUEST_ERROR:
283 case SDHCI_RESET_FOR_TUNING_ABORT:
284 case SDHCI_RESET_FOR_CARD_REMOVED:
285 case SDHCI_RESET_FOR_CQE_RECOVERY:
286 sdhci_do_reset(host, SDHCI_RESET_CMD);
287 sdhci_do_reset(host, SDHCI_RESET_DATA);
288 break;
289 case SDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY:
290 sdhci_do_reset(host, SDHCI_RESET_DATA);
291 break;
292 }
293}
294
295#define sdhci_reset_for(h, r) sdhci_reset_for_reason((h), SDHCI_RESET_FOR_##r)
296
297static void sdhci_set_default_irqs(struct sdhci_host *host)
298{
299 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
300 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
301 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
302 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
303 SDHCI_INT_RESPONSE;
304
305 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
306 host->tuning_mode == SDHCI_TUNING_MODE_3)
307 host->ier |= SDHCI_INT_RETUNE;
308
309 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
310 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
311}
312
313static void sdhci_config_dma(struct sdhci_host *host)
314{
315 u8 ctrl;
316 u16 ctrl2;
317
318 if (host->version < SDHCI_SPEC_200)
319 return;
320
321 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
322
323 /*
324 * Always adjust the DMA selection as some controllers
325 * (e.g. JMicron) can't do PIO properly when the selection
326 * is ADMA.
327 */
328 ctrl &= ~SDHCI_CTRL_DMA_MASK;
329 if (!(host->flags & SDHCI_REQ_USE_DMA))
330 goto out;
331
332 /* Note if DMA Select is zero then SDMA is selected */
333 if (host->flags & SDHCI_USE_ADMA)
334 ctrl |= SDHCI_CTRL_ADMA32;
335
336 if (host->flags & SDHCI_USE_64_BIT_DMA) {
337 /*
338 * If v4 mode, all supported DMA can be 64-bit addressing if
339 * controller supports 64-bit system address, otherwise only
340 * ADMA can support 64-bit addressing.
341 */
342 if (host->v4_mode) {
343 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
344 ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
345 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
346 } else if (host->flags & SDHCI_USE_ADMA) {
347 /*
348 * Don't need to undo SDHCI_CTRL_ADMA32 in order to
349 * set SDHCI_CTRL_ADMA64.
350 */
351 ctrl |= SDHCI_CTRL_ADMA64;
352 }
353 }
354
355out:
356 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
357}
358
359static void sdhci_init(struct sdhci_host *host, int soft)
360{
361 struct mmc_host *mmc = host->mmc;
362 unsigned long flags;
363
364 if (soft)
365 sdhci_reset_for(host, INIT);
366 else
367 sdhci_reset_for_all(host);
368
369 if (host->v4_mode)
370 sdhci_do_enable_v4_mode(host);
371
372 spin_lock_irqsave(&host->lock, flags);
373 sdhci_set_default_irqs(host);
374 spin_unlock_irqrestore(&host->lock, flags);
375
376 host->cqe_on = false;
377
378 if (soft) {
379 /* force clock reconfiguration */
380 host->clock = 0;
381 host->reinit_uhs = true;
382 mmc->ops->set_ios(mmc, &mmc->ios);
383 }
384}
385
386static void sdhci_reinit(struct sdhci_host *host)
387{
388 u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
389
390 sdhci_init(host, 0);
391 sdhci_enable_card_detection(host);
392
393 /*
394 * A change to the card detect bits indicates a change in present state,
395 * refer sdhci_set_card_detection(). A card detect interrupt might have
396 * been missed while the host controller was being reset, so trigger a
397 * rescan to check.
398 */
399 if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT)))
400 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
401}
402
403static void __sdhci_led_activate(struct sdhci_host *host)
404{
405 u8 ctrl;
406
407 if (host->quirks & SDHCI_QUIRK_NO_LED)
408 return;
409
410 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
411 ctrl |= SDHCI_CTRL_LED;
412 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
413}
414
415static void __sdhci_led_deactivate(struct sdhci_host *host)
416{
417 u8 ctrl;
418
419 if (host->quirks & SDHCI_QUIRK_NO_LED)
420 return;
421
422 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
423 ctrl &= ~SDHCI_CTRL_LED;
424 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
425}
426
427#if IS_REACHABLE(CONFIG_LEDS_CLASS)
428static void sdhci_led_control(struct led_classdev *led,
429 enum led_brightness brightness)
430{
431 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
432 unsigned long flags;
433
434 spin_lock_irqsave(&host->lock, flags);
435
436 if (host->runtime_suspended)
437 goto out;
438
439 if (brightness == LED_OFF)
440 __sdhci_led_deactivate(host);
441 else
442 __sdhci_led_activate(host);
443out:
444 spin_unlock_irqrestore(&host->lock, flags);
445}
446
447static int sdhci_led_register(struct sdhci_host *host)
448{
449 struct mmc_host *mmc = host->mmc;
450
451 if (host->quirks & SDHCI_QUIRK_NO_LED)
452 return 0;
453
454 snprintf(host->led_name, sizeof(host->led_name),
455 "%s::", mmc_hostname(mmc));
456
457 host->led.name = host->led_name;
458 host->led.brightness = LED_OFF;
459 host->led.default_trigger = mmc_hostname(mmc);
460 host->led.brightness_set = sdhci_led_control;
461
462 return led_classdev_register(mmc_dev(mmc), &host->led);
463}
464
465static void sdhci_led_unregister(struct sdhci_host *host)
466{
467 if (host->quirks & SDHCI_QUIRK_NO_LED)
468 return;
469
470 led_classdev_unregister(&host->led);
471}
472
473static inline void sdhci_led_activate(struct sdhci_host *host)
474{
475}
476
477static inline void sdhci_led_deactivate(struct sdhci_host *host)
478{
479}
480
481#else
482
483static inline int sdhci_led_register(struct sdhci_host *host)
484{
485 return 0;
486}
487
488static inline void sdhci_led_unregister(struct sdhci_host *host)
489{
490}
491
492static inline void sdhci_led_activate(struct sdhci_host *host)
493{
494 __sdhci_led_activate(host);
495}
496
497static inline void sdhci_led_deactivate(struct sdhci_host *host)
498{
499 __sdhci_led_deactivate(host);
500}
501
502#endif
503
504static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
505 unsigned long timeout)
506{
507 if (sdhci_data_line_cmd(mrq->cmd))
508 mod_timer(&host->data_timer, timeout);
509 else
510 mod_timer(&host->timer, timeout);
511}
512
513static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
514{
515 if (sdhci_data_line_cmd(mrq->cmd))
516 del_timer(&host->data_timer);
517 else
518 del_timer(&host->timer);
519}
520
521static inline bool sdhci_has_requests(struct sdhci_host *host)
522{
523 return host->cmd || host->data_cmd;
524}
525
526/*****************************************************************************\
527 * *
528 * Core functions *
529 * *
530\*****************************************************************************/
531
532static void sdhci_read_block_pio(struct sdhci_host *host)
533{
534 size_t blksize, len, chunk;
535 u32 scratch;
536 u8 *buf;
537
538 DBG("PIO reading\n");
539
540 blksize = host->data->blksz;
541 chunk = 0;
542
543 while (blksize) {
544 BUG_ON(!sg_miter_next(&host->sg_miter));
545
546 len = min(host->sg_miter.length, blksize);
547
548 blksize -= len;
549 host->sg_miter.consumed = len;
550
551 buf = host->sg_miter.addr;
552
553 while (len) {
554 if (chunk == 0) {
555 scratch = sdhci_readl(host, SDHCI_BUFFER);
556 chunk = 4;
557 }
558
559 *buf = scratch & 0xFF;
560
561 buf++;
562 scratch >>= 8;
563 chunk--;
564 len--;
565 }
566 }
567
568 sg_miter_stop(&host->sg_miter);
569}
570
571static void sdhci_write_block_pio(struct sdhci_host *host)
572{
573 size_t blksize, len, chunk;
574 u32 scratch;
575 u8 *buf;
576
577 DBG("PIO writing\n");
578
579 blksize = host->data->blksz;
580 chunk = 0;
581 scratch = 0;
582
583 while (blksize) {
584 BUG_ON(!sg_miter_next(&host->sg_miter));
585
586 len = min(host->sg_miter.length, blksize);
587
588 blksize -= len;
589 host->sg_miter.consumed = len;
590
591 buf = host->sg_miter.addr;
592
593 while (len) {
594 scratch |= (u32)*buf << (chunk * 8);
595
596 buf++;
597 chunk++;
598 len--;
599
600 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
601 sdhci_writel(host, scratch, SDHCI_BUFFER);
602 chunk = 0;
603 scratch = 0;
604 }
605 }
606 }
607
608 sg_miter_stop(&host->sg_miter);
609}
610
611static void sdhci_transfer_pio(struct sdhci_host *host)
612{
613 u32 mask;
614
615 if (host->blocks == 0)
616 return;
617
618 if (host->data->flags & MMC_DATA_READ)
619 mask = SDHCI_DATA_AVAILABLE;
620 else
621 mask = SDHCI_SPACE_AVAILABLE;
622
623 /*
624 * Some controllers (JMicron JMB38x) mess up the buffer bits
625 * for transfers < 4 bytes. As long as it is just one block,
626 * we can ignore the bits.
627 */
628 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
629 (host->data->blocks == 1))
630 mask = ~0;
631
632 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
633 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
634 udelay(100);
635
636 if (host->data->flags & MMC_DATA_READ)
637 sdhci_read_block_pio(host);
638 else
639 sdhci_write_block_pio(host);
640
641 host->blocks--;
642 if (host->blocks == 0)
643 break;
644 }
645
646 DBG("PIO transfer complete.\n");
647}
648
649static int sdhci_pre_dma_transfer(struct sdhci_host *host,
650 struct mmc_data *data, int cookie)
651{
652 int sg_count;
653
654 /*
655 * If the data buffers are already mapped, return the previous
656 * dma_map_sg() result.
657 */
658 if (data->host_cookie == COOKIE_PRE_MAPPED)
659 return data->sg_count;
660
661 /* Bounce write requests to the bounce buffer */
662 if (host->bounce_buffer) {
663 unsigned int length = data->blksz * data->blocks;
664
665 if (length > host->bounce_buffer_size) {
666 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
667 mmc_hostname(host->mmc), length,
668 host->bounce_buffer_size);
669 return -EIO;
670 }
671 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
672 /* Copy the data to the bounce buffer */
673 if (host->ops->copy_to_bounce_buffer) {
674 host->ops->copy_to_bounce_buffer(host,
675 data, length);
676 } else {
677 sg_copy_to_buffer(data->sg, data->sg_len,
678 host->bounce_buffer, length);
679 }
680 }
681 /* Switch ownership to the DMA */
682 dma_sync_single_for_device(mmc_dev(host->mmc),
683 host->bounce_addr,
684 host->bounce_buffer_size,
685 mmc_get_dma_dir(data));
686 /* Just a dummy value */
687 sg_count = 1;
688 } else {
689 /* Just access the data directly from memory */
690 sg_count = dma_map_sg(mmc_dev(host->mmc),
691 data->sg, data->sg_len,
692 mmc_get_dma_dir(data));
693 }
694
695 if (sg_count == 0)
696 return -ENOSPC;
697
698 data->sg_count = sg_count;
699 data->host_cookie = cookie;
700
701 return sg_count;
702}
703
704static char *sdhci_kmap_atomic(struct scatterlist *sg)
705{
706 return kmap_local_page(sg_page(sg)) + sg->offset;
707}
708
709static void sdhci_kunmap_atomic(void *buffer)
710{
711 kunmap_local(buffer);
712}
713
714void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
715 dma_addr_t addr, int len, unsigned int cmd)
716{
717 struct sdhci_adma2_64_desc *dma_desc = *desc;
718
719 /* 32-bit and 64-bit descriptors have these members in same position */
720 dma_desc->cmd = cpu_to_le16(cmd);
721 dma_desc->len = cpu_to_le16(len);
722 dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr));
723
724 if (host->flags & SDHCI_USE_64_BIT_DMA)
725 dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr));
726
727 *desc += host->desc_sz;
728}
729EXPORT_SYMBOL_GPL(sdhci_adma_write_desc);
730
731static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
732 void **desc, dma_addr_t addr,
733 int len, unsigned int cmd)
734{
735 if (host->ops->adma_write_desc)
736 host->ops->adma_write_desc(host, desc, addr, len, cmd);
737 else
738 sdhci_adma_write_desc(host, desc, addr, len, cmd);
739}
740
741static void sdhci_adma_mark_end(void *desc)
742{
743 struct sdhci_adma2_64_desc *dma_desc = desc;
744
745 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
746 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
747}
748
749static void sdhci_adma_table_pre(struct sdhci_host *host,
750 struct mmc_data *data, int sg_count)
751{
752 struct scatterlist *sg;
753 dma_addr_t addr, align_addr;
754 void *desc, *align;
755 char *buffer;
756 int len, offset, i;
757
758 /*
759 * The spec does not specify endianness of descriptor table.
760 * We currently guess that it is LE.
761 */
762
763 host->sg_count = sg_count;
764
765 desc = host->adma_table;
766 align = host->align_buffer;
767
768 align_addr = host->align_addr;
769
770 for_each_sg(data->sg, sg, host->sg_count, i) {
771 addr = sg_dma_address(sg);
772 len = sg_dma_len(sg);
773
774 /*
775 * The SDHCI specification states that ADMA addresses must
776 * be 32-bit aligned. If they aren't, then we use a bounce
777 * buffer for the (up to three) bytes that screw up the
778 * alignment.
779 */
780 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
781 SDHCI_ADMA2_MASK;
782 if (offset) {
783 if (data->flags & MMC_DATA_WRITE) {
784 buffer = sdhci_kmap_atomic(sg);
785 memcpy(align, buffer, offset);
786 sdhci_kunmap_atomic(buffer);
787 }
788
789 /* tran, valid */
790 __sdhci_adma_write_desc(host, &desc, align_addr,
791 offset, ADMA2_TRAN_VALID);
792
793 BUG_ON(offset > 65536);
794
795 align += SDHCI_ADMA2_ALIGN;
796 align_addr += SDHCI_ADMA2_ALIGN;
797
798 addr += offset;
799 len -= offset;
800 }
801
802 /*
803 * The block layer forces a minimum segment size of PAGE_SIZE,
804 * so 'len' can be too big here if PAGE_SIZE >= 64KiB. Write
805 * multiple descriptors, noting that the ADMA table is sized
806 * for 4KiB chunks anyway, so it will be big enough.
807 */
808 while (len > host->max_adma) {
809 int n = 32 * 1024; /* 32KiB*/
810
811 __sdhci_adma_write_desc(host, &desc, addr, n, ADMA2_TRAN_VALID);
812 addr += n;
813 len -= n;
814 }
815
816 /* tran, valid */
817 if (len)
818 __sdhci_adma_write_desc(host, &desc, addr, len,
819 ADMA2_TRAN_VALID);
820
821 /*
822 * If this triggers then we have a calculation bug
823 * somewhere. :/
824 */
825 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
826 }
827
828 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
829 /* Mark the last descriptor as the terminating descriptor */
830 if (desc != host->adma_table) {
831 desc -= host->desc_sz;
832 sdhci_adma_mark_end(desc);
833 }
834 } else {
835 /* Add a terminating entry - nop, end, valid */
836 __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
837 }
838}
839
840static void sdhci_adma_table_post(struct sdhci_host *host,
841 struct mmc_data *data)
842{
843 struct scatterlist *sg;
844 int i, size;
845 void *align;
846 char *buffer;
847
848 if (data->flags & MMC_DATA_READ) {
849 bool has_unaligned = false;
850
851 /* Do a quick scan of the SG list for any unaligned mappings */
852 for_each_sg(data->sg, sg, host->sg_count, i)
853 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
854 has_unaligned = true;
855 break;
856 }
857
858 if (has_unaligned) {
859 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
860 data->sg_len, DMA_FROM_DEVICE);
861
862 align = host->align_buffer;
863
864 for_each_sg(data->sg, sg, host->sg_count, i) {
865 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
866 size = SDHCI_ADMA2_ALIGN -
867 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
868
869 buffer = sdhci_kmap_atomic(sg);
870 memcpy(buffer, align, size);
871 sdhci_kunmap_atomic(buffer);
872
873 align += SDHCI_ADMA2_ALIGN;
874 }
875 }
876 }
877 }
878}
879
880static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
881{
882 sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
883 if (host->flags & SDHCI_USE_64_BIT_DMA)
884 sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
885}
886
887static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
888{
889 if (host->bounce_buffer)
890 return host->bounce_addr;
891 else
892 return sg_dma_address(host->data->sg);
893}
894
895static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
896{
897 if (host->v4_mode)
898 sdhci_set_adma_addr(host, addr);
899 else
900 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
901}
902
903static unsigned int sdhci_target_timeout(struct sdhci_host *host,
904 struct mmc_command *cmd,
905 struct mmc_data *data)
906{
907 unsigned int target_timeout;
908
909 /* timeout in us */
910 if (!data) {
911 target_timeout = cmd->busy_timeout * 1000;
912 } else {
913 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
914 if (host->clock && data->timeout_clks) {
915 unsigned long long val;
916
917 /*
918 * data->timeout_clks is in units of clock cycles.
919 * host->clock is in Hz. target_timeout is in us.
920 * Hence, us = 1000000 * cycles / Hz. Round up.
921 */
922 val = 1000000ULL * data->timeout_clks;
923 if (do_div(val, host->clock))
924 target_timeout++;
925 target_timeout += val;
926 }
927 }
928
929 return target_timeout;
930}
931
932static void sdhci_calc_sw_timeout(struct sdhci_host *host,
933 struct mmc_command *cmd)
934{
935 struct mmc_data *data = cmd->data;
936 struct mmc_host *mmc = host->mmc;
937 struct mmc_ios *ios = &mmc->ios;
938 unsigned char bus_width = 1 << ios->bus_width;
939 unsigned int blksz;
940 unsigned int freq;
941 u64 target_timeout;
942 u64 transfer_time;
943
944 target_timeout = sdhci_target_timeout(host, cmd, data);
945 target_timeout *= NSEC_PER_USEC;
946
947 if (data) {
948 blksz = data->blksz;
949 freq = mmc->actual_clock ? : host->clock;
950 transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
951 do_div(transfer_time, freq);
952 /* multiply by '2' to account for any unknowns */
953 transfer_time = transfer_time * 2;
954 /* calculate timeout for the entire data */
955 host->data_timeout = data->blocks * target_timeout +
956 transfer_time;
957 } else {
958 host->data_timeout = target_timeout;
959 }
960
961 if (host->data_timeout)
962 host->data_timeout += MMC_CMD_TRANSFER_TIME;
963}
964
965static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
966 bool *too_big)
967{
968 u8 count;
969 struct mmc_data *data;
970 unsigned target_timeout, current_timeout;
971
972 *too_big = false;
973
974 /*
975 * If the host controller provides us with an incorrect timeout
976 * value, just skip the check and use the maximum. The hardware may take
977 * longer to time out, but that's much better than having a too-short
978 * timeout value.
979 */
980 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
981 return host->max_timeout_count;
982
983 /* Unspecified command, assume max */
984 if (cmd == NULL)
985 return host->max_timeout_count;
986
987 data = cmd->data;
988 /* Unspecified timeout, assume max */
989 if (!data && !cmd->busy_timeout)
990 return host->max_timeout_count;
991
992 /* timeout in us */
993 target_timeout = sdhci_target_timeout(host, cmd, data);
994
995 /*
996 * Figure out needed cycles.
997 * We do this in steps in order to fit inside a 32 bit int.
998 * The first step is the minimum timeout, which will have a
999 * minimum resolution of 6 bits:
1000 * (1) 2^13*1000 > 2^22,
1001 * (2) host->timeout_clk < 2^16
1002 * =>
1003 * (1) / (2) > 2^6
1004 */
1005 count = 0;
1006 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
1007 while (current_timeout < target_timeout) {
1008 count++;
1009 current_timeout <<= 1;
1010 if (count > host->max_timeout_count) {
1011 if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
1012 DBG("Too large timeout 0x%x requested for CMD%d!\n",
1013 count, cmd->opcode);
1014 count = host->max_timeout_count;
1015 *too_big = true;
1016 break;
1017 }
1018 }
1019
1020 return count;
1021}
1022
1023static void sdhci_set_transfer_irqs(struct sdhci_host *host)
1024{
1025 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
1026 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
1027
1028 if (host->flags & SDHCI_REQ_USE_DMA)
1029 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
1030 else
1031 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
1032
1033 if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
1034 host->ier |= SDHCI_INT_AUTO_CMD_ERR;
1035 else
1036 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
1037
1038 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1039 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1040}
1041
1042void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
1043{
1044 if (enable)
1045 host->ier |= SDHCI_INT_DATA_TIMEOUT;
1046 else
1047 host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
1048 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1049 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1050}
1051EXPORT_SYMBOL_GPL(sdhci_set_data_timeout_irq);
1052
1053void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1054{
1055 bool too_big = false;
1056 u8 count = sdhci_calc_timeout(host, cmd, &too_big);
1057
1058 if (too_big &&
1059 host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
1060 sdhci_calc_sw_timeout(host, cmd);
1061 sdhci_set_data_timeout_irq(host, false);
1062 } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
1063 sdhci_set_data_timeout_irq(host, true);
1064 }
1065
1066 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
1067}
1068EXPORT_SYMBOL_GPL(__sdhci_set_timeout);
1069
1070static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1071{
1072 if (host->ops->set_timeout)
1073 host->ops->set_timeout(host, cmd);
1074 else
1075 __sdhci_set_timeout(host, cmd);
1076}
1077
1078static void sdhci_initialize_data(struct sdhci_host *host,
1079 struct mmc_data *data)
1080{
1081 WARN_ON(host->data);
1082
1083 /* Sanity checks */
1084 BUG_ON(data->blksz * data->blocks > 524288);
1085 BUG_ON(data->blksz > host->mmc->max_blk_size);
1086 BUG_ON(data->blocks > 65535);
1087
1088 host->data = data;
1089 host->data_early = 0;
1090 host->data->bytes_xfered = 0;
1091}
1092
1093static inline void sdhci_set_block_info(struct sdhci_host *host,
1094 struct mmc_data *data)
1095{
1096 /* Set the DMA boundary value and block size */
1097 sdhci_writew(host,
1098 SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
1099 SDHCI_BLOCK_SIZE);
1100 /*
1101 * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
1102 * can be supported, in that case 16-bit block count register must be 0.
1103 */
1104 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1105 (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
1106 if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
1107 sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
1108 sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
1109 } else {
1110 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1111 }
1112}
1113
1114static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
1115{
1116 struct mmc_data *data = cmd->data;
1117
1118 sdhci_initialize_data(host, data);
1119
1120 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1121 struct scatterlist *sg;
1122 unsigned int length_mask, offset_mask;
1123 int i;
1124
1125 host->flags |= SDHCI_REQ_USE_DMA;
1126
1127 /*
1128 * FIXME: This doesn't account for merging when mapping the
1129 * scatterlist.
1130 *
1131 * The assumption here being that alignment and lengths are
1132 * the same after DMA mapping to device address space.
1133 */
1134 length_mask = 0;
1135 offset_mask = 0;
1136 if (host->flags & SDHCI_USE_ADMA) {
1137 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
1138 length_mask = 3;
1139 /*
1140 * As we use up to 3 byte chunks to work
1141 * around alignment problems, we need to
1142 * check the offset as well.
1143 */
1144 offset_mask = 3;
1145 }
1146 } else {
1147 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
1148 length_mask = 3;
1149 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
1150 offset_mask = 3;
1151 }
1152
1153 if (unlikely(length_mask | offset_mask)) {
1154 for_each_sg(data->sg, sg, data->sg_len, i) {
1155 if (sg->length & length_mask) {
1156 DBG("Reverting to PIO because of transfer size (%d)\n",
1157 sg->length);
1158 host->flags &= ~SDHCI_REQ_USE_DMA;
1159 break;
1160 }
1161 if (sg->offset & offset_mask) {
1162 DBG("Reverting to PIO because of bad alignment\n");
1163 host->flags &= ~SDHCI_REQ_USE_DMA;
1164 break;
1165 }
1166 }
1167 }
1168 }
1169
1170 if (host->flags & SDHCI_REQ_USE_DMA) {
1171 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1172
1173 if (sg_cnt <= 0) {
1174 /*
1175 * This only happens when someone fed
1176 * us an invalid request.
1177 */
1178 WARN_ON(1);
1179 host->flags &= ~SDHCI_REQ_USE_DMA;
1180 } else if (host->flags & SDHCI_USE_ADMA) {
1181 sdhci_adma_table_pre(host, data, sg_cnt);
1182 sdhci_set_adma_addr(host, host->adma_addr);
1183 } else {
1184 WARN_ON(sg_cnt != 1);
1185 sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
1186 }
1187 }
1188
1189 sdhci_config_dma(host);
1190
1191 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
1192 int flags;
1193
1194 flags = SG_MITER_ATOMIC;
1195 if (host->data->flags & MMC_DATA_READ)
1196 flags |= SG_MITER_TO_SG;
1197 else
1198 flags |= SG_MITER_FROM_SG;
1199 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1200 host->blocks = data->blocks;
1201 }
1202
1203 sdhci_set_transfer_irqs(host);
1204
1205 sdhci_set_block_info(host, data);
1206}
1207
1208#if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
1209
1210static int sdhci_external_dma_init(struct sdhci_host *host)
1211{
1212 int ret = 0;
1213 struct mmc_host *mmc = host->mmc;
1214
1215 host->tx_chan = dma_request_chan(mmc_dev(mmc), "tx");
1216 if (IS_ERR(host->tx_chan)) {
1217 ret = PTR_ERR(host->tx_chan);
1218 if (ret != -EPROBE_DEFER)
1219 pr_warn("Failed to request TX DMA channel.\n");
1220 host->tx_chan = NULL;
1221 return ret;
1222 }
1223
1224 host->rx_chan = dma_request_chan(mmc_dev(mmc), "rx");
1225 if (IS_ERR(host->rx_chan)) {
1226 if (host->tx_chan) {
1227 dma_release_channel(host->tx_chan);
1228 host->tx_chan = NULL;
1229 }
1230
1231 ret = PTR_ERR(host->rx_chan);
1232 if (ret != -EPROBE_DEFER)
1233 pr_warn("Failed to request RX DMA channel.\n");
1234 host->rx_chan = NULL;
1235 }
1236
1237 return ret;
1238}
1239
1240static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1241 struct mmc_data *data)
1242{
1243 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
1244}
1245
1246static int sdhci_external_dma_setup(struct sdhci_host *host,
1247 struct mmc_command *cmd)
1248{
1249 int ret, i;
1250 enum dma_transfer_direction dir;
1251 struct dma_async_tx_descriptor *desc;
1252 struct mmc_data *data = cmd->data;
1253 struct dma_chan *chan;
1254 struct dma_slave_config cfg;
1255 dma_cookie_t cookie;
1256 int sg_cnt;
1257
1258 if (!host->mapbase)
1259 return -EINVAL;
1260
1261 memset(&cfg, 0, sizeof(cfg));
1262 cfg.src_addr = host->mapbase + SDHCI_BUFFER;
1263 cfg.dst_addr = host->mapbase + SDHCI_BUFFER;
1264 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1265 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1266 cfg.src_maxburst = data->blksz / 4;
1267 cfg.dst_maxburst = data->blksz / 4;
1268
1269 /* Sanity check: all the SG entries must be aligned by block size. */
1270 for (i = 0; i < data->sg_len; i++) {
1271 if ((data->sg + i)->length % data->blksz)
1272 return -EINVAL;
1273 }
1274
1275 chan = sdhci_external_dma_channel(host, data);
1276
1277 ret = dmaengine_slave_config(chan, &cfg);
1278 if (ret)
1279 return ret;
1280
1281 sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1282 if (sg_cnt <= 0)
1283 return -EINVAL;
1284
1285 dir = data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
1286 desc = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, dir,
1287 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1288 if (!desc)
1289 return -EINVAL;
1290
1291 desc->callback = NULL;
1292 desc->callback_param = NULL;
1293
1294 cookie = dmaengine_submit(desc);
1295 if (dma_submit_error(cookie))
1296 ret = cookie;
1297
1298 return ret;
1299}
1300
1301static void sdhci_external_dma_release(struct sdhci_host *host)
1302{
1303 if (host->tx_chan) {
1304 dma_release_channel(host->tx_chan);
1305 host->tx_chan = NULL;
1306 }
1307
1308 if (host->rx_chan) {
1309 dma_release_channel(host->rx_chan);
1310 host->rx_chan = NULL;
1311 }
1312
1313 sdhci_switch_external_dma(host, false);
1314}
1315
1316static void __sdhci_external_dma_prepare_data(struct sdhci_host *host,
1317 struct mmc_command *cmd)
1318{
1319 struct mmc_data *data = cmd->data;
1320
1321 sdhci_initialize_data(host, data);
1322
1323 host->flags |= SDHCI_REQ_USE_DMA;
1324 sdhci_set_transfer_irqs(host);
1325
1326 sdhci_set_block_info(host, data);
1327}
1328
1329static void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1330 struct mmc_command *cmd)
1331{
1332 if (!sdhci_external_dma_setup(host, cmd)) {
1333 __sdhci_external_dma_prepare_data(host, cmd);
1334 } else {
1335 sdhci_external_dma_release(host);
1336 pr_err("%s: Cannot use external DMA, switch to the DMA/PIO which standard SDHCI provides.\n",
1337 mmc_hostname(host->mmc));
1338 sdhci_prepare_data(host, cmd);
1339 }
1340}
1341
1342static void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1343 struct mmc_command *cmd)
1344{
1345 struct dma_chan *chan;
1346
1347 if (!cmd->data)
1348 return;
1349
1350 chan = sdhci_external_dma_channel(host, cmd->data);
1351 if (chan)
1352 dma_async_issue_pending(chan);
1353}
1354
1355#else
1356
1357static inline int sdhci_external_dma_init(struct sdhci_host *host)
1358{
1359 return -EOPNOTSUPP;
1360}
1361
1362static inline void sdhci_external_dma_release(struct sdhci_host *host)
1363{
1364}
1365
1366static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1367 struct mmc_command *cmd)
1368{
1369 /* This should never happen */
1370 WARN_ON_ONCE(1);
1371}
1372
1373static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1374 struct mmc_command *cmd)
1375{
1376}
1377
1378static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1379 struct mmc_data *data)
1380{
1381 return NULL;
1382}
1383
1384#endif
1385
1386void sdhci_switch_external_dma(struct sdhci_host *host, bool en)
1387{
1388 host->use_external_dma = en;
1389}
1390EXPORT_SYMBOL_GPL(sdhci_switch_external_dma);
1391
1392static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
1393 struct mmc_request *mrq)
1394{
1395 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
1396 !mrq->cap_cmd_during_tfr;
1397}
1398
1399static inline bool sdhci_auto_cmd23(struct sdhci_host *host,
1400 struct mmc_request *mrq)
1401{
1402 return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
1403}
1404
1405static inline bool sdhci_manual_cmd23(struct sdhci_host *host,
1406 struct mmc_request *mrq)
1407{
1408 return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23);
1409}
1410
1411static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
1412 struct mmc_command *cmd,
1413 u16 *mode)
1414{
1415 bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
1416 (cmd->opcode != SD_IO_RW_EXTENDED);
1417 bool use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq);
1418 u16 ctrl2;
1419
1420 /*
1421 * In case of Version 4.10 or later, use of 'Auto CMD Auto
1422 * Select' is recommended rather than use of 'Auto CMD12
1423 * Enable' or 'Auto CMD23 Enable'. We require Version 4 Mode
1424 * here because some controllers (e.g sdhci-of-dwmshc) expect it.
1425 */
1426 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1427 (use_cmd12 || use_cmd23)) {
1428 *mode |= SDHCI_TRNS_AUTO_SEL;
1429
1430 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1431 if (use_cmd23)
1432 ctrl2 |= SDHCI_CMD23_ENABLE;
1433 else
1434 ctrl2 &= ~SDHCI_CMD23_ENABLE;
1435 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
1436
1437 return;
1438 }
1439
1440 /*
1441 * If we are sending CMD23, CMD12 never gets sent
1442 * on successful completion (so no Auto-CMD12).
1443 */
1444 if (use_cmd12)
1445 *mode |= SDHCI_TRNS_AUTO_CMD12;
1446 else if (use_cmd23)
1447 *mode |= SDHCI_TRNS_AUTO_CMD23;
1448}
1449
1450static void sdhci_set_transfer_mode(struct sdhci_host *host,
1451 struct mmc_command *cmd)
1452{
1453 u16 mode = 0;
1454 struct mmc_data *data = cmd->data;
1455
1456 if (data == NULL) {
1457 if (host->quirks2 &
1458 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
1459 /* must not clear SDHCI_TRANSFER_MODE when tuning */
1460 if (!mmc_op_tuning(cmd->opcode))
1461 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1462 } else {
1463 /* clear Auto CMD settings for no data CMDs */
1464 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1465 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
1466 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
1467 }
1468 return;
1469 }
1470
1471 WARN_ON(!host->data);
1472
1473 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1474 mode = SDHCI_TRNS_BLK_CNT_EN;
1475
1476 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
1477 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
1478 sdhci_auto_cmd_select(host, cmd, &mode);
1479 if (sdhci_auto_cmd23(host, cmd->mrq))
1480 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
1481 }
1482
1483 if (data->flags & MMC_DATA_READ)
1484 mode |= SDHCI_TRNS_READ;
1485 if (host->flags & SDHCI_REQ_USE_DMA)
1486 mode |= SDHCI_TRNS_DMA;
1487
1488 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1489}
1490
1491static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
1492{
1493 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1494 ((mrq->cmd && mrq->cmd->error) ||
1495 (mrq->sbc && mrq->sbc->error) ||
1496 (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
1497 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1498}
1499
1500static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq)
1501{
1502 int i;
1503
1504 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1505 if (host->mrqs_done[i] == mrq) {
1506 WARN_ON(1);
1507 return;
1508 }
1509 }
1510
1511 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1512 if (!host->mrqs_done[i]) {
1513 host->mrqs_done[i] = mrq;
1514 break;
1515 }
1516 }
1517
1518 WARN_ON(i >= SDHCI_MAX_MRQS);
1519}
1520
1521static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1522{
1523 if (host->cmd && host->cmd->mrq == mrq)
1524 host->cmd = NULL;
1525
1526 if (host->data_cmd && host->data_cmd->mrq == mrq)
1527 host->data_cmd = NULL;
1528
1529 if (host->deferred_cmd && host->deferred_cmd->mrq == mrq)
1530 host->deferred_cmd = NULL;
1531
1532 if (host->data && host->data->mrq == mrq)
1533 host->data = NULL;
1534
1535 if (sdhci_needs_reset(host, mrq))
1536 host->pending_reset = true;
1537
1538 sdhci_set_mrq_done(host, mrq);
1539
1540 sdhci_del_timer(host, mrq);
1541
1542 if (!sdhci_has_requests(host))
1543 sdhci_led_deactivate(host);
1544}
1545
1546static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1547{
1548 __sdhci_finish_mrq(host, mrq);
1549
1550 queue_work(host->complete_wq, &host->complete_work);
1551}
1552
1553static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout)
1554{
1555 struct mmc_command *data_cmd = host->data_cmd;
1556 struct mmc_data *data = host->data;
1557
1558 host->data = NULL;
1559 host->data_cmd = NULL;
1560
1561 /*
1562 * The controller needs a reset of internal state machines upon error
1563 * conditions.
1564 */
1565 if (data->error) {
1566 if (!host->cmd || host->cmd == data_cmd)
1567 sdhci_reset_for(host, REQUEST_ERROR);
1568 else
1569 sdhci_reset_for(host, REQUEST_ERROR_DATA_ONLY);
1570 }
1571
1572 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1573 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1574 sdhci_adma_table_post(host, data);
1575
1576 /*
1577 * The specification states that the block count register must
1578 * be updated, but it does not specify at what point in the
1579 * data flow. That makes the register entirely useless to read
1580 * back so we have to assume that nothing made it to the card
1581 * in the event of an error.
1582 */
1583 if (data->error)
1584 data->bytes_xfered = 0;
1585 else
1586 data->bytes_xfered = data->blksz * data->blocks;
1587
1588 /*
1589 * Need to send CMD12 if -
1590 * a) open-ended multiblock transfer not using auto CMD12 (no CMD23)
1591 * b) error in multiblock transfer
1592 */
1593 if (data->stop &&
1594 ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) ||
1595 data->error)) {
1596 /*
1597 * 'cap_cmd_during_tfr' request must not use the command line
1598 * after mmc_command_done() has been called. It is upper layer's
1599 * responsibility to send the stop command if required.
1600 */
1601 if (data->mrq->cap_cmd_during_tfr) {
1602 __sdhci_finish_mrq(host, data->mrq);
1603 } else {
1604 /* Avoid triggering warning in sdhci_send_command() */
1605 host->cmd = NULL;
1606 if (!sdhci_send_command(host, data->stop)) {
1607 if (sw_data_timeout) {
1608 /*
1609 * This is anyway a sw data timeout, so
1610 * give up now.
1611 */
1612 data->stop->error = -EIO;
1613 __sdhci_finish_mrq(host, data->mrq);
1614 } else {
1615 WARN_ON(host->deferred_cmd);
1616 host->deferred_cmd = data->stop;
1617 }
1618 }
1619 }
1620 } else {
1621 __sdhci_finish_mrq(host, data->mrq);
1622 }
1623}
1624
1625static void sdhci_finish_data(struct sdhci_host *host)
1626{
1627 __sdhci_finish_data(host, false);
1628}
1629
1630static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1631{
1632 int flags;
1633 u32 mask;
1634 unsigned long timeout;
1635
1636 WARN_ON(host->cmd);
1637
1638 /* Initially, a command has no error */
1639 cmd->error = 0;
1640
1641 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1642 cmd->opcode == MMC_STOP_TRANSMISSION)
1643 cmd->flags |= MMC_RSP_BUSY;
1644
1645 mask = SDHCI_CMD_INHIBIT;
1646 if (sdhci_data_line_cmd(cmd))
1647 mask |= SDHCI_DATA_INHIBIT;
1648
1649 /* We shouldn't wait for data inihibit for stop commands, even
1650 though they might use busy signaling */
1651 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1652 mask &= ~SDHCI_DATA_INHIBIT;
1653
1654 if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)
1655 return false;
1656
1657 host->cmd = cmd;
1658 host->data_timeout = 0;
1659 if (sdhci_data_line_cmd(cmd)) {
1660 WARN_ON(host->data_cmd);
1661 host->data_cmd = cmd;
1662 sdhci_set_timeout(host, cmd);
1663 }
1664
1665 if (cmd->data) {
1666 if (host->use_external_dma)
1667 sdhci_external_dma_prepare_data(host, cmd);
1668 else
1669 sdhci_prepare_data(host, cmd);
1670 }
1671
1672 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1673
1674 sdhci_set_transfer_mode(host, cmd);
1675
1676 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1677 WARN_ONCE(1, "Unsupported response type!\n");
1678 /*
1679 * This does not happen in practice because 136-bit response
1680 * commands never have busy waiting, so rather than complicate
1681 * the error path, just remove busy waiting and continue.
1682 */
1683 cmd->flags &= ~MMC_RSP_BUSY;
1684 }
1685
1686 if (!(cmd->flags & MMC_RSP_PRESENT))
1687 flags = SDHCI_CMD_RESP_NONE;
1688 else if (cmd->flags & MMC_RSP_136)
1689 flags = SDHCI_CMD_RESP_LONG;
1690 else if (cmd->flags & MMC_RSP_BUSY)
1691 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1692 else
1693 flags = SDHCI_CMD_RESP_SHORT;
1694
1695 if (cmd->flags & MMC_RSP_CRC)
1696 flags |= SDHCI_CMD_CRC;
1697 if (cmd->flags & MMC_RSP_OPCODE)
1698 flags |= SDHCI_CMD_INDEX;
1699
1700 /* CMD19 is special in that the Data Present Select should be set */
1701 if (cmd->data || mmc_op_tuning(cmd->opcode))
1702 flags |= SDHCI_CMD_DATA;
1703
1704 timeout = jiffies;
1705 if (host->data_timeout)
1706 timeout += nsecs_to_jiffies(host->data_timeout);
1707 else if (!cmd->data && cmd->busy_timeout > 9000)
1708 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1709 else
1710 timeout += 10 * HZ;
1711 sdhci_mod_timer(host, cmd->mrq, timeout);
1712
1713 if (host->use_external_dma)
1714 sdhci_external_dma_pre_transfer(host, cmd);
1715
1716 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1717
1718 return true;
1719}
1720
1721static bool sdhci_present_error(struct sdhci_host *host,
1722 struct mmc_command *cmd, bool present)
1723{
1724 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1725 cmd->error = -ENOMEDIUM;
1726 return true;
1727 }
1728
1729 return false;
1730}
1731
1732static bool sdhci_send_command_retry(struct sdhci_host *host,
1733 struct mmc_command *cmd,
1734 unsigned long flags)
1735 __releases(host->lock)
1736 __acquires(host->lock)
1737{
1738 struct mmc_command *deferred_cmd = host->deferred_cmd;
1739 int timeout = 10; /* Approx. 10 ms */
1740 bool present;
1741
1742 while (!sdhci_send_command(host, cmd)) {
1743 if (!timeout--) {
1744 pr_err("%s: Controller never released inhibit bit(s).\n",
1745 mmc_hostname(host->mmc));
1746 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
1747 sdhci_dumpregs(host);
1748 cmd->error = -EIO;
1749 return false;
1750 }
1751
1752 spin_unlock_irqrestore(&host->lock, flags);
1753
1754 usleep_range(1000, 1250);
1755
1756 present = host->mmc->ops->get_cd(host->mmc);
1757
1758 spin_lock_irqsave(&host->lock, flags);
1759
1760 /* A deferred command might disappear, handle that */
1761 if (cmd == deferred_cmd && cmd != host->deferred_cmd)
1762 return true;
1763
1764 if (sdhci_present_error(host, cmd, present))
1765 return false;
1766 }
1767
1768 if (cmd == host->deferred_cmd)
1769 host->deferred_cmd = NULL;
1770
1771 return true;
1772}
1773
1774static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1775{
1776 int i, reg;
1777
1778 for (i = 0; i < 4; i++) {
1779 reg = SDHCI_RESPONSE + (3 - i) * 4;
1780 cmd->resp[i] = sdhci_readl(host, reg);
1781 }
1782
1783 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1784 return;
1785
1786 /* CRC is stripped so we need to do some shifting */
1787 for (i = 0; i < 4; i++) {
1788 cmd->resp[i] <<= 8;
1789 if (i != 3)
1790 cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1791 }
1792}
1793
1794static void sdhci_finish_command(struct sdhci_host *host)
1795{
1796 struct mmc_command *cmd = host->cmd;
1797
1798 host->cmd = NULL;
1799
1800 if (cmd->flags & MMC_RSP_PRESENT) {
1801 if (cmd->flags & MMC_RSP_136) {
1802 sdhci_read_rsp_136(host, cmd);
1803 } else {
1804 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1805 }
1806 }
1807
1808 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1809 mmc_command_done(host->mmc, cmd->mrq);
1810
1811 /*
1812 * The host can send and interrupt when the busy state has
1813 * ended, allowing us to wait without wasting CPU cycles.
1814 * The busy signal uses DAT0 so this is similar to waiting
1815 * for data to complete.
1816 *
1817 * Note: The 1.0 specification is a bit ambiguous about this
1818 * feature so there might be some problems with older
1819 * controllers.
1820 */
1821 if (cmd->flags & MMC_RSP_BUSY) {
1822 if (cmd->data) {
1823 DBG("Cannot wait for busy signal when also doing a data transfer");
1824 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1825 cmd == host->data_cmd) {
1826 /* Command complete before busy is ended */
1827 return;
1828 }
1829 }
1830
1831 /* Finished CMD23, now send actual command. */
1832 if (cmd == cmd->mrq->sbc) {
1833 if (!sdhci_send_command(host, cmd->mrq->cmd)) {
1834 WARN_ON(host->deferred_cmd);
1835 host->deferred_cmd = cmd->mrq->cmd;
1836 }
1837 } else {
1838
1839 /* Processed actual command. */
1840 if (host->data && host->data_early)
1841 sdhci_finish_data(host);
1842
1843 if (!cmd->data)
1844 __sdhci_finish_mrq(host, cmd->mrq);
1845 }
1846}
1847
1848static u16 sdhci_get_preset_value(struct sdhci_host *host)
1849{
1850 u16 preset = 0;
1851
1852 switch (host->timing) {
1853 case MMC_TIMING_MMC_HS:
1854 case MMC_TIMING_SD_HS:
1855 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HIGH_SPEED);
1856 break;
1857 case MMC_TIMING_UHS_SDR12:
1858 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1859 break;
1860 case MMC_TIMING_UHS_SDR25:
1861 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1862 break;
1863 case MMC_TIMING_UHS_SDR50:
1864 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1865 break;
1866 case MMC_TIMING_UHS_SDR104:
1867 case MMC_TIMING_MMC_HS200:
1868 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1869 break;
1870 case MMC_TIMING_UHS_DDR50:
1871 case MMC_TIMING_MMC_DDR52:
1872 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1873 break;
1874 case MMC_TIMING_MMC_HS400:
1875 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1876 break;
1877 default:
1878 pr_warn("%s: Invalid UHS-I mode selected\n",
1879 mmc_hostname(host->mmc));
1880 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1881 break;
1882 }
1883 return preset;
1884}
1885
1886u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1887 unsigned int *actual_clock)
1888{
1889 int div = 0; /* Initialized for compiler warning */
1890 int real_div = div, clk_mul = 1;
1891 u16 clk = 0;
1892 bool switch_base_clk = false;
1893
1894 if (host->version >= SDHCI_SPEC_300) {
1895 if (host->preset_enabled) {
1896 u16 pre_val;
1897
1898 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1899 pre_val = sdhci_get_preset_value(host);
1900 div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
1901 if (host->clk_mul &&
1902 (pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
1903 clk = SDHCI_PROG_CLOCK_MODE;
1904 real_div = div + 1;
1905 clk_mul = host->clk_mul;
1906 } else {
1907 real_div = max_t(int, 1, div << 1);
1908 }
1909 goto clock_set;
1910 }
1911
1912 /*
1913 * Check if the Host Controller supports Programmable Clock
1914 * Mode.
1915 */
1916 if (host->clk_mul) {
1917 for (div = 1; div <= 1024; div++) {
1918 if ((host->max_clk * host->clk_mul / div)
1919 <= clock)
1920 break;
1921 }
1922 if ((host->max_clk * host->clk_mul / div) <= clock) {
1923 /*
1924 * Set Programmable Clock Mode in the Clock
1925 * Control register.
1926 */
1927 clk = SDHCI_PROG_CLOCK_MODE;
1928 real_div = div;
1929 clk_mul = host->clk_mul;
1930 div--;
1931 } else {
1932 /*
1933 * Divisor can be too small to reach clock
1934 * speed requirement. Then use the base clock.
1935 */
1936 switch_base_clk = true;
1937 }
1938 }
1939
1940 if (!host->clk_mul || switch_base_clk) {
1941 /* Version 3.00 divisors must be a multiple of 2. */
1942 if (host->max_clk <= clock)
1943 div = 1;
1944 else {
1945 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1946 div += 2) {
1947 if ((host->max_clk / div) <= clock)
1948 break;
1949 }
1950 }
1951 real_div = div;
1952 div >>= 1;
1953 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1954 && !div && host->max_clk <= 25000000)
1955 div = 1;
1956 }
1957 } else {
1958 /* Version 2.00 divisors must be a power of 2. */
1959 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1960 if ((host->max_clk / div) <= clock)
1961 break;
1962 }
1963 real_div = div;
1964 div >>= 1;
1965 }
1966
1967clock_set:
1968 if (real_div)
1969 *actual_clock = (host->max_clk * clk_mul) / real_div;
1970 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1971 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1972 << SDHCI_DIVIDER_HI_SHIFT;
1973
1974 return clk;
1975}
1976EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1977
1978void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1979{
1980 ktime_t timeout;
1981
1982 clk |= SDHCI_CLOCK_INT_EN;
1983 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1984
1985 /* Wait max 150 ms */
1986 timeout = ktime_add_ms(ktime_get(), 150);
1987 while (1) {
1988 bool timedout = ktime_after(ktime_get(), timeout);
1989
1990 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1991 if (clk & SDHCI_CLOCK_INT_STABLE)
1992 break;
1993 if (timedout) {
1994 pr_err("%s: Internal clock never stabilised.\n",
1995 mmc_hostname(host->mmc));
1996 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
1997 sdhci_dumpregs(host);
1998 return;
1999 }
2000 udelay(10);
2001 }
2002
2003 if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
2004 clk |= SDHCI_CLOCK_PLL_EN;
2005 clk &= ~SDHCI_CLOCK_INT_STABLE;
2006 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2007
2008 /* Wait max 150 ms */
2009 timeout = ktime_add_ms(ktime_get(), 150);
2010 while (1) {
2011 bool timedout = ktime_after(ktime_get(), timeout);
2012
2013 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2014 if (clk & SDHCI_CLOCK_INT_STABLE)
2015 break;
2016 if (timedout) {
2017 pr_err("%s: PLL clock never stabilised.\n",
2018 mmc_hostname(host->mmc));
2019 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
2020 sdhci_dumpregs(host);
2021 return;
2022 }
2023 udelay(10);
2024 }
2025 }
2026
2027 clk |= SDHCI_CLOCK_CARD_EN;
2028 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2029}
2030EXPORT_SYMBOL_GPL(sdhci_enable_clk);
2031
2032void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
2033{
2034 u16 clk;
2035
2036 host->mmc->actual_clock = 0;
2037
2038 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
2039
2040 if (clock == 0)
2041 return;
2042
2043 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
2044 sdhci_enable_clk(host, clk);
2045}
2046EXPORT_SYMBOL_GPL(sdhci_set_clock);
2047
2048static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
2049 unsigned short vdd)
2050{
2051 struct mmc_host *mmc = host->mmc;
2052
2053 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2054
2055 if (mode != MMC_POWER_OFF)
2056 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
2057 else
2058 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2059}
2060
2061void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
2062 unsigned short vdd)
2063{
2064 u8 pwr = 0;
2065
2066 if (mode != MMC_POWER_OFF) {
2067 switch (1 << vdd) {
2068 case MMC_VDD_165_195:
2069 /*
2070 * Without a regulator, SDHCI does not support 2.0v
2071 * so we only get here if the driver deliberately
2072 * added the 2.0v range to ocr_avail. Map it to 1.8v
2073 * for the purpose of turning on the power.
2074 */
2075 case MMC_VDD_20_21:
2076 pwr = SDHCI_POWER_180;
2077 break;
2078 case MMC_VDD_29_30:
2079 case MMC_VDD_30_31:
2080 pwr = SDHCI_POWER_300;
2081 break;
2082 case MMC_VDD_32_33:
2083 case MMC_VDD_33_34:
2084 /*
2085 * 3.4 ~ 3.6V are valid only for those platforms where it's
2086 * known that the voltage range is supported by hardware.
2087 */
2088 case MMC_VDD_34_35:
2089 case MMC_VDD_35_36:
2090 pwr = SDHCI_POWER_330;
2091 break;
2092 default:
2093 WARN(1, "%s: Invalid vdd %#x\n",
2094 mmc_hostname(host->mmc), vdd);
2095 break;
2096 }
2097 }
2098
2099 if (host->pwr == pwr)
2100 return;
2101
2102 host->pwr = pwr;
2103
2104 if (pwr == 0) {
2105 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2106 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2107 sdhci_runtime_pm_bus_off(host);
2108 } else {
2109 /*
2110 * Spec says that we should clear the power reg before setting
2111 * a new value. Some controllers don't seem to like this though.
2112 */
2113 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
2114 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2115
2116 /*
2117 * At least the Marvell CaFe chip gets confused if we set the
2118 * voltage and set turn on power at the same time, so set the
2119 * voltage first.
2120 */
2121 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
2122 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2123
2124 pwr |= SDHCI_POWER_ON;
2125
2126 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2127
2128 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2129 sdhci_runtime_pm_bus_on(host);
2130
2131 /*
2132 * Some controllers need an extra 10ms delay of 10ms before
2133 * they can apply clock after applying power
2134 */
2135 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
2136 mdelay(10);
2137 }
2138}
2139EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
2140
2141void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
2142 unsigned short vdd)
2143{
2144 if (IS_ERR(host->mmc->supply.vmmc))
2145 sdhci_set_power_noreg(host, mode, vdd);
2146 else
2147 sdhci_set_power_reg(host, mode, vdd);
2148}
2149EXPORT_SYMBOL_GPL(sdhci_set_power);
2150
2151/*
2152 * Some controllers need to configure a valid bus voltage on their power
2153 * register regardless of whether an external regulator is taking care of power
2154 * supply. This helper function takes care of it if set as the controller's
2155 * sdhci_ops.set_power callback.
2156 */
2157void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
2158 unsigned char mode,
2159 unsigned short vdd)
2160{
2161 if (!IS_ERR(host->mmc->supply.vmmc)) {
2162 struct mmc_host *mmc = host->mmc;
2163
2164 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2165 }
2166 sdhci_set_power_noreg(host, mode, vdd);
2167}
2168EXPORT_SYMBOL_GPL(sdhci_set_power_and_bus_voltage);
2169
2170/*****************************************************************************\
2171 * *
2172 * MMC callbacks *
2173 * *
2174\*****************************************************************************/
2175
2176void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
2177{
2178 struct sdhci_host *host = mmc_priv(mmc);
2179 struct mmc_command *cmd;
2180 unsigned long flags;
2181 bool present;
2182
2183 /* Firstly check card presence */
2184 present = mmc->ops->get_cd(mmc);
2185
2186 spin_lock_irqsave(&host->lock, flags);
2187
2188 sdhci_led_activate(host);
2189
2190 if (sdhci_present_error(host, mrq->cmd, present))
2191 goto out_finish;
2192
2193 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2194
2195 if (!sdhci_send_command_retry(host, cmd, flags))
2196 goto out_finish;
2197
2198 spin_unlock_irqrestore(&host->lock, flags);
2199
2200 return;
2201
2202out_finish:
2203 sdhci_finish_mrq(host, mrq);
2204 spin_unlock_irqrestore(&host->lock, flags);
2205}
2206EXPORT_SYMBOL_GPL(sdhci_request);
2207
2208int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq)
2209{
2210 struct sdhci_host *host = mmc_priv(mmc);
2211 struct mmc_command *cmd;
2212 unsigned long flags;
2213 int ret = 0;
2214
2215 spin_lock_irqsave(&host->lock, flags);
2216
2217 if (sdhci_present_error(host, mrq->cmd, true)) {
2218 sdhci_finish_mrq(host, mrq);
2219 goto out_finish;
2220 }
2221
2222 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2223
2224 /*
2225 * The HSQ may send a command in interrupt context without polling
2226 * the busy signaling, which means we should return BUSY if controller
2227 * has not released inhibit bits to allow HSQ trying to send request
2228 * again in non-atomic context. So we should not finish this request
2229 * here.
2230 */
2231 if (!sdhci_send_command(host, cmd))
2232 ret = -EBUSY;
2233 else
2234 sdhci_led_activate(host);
2235
2236out_finish:
2237 spin_unlock_irqrestore(&host->lock, flags);
2238 return ret;
2239}
2240EXPORT_SYMBOL_GPL(sdhci_request_atomic);
2241
2242void sdhci_set_bus_width(struct sdhci_host *host, int width)
2243{
2244 u8 ctrl;
2245
2246 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2247 if (width == MMC_BUS_WIDTH_8) {
2248 ctrl &= ~SDHCI_CTRL_4BITBUS;
2249 ctrl |= SDHCI_CTRL_8BITBUS;
2250 } else {
2251 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
2252 ctrl &= ~SDHCI_CTRL_8BITBUS;
2253 if (width == MMC_BUS_WIDTH_4)
2254 ctrl |= SDHCI_CTRL_4BITBUS;
2255 else
2256 ctrl &= ~SDHCI_CTRL_4BITBUS;
2257 }
2258 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2259}
2260EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
2261
2262void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
2263{
2264 u16 ctrl_2;
2265
2266 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2267 /* Select Bus Speed Mode for host */
2268 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
2269 if ((timing == MMC_TIMING_MMC_HS200) ||
2270 (timing == MMC_TIMING_UHS_SDR104))
2271 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
2272 else if (timing == MMC_TIMING_UHS_SDR12)
2273 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
2274 else if (timing == MMC_TIMING_UHS_SDR25)
2275 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
2276 else if (timing == MMC_TIMING_UHS_SDR50)
2277 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
2278 else if ((timing == MMC_TIMING_UHS_DDR50) ||
2279 (timing == MMC_TIMING_MMC_DDR52))
2280 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
2281 else if (timing == MMC_TIMING_MMC_HS400)
2282 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
2283 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2284}
2285EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
2286
2287static bool sdhci_timing_has_preset(unsigned char timing)
2288{
2289 switch (timing) {
2290 case MMC_TIMING_UHS_SDR12:
2291 case MMC_TIMING_UHS_SDR25:
2292 case MMC_TIMING_UHS_SDR50:
2293 case MMC_TIMING_UHS_SDR104:
2294 case MMC_TIMING_UHS_DDR50:
2295 case MMC_TIMING_MMC_DDR52:
2296 return true;
2297 }
2298 return false;
2299}
2300
2301static bool sdhci_preset_needed(struct sdhci_host *host, unsigned char timing)
2302{
2303 return !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
2304 sdhci_timing_has_preset(timing);
2305}
2306
2307static bool sdhci_presetable_values_change(struct sdhci_host *host, struct mmc_ios *ios)
2308{
2309 /*
2310 * Preset Values are: Driver Strength, Clock Generator and SDCLK/RCLK
2311 * Frequency. Check if preset values need to be enabled, or the Driver
2312 * Strength needs updating. Note, clock changes are handled separately.
2313 */
2314 return !host->preset_enabled &&
2315 (sdhci_preset_needed(host, ios->timing) || host->drv_type != ios->drv_type);
2316}
2317
2318void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2319{
2320 struct sdhci_host *host = mmc_priv(mmc);
2321 bool reinit_uhs = host->reinit_uhs;
2322 bool turning_on_clk = false;
2323 u8 ctrl;
2324
2325 host->reinit_uhs = false;
2326
2327 if (ios->power_mode == MMC_POWER_UNDEFINED)
2328 return;
2329
2330 if (host->flags & SDHCI_DEVICE_DEAD) {
2331 if (!IS_ERR(mmc->supply.vmmc) &&
2332 ios->power_mode == MMC_POWER_OFF)
2333 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
2334 return;
2335 }
2336
2337 /*
2338 * Reset the chip on each power off.
2339 * Should clear out any weird states.
2340 */
2341 if (ios->power_mode == MMC_POWER_OFF) {
2342 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2343 sdhci_reinit(host);
2344 }
2345
2346 if (host->version >= SDHCI_SPEC_300 &&
2347 (ios->power_mode == MMC_POWER_UP) &&
2348 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
2349 sdhci_enable_preset_value(host, false);
2350
2351 if (!ios->clock || ios->clock != host->clock) {
2352 turning_on_clk = ios->clock && !host->clock;
2353
2354 host->ops->set_clock(host, ios->clock);
2355 host->clock = ios->clock;
2356
2357 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
2358 host->clock) {
2359 host->timeout_clk = mmc->actual_clock ?
2360 mmc->actual_clock / 1000 :
2361 host->clock / 1000;
2362 mmc->max_busy_timeout =
2363 host->ops->get_max_timeout_count ?
2364 host->ops->get_max_timeout_count(host) :
2365 1 << 27;
2366 mmc->max_busy_timeout /= host->timeout_clk;
2367 }
2368 }
2369
2370 if (host->ops->set_power)
2371 host->ops->set_power(host, ios->power_mode, ios->vdd);
2372 else
2373 sdhci_set_power(host, ios->power_mode, ios->vdd);
2374
2375 if (host->ops->platform_send_init_74_clocks)
2376 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
2377
2378 host->ops->set_bus_width(host, ios->bus_width);
2379
2380 /*
2381 * Special case to avoid multiple clock changes during voltage
2382 * switching.
2383 */
2384 if (!reinit_uhs &&
2385 turning_on_clk &&
2386 host->timing == ios->timing &&
2387 host->version >= SDHCI_SPEC_300 &&
2388 !sdhci_presetable_values_change(host, ios))
2389 return;
2390
2391 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2392
2393 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
2394 if (ios->timing == MMC_TIMING_SD_HS ||
2395 ios->timing == MMC_TIMING_MMC_HS ||
2396 ios->timing == MMC_TIMING_MMC_HS400 ||
2397 ios->timing == MMC_TIMING_MMC_HS200 ||
2398 ios->timing == MMC_TIMING_MMC_DDR52 ||
2399 ios->timing == MMC_TIMING_UHS_SDR50 ||
2400 ios->timing == MMC_TIMING_UHS_SDR104 ||
2401 ios->timing == MMC_TIMING_UHS_DDR50 ||
2402 ios->timing == MMC_TIMING_UHS_SDR25)
2403 ctrl |= SDHCI_CTRL_HISPD;
2404 else
2405 ctrl &= ~SDHCI_CTRL_HISPD;
2406 }
2407
2408 if (host->version >= SDHCI_SPEC_300) {
2409 u16 clk, ctrl_2;
2410
2411 /*
2412 * According to SDHCI Spec v3.00, if the Preset Value
2413 * Enable in the Host Control 2 register is set, we
2414 * need to reset SD Clock Enable before changing High
2415 * Speed Enable to avoid generating clock glitches.
2416 */
2417 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2418 if (clk & SDHCI_CLOCK_CARD_EN) {
2419 clk &= ~SDHCI_CLOCK_CARD_EN;
2420 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2421 }
2422
2423 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2424
2425 if (!host->preset_enabled) {
2426 /*
2427 * We only need to set Driver Strength if the
2428 * preset value enable is not set.
2429 */
2430 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2431 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
2432 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
2433 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
2434 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
2435 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2436 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
2437 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
2438 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
2439 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
2440 else {
2441 pr_warn("%s: invalid driver type, default to driver type B\n",
2442 mmc_hostname(mmc));
2443 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2444 }
2445
2446 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2447 host->drv_type = ios->drv_type;
2448 }
2449
2450 host->ops->set_uhs_signaling(host, ios->timing);
2451 host->timing = ios->timing;
2452
2453 if (sdhci_preset_needed(host, ios->timing)) {
2454 u16 preset;
2455
2456 sdhci_enable_preset_value(host, true);
2457 preset = sdhci_get_preset_value(host);
2458 ios->drv_type = FIELD_GET(SDHCI_PRESET_DRV_MASK,
2459 preset);
2460 host->drv_type = ios->drv_type;
2461 }
2462
2463 /* Re-enable SD Clock */
2464 host->ops->set_clock(host, host->clock);
2465 } else
2466 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2467}
2468EXPORT_SYMBOL_GPL(sdhci_set_ios);
2469
2470static int sdhci_get_cd(struct mmc_host *mmc)
2471{
2472 struct sdhci_host *host = mmc_priv(mmc);
2473 int gpio_cd = mmc_gpio_get_cd(mmc);
2474
2475 if (host->flags & SDHCI_DEVICE_DEAD)
2476 return 0;
2477
2478 /* If nonremovable, assume that the card is always present. */
2479 if (!mmc_card_is_removable(mmc))
2480 return 1;
2481
2482 /*
2483 * Try slot gpio detect, if defined it take precedence
2484 * over build in controller functionality
2485 */
2486 if (gpio_cd >= 0)
2487 return !!gpio_cd;
2488
2489 /* If polling, assume that the card is always present. */
2490 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2491 return 1;
2492
2493 /* Host native card detect */
2494 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2495}
2496
2497int sdhci_get_cd_nogpio(struct mmc_host *mmc)
2498{
2499 struct sdhci_host *host = mmc_priv(mmc);
2500 unsigned long flags;
2501 int ret = 0;
2502
2503 spin_lock_irqsave(&host->lock, flags);
2504
2505 if (host->flags & SDHCI_DEVICE_DEAD)
2506 goto out;
2507
2508 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2509out:
2510 spin_unlock_irqrestore(&host->lock, flags);
2511
2512 return ret;
2513}
2514EXPORT_SYMBOL_GPL(sdhci_get_cd_nogpio);
2515
2516static int sdhci_check_ro(struct sdhci_host *host)
2517{
2518 unsigned long flags;
2519 int is_readonly;
2520
2521 spin_lock_irqsave(&host->lock, flags);
2522
2523 if (host->flags & SDHCI_DEVICE_DEAD)
2524 is_readonly = 0;
2525 else if (host->ops->get_ro)
2526 is_readonly = host->ops->get_ro(host);
2527 else if (mmc_can_gpio_ro(host->mmc))
2528 is_readonly = mmc_gpio_get_ro(host->mmc);
2529 else
2530 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2531 & SDHCI_WRITE_PROTECT);
2532
2533 spin_unlock_irqrestore(&host->lock, flags);
2534
2535 /* This quirk needs to be replaced by a callback-function later */
2536 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
2537 !is_readonly : is_readonly;
2538}
2539
2540#define SAMPLE_COUNT 5
2541
2542static int sdhci_get_ro(struct mmc_host *mmc)
2543{
2544 struct sdhci_host *host = mmc_priv(mmc);
2545 int i, ro_count;
2546
2547 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
2548 return sdhci_check_ro(host);
2549
2550 ro_count = 0;
2551 for (i = 0; i < SAMPLE_COUNT; i++) {
2552 if (sdhci_check_ro(host)) {
2553 if (++ro_count > SAMPLE_COUNT / 2)
2554 return 1;
2555 }
2556 msleep(30);
2557 }
2558 return 0;
2559}
2560
2561static void sdhci_hw_reset(struct mmc_host *mmc)
2562{
2563 struct sdhci_host *host = mmc_priv(mmc);
2564
2565 if (host->ops && host->ops->hw_reset)
2566 host->ops->hw_reset(host);
2567}
2568
2569static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2570{
2571 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
2572 if (enable)
2573 host->ier |= SDHCI_INT_CARD_INT;
2574 else
2575 host->ier &= ~SDHCI_INT_CARD_INT;
2576
2577 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2578 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2579 }
2580}
2581
2582void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
2583{
2584 struct sdhci_host *host = mmc_priv(mmc);
2585 unsigned long flags;
2586
2587 if (enable)
2588 pm_runtime_get_noresume(mmc_dev(mmc));
2589
2590 spin_lock_irqsave(&host->lock, flags);
2591 sdhci_enable_sdio_irq_nolock(host, enable);
2592 spin_unlock_irqrestore(&host->lock, flags);
2593
2594 if (!enable)
2595 pm_runtime_put_noidle(mmc_dev(mmc));
2596}
2597EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
2598
2599static void sdhci_ack_sdio_irq(struct mmc_host *mmc)
2600{
2601 struct sdhci_host *host = mmc_priv(mmc);
2602 unsigned long flags;
2603
2604 spin_lock_irqsave(&host->lock, flags);
2605 sdhci_enable_sdio_irq_nolock(host, true);
2606 spin_unlock_irqrestore(&host->lock, flags);
2607}
2608
2609int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2610 struct mmc_ios *ios)
2611{
2612 struct sdhci_host *host = mmc_priv(mmc);
2613 u16 ctrl;
2614 int ret;
2615
2616 /*
2617 * Signal Voltage Switching is only applicable for Host Controllers
2618 * v3.00 and above.
2619 */
2620 if (host->version < SDHCI_SPEC_300)
2621 return 0;
2622
2623 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2624
2625 switch (ios->signal_voltage) {
2626 case MMC_SIGNAL_VOLTAGE_330:
2627 if (!(host->flags & SDHCI_SIGNALING_330))
2628 return -EINVAL;
2629 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2630 ctrl &= ~SDHCI_CTRL_VDD_180;
2631 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2632
2633 if (!IS_ERR(mmc->supply.vqmmc)) {
2634 ret = mmc_regulator_set_vqmmc(mmc, ios);
2635 if (ret < 0) {
2636 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
2637 mmc_hostname(mmc));
2638 return -EIO;
2639 }
2640 }
2641 /* Wait for 5ms */
2642 usleep_range(5000, 5500);
2643
2644 /* 3.3V regulator output should be stable within 5 ms */
2645 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2646 if (!(ctrl & SDHCI_CTRL_VDD_180))
2647 return 0;
2648
2649 pr_warn("%s: 3.3V regulator output did not become stable\n",
2650 mmc_hostname(mmc));
2651
2652 return -EAGAIN;
2653 case MMC_SIGNAL_VOLTAGE_180:
2654 if (!(host->flags & SDHCI_SIGNALING_180))
2655 return -EINVAL;
2656 if (!IS_ERR(mmc->supply.vqmmc)) {
2657 ret = mmc_regulator_set_vqmmc(mmc, ios);
2658 if (ret < 0) {
2659 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
2660 mmc_hostname(mmc));
2661 return -EIO;
2662 }
2663 }
2664
2665 /*
2666 * Enable 1.8V Signal Enable in the Host Control2
2667 * register
2668 */
2669 ctrl |= SDHCI_CTRL_VDD_180;
2670 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2671
2672 /* Some controller need to do more when switching */
2673 if (host->ops->voltage_switch)
2674 host->ops->voltage_switch(host);
2675
2676 /* 1.8V regulator output should be stable within 5 ms */
2677 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2678 if (ctrl & SDHCI_CTRL_VDD_180)
2679 return 0;
2680
2681 pr_warn("%s: 1.8V regulator output did not become stable\n",
2682 mmc_hostname(mmc));
2683
2684 return -EAGAIN;
2685 case MMC_SIGNAL_VOLTAGE_120:
2686 if (!(host->flags & SDHCI_SIGNALING_120))
2687 return -EINVAL;
2688 if (!IS_ERR(mmc->supply.vqmmc)) {
2689 ret = mmc_regulator_set_vqmmc(mmc, ios);
2690 if (ret < 0) {
2691 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
2692 mmc_hostname(mmc));
2693 return -EIO;
2694 }
2695 }
2696 return 0;
2697 default:
2698 /* No signal voltage switch required */
2699 return 0;
2700 }
2701}
2702EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2703
2704static int sdhci_card_busy(struct mmc_host *mmc)
2705{
2706 struct sdhci_host *host = mmc_priv(mmc);
2707 u32 present_state;
2708
2709 /* Check whether DAT[0] is 0 */
2710 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2711
2712 return !(present_state & SDHCI_DATA_0_LVL_MASK);
2713}
2714
2715static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2716{
2717 struct sdhci_host *host = mmc_priv(mmc);
2718 unsigned long flags;
2719
2720 spin_lock_irqsave(&host->lock, flags);
2721 host->flags |= SDHCI_HS400_TUNING;
2722 spin_unlock_irqrestore(&host->lock, flags);
2723
2724 return 0;
2725}
2726
2727void sdhci_start_tuning(struct sdhci_host *host)
2728{
2729 u16 ctrl;
2730
2731 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2732 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2733 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2734 ctrl |= SDHCI_CTRL_TUNED_CLK;
2735 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2736
2737 /*
2738 * As per the Host Controller spec v3.00, tuning command
2739 * generates Buffer Read Ready interrupt, so enable that.
2740 *
2741 * Note: The spec clearly says that when tuning sequence
2742 * is being performed, the controller does not generate
2743 * interrupts other than Buffer Read Ready interrupt. But
2744 * to make sure we don't hit a controller bug, we _only_
2745 * enable Buffer Read Ready interrupt here.
2746 */
2747 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2748 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2749}
2750EXPORT_SYMBOL_GPL(sdhci_start_tuning);
2751
2752void sdhci_end_tuning(struct sdhci_host *host)
2753{
2754 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2755 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2756}
2757EXPORT_SYMBOL_GPL(sdhci_end_tuning);
2758
2759void sdhci_reset_tuning(struct sdhci_host *host)
2760{
2761 u16 ctrl;
2762
2763 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2764 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2765 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2766 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2767}
2768EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
2769
2770void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2771{
2772 sdhci_reset_tuning(host);
2773
2774 sdhci_reset_for(host, TUNING_ABORT);
2775
2776 sdhci_end_tuning(host);
2777
2778 mmc_send_abort_tuning(host->mmc, opcode);
2779}
2780EXPORT_SYMBOL_GPL(sdhci_abort_tuning);
2781
2782/*
2783 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2784 * tuning command does not have a data payload (or rather the hardware does it
2785 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2786 * interrupt setup is different to other commands and there is no timeout
2787 * interrupt so special handling is needed.
2788 */
2789void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2790{
2791 struct mmc_host *mmc = host->mmc;
2792 struct mmc_command cmd = {};
2793 struct mmc_request mrq = {};
2794 unsigned long flags;
2795 u32 b = host->sdma_boundary;
2796
2797 spin_lock_irqsave(&host->lock, flags);
2798
2799 cmd.opcode = opcode;
2800 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2801 cmd.mrq = &mrq;
2802
2803 mrq.cmd = &cmd;
2804 /*
2805 * In response to CMD19, the card sends 64 bytes of tuning
2806 * block to the Host Controller. So we set the block size
2807 * to 64 here.
2808 */
2809 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2810 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2811 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2812 else
2813 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2814
2815 /*
2816 * The tuning block is sent by the card to the host controller.
2817 * So we set the TRNS_READ bit in the Transfer Mode register.
2818 * This also takes care of setting DMA Enable and Multi Block
2819 * Select in the same register to 0.
2820 */
2821 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2822
2823 if (!sdhci_send_command_retry(host, &cmd, flags)) {
2824 spin_unlock_irqrestore(&host->lock, flags);
2825 host->tuning_done = 0;
2826 return;
2827 }
2828
2829 host->cmd = NULL;
2830
2831 sdhci_del_timer(host, &mrq);
2832
2833 host->tuning_done = 0;
2834
2835 spin_unlock_irqrestore(&host->lock, flags);
2836
2837 /* Wait for Buffer Read Ready interrupt */
2838 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2839 msecs_to_jiffies(50));
2840
2841}
2842EXPORT_SYMBOL_GPL(sdhci_send_tuning);
2843
2844static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2845{
2846 int i;
2847
2848 /*
2849 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2850 * of loops reaches tuning loop count.
2851 */
2852 for (i = 0; i < host->tuning_loop_count; i++) {
2853 u16 ctrl;
2854
2855 sdhci_send_tuning(host, opcode);
2856
2857 if (!host->tuning_done) {
2858 pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
2859 mmc_hostname(host->mmc));
2860 sdhci_abort_tuning(host, opcode);
2861 return -ETIMEDOUT;
2862 }
2863
2864 /* Spec does not require a delay between tuning cycles */
2865 if (host->tuning_delay > 0)
2866 mdelay(host->tuning_delay);
2867
2868 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2869 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2870 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2871 return 0; /* Success! */
2872 break;
2873 }
2874
2875 }
2876
2877 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2878 mmc_hostname(host->mmc));
2879 sdhci_reset_tuning(host);
2880 return -EAGAIN;
2881}
2882
2883int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2884{
2885 struct sdhci_host *host = mmc_priv(mmc);
2886 int err = 0;
2887 unsigned int tuning_count = 0;
2888 bool hs400_tuning;
2889
2890 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2891
2892 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2893 tuning_count = host->tuning_count;
2894
2895 /*
2896 * The Host Controller needs tuning in case of SDR104 and DDR50
2897 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2898 * the Capabilities register.
2899 * If the Host Controller supports the HS200 mode then the
2900 * tuning function has to be executed.
2901 */
2902 switch (host->timing) {
2903 /* HS400 tuning is done in HS200 mode */
2904 case MMC_TIMING_MMC_HS400:
2905 err = -EINVAL;
2906 goto out;
2907
2908 case MMC_TIMING_MMC_HS200:
2909 /*
2910 * Periodic re-tuning for HS400 is not expected to be needed, so
2911 * disable it here.
2912 */
2913 if (hs400_tuning)
2914 tuning_count = 0;
2915 break;
2916
2917 case MMC_TIMING_UHS_SDR104:
2918 case MMC_TIMING_UHS_DDR50:
2919 break;
2920
2921 case MMC_TIMING_UHS_SDR50:
2922 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2923 break;
2924 fallthrough;
2925
2926 default:
2927 goto out;
2928 }
2929
2930 if (host->ops->platform_execute_tuning) {
2931 err = host->ops->platform_execute_tuning(host, opcode);
2932 goto out;
2933 }
2934
2935 mmc->retune_period = tuning_count;
2936
2937 if (host->tuning_delay < 0)
2938 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2939
2940 sdhci_start_tuning(host);
2941
2942 host->tuning_err = __sdhci_execute_tuning(host, opcode);
2943
2944 sdhci_end_tuning(host);
2945out:
2946 host->flags &= ~SDHCI_HS400_TUNING;
2947
2948 return err;
2949}
2950EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2951
2952static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2953{
2954 /* Host Controller v3.00 defines preset value registers */
2955 if (host->version < SDHCI_SPEC_300)
2956 return;
2957
2958 /*
2959 * We only enable or disable Preset Value if they are not already
2960 * enabled or disabled respectively. Otherwise, we bail out.
2961 */
2962 if (host->preset_enabled != enable) {
2963 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2964
2965 if (enable)
2966 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2967 else
2968 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2969
2970 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2971
2972 if (enable)
2973 host->flags |= SDHCI_PV_ENABLED;
2974 else
2975 host->flags &= ~SDHCI_PV_ENABLED;
2976
2977 host->preset_enabled = enable;
2978 }
2979}
2980
2981static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2982 int err)
2983{
2984 struct mmc_data *data = mrq->data;
2985
2986 if (data->host_cookie != COOKIE_UNMAPPED)
2987 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
2988 mmc_get_dma_dir(data));
2989
2990 data->host_cookie = COOKIE_UNMAPPED;
2991}
2992
2993static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2994{
2995 struct sdhci_host *host = mmc_priv(mmc);
2996
2997 mrq->data->host_cookie = COOKIE_UNMAPPED;
2998
2999 /*
3000 * No pre-mapping in the pre hook if we're using the bounce buffer,
3001 * for that we would need two bounce buffers since one buffer is
3002 * in flight when this is getting called.
3003 */
3004 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
3005 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
3006}
3007
3008static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
3009{
3010 if (host->data_cmd) {
3011 host->data_cmd->error = err;
3012 sdhci_finish_mrq(host, host->data_cmd->mrq);
3013 }
3014
3015 if (host->cmd) {
3016 host->cmd->error = err;
3017 sdhci_finish_mrq(host, host->cmd->mrq);
3018 }
3019}
3020
3021static void sdhci_card_event(struct mmc_host *mmc)
3022{
3023 struct sdhci_host *host = mmc_priv(mmc);
3024 unsigned long flags;
3025 int present;
3026
3027 /* First check if client has provided their own card event */
3028 if (host->ops->card_event)
3029 host->ops->card_event(host);
3030
3031 present = mmc->ops->get_cd(mmc);
3032
3033 spin_lock_irqsave(&host->lock, flags);
3034
3035 /* Check sdhci_has_requests() first in case we are runtime suspended */
3036 if (sdhci_has_requests(host) && !present) {
3037 pr_err("%s: Card removed during transfer!\n",
3038 mmc_hostname(mmc));
3039 pr_err("%s: Resetting controller.\n",
3040 mmc_hostname(mmc));
3041
3042 sdhci_reset_for(host, CARD_REMOVED);
3043
3044 sdhci_error_out_mrqs(host, -ENOMEDIUM);
3045 }
3046
3047 spin_unlock_irqrestore(&host->lock, flags);
3048}
3049
3050static const struct mmc_host_ops sdhci_ops = {
3051 .request = sdhci_request,
3052 .post_req = sdhci_post_req,
3053 .pre_req = sdhci_pre_req,
3054 .set_ios = sdhci_set_ios,
3055 .get_cd = sdhci_get_cd,
3056 .get_ro = sdhci_get_ro,
3057 .card_hw_reset = sdhci_hw_reset,
3058 .enable_sdio_irq = sdhci_enable_sdio_irq,
3059 .ack_sdio_irq = sdhci_ack_sdio_irq,
3060 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
3061 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
3062 .execute_tuning = sdhci_execute_tuning,
3063 .card_event = sdhci_card_event,
3064 .card_busy = sdhci_card_busy,
3065};
3066
3067/*****************************************************************************\
3068 * *
3069 * Request done *
3070 * *
3071\*****************************************************************************/
3072
3073static bool sdhci_request_done(struct sdhci_host *host)
3074{
3075 unsigned long flags;
3076 struct mmc_request *mrq;
3077 int i;
3078
3079 spin_lock_irqsave(&host->lock, flags);
3080
3081 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3082 mrq = host->mrqs_done[i];
3083 if (mrq)
3084 break;
3085 }
3086
3087 if (!mrq) {
3088 spin_unlock_irqrestore(&host->lock, flags);
3089 return true;
3090 }
3091
3092 /*
3093 * The controller needs a reset of internal state machines
3094 * upon error conditions.
3095 */
3096 if (sdhci_needs_reset(host, mrq)) {
3097 /*
3098 * Do not finish until command and data lines are available for
3099 * reset. Note there can only be one other mrq, so it cannot
3100 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
3101 * would both be null.
3102 */
3103 if (host->cmd || host->data_cmd) {
3104 spin_unlock_irqrestore(&host->lock, flags);
3105 return true;
3106 }
3107
3108 /* Some controllers need this kick or reset won't work here */
3109 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
3110 /* This is to force an update */
3111 host->ops->set_clock(host, host->clock);
3112
3113 sdhci_reset_for(host, REQUEST_ERROR);
3114
3115 host->pending_reset = false;
3116 }
3117
3118 /*
3119 * Always unmap the data buffers if they were mapped by
3120 * sdhci_prepare_data() whenever we finish with a request.
3121 * This avoids leaking DMA mappings on error.
3122 */
3123 if (host->flags & SDHCI_REQ_USE_DMA) {
3124 struct mmc_data *data = mrq->data;
3125
3126 if (host->use_external_dma && data &&
3127 (mrq->cmd->error || data->error)) {
3128 struct dma_chan *chan = sdhci_external_dma_channel(host, data);
3129
3130 host->mrqs_done[i] = NULL;
3131 spin_unlock_irqrestore(&host->lock, flags);
3132 dmaengine_terminate_sync(chan);
3133 spin_lock_irqsave(&host->lock, flags);
3134 sdhci_set_mrq_done(host, mrq);
3135 }
3136
3137 if (data && data->host_cookie == COOKIE_MAPPED) {
3138 if (host->bounce_buffer) {
3139 /*
3140 * On reads, copy the bounced data into the
3141 * sglist
3142 */
3143 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
3144 unsigned int length = data->bytes_xfered;
3145
3146 if (length > host->bounce_buffer_size) {
3147 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
3148 mmc_hostname(host->mmc),
3149 host->bounce_buffer_size,
3150 data->bytes_xfered);
3151 /* Cap it down and continue */
3152 length = host->bounce_buffer_size;
3153 }
3154 dma_sync_single_for_cpu(
3155 mmc_dev(host->mmc),
3156 host->bounce_addr,
3157 host->bounce_buffer_size,
3158 DMA_FROM_DEVICE);
3159 sg_copy_from_buffer(data->sg,
3160 data->sg_len,
3161 host->bounce_buffer,
3162 length);
3163 } else {
3164 /* No copying, just switch ownership */
3165 dma_sync_single_for_cpu(
3166 mmc_dev(host->mmc),
3167 host->bounce_addr,
3168 host->bounce_buffer_size,
3169 mmc_get_dma_dir(data));
3170 }
3171 } else {
3172 /* Unmap the raw data */
3173 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
3174 data->sg_len,
3175 mmc_get_dma_dir(data));
3176 }
3177 data->host_cookie = COOKIE_UNMAPPED;
3178 }
3179 }
3180
3181 host->mrqs_done[i] = NULL;
3182
3183 spin_unlock_irqrestore(&host->lock, flags);
3184
3185 if (host->ops->request_done)
3186 host->ops->request_done(host, mrq);
3187 else
3188 mmc_request_done(host->mmc, mrq);
3189
3190 return false;
3191}
3192
3193static void sdhci_complete_work(struct work_struct *work)
3194{
3195 struct sdhci_host *host = container_of(work, struct sdhci_host,
3196 complete_work);
3197
3198 while (!sdhci_request_done(host))
3199 ;
3200}
3201
3202static void sdhci_timeout_timer(struct timer_list *t)
3203{
3204 struct sdhci_host *host;
3205 unsigned long flags;
3206
3207 host = from_timer(host, t, timer);
3208
3209 spin_lock_irqsave(&host->lock, flags);
3210
3211 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
3212 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
3213 mmc_hostname(host->mmc));
3214 sdhci_err_stats_inc(host, REQ_TIMEOUT);
3215 sdhci_dumpregs(host);
3216
3217 host->cmd->error = -ETIMEDOUT;
3218 sdhci_finish_mrq(host, host->cmd->mrq);
3219 }
3220
3221 spin_unlock_irqrestore(&host->lock, flags);
3222}
3223
3224static void sdhci_timeout_data_timer(struct timer_list *t)
3225{
3226 struct sdhci_host *host;
3227 unsigned long flags;
3228
3229 host = from_timer(host, t, data_timer);
3230
3231 spin_lock_irqsave(&host->lock, flags);
3232
3233 if (host->data || host->data_cmd ||
3234 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
3235 pr_err("%s: Timeout waiting for hardware interrupt.\n",
3236 mmc_hostname(host->mmc));
3237 sdhci_err_stats_inc(host, REQ_TIMEOUT);
3238 sdhci_dumpregs(host);
3239
3240 if (host->data) {
3241 host->data->error = -ETIMEDOUT;
3242 __sdhci_finish_data(host, true);
3243 queue_work(host->complete_wq, &host->complete_work);
3244 } else if (host->data_cmd) {
3245 host->data_cmd->error = -ETIMEDOUT;
3246 sdhci_finish_mrq(host, host->data_cmd->mrq);
3247 } else {
3248 host->cmd->error = -ETIMEDOUT;
3249 sdhci_finish_mrq(host, host->cmd->mrq);
3250 }
3251 }
3252
3253 spin_unlock_irqrestore(&host->lock, flags);
3254}
3255
3256/*****************************************************************************\
3257 * *
3258 * Interrupt handling *
3259 * *
3260\*****************************************************************************/
3261
3262static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
3263{
3264 /* Handle auto-CMD12 error */
3265 if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
3266 struct mmc_request *mrq = host->data_cmd->mrq;
3267 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3268 int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3269 SDHCI_INT_DATA_TIMEOUT :
3270 SDHCI_INT_DATA_CRC;
3271
3272 /* Treat auto-CMD12 error the same as data error */
3273 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
3274 *intmask_p |= data_err_bit;
3275 return;
3276 }
3277 }
3278
3279 if (!host->cmd) {
3280 /*
3281 * SDHCI recovers from errors by resetting the cmd and data
3282 * circuits. Until that is done, there very well might be more
3283 * interrupts, so ignore them in that case.
3284 */
3285 if (host->pending_reset)
3286 return;
3287 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
3288 mmc_hostname(host->mmc), (unsigned)intmask);
3289 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
3290 sdhci_dumpregs(host);
3291 return;
3292 }
3293
3294 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
3295 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
3296 if (intmask & SDHCI_INT_TIMEOUT) {
3297 host->cmd->error = -ETIMEDOUT;
3298 sdhci_err_stats_inc(host, CMD_TIMEOUT);
3299 } else {
3300 host->cmd->error = -EILSEQ;
3301 if (!mmc_op_tuning(host->cmd->opcode))
3302 sdhci_err_stats_inc(host, CMD_CRC);
3303 }
3304 /* Treat data command CRC error the same as data CRC error */
3305 if (host->cmd->data &&
3306 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
3307 SDHCI_INT_CRC) {
3308 host->cmd = NULL;
3309 *intmask_p |= SDHCI_INT_DATA_CRC;
3310 return;
3311 }
3312
3313 __sdhci_finish_mrq(host, host->cmd->mrq);
3314 return;
3315 }
3316
3317 /* Handle auto-CMD23 error */
3318 if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
3319 struct mmc_request *mrq = host->cmd->mrq;
3320 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3321 int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3322 -ETIMEDOUT :
3323 -EILSEQ;
3324
3325 sdhci_err_stats_inc(host, AUTO_CMD);
3326
3327 if (sdhci_auto_cmd23(host, mrq)) {
3328 mrq->sbc->error = err;
3329 __sdhci_finish_mrq(host, mrq);
3330 return;
3331 }
3332 }
3333
3334 if (intmask & SDHCI_INT_RESPONSE)
3335 sdhci_finish_command(host);
3336}
3337
3338static void sdhci_adma_show_error(struct sdhci_host *host)
3339{
3340 void *desc = host->adma_table;
3341 dma_addr_t dma = host->adma_addr;
3342
3343 sdhci_dumpregs(host);
3344
3345 while (true) {
3346 struct sdhci_adma2_64_desc *dma_desc = desc;
3347
3348 if (host->flags & SDHCI_USE_64_BIT_DMA)
3349 SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
3350 (unsigned long long)dma,
3351 le32_to_cpu(dma_desc->addr_hi),
3352 le32_to_cpu(dma_desc->addr_lo),
3353 le16_to_cpu(dma_desc->len),
3354 le16_to_cpu(dma_desc->cmd));
3355 else
3356 SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
3357 (unsigned long long)dma,
3358 le32_to_cpu(dma_desc->addr_lo),
3359 le16_to_cpu(dma_desc->len),
3360 le16_to_cpu(dma_desc->cmd));
3361
3362 desc += host->desc_sz;
3363 dma += host->desc_sz;
3364
3365 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
3366 break;
3367 }
3368}
3369
3370static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
3371{
3372 /*
3373 * CMD19 generates _only_ Buffer Read Ready interrupt if
3374 * use sdhci_send_tuning.
3375 * Need to exclude this case: PIO mode and use mmc_send_tuning,
3376 * If not, sdhci_transfer_pio will never be called, make the
3377 * SDHCI_INT_DATA_AVAIL always there, stuck in irq storm.
3378 */
3379 if (intmask & SDHCI_INT_DATA_AVAIL && !host->data) {
3380 if (mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)))) {
3381 host->tuning_done = 1;
3382 wake_up(&host->buf_ready_int);
3383 return;
3384 }
3385 }
3386
3387 if (!host->data) {
3388 struct mmc_command *data_cmd = host->data_cmd;
3389
3390 /*
3391 * The "data complete" interrupt is also used to
3392 * indicate that a busy state has ended. See comment
3393 * above in sdhci_cmd_irq().
3394 */
3395 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
3396 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
3397 host->data_cmd = NULL;
3398 data_cmd->error = -ETIMEDOUT;
3399 sdhci_err_stats_inc(host, CMD_TIMEOUT);
3400 __sdhci_finish_mrq(host, data_cmd->mrq);
3401 return;
3402 }
3403 if (intmask & SDHCI_INT_DATA_END) {
3404 host->data_cmd = NULL;
3405 /*
3406 * Some cards handle busy-end interrupt
3407 * before the command completed, so make
3408 * sure we do things in the proper order.
3409 */
3410 if (host->cmd == data_cmd)
3411 return;
3412
3413 __sdhci_finish_mrq(host, data_cmd->mrq);
3414 return;
3415 }
3416 }
3417
3418 /*
3419 * SDHCI recovers from errors by resetting the cmd and data
3420 * circuits. Until that is done, there very well might be more
3421 * interrupts, so ignore them in that case.
3422 */
3423 if (host->pending_reset)
3424 return;
3425
3426 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
3427 mmc_hostname(host->mmc), (unsigned)intmask);
3428 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
3429 sdhci_dumpregs(host);
3430
3431 return;
3432 }
3433
3434 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
3435 host->data->error = -ETIMEDOUT;
3436 sdhci_err_stats_inc(host, DAT_TIMEOUT);
3437 } else if (intmask & SDHCI_INT_DATA_END_BIT) {
3438 host->data->error = -EILSEQ;
3439 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
3440 sdhci_err_stats_inc(host, DAT_CRC);
3441 } else if ((intmask & SDHCI_INT_DATA_CRC) &&
3442 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
3443 != MMC_BUS_TEST_R) {
3444 host->data->error = -EILSEQ;
3445 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
3446 sdhci_err_stats_inc(host, DAT_CRC);
3447 } else if (intmask & SDHCI_INT_ADMA_ERROR) {
3448 pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
3449 intmask);
3450 sdhci_adma_show_error(host);
3451 sdhci_err_stats_inc(host, ADMA);
3452 host->data->error = -EIO;
3453 if (host->ops->adma_workaround)
3454 host->ops->adma_workaround(host, intmask);
3455 }
3456
3457 if (host->data->error)
3458 sdhci_finish_data(host);
3459 else {
3460 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
3461 sdhci_transfer_pio(host);
3462
3463 /*
3464 * We currently don't do anything fancy with DMA
3465 * boundaries, but as we can't disable the feature
3466 * we need to at least restart the transfer.
3467 *
3468 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
3469 * should return a valid address to continue from, but as
3470 * some controllers are faulty, don't trust them.
3471 */
3472 if (intmask & SDHCI_INT_DMA_END) {
3473 dma_addr_t dmastart, dmanow;
3474
3475 dmastart = sdhci_sdma_address(host);
3476 dmanow = dmastart + host->data->bytes_xfered;
3477 /*
3478 * Force update to the next DMA block boundary.
3479 */
3480 dmanow = (dmanow &
3481 ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
3482 SDHCI_DEFAULT_BOUNDARY_SIZE;
3483 host->data->bytes_xfered = dmanow - dmastart;
3484 DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
3485 &dmastart, host->data->bytes_xfered, &dmanow);
3486 sdhci_set_sdma_addr(host, dmanow);
3487 }
3488
3489 if (intmask & SDHCI_INT_DATA_END) {
3490 if (host->cmd == host->data_cmd) {
3491 /*
3492 * Data managed to finish before the
3493 * command completed. Make sure we do
3494 * things in the proper order.
3495 */
3496 host->data_early = 1;
3497 } else {
3498 sdhci_finish_data(host);
3499 }
3500 }
3501 }
3502}
3503
3504static inline bool sdhci_defer_done(struct sdhci_host *host,
3505 struct mmc_request *mrq)
3506{
3507 struct mmc_data *data = mrq->data;
3508
3509 return host->pending_reset || host->always_defer_done ||
3510 ((host->flags & SDHCI_REQ_USE_DMA) && data &&
3511 data->host_cookie == COOKIE_MAPPED);
3512}
3513
3514static irqreturn_t sdhci_irq(int irq, void *dev_id)
3515{
3516 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0};
3517 irqreturn_t result = IRQ_NONE;
3518 struct sdhci_host *host = dev_id;
3519 u32 intmask, mask, unexpected = 0;
3520 int max_loops = 16;
3521 int i;
3522
3523 spin_lock(&host->lock);
3524
3525 if (host->runtime_suspended) {
3526 spin_unlock(&host->lock);
3527 return IRQ_NONE;
3528 }
3529
3530 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3531 if (!intmask || intmask == 0xffffffff) {
3532 result = IRQ_NONE;
3533 goto out;
3534 }
3535
3536 do {
3537 DBG("IRQ status 0x%08x\n", intmask);
3538
3539 if (host->ops->irq) {
3540 intmask = host->ops->irq(host, intmask);
3541 if (!intmask)
3542 goto cont;
3543 }
3544
3545 /* Clear selected interrupts. */
3546 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3547 SDHCI_INT_BUS_POWER);
3548 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3549
3550 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3551 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3552 SDHCI_CARD_PRESENT;
3553
3554 /*
3555 * There is a observation on i.mx esdhc. INSERT
3556 * bit will be immediately set again when it gets
3557 * cleared, if a card is inserted. We have to mask
3558 * the irq to prevent interrupt storm which will
3559 * freeze the system. And the REMOVE gets the
3560 * same situation.
3561 *
3562 * More testing are needed here to ensure it works
3563 * for other platforms though.
3564 */
3565 host->ier &= ~(SDHCI_INT_CARD_INSERT |
3566 SDHCI_INT_CARD_REMOVE);
3567 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
3568 SDHCI_INT_CARD_INSERT;
3569 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3570 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3571
3572 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
3573 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3574
3575 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
3576 SDHCI_INT_CARD_REMOVE);
3577 result = IRQ_WAKE_THREAD;
3578 }
3579
3580 if (intmask & SDHCI_INT_CMD_MASK)
3581 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
3582
3583 if (intmask & SDHCI_INT_DATA_MASK)
3584 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
3585
3586 if (intmask & SDHCI_INT_BUS_POWER)
3587 pr_err("%s: Card is consuming too much power!\n",
3588 mmc_hostname(host->mmc));
3589
3590 if (intmask & SDHCI_INT_RETUNE)
3591 mmc_retune_needed(host->mmc);
3592
3593 if ((intmask & SDHCI_INT_CARD_INT) &&
3594 (host->ier & SDHCI_INT_CARD_INT)) {
3595 sdhci_enable_sdio_irq_nolock(host, false);
3596 sdio_signal_irq(host->mmc);
3597 }
3598
3599 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
3600 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3601 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
3602 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
3603
3604 if (intmask) {
3605 unexpected |= intmask;
3606 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3607 }
3608cont:
3609 if (result == IRQ_NONE)
3610 result = IRQ_HANDLED;
3611
3612 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3613 } while (intmask && --max_loops);
3614
3615 /* Determine if mrqs can be completed immediately */
3616 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3617 struct mmc_request *mrq = host->mrqs_done[i];
3618
3619 if (!mrq)
3620 continue;
3621
3622 if (sdhci_defer_done(host, mrq)) {
3623 result = IRQ_WAKE_THREAD;
3624 } else {
3625 mrqs_done[i] = mrq;
3626 host->mrqs_done[i] = NULL;
3627 }
3628 }
3629out:
3630 if (host->deferred_cmd)
3631 result = IRQ_WAKE_THREAD;
3632
3633 spin_unlock(&host->lock);
3634
3635 /* Process mrqs ready for immediate completion */
3636 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3637 if (!mrqs_done[i])
3638 continue;
3639
3640 if (host->ops->request_done)
3641 host->ops->request_done(host, mrqs_done[i]);
3642 else
3643 mmc_request_done(host->mmc, mrqs_done[i]);
3644 }
3645
3646 if (unexpected) {
3647 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3648 mmc_hostname(host->mmc), unexpected);
3649 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
3650 sdhci_dumpregs(host);
3651 }
3652
3653 return result;
3654}
3655
3656static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
3657{
3658 struct sdhci_host *host = dev_id;
3659 struct mmc_command *cmd;
3660 unsigned long flags;
3661 u32 isr;
3662
3663 while (!sdhci_request_done(host))
3664 ;
3665
3666 spin_lock_irqsave(&host->lock, flags);
3667
3668 isr = host->thread_isr;
3669 host->thread_isr = 0;
3670
3671 cmd = host->deferred_cmd;
3672 if (cmd && !sdhci_send_command_retry(host, cmd, flags))
3673 sdhci_finish_mrq(host, cmd->mrq);
3674
3675 spin_unlock_irqrestore(&host->lock, flags);
3676
3677 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3678 struct mmc_host *mmc = host->mmc;
3679
3680 mmc->ops->card_event(mmc);
3681 mmc_detect_change(mmc, msecs_to_jiffies(200));
3682 }
3683
3684 return IRQ_HANDLED;
3685}
3686
3687/*****************************************************************************\
3688 * *
3689 * Suspend/resume *
3690 * *
3691\*****************************************************************************/
3692
3693#ifdef CONFIG_PM
3694
3695static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
3696{
3697 return mmc_card_is_removable(host->mmc) &&
3698 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3699 !mmc_can_gpio_cd(host->mmc);
3700}
3701
3702/*
3703 * To enable wakeup events, the corresponding events have to be enabled in
3704 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
3705 * Table' in the SD Host Controller Standard Specification.
3706 * It is useless to restore SDHCI_INT_ENABLE state in
3707 * sdhci_disable_irq_wakeups() since it will be set by
3708 * sdhci_enable_card_detection() or sdhci_init().
3709 */
3710static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
3711{
3712 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
3713 SDHCI_WAKE_ON_INT;
3714 u32 irq_val = 0;
3715 u8 wake_val = 0;
3716 u8 val;
3717
3718 if (sdhci_cd_irq_can_wakeup(host)) {
3719 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
3720 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
3721 }
3722
3723 if (mmc_card_wake_sdio_irq(host->mmc)) {
3724 wake_val |= SDHCI_WAKE_ON_INT;
3725 irq_val |= SDHCI_INT_CARD_INT;
3726 }
3727
3728 if (!irq_val)
3729 return false;
3730
3731 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3732 val &= ~mask;
3733 val |= wake_val;
3734 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3735
3736 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
3737
3738 host->irq_wake_enabled = !enable_irq_wake(host->irq);
3739
3740 return host->irq_wake_enabled;
3741}
3742
3743static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3744{
3745 u8 val;
3746 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3747 | SDHCI_WAKE_ON_INT;
3748
3749 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3750 val &= ~mask;
3751 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3752
3753 disable_irq_wake(host->irq);
3754
3755 host->irq_wake_enabled = false;
3756}
3757
3758int sdhci_suspend_host(struct sdhci_host *host)
3759{
3760 sdhci_disable_card_detection(host);
3761
3762 mmc_retune_timer_stop(host->mmc);
3763
3764 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
3765 !sdhci_enable_irq_wakeups(host)) {
3766 host->ier = 0;
3767 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3768 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3769 free_irq(host->irq, host);
3770 }
3771
3772 return 0;
3773}
3774
3775EXPORT_SYMBOL_GPL(sdhci_suspend_host);
3776
3777int sdhci_resume_host(struct sdhci_host *host)
3778{
3779 struct mmc_host *mmc = host->mmc;
3780 int ret = 0;
3781
3782 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3783 if (host->ops->enable_dma)
3784 host->ops->enable_dma(host);
3785 }
3786
3787 if ((mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3788 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3789 /* Card keeps power but host controller does not */
3790 sdhci_init(host, 0);
3791 host->pwr = 0;
3792 host->clock = 0;
3793 host->reinit_uhs = true;
3794 mmc->ops->set_ios(mmc, &mmc->ios);
3795 } else {
3796 sdhci_init(host, (mmc->pm_flags & MMC_PM_KEEP_POWER));
3797 }
3798
3799 if (host->irq_wake_enabled) {
3800 sdhci_disable_irq_wakeups(host);
3801 } else {
3802 ret = request_threaded_irq(host->irq, sdhci_irq,
3803 sdhci_thread_irq, IRQF_SHARED,
3804 mmc_hostname(mmc), host);
3805 if (ret)
3806 return ret;
3807 }
3808
3809 sdhci_enable_card_detection(host);
3810
3811 return ret;
3812}
3813
3814EXPORT_SYMBOL_GPL(sdhci_resume_host);
3815
3816int sdhci_runtime_suspend_host(struct sdhci_host *host)
3817{
3818 unsigned long flags;
3819
3820 mmc_retune_timer_stop(host->mmc);
3821
3822 spin_lock_irqsave(&host->lock, flags);
3823 host->ier &= SDHCI_INT_CARD_INT;
3824 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3825 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3826 spin_unlock_irqrestore(&host->lock, flags);
3827
3828 synchronize_hardirq(host->irq);
3829
3830 spin_lock_irqsave(&host->lock, flags);
3831 host->runtime_suspended = true;
3832 spin_unlock_irqrestore(&host->lock, flags);
3833
3834 return 0;
3835}
3836EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3837
3838int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
3839{
3840 struct mmc_host *mmc = host->mmc;
3841 unsigned long flags;
3842 int host_flags = host->flags;
3843
3844 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3845 if (host->ops->enable_dma)
3846 host->ops->enable_dma(host);
3847 }
3848
3849 sdhci_init(host, soft_reset);
3850
3851 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3852 mmc->ios.power_mode != MMC_POWER_OFF) {
3853 /* Force clock and power re-program */
3854 host->pwr = 0;
3855 host->clock = 0;
3856 host->reinit_uhs = true;
3857 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3858 mmc->ops->set_ios(mmc, &mmc->ios);
3859
3860 if ((host_flags & SDHCI_PV_ENABLED) &&
3861 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3862 spin_lock_irqsave(&host->lock, flags);
3863 sdhci_enable_preset_value(host, true);
3864 spin_unlock_irqrestore(&host->lock, flags);
3865 }
3866
3867 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3868 mmc->ops->hs400_enhanced_strobe)
3869 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3870 }
3871
3872 spin_lock_irqsave(&host->lock, flags);
3873
3874 host->runtime_suspended = false;
3875
3876 /* Enable SDIO IRQ */
3877 if (sdio_irq_claimed(mmc))
3878 sdhci_enable_sdio_irq_nolock(host, true);
3879
3880 /* Enable Card Detection */
3881 sdhci_enable_card_detection(host);
3882
3883 spin_unlock_irqrestore(&host->lock, flags);
3884
3885 return 0;
3886}
3887EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3888
3889#endif /* CONFIG_PM */
3890
3891/*****************************************************************************\
3892 * *
3893 * Command Queue Engine (CQE) helpers *
3894 * *
3895\*****************************************************************************/
3896
3897void sdhci_cqe_enable(struct mmc_host *mmc)
3898{
3899 struct sdhci_host *host = mmc_priv(mmc);
3900 unsigned long flags;
3901 u8 ctrl;
3902
3903 spin_lock_irqsave(&host->lock, flags);
3904
3905 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3906 ctrl &= ~SDHCI_CTRL_DMA_MASK;
3907 /*
3908 * Host from V4.10 supports ADMA3 DMA type.
3909 * ADMA3 performs integrated descriptor which is more suitable
3910 * for cmd queuing to fetch both command and transfer descriptors.
3911 */
3912 if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
3913 ctrl |= SDHCI_CTRL_ADMA3;
3914 else if (host->flags & SDHCI_USE_64_BIT_DMA)
3915 ctrl |= SDHCI_CTRL_ADMA64;
3916 else
3917 ctrl |= SDHCI_CTRL_ADMA32;
3918 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3919
3920 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3921 SDHCI_BLOCK_SIZE);
3922
3923 /* Set maximum timeout */
3924 sdhci_set_timeout(host, NULL);
3925
3926 host->ier = host->cqe_ier;
3927
3928 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3929 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3930
3931 host->cqe_on = true;
3932
3933 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3934 mmc_hostname(mmc), host->ier,
3935 sdhci_readl(host, SDHCI_INT_STATUS));
3936
3937 spin_unlock_irqrestore(&host->lock, flags);
3938}
3939EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3940
3941void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3942{
3943 struct sdhci_host *host = mmc_priv(mmc);
3944 unsigned long flags;
3945
3946 spin_lock_irqsave(&host->lock, flags);
3947
3948 sdhci_set_default_irqs(host);
3949
3950 host->cqe_on = false;
3951
3952 if (recovery)
3953 sdhci_reset_for(host, CQE_RECOVERY);
3954
3955 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3956 mmc_hostname(mmc), host->ier,
3957 sdhci_readl(host, SDHCI_INT_STATUS));
3958
3959 spin_unlock_irqrestore(&host->lock, flags);
3960}
3961EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3962
3963bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3964 int *data_error)
3965{
3966 u32 mask;
3967
3968 if (!host->cqe_on)
3969 return false;
3970
3971 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC)) {
3972 *cmd_error = -EILSEQ;
3973 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
3974 sdhci_err_stats_inc(host, CMD_CRC);
3975 } else if (intmask & SDHCI_INT_TIMEOUT) {
3976 *cmd_error = -ETIMEDOUT;
3977 sdhci_err_stats_inc(host, CMD_TIMEOUT);
3978 } else
3979 *cmd_error = 0;
3980
3981 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC)) {
3982 *data_error = -EILSEQ;
3983 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
3984 sdhci_err_stats_inc(host, DAT_CRC);
3985 } else if (intmask & SDHCI_INT_DATA_TIMEOUT) {
3986 *data_error = -ETIMEDOUT;
3987 sdhci_err_stats_inc(host, DAT_TIMEOUT);
3988 } else if (intmask & SDHCI_INT_ADMA_ERROR) {
3989 *data_error = -EIO;
3990 sdhci_err_stats_inc(host, ADMA);
3991 } else
3992 *data_error = 0;
3993
3994 /* Clear selected interrupts. */
3995 mask = intmask & host->cqe_ier;
3996 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3997
3998 if (intmask & SDHCI_INT_BUS_POWER)
3999 pr_err("%s: Card is consuming too much power!\n",
4000 mmc_hostname(host->mmc));
4001
4002 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
4003 if (intmask) {
4004 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
4005 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
4006 mmc_hostname(host->mmc), intmask);
4007 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
4008 sdhci_dumpregs(host);
4009 }
4010
4011 return true;
4012}
4013EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
4014
4015/*****************************************************************************\
4016 * *
4017 * Device allocation/registration *
4018 * *
4019\*****************************************************************************/
4020
4021struct sdhci_host *sdhci_alloc_host(struct device *dev,
4022 size_t priv_size)
4023{
4024 struct mmc_host *mmc;
4025 struct sdhci_host *host;
4026
4027 WARN_ON(dev == NULL);
4028
4029 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
4030 if (!mmc)
4031 return ERR_PTR(-ENOMEM);
4032
4033 host = mmc_priv(mmc);
4034 host->mmc = mmc;
4035 host->mmc_host_ops = sdhci_ops;
4036 mmc->ops = &host->mmc_host_ops;
4037
4038 host->flags = SDHCI_SIGNALING_330;
4039
4040 host->cqe_ier = SDHCI_CQE_INT_MASK;
4041 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
4042
4043 host->tuning_delay = -1;
4044 host->tuning_loop_count = MAX_TUNING_LOOP;
4045
4046 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
4047
4048 /*
4049 * The DMA table descriptor count is calculated as the maximum
4050 * number of segments times 2, to allow for an alignment
4051 * descriptor for each segment, plus 1 for a nop end descriptor.
4052 */
4053 host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
4054 host->max_adma = 65536;
4055
4056 host->max_timeout_count = 0xE;
4057
4058 return host;
4059}
4060
4061EXPORT_SYMBOL_GPL(sdhci_alloc_host);
4062
4063static int sdhci_set_dma_mask(struct sdhci_host *host)
4064{
4065 struct mmc_host *mmc = host->mmc;
4066 struct device *dev = mmc_dev(mmc);
4067 int ret = -EINVAL;
4068
4069 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
4070 host->flags &= ~SDHCI_USE_64_BIT_DMA;
4071
4072 /* Try 64-bit mask if hardware is capable of it */
4073 if (host->flags & SDHCI_USE_64_BIT_DMA) {
4074 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
4075 if (ret) {
4076 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
4077 mmc_hostname(mmc));
4078 host->flags &= ~SDHCI_USE_64_BIT_DMA;
4079 }
4080 }
4081
4082 /* 32-bit mask as default & fallback */
4083 if (ret) {
4084 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
4085 if (ret)
4086 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
4087 mmc_hostname(mmc));
4088 }
4089
4090 return ret;
4091}
4092
4093void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
4094 const u32 *caps, const u32 *caps1)
4095{
4096 u16 v;
4097 u64 dt_caps_mask = 0;
4098 u64 dt_caps = 0;
4099
4100 if (host->read_caps)
4101 return;
4102
4103 host->read_caps = true;
4104
4105 if (debug_quirks)
4106 host->quirks = debug_quirks;
4107
4108 if (debug_quirks2)
4109 host->quirks2 = debug_quirks2;
4110
4111 sdhci_reset_for_all(host);
4112
4113 if (host->v4_mode)
4114 sdhci_do_enable_v4_mode(host);
4115
4116 device_property_read_u64(mmc_dev(host->mmc),
4117 "sdhci-caps-mask", &dt_caps_mask);
4118 device_property_read_u64(mmc_dev(host->mmc),
4119 "sdhci-caps", &dt_caps);
4120
4121 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
4122 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
4123
4124 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
4125 return;
4126
4127 if (caps) {
4128 host->caps = *caps;
4129 } else {
4130 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
4131 host->caps &= ~lower_32_bits(dt_caps_mask);
4132 host->caps |= lower_32_bits(dt_caps);
4133 }
4134
4135 if (host->version < SDHCI_SPEC_300)
4136 return;
4137
4138 if (caps1) {
4139 host->caps1 = *caps1;
4140 } else {
4141 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
4142 host->caps1 &= ~upper_32_bits(dt_caps_mask);
4143 host->caps1 |= upper_32_bits(dt_caps);
4144 }
4145}
4146EXPORT_SYMBOL_GPL(__sdhci_read_caps);
4147
4148static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
4149{
4150 struct mmc_host *mmc = host->mmc;
4151 unsigned int max_blocks;
4152 unsigned int bounce_size;
4153 int ret;
4154
4155 /*
4156 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
4157 * has diminishing returns, this is probably because SD/MMC
4158 * cards are usually optimized to handle this size of requests.
4159 */
4160 bounce_size = SZ_64K;
4161 /*
4162 * Adjust downwards to maximum request size if this is less
4163 * than our segment size, else hammer down the maximum
4164 * request size to the maximum buffer size.
4165 */
4166 if (mmc->max_req_size < bounce_size)
4167 bounce_size = mmc->max_req_size;
4168 max_blocks = bounce_size / 512;
4169
4170 /*
4171 * When we just support one segment, we can get significant
4172 * speedups by the help of a bounce buffer to group scattered
4173 * reads/writes together.
4174 */
4175 host->bounce_buffer = devm_kmalloc(mmc_dev(mmc),
4176 bounce_size,
4177 GFP_KERNEL);
4178 if (!host->bounce_buffer) {
4179 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
4180 mmc_hostname(mmc),
4181 bounce_size);
4182 /*
4183 * Exiting with zero here makes sure we proceed with
4184 * mmc->max_segs == 1.
4185 */
4186 return;
4187 }
4188
4189 host->bounce_addr = dma_map_single(mmc_dev(mmc),
4190 host->bounce_buffer,
4191 bounce_size,
4192 DMA_BIDIRECTIONAL);
4193 ret = dma_mapping_error(mmc_dev(mmc), host->bounce_addr);
4194 if (ret) {
4195 devm_kfree(mmc_dev(mmc), host->bounce_buffer);
4196 host->bounce_buffer = NULL;
4197 /* Again fall back to max_segs == 1 */
4198 return;
4199 }
4200
4201 host->bounce_buffer_size = bounce_size;
4202
4203 /* Lie about this since we're bouncing */
4204 mmc->max_segs = max_blocks;
4205 mmc->max_seg_size = bounce_size;
4206 mmc->max_req_size = bounce_size;
4207
4208 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
4209 mmc_hostname(mmc), max_blocks, bounce_size);
4210}
4211
4212static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
4213{
4214 /*
4215 * According to SD Host Controller spec v4.10, bit[27] added from
4216 * version 4.10 in Capabilities Register is used as 64-bit System
4217 * Address support for V4 mode.
4218 */
4219 if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
4220 return host->caps & SDHCI_CAN_64BIT_V4;
4221
4222 return host->caps & SDHCI_CAN_64BIT;
4223}
4224
4225int sdhci_setup_host(struct sdhci_host *host)
4226{
4227 struct mmc_host *mmc;
4228 u32 max_current_caps;
4229 unsigned int ocr_avail;
4230 unsigned int override_timeout_clk;
4231 u32 max_clk;
4232 int ret = 0;
4233 bool enable_vqmmc = false;
4234
4235 WARN_ON(host == NULL);
4236 if (host == NULL)
4237 return -EINVAL;
4238
4239 mmc = host->mmc;
4240
4241 /*
4242 * If there are external regulators, get them. Note this must be done
4243 * early before resetting the host and reading the capabilities so that
4244 * the host can take the appropriate action if regulators are not
4245 * available.
4246 */
4247 if (!mmc->supply.vqmmc) {
4248 ret = mmc_regulator_get_supply(mmc);
4249 if (ret)
4250 return ret;
4251 enable_vqmmc = true;
4252 }
4253
4254 DBG("Version: 0x%08x | Present: 0x%08x\n",
4255 sdhci_readw(host, SDHCI_HOST_VERSION),
4256 sdhci_readl(host, SDHCI_PRESENT_STATE));
4257 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
4258 sdhci_readl(host, SDHCI_CAPABILITIES),
4259 sdhci_readl(host, SDHCI_CAPABILITIES_1));
4260
4261 sdhci_read_caps(host);
4262
4263 override_timeout_clk = host->timeout_clk;
4264
4265 if (host->version > SDHCI_SPEC_420) {
4266 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
4267 mmc_hostname(mmc), host->version);
4268 }
4269
4270 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
4271 host->flags |= SDHCI_USE_SDMA;
4272 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
4273 DBG("Controller doesn't have SDMA capability\n");
4274 else
4275 host->flags |= SDHCI_USE_SDMA;
4276
4277 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
4278 (host->flags & SDHCI_USE_SDMA)) {
4279 DBG("Disabling DMA as it is marked broken\n");
4280 host->flags &= ~SDHCI_USE_SDMA;
4281 }
4282
4283 if ((host->version >= SDHCI_SPEC_200) &&
4284 (host->caps & SDHCI_CAN_DO_ADMA2))
4285 host->flags |= SDHCI_USE_ADMA;
4286
4287 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
4288 (host->flags & SDHCI_USE_ADMA)) {
4289 DBG("Disabling ADMA as it is marked broken\n");
4290 host->flags &= ~SDHCI_USE_ADMA;
4291 }
4292
4293 if (sdhci_can_64bit_dma(host))
4294 host->flags |= SDHCI_USE_64_BIT_DMA;
4295
4296 if (host->use_external_dma) {
4297 ret = sdhci_external_dma_init(host);
4298 if (ret == -EPROBE_DEFER)
4299 goto unreg;
4300 /*
4301 * Fall back to use the DMA/PIO integrated in standard SDHCI
4302 * instead of external DMA devices.
4303 */
4304 else if (ret)
4305 sdhci_switch_external_dma(host, false);
4306 /* Disable internal DMA sources */
4307 else
4308 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4309 }
4310
4311 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
4312 if (host->ops->set_dma_mask)
4313 ret = host->ops->set_dma_mask(host);
4314 else
4315 ret = sdhci_set_dma_mask(host);
4316
4317 if (!ret && host->ops->enable_dma)
4318 ret = host->ops->enable_dma(host);
4319
4320 if (ret) {
4321 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
4322 mmc_hostname(mmc));
4323 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4324
4325 ret = 0;
4326 }
4327 }
4328
4329 /* SDMA does not support 64-bit DMA if v4 mode not set */
4330 if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
4331 host->flags &= ~SDHCI_USE_SDMA;
4332
4333 if (host->flags & SDHCI_USE_ADMA) {
4334 dma_addr_t dma;
4335 void *buf;
4336
4337 if (!(host->flags & SDHCI_USE_64_BIT_DMA))
4338 host->alloc_desc_sz = SDHCI_ADMA2_32_DESC_SZ;
4339 else if (!host->alloc_desc_sz)
4340 host->alloc_desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
4341
4342 host->desc_sz = host->alloc_desc_sz;
4343 host->adma_table_sz = host->adma_table_cnt * host->desc_sz;
4344
4345 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
4346 /*
4347 * Use zalloc to zero the reserved high 32-bits of 128-bit
4348 * descriptors so that they never need to be written.
4349 */
4350 buf = dma_alloc_coherent(mmc_dev(mmc),
4351 host->align_buffer_sz + host->adma_table_sz,
4352 &dma, GFP_KERNEL);
4353 if (!buf) {
4354 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
4355 mmc_hostname(mmc));
4356 host->flags &= ~SDHCI_USE_ADMA;
4357 } else if ((dma + host->align_buffer_sz) &
4358 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
4359 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
4360 mmc_hostname(mmc));
4361 host->flags &= ~SDHCI_USE_ADMA;
4362 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4363 host->adma_table_sz, buf, dma);
4364 } else {
4365 host->align_buffer = buf;
4366 host->align_addr = dma;
4367
4368 host->adma_table = buf + host->align_buffer_sz;
4369 host->adma_addr = dma + host->align_buffer_sz;
4370 }
4371 }
4372
4373 /*
4374 * If we use DMA, then it's up to the caller to set the DMA
4375 * mask, but PIO does not need the hw shim so we set a new
4376 * mask here in that case.
4377 */
4378 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
4379 host->dma_mask = DMA_BIT_MASK(64);
4380 mmc_dev(mmc)->dma_mask = &host->dma_mask;
4381 }
4382
4383 if (host->version >= SDHCI_SPEC_300)
4384 host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps);
4385 else
4386 host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps);
4387
4388 host->max_clk *= 1000000;
4389 if (host->max_clk == 0 || host->quirks &
4390 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4391 if (!host->ops->get_max_clock) {
4392 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
4393 mmc_hostname(mmc));
4394 ret = -ENODEV;
4395 goto undma;
4396 }
4397 host->max_clk = host->ops->get_max_clock(host);
4398 }
4399
4400 /*
4401 * In case of Host Controller v3.00, find out whether clock
4402 * multiplier is supported.
4403 */
4404 host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1);
4405
4406 /*
4407 * In case the value in Clock Multiplier is 0, then programmable
4408 * clock mode is not supported, otherwise the actual clock
4409 * multiplier is one more than the value of Clock Multiplier
4410 * in the Capabilities Register.
4411 */
4412 if (host->clk_mul)
4413 host->clk_mul += 1;
4414
4415 /*
4416 * Set host parameters.
4417 */
4418 max_clk = host->max_clk;
4419
4420 if (host->ops->get_min_clock)
4421 mmc->f_min = host->ops->get_min_clock(host);
4422 else if (host->version >= SDHCI_SPEC_300) {
4423 if (host->clk_mul)
4424 max_clk = host->max_clk * host->clk_mul;
4425 /*
4426 * Divided Clock Mode minimum clock rate is always less than
4427 * Programmable Clock Mode minimum clock rate.
4428 */
4429 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
4430 } else
4431 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
4432
4433 if (!mmc->f_max || mmc->f_max > max_clk)
4434 mmc->f_max = max_clk;
4435
4436 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4437 host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps);
4438
4439 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
4440 host->timeout_clk *= 1000;
4441
4442 if (host->timeout_clk == 0) {
4443 if (!host->ops->get_timeout_clock) {
4444 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
4445 mmc_hostname(mmc));
4446 ret = -ENODEV;
4447 goto undma;
4448 }
4449
4450 host->timeout_clk =
4451 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
4452 1000);
4453 }
4454
4455 if (override_timeout_clk)
4456 host->timeout_clk = override_timeout_clk;
4457
4458 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
4459 host->ops->get_max_timeout_count(host) : 1 << 27;
4460 mmc->max_busy_timeout /= host->timeout_clk;
4461 }
4462
4463 if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
4464 !host->ops->get_max_timeout_count)
4465 mmc->max_busy_timeout = 0;
4466
4467 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_CMD23;
4468 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
4469
4470 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
4471 host->flags |= SDHCI_AUTO_CMD12;
4472
4473 /*
4474 * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
4475 * For v4 mode, SDMA may use Auto-CMD23 as well.
4476 */
4477 if ((host->version >= SDHCI_SPEC_300) &&
4478 ((host->flags & SDHCI_USE_ADMA) ||
4479 !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
4480 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
4481 host->flags |= SDHCI_AUTO_CMD23;
4482 DBG("Auto-CMD23 available\n");
4483 } else {
4484 DBG("Auto-CMD23 unavailable\n");
4485 }
4486
4487 /*
4488 * A controller may support 8-bit width, but the board itself
4489 * might not have the pins brought out. Boards that support
4490 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
4491 * their platform code before calling sdhci_add_host(), and we
4492 * won't assume 8-bit width for hosts without that CAP.
4493 */
4494 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
4495 mmc->caps |= MMC_CAP_4_BIT_DATA;
4496
4497 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
4498 mmc->caps &= ~MMC_CAP_CMD23;
4499
4500 if (host->caps & SDHCI_CAN_DO_HISPD)
4501 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
4502
4503 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4504 mmc_card_is_removable(mmc) &&
4505 mmc_gpio_get_cd(mmc) < 0)
4506 mmc->caps |= MMC_CAP_NEEDS_POLL;
4507
4508 if (!IS_ERR(mmc->supply.vqmmc)) {
4509 if (enable_vqmmc) {
4510 ret = regulator_enable(mmc->supply.vqmmc);
4511 host->sdhci_core_to_disable_vqmmc = !ret;
4512 }
4513
4514 /* If vqmmc provides no 1.8V signalling, then there's no UHS */
4515 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
4516 1950000))
4517 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
4518 SDHCI_SUPPORT_SDR50 |
4519 SDHCI_SUPPORT_DDR50);
4520
4521 /* In eMMC case vqmmc might be a fixed 1.8V regulator */
4522 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
4523 3600000))
4524 host->flags &= ~SDHCI_SIGNALING_330;
4525
4526 if (ret) {
4527 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
4528 mmc_hostname(mmc), ret);
4529 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
4530 }
4531
4532 }
4533
4534 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
4535 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4536 SDHCI_SUPPORT_DDR50);
4537 /*
4538 * The SDHCI controller in a SoC might support HS200/HS400
4539 * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
4540 * but if the board is modeled such that the IO lines are not
4541 * connected to 1.8v then HS200/HS400 cannot be supported.
4542 * Disable HS200/HS400 if the board does not have 1.8v connected
4543 * to the IO lines. (Applicable for other modes in 1.8v)
4544 */
4545 mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
4546 mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
4547 }
4548
4549 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
4550 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4551 SDHCI_SUPPORT_DDR50))
4552 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
4553
4554 /* SDR104 supports also implies SDR50 support */
4555 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
4556 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
4557 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
4558 * field can be promoted to support HS200.
4559 */
4560 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
4561 mmc->caps2 |= MMC_CAP2_HS200;
4562 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
4563 mmc->caps |= MMC_CAP_UHS_SDR50;
4564 }
4565
4566 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
4567 (host->caps1 & SDHCI_SUPPORT_HS400))
4568 mmc->caps2 |= MMC_CAP2_HS400;
4569
4570 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
4571 (IS_ERR(mmc->supply.vqmmc) ||
4572 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
4573 1300000)))
4574 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
4575
4576 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
4577 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
4578 mmc->caps |= MMC_CAP_UHS_DDR50;
4579
4580 /* Does the host need tuning for SDR50? */
4581 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
4582 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
4583
4584 /* Driver Type(s) (A, C, D) supported by the host */
4585 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
4586 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
4587 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
4588 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
4589 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
4590 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
4591
4592 /* Initial value for re-tuning timer count */
4593 host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK,
4594 host->caps1);
4595
4596 /*
4597 * In case Re-tuning Timer is not disabled, the actual value of
4598 * re-tuning timer will be 2 ^ (n - 1).
4599 */
4600 if (host->tuning_count)
4601 host->tuning_count = 1 << (host->tuning_count - 1);
4602
4603 /* Re-tuning mode supported by the Host Controller */
4604 host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1);
4605
4606 ocr_avail = 0;
4607
4608 /*
4609 * According to SD Host Controller spec v3.00, if the Host System
4610 * can afford more than 150mA, Host Driver should set XPC to 1. Also
4611 * the value is meaningful only if Voltage Support in the Capabilities
4612 * register is set. The actual current value is 4 times the register
4613 * value.
4614 */
4615 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
4616 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
4617 int curr = regulator_get_current_limit(mmc->supply.vmmc);
4618 if (curr > 0) {
4619
4620 /* convert to SDHCI_MAX_CURRENT format */
4621 curr = curr/1000; /* convert to mA */
4622 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
4623
4624 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
4625 max_current_caps =
4626 FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, curr) |
4627 FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, curr) |
4628 FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, curr);
4629 }
4630 }
4631
4632 if (host->caps & SDHCI_CAN_VDD_330) {
4633 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
4634
4635 mmc->max_current_330 = FIELD_GET(SDHCI_MAX_CURRENT_330_MASK,
4636 max_current_caps) *
4637 SDHCI_MAX_CURRENT_MULTIPLIER;
4638 }
4639 if (host->caps & SDHCI_CAN_VDD_300) {
4640 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
4641
4642 mmc->max_current_300 = FIELD_GET(SDHCI_MAX_CURRENT_300_MASK,
4643 max_current_caps) *
4644 SDHCI_MAX_CURRENT_MULTIPLIER;
4645 }
4646 if (host->caps & SDHCI_CAN_VDD_180) {
4647 ocr_avail |= MMC_VDD_165_195;
4648
4649 mmc->max_current_180 = FIELD_GET(SDHCI_MAX_CURRENT_180_MASK,
4650 max_current_caps) *
4651 SDHCI_MAX_CURRENT_MULTIPLIER;
4652 }
4653
4654 /* If OCR set by host, use it instead. */
4655 if (host->ocr_mask)
4656 ocr_avail = host->ocr_mask;
4657
4658 /* If OCR set by external regulators, give it highest prio. */
4659 if (mmc->ocr_avail)
4660 ocr_avail = mmc->ocr_avail;
4661
4662 mmc->ocr_avail = ocr_avail;
4663 mmc->ocr_avail_sdio = ocr_avail;
4664 if (host->ocr_avail_sdio)
4665 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
4666 mmc->ocr_avail_sd = ocr_avail;
4667 if (host->ocr_avail_sd)
4668 mmc->ocr_avail_sd &= host->ocr_avail_sd;
4669 else /* normal SD controllers don't support 1.8V */
4670 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
4671 mmc->ocr_avail_mmc = ocr_avail;
4672 if (host->ocr_avail_mmc)
4673 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
4674
4675 if (mmc->ocr_avail == 0) {
4676 pr_err("%s: Hardware doesn't report any support voltages.\n",
4677 mmc_hostname(mmc));
4678 ret = -ENODEV;
4679 goto unreg;
4680 }
4681
4682 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
4683 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
4684 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
4685 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
4686 host->flags |= SDHCI_SIGNALING_180;
4687
4688 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
4689 host->flags |= SDHCI_SIGNALING_120;
4690
4691 spin_lock_init(&host->lock);
4692
4693 /*
4694 * Maximum number of sectors in one transfer. Limited by SDMA boundary
4695 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
4696 * is less anyway.
4697 */
4698 mmc->max_req_size = 524288;
4699
4700 /*
4701 * Maximum number of segments. Depends on if the hardware
4702 * can do scatter/gather or not.
4703 */
4704 if (host->flags & SDHCI_USE_ADMA) {
4705 mmc->max_segs = SDHCI_MAX_SEGS;
4706 } else if (host->flags & SDHCI_USE_SDMA) {
4707 mmc->max_segs = 1;
4708 mmc->max_req_size = min_t(size_t, mmc->max_req_size,
4709 dma_max_mapping_size(mmc_dev(mmc)));
4710 } else { /* PIO */
4711 mmc->max_segs = SDHCI_MAX_SEGS;
4712 }
4713
4714 /*
4715 * Maximum segment size. Could be one segment with the maximum number
4716 * of bytes. When doing hardware scatter/gather, each entry cannot
4717 * be larger than 64 KiB though.
4718 */
4719 if (host->flags & SDHCI_USE_ADMA) {
4720 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) {
4721 host->max_adma = 65532; /* 32-bit alignment */
4722 mmc->max_seg_size = 65535;
4723 } else {
4724 mmc->max_seg_size = 65536;
4725 }
4726 } else {
4727 mmc->max_seg_size = mmc->max_req_size;
4728 }
4729
4730 /*
4731 * Maximum block size. This varies from controller to controller and
4732 * is specified in the capabilities register.
4733 */
4734 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4735 mmc->max_blk_size = 2;
4736 } else {
4737 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
4738 SDHCI_MAX_BLOCK_SHIFT;
4739 if (mmc->max_blk_size >= 3) {
4740 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
4741 mmc_hostname(mmc));
4742 mmc->max_blk_size = 0;
4743 }
4744 }
4745
4746 mmc->max_blk_size = 512 << mmc->max_blk_size;
4747
4748 /*
4749 * Maximum block count.
4750 */
4751 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
4752
4753 if (mmc->max_segs == 1)
4754 /* This may alter mmc->*_blk_* parameters */
4755 sdhci_allocate_bounce_buffer(host);
4756
4757 return 0;
4758
4759unreg:
4760 if (host->sdhci_core_to_disable_vqmmc)
4761 regulator_disable(mmc->supply.vqmmc);
4762undma:
4763 if (host->align_buffer)
4764 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4765 host->adma_table_sz, host->align_buffer,
4766 host->align_addr);
4767 host->adma_table = NULL;
4768 host->align_buffer = NULL;
4769
4770 return ret;
4771}
4772EXPORT_SYMBOL_GPL(sdhci_setup_host);
4773
4774void sdhci_cleanup_host(struct sdhci_host *host)
4775{
4776 struct mmc_host *mmc = host->mmc;
4777
4778 if (host->sdhci_core_to_disable_vqmmc)
4779 regulator_disable(mmc->supply.vqmmc);
4780
4781 if (host->align_buffer)
4782 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4783 host->adma_table_sz, host->align_buffer,
4784 host->align_addr);
4785
4786 if (host->use_external_dma)
4787 sdhci_external_dma_release(host);
4788
4789 host->adma_table = NULL;
4790 host->align_buffer = NULL;
4791}
4792EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
4793
4794int __sdhci_add_host(struct sdhci_host *host)
4795{
4796 unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI;
4797 struct mmc_host *mmc = host->mmc;
4798 int ret;
4799
4800 if ((mmc->caps2 & MMC_CAP2_CQE) &&
4801 (host->quirks & SDHCI_QUIRK_BROKEN_CQE)) {
4802 mmc->caps2 &= ~MMC_CAP2_CQE;
4803 mmc->cqe_ops = NULL;
4804 }
4805
4806 host->complete_wq = alloc_workqueue("sdhci", flags, 0);
4807 if (!host->complete_wq)
4808 return -ENOMEM;
4809
4810 INIT_WORK(&host->complete_work, sdhci_complete_work);
4811
4812 timer_setup(&host->timer, sdhci_timeout_timer, 0);
4813 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
4814
4815 init_waitqueue_head(&host->buf_ready_int);
4816
4817 sdhci_init(host, 0);
4818
4819 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
4820 IRQF_SHARED, mmc_hostname(mmc), host);
4821 if (ret) {
4822 pr_err("%s: Failed to request IRQ %d: %d\n",
4823 mmc_hostname(mmc), host->irq, ret);
4824 goto unwq;
4825 }
4826
4827 ret = sdhci_led_register(host);
4828 if (ret) {
4829 pr_err("%s: Failed to register LED device: %d\n",
4830 mmc_hostname(mmc), ret);
4831 goto unirq;
4832 }
4833
4834 ret = mmc_add_host(mmc);
4835 if (ret)
4836 goto unled;
4837
4838 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
4839 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
4840 host->use_external_dma ? "External DMA" :
4841 (host->flags & SDHCI_USE_ADMA) ?
4842 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
4843 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4844
4845 sdhci_enable_card_detection(host);
4846
4847 return 0;
4848
4849unled:
4850 sdhci_led_unregister(host);
4851unirq:
4852 sdhci_reset_for_all(host);
4853 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4854 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4855 free_irq(host->irq, host);
4856unwq:
4857 destroy_workqueue(host->complete_wq);
4858
4859 return ret;
4860}
4861EXPORT_SYMBOL_GPL(__sdhci_add_host);
4862
4863int sdhci_add_host(struct sdhci_host *host)
4864{
4865 int ret;
4866
4867 ret = sdhci_setup_host(host);
4868 if (ret)
4869 return ret;
4870
4871 ret = __sdhci_add_host(host);
4872 if (ret)
4873 goto cleanup;
4874
4875 return 0;
4876
4877cleanup:
4878 sdhci_cleanup_host(host);
4879
4880 return ret;
4881}
4882EXPORT_SYMBOL_GPL(sdhci_add_host);
4883
4884void sdhci_remove_host(struct sdhci_host *host, int dead)
4885{
4886 struct mmc_host *mmc = host->mmc;
4887 unsigned long flags;
4888
4889 if (dead) {
4890 spin_lock_irqsave(&host->lock, flags);
4891
4892 host->flags |= SDHCI_DEVICE_DEAD;
4893
4894 if (sdhci_has_requests(host)) {
4895 pr_err("%s: Controller removed during "
4896 " transfer!\n", mmc_hostname(mmc));
4897 sdhci_error_out_mrqs(host, -ENOMEDIUM);
4898 }
4899
4900 spin_unlock_irqrestore(&host->lock, flags);
4901 }
4902
4903 sdhci_disable_card_detection(host);
4904
4905 mmc_remove_host(mmc);
4906
4907 sdhci_led_unregister(host);
4908
4909 if (!dead)
4910 sdhci_reset_for_all(host);
4911
4912 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4913 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4914 free_irq(host->irq, host);
4915
4916 del_timer_sync(&host->timer);
4917 del_timer_sync(&host->data_timer);
4918
4919 destroy_workqueue(host->complete_wq);
4920
4921 if (host->sdhci_core_to_disable_vqmmc)
4922 regulator_disable(mmc->supply.vqmmc);
4923
4924 if (host->align_buffer)
4925 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4926 host->adma_table_sz, host->align_buffer,
4927 host->align_addr);
4928
4929 if (host->use_external_dma)
4930 sdhci_external_dma_release(host);
4931
4932 host->adma_table = NULL;
4933 host->align_buffer = NULL;
4934}
4935
4936EXPORT_SYMBOL_GPL(sdhci_remove_host);
4937
4938void sdhci_free_host(struct sdhci_host *host)
4939{
4940 mmc_free_host(host->mmc);
4941}
4942
4943EXPORT_SYMBOL_GPL(sdhci_free_host);
4944
4945/*****************************************************************************\
4946 * *
4947 * Driver init/exit *
4948 * *
4949\*****************************************************************************/
4950
4951static int __init sdhci_drv_init(void)
4952{
4953 pr_info(DRIVER_NAME
4954 ": Secure Digital Host Controller Interface driver\n");
4955 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4956
4957 return 0;
4958}
4959
4960static void __exit sdhci_drv_exit(void)
4961{
4962}
4963
4964module_init(sdhci_drv_init);
4965module_exit(sdhci_drv_exit);
4966
4967module_param(debug_quirks, uint, 0444);
4968module_param(debug_quirks2, uint, 0444);
4969
4970MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4971MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4972MODULE_LICENSE("GPL");
4973
4974MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4975MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 *
5 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 *
7 * Thanks to the following companies for their support:
8 *
9 * - JMicron (hardware and technical support)
10 */
11
12#include <linux/bitfield.h>
13#include <linux/delay.h>
14#include <linux/dmaengine.h>
15#include <linux/ktime.h>
16#include <linux/highmem.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/dma-mapping.h>
20#include <linux/slab.h>
21#include <linux/scatterlist.h>
22#include <linux/sizes.h>
23#include <linux/regulator/consumer.h>
24#include <linux/pm_runtime.h>
25#include <linux/of.h>
26
27#include <linux/leds.h>
28
29#include <linux/mmc/mmc.h>
30#include <linux/mmc/host.h>
31#include <linux/mmc/card.h>
32#include <linux/mmc/sdio.h>
33#include <linux/mmc/slot-gpio.h>
34
35#include "sdhci.h"
36
37#define DRIVER_NAME "sdhci"
38
39#define DBG(f, x...) \
40 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
41
42#define SDHCI_DUMP(f, x...) \
43 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
44
45#define MAX_TUNING_LOOP 40
46
47static unsigned int debug_quirks = 0;
48static unsigned int debug_quirks2;
49
50static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
51
52static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
53
54void sdhci_dumpregs(struct sdhci_host *host)
55{
56 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
57
58 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
59 sdhci_readl(host, SDHCI_DMA_ADDRESS),
60 sdhci_readw(host, SDHCI_HOST_VERSION));
61 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
62 sdhci_readw(host, SDHCI_BLOCK_SIZE),
63 sdhci_readw(host, SDHCI_BLOCK_COUNT));
64 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
65 sdhci_readl(host, SDHCI_ARGUMENT),
66 sdhci_readw(host, SDHCI_TRANSFER_MODE));
67 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
68 sdhci_readl(host, SDHCI_PRESENT_STATE),
69 sdhci_readb(host, SDHCI_HOST_CONTROL));
70 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
71 sdhci_readb(host, SDHCI_POWER_CONTROL),
72 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
73 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
74 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
75 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
76 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
77 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
78 sdhci_readl(host, SDHCI_INT_STATUS));
79 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
80 sdhci_readl(host, SDHCI_INT_ENABLE),
81 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
82 SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
83 sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
84 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
85 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
86 sdhci_readl(host, SDHCI_CAPABILITIES),
87 sdhci_readl(host, SDHCI_CAPABILITIES_1));
88 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
89 sdhci_readw(host, SDHCI_COMMAND),
90 sdhci_readl(host, SDHCI_MAX_CURRENT));
91 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
92 sdhci_readl(host, SDHCI_RESPONSE),
93 sdhci_readl(host, SDHCI_RESPONSE + 4));
94 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
95 sdhci_readl(host, SDHCI_RESPONSE + 8),
96 sdhci_readl(host, SDHCI_RESPONSE + 12));
97 SDHCI_DUMP("Host ctl2: 0x%08x\n",
98 sdhci_readw(host, SDHCI_HOST_CONTROL2));
99
100 if (host->flags & SDHCI_USE_ADMA) {
101 if (host->flags & SDHCI_USE_64_BIT_DMA) {
102 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
103 sdhci_readl(host, SDHCI_ADMA_ERROR),
104 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
105 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
106 } else {
107 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
108 sdhci_readl(host, SDHCI_ADMA_ERROR),
109 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
110 }
111 }
112
113 if (host->ops->dump_vendor_regs)
114 host->ops->dump_vendor_regs(host);
115
116 SDHCI_DUMP("============================================\n");
117}
118EXPORT_SYMBOL_GPL(sdhci_dumpregs);
119
120/*****************************************************************************\
121 * *
122 * Low level functions *
123 * *
124\*****************************************************************************/
125
126static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
127{
128 u16 ctrl2;
129
130 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
131 if (ctrl2 & SDHCI_CTRL_V4_MODE)
132 return;
133
134 ctrl2 |= SDHCI_CTRL_V4_MODE;
135 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
136}
137
138/*
139 * This can be called before sdhci_add_host() by Vendor's host controller
140 * driver to enable v4 mode if supported.
141 */
142void sdhci_enable_v4_mode(struct sdhci_host *host)
143{
144 host->v4_mode = true;
145 sdhci_do_enable_v4_mode(host);
146}
147EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
148
149static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
150{
151 return cmd->data || cmd->flags & MMC_RSP_BUSY;
152}
153
154static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
155{
156 u32 present;
157
158 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
159 !mmc_card_is_removable(host->mmc) || mmc_can_gpio_cd(host->mmc))
160 return;
161
162 if (enable) {
163 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
164 SDHCI_CARD_PRESENT;
165
166 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
167 SDHCI_INT_CARD_INSERT;
168 } else {
169 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
170 }
171
172 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
173 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
174}
175
176static void sdhci_enable_card_detection(struct sdhci_host *host)
177{
178 sdhci_set_card_detection(host, true);
179}
180
181static void sdhci_disable_card_detection(struct sdhci_host *host)
182{
183 sdhci_set_card_detection(host, false);
184}
185
186static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
187{
188 if (host->bus_on)
189 return;
190 host->bus_on = true;
191 pm_runtime_get_noresume(mmc_dev(host->mmc));
192}
193
194static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
195{
196 if (!host->bus_on)
197 return;
198 host->bus_on = false;
199 pm_runtime_put_noidle(mmc_dev(host->mmc));
200}
201
202void sdhci_reset(struct sdhci_host *host, u8 mask)
203{
204 ktime_t timeout;
205
206 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
207
208 if (mask & SDHCI_RESET_ALL) {
209 host->clock = 0;
210 /* Reset-all turns off SD Bus Power */
211 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
212 sdhci_runtime_pm_bus_off(host);
213 }
214
215 /* Wait max 100 ms */
216 timeout = ktime_add_ms(ktime_get(), 100);
217
218 /* hw clears the bit when it's done */
219 while (1) {
220 bool timedout = ktime_after(ktime_get(), timeout);
221
222 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
223 break;
224 if (timedout) {
225 pr_err("%s: Reset 0x%x never completed.\n",
226 mmc_hostname(host->mmc), (int)mask);
227 sdhci_dumpregs(host);
228 return;
229 }
230 udelay(10);
231 }
232}
233EXPORT_SYMBOL_GPL(sdhci_reset);
234
235static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
236{
237 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
238 struct mmc_host *mmc = host->mmc;
239
240 if (!mmc->ops->get_cd(mmc))
241 return;
242 }
243
244 host->ops->reset(host, mask);
245
246 if (mask & SDHCI_RESET_ALL) {
247 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
248 if (host->ops->enable_dma)
249 host->ops->enable_dma(host);
250 }
251
252 /* Resetting the controller clears many */
253 host->preset_enabled = false;
254 }
255}
256
257static void sdhci_set_default_irqs(struct sdhci_host *host)
258{
259 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
260 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
261 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
262 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
263 SDHCI_INT_RESPONSE;
264
265 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
266 host->tuning_mode == SDHCI_TUNING_MODE_3)
267 host->ier |= SDHCI_INT_RETUNE;
268
269 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
270 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
271}
272
273static void sdhci_config_dma(struct sdhci_host *host)
274{
275 u8 ctrl;
276 u16 ctrl2;
277
278 if (host->version < SDHCI_SPEC_200)
279 return;
280
281 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
282
283 /*
284 * Always adjust the DMA selection as some controllers
285 * (e.g. JMicron) can't do PIO properly when the selection
286 * is ADMA.
287 */
288 ctrl &= ~SDHCI_CTRL_DMA_MASK;
289 if (!(host->flags & SDHCI_REQ_USE_DMA))
290 goto out;
291
292 /* Note if DMA Select is zero then SDMA is selected */
293 if (host->flags & SDHCI_USE_ADMA)
294 ctrl |= SDHCI_CTRL_ADMA32;
295
296 if (host->flags & SDHCI_USE_64_BIT_DMA) {
297 /*
298 * If v4 mode, all supported DMA can be 64-bit addressing if
299 * controller supports 64-bit system address, otherwise only
300 * ADMA can support 64-bit addressing.
301 */
302 if (host->v4_mode) {
303 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
304 ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
305 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
306 } else if (host->flags & SDHCI_USE_ADMA) {
307 /*
308 * Don't need to undo SDHCI_CTRL_ADMA32 in order to
309 * set SDHCI_CTRL_ADMA64.
310 */
311 ctrl |= SDHCI_CTRL_ADMA64;
312 }
313 }
314
315out:
316 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
317}
318
319static void sdhci_init(struct sdhci_host *host, int soft)
320{
321 struct mmc_host *mmc = host->mmc;
322 unsigned long flags;
323
324 if (soft)
325 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
326 else
327 sdhci_do_reset(host, SDHCI_RESET_ALL);
328
329 if (host->v4_mode)
330 sdhci_do_enable_v4_mode(host);
331
332 spin_lock_irqsave(&host->lock, flags);
333 sdhci_set_default_irqs(host);
334 spin_unlock_irqrestore(&host->lock, flags);
335
336 host->cqe_on = false;
337
338 if (soft) {
339 /* force clock reconfiguration */
340 host->clock = 0;
341 mmc->ops->set_ios(mmc, &mmc->ios);
342 }
343}
344
345static void sdhci_reinit(struct sdhci_host *host)
346{
347 u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
348
349 sdhci_init(host, 0);
350 sdhci_enable_card_detection(host);
351
352 /*
353 * A change to the card detect bits indicates a change in present state,
354 * refer sdhci_set_card_detection(). A card detect interrupt might have
355 * been missed while the host controller was being reset, so trigger a
356 * rescan to check.
357 */
358 if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT)))
359 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
360}
361
362static void __sdhci_led_activate(struct sdhci_host *host)
363{
364 u8 ctrl;
365
366 if (host->quirks & SDHCI_QUIRK_NO_LED)
367 return;
368
369 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
370 ctrl |= SDHCI_CTRL_LED;
371 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
372}
373
374static void __sdhci_led_deactivate(struct sdhci_host *host)
375{
376 u8 ctrl;
377
378 if (host->quirks & SDHCI_QUIRK_NO_LED)
379 return;
380
381 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
382 ctrl &= ~SDHCI_CTRL_LED;
383 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
384}
385
386#if IS_REACHABLE(CONFIG_LEDS_CLASS)
387static void sdhci_led_control(struct led_classdev *led,
388 enum led_brightness brightness)
389{
390 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
391 unsigned long flags;
392
393 spin_lock_irqsave(&host->lock, flags);
394
395 if (host->runtime_suspended)
396 goto out;
397
398 if (brightness == LED_OFF)
399 __sdhci_led_deactivate(host);
400 else
401 __sdhci_led_activate(host);
402out:
403 spin_unlock_irqrestore(&host->lock, flags);
404}
405
406static int sdhci_led_register(struct sdhci_host *host)
407{
408 struct mmc_host *mmc = host->mmc;
409
410 if (host->quirks & SDHCI_QUIRK_NO_LED)
411 return 0;
412
413 snprintf(host->led_name, sizeof(host->led_name),
414 "%s::", mmc_hostname(mmc));
415
416 host->led.name = host->led_name;
417 host->led.brightness = LED_OFF;
418 host->led.default_trigger = mmc_hostname(mmc);
419 host->led.brightness_set = sdhci_led_control;
420
421 return led_classdev_register(mmc_dev(mmc), &host->led);
422}
423
424static void sdhci_led_unregister(struct sdhci_host *host)
425{
426 if (host->quirks & SDHCI_QUIRK_NO_LED)
427 return;
428
429 led_classdev_unregister(&host->led);
430}
431
432static inline void sdhci_led_activate(struct sdhci_host *host)
433{
434}
435
436static inline void sdhci_led_deactivate(struct sdhci_host *host)
437{
438}
439
440#else
441
442static inline int sdhci_led_register(struct sdhci_host *host)
443{
444 return 0;
445}
446
447static inline void sdhci_led_unregister(struct sdhci_host *host)
448{
449}
450
451static inline void sdhci_led_activate(struct sdhci_host *host)
452{
453 __sdhci_led_activate(host);
454}
455
456static inline void sdhci_led_deactivate(struct sdhci_host *host)
457{
458 __sdhci_led_deactivate(host);
459}
460
461#endif
462
463static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
464 unsigned long timeout)
465{
466 if (sdhci_data_line_cmd(mrq->cmd))
467 mod_timer(&host->data_timer, timeout);
468 else
469 mod_timer(&host->timer, timeout);
470}
471
472static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
473{
474 if (sdhci_data_line_cmd(mrq->cmd))
475 del_timer(&host->data_timer);
476 else
477 del_timer(&host->timer);
478}
479
480static inline bool sdhci_has_requests(struct sdhci_host *host)
481{
482 return host->cmd || host->data_cmd;
483}
484
485/*****************************************************************************\
486 * *
487 * Core functions *
488 * *
489\*****************************************************************************/
490
491static void sdhci_read_block_pio(struct sdhci_host *host)
492{
493 unsigned long flags;
494 size_t blksize, len, chunk;
495 u32 scratch;
496 u8 *buf;
497
498 DBG("PIO reading\n");
499
500 blksize = host->data->blksz;
501 chunk = 0;
502
503 local_irq_save(flags);
504
505 while (blksize) {
506 BUG_ON(!sg_miter_next(&host->sg_miter));
507
508 len = min(host->sg_miter.length, blksize);
509
510 blksize -= len;
511 host->sg_miter.consumed = len;
512
513 buf = host->sg_miter.addr;
514
515 while (len) {
516 if (chunk == 0) {
517 scratch = sdhci_readl(host, SDHCI_BUFFER);
518 chunk = 4;
519 }
520
521 *buf = scratch & 0xFF;
522
523 buf++;
524 scratch >>= 8;
525 chunk--;
526 len--;
527 }
528 }
529
530 sg_miter_stop(&host->sg_miter);
531
532 local_irq_restore(flags);
533}
534
535static void sdhci_write_block_pio(struct sdhci_host *host)
536{
537 unsigned long flags;
538 size_t blksize, len, chunk;
539 u32 scratch;
540 u8 *buf;
541
542 DBG("PIO writing\n");
543
544 blksize = host->data->blksz;
545 chunk = 0;
546 scratch = 0;
547
548 local_irq_save(flags);
549
550 while (blksize) {
551 BUG_ON(!sg_miter_next(&host->sg_miter));
552
553 len = min(host->sg_miter.length, blksize);
554
555 blksize -= len;
556 host->sg_miter.consumed = len;
557
558 buf = host->sg_miter.addr;
559
560 while (len) {
561 scratch |= (u32)*buf << (chunk * 8);
562
563 buf++;
564 chunk++;
565 len--;
566
567 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
568 sdhci_writel(host, scratch, SDHCI_BUFFER);
569 chunk = 0;
570 scratch = 0;
571 }
572 }
573 }
574
575 sg_miter_stop(&host->sg_miter);
576
577 local_irq_restore(flags);
578}
579
580static void sdhci_transfer_pio(struct sdhci_host *host)
581{
582 u32 mask;
583
584 if (host->blocks == 0)
585 return;
586
587 if (host->data->flags & MMC_DATA_READ)
588 mask = SDHCI_DATA_AVAILABLE;
589 else
590 mask = SDHCI_SPACE_AVAILABLE;
591
592 /*
593 * Some controllers (JMicron JMB38x) mess up the buffer bits
594 * for transfers < 4 bytes. As long as it is just one block,
595 * we can ignore the bits.
596 */
597 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
598 (host->data->blocks == 1))
599 mask = ~0;
600
601 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
602 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
603 udelay(100);
604
605 if (host->data->flags & MMC_DATA_READ)
606 sdhci_read_block_pio(host);
607 else
608 sdhci_write_block_pio(host);
609
610 host->blocks--;
611 if (host->blocks == 0)
612 break;
613 }
614
615 DBG("PIO transfer complete.\n");
616}
617
618static int sdhci_pre_dma_transfer(struct sdhci_host *host,
619 struct mmc_data *data, int cookie)
620{
621 int sg_count;
622
623 /*
624 * If the data buffers are already mapped, return the previous
625 * dma_map_sg() result.
626 */
627 if (data->host_cookie == COOKIE_PRE_MAPPED)
628 return data->sg_count;
629
630 /* Bounce write requests to the bounce buffer */
631 if (host->bounce_buffer) {
632 unsigned int length = data->blksz * data->blocks;
633
634 if (length > host->bounce_buffer_size) {
635 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
636 mmc_hostname(host->mmc), length,
637 host->bounce_buffer_size);
638 return -EIO;
639 }
640 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
641 /* Copy the data to the bounce buffer */
642 if (host->ops->copy_to_bounce_buffer) {
643 host->ops->copy_to_bounce_buffer(host,
644 data, length);
645 } else {
646 sg_copy_to_buffer(data->sg, data->sg_len,
647 host->bounce_buffer, length);
648 }
649 }
650 /* Switch ownership to the DMA */
651 dma_sync_single_for_device(mmc_dev(host->mmc),
652 host->bounce_addr,
653 host->bounce_buffer_size,
654 mmc_get_dma_dir(data));
655 /* Just a dummy value */
656 sg_count = 1;
657 } else {
658 /* Just access the data directly from memory */
659 sg_count = dma_map_sg(mmc_dev(host->mmc),
660 data->sg, data->sg_len,
661 mmc_get_dma_dir(data));
662 }
663
664 if (sg_count == 0)
665 return -ENOSPC;
666
667 data->sg_count = sg_count;
668 data->host_cookie = cookie;
669
670 return sg_count;
671}
672
673static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
674{
675 local_irq_save(*flags);
676 return kmap_atomic(sg_page(sg)) + sg->offset;
677}
678
679static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
680{
681 kunmap_atomic(buffer);
682 local_irq_restore(*flags);
683}
684
685void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
686 dma_addr_t addr, int len, unsigned int cmd)
687{
688 struct sdhci_adma2_64_desc *dma_desc = *desc;
689
690 /* 32-bit and 64-bit descriptors have these members in same position */
691 dma_desc->cmd = cpu_to_le16(cmd);
692 dma_desc->len = cpu_to_le16(len);
693 dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr));
694
695 if (host->flags & SDHCI_USE_64_BIT_DMA)
696 dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr));
697
698 *desc += host->desc_sz;
699}
700EXPORT_SYMBOL_GPL(sdhci_adma_write_desc);
701
702static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
703 void **desc, dma_addr_t addr,
704 int len, unsigned int cmd)
705{
706 if (host->ops->adma_write_desc)
707 host->ops->adma_write_desc(host, desc, addr, len, cmd);
708 else
709 sdhci_adma_write_desc(host, desc, addr, len, cmd);
710}
711
712static void sdhci_adma_mark_end(void *desc)
713{
714 struct sdhci_adma2_64_desc *dma_desc = desc;
715
716 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
717 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
718}
719
720static void sdhci_adma_table_pre(struct sdhci_host *host,
721 struct mmc_data *data, int sg_count)
722{
723 struct scatterlist *sg;
724 unsigned long flags;
725 dma_addr_t addr, align_addr;
726 void *desc, *align;
727 char *buffer;
728 int len, offset, i;
729
730 /*
731 * The spec does not specify endianness of descriptor table.
732 * We currently guess that it is LE.
733 */
734
735 host->sg_count = sg_count;
736
737 desc = host->adma_table;
738 align = host->align_buffer;
739
740 align_addr = host->align_addr;
741
742 for_each_sg(data->sg, sg, host->sg_count, i) {
743 addr = sg_dma_address(sg);
744 len = sg_dma_len(sg);
745
746 /*
747 * The SDHCI specification states that ADMA addresses must
748 * be 32-bit aligned. If they aren't, then we use a bounce
749 * buffer for the (up to three) bytes that screw up the
750 * alignment.
751 */
752 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
753 SDHCI_ADMA2_MASK;
754 if (offset) {
755 if (data->flags & MMC_DATA_WRITE) {
756 buffer = sdhci_kmap_atomic(sg, &flags);
757 memcpy(align, buffer, offset);
758 sdhci_kunmap_atomic(buffer, &flags);
759 }
760
761 /* tran, valid */
762 __sdhci_adma_write_desc(host, &desc, align_addr,
763 offset, ADMA2_TRAN_VALID);
764
765 BUG_ON(offset > 65536);
766
767 align += SDHCI_ADMA2_ALIGN;
768 align_addr += SDHCI_ADMA2_ALIGN;
769
770 addr += offset;
771 len -= offset;
772 }
773
774 BUG_ON(len > 65536);
775
776 /* tran, valid */
777 if (len)
778 __sdhci_adma_write_desc(host, &desc, addr, len,
779 ADMA2_TRAN_VALID);
780
781 /*
782 * If this triggers then we have a calculation bug
783 * somewhere. :/
784 */
785 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
786 }
787
788 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
789 /* Mark the last descriptor as the terminating descriptor */
790 if (desc != host->adma_table) {
791 desc -= host->desc_sz;
792 sdhci_adma_mark_end(desc);
793 }
794 } else {
795 /* Add a terminating entry - nop, end, valid */
796 __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
797 }
798}
799
800static void sdhci_adma_table_post(struct sdhci_host *host,
801 struct mmc_data *data)
802{
803 struct scatterlist *sg;
804 int i, size;
805 void *align;
806 char *buffer;
807 unsigned long flags;
808
809 if (data->flags & MMC_DATA_READ) {
810 bool has_unaligned = false;
811
812 /* Do a quick scan of the SG list for any unaligned mappings */
813 for_each_sg(data->sg, sg, host->sg_count, i)
814 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
815 has_unaligned = true;
816 break;
817 }
818
819 if (has_unaligned) {
820 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
821 data->sg_len, DMA_FROM_DEVICE);
822
823 align = host->align_buffer;
824
825 for_each_sg(data->sg, sg, host->sg_count, i) {
826 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
827 size = SDHCI_ADMA2_ALIGN -
828 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
829
830 buffer = sdhci_kmap_atomic(sg, &flags);
831 memcpy(buffer, align, size);
832 sdhci_kunmap_atomic(buffer, &flags);
833
834 align += SDHCI_ADMA2_ALIGN;
835 }
836 }
837 }
838 }
839}
840
841static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
842{
843 sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
844 if (host->flags & SDHCI_USE_64_BIT_DMA)
845 sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
846}
847
848static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
849{
850 if (host->bounce_buffer)
851 return host->bounce_addr;
852 else
853 return sg_dma_address(host->data->sg);
854}
855
856static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
857{
858 if (host->v4_mode)
859 sdhci_set_adma_addr(host, addr);
860 else
861 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
862}
863
864static unsigned int sdhci_target_timeout(struct sdhci_host *host,
865 struct mmc_command *cmd,
866 struct mmc_data *data)
867{
868 unsigned int target_timeout;
869
870 /* timeout in us */
871 if (!data) {
872 target_timeout = cmd->busy_timeout * 1000;
873 } else {
874 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
875 if (host->clock && data->timeout_clks) {
876 unsigned long long val;
877
878 /*
879 * data->timeout_clks is in units of clock cycles.
880 * host->clock is in Hz. target_timeout is in us.
881 * Hence, us = 1000000 * cycles / Hz. Round up.
882 */
883 val = 1000000ULL * data->timeout_clks;
884 if (do_div(val, host->clock))
885 target_timeout++;
886 target_timeout += val;
887 }
888 }
889
890 return target_timeout;
891}
892
893static void sdhci_calc_sw_timeout(struct sdhci_host *host,
894 struct mmc_command *cmd)
895{
896 struct mmc_data *data = cmd->data;
897 struct mmc_host *mmc = host->mmc;
898 struct mmc_ios *ios = &mmc->ios;
899 unsigned char bus_width = 1 << ios->bus_width;
900 unsigned int blksz;
901 unsigned int freq;
902 u64 target_timeout;
903 u64 transfer_time;
904
905 target_timeout = sdhci_target_timeout(host, cmd, data);
906 target_timeout *= NSEC_PER_USEC;
907
908 if (data) {
909 blksz = data->blksz;
910 freq = mmc->actual_clock ? : host->clock;
911 transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
912 do_div(transfer_time, freq);
913 /* multiply by '2' to account for any unknowns */
914 transfer_time = transfer_time * 2;
915 /* calculate timeout for the entire data */
916 host->data_timeout = data->blocks * target_timeout +
917 transfer_time;
918 } else {
919 host->data_timeout = target_timeout;
920 }
921
922 if (host->data_timeout)
923 host->data_timeout += MMC_CMD_TRANSFER_TIME;
924}
925
926static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
927 bool *too_big)
928{
929 u8 count;
930 struct mmc_data *data;
931 unsigned target_timeout, current_timeout;
932
933 *too_big = true;
934
935 /*
936 * If the host controller provides us with an incorrect timeout
937 * value, just skip the check and use 0xE. The hardware may take
938 * longer to time out, but that's much better than having a too-short
939 * timeout value.
940 */
941 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
942 return 0xE;
943
944 /* Unspecified command, asume max */
945 if (cmd == NULL)
946 return 0xE;
947
948 data = cmd->data;
949 /* Unspecified timeout, assume max */
950 if (!data && !cmd->busy_timeout)
951 return 0xE;
952
953 /* timeout in us */
954 target_timeout = sdhci_target_timeout(host, cmd, data);
955
956 /*
957 * Figure out needed cycles.
958 * We do this in steps in order to fit inside a 32 bit int.
959 * The first step is the minimum timeout, which will have a
960 * minimum resolution of 6 bits:
961 * (1) 2^13*1000 > 2^22,
962 * (2) host->timeout_clk < 2^16
963 * =>
964 * (1) / (2) > 2^6
965 */
966 count = 0;
967 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
968 while (current_timeout < target_timeout) {
969 count++;
970 current_timeout <<= 1;
971 if (count >= 0xF)
972 break;
973 }
974
975 if (count >= 0xF) {
976 if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
977 DBG("Too large timeout 0x%x requested for CMD%d!\n",
978 count, cmd->opcode);
979 count = 0xE;
980 } else {
981 *too_big = false;
982 }
983
984 return count;
985}
986
987static void sdhci_set_transfer_irqs(struct sdhci_host *host)
988{
989 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
990 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
991
992 if (host->flags & SDHCI_REQ_USE_DMA)
993 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
994 else
995 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
996
997 if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
998 host->ier |= SDHCI_INT_AUTO_CMD_ERR;
999 else
1000 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
1001
1002 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1003 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1004}
1005
1006void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
1007{
1008 if (enable)
1009 host->ier |= SDHCI_INT_DATA_TIMEOUT;
1010 else
1011 host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
1012 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1013 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1014}
1015EXPORT_SYMBOL_GPL(sdhci_set_data_timeout_irq);
1016
1017void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1018{
1019 bool too_big = false;
1020 u8 count = sdhci_calc_timeout(host, cmd, &too_big);
1021
1022 if (too_big &&
1023 host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
1024 sdhci_calc_sw_timeout(host, cmd);
1025 sdhci_set_data_timeout_irq(host, false);
1026 } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
1027 sdhci_set_data_timeout_irq(host, true);
1028 }
1029
1030 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
1031}
1032EXPORT_SYMBOL_GPL(__sdhci_set_timeout);
1033
1034static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1035{
1036 if (host->ops->set_timeout)
1037 host->ops->set_timeout(host, cmd);
1038 else
1039 __sdhci_set_timeout(host, cmd);
1040}
1041
1042static void sdhci_initialize_data(struct sdhci_host *host,
1043 struct mmc_data *data)
1044{
1045 WARN_ON(host->data);
1046
1047 /* Sanity checks */
1048 BUG_ON(data->blksz * data->blocks > 524288);
1049 BUG_ON(data->blksz > host->mmc->max_blk_size);
1050 BUG_ON(data->blocks > 65535);
1051
1052 host->data = data;
1053 host->data_early = 0;
1054 host->data->bytes_xfered = 0;
1055}
1056
1057static inline void sdhci_set_block_info(struct sdhci_host *host,
1058 struct mmc_data *data)
1059{
1060 /* Set the DMA boundary value and block size */
1061 sdhci_writew(host,
1062 SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
1063 SDHCI_BLOCK_SIZE);
1064 /*
1065 * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
1066 * can be supported, in that case 16-bit block count register must be 0.
1067 */
1068 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1069 (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
1070 if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
1071 sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
1072 sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
1073 } else {
1074 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1075 }
1076}
1077
1078static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
1079{
1080 struct mmc_data *data = cmd->data;
1081
1082 sdhci_initialize_data(host, data);
1083
1084 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1085 struct scatterlist *sg;
1086 unsigned int length_mask, offset_mask;
1087 int i;
1088
1089 host->flags |= SDHCI_REQ_USE_DMA;
1090
1091 /*
1092 * FIXME: This doesn't account for merging when mapping the
1093 * scatterlist.
1094 *
1095 * The assumption here being that alignment and lengths are
1096 * the same after DMA mapping to device address space.
1097 */
1098 length_mask = 0;
1099 offset_mask = 0;
1100 if (host->flags & SDHCI_USE_ADMA) {
1101 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
1102 length_mask = 3;
1103 /*
1104 * As we use up to 3 byte chunks to work
1105 * around alignment problems, we need to
1106 * check the offset as well.
1107 */
1108 offset_mask = 3;
1109 }
1110 } else {
1111 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
1112 length_mask = 3;
1113 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
1114 offset_mask = 3;
1115 }
1116
1117 if (unlikely(length_mask | offset_mask)) {
1118 for_each_sg(data->sg, sg, data->sg_len, i) {
1119 if (sg->length & length_mask) {
1120 DBG("Reverting to PIO because of transfer size (%d)\n",
1121 sg->length);
1122 host->flags &= ~SDHCI_REQ_USE_DMA;
1123 break;
1124 }
1125 if (sg->offset & offset_mask) {
1126 DBG("Reverting to PIO because of bad alignment\n");
1127 host->flags &= ~SDHCI_REQ_USE_DMA;
1128 break;
1129 }
1130 }
1131 }
1132 }
1133
1134 if (host->flags & SDHCI_REQ_USE_DMA) {
1135 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1136
1137 if (sg_cnt <= 0) {
1138 /*
1139 * This only happens when someone fed
1140 * us an invalid request.
1141 */
1142 WARN_ON(1);
1143 host->flags &= ~SDHCI_REQ_USE_DMA;
1144 } else if (host->flags & SDHCI_USE_ADMA) {
1145 sdhci_adma_table_pre(host, data, sg_cnt);
1146 sdhci_set_adma_addr(host, host->adma_addr);
1147 } else {
1148 WARN_ON(sg_cnt != 1);
1149 sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
1150 }
1151 }
1152
1153 sdhci_config_dma(host);
1154
1155 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
1156 int flags;
1157
1158 flags = SG_MITER_ATOMIC;
1159 if (host->data->flags & MMC_DATA_READ)
1160 flags |= SG_MITER_TO_SG;
1161 else
1162 flags |= SG_MITER_FROM_SG;
1163 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1164 host->blocks = data->blocks;
1165 }
1166
1167 sdhci_set_transfer_irqs(host);
1168
1169 sdhci_set_block_info(host, data);
1170}
1171
1172#if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
1173
1174static int sdhci_external_dma_init(struct sdhci_host *host)
1175{
1176 int ret = 0;
1177 struct mmc_host *mmc = host->mmc;
1178
1179 host->tx_chan = dma_request_chan(mmc_dev(mmc), "tx");
1180 if (IS_ERR(host->tx_chan)) {
1181 ret = PTR_ERR(host->tx_chan);
1182 if (ret != -EPROBE_DEFER)
1183 pr_warn("Failed to request TX DMA channel.\n");
1184 host->tx_chan = NULL;
1185 return ret;
1186 }
1187
1188 host->rx_chan = dma_request_chan(mmc_dev(mmc), "rx");
1189 if (IS_ERR(host->rx_chan)) {
1190 if (host->tx_chan) {
1191 dma_release_channel(host->tx_chan);
1192 host->tx_chan = NULL;
1193 }
1194
1195 ret = PTR_ERR(host->rx_chan);
1196 if (ret != -EPROBE_DEFER)
1197 pr_warn("Failed to request RX DMA channel.\n");
1198 host->rx_chan = NULL;
1199 }
1200
1201 return ret;
1202}
1203
1204static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1205 struct mmc_data *data)
1206{
1207 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
1208}
1209
1210static int sdhci_external_dma_setup(struct sdhci_host *host,
1211 struct mmc_command *cmd)
1212{
1213 int ret, i;
1214 enum dma_transfer_direction dir;
1215 struct dma_async_tx_descriptor *desc;
1216 struct mmc_data *data = cmd->data;
1217 struct dma_chan *chan;
1218 struct dma_slave_config cfg;
1219 dma_cookie_t cookie;
1220 int sg_cnt;
1221
1222 if (!host->mapbase)
1223 return -EINVAL;
1224
1225 memset(&cfg, 0, sizeof(cfg));
1226 cfg.src_addr = host->mapbase + SDHCI_BUFFER;
1227 cfg.dst_addr = host->mapbase + SDHCI_BUFFER;
1228 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1229 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1230 cfg.src_maxburst = data->blksz / 4;
1231 cfg.dst_maxburst = data->blksz / 4;
1232
1233 /* Sanity check: all the SG entries must be aligned by block size. */
1234 for (i = 0; i < data->sg_len; i++) {
1235 if ((data->sg + i)->length % data->blksz)
1236 return -EINVAL;
1237 }
1238
1239 chan = sdhci_external_dma_channel(host, data);
1240
1241 ret = dmaengine_slave_config(chan, &cfg);
1242 if (ret)
1243 return ret;
1244
1245 sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1246 if (sg_cnt <= 0)
1247 return -EINVAL;
1248
1249 dir = data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
1250 desc = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, dir,
1251 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1252 if (!desc)
1253 return -EINVAL;
1254
1255 desc->callback = NULL;
1256 desc->callback_param = NULL;
1257
1258 cookie = dmaengine_submit(desc);
1259 if (dma_submit_error(cookie))
1260 ret = cookie;
1261
1262 return ret;
1263}
1264
1265static void sdhci_external_dma_release(struct sdhci_host *host)
1266{
1267 if (host->tx_chan) {
1268 dma_release_channel(host->tx_chan);
1269 host->tx_chan = NULL;
1270 }
1271
1272 if (host->rx_chan) {
1273 dma_release_channel(host->rx_chan);
1274 host->rx_chan = NULL;
1275 }
1276
1277 sdhci_switch_external_dma(host, false);
1278}
1279
1280static void __sdhci_external_dma_prepare_data(struct sdhci_host *host,
1281 struct mmc_command *cmd)
1282{
1283 struct mmc_data *data = cmd->data;
1284
1285 sdhci_initialize_data(host, data);
1286
1287 host->flags |= SDHCI_REQ_USE_DMA;
1288 sdhci_set_transfer_irqs(host);
1289
1290 sdhci_set_block_info(host, data);
1291}
1292
1293static void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1294 struct mmc_command *cmd)
1295{
1296 if (!sdhci_external_dma_setup(host, cmd)) {
1297 __sdhci_external_dma_prepare_data(host, cmd);
1298 } else {
1299 sdhci_external_dma_release(host);
1300 pr_err("%s: Cannot use external DMA, switch to the DMA/PIO which standard SDHCI provides.\n",
1301 mmc_hostname(host->mmc));
1302 sdhci_prepare_data(host, cmd);
1303 }
1304}
1305
1306static void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1307 struct mmc_command *cmd)
1308{
1309 struct dma_chan *chan;
1310
1311 if (!cmd->data)
1312 return;
1313
1314 chan = sdhci_external_dma_channel(host, cmd->data);
1315 if (chan)
1316 dma_async_issue_pending(chan);
1317}
1318
1319#else
1320
1321static inline int sdhci_external_dma_init(struct sdhci_host *host)
1322{
1323 return -EOPNOTSUPP;
1324}
1325
1326static inline void sdhci_external_dma_release(struct sdhci_host *host)
1327{
1328}
1329
1330static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1331 struct mmc_command *cmd)
1332{
1333 /* This should never happen */
1334 WARN_ON_ONCE(1);
1335}
1336
1337static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1338 struct mmc_command *cmd)
1339{
1340}
1341
1342static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1343 struct mmc_data *data)
1344{
1345 return NULL;
1346}
1347
1348#endif
1349
1350void sdhci_switch_external_dma(struct sdhci_host *host, bool en)
1351{
1352 host->use_external_dma = en;
1353}
1354EXPORT_SYMBOL_GPL(sdhci_switch_external_dma);
1355
1356static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
1357 struct mmc_request *mrq)
1358{
1359 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
1360 !mrq->cap_cmd_during_tfr;
1361}
1362
1363static inline bool sdhci_auto_cmd23(struct sdhci_host *host,
1364 struct mmc_request *mrq)
1365{
1366 return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
1367}
1368
1369static inline bool sdhci_manual_cmd23(struct sdhci_host *host,
1370 struct mmc_request *mrq)
1371{
1372 return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23);
1373}
1374
1375static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
1376 struct mmc_command *cmd,
1377 u16 *mode)
1378{
1379 bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
1380 (cmd->opcode != SD_IO_RW_EXTENDED);
1381 bool use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq);
1382 u16 ctrl2;
1383
1384 /*
1385 * In case of Version 4.10 or later, use of 'Auto CMD Auto
1386 * Select' is recommended rather than use of 'Auto CMD12
1387 * Enable' or 'Auto CMD23 Enable'. We require Version 4 Mode
1388 * here because some controllers (e.g sdhci-of-dwmshc) expect it.
1389 */
1390 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1391 (use_cmd12 || use_cmd23)) {
1392 *mode |= SDHCI_TRNS_AUTO_SEL;
1393
1394 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1395 if (use_cmd23)
1396 ctrl2 |= SDHCI_CMD23_ENABLE;
1397 else
1398 ctrl2 &= ~SDHCI_CMD23_ENABLE;
1399 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
1400
1401 return;
1402 }
1403
1404 /*
1405 * If we are sending CMD23, CMD12 never gets sent
1406 * on successful completion (so no Auto-CMD12).
1407 */
1408 if (use_cmd12)
1409 *mode |= SDHCI_TRNS_AUTO_CMD12;
1410 else if (use_cmd23)
1411 *mode |= SDHCI_TRNS_AUTO_CMD23;
1412}
1413
1414static void sdhci_set_transfer_mode(struct sdhci_host *host,
1415 struct mmc_command *cmd)
1416{
1417 u16 mode = 0;
1418 struct mmc_data *data = cmd->data;
1419
1420 if (data == NULL) {
1421 if (host->quirks2 &
1422 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
1423 /* must not clear SDHCI_TRANSFER_MODE when tuning */
1424 if (cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
1425 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1426 } else {
1427 /* clear Auto CMD settings for no data CMDs */
1428 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1429 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
1430 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
1431 }
1432 return;
1433 }
1434
1435 WARN_ON(!host->data);
1436
1437 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1438 mode = SDHCI_TRNS_BLK_CNT_EN;
1439
1440 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
1441 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
1442 sdhci_auto_cmd_select(host, cmd, &mode);
1443 if (sdhci_auto_cmd23(host, cmd->mrq))
1444 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
1445 }
1446
1447 if (data->flags & MMC_DATA_READ)
1448 mode |= SDHCI_TRNS_READ;
1449 if (host->flags & SDHCI_REQ_USE_DMA)
1450 mode |= SDHCI_TRNS_DMA;
1451
1452 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1453}
1454
1455static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
1456{
1457 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1458 ((mrq->cmd && mrq->cmd->error) ||
1459 (mrq->sbc && mrq->sbc->error) ||
1460 (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
1461 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1462}
1463
1464static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq)
1465{
1466 int i;
1467
1468 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1469 if (host->mrqs_done[i] == mrq) {
1470 WARN_ON(1);
1471 return;
1472 }
1473 }
1474
1475 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1476 if (!host->mrqs_done[i]) {
1477 host->mrqs_done[i] = mrq;
1478 break;
1479 }
1480 }
1481
1482 WARN_ON(i >= SDHCI_MAX_MRQS);
1483}
1484
1485static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1486{
1487 if (host->cmd && host->cmd->mrq == mrq)
1488 host->cmd = NULL;
1489
1490 if (host->data_cmd && host->data_cmd->mrq == mrq)
1491 host->data_cmd = NULL;
1492
1493 if (host->deferred_cmd && host->deferred_cmd->mrq == mrq)
1494 host->deferred_cmd = NULL;
1495
1496 if (host->data && host->data->mrq == mrq)
1497 host->data = NULL;
1498
1499 if (sdhci_needs_reset(host, mrq))
1500 host->pending_reset = true;
1501
1502 sdhci_set_mrq_done(host, mrq);
1503
1504 sdhci_del_timer(host, mrq);
1505
1506 if (!sdhci_has_requests(host))
1507 sdhci_led_deactivate(host);
1508}
1509
1510static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1511{
1512 __sdhci_finish_mrq(host, mrq);
1513
1514 queue_work(host->complete_wq, &host->complete_work);
1515}
1516
1517static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout)
1518{
1519 struct mmc_command *data_cmd = host->data_cmd;
1520 struct mmc_data *data = host->data;
1521
1522 host->data = NULL;
1523 host->data_cmd = NULL;
1524
1525 /*
1526 * The controller needs a reset of internal state machines upon error
1527 * conditions.
1528 */
1529 if (data->error) {
1530 if (!host->cmd || host->cmd == data_cmd)
1531 sdhci_do_reset(host, SDHCI_RESET_CMD);
1532 sdhci_do_reset(host, SDHCI_RESET_DATA);
1533 }
1534
1535 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1536 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1537 sdhci_adma_table_post(host, data);
1538
1539 /*
1540 * The specification states that the block count register must
1541 * be updated, but it does not specify at what point in the
1542 * data flow. That makes the register entirely useless to read
1543 * back so we have to assume that nothing made it to the card
1544 * in the event of an error.
1545 */
1546 if (data->error)
1547 data->bytes_xfered = 0;
1548 else
1549 data->bytes_xfered = data->blksz * data->blocks;
1550
1551 /*
1552 * Need to send CMD12 if -
1553 * a) open-ended multiblock transfer not using auto CMD12 (no CMD23)
1554 * b) error in multiblock transfer
1555 */
1556 if (data->stop &&
1557 ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) ||
1558 data->error)) {
1559 /*
1560 * 'cap_cmd_during_tfr' request must not use the command line
1561 * after mmc_command_done() has been called. It is upper layer's
1562 * responsibility to send the stop command if required.
1563 */
1564 if (data->mrq->cap_cmd_during_tfr) {
1565 __sdhci_finish_mrq(host, data->mrq);
1566 } else {
1567 /* Avoid triggering warning in sdhci_send_command() */
1568 host->cmd = NULL;
1569 if (!sdhci_send_command(host, data->stop)) {
1570 if (sw_data_timeout) {
1571 /*
1572 * This is anyway a sw data timeout, so
1573 * give up now.
1574 */
1575 data->stop->error = -EIO;
1576 __sdhci_finish_mrq(host, data->mrq);
1577 } else {
1578 WARN_ON(host->deferred_cmd);
1579 host->deferred_cmd = data->stop;
1580 }
1581 }
1582 }
1583 } else {
1584 __sdhci_finish_mrq(host, data->mrq);
1585 }
1586}
1587
1588static void sdhci_finish_data(struct sdhci_host *host)
1589{
1590 __sdhci_finish_data(host, false);
1591}
1592
1593static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1594{
1595 int flags;
1596 u32 mask;
1597 unsigned long timeout;
1598
1599 WARN_ON(host->cmd);
1600
1601 /* Initially, a command has no error */
1602 cmd->error = 0;
1603
1604 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1605 cmd->opcode == MMC_STOP_TRANSMISSION)
1606 cmd->flags |= MMC_RSP_BUSY;
1607
1608 mask = SDHCI_CMD_INHIBIT;
1609 if (sdhci_data_line_cmd(cmd))
1610 mask |= SDHCI_DATA_INHIBIT;
1611
1612 /* We shouldn't wait for data inihibit for stop commands, even
1613 though they might use busy signaling */
1614 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1615 mask &= ~SDHCI_DATA_INHIBIT;
1616
1617 if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)
1618 return false;
1619
1620 host->cmd = cmd;
1621 host->data_timeout = 0;
1622 if (sdhci_data_line_cmd(cmd)) {
1623 WARN_ON(host->data_cmd);
1624 host->data_cmd = cmd;
1625 sdhci_set_timeout(host, cmd);
1626 }
1627
1628 if (cmd->data) {
1629 if (host->use_external_dma)
1630 sdhci_external_dma_prepare_data(host, cmd);
1631 else
1632 sdhci_prepare_data(host, cmd);
1633 }
1634
1635 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1636
1637 sdhci_set_transfer_mode(host, cmd);
1638
1639 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1640 WARN_ONCE(1, "Unsupported response type!\n");
1641 /*
1642 * This does not happen in practice because 136-bit response
1643 * commands never have busy waiting, so rather than complicate
1644 * the error path, just remove busy waiting and continue.
1645 */
1646 cmd->flags &= ~MMC_RSP_BUSY;
1647 }
1648
1649 if (!(cmd->flags & MMC_RSP_PRESENT))
1650 flags = SDHCI_CMD_RESP_NONE;
1651 else if (cmd->flags & MMC_RSP_136)
1652 flags = SDHCI_CMD_RESP_LONG;
1653 else if (cmd->flags & MMC_RSP_BUSY)
1654 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1655 else
1656 flags = SDHCI_CMD_RESP_SHORT;
1657
1658 if (cmd->flags & MMC_RSP_CRC)
1659 flags |= SDHCI_CMD_CRC;
1660 if (cmd->flags & MMC_RSP_OPCODE)
1661 flags |= SDHCI_CMD_INDEX;
1662
1663 /* CMD19 is special in that the Data Present Select should be set */
1664 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1665 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1666 flags |= SDHCI_CMD_DATA;
1667
1668 timeout = jiffies;
1669 if (host->data_timeout)
1670 timeout += nsecs_to_jiffies(host->data_timeout);
1671 else if (!cmd->data && cmd->busy_timeout > 9000)
1672 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1673 else
1674 timeout += 10 * HZ;
1675 sdhci_mod_timer(host, cmd->mrq, timeout);
1676
1677 if (host->use_external_dma)
1678 sdhci_external_dma_pre_transfer(host, cmd);
1679
1680 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1681
1682 return true;
1683}
1684
1685static bool sdhci_present_error(struct sdhci_host *host,
1686 struct mmc_command *cmd, bool present)
1687{
1688 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1689 cmd->error = -ENOMEDIUM;
1690 return true;
1691 }
1692
1693 return false;
1694}
1695
1696static bool sdhci_send_command_retry(struct sdhci_host *host,
1697 struct mmc_command *cmd,
1698 unsigned long flags)
1699 __releases(host->lock)
1700 __acquires(host->lock)
1701{
1702 struct mmc_command *deferred_cmd = host->deferred_cmd;
1703 int timeout = 10; /* Approx. 10 ms */
1704 bool present;
1705
1706 while (!sdhci_send_command(host, cmd)) {
1707 if (!timeout--) {
1708 pr_err("%s: Controller never released inhibit bit(s).\n",
1709 mmc_hostname(host->mmc));
1710 sdhci_dumpregs(host);
1711 cmd->error = -EIO;
1712 return false;
1713 }
1714
1715 spin_unlock_irqrestore(&host->lock, flags);
1716
1717 usleep_range(1000, 1250);
1718
1719 present = host->mmc->ops->get_cd(host->mmc);
1720
1721 spin_lock_irqsave(&host->lock, flags);
1722
1723 /* A deferred command might disappear, handle that */
1724 if (cmd == deferred_cmd && cmd != host->deferred_cmd)
1725 return true;
1726
1727 if (sdhci_present_error(host, cmd, present))
1728 return false;
1729 }
1730
1731 if (cmd == host->deferred_cmd)
1732 host->deferred_cmd = NULL;
1733
1734 return true;
1735}
1736
1737static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1738{
1739 int i, reg;
1740
1741 for (i = 0; i < 4; i++) {
1742 reg = SDHCI_RESPONSE + (3 - i) * 4;
1743 cmd->resp[i] = sdhci_readl(host, reg);
1744 }
1745
1746 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1747 return;
1748
1749 /* CRC is stripped so we need to do some shifting */
1750 for (i = 0; i < 4; i++) {
1751 cmd->resp[i] <<= 8;
1752 if (i != 3)
1753 cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1754 }
1755}
1756
1757static void sdhci_finish_command(struct sdhci_host *host)
1758{
1759 struct mmc_command *cmd = host->cmd;
1760
1761 host->cmd = NULL;
1762
1763 if (cmd->flags & MMC_RSP_PRESENT) {
1764 if (cmd->flags & MMC_RSP_136) {
1765 sdhci_read_rsp_136(host, cmd);
1766 } else {
1767 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1768 }
1769 }
1770
1771 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1772 mmc_command_done(host->mmc, cmd->mrq);
1773
1774 /*
1775 * The host can send and interrupt when the busy state has
1776 * ended, allowing us to wait without wasting CPU cycles.
1777 * The busy signal uses DAT0 so this is similar to waiting
1778 * for data to complete.
1779 *
1780 * Note: The 1.0 specification is a bit ambiguous about this
1781 * feature so there might be some problems with older
1782 * controllers.
1783 */
1784 if (cmd->flags & MMC_RSP_BUSY) {
1785 if (cmd->data) {
1786 DBG("Cannot wait for busy signal when also doing a data transfer");
1787 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1788 cmd == host->data_cmd) {
1789 /* Command complete before busy is ended */
1790 return;
1791 }
1792 }
1793
1794 /* Finished CMD23, now send actual command. */
1795 if (cmd == cmd->mrq->sbc) {
1796 if (!sdhci_send_command(host, cmd->mrq->cmd)) {
1797 WARN_ON(host->deferred_cmd);
1798 host->deferred_cmd = cmd->mrq->cmd;
1799 }
1800 } else {
1801
1802 /* Processed actual command. */
1803 if (host->data && host->data_early)
1804 sdhci_finish_data(host);
1805
1806 if (!cmd->data)
1807 __sdhci_finish_mrq(host, cmd->mrq);
1808 }
1809}
1810
1811static u16 sdhci_get_preset_value(struct sdhci_host *host)
1812{
1813 u16 preset = 0;
1814
1815 switch (host->timing) {
1816 case MMC_TIMING_MMC_HS:
1817 case MMC_TIMING_SD_HS:
1818 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HIGH_SPEED);
1819 break;
1820 case MMC_TIMING_UHS_SDR12:
1821 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1822 break;
1823 case MMC_TIMING_UHS_SDR25:
1824 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1825 break;
1826 case MMC_TIMING_UHS_SDR50:
1827 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1828 break;
1829 case MMC_TIMING_UHS_SDR104:
1830 case MMC_TIMING_MMC_HS200:
1831 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1832 break;
1833 case MMC_TIMING_UHS_DDR50:
1834 case MMC_TIMING_MMC_DDR52:
1835 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1836 break;
1837 case MMC_TIMING_MMC_HS400:
1838 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1839 break;
1840 default:
1841 pr_warn("%s: Invalid UHS-I mode selected\n",
1842 mmc_hostname(host->mmc));
1843 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1844 break;
1845 }
1846 return preset;
1847}
1848
1849u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1850 unsigned int *actual_clock)
1851{
1852 int div = 0; /* Initialized for compiler warning */
1853 int real_div = div, clk_mul = 1;
1854 u16 clk = 0;
1855 bool switch_base_clk = false;
1856
1857 if (host->version >= SDHCI_SPEC_300) {
1858 if (host->preset_enabled) {
1859 u16 pre_val;
1860
1861 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1862 pre_val = sdhci_get_preset_value(host);
1863 div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
1864 if (host->clk_mul &&
1865 (pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
1866 clk = SDHCI_PROG_CLOCK_MODE;
1867 real_div = div + 1;
1868 clk_mul = host->clk_mul;
1869 } else {
1870 real_div = max_t(int, 1, div << 1);
1871 }
1872 goto clock_set;
1873 }
1874
1875 /*
1876 * Check if the Host Controller supports Programmable Clock
1877 * Mode.
1878 */
1879 if (host->clk_mul) {
1880 for (div = 1; div <= 1024; div++) {
1881 if ((host->max_clk * host->clk_mul / div)
1882 <= clock)
1883 break;
1884 }
1885 if ((host->max_clk * host->clk_mul / div) <= clock) {
1886 /*
1887 * Set Programmable Clock Mode in the Clock
1888 * Control register.
1889 */
1890 clk = SDHCI_PROG_CLOCK_MODE;
1891 real_div = div;
1892 clk_mul = host->clk_mul;
1893 div--;
1894 } else {
1895 /*
1896 * Divisor can be too small to reach clock
1897 * speed requirement. Then use the base clock.
1898 */
1899 switch_base_clk = true;
1900 }
1901 }
1902
1903 if (!host->clk_mul || switch_base_clk) {
1904 /* Version 3.00 divisors must be a multiple of 2. */
1905 if (host->max_clk <= clock)
1906 div = 1;
1907 else {
1908 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1909 div += 2) {
1910 if ((host->max_clk / div) <= clock)
1911 break;
1912 }
1913 }
1914 real_div = div;
1915 div >>= 1;
1916 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1917 && !div && host->max_clk <= 25000000)
1918 div = 1;
1919 }
1920 } else {
1921 /* Version 2.00 divisors must be a power of 2. */
1922 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1923 if ((host->max_clk / div) <= clock)
1924 break;
1925 }
1926 real_div = div;
1927 div >>= 1;
1928 }
1929
1930clock_set:
1931 if (real_div)
1932 *actual_clock = (host->max_clk * clk_mul) / real_div;
1933 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1934 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1935 << SDHCI_DIVIDER_HI_SHIFT;
1936
1937 return clk;
1938}
1939EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1940
1941void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1942{
1943 ktime_t timeout;
1944
1945 clk |= SDHCI_CLOCK_INT_EN;
1946 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1947
1948 /* Wait max 150 ms */
1949 timeout = ktime_add_ms(ktime_get(), 150);
1950 while (1) {
1951 bool timedout = ktime_after(ktime_get(), timeout);
1952
1953 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1954 if (clk & SDHCI_CLOCK_INT_STABLE)
1955 break;
1956 if (timedout) {
1957 pr_err("%s: Internal clock never stabilised.\n",
1958 mmc_hostname(host->mmc));
1959 sdhci_dumpregs(host);
1960 return;
1961 }
1962 udelay(10);
1963 }
1964
1965 if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
1966 clk |= SDHCI_CLOCK_PLL_EN;
1967 clk &= ~SDHCI_CLOCK_INT_STABLE;
1968 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1969
1970 /* Wait max 150 ms */
1971 timeout = ktime_add_ms(ktime_get(), 150);
1972 while (1) {
1973 bool timedout = ktime_after(ktime_get(), timeout);
1974
1975 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1976 if (clk & SDHCI_CLOCK_INT_STABLE)
1977 break;
1978 if (timedout) {
1979 pr_err("%s: PLL clock never stabilised.\n",
1980 mmc_hostname(host->mmc));
1981 sdhci_dumpregs(host);
1982 return;
1983 }
1984 udelay(10);
1985 }
1986 }
1987
1988 clk |= SDHCI_CLOCK_CARD_EN;
1989 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1990}
1991EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1992
1993void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1994{
1995 u16 clk;
1996
1997 host->mmc->actual_clock = 0;
1998
1999 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
2000
2001 if (clock == 0)
2002 return;
2003
2004 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
2005 sdhci_enable_clk(host, clk);
2006}
2007EXPORT_SYMBOL_GPL(sdhci_set_clock);
2008
2009static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
2010 unsigned short vdd)
2011{
2012 struct mmc_host *mmc = host->mmc;
2013
2014 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2015
2016 if (mode != MMC_POWER_OFF)
2017 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
2018 else
2019 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2020}
2021
2022void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
2023 unsigned short vdd)
2024{
2025 u8 pwr = 0;
2026
2027 if (mode != MMC_POWER_OFF) {
2028 switch (1 << vdd) {
2029 case MMC_VDD_165_195:
2030 /*
2031 * Without a regulator, SDHCI does not support 2.0v
2032 * so we only get here if the driver deliberately
2033 * added the 2.0v range to ocr_avail. Map it to 1.8v
2034 * for the purpose of turning on the power.
2035 */
2036 case MMC_VDD_20_21:
2037 pwr = SDHCI_POWER_180;
2038 break;
2039 case MMC_VDD_29_30:
2040 case MMC_VDD_30_31:
2041 pwr = SDHCI_POWER_300;
2042 break;
2043 case MMC_VDD_32_33:
2044 case MMC_VDD_33_34:
2045 pwr = SDHCI_POWER_330;
2046 break;
2047 default:
2048 WARN(1, "%s: Invalid vdd %#x\n",
2049 mmc_hostname(host->mmc), vdd);
2050 break;
2051 }
2052 }
2053
2054 if (host->pwr == pwr)
2055 return;
2056
2057 host->pwr = pwr;
2058
2059 if (pwr == 0) {
2060 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2061 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2062 sdhci_runtime_pm_bus_off(host);
2063 } else {
2064 /*
2065 * Spec says that we should clear the power reg before setting
2066 * a new value. Some controllers don't seem to like this though.
2067 */
2068 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
2069 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2070
2071 /*
2072 * At least the Marvell CaFe chip gets confused if we set the
2073 * voltage and set turn on power at the same time, so set the
2074 * voltage first.
2075 */
2076 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
2077 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2078
2079 pwr |= SDHCI_POWER_ON;
2080
2081 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2082
2083 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2084 sdhci_runtime_pm_bus_on(host);
2085
2086 /*
2087 * Some controllers need an extra 10ms delay of 10ms before
2088 * they can apply clock after applying power
2089 */
2090 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
2091 mdelay(10);
2092 }
2093}
2094EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
2095
2096void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
2097 unsigned short vdd)
2098{
2099 if (IS_ERR(host->mmc->supply.vmmc))
2100 sdhci_set_power_noreg(host, mode, vdd);
2101 else
2102 sdhci_set_power_reg(host, mode, vdd);
2103}
2104EXPORT_SYMBOL_GPL(sdhci_set_power);
2105
2106/*
2107 * Some controllers need to configure a valid bus voltage on their power
2108 * register regardless of whether an external regulator is taking care of power
2109 * supply. This helper function takes care of it if set as the controller's
2110 * sdhci_ops.set_power callback.
2111 */
2112void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
2113 unsigned char mode,
2114 unsigned short vdd)
2115{
2116 if (!IS_ERR(host->mmc->supply.vmmc)) {
2117 struct mmc_host *mmc = host->mmc;
2118
2119 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2120 }
2121 sdhci_set_power_noreg(host, mode, vdd);
2122}
2123EXPORT_SYMBOL_GPL(sdhci_set_power_and_bus_voltage);
2124
2125/*****************************************************************************\
2126 * *
2127 * MMC callbacks *
2128 * *
2129\*****************************************************************************/
2130
2131void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
2132{
2133 struct sdhci_host *host = mmc_priv(mmc);
2134 struct mmc_command *cmd;
2135 unsigned long flags;
2136 bool present;
2137
2138 /* Firstly check card presence */
2139 present = mmc->ops->get_cd(mmc);
2140
2141 spin_lock_irqsave(&host->lock, flags);
2142
2143 sdhci_led_activate(host);
2144
2145 if (sdhci_present_error(host, mrq->cmd, present))
2146 goto out_finish;
2147
2148 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2149
2150 if (!sdhci_send_command_retry(host, cmd, flags))
2151 goto out_finish;
2152
2153 spin_unlock_irqrestore(&host->lock, flags);
2154
2155 return;
2156
2157out_finish:
2158 sdhci_finish_mrq(host, mrq);
2159 spin_unlock_irqrestore(&host->lock, flags);
2160}
2161EXPORT_SYMBOL_GPL(sdhci_request);
2162
2163int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq)
2164{
2165 struct sdhci_host *host = mmc_priv(mmc);
2166 struct mmc_command *cmd;
2167 unsigned long flags;
2168 int ret = 0;
2169
2170 spin_lock_irqsave(&host->lock, flags);
2171
2172 if (sdhci_present_error(host, mrq->cmd, true)) {
2173 sdhci_finish_mrq(host, mrq);
2174 goto out_finish;
2175 }
2176
2177 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2178
2179 /*
2180 * The HSQ may send a command in interrupt context without polling
2181 * the busy signaling, which means we should return BUSY if controller
2182 * has not released inhibit bits to allow HSQ trying to send request
2183 * again in non-atomic context. So we should not finish this request
2184 * here.
2185 */
2186 if (!sdhci_send_command(host, cmd))
2187 ret = -EBUSY;
2188 else
2189 sdhci_led_activate(host);
2190
2191out_finish:
2192 spin_unlock_irqrestore(&host->lock, flags);
2193 return ret;
2194}
2195EXPORT_SYMBOL_GPL(sdhci_request_atomic);
2196
2197void sdhci_set_bus_width(struct sdhci_host *host, int width)
2198{
2199 u8 ctrl;
2200
2201 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2202 if (width == MMC_BUS_WIDTH_8) {
2203 ctrl &= ~SDHCI_CTRL_4BITBUS;
2204 ctrl |= SDHCI_CTRL_8BITBUS;
2205 } else {
2206 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
2207 ctrl &= ~SDHCI_CTRL_8BITBUS;
2208 if (width == MMC_BUS_WIDTH_4)
2209 ctrl |= SDHCI_CTRL_4BITBUS;
2210 else
2211 ctrl &= ~SDHCI_CTRL_4BITBUS;
2212 }
2213 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2214}
2215EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
2216
2217void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
2218{
2219 u16 ctrl_2;
2220
2221 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2222 /* Select Bus Speed Mode for host */
2223 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
2224 if ((timing == MMC_TIMING_MMC_HS200) ||
2225 (timing == MMC_TIMING_UHS_SDR104))
2226 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
2227 else if (timing == MMC_TIMING_UHS_SDR12)
2228 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
2229 else if (timing == MMC_TIMING_UHS_SDR25)
2230 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
2231 else if (timing == MMC_TIMING_UHS_SDR50)
2232 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
2233 else if ((timing == MMC_TIMING_UHS_DDR50) ||
2234 (timing == MMC_TIMING_MMC_DDR52))
2235 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
2236 else if (timing == MMC_TIMING_MMC_HS400)
2237 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
2238 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2239}
2240EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
2241
2242void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2243{
2244 struct sdhci_host *host = mmc_priv(mmc);
2245 u8 ctrl;
2246
2247 if (ios->power_mode == MMC_POWER_UNDEFINED)
2248 return;
2249
2250 if (host->flags & SDHCI_DEVICE_DEAD) {
2251 if (!IS_ERR(mmc->supply.vmmc) &&
2252 ios->power_mode == MMC_POWER_OFF)
2253 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
2254 return;
2255 }
2256
2257 /*
2258 * Reset the chip on each power off.
2259 * Should clear out any weird states.
2260 */
2261 if (ios->power_mode == MMC_POWER_OFF) {
2262 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2263 sdhci_reinit(host);
2264 }
2265
2266 if (host->version >= SDHCI_SPEC_300 &&
2267 (ios->power_mode == MMC_POWER_UP) &&
2268 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
2269 sdhci_enable_preset_value(host, false);
2270
2271 if (!ios->clock || ios->clock != host->clock) {
2272 host->ops->set_clock(host, ios->clock);
2273 host->clock = ios->clock;
2274
2275 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
2276 host->clock) {
2277 host->timeout_clk = mmc->actual_clock ?
2278 mmc->actual_clock / 1000 :
2279 host->clock / 1000;
2280 mmc->max_busy_timeout =
2281 host->ops->get_max_timeout_count ?
2282 host->ops->get_max_timeout_count(host) :
2283 1 << 27;
2284 mmc->max_busy_timeout /= host->timeout_clk;
2285 }
2286 }
2287
2288 if (host->ops->set_power)
2289 host->ops->set_power(host, ios->power_mode, ios->vdd);
2290 else
2291 sdhci_set_power(host, ios->power_mode, ios->vdd);
2292
2293 if (host->ops->platform_send_init_74_clocks)
2294 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
2295
2296 host->ops->set_bus_width(host, ios->bus_width);
2297
2298 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2299
2300 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
2301 if (ios->timing == MMC_TIMING_SD_HS ||
2302 ios->timing == MMC_TIMING_MMC_HS ||
2303 ios->timing == MMC_TIMING_MMC_HS400 ||
2304 ios->timing == MMC_TIMING_MMC_HS200 ||
2305 ios->timing == MMC_TIMING_MMC_DDR52 ||
2306 ios->timing == MMC_TIMING_UHS_SDR50 ||
2307 ios->timing == MMC_TIMING_UHS_SDR104 ||
2308 ios->timing == MMC_TIMING_UHS_DDR50 ||
2309 ios->timing == MMC_TIMING_UHS_SDR25)
2310 ctrl |= SDHCI_CTRL_HISPD;
2311 else
2312 ctrl &= ~SDHCI_CTRL_HISPD;
2313 }
2314
2315 if (host->version >= SDHCI_SPEC_300) {
2316 u16 clk, ctrl_2;
2317
2318 if (!host->preset_enabled) {
2319 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2320 /*
2321 * We only need to set Driver Strength if the
2322 * preset value enable is not set.
2323 */
2324 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2325 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
2326 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
2327 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
2328 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
2329 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2330 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
2331 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
2332 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
2333 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
2334 else {
2335 pr_warn("%s: invalid driver type, default to driver type B\n",
2336 mmc_hostname(mmc));
2337 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2338 }
2339
2340 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2341 } else {
2342 /*
2343 * According to SDHC Spec v3.00, if the Preset Value
2344 * Enable in the Host Control 2 register is set, we
2345 * need to reset SD Clock Enable before changing High
2346 * Speed Enable to avoid generating clock gliches.
2347 */
2348
2349 /* Reset SD Clock Enable */
2350 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2351 clk &= ~SDHCI_CLOCK_CARD_EN;
2352 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2353
2354 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2355
2356 /* Re-enable SD Clock */
2357 host->ops->set_clock(host, host->clock);
2358 }
2359
2360 /* Reset SD Clock Enable */
2361 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2362 clk &= ~SDHCI_CLOCK_CARD_EN;
2363 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2364
2365 host->ops->set_uhs_signaling(host, ios->timing);
2366 host->timing = ios->timing;
2367
2368 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
2369 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
2370 (ios->timing == MMC_TIMING_UHS_SDR25) ||
2371 (ios->timing == MMC_TIMING_UHS_SDR50) ||
2372 (ios->timing == MMC_TIMING_UHS_SDR104) ||
2373 (ios->timing == MMC_TIMING_UHS_DDR50) ||
2374 (ios->timing == MMC_TIMING_MMC_DDR52))) {
2375 u16 preset;
2376
2377 sdhci_enable_preset_value(host, true);
2378 preset = sdhci_get_preset_value(host);
2379 ios->drv_type = FIELD_GET(SDHCI_PRESET_DRV_MASK,
2380 preset);
2381 }
2382
2383 /* Re-enable SD Clock */
2384 host->ops->set_clock(host, host->clock);
2385 } else
2386 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2387
2388 /*
2389 * Some (ENE) controllers go apeshit on some ios operation,
2390 * signalling timeout and CRC errors even on CMD0. Resetting
2391 * it on each ios seems to solve the problem.
2392 */
2393 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
2394 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
2395}
2396EXPORT_SYMBOL_GPL(sdhci_set_ios);
2397
2398static int sdhci_get_cd(struct mmc_host *mmc)
2399{
2400 struct sdhci_host *host = mmc_priv(mmc);
2401 int gpio_cd = mmc_gpio_get_cd(mmc);
2402
2403 if (host->flags & SDHCI_DEVICE_DEAD)
2404 return 0;
2405
2406 /* If nonremovable, assume that the card is always present. */
2407 if (!mmc_card_is_removable(mmc))
2408 return 1;
2409
2410 /*
2411 * Try slot gpio detect, if defined it take precedence
2412 * over build in controller functionality
2413 */
2414 if (gpio_cd >= 0)
2415 return !!gpio_cd;
2416
2417 /* If polling, assume that the card is always present. */
2418 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2419 return 1;
2420
2421 /* Host native card detect */
2422 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2423}
2424
2425static int sdhci_check_ro(struct sdhci_host *host)
2426{
2427 unsigned long flags;
2428 int is_readonly;
2429
2430 spin_lock_irqsave(&host->lock, flags);
2431
2432 if (host->flags & SDHCI_DEVICE_DEAD)
2433 is_readonly = 0;
2434 else if (host->ops->get_ro)
2435 is_readonly = host->ops->get_ro(host);
2436 else if (mmc_can_gpio_ro(host->mmc))
2437 is_readonly = mmc_gpio_get_ro(host->mmc);
2438 else
2439 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2440 & SDHCI_WRITE_PROTECT);
2441
2442 spin_unlock_irqrestore(&host->lock, flags);
2443
2444 /* This quirk needs to be replaced by a callback-function later */
2445 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
2446 !is_readonly : is_readonly;
2447}
2448
2449#define SAMPLE_COUNT 5
2450
2451static int sdhci_get_ro(struct mmc_host *mmc)
2452{
2453 struct sdhci_host *host = mmc_priv(mmc);
2454 int i, ro_count;
2455
2456 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
2457 return sdhci_check_ro(host);
2458
2459 ro_count = 0;
2460 for (i = 0; i < SAMPLE_COUNT; i++) {
2461 if (sdhci_check_ro(host)) {
2462 if (++ro_count > SAMPLE_COUNT / 2)
2463 return 1;
2464 }
2465 msleep(30);
2466 }
2467 return 0;
2468}
2469
2470static void sdhci_hw_reset(struct mmc_host *mmc)
2471{
2472 struct sdhci_host *host = mmc_priv(mmc);
2473
2474 if (host->ops && host->ops->hw_reset)
2475 host->ops->hw_reset(host);
2476}
2477
2478static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2479{
2480 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
2481 if (enable)
2482 host->ier |= SDHCI_INT_CARD_INT;
2483 else
2484 host->ier &= ~SDHCI_INT_CARD_INT;
2485
2486 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2487 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2488 }
2489}
2490
2491void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
2492{
2493 struct sdhci_host *host = mmc_priv(mmc);
2494 unsigned long flags;
2495
2496 if (enable)
2497 pm_runtime_get_noresume(mmc_dev(mmc));
2498
2499 spin_lock_irqsave(&host->lock, flags);
2500 sdhci_enable_sdio_irq_nolock(host, enable);
2501 spin_unlock_irqrestore(&host->lock, flags);
2502
2503 if (!enable)
2504 pm_runtime_put_noidle(mmc_dev(mmc));
2505}
2506EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
2507
2508static void sdhci_ack_sdio_irq(struct mmc_host *mmc)
2509{
2510 struct sdhci_host *host = mmc_priv(mmc);
2511 unsigned long flags;
2512
2513 spin_lock_irqsave(&host->lock, flags);
2514 sdhci_enable_sdio_irq_nolock(host, true);
2515 spin_unlock_irqrestore(&host->lock, flags);
2516}
2517
2518int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2519 struct mmc_ios *ios)
2520{
2521 struct sdhci_host *host = mmc_priv(mmc);
2522 u16 ctrl;
2523 int ret;
2524
2525 /*
2526 * Signal Voltage Switching is only applicable for Host Controllers
2527 * v3.00 and above.
2528 */
2529 if (host->version < SDHCI_SPEC_300)
2530 return 0;
2531
2532 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2533
2534 switch (ios->signal_voltage) {
2535 case MMC_SIGNAL_VOLTAGE_330:
2536 if (!(host->flags & SDHCI_SIGNALING_330))
2537 return -EINVAL;
2538 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2539 ctrl &= ~SDHCI_CTRL_VDD_180;
2540 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2541
2542 if (!IS_ERR(mmc->supply.vqmmc)) {
2543 ret = mmc_regulator_set_vqmmc(mmc, ios);
2544 if (ret < 0) {
2545 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
2546 mmc_hostname(mmc));
2547 return -EIO;
2548 }
2549 }
2550 /* Wait for 5ms */
2551 usleep_range(5000, 5500);
2552
2553 /* 3.3V regulator output should be stable within 5 ms */
2554 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2555 if (!(ctrl & SDHCI_CTRL_VDD_180))
2556 return 0;
2557
2558 pr_warn("%s: 3.3V regulator output did not become stable\n",
2559 mmc_hostname(mmc));
2560
2561 return -EAGAIN;
2562 case MMC_SIGNAL_VOLTAGE_180:
2563 if (!(host->flags & SDHCI_SIGNALING_180))
2564 return -EINVAL;
2565 if (!IS_ERR(mmc->supply.vqmmc)) {
2566 ret = mmc_regulator_set_vqmmc(mmc, ios);
2567 if (ret < 0) {
2568 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
2569 mmc_hostname(mmc));
2570 return -EIO;
2571 }
2572 }
2573
2574 /*
2575 * Enable 1.8V Signal Enable in the Host Control2
2576 * register
2577 */
2578 ctrl |= SDHCI_CTRL_VDD_180;
2579 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2580
2581 /* Some controller need to do more when switching */
2582 if (host->ops->voltage_switch)
2583 host->ops->voltage_switch(host);
2584
2585 /* 1.8V regulator output should be stable within 5 ms */
2586 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2587 if (ctrl & SDHCI_CTRL_VDD_180)
2588 return 0;
2589
2590 pr_warn("%s: 1.8V regulator output did not become stable\n",
2591 mmc_hostname(mmc));
2592
2593 return -EAGAIN;
2594 case MMC_SIGNAL_VOLTAGE_120:
2595 if (!(host->flags & SDHCI_SIGNALING_120))
2596 return -EINVAL;
2597 if (!IS_ERR(mmc->supply.vqmmc)) {
2598 ret = mmc_regulator_set_vqmmc(mmc, ios);
2599 if (ret < 0) {
2600 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
2601 mmc_hostname(mmc));
2602 return -EIO;
2603 }
2604 }
2605 return 0;
2606 default:
2607 /* No signal voltage switch required */
2608 return 0;
2609 }
2610}
2611EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2612
2613static int sdhci_card_busy(struct mmc_host *mmc)
2614{
2615 struct sdhci_host *host = mmc_priv(mmc);
2616 u32 present_state;
2617
2618 /* Check whether DAT[0] is 0 */
2619 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2620
2621 return !(present_state & SDHCI_DATA_0_LVL_MASK);
2622}
2623
2624static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2625{
2626 struct sdhci_host *host = mmc_priv(mmc);
2627 unsigned long flags;
2628
2629 spin_lock_irqsave(&host->lock, flags);
2630 host->flags |= SDHCI_HS400_TUNING;
2631 spin_unlock_irqrestore(&host->lock, flags);
2632
2633 return 0;
2634}
2635
2636void sdhci_start_tuning(struct sdhci_host *host)
2637{
2638 u16 ctrl;
2639
2640 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2641 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2642 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2643 ctrl |= SDHCI_CTRL_TUNED_CLK;
2644 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2645
2646 /*
2647 * As per the Host Controller spec v3.00, tuning command
2648 * generates Buffer Read Ready interrupt, so enable that.
2649 *
2650 * Note: The spec clearly says that when tuning sequence
2651 * is being performed, the controller does not generate
2652 * interrupts other than Buffer Read Ready interrupt. But
2653 * to make sure we don't hit a controller bug, we _only_
2654 * enable Buffer Read Ready interrupt here.
2655 */
2656 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2657 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2658}
2659EXPORT_SYMBOL_GPL(sdhci_start_tuning);
2660
2661void sdhci_end_tuning(struct sdhci_host *host)
2662{
2663 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2664 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2665}
2666EXPORT_SYMBOL_GPL(sdhci_end_tuning);
2667
2668void sdhci_reset_tuning(struct sdhci_host *host)
2669{
2670 u16 ctrl;
2671
2672 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2673 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2674 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2675 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2676}
2677EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
2678
2679void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2680{
2681 sdhci_reset_tuning(host);
2682
2683 sdhci_do_reset(host, SDHCI_RESET_CMD);
2684 sdhci_do_reset(host, SDHCI_RESET_DATA);
2685
2686 sdhci_end_tuning(host);
2687
2688 mmc_send_abort_tuning(host->mmc, opcode);
2689}
2690EXPORT_SYMBOL_GPL(sdhci_abort_tuning);
2691
2692/*
2693 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2694 * tuning command does not have a data payload (or rather the hardware does it
2695 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2696 * interrupt setup is different to other commands and there is no timeout
2697 * interrupt so special handling is needed.
2698 */
2699void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2700{
2701 struct mmc_host *mmc = host->mmc;
2702 struct mmc_command cmd = {};
2703 struct mmc_request mrq = {};
2704 unsigned long flags;
2705 u32 b = host->sdma_boundary;
2706
2707 spin_lock_irqsave(&host->lock, flags);
2708
2709 cmd.opcode = opcode;
2710 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2711 cmd.mrq = &mrq;
2712
2713 mrq.cmd = &cmd;
2714 /*
2715 * In response to CMD19, the card sends 64 bytes of tuning
2716 * block to the Host Controller. So we set the block size
2717 * to 64 here.
2718 */
2719 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2720 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2721 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2722 else
2723 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2724
2725 /*
2726 * The tuning block is sent by the card to the host controller.
2727 * So we set the TRNS_READ bit in the Transfer Mode register.
2728 * This also takes care of setting DMA Enable and Multi Block
2729 * Select in the same register to 0.
2730 */
2731 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2732
2733 if (!sdhci_send_command_retry(host, &cmd, flags)) {
2734 spin_unlock_irqrestore(&host->lock, flags);
2735 host->tuning_done = 0;
2736 return;
2737 }
2738
2739 host->cmd = NULL;
2740
2741 sdhci_del_timer(host, &mrq);
2742
2743 host->tuning_done = 0;
2744
2745 spin_unlock_irqrestore(&host->lock, flags);
2746
2747 /* Wait for Buffer Read Ready interrupt */
2748 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2749 msecs_to_jiffies(50));
2750
2751}
2752EXPORT_SYMBOL_GPL(sdhci_send_tuning);
2753
2754static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2755{
2756 int i;
2757
2758 /*
2759 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2760 * of loops reaches tuning loop count.
2761 */
2762 for (i = 0; i < host->tuning_loop_count; i++) {
2763 u16 ctrl;
2764
2765 sdhci_send_tuning(host, opcode);
2766
2767 if (!host->tuning_done) {
2768 pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
2769 mmc_hostname(host->mmc));
2770 sdhci_abort_tuning(host, opcode);
2771 return -ETIMEDOUT;
2772 }
2773
2774 /* Spec does not require a delay between tuning cycles */
2775 if (host->tuning_delay > 0)
2776 mdelay(host->tuning_delay);
2777
2778 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2779 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2780 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2781 return 0; /* Success! */
2782 break;
2783 }
2784
2785 }
2786
2787 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2788 mmc_hostname(host->mmc));
2789 sdhci_reset_tuning(host);
2790 return -EAGAIN;
2791}
2792
2793int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2794{
2795 struct sdhci_host *host = mmc_priv(mmc);
2796 int err = 0;
2797 unsigned int tuning_count = 0;
2798 bool hs400_tuning;
2799
2800 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2801
2802 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2803 tuning_count = host->tuning_count;
2804
2805 /*
2806 * The Host Controller needs tuning in case of SDR104 and DDR50
2807 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2808 * the Capabilities register.
2809 * If the Host Controller supports the HS200 mode then the
2810 * tuning function has to be executed.
2811 */
2812 switch (host->timing) {
2813 /* HS400 tuning is done in HS200 mode */
2814 case MMC_TIMING_MMC_HS400:
2815 err = -EINVAL;
2816 goto out;
2817
2818 case MMC_TIMING_MMC_HS200:
2819 /*
2820 * Periodic re-tuning for HS400 is not expected to be needed, so
2821 * disable it here.
2822 */
2823 if (hs400_tuning)
2824 tuning_count = 0;
2825 break;
2826
2827 case MMC_TIMING_UHS_SDR104:
2828 case MMC_TIMING_UHS_DDR50:
2829 break;
2830
2831 case MMC_TIMING_UHS_SDR50:
2832 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2833 break;
2834 fallthrough;
2835
2836 default:
2837 goto out;
2838 }
2839
2840 if (host->ops->platform_execute_tuning) {
2841 err = host->ops->platform_execute_tuning(host, opcode);
2842 goto out;
2843 }
2844
2845 mmc->retune_period = tuning_count;
2846
2847 if (host->tuning_delay < 0)
2848 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2849
2850 sdhci_start_tuning(host);
2851
2852 host->tuning_err = __sdhci_execute_tuning(host, opcode);
2853
2854 sdhci_end_tuning(host);
2855out:
2856 host->flags &= ~SDHCI_HS400_TUNING;
2857
2858 return err;
2859}
2860EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2861
2862static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2863{
2864 /* Host Controller v3.00 defines preset value registers */
2865 if (host->version < SDHCI_SPEC_300)
2866 return;
2867
2868 /*
2869 * We only enable or disable Preset Value if they are not already
2870 * enabled or disabled respectively. Otherwise, we bail out.
2871 */
2872 if (host->preset_enabled != enable) {
2873 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2874
2875 if (enable)
2876 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2877 else
2878 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2879
2880 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2881
2882 if (enable)
2883 host->flags |= SDHCI_PV_ENABLED;
2884 else
2885 host->flags &= ~SDHCI_PV_ENABLED;
2886
2887 host->preset_enabled = enable;
2888 }
2889}
2890
2891static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2892 int err)
2893{
2894 struct mmc_data *data = mrq->data;
2895
2896 if (data->host_cookie != COOKIE_UNMAPPED)
2897 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
2898 mmc_get_dma_dir(data));
2899
2900 data->host_cookie = COOKIE_UNMAPPED;
2901}
2902
2903static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2904{
2905 struct sdhci_host *host = mmc_priv(mmc);
2906
2907 mrq->data->host_cookie = COOKIE_UNMAPPED;
2908
2909 /*
2910 * No pre-mapping in the pre hook if we're using the bounce buffer,
2911 * for that we would need two bounce buffers since one buffer is
2912 * in flight when this is getting called.
2913 */
2914 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
2915 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2916}
2917
2918static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2919{
2920 if (host->data_cmd) {
2921 host->data_cmd->error = err;
2922 sdhci_finish_mrq(host, host->data_cmd->mrq);
2923 }
2924
2925 if (host->cmd) {
2926 host->cmd->error = err;
2927 sdhci_finish_mrq(host, host->cmd->mrq);
2928 }
2929}
2930
2931static void sdhci_card_event(struct mmc_host *mmc)
2932{
2933 struct sdhci_host *host = mmc_priv(mmc);
2934 unsigned long flags;
2935 int present;
2936
2937 /* First check if client has provided their own card event */
2938 if (host->ops->card_event)
2939 host->ops->card_event(host);
2940
2941 present = mmc->ops->get_cd(mmc);
2942
2943 spin_lock_irqsave(&host->lock, flags);
2944
2945 /* Check sdhci_has_requests() first in case we are runtime suspended */
2946 if (sdhci_has_requests(host) && !present) {
2947 pr_err("%s: Card removed during transfer!\n",
2948 mmc_hostname(mmc));
2949 pr_err("%s: Resetting controller.\n",
2950 mmc_hostname(mmc));
2951
2952 sdhci_do_reset(host, SDHCI_RESET_CMD);
2953 sdhci_do_reset(host, SDHCI_RESET_DATA);
2954
2955 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2956 }
2957
2958 spin_unlock_irqrestore(&host->lock, flags);
2959}
2960
2961static const struct mmc_host_ops sdhci_ops = {
2962 .request = sdhci_request,
2963 .post_req = sdhci_post_req,
2964 .pre_req = sdhci_pre_req,
2965 .set_ios = sdhci_set_ios,
2966 .get_cd = sdhci_get_cd,
2967 .get_ro = sdhci_get_ro,
2968 .hw_reset = sdhci_hw_reset,
2969 .enable_sdio_irq = sdhci_enable_sdio_irq,
2970 .ack_sdio_irq = sdhci_ack_sdio_irq,
2971 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2972 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2973 .execute_tuning = sdhci_execute_tuning,
2974 .card_event = sdhci_card_event,
2975 .card_busy = sdhci_card_busy,
2976};
2977
2978/*****************************************************************************\
2979 * *
2980 * Request done *
2981 * *
2982\*****************************************************************************/
2983
2984static bool sdhci_request_done(struct sdhci_host *host)
2985{
2986 unsigned long flags;
2987 struct mmc_request *mrq;
2988 int i;
2989
2990 spin_lock_irqsave(&host->lock, flags);
2991
2992 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2993 mrq = host->mrqs_done[i];
2994 if (mrq)
2995 break;
2996 }
2997
2998 if (!mrq) {
2999 spin_unlock_irqrestore(&host->lock, flags);
3000 return true;
3001 }
3002
3003 /*
3004 * The controller needs a reset of internal state machines
3005 * upon error conditions.
3006 */
3007 if (sdhci_needs_reset(host, mrq)) {
3008 /*
3009 * Do not finish until command and data lines are available for
3010 * reset. Note there can only be one other mrq, so it cannot
3011 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
3012 * would both be null.
3013 */
3014 if (host->cmd || host->data_cmd) {
3015 spin_unlock_irqrestore(&host->lock, flags);
3016 return true;
3017 }
3018
3019 /* Some controllers need this kick or reset won't work here */
3020 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
3021 /* This is to force an update */
3022 host->ops->set_clock(host, host->clock);
3023
3024 /*
3025 * Spec says we should do both at the same time, but Ricoh
3026 * controllers do not like that.
3027 */
3028 sdhci_do_reset(host, SDHCI_RESET_CMD);
3029 sdhci_do_reset(host, SDHCI_RESET_DATA);
3030
3031 host->pending_reset = false;
3032 }
3033
3034 /*
3035 * Always unmap the data buffers if they were mapped by
3036 * sdhci_prepare_data() whenever we finish with a request.
3037 * This avoids leaking DMA mappings on error.
3038 */
3039 if (host->flags & SDHCI_REQ_USE_DMA) {
3040 struct mmc_data *data = mrq->data;
3041
3042 if (host->use_external_dma && data &&
3043 (mrq->cmd->error || data->error)) {
3044 struct dma_chan *chan = sdhci_external_dma_channel(host, data);
3045
3046 host->mrqs_done[i] = NULL;
3047 spin_unlock_irqrestore(&host->lock, flags);
3048 dmaengine_terminate_sync(chan);
3049 spin_lock_irqsave(&host->lock, flags);
3050 sdhci_set_mrq_done(host, mrq);
3051 }
3052
3053 if (data && data->host_cookie == COOKIE_MAPPED) {
3054 if (host->bounce_buffer) {
3055 /*
3056 * On reads, copy the bounced data into the
3057 * sglist
3058 */
3059 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
3060 unsigned int length = data->bytes_xfered;
3061
3062 if (length > host->bounce_buffer_size) {
3063 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
3064 mmc_hostname(host->mmc),
3065 host->bounce_buffer_size,
3066 data->bytes_xfered);
3067 /* Cap it down and continue */
3068 length = host->bounce_buffer_size;
3069 }
3070 dma_sync_single_for_cpu(
3071 mmc_dev(host->mmc),
3072 host->bounce_addr,
3073 host->bounce_buffer_size,
3074 DMA_FROM_DEVICE);
3075 sg_copy_from_buffer(data->sg,
3076 data->sg_len,
3077 host->bounce_buffer,
3078 length);
3079 } else {
3080 /* No copying, just switch ownership */
3081 dma_sync_single_for_cpu(
3082 mmc_dev(host->mmc),
3083 host->bounce_addr,
3084 host->bounce_buffer_size,
3085 mmc_get_dma_dir(data));
3086 }
3087 } else {
3088 /* Unmap the raw data */
3089 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
3090 data->sg_len,
3091 mmc_get_dma_dir(data));
3092 }
3093 data->host_cookie = COOKIE_UNMAPPED;
3094 }
3095 }
3096
3097 host->mrqs_done[i] = NULL;
3098
3099 spin_unlock_irqrestore(&host->lock, flags);
3100
3101 if (host->ops->request_done)
3102 host->ops->request_done(host, mrq);
3103 else
3104 mmc_request_done(host->mmc, mrq);
3105
3106 return false;
3107}
3108
3109static void sdhci_complete_work(struct work_struct *work)
3110{
3111 struct sdhci_host *host = container_of(work, struct sdhci_host,
3112 complete_work);
3113
3114 while (!sdhci_request_done(host))
3115 ;
3116}
3117
3118static void sdhci_timeout_timer(struct timer_list *t)
3119{
3120 struct sdhci_host *host;
3121 unsigned long flags;
3122
3123 host = from_timer(host, t, timer);
3124
3125 spin_lock_irqsave(&host->lock, flags);
3126
3127 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
3128 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
3129 mmc_hostname(host->mmc));
3130 sdhci_dumpregs(host);
3131
3132 host->cmd->error = -ETIMEDOUT;
3133 sdhci_finish_mrq(host, host->cmd->mrq);
3134 }
3135
3136 spin_unlock_irqrestore(&host->lock, flags);
3137}
3138
3139static void sdhci_timeout_data_timer(struct timer_list *t)
3140{
3141 struct sdhci_host *host;
3142 unsigned long flags;
3143
3144 host = from_timer(host, t, data_timer);
3145
3146 spin_lock_irqsave(&host->lock, flags);
3147
3148 if (host->data || host->data_cmd ||
3149 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
3150 pr_err("%s: Timeout waiting for hardware interrupt.\n",
3151 mmc_hostname(host->mmc));
3152 sdhci_dumpregs(host);
3153
3154 if (host->data) {
3155 host->data->error = -ETIMEDOUT;
3156 __sdhci_finish_data(host, true);
3157 queue_work(host->complete_wq, &host->complete_work);
3158 } else if (host->data_cmd) {
3159 host->data_cmd->error = -ETIMEDOUT;
3160 sdhci_finish_mrq(host, host->data_cmd->mrq);
3161 } else {
3162 host->cmd->error = -ETIMEDOUT;
3163 sdhci_finish_mrq(host, host->cmd->mrq);
3164 }
3165 }
3166
3167 spin_unlock_irqrestore(&host->lock, flags);
3168}
3169
3170/*****************************************************************************\
3171 * *
3172 * Interrupt handling *
3173 * *
3174\*****************************************************************************/
3175
3176static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
3177{
3178 /* Handle auto-CMD12 error */
3179 if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
3180 struct mmc_request *mrq = host->data_cmd->mrq;
3181 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3182 int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3183 SDHCI_INT_DATA_TIMEOUT :
3184 SDHCI_INT_DATA_CRC;
3185
3186 /* Treat auto-CMD12 error the same as data error */
3187 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
3188 *intmask_p |= data_err_bit;
3189 return;
3190 }
3191 }
3192
3193 if (!host->cmd) {
3194 /*
3195 * SDHCI recovers from errors by resetting the cmd and data
3196 * circuits. Until that is done, there very well might be more
3197 * interrupts, so ignore them in that case.
3198 */
3199 if (host->pending_reset)
3200 return;
3201 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
3202 mmc_hostname(host->mmc), (unsigned)intmask);
3203 sdhci_dumpregs(host);
3204 return;
3205 }
3206
3207 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
3208 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
3209 if (intmask & SDHCI_INT_TIMEOUT)
3210 host->cmd->error = -ETIMEDOUT;
3211 else
3212 host->cmd->error = -EILSEQ;
3213
3214 /* Treat data command CRC error the same as data CRC error */
3215 if (host->cmd->data &&
3216 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
3217 SDHCI_INT_CRC) {
3218 host->cmd = NULL;
3219 *intmask_p |= SDHCI_INT_DATA_CRC;
3220 return;
3221 }
3222
3223 __sdhci_finish_mrq(host, host->cmd->mrq);
3224 return;
3225 }
3226
3227 /* Handle auto-CMD23 error */
3228 if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
3229 struct mmc_request *mrq = host->cmd->mrq;
3230 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3231 int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3232 -ETIMEDOUT :
3233 -EILSEQ;
3234
3235 if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
3236 mrq->sbc->error = err;
3237 __sdhci_finish_mrq(host, mrq);
3238 return;
3239 }
3240 }
3241
3242 if (intmask & SDHCI_INT_RESPONSE)
3243 sdhci_finish_command(host);
3244}
3245
3246static void sdhci_adma_show_error(struct sdhci_host *host)
3247{
3248 void *desc = host->adma_table;
3249 dma_addr_t dma = host->adma_addr;
3250
3251 sdhci_dumpregs(host);
3252
3253 while (true) {
3254 struct sdhci_adma2_64_desc *dma_desc = desc;
3255
3256 if (host->flags & SDHCI_USE_64_BIT_DMA)
3257 SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
3258 (unsigned long long)dma,
3259 le32_to_cpu(dma_desc->addr_hi),
3260 le32_to_cpu(dma_desc->addr_lo),
3261 le16_to_cpu(dma_desc->len),
3262 le16_to_cpu(dma_desc->cmd));
3263 else
3264 SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
3265 (unsigned long long)dma,
3266 le32_to_cpu(dma_desc->addr_lo),
3267 le16_to_cpu(dma_desc->len),
3268 le16_to_cpu(dma_desc->cmd));
3269
3270 desc += host->desc_sz;
3271 dma += host->desc_sz;
3272
3273 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
3274 break;
3275 }
3276}
3277
3278static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
3279{
3280 u32 command;
3281
3282 /* CMD19 generates _only_ Buffer Read Ready interrupt */
3283 if (intmask & SDHCI_INT_DATA_AVAIL) {
3284 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
3285 if (command == MMC_SEND_TUNING_BLOCK ||
3286 command == MMC_SEND_TUNING_BLOCK_HS200) {
3287 host->tuning_done = 1;
3288 wake_up(&host->buf_ready_int);
3289 return;
3290 }
3291 }
3292
3293 if (!host->data) {
3294 struct mmc_command *data_cmd = host->data_cmd;
3295
3296 /*
3297 * The "data complete" interrupt is also used to
3298 * indicate that a busy state has ended. See comment
3299 * above in sdhci_cmd_irq().
3300 */
3301 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
3302 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
3303 host->data_cmd = NULL;
3304 data_cmd->error = -ETIMEDOUT;
3305 __sdhci_finish_mrq(host, data_cmd->mrq);
3306 return;
3307 }
3308 if (intmask & SDHCI_INT_DATA_END) {
3309 host->data_cmd = NULL;
3310 /*
3311 * Some cards handle busy-end interrupt
3312 * before the command completed, so make
3313 * sure we do things in the proper order.
3314 */
3315 if (host->cmd == data_cmd)
3316 return;
3317
3318 __sdhci_finish_mrq(host, data_cmd->mrq);
3319 return;
3320 }
3321 }
3322
3323 /*
3324 * SDHCI recovers from errors by resetting the cmd and data
3325 * circuits. Until that is done, there very well might be more
3326 * interrupts, so ignore them in that case.
3327 */
3328 if (host->pending_reset)
3329 return;
3330
3331 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
3332 mmc_hostname(host->mmc), (unsigned)intmask);
3333 sdhci_dumpregs(host);
3334
3335 return;
3336 }
3337
3338 if (intmask & SDHCI_INT_DATA_TIMEOUT)
3339 host->data->error = -ETIMEDOUT;
3340 else if (intmask & SDHCI_INT_DATA_END_BIT)
3341 host->data->error = -EILSEQ;
3342 else if ((intmask & SDHCI_INT_DATA_CRC) &&
3343 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
3344 != MMC_BUS_TEST_R)
3345 host->data->error = -EILSEQ;
3346 else if (intmask & SDHCI_INT_ADMA_ERROR) {
3347 pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
3348 intmask);
3349 sdhci_adma_show_error(host);
3350 host->data->error = -EIO;
3351 if (host->ops->adma_workaround)
3352 host->ops->adma_workaround(host, intmask);
3353 }
3354
3355 if (host->data->error)
3356 sdhci_finish_data(host);
3357 else {
3358 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
3359 sdhci_transfer_pio(host);
3360
3361 /*
3362 * We currently don't do anything fancy with DMA
3363 * boundaries, but as we can't disable the feature
3364 * we need to at least restart the transfer.
3365 *
3366 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
3367 * should return a valid address to continue from, but as
3368 * some controllers are faulty, don't trust them.
3369 */
3370 if (intmask & SDHCI_INT_DMA_END) {
3371 dma_addr_t dmastart, dmanow;
3372
3373 dmastart = sdhci_sdma_address(host);
3374 dmanow = dmastart + host->data->bytes_xfered;
3375 /*
3376 * Force update to the next DMA block boundary.
3377 */
3378 dmanow = (dmanow &
3379 ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
3380 SDHCI_DEFAULT_BOUNDARY_SIZE;
3381 host->data->bytes_xfered = dmanow - dmastart;
3382 DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
3383 &dmastart, host->data->bytes_xfered, &dmanow);
3384 sdhci_set_sdma_addr(host, dmanow);
3385 }
3386
3387 if (intmask & SDHCI_INT_DATA_END) {
3388 if (host->cmd == host->data_cmd) {
3389 /*
3390 * Data managed to finish before the
3391 * command completed. Make sure we do
3392 * things in the proper order.
3393 */
3394 host->data_early = 1;
3395 } else {
3396 sdhci_finish_data(host);
3397 }
3398 }
3399 }
3400}
3401
3402static inline bool sdhci_defer_done(struct sdhci_host *host,
3403 struct mmc_request *mrq)
3404{
3405 struct mmc_data *data = mrq->data;
3406
3407 return host->pending_reset || host->always_defer_done ||
3408 ((host->flags & SDHCI_REQ_USE_DMA) && data &&
3409 data->host_cookie == COOKIE_MAPPED);
3410}
3411
3412static irqreturn_t sdhci_irq(int irq, void *dev_id)
3413{
3414 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0};
3415 irqreturn_t result = IRQ_NONE;
3416 struct sdhci_host *host = dev_id;
3417 u32 intmask, mask, unexpected = 0;
3418 int max_loops = 16;
3419 int i;
3420
3421 spin_lock(&host->lock);
3422
3423 if (host->runtime_suspended) {
3424 spin_unlock(&host->lock);
3425 return IRQ_NONE;
3426 }
3427
3428 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3429 if (!intmask || intmask == 0xffffffff) {
3430 result = IRQ_NONE;
3431 goto out;
3432 }
3433
3434 do {
3435 DBG("IRQ status 0x%08x\n", intmask);
3436
3437 if (host->ops->irq) {
3438 intmask = host->ops->irq(host, intmask);
3439 if (!intmask)
3440 goto cont;
3441 }
3442
3443 /* Clear selected interrupts. */
3444 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3445 SDHCI_INT_BUS_POWER);
3446 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3447
3448 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3449 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3450 SDHCI_CARD_PRESENT;
3451
3452 /*
3453 * There is a observation on i.mx esdhc. INSERT
3454 * bit will be immediately set again when it gets
3455 * cleared, if a card is inserted. We have to mask
3456 * the irq to prevent interrupt storm which will
3457 * freeze the system. And the REMOVE gets the
3458 * same situation.
3459 *
3460 * More testing are needed here to ensure it works
3461 * for other platforms though.
3462 */
3463 host->ier &= ~(SDHCI_INT_CARD_INSERT |
3464 SDHCI_INT_CARD_REMOVE);
3465 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
3466 SDHCI_INT_CARD_INSERT;
3467 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3468 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3469
3470 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
3471 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3472
3473 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
3474 SDHCI_INT_CARD_REMOVE);
3475 result = IRQ_WAKE_THREAD;
3476 }
3477
3478 if (intmask & SDHCI_INT_CMD_MASK)
3479 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
3480
3481 if (intmask & SDHCI_INT_DATA_MASK)
3482 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
3483
3484 if (intmask & SDHCI_INT_BUS_POWER)
3485 pr_err("%s: Card is consuming too much power!\n",
3486 mmc_hostname(host->mmc));
3487
3488 if (intmask & SDHCI_INT_RETUNE)
3489 mmc_retune_needed(host->mmc);
3490
3491 if ((intmask & SDHCI_INT_CARD_INT) &&
3492 (host->ier & SDHCI_INT_CARD_INT)) {
3493 sdhci_enable_sdio_irq_nolock(host, false);
3494 sdio_signal_irq(host->mmc);
3495 }
3496
3497 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
3498 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3499 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
3500 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
3501
3502 if (intmask) {
3503 unexpected |= intmask;
3504 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3505 }
3506cont:
3507 if (result == IRQ_NONE)
3508 result = IRQ_HANDLED;
3509
3510 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3511 } while (intmask && --max_loops);
3512
3513 /* Determine if mrqs can be completed immediately */
3514 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3515 struct mmc_request *mrq = host->mrqs_done[i];
3516
3517 if (!mrq)
3518 continue;
3519
3520 if (sdhci_defer_done(host, mrq)) {
3521 result = IRQ_WAKE_THREAD;
3522 } else {
3523 mrqs_done[i] = mrq;
3524 host->mrqs_done[i] = NULL;
3525 }
3526 }
3527out:
3528 if (host->deferred_cmd)
3529 result = IRQ_WAKE_THREAD;
3530
3531 spin_unlock(&host->lock);
3532
3533 /* Process mrqs ready for immediate completion */
3534 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3535 if (!mrqs_done[i])
3536 continue;
3537
3538 if (host->ops->request_done)
3539 host->ops->request_done(host, mrqs_done[i]);
3540 else
3541 mmc_request_done(host->mmc, mrqs_done[i]);
3542 }
3543
3544 if (unexpected) {
3545 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3546 mmc_hostname(host->mmc), unexpected);
3547 sdhci_dumpregs(host);
3548 }
3549
3550 return result;
3551}
3552
3553static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
3554{
3555 struct sdhci_host *host = dev_id;
3556 struct mmc_command *cmd;
3557 unsigned long flags;
3558 u32 isr;
3559
3560 while (!sdhci_request_done(host))
3561 ;
3562
3563 spin_lock_irqsave(&host->lock, flags);
3564
3565 isr = host->thread_isr;
3566 host->thread_isr = 0;
3567
3568 cmd = host->deferred_cmd;
3569 if (cmd && !sdhci_send_command_retry(host, cmd, flags))
3570 sdhci_finish_mrq(host, cmd->mrq);
3571
3572 spin_unlock_irqrestore(&host->lock, flags);
3573
3574 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3575 struct mmc_host *mmc = host->mmc;
3576
3577 mmc->ops->card_event(mmc);
3578 mmc_detect_change(mmc, msecs_to_jiffies(200));
3579 }
3580
3581 return IRQ_HANDLED;
3582}
3583
3584/*****************************************************************************\
3585 * *
3586 * Suspend/resume *
3587 * *
3588\*****************************************************************************/
3589
3590#ifdef CONFIG_PM
3591
3592static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
3593{
3594 return mmc_card_is_removable(host->mmc) &&
3595 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3596 !mmc_can_gpio_cd(host->mmc);
3597}
3598
3599/*
3600 * To enable wakeup events, the corresponding events have to be enabled in
3601 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
3602 * Table' in the SD Host Controller Standard Specification.
3603 * It is useless to restore SDHCI_INT_ENABLE state in
3604 * sdhci_disable_irq_wakeups() since it will be set by
3605 * sdhci_enable_card_detection() or sdhci_init().
3606 */
3607static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
3608{
3609 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
3610 SDHCI_WAKE_ON_INT;
3611 u32 irq_val = 0;
3612 u8 wake_val = 0;
3613 u8 val;
3614
3615 if (sdhci_cd_irq_can_wakeup(host)) {
3616 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
3617 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
3618 }
3619
3620 if (mmc_card_wake_sdio_irq(host->mmc)) {
3621 wake_val |= SDHCI_WAKE_ON_INT;
3622 irq_val |= SDHCI_INT_CARD_INT;
3623 }
3624
3625 if (!irq_val)
3626 return false;
3627
3628 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3629 val &= ~mask;
3630 val |= wake_val;
3631 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3632
3633 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
3634
3635 host->irq_wake_enabled = !enable_irq_wake(host->irq);
3636
3637 return host->irq_wake_enabled;
3638}
3639
3640static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3641{
3642 u8 val;
3643 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3644 | SDHCI_WAKE_ON_INT;
3645
3646 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3647 val &= ~mask;
3648 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3649
3650 disable_irq_wake(host->irq);
3651
3652 host->irq_wake_enabled = false;
3653}
3654
3655int sdhci_suspend_host(struct sdhci_host *host)
3656{
3657 sdhci_disable_card_detection(host);
3658
3659 mmc_retune_timer_stop(host->mmc);
3660
3661 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
3662 !sdhci_enable_irq_wakeups(host)) {
3663 host->ier = 0;
3664 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3665 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3666 free_irq(host->irq, host);
3667 }
3668
3669 return 0;
3670}
3671
3672EXPORT_SYMBOL_GPL(sdhci_suspend_host);
3673
3674int sdhci_resume_host(struct sdhci_host *host)
3675{
3676 struct mmc_host *mmc = host->mmc;
3677 int ret = 0;
3678
3679 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3680 if (host->ops->enable_dma)
3681 host->ops->enable_dma(host);
3682 }
3683
3684 if ((mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3685 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3686 /* Card keeps power but host controller does not */
3687 sdhci_init(host, 0);
3688 host->pwr = 0;
3689 host->clock = 0;
3690 mmc->ops->set_ios(mmc, &mmc->ios);
3691 } else {
3692 sdhci_init(host, (mmc->pm_flags & MMC_PM_KEEP_POWER));
3693 }
3694
3695 if (host->irq_wake_enabled) {
3696 sdhci_disable_irq_wakeups(host);
3697 } else {
3698 ret = request_threaded_irq(host->irq, sdhci_irq,
3699 sdhci_thread_irq, IRQF_SHARED,
3700 mmc_hostname(mmc), host);
3701 if (ret)
3702 return ret;
3703 }
3704
3705 sdhci_enable_card_detection(host);
3706
3707 return ret;
3708}
3709
3710EXPORT_SYMBOL_GPL(sdhci_resume_host);
3711
3712int sdhci_runtime_suspend_host(struct sdhci_host *host)
3713{
3714 unsigned long flags;
3715
3716 mmc_retune_timer_stop(host->mmc);
3717
3718 spin_lock_irqsave(&host->lock, flags);
3719 host->ier &= SDHCI_INT_CARD_INT;
3720 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3721 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3722 spin_unlock_irqrestore(&host->lock, flags);
3723
3724 synchronize_hardirq(host->irq);
3725
3726 spin_lock_irqsave(&host->lock, flags);
3727 host->runtime_suspended = true;
3728 spin_unlock_irqrestore(&host->lock, flags);
3729
3730 return 0;
3731}
3732EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3733
3734int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
3735{
3736 struct mmc_host *mmc = host->mmc;
3737 unsigned long flags;
3738 int host_flags = host->flags;
3739
3740 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3741 if (host->ops->enable_dma)
3742 host->ops->enable_dma(host);
3743 }
3744
3745 sdhci_init(host, soft_reset);
3746
3747 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3748 mmc->ios.power_mode != MMC_POWER_OFF) {
3749 /* Force clock and power re-program */
3750 host->pwr = 0;
3751 host->clock = 0;
3752 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3753 mmc->ops->set_ios(mmc, &mmc->ios);
3754
3755 if ((host_flags & SDHCI_PV_ENABLED) &&
3756 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3757 spin_lock_irqsave(&host->lock, flags);
3758 sdhci_enable_preset_value(host, true);
3759 spin_unlock_irqrestore(&host->lock, flags);
3760 }
3761
3762 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3763 mmc->ops->hs400_enhanced_strobe)
3764 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3765 }
3766
3767 spin_lock_irqsave(&host->lock, flags);
3768
3769 host->runtime_suspended = false;
3770
3771 /* Enable SDIO IRQ */
3772 if (sdio_irq_claimed(mmc))
3773 sdhci_enable_sdio_irq_nolock(host, true);
3774
3775 /* Enable Card Detection */
3776 sdhci_enable_card_detection(host);
3777
3778 spin_unlock_irqrestore(&host->lock, flags);
3779
3780 return 0;
3781}
3782EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3783
3784#endif /* CONFIG_PM */
3785
3786/*****************************************************************************\
3787 * *
3788 * Command Queue Engine (CQE) helpers *
3789 * *
3790\*****************************************************************************/
3791
3792void sdhci_cqe_enable(struct mmc_host *mmc)
3793{
3794 struct sdhci_host *host = mmc_priv(mmc);
3795 unsigned long flags;
3796 u8 ctrl;
3797
3798 spin_lock_irqsave(&host->lock, flags);
3799
3800 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3801 ctrl &= ~SDHCI_CTRL_DMA_MASK;
3802 /*
3803 * Host from V4.10 supports ADMA3 DMA type.
3804 * ADMA3 performs integrated descriptor which is more suitable
3805 * for cmd queuing to fetch both command and transfer descriptors.
3806 */
3807 if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
3808 ctrl |= SDHCI_CTRL_ADMA3;
3809 else if (host->flags & SDHCI_USE_64_BIT_DMA)
3810 ctrl |= SDHCI_CTRL_ADMA64;
3811 else
3812 ctrl |= SDHCI_CTRL_ADMA32;
3813 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3814
3815 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3816 SDHCI_BLOCK_SIZE);
3817
3818 /* Set maximum timeout */
3819 sdhci_set_timeout(host, NULL);
3820
3821 host->ier = host->cqe_ier;
3822
3823 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3824 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3825
3826 host->cqe_on = true;
3827
3828 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3829 mmc_hostname(mmc), host->ier,
3830 sdhci_readl(host, SDHCI_INT_STATUS));
3831
3832 spin_unlock_irqrestore(&host->lock, flags);
3833}
3834EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3835
3836void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3837{
3838 struct sdhci_host *host = mmc_priv(mmc);
3839 unsigned long flags;
3840
3841 spin_lock_irqsave(&host->lock, flags);
3842
3843 sdhci_set_default_irqs(host);
3844
3845 host->cqe_on = false;
3846
3847 if (recovery) {
3848 sdhci_do_reset(host, SDHCI_RESET_CMD);
3849 sdhci_do_reset(host, SDHCI_RESET_DATA);
3850 }
3851
3852 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3853 mmc_hostname(mmc), host->ier,
3854 sdhci_readl(host, SDHCI_INT_STATUS));
3855
3856 spin_unlock_irqrestore(&host->lock, flags);
3857}
3858EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3859
3860bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3861 int *data_error)
3862{
3863 u32 mask;
3864
3865 if (!host->cqe_on)
3866 return false;
3867
3868 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
3869 *cmd_error = -EILSEQ;
3870 else if (intmask & SDHCI_INT_TIMEOUT)
3871 *cmd_error = -ETIMEDOUT;
3872 else
3873 *cmd_error = 0;
3874
3875 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
3876 *data_error = -EILSEQ;
3877 else if (intmask & SDHCI_INT_DATA_TIMEOUT)
3878 *data_error = -ETIMEDOUT;
3879 else if (intmask & SDHCI_INT_ADMA_ERROR)
3880 *data_error = -EIO;
3881 else
3882 *data_error = 0;
3883
3884 /* Clear selected interrupts. */
3885 mask = intmask & host->cqe_ier;
3886 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3887
3888 if (intmask & SDHCI_INT_BUS_POWER)
3889 pr_err("%s: Card is consuming too much power!\n",
3890 mmc_hostname(host->mmc));
3891
3892 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3893 if (intmask) {
3894 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3895 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3896 mmc_hostname(host->mmc), intmask);
3897 sdhci_dumpregs(host);
3898 }
3899
3900 return true;
3901}
3902EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
3903
3904/*****************************************************************************\
3905 * *
3906 * Device allocation/registration *
3907 * *
3908\*****************************************************************************/
3909
3910struct sdhci_host *sdhci_alloc_host(struct device *dev,
3911 size_t priv_size)
3912{
3913 struct mmc_host *mmc;
3914 struct sdhci_host *host;
3915
3916 WARN_ON(dev == NULL);
3917
3918 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3919 if (!mmc)
3920 return ERR_PTR(-ENOMEM);
3921
3922 host = mmc_priv(mmc);
3923 host->mmc = mmc;
3924 host->mmc_host_ops = sdhci_ops;
3925 mmc->ops = &host->mmc_host_ops;
3926
3927 host->flags = SDHCI_SIGNALING_330;
3928
3929 host->cqe_ier = SDHCI_CQE_INT_MASK;
3930 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3931
3932 host->tuning_delay = -1;
3933 host->tuning_loop_count = MAX_TUNING_LOOP;
3934
3935 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
3936
3937 /*
3938 * The DMA table descriptor count is calculated as the maximum
3939 * number of segments times 2, to allow for an alignment
3940 * descriptor for each segment, plus 1 for a nop end descriptor.
3941 */
3942 host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
3943
3944 return host;
3945}
3946
3947EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3948
3949static int sdhci_set_dma_mask(struct sdhci_host *host)
3950{
3951 struct mmc_host *mmc = host->mmc;
3952 struct device *dev = mmc_dev(mmc);
3953 int ret = -EINVAL;
3954
3955 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3956 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3957
3958 /* Try 64-bit mask if hardware is capable of it */
3959 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3960 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3961 if (ret) {
3962 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3963 mmc_hostname(mmc));
3964 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3965 }
3966 }
3967
3968 /* 32-bit mask as default & fallback */
3969 if (ret) {
3970 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3971 if (ret)
3972 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3973 mmc_hostname(mmc));
3974 }
3975
3976 return ret;
3977}
3978
3979void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
3980 const u32 *caps, const u32 *caps1)
3981{
3982 u16 v;
3983 u64 dt_caps_mask = 0;
3984 u64 dt_caps = 0;
3985
3986 if (host->read_caps)
3987 return;
3988
3989 host->read_caps = true;
3990
3991 if (debug_quirks)
3992 host->quirks = debug_quirks;
3993
3994 if (debug_quirks2)
3995 host->quirks2 = debug_quirks2;
3996
3997 sdhci_do_reset(host, SDHCI_RESET_ALL);
3998
3999 if (host->v4_mode)
4000 sdhci_do_enable_v4_mode(host);
4001
4002 device_property_read_u64(mmc_dev(host->mmc),
4003 "sdhci-caps-mask", &dt_caps_mask);
4004 device_property_read_u64(mmc_dev(host->mmc),
4005 "sdhci-caps", &dt_caps);
4006
4007 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
4008 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
4009
4010 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
4011 return;
4012
4013 if (caps) {
4014 host->caps = *caps;
4015 } else {
4016 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
4017 host->caps &= ~lower_32_bits(dt_caps_mask);
4018 host->caps |= lower_32_bits(dt_caps);
4019 }
4020
4021 if (host->version < SDHCI_SPEC_300)
4022 return;
4023
4024 if (caps1) {
4025 host->caps1 = *caps1;
4026 } else {
4027 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
4028 host->caps1 &= ~upper_32_bits(dt_caps_mask);
4029 host->caps1 |= upper_32_bits(dt_caps);
4030 }
4031}
4032EXPORT_SYMBOL_GPL(__sdhci_read_caps);
4033
4034static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
4035{
4036 struct mmc_host *mmc = host->mmc;
4037 unsigned int max_blocks;
4038 unsigned int bounce_size;
4039 int ret;
4040
4041 /*
4042 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
4043 * has diminishing returns, this is probably because SD/MMC
4044 * cards are usually optimized to handle this size of requests.
4045 */
4046 bounce_size = SZ_64K;
4047 /*
4048 * Adjust downwards to maximum request size if this is less
4049 * than our segment size, else hammer down the maximum
4050 * request size to the maximum buffer size.
4051 */
4052 if (mmc->max_req_size < bounce_size)
4053 bounce_size = mmc->max_req_size;
4054 max_blocks = bounce_size / 512;
4055
4056 /*
4057 * When we just support one segment, we can get significant
4058 * speedups by the help of a bounce buffer to group scattered
4059 * reads/writes together.
4060 */
4061 host->bounce_buffer = devm_kmalloc(mmc_dev(mmc),
4062 bounce_size,
4063 GFP_KERNEL);
4064 if (!host->bounce_buffer) {
4065 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
4066 mmc_hostname(mmc),
4067 bounce_size);
4068 /*
4069 * Exiting with zero here makes sure we proceed with
4070 * mmc->max_segs == 1.
4071 */
4072 return;
4073 }
4074
4075 host->bounce_addr = dma_map_single(mmc_dev(mmc),
4076 host->bounce_buffer,
4077 bounce_size,
4078 DMA_BIDIRECTIONAL);
4079 ret = dma_mapping_error(mmc_dev(mmc), host->bounce_addr);
4080 if (ret) {
4081 devm_kfree(mmc_dev(mmc), host->bounce_buffer);
4082 host->bounce_buffer = NULL;
4083 /* Again fall back to max_segs == 1 */
4084 return;
4085 }
4086
4087 host->bounce_buffer_size = bounce_size;
4088
4089 /* Lie about this since we're bouncing */
4090 mmc->max_segs = max_blocks;
4091 mmc->max_seg_size = bounce_size;
4092 mmc->max_req_size = bounce_size;
4093
4094 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
4095 mmc_hostname(mmc), max_blocks, bounce_size);
4096}
4097
4098static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
4099{
4100 /*
4101 * According to SD Host Controller spec v4.10, bit[27] added from
4102 * version 4.10 in Capabilities Register is used as 64-bit System
4103 * Address support for V4 mode.
4104 */
4105 if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
4106 return host->caps & SDHCI_CAN_64BIT_V4;
4107
4108 return host->caps & SDHCI_CAN_64BIT;
4109}
4110
4111int sdhci_setup_host(struct sdhci_host *host)
4112{
4113 struct mmc_host *mmc;
4114 u32 max_current_caps;
4115 unsigned int ocr_avail;
4116 unsigned int override_timeout_clk;
4117 u32 max_clk;
4118 int ret = 0;
4119 bool enable_vqmmc = false;
4120
4121 WARN_ON(host == NULL);
4122 if (host == NULL)
4123 return -EINVAL;
4124
4125 mmc = host->mmc;
4126
4127 /*
4128 * If there are external regulators, get them. Note this must be done
4129 * early before resetting the host and reading the capabilities so that
4130 * the host can take the appropriate action if regulators are not
4131 * available.
4132 */
4133 if (!mmc->supply.vqmmc) {
4134 ret = mmc_regulator_get_supply(mmc);
4135 if (ret)
4136 return ret;
4137 enable_vqmmc = true;
4138 }
4139
4140 DBG("Version: 0x%08x | Present: 0x%08x\n",
4141 sdhci_readw(host, SDHCI_HOST_VERSION),
4142 sdhci_readl(host, SDHCI_PRESENT_STATE));
4143 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
4144 sdhci_readl(host, SDHCI_CAPABILITIES),
4145 sdhci_readl(host, SDHCI_CAPABILITIES_1));
4146
4147 sdhci_read_caps(host);
4148
4149 override_timeout_clk = host->timeout_clk;
4150
4151 if (host->version > SDHCI_SPEC_420) {
4152 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
4153 mmc_hostname(mmc), host->version);
4154 }
4155
4156 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
4157 host->flags |= SDHCI_USE_SDMA;
4158 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
4159 DBG("Controller doesn't have SDMA capability\n");
4160 else
4161 host->flags |= SDHCI_USE_SDMA;
4162
4163 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
4164 (host->flags & SDHCI_USE_SDMA)) {
4165 DBG("Disabling DMA as it is marked broken\n");
4166 host->flags &= ~SDHCI_USE_SDMA;
4167 }
4168
4169 if ((host->version >= SDHCI_SPEC_200) &&
4170 (host->caps & SDHCI_CAN_DO_ADMA2))
4171 host->flags |= SDHCI_USE_ADMA;
4172
4173 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
4174 (host->flags & SDHCI_USE_ADMA)) {
4175 DBG("Disabling ADMA as it is marked broken\n");
4176 host->flags &= ~SDHCI_USE_ADMA;
4177 }
4178
4179 if (sdhci_can_64bit_dma(host))
4180 host->flags |= SDHCI_USE_64_BIT_DMA;
4181
4182 if (host->use_external_dma) {
4183 ret = sdhci_external_dma_init(host);
4184 if (ret == -EPROBE_DEFER)
4185 goto unreg;
4186 /*
4187 * Fall back to use the DMA/PIO integrated in standard SDHCI
4188 * instead of external DMA devices.
4189 */
4190 else if (ret)
4191 sdhci_switch_external_dma(host, false);
4192 /* Disable internal DMA sources */
4193 else
4194 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4195 }
4196
4197 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
4198 if (host->ops->set_dma_mask)
4199 ret = host->ops->set_dma_mask(host);
4200 else
4201 ret = sdhci_set_dma_mask(host);
4202
4203 if (!ret && host->ops->enable_dma)
4204 ret = host->ops->enable_dma(host);
4205
4206 if (ret) {
4207 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
4208 mmc_hostname(mmc));
4209 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4210
4211 ret = 0;
4212 }
4213 }
4214
4215 /* SDMA does not support 64-bit DMA if v4 mode not set */
4216 if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
4217 host->flags &= ~SDHCI_USE_SDMA;
4218
4219 if (host->flags & SDHCI_USE_ADMA) {
4220 dma_addr_t dma;
4221 void *buf;
4222
4223 if (!(host->flags & SDHCI_USE_64_BIT_DMA))
4224 host->alloc_desc_sz = SDHCI_ADMA2_32_DESC_SZ;
4225 else if (!host->alloc_desc_sz)
4226 host->alloc_desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
4227
4228 host->desc_sz = host->alloc_desc_sz;
4229 host->adma_table_sz = host->adma_table_cnt * host->desc_sz;
4230
4231 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
4232 /*
4233 * Use zalloc to zero the reserved high 32-bits of 128-bit
4234 * descriptors so that they never need to be written.
4235 */
4236 buf = dma_alloc_coherent(mmc_dev(mmc),
4237 host->align_buffer_sz + host->adma_table_sz,
4238 &dma, GFP_KERNEL);
4239 if (!buf) {
4240 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
4241 mmc_hostname(mmc));
4242 host->flags &= ~SDHCI_USE_ADMA;
4243 } else if ((dma + host->align_buffer_sz) &
4244 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
4245 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
4246 mmc_hostname(mmc));
4247 host->flags &= ~SDHCI_USE_ADMA;
4248 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4249 host->adma_table_sz, buf, dma);
4250 } else {
4251 host->align_buffer = buf;
4252 host->align_addr = dma;
4253
4254 host->adma_table = buf + host->align_buffer_sz;
4255 host->adma_addr = dma + host->align_buffer_sz;
4256 }
4257 }
4258
4259 /*
4260 * If we use DMA, then it's up to the caller to set the DMA
4261 * mask, but PIO does not need the hw shim so we set a new
4262 * mask here in that case.
4263 */
4264 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
4265 host->dma_mask = DMA_BIT_MASK(64);
4266 mmc_dev(mmc)->dma_mask = &host->dma_mask;
4267 }
4268
4269 if (host->version >= SDHCI_SPEC_300)
4270 host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps);
4271 else
4272 host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps);
4273
4274 host->max_clk *= 1000000;
4275 if (host->max_clk == 0 || host->quirks &
4276 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4277 if (!host->ops->get_max_clock) {
4278 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
4279 mmc_hostname(mmc));
4280 ret = -ENODEV;
4281 goto undma;
4282 }
4283 host->max_clk = host->ops->get_max_clock(host);
4284 }
4285
4286 /*
4287 * In case of Host Controller v3.00, find out whether clock
4288 * multiplier is supported.
4289 */
4290 host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1);
4291
4292 /*
4293 * In case the value in Clock Multiplier is 0, then programmable
4294 * clock mode is not supported, otherwise the actual clock
4295 * multiplier is one more than the value of Clock Multiplier
4296 * in the Capabilities Register.
4297 */
4298 if (host->clk_mul)
4299 host->clk_mul += 1;
4300
4301 /*
4302 * Set host parameters.
4303 */
4304 max_clk = host->max_clk;
4305
4306 if (host->ops->get_min_clock)
4307 mmc->f_min = host->ops->get_min_clock(host);
4308 else if (host->version >= SDHCI_SPEC_300) {
4309 if (host->clk_mul)
4310 max_clk = host->max_clk * host->clk_mul;
4311 /*
4312 * Divided Clock Mode minimum clock rate is always less than
4313 * Programmable Clock Mode minimum clock rate.
4314 */
4315 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
4316 } else
4317 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
4318
4319 if (!mmc->f_max || mmc->f_max > max_clk)
4320 mmc->f_max = max_clk;
4321
4322 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4323 host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps);
4324
4325 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
4326 host->timeout_clk *= 1000;
4327
4328 if (host->timeout_clk == 0) {
4329 if (!host->ops->get_timeout_clock) {
4330 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
4331 mmc_hostname(mmc));
4332 ret = -ENODEV;
4333 goto undma;
4334 }
4335
4336 host->timeout_clk =
4337 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
4338 1000);
4339 }
4340
4341 if (override_timeout_clk)
4342 host->timeout_clk = override_timeout_clk;
4343
4344 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
4345 host->ops->get_max_timeout_count(host) : 1 << 27;
4346 mmc->max_busy_timeout /= host->timeout_clk;
4347 }
4348
4349 if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
4350 !host->ops->get_max_timeout_count)
4351 mmc->max_busy_timeout = 0;
4352
4353 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_CMD23;
4354 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
4355
4356 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
4357 host->flags |= SDHCI_AUTO_CMD12;
4358
4359 /*
4360 * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
4361 * For v4 mode, SDMA may use Auto-CMD23 as well.
4362 */
4363 if ((host->version >= SDHCI_SPEC_300) &&
4364 ((host->flags & SDHCI_USE_ADMA) ||
4365 !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
4366 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
4367 host->flags |= SDHCI_AUTO_CMD23;
4368 DBG("Auto-CMD23 available\n");
4369 } else {
4370 DBG("Auto-CMD23 unavailable\n");
4371 }
4372
4373 /*
4374 * A controller may support 8-bit width, but the board itself
4375 * might not have the pins brought out. Boards that support
4376 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
4377 * their platform code before calling sdhci_add_host(), and we
4378 * won't assume 8-bit width for hosts without that CAP.
4379 */
4380 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
4381 mmc->caps |= MMC_CAP_4_BIT_DATA;
4382
4383 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
4384 mmc->caps &= ~MMC_CAP_CMD23;
4385
4386 if (host->caps & SDHCI_CAN_DO_HISPD)
4387 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
4388
4389 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4390 mmc_card_is_removable(mmc) &&
4391 mmc_gpio_get_cd(mmc) < 0)
4392 mmc->caps |= MMC_CAP_NEEDS_POLL;
4393
4394 if (!IS_ERR(mmc->supply.vqmmc)) {
4395 if (enable_vqmmc) {
4396 ret = regulator_enable(mmc->supply.vqmmc);
4397 host->sdhci_core_to_disable_vqmmc = !ret;
4398 }
4399
4400 /* If vqmmc provides no 1.8V signalling, then there's no UHS */
4401 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
4402 1950000))
4403 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
4404 SDHCI_SUPPORT_SDR50 |
4405 SDHCI_SUPPORT_DDR50);
4406
4407 /* In eMMC case vqmmc might be a fixed 1.8V regulator */
4408 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
4409 3600000))
4410 host->flags &= ~SDHCI_SIGNALING_330;
4411
4412 if (ret) {
4413 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
4414 mmc_hostname(mmc), ret);
4415 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
4416 }
4417
4418 }
4419
4420 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
4421 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4422 SDHCI_SUPPORT_DDR50);
4423 /*
4424 * The SDHCI controller in a SoC might support HS200/HS400
4425 * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
4426 * but if the board is modeled such that the IO lines are not
4427 * connected to 1.8v then HS200/HS400 cannot be supported.
4428 * Disable HS200/HS400 if the board does not have 1.8v connected
4429 * to the IO lines. (Applicable for other modes in 1.8v)
4430 */
4431 mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
4432 mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
4433 }
4434
4435 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
4436 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4437 SDHCI_SUPPORT_DDR50))
4438 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
4439
4440 /* SDR104 supports also implies SDR50 support */
4441 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
4442 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
4443 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
4444 * field can be promoted to support HS200.
4445 */
4446 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
4447 mmc->caps2 |= MMC_CAP2_HS200;
4448 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
4449 mmc->caps |= MMC_CAP_UHS_SDR50;
4450 }
4451
4452 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
4453 (host->caps1 & SDHCI_SUPPORT_HS400))
4454 mmc->caps2 |= MMC_CAP2_HS400;
4455
4456 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
4457 (IS_ERR(mmc->supply.vqmmc) ||
4458 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
4459 1300000)))
4460 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
4461
4462 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
4463 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
4464 mmc->caps |= MMC_CAP_UHS_DDR50;
4465
4466 /* Does the host need tuning for SDR50? */
4467 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
4468 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
4469
4470 /* Driver Type(s) (A, C, D) supported by the host */
4471 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
4472 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
4473 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
4474 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
4475 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
4476 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
4477
4478 /* Initial value for re-tuning timer count */
4479 host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK,
4480 host->caps1);
4481
4482 /*
4483 * In case Re-tuning Timer is not disabled, the actual value of
4484 * re-tuning timer will be 2 ^ (n - 1).
4485 */
4486 if (host->tuning_count)
4487 host->tuning_count = 1 << (host->tuning_count - 1);
4488
4489 /* Re-tuning mode supported by the Host Controller */
4490 host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1);
4491
4492 ocr_avail = 0;
4493
4494 /*
4495 * According to SD Host Controller spec v3.00, if the Host System
4496 * can afford more than 150mA, Host Driver should set XPC to 1. Also
4497 * the value is meaningful only if Voltage Support in the Capabilities
4498 * register is set. The actual current value is 4 times the register
4499 * value.
4500 */
4501 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
4502 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
4503 int curr = regulator_get_current_limit(mmc->supply.vmmc);
4504 if (curr > 0) {
4505
4506 /* convert to SDHCI_MAX_CURRENT format */
4507 curr = curr/1000; /* convert to mA */
4508 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
4509
4510 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
4511 max_current_caps =
4512 FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, curr) |
4513 FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, curr) |
4514 FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, curr);
4515 }
4516 }
4517
4518 if (host->caps & SDHCI_CAN_VDD_330) {
4519 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
4520
4521 mmc->max_current_330 = FIELD_GET(SDHCI_MAX_CURRENT_330_MASK,
4522 max_current_caps) *
4523 SDHCI_MAX_CURRENT_MULTIPLIER;
4524 }
4525 if (host->caps & SDHCI_CAN_VDD_300) {
4526 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
4527
4528 mmc->max_current_300 = FIELD_GET(SDHCI_MAX_CURRENT_300_MASK,
4529 max_current_caps) *
4530 SDHCI_MAX_CURRENT_MULTIPLIER;
4531 }
4532 if (host->caps & SDHCI_CAN_VDD_180) {
4533 ocr_avail |= MMC_VDD_165_195;
4534
4535 mmc->max_current_180 = FIELD_GET(SDHCI_MAX_CURRENT_180_MASK,
4536 max_current_caps) *
4537 SDHCI_MAX_CURRENT_MULTIPLIER;
4538 }
4539
4540 /* If OCR set by host, use it instead. */
4541 if (host->ocr_mask)
4542 ocr_avail = host->ocr_mask;
4543
4544 /* If OCR set by external regulators, give it highest prio. */
4545 if (mmc->ocr_avail)
4546 ocr_avail = mmc->ocr_avail;
4547
4548 mmc->ocr_avail = ocr_avail;
4549 mmc->ocr_avail_sdio = ocr_avail;
4550 if (host->ocr_avail_sdio)
4551 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
4552 mmc->ocr_avail_sd = ocr_avail;
4553 if (host->ocr_avail_sd)
4554 mmc->ocr_avail_sd &= host->ocr_avail_sd;
4555 else /* normal SD controllers don't support 1.8V */
4556 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
4557 mmc->ocr_avail_mmc = ocr_avail;
4558 if (host->ocr_avail_mmc)
4559 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
4560
4561 if (mmc->ocr_avail == 0) {
4562 pr_err("%s: Hardware doesn't report any support voltages.\n",
4563 mmc_hostname(mmc));
4564 ret = -ENODEV;
4565 goto unreg;
4566 }
4567
4568 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
4569 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
4570 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
4571 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
4572 host->flags |= SDHCI_SIGNALING_180;
4573
4574 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
4575 host->flags |= SDHCI_SIGNALING_120;
4576
4577 spin_lock_init(&host->lock);
4578
4579 /*
4580 * Maximum number of sectors in one transfer. Limited by SDMA boundary
4581 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
4582 * is less anyway.
4583 */
4584 mmc->max_req_size = 524288;
4585
4586 /*
4587 * Maximum number of segments. Depends on if the hardware
4588 * can do scatter/gather or not.
4589 */
4590 if (host->flags & SDHCI_USE_ADMA) {
4591 mmc->max_segs = SDHCI_MAX_SEGS;
4592 } else if (host->flags & SDHCI_USE_SDMA) {
4593 mmc->max_segs = 1;
4594 mmc->max_req_size = min_t(size_t, mmc->max_req_size,
4595 dma_max_mapping_size(mmc_dev(mmc)));
4596 } else { /* PIO */
4597 mmc->max_segs = SDHCI_MAX_SEGS;
4598 }
4599
4600 /*
4601 * Maximum segment size. Could be one segment with the maximum number
4602 * of bytes. When doing hardware scatter/gather, each entry cannot
4603 * be larger than 64 KiB though.
4604 */
4605 if (host->flags & SDHCI_USE_ADMA) {
4606 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
4607 mmc->max_seg_size = 65535;
4608 else
4609 mmc->max_seg_size = 65536;
4610 } else {
4611 mmc->max_seg_size = mmc->max_req_size;
4612 }
4613
4614 /*
4615 * Maximum block size. This varies from controller to controller and
4616 * is specified in the capabilities register.
4617 */
4618 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4619 mmc->max_blk_size = 2;
4620 } else {
4621 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
4622 SDHCI_MAX_BLOCK_SHIFT;
4623 if (mmc->max_blk_size >= 3) {
4624 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
4625 mmc_hostname(mmc));
4626 mmc->max_blk_size = 0;
4627 }
4628 }
4629
4630 mmc->max_blk_size = 512 << mmc->max_blk_size;
4631
4632 /*
4633 * Maximum block count.
4634 */
4635 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
4636
4637 if (mmc->max_segs == 1)
4638 /* This may alter mmc->*_blk_* parameters */
4639 sdhci_allocate_bounce_buffer(host);
4640
4641 return 0;
4642
4643unreg:
4644 if (host->sdhci_core_to_disable_vqmmc)
4645 regulator_disable(mmc->supply.vqmmc);
4646undma:
4647 if (host->align_buffer)
4648 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4649 host->adma_table_sz, host->align_buffer,
4650 host->align_addr);
4651 host->adma_table = NULL;
4652 host->align_buffer = NULL;
4653
4654 return ret;
4655}
4656EXPORT_SYMBOL_GPL(sdhci_setup_host);
4657
4658void sdhci_cleanup_host(struct sdhci_host *host)
4659{
4660 struct mmc_host *mmc = host->mmc;
4661
4662 if (host->sdhci_core_to_disable_vqmmc)
4663 regulator_disable(mmc->supply.vqmmc);
4664
4665 if (host->align_buffer)
4666 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4667 host->adma_table_sz, host->align_buffer,
4668 host->align_addr);
4669
4670 if (host->use_external_dma)
4671 sdhci_external_dma_release(host);
4672
4673 host->adma_table = NULL;
4674 host->align_buffer = NULL;
4675}
4676EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
4677
4678int __sdhci_add_host(struct sdhci_host *host)
4679{
4680 unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI;
4681 struct mmc_host *mmc = host->mmc;
4682 int ret;
4683
4684 if ((mmc->caps2 & MMC_CAP2_CQE) &&
4685 (host->quirks & SDHCI_QUIRK_BROKEN_CQE)) {
4686 mmc->caps2 &= ~MMC_CAP2_CQE;
4687 mmc->cqe_ops = NULL;
4688 }
4689
4690 host->complete_wq = alloc_workqueue("sdhci", flags, 0);
4691 if (!host->complete_wq)
4692 return -ENOMEM;
4693
4694 INIT_WORK(&host->complete_work, sdhci_complete_work);
4695
4696 timer_setup(&host->timer, sdhci_timeout_timer, 0);
4697 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
4698
4699 init_waitqueue_head(&host->buf_ready_int);
4700
4701 sdhci_init(host, 0);
4702
4703 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
4704 IRQF_SHARED, mmc_hostname(mmc), host);
4705 if (ret) {
4706 pr_err("%s: Failed to request IRQ %d: %d\n",
4707 mmc_hostname(mmc), host->irq, ret);
4708 goto unwq;
4709 }
4710
4711 ret = sdhci_led_register(host);
4712 if (ret) {
4713 pr_err("%s: Failed to register LED device: %d\n",
4714 mmc_hostname(mmc), ret);
4715 goto unirq;
4716 }
4717
4718 ret = mmc_add_host(mmc);
4719 if (ret)
4720 goto unled;
4721
4722 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
4723 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
4724 host->use_external_dma ? "External DMA" :
4725 (host->flags & SDHCI_USE_ADMA) ?
4726 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
4727 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4728
4729 sdhci_enable_card_detection(host);
4730
4731 return 0;
4732
4733unled:
4734 sdhci_led_unregister(host);
4735unirq:
4736 sdhci_do_reset(host, SDHCI_RESET_ALL);
4737 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4738 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4739 free_irq(host->irq, host);
4740unwq:
4741 destroy_workqueue(host->complete_wq);
4742
4743 return ret;
4744}
4745EXPORT_SYMBOL_GPL(__sdhci_add_host);
4746
4747int sdhci_add_host(struct sdhci_host *host)
4748{
4749 int ret;
4750
4751 ret = sdhci_setup_host(host);
4752 if (ret)
4753 return ret;
4754
4755 ret = __sdhci_add_host(host);
4756 if (ret)
4757 goto cleanup;
4758
4759 return 0;
4760
4761cleanup:
4762 sdhci_cleanup_host(host);
4763
4764 return ret;
4765}
4766EXPORT_SYMBOL_GPL(sdhci_add_host);
4767
4768void sdhci_remove_host(struct sdhci_host *host, int dead)
4769{
4770 struct mmc_host *mmc = host->mmc;
4771 unsigned long flags;
4772
4773 if (dead) {
4774 spin_lock_irqsave(&host->lock, flags);
4775
4776 host->flags |= SDHCI_DEVICE_DEAD;
4777
4778 if (sdhci_has_requests(host)) {
4779 pr_err("%s: Controller removed during "
4780 " transfer!\n", mmc_hostname(mmc));
4781 sdhci_error_out_mrqs(host, -ENOMEDIUM);
4782 }
4783
4784 spin_unlock_irqrestore(&host->lock, flags);
4785 }
4786
4787 sdhci_disable_card_detection(host);
4788
4789 mmc_remove_host(mmc);
4790
4791 sdhci_led_unregister(host);
4792
4793 if (!dead)
4794 sdhci_do_reset(host, SDHCI_RESET_ALL);
4795
4796 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4797 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4798 free_irq(host->irq, host);
4799
4800 del_timer_sync(&host->timer);
4801 del_timer_sync(&host->data_timer);
4802
4803 destroy_workqueue(host->complete_wq);
4804
4805 if (host->sdhci_core_to_disable_vqmmc)
4806 regulator_disable(mmc->supply.vqmmc);
4807
4808 if (host->align_buffer)
4809 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4810 host->adma_table_sz, host->align_buffer,
4811 host->align_addr);
4812
4813 if (host->use_external_dma)
4814 sdhci_external_dma_release(host);
4815
4816 host->adma_table = NULL;
4817 host->align_buffer = NULL;
4818}
4819
4820EXPORT_SYMBOL_GPL(sdhci_remove_host);
4821
4822void sdhci_free_host(struct sdhci_host *host)
4823{
4824 mmc_free_host(host->mmc);
4825}
4826
4827EXPORT_SYMBOL_GPL(sdhci_free_host);
4828
4829/*****************************************************************************\
4830 * *
4831 * Driver init/exit *
4832 * *
4833\*****************************************************************************/
4834
4835static int __init sdhci_drv_init(void)
4836{
4837 pr_info(DRIVER_NAME
4838 ": Secure Digital Host Controller Interface driver\n");
4839 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4840
4841 return 0;
4842}
4843
4844static void __exit sdhci_drv_exit(void)
4845{
4846}
4847
4848module_init(sdhci_drv_init);
4849module_exit(sdhci_drv_exit);
4850
4851module_param(debug_quirks, uint, 0444);
4852module_param(debug_quirks2, uint, 0444);
4853
4854MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4855MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4856MODULE_LICENSE("GPL");
4857
4858MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4859MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");