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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 *
5 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 *
7 * Thanks to the following companies for their support:
8 *
9 * - JMicron (hardware and technical support)
10 */
11
12#include <linux/bitfield.h>
13#include <linux/delay.h>
14#include <linux/dmaengine.h>
15#include <linux/ktime.h>
16#include <linux/highmem.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/dma-mapping.h>
20#include <linux/slab.h>
21#include <linux/scatterlist.h>
22#include <linux/sizes.h>
23#include <linux/regulator/consumer.h>
24#include <linux/pm_runtime.h>
25#include <linux/of.h>
26
27#include <linux/leds.h>
28
29#include <linux/mmc/mmc.h>
30#include <linux/mmc/host.h>
31#include <linux/mmc/card.h>
32#include <linux/mmc/sdio.h>
33#include <linux/mmc/slot-gpio.h>
34
35#include "sdhci.h"
36
37#define DRIVER_NAME "sdhci"
38
39#define DBG(f, x...) \
40 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
41
42#define SDHCI_DUMP(f, x...) \
43 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
44
45#define MAX_TUNING_LOOP 40
46
47static unsigned int debug_quirks = 0;
48static unsigned int debug_quirks2;
49
50static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
51
52static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
53
54void sdhci_dumpregs(struct sdhci_host *host)
55{
56 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
57
58 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
59 sdhci_readl(host, SDHCI_DMA_ADDRESS),
60 sdhci_readw(host, SDHCI_HOST_VERSION));
61 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
62 sdhci_readw(host, SDHCI_BLOCK_SIZE),
63 sdhci_readw(host, SDHCI_BLOCK_COUNT));
64 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
65 sdhci_readl(host, SDHCI_ARGUMENT),
66 sdhci_readw(host, SDHCI_TRANSFER_MODE));
67 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
68 sdhci_readl(host, SDHCI_PRESENT_STATE),
69 sdhci_readb(host, SDHCI_HOST_CONTROL));
70 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
71 sdhci_readb(host, SDHCI_POWER_CONTROL),
72 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
73 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
74 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
75 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
76 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
77 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
78 sdhci_readl(host, SDHCI_INT_STATUS));
79 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
80 sdhci_readl(host, SDHCI_INT_ENABLE),
81 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
82 SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
83 sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
84 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
85 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
86 sdhci_readl(host, SDHCI_CAPABILITIES),
87 sdhci_readl(host, SDHCI_CAPABILITIES_1));
88 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
89 sdhci_readw(host, SDHCI_COMMAND),
90 sdhci_readl(host, SDHCI_MAX_CURRENT));
91 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
92 sdhci_readl(host, SDHCI_RESPONSE),
93 sdhci_readl(host, SDHCI_RESPONSE + 4));
94 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
95 sdhci_readl(host, SDHCI_RESPONSE + 8),
96 sdhci_readl(host, SDHCI_RESPONSE + 12));
97 SDHCI_DUMP("Host ctl2: 0x%08x\n",
98 sdhci_readw(host, SDHCI_HOST_CONTROL2));
99
100 if (host->flags & SDHCI_USE_ADMA) {
101 if (host->flags & SDHCI_USE_64_BIT_DMA) {
102 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
103 sdhci_readl(host, SDHCI_ADMA_ERROR),
104 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
105 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
106 } else {
107 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
108 sdhci_readl(host, SDHCI_ADMA_ERROR),
109 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
110 }
111 }
112
113 if (host->ops->dump_vendor_regs)
114 host->ops->dump_vendor_regs(host);
115
116 SDHCI_DUMP("============================================\n");
117}
118EXPORT_SYMBOL_GPL(sdhci_dumpregs);
119
120/*****************************************************************************\
121 * *
122 * Low level functions *
123 * *
124\*****************************************************************************/
125
126static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
127{
128 u16 ctrl2;
129
130 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
131 if (ctrl2 & SDHCI_CTRL_V4_MODE)
132 return;
133
134 ctrl2 |= SDHCI_CTRL_V4_MODE;
135 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
136}
137
138/*
139 * This can be called before sdhci_add_host() by Vendor's host controller
140 * driver to enable v4 mode if supported.
141 */
142void sdhci_enable_v4_mode(struct sdhci_host *host)
143{
144 host->v4_mode = true;
145 sdhci_do_enable_v4_mode(host);
146}
147EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
148
149static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
150{
151 return cmd->data || cmd->flags & MMC_RSP_BUSY;
152}
153
154static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
155{
156 u32 present;
157
158 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
159 !mmc_card_is_removable(host->mmc) || mmc_can_gpio_cd(host->mmc))
160 return;
161
162 if (enable) {
163 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
164 SDHCI_CARD_PRESENT;
165
166 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
167 SDHCI_INT_CARD_INSERT;
168 } else {
169 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
170 }
171
172 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
173 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
174}
175
176static void sdhci_enable_card_detection(struct sdhci_host *host)
177{
178 sdhci_set_card_detection(host, true);
179}
180
181static void sdhci_disable_card_detection(struct sdhci_host *host)
182{
183 sdhci_set_card_detection(host, false);
184}
185
186static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
187{
188 if (host->bus_on)
189 return;
190 host->bus_on = true;
191 pm_runtime_get_noresume(mmc_dev(host->mmc));
192}
193
194static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
195{
196 if (!host->bus_on)
197 return;
198 host->bus_on = false;
199 pm_runtime_put_noidle(mmc_dev(host->mmc));
200}
201
202void sdhci_reset(struct sdhci_host *host, u8 mask)
203{
204 ktime_t timeout;
205
206 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
207
208 if (mask & SDHCI_RESET_ALL) {
209 host->clock = 0;
210 /* Reset-all turns off SD Bus Power */
211 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
212 sdhci_runtime_pm_bus_off(host);
213 }
214
215 /* Wait max 100 ms */
216 timeout = ktime_add_ms(ktime_get(), 100);
217
218 /* hw clears the bit when it's done */
219 while (1) {
220 bool timedout = ktime_after(ktime_get(), timeout);
221
222 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
223 break;
224 if (timedout) {
225 pr_err("%s: Reset 0x%x never completed.\n",
226 mmc_hostname(host->mmc), (int)mask);
227 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
228 sdhci_dumpregs(host);
229 return;
230 }
231 udelay(10);
232 }
233}
234EXPORT_SYMBOL_GPL(sdhci_reset);
235
236static bool sdhci_do_reset(struct sdhci_host *host, u8 mask)
237{
238 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
239 struct mmc_host *mmc = host->mmc;
240
241 if (!mmc->ops->get_cd(mmc))
242 return false;
243 }
244
245 host->ops->reset(host, mask);
246
247 return true;
248}
249
250static void sdhci_reset_for_all(struct sdhci_host *host)
251{
252 if (sdhci_do_reset(host, SDHCI_RESET_ALL)) {
253 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
254 if (host->ops->enable_dma)
255 host->ops->enable_dma(host);
256 }
257 /* Resetting the controller clears many */
258 host->preset_enabled = false;
259 }
260}
261
262enum sdhci_reset_reason {
263 SDHCI_RESET_FOR_INIT,
264 SDHCI_RESET_FOR_REQUEST_ERROR,
265 SDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY,
266 SDHCI_RESET_FOR_TUNING_ABORT,
267 SDHCI_RESET_FOR_CARD_REMOVED,
268 SDHCI_RESET_FOR_CQE_RECOVERY,
269};
270
271static void sdhci_reset_for_reason(struct sdhci_host *host, enum sdhci_reset_reason reason)
272{
273 if (host->quirks2 & SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER) {
274 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
275 return;
276 }
277
278 switch (reason) {
279 case SDHCI_RESET_FOR_INIT:
280 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
281 break;
282 case SDHCI_RESET_FOR_REQUEST_ERROR:
283 case SDHCI_RESET_FOR_TUNING_ABORT:
284 case SDHCI_RESET_FOR_CARD_REMOVED:
285 case SDHCI_RESET_FOR_CQE_RECOVERY:
286 sdhci_do_reset(host, SDHCI_RESET_CMD);
287 sdhci_do_reset(host, SDHCI_RESET_DATA);
288 break;
289 case SDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY:
290 sdhci_do_reset(host, SDHCI_RESET_DATA);
291 break;
292 }
293}
294
295#define sdhci_reset_for(h, r) sdhci_reset_for_reason((h), SDHCI_RESET_FOR_##r)
296
297static void sdhci_set_default_irqs(struct sdhci_host *host)
298{
299 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
300 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
301 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
302 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
303 SDHCI_INT_RESPONSE;
304
305 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
306 host->tuning_mode == SDHCI_TUNING_MODE_3)
307 host->ier |= SDHCI_INT_RETUNE;
308
309 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
310 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
311}
312
313static void sdhci_config_dma(struct sdhci_host *host)
314{
315 u8 ctrl;
316 u16 ctrl2;
317
318 if (host->version < SDHCI_SPEC_200)
319 return;
320
321 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
322
323 /*
324 * Always adjust the DMA selection as some controllers
325 * (e.g. JMicron) can't do PIO properly when the selection
326 * is ADMA.
327 */
328 ctrl &= ~SDHCI_CTRL_DMA_MASK;
329 if (!(host->flags & SDHCI_REQ_USE_DMA))
330 goto out;
331
332 /* Note if DMA Select is zero then SDMA is selected */
333 if (host->flags & SDHCI_USE_ADMA)
334 ctrl |= SDHCI_CTRL_ADMA32;
335
336 if (host->flags & SDHCI_USE_64_BIT_DMA) {
337 /*
338 * If v4 mode, all supported DMA can be 64-bit addressing if
339 * controller supports 64-bit system address, otherwise only
340 * ADMA can support 64-bit addressing.
341 */
342 if (host->v4_mode) {
343 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
344 ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
345 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
346 } else if (host->flags & SDHCI_USE_ADMA) {
347 /*
348 * Don't need to undo SDHCI_CTRL_ADMA32 in order to
349 * set SDHCI_CTRL_ADMA64.
350 */
351 ctrl |= SDHCI_CTRL_ADMA64;
352 }
353 }
354
355out:
356 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
357}
358
359static void sdhci_init(struct sdhci_host *host, int soft)
360{
361 struct mmc_host *mmc = host->mmc;
362 unsigned long flags;
363
364 if (soft)
365 sdhci_reset_for(host, INIT);
366 else
367 sdhci_reset_for_all(host);
368
369 if (host->v4_mode)
370 sdhci_do_enable_v4_mode(host);
371
372 spin_lock_irqsave(&host->lock, flags);
373 sdhci_set_default_irqs(host);
374 spin_unlock_irqrestore(&host->lock, flags);
375
376 host->cqe_on = false;
377
378 if (soft) {
379 /* force clock reconfiguration */
380 host->clock = 0;
381 host->reinit_uhs = true;
382 mmc->ops->set_ios(mmc, &mmc->ios);
383 }
384}
385
386static void sdhci_reinit(struct sdhci_host *host)
387{
388 u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
389
390 sdhci_init(host, 0);
391 sdhci_enable_card_detection(host);
392
393 /*
394 * A change to the card detect bits indicates a change in present state,
395 * refer sdhci_set_card_detection(). A card detect interrupt might have
396 * been missed while the host controller was being reset, so trigger a
397 * rescan to check.
398 */
399 if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT)))
400 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
401}
402
403static void __sdhci_led_activate(struct sdhci_host *host)
404{
405 u8 ctrl;
406
407 if (host->quirks & SDHCI_QUIRK_NO_LED)
408 return;
409
410 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
411 ctrl |= SDHCI_CTRL_LED;
412 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
413}
414
415static void __sdhci_led_deactivate(struct sdhci_host *host)
416{
417 u8 ctrl;
418
419 if (host->quirks & SDHCI_QUIRK_NO_LED)
420 return;
421
422 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
423 ctrl &= ~SDHCI_CTRL_LED;
424 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
425}
426
427#if IS_REACHABLE(CONFIG_LEDS_CLASS)
428static void sdhci_led_control(struct led_classdev *led,
429 enum led_brightness brightness)
430{
431 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
432 unsigned long flags;
433
434 spin_lock_irqsave(&host->lock, flags);
435
436 if (host->runtime_suspended)
437 goto out;
438
439 if (brightness == LED_OFF)
440 __sdhci_led_deactivate(host);
441 else
442 __sdhci_led_activate(host);
443out:
444 spin_unlock_irqrestore(&host->lock, flags);
445}
446
447static int sdhci_led_register(struct sdhci_host *host)
448{
449 struct mmc_host *mmc = host->mmc;
450
451 if (host->quirks & SDHCI_QUIRK_NO_LED)
452 return 0;
453
454 snprintf(host->led_name, sizeof(host->led_name),
455 "%s::", mmc_hostname(mmc));
456
457 host->led.name = host->led_name;
458 host->led.brightness = LED_OFF;
459 host->led.default_trigger = mmc_hostname(mmc);
460 host->led.brightness_set = sdhci_led_control;
461
462 return led_classdev_register(mmc_dev(mmc), &host->led);
463}
464
465static void sdhci_led_unregister(struct sdhci_host *host)
466{
467 if (host->quirks & SDHCI_QUIRK_NO_LED)
468 return;
469
470 led_classdev_unregister(&host->led);
471}
472
473static inline void sdhci_led_activate(struct sdhci_host *host)
474{
475}
476
477static inline void sdhci_led_deactivate(struct sdhci_host *host)
478{
479}
480
481#else
482
483static inline int sdhci_led_register(struct sdhci_host *host)
484{
485 return 0;
486}
487
488static inline void sdhci_led_unregister(struct sdhci_host *host)
489{
490}
491
492static inline void sdhci_led_activate(struct sdhci_host *host)
493{
494 __sdhci_led_activate(host);
495}
496
497static inline void sdhci_led_deactivate(struct sdhci_host *host)
498{
499 __sdhci_led_deactivate(host);
500}
501
502#endif
503
504static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
505 unsigned long timeout)
506{
507 if (sdhci_data_line_cmd(mrq->cmd))
508 mod_timer(&host->data_timer, timeout);
509 else
510 mod_timer(&host->timer, timeout);
511}
512
513static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
514{
515 if (sdhci_data_line_cmd(mrq->cmd))
516 del_timer(&host->data_timer);
517 else
518 del_timer(&host->timer);
519}
520
521static inline bool sdhci_has_requests(struct sdhci_host *host)
522{
523 return host->cmd || host->data_cmd;
524}
525
526/*****************************************************************************\
527 * *
528 * Core functions *
529 * *
530\*****************************************************************************/
531
532static void sdhci_read_block_pio(struct sdhci_host *host)
533{
534 size_t blksize, len, chunk;
535 u32 scratch;
536 u8 *buf;
537
538 DBG("PIO reading\n");
539
540 blksize = host->data->blksz;
541 chunk = 0;
542
543 while (blksize) {
544 BUG_ON(!sg_miter_next(&host->sg_miter));
545
546 len = min(host->sg_miter.length, blksize);
547
548 blksize -= len;
549 host->sg_miter.consumed = len;
550
551 buf = host->sg_miter.addr;
552
553 while (len) {
554 if (chunk == 0) {
555 scratch = sdhci_readl(host, SDHCI_BUFFER);
556 chunk = 4;
557 }
558
559 *buf = scratch & 0xFF;
560
561 buf++;
562 scratch >>= 8;
563 chunk--;
564 len--;
565 }
566 }
567
568 sg_miter_stop(&host->sg_miter);
569}
570
571static void sdhci_write_block_pio(struct sdhci_host *host)
572{
573 size_t blksize, len, chunk;
574 u32 scratch;
575 u8 *buf;
576
577 DBG("PIO writing\n");
578
579 blksize = host->data->blksz;
580 chunk = 0;
581 scratch = 0;
582
583 while (blksize) {
584 BUG_ON(!sg_miter_next(&host->sg_miter));
585
586 len = min(host->sg_miter.length, blksize);
587
588 blksize -= len;
589 host->sg_miter.consumed = len;
590
591 buf = host->sg_miter.addr;
592
593 while (len) {
594 scratch |= (u32)*buf << (chunk * 8);
595
596 buf++;
597 chunk++;
598 len--;
599
600 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
601 sdhci_writel(host, scratch, SDHCI_BUFFER);
602 chunk = 0;
603 scratch = 0;
604 }
605 }
606 }
607
608 sg_miter_stop(&host->sg_miter);
609}
610
611static void sdhci_transfer_pio(struct sdhci_host *host)
612{
613 u32 mask;
614
615 if (host->blocks == 0)
616 return;
617
618 if (host->data->flags & MMC_DATA_READ)
619 mask = SDHCI_DATA_AVAILABLE;
620 else
621 mask = SDHCI_SPACE_AVAILABLE;
622
623 /*
624 * Some controllers (JMicron JMB38x) mess up the buffer bits
625 * for transfers < 4 bytes. As long as it is just one block,
626 * we can ignore the bits.
627 */
628 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
629 (host->data->blocks == 1))
630 mask = ~0;
631
632 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
633 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
634 udelay(100);
635
636 if (host->data->flags & MMC_DATA_READ)
637 sdhci_read_block_pio(host);
638 else
639 sdhci_write_block_pio(host);
640
641 host->blocks--;
642 if (host->blocks == 0)
643 break;
644 }
645
646 DBG("PIO transfer complete.\n");
647}
648
649static int sdhci_pre_dma_transfer(struct sdhci_host *host,
650 struct mmc_data *data, int cookie)
651{
652 int sg_count;
653
654 /*
655 * If the data buffers are already mapped, return the previous
656 * dma_map_sg() result.
657 */
658 if (data->host_cookie == COOKIE_PRE_MAPPED)
659 return data->sg_count;
660
661 /* Bounce write requests to the bounce buffer */
662 if (host->bounce_buffer) {
663 unsigned int length = data->blksz * data->blocks;
664
665 if (length > host->bounce_buffer_size) {
666 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
667 mmc_hostname(host->mmc), length,
668 host->bounce_buffer_size);
669 return -EIO;
670 }
671 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
672 /* Copy the data to the bounce buffer */
673 if (host->ops->copy_to_bounce_buffer) {
674 host->ops->copy_to_bounce_buffer(host,
675 data, length);
676 } else {
677 sg_copy_to_buffer(data->sg, data->sg_len,
678 host->bounce_buffer, length);
679 }
680 }
681 /* Switch ownership to the DMA */
682 dma_sync_single_for_device(mmc_dev(host->mmc),
683 host->bounce_addr,
684 host->bounce_buffer_size,
685 mmc_get_dma_dir(data));
686 /* Just a dummy value */
687 sg_count = 1;
688 } else {
689 /* Just access the data directly from memory */
690 sg_count = dma_map_sg(mmc_dev(host->mmc),
691 data->sg, data->sg_len,
692 mmc_get_dma_dir(data));
693 }
694
695 if (sg_count == 0)
696 return -ENOSPC;
697
698 data->sg_count = sg_count;
699 data->host_cookie = cookie;
700
701 return sg_count;
702}
703
704static char *sdhci_kmap_atomic(struct scatterlist *sg)
705{
706 return kmap_local_page(sg_page(sg)) + sg->offset;
707}
708
709static void sdhci_kunmap_atomic(void *buffer)
710{
711 kunmap_local(buffer);
712}
713
714void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
715 dma_addr_t addr, int len, unsigned int cmd)
716{
717 struct sdhci_adma2_64_desc *dma_desc = *desc;
718
719 /* 32-bit and 64-bit descriptors have these members in same position */
720 dma_desc->cmd = cpu_to_le16(cmd);
721 dma_desc->len = cpu_to_le16(len);
722 dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr));
723
724 if (host->flags & SDHCI_USE_64_BIT_DMA)
725 dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr));
726
727 *desc += host->desc_sz;
728}
729EXPORT_SYMBOL_GPL(sdhci_adma_write_desc);
730
731static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
732 void **desc, dma_addr_t addr,
733 int len, unsigned int cmd)
734{
735 if (host->ops->adma_write_desc)
736 host->ops->adma_write_desc(host, desc, addr, len, cmd);
737 else
738 sdhci_adma_write_desc(host, desc, addr, len, cmd);
739}
740
741static void sdhci_adma_mark_end(void *desc)
742{
743 struct sdhci_adma2_64_desc *dma_desc = desc;
744
745 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
746 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
747}
748
749static void sdhci_adma_table_pre(struct sdhci_host *host,
750 struct mmc_data *data, int sg_count)
751{
752 struct scatterlist *sg;
753 dma_addr_t addr, align_addr;
754 void *desc, *align;
755 char *buffer;
756 int len, offset, i;
757
758 /*
759 * The spec does not specify endianness of descriptor table.
760 * We currently guess that it is LE.
761 */
762
763 host->sg_count = sg_count;
764
765 desc = host->adma_table;
766 align = host->align_buffer;
767
768 align_addr = host->align_addr;
769
770 for_each_sg(data->sg, sg, host->sg_count, i) {
771 addr = sg_dma_address(sg);
772 len = sg_dma_len(sg);
773
774 /*
775 * The SDHCI specification states that ADMA addresses must
776 * be 32-bit aligned. If they aren't, then we use a bounce
777 * buffer for the (up to three) bytes that screw up the
778 * alignment.
779 */
780 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
781 SDHCI_ADMA2_MASK;
782 if (offset) {
783 if (data->flags & MMC_DATA_WRITE) {
784 buffer = sdhci_kmap_atomic(sg);
785 memcpy(align, buffer, offset);
786 sdhci_kunmap_atomic(buffer);
787 }
788
789 /* tran, valid */
790 __sdhci_adma_write_desc(host, &desc, align_addr,
791 offset, ADMA2_TRAN_VALID);
792
793 BUG_ON(offset > 65536);
794
795 align += SDHCI_ADMA2_ALIGN;
796 align_addr += SDHCI_ADMA2_ALIGN;
797
798 addr += offset;
799 len -= offset;
800 }
801
802 /*
803 * The block layer forces a minimum segment size of PAGE_SIZE,
804 * so 'len' can be too big here if PAGE_SIZE >= 64KiB. Write
805 * multiple descriptors, noting that the ADMA table is sized
806 * for 4KiB chunks anyway, so it will be big enough.
807 */
808 while (len > host->max_adma) {
809 int n = 32 * 1024; /* 32KiB*/
810
811 __sdhci_adma_write_desc(host, &desc, addr, n, ADMA2_TRAN_VALID);
812 addr += n;
813 len -= n;
814 }
815
816 /* tran, valid */
817 if (len)
818 __sdhci_adma_write_desc(host, &desc, addr, len,
819 ADMA2_TRAN_VALID);
820
821 /*
822 * If this triggers then we have a calculation bug
823 * somewhere. :/
824 */
825 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
826 }
827
828 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
829 /* Mark the last descriptor as the terminating descriptor */
830 if (desc != host->adma_table) {
831 desc -= host->desc_sz;
832 sdhci_adma_mark_end(desc);
833 }
834 } else {
835 /* Add a terminating entry - nop, end, valid */
836 __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
837 }
838}
839
840static void sdhci_adma_table_post(struct sdhci_host *host,
841 struct mmc_data *data)
842{
843 struct scatterlist *sg;
844 int i, size;
845 void *align;
846 char *buffer;
847
848 if (data->flags & MMC_DATA_READ) {
849 bool has_unaligned = false;
850
851 /* Do a quick scan of the SG list for any unaligned mappings */
852 for_each_sg(data->sg, sg, host->sg_count, i)
853 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
854 has_unaligned = true;
855 break;
856 }
857
858 if (has_unaligned) {
859 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
860 data->sg_len, DMA_FROM_DEVICE);
861
862 align = host->align_buffer;
863
864 for_each_sg(data->sg, sg, host->sg_count, i) {
865 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
866 size = SDHCI_ADMA2_ALIGN -
867 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
868
869 buffer = sdhci_kmap_atomic(sg);
870 memcpy(buffer, align, size);
871 sdhci_kunmap_atomic(buffer);
872
873 align += SDHCI_ADMA2_ALIGN;
874 }
875 }
876 }
877 }
878}
879
880static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
881{
882 sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
883 if (host->flags & SDHCI_USE_64_BIT_DMA)
884 sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
885}
886
887static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
888{
889 if (host->bounce_buffer)
890 return host->bounce_addr;
891 else
892 return sg_dma_address(host->data->sg);
893}
894
895static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
896{
897 if (host->v4_mode)
898 sdhci_set_adma_addr(host, addr);
899 else
900 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
901}
902
903static unsigned int sdhci_target_timeout(struct sdhci_host *host,
904 struct mmc_command *cmd,
905 struct mmc_data *data)
906{
907 unsigned int target_timeout;
908
909 /* timeout in us */
910 if (!data) {
911 target_timeout = cmd->busy_timeout * 1000;
912 } else {
913 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
914 if (host->clock && data->timeout_clks) {
915 unsigned long long val;
916
917 /*
918 * data->timeout_clks is in units of clock cycles.
919 * host->clock is in Hz. target_timeout is in us.
920 * Hence, us = 1000000 * cycles / Hz. Round up.
921 */
922 val = 1000000ULL * data->timeout_clks;
923 if (do_div(val, host->clock))
924 target_timeout++;
925 target_timeout += val;
926 }
927 }
928
929 return target_timeout;
930}
931
932static void sdhci_calc_sw_timeout(struct sdhci_host *host,
933 struct mmc_command *cmd)
934{
935 struct mmc_data *data = cmd->data;
936 struct mmc_host *mmc = host->mmc;
937 struct mmc_ios *ios = &mmc->ios;
938 unsigned char bus_width = 1 << ios->bus_width;
939 unsigned int blksz;
940 unsigned int freq;
941 u64 target_timeout;
942 u64 transfer_time;
943
944 target_timeout = sdhci_target_timeout(host, cmd, data);
945 target_timeout *= NSEC_PER_USEC;
946
947 if (data) {
948 blksz = data->blksz;
949 freq = mmc->actual_clock ? : host->clock;
950 transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
951 do_div(transfer_time, freq);
952 /* multiply by '2' to account for any unknowns */
953 transfer_time = transfer_time * 2;
954 /* calculate timeout for the entire data */
955 host->data_timeout = data->blocks * target_timeout +
956 transfer_time;
957 } else {
958 host->data_timeout = target_timeout;
959 }
960
961 if (host->data_timeout)
962 host->data_timeout += MMC_CMD_TRANSFER_TIME;
963}
964
965static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
966 bool *too_big)
967{
968 u8 count;
969 struct mmc_data *data;
970 unsigned target_timeout, current_timeout;
971
972 *too_big = false;
973
974 /*
975 * If the host controller provides us with an incorrect timeout
976 * value, just skip the check and use the maximum. The hardware may take
977 * longer to time out, but that's much better than having a too-short
978 * timeout value.
979 */
980 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
981 return host->max_timeout_count;
982
983 /* Unspecified command, assume max */
984 if (cmd == NULL)
985 return host->max_timeout_count;
986
987 data = cmd->data;
988 /* Unspecified timeout, assume max */
989 if (!data && !cmd->busy_timeout)
990 return host->max_timeout_count;
991
992 /* timeout in us */
993 target_timeout = sdhci_target_timeout(host, cmd, data);
994
995 /*
996 * Figure out needed cycles.
997 * We do this in steps in order to fit inside a 32 bit int.
998 * The first step is the minimum timeout, which will have a
999 * minimum resolution of 6 bits:
1000 * (1) 2^13*1000 > 2^22,
1001 * (2) host->timeout_clk < 2^16
1002 * =>
1003 * (1) / (2) > 2^6
1004 */
1005 count = 0;
1006 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
1007 while (current_timeout < target_timeout) {
1008 count++;
1009 current_timeout <<= 1;
1010 if (count > host->max_timeout_count) {
1011 if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
1012 DBG("Too large timeout 0x%x requested for CMD%d!\n",
1013 count, cmd->opcode);
1014 count = host->max_timeout_count;
1015 *too_big = true;
1016 break;
1017 }
1018 }
1019
1020 return count;
1021}
1022
1023static void sdhci_set_transfer_irqs(struct sdhci_host *host)
1024{
1025 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
1026 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
1027
1028 if (host->flags & SDHCI_REQ_USE_DMA)
1029 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
1030 else
1031 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
1032
1033 if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
1034 host->ier |= SDHCI_INT_AUTO_CMD_ERR;
1035 else
1036 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
1037
1038 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1039 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1040}
1041
1042void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
1043{
1044 if (enable)
1045 host->ier |= SDHCI_INT_DATA_TIMEOUT;
1046 else
1047 host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
1048 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1049 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1050}
1051EXPORT_SYMBOL_GPL(sdhci_set_data_timeout_irq);
1052
1053void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1054{
1055 bool too_big = false;
1056 u8 count = sdhci_calc_timeout(host, cmd, &too_big);
1057
1058 if (too_big &&
1059 host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
1060 sdhci_calc_sw_timeout(host, cmd);
1061 sdhci_set_data_timeout_irq(host, false);
1062 } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
1063 sdhci_set_data_timeout_irq(host, true);
1064 }
1065
1066 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
1067}
1068EXPORT_SYMBOL_GPL(__sdhci_set_timeout);
1069
1070static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1071{
1072 if (host->ops->set_timeout)
1073 host->ops->set_timeout(host, cmd);
1074 else
1075 __sdhci_set_timeout(host, cmd);
1076}
1077
1078static void sdhci_initialize_data(struct sdhci_host *host,
1079 struct mmc_data *data)
1080{
1081 WARN_ON(host->data);
1082
1083 /* Sanity checks */
1084 BUG_ON(data->blksz * data->blocks > 524288);
1085 BUG_ON(data->blksz > host->mmc->max_blk_size);
1086 BUG_ON(data->blocks > 65535);
1087
1088 host->data = data;
1089 host->data_early = 0;
1090 host->data->bytes_xfered = 0;
1091}
1092
1093static inline void sdhci_set_block_info(struct sdhci_host *host,
1094 struct mmc_data *data)
1095{
1096 /* Set the DMA boundary value and block size */
1097 sdhci_writew(host,
1098 SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
1099 SDHCI_BLOCK_SIZE);
1100 /*
1101 * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
1102 * can be supported, in that case 16-bit block count register must be 0.
1103 */
1104 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1105 (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
1106 if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
1107 sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
1108 sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
1109 } else {
1110 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1111 }
1112}
1113
1114static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
1115{
1116 struct mmc_data *data = cmd->data;
1117
1118 sdhci_initialize_data(host, data);
1119
1120 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1121 struct scatterlist *sg;
1122 unsigned int length_mask, offset_mask;
1123 int i;
1124
1125 host->flags |= SDHCI_REQ_USE_DMA;
1126
1127 /*
1128 * FIXME: This doesn't account for merging when mapping the
1129 * scatterlist.
1130 *
1131 * The assumption here being that alignment and lengths are
1132 * the same after DMA mapping to device address space.
1133 */
1134 length_mask = 0;
1135 offset_mask = 0;
1136 if (host->flags & SDHCI_USE_ADMA) {
1137 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
1138 length_mask = 3;
1139 /*
1140 * As we use up to 3 byte chunks to work
1141 * around alignment problems, we need to
1142 * check the offset as well.
1143 */
1144 offset_mask = 3;
1145 }
1146 } else {
1147 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
1148 length_mask = 3;
1149 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
1150 offset_mask = 3;
1151 }
1152
1153 if (unlikely(length_mask | offset_mask)) {
1154 for_each_sg(data->sg, sg, data->sg_len, i) {
1155 if (sg->length & length_mask) {
1156 DBG("Reverting to PIO because of transfer size (%d)\n",
1157 sg->length);
1158 host->flags &= ~SDHCI_REQ_USE_DMA;
1159 break;
1160 }
1161 if (sg->offset & offset_mask) {
1162 DBG("Reverting to PIO because of bad alignment\n");
1163 host->flags &= ~SDHCI_REQ_USE_DMA;
1164 break;
1165 }
1166 }
1167 }
1168 }
1169
1170 if (host->flags & SDHCI_REQ_USE_DMA) {
1171 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1172
1173 if (sg_cnt <= 0) {
1174 /*
1175 * This only happens when someone fed
1176 * us an invalid request.
1177 */
1178 WARN_ON(1);
1179 host->flags &= ~SDHCI_REQ_USE_DMA;
1180 } else if (host->flags & SDHCI_USE_ADMA) {
1181 sdhci_adma_table_pre(host, data, sg_cnt);
1182 sdhci_set_adma_addr(host, host->adma_addr);
1183 } else {
1184 WARN_ON(sg_cnt != 1);
1185 sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
1186 }
1187 }
1188
1189 sdhci_config_dma(host);
1190
1191 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
1192 int flags;
1193
1194 flags = SG_MITER_ATOMIC;
1195 if (host->data->flags & MMC_DATA_READ)
1196 flags |= SG_MITER_TO_SG;
1197 else
1198 flags |= SG_MITER_FROM_SG;
1199 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1200 host->blocks = data->blocks;
1201 }
1202
1203 sdhci_set_transfer_irqs(host);
1204
1205 sdhci_set_block_info(host, data);
1206}
1207
1208#if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
1209
1210static int sdhci_external_dma_init(struct sdhci_host *host)
1211{
1212 int ret = 0;
1213 struct mmc_host *mmc = host->mmc;
1214
1215 host->tx_chan = dma_request_chan(mmc_dev(mmc), "tx");
1216 if (IS_ERR(host->tx_chan)) {
1217 ret = PTR_ERR(host->tx_chan);
1218 if (ret != -EPROBE_DEFER)
1219 pr_warn("Failed to request TX DMA channel.\n");
1220 host->tx_chan = NULL;
1221 return ret;
1222 }
1223
1224 host->rx_chan = dma_request_chan(mmc_dev(mmc), "rx");
1225 if (IS_ERR(host->rx_chan)) {
1226 if (host->tx_chan) {
1227 dma_release_channel(host->tx_chan);
1228 host->tx_chan = NULL;
1229 }
1230
1231 ret = PTR_ERR(host->rx_chan);
1232 if (ret != -EPROBE_DEFER)
1233 pr_warn("Failed to request RX DMA channel.\n");
1234 host->rx_chan = NULL;
1235 }
1236
1237 return ret;
1238}
1239
1240static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1241 struct mmc_data *data)
1242{
1243 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
1244}
1245
1246static int sdhci_external_dma_setup(struct sdhci_host *host,
1247 struct mmc_command *cmd)
1248{
1249 int ret, i;
1250 enum dma_transfer_direction dir;
1251 struct dma_async_tx_descriptor *desc;
1252 struct mmc_data *data = cmd->data;
1253 struct dma_chan *chan;
1254 struct dma_slave_config cfg;
1255 dma_cookie_t cookie;
1256 int sg_cnt;
1257
1258 if (!host->mapbase)
1259 return -EINVAL;
1260
1261 memset(&cfg, 0, sizeof(cfg));
1262 cfg.src_addr = host->mapbase + SDHCI_BUFFER;
1263 cfg.dst_addr = host->mapbase + SDHCI_BUFFER;
1264 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1265 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1266 cfg.src_maxburst = data->blksz / 4;
1267 cfg.dst_maxburst = data->blksz / 4;
1268
1269 /* Sanity check: all the SG entries must be aligned by block size. */
1270 for (i = 0; i < data->sg_len; i++) {
1271 if ((data->sg + i)->length % data->blksz)
1272 return -EINVAL;
1273 }
1274
1275 chan = sdhci_external_dma_channel(host, data);
1276
1277 ret = dmaengine_slave_config(chan, &cfg);
1278 if (ret)
1279 return ret;
1280
1281 sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1282 if (sg_cnt <= 0)
1283 return -EINVAL;
1284
1285 dir = data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
1286 desc = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, dir,
1287 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1288 if (!desc)
1289 return -EINVAL;
1290
1291 desc->callback = NULL;
1292 desc->callback_param = NULL;
1293
1294 cookie = dmaengine_submit(desc);
1295 if (dma_submit_error(cookie))
1296 ret = cookie;
1297
1298 return ret;
1299}
1300
1301static void sdhci_external_dma_release(struct sdhci_host *host)
1302{
1303 if (host->tx_chan) {
1304 dma_release_channel(host->tx_chan);
1305 host->tx_chan = NULL;
1306 }
1307
1308 if (host->rx_chan) {
1309 dma_release_channel(host->rx_chan);
1310 host->rx_chan = NULL;
1311 }
1312
1313 sdhci_switch_external_dma(host, false);
1314}
1315
1316static void __sdhci_external_dma_prepare_data(struct sdhci_host *host,
1317 struct mmc_command *cmd)
1318{
1319 struct mmc_data *data = cmd->data;
1320
1321 sdhci_initialize_data(host, data);
1322
1323 host->flags |= SDHCI_REQ_USE_DMA;
1324 sdhci_set_transfer_irqs(host);
1325
1326 sdhci_set_block_info(host, data);
1327}
1328
1329static void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1330 struct mmc_command *cmd)
1331{
1332 if (!sdhci_external_dma_setup(host, cmd)) {
1333 __sdhci_external_dma_prepare_data(host, cmd);
1334 } else {
1335 sdhci_external_dma_release(host);
1336 pr_err("%s: Cannot use external DMA, switch to the DMA/PIO which standard SDHCI provides.\n",
1337 mmc_hostname(host->mmc));
1338 sdhci_prepare_data(host, cmd);
1339 }
1340}
1341
1342static void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1343 struct mmc_command *cmd)
1344{
1345 struct dma_chan *chan;
1346
1347 if (!cmd->data)
1348 return;
1349
1350 chan = sdhci_external_dma_channel(host, cmd->data);
1351 if (chan)
1352 dma_async_issue_pending(chan);
1353}
1354
1355#else
1356
1357static inline int sdhci_external_dma_init(struct sdhci_host *host)
1358{
1359 return -EOPNOTSUPP;
1360}
1361
1362static inline void sdhci_external_dma_release(struct sdhci_host *host)
1363{
1364}
1365
1366static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1367 struct mmc_command *cmd)
1368{
1369 /* This should never happen */
1370 WARN_ON_ONCE(1);
1371}
1372
1373static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1374 struct mmc_command *cmd)
1375{
1376}
1377
1378static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1379 struct mmc_data *data)
1380{
1381 return NULL;
1382}
1383
1384#endif
1385
1386void sdhci_switch_external_dma(struct sdhci_host *host, bool en)
1387{
1388 host->use_external_dma = en;
1389}
1390EXPORT_SYMBOL_GPL(sdhci_switch_external_dma);
1391
1392static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
1393 struct mmc_request *mrq)
1394{
1395 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
1396 !mrq->cap_cmd_during_tfr;
1397}
1398
1399static inline bool sdhci_auto_cmd23(struct sdhci_host *host,
1400 struct mmc_request *mrq)
1401{
1402 return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
1403}
1404
1405static inline bool sdhci_manual_cmd23(struct sdhci_host *host,
1406 struct mmc_request *mrq)
1407{
1408 return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23);
1409}
1410
1411static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
1412 struct mmc_command *cmd,
1413 u16 *mode)
1414{
1415 bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
1416 (cmd->opcode != SD_IO_RW_EXTENDED);
1417 bool use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq);
1418 u16 ctrl2;
1419
1420 /*
1421 * In case of Version 4.10 or later, use of 'Auto CMD Auto
1422 * Select' is recommended rather than use of 'Auto CMD12
1423 * Enable' or 'Auto CMD23 Enable'. We require Version 4 Mode
1424 * here because some controllers (e.g sdhci-of-dwmshc) expect it.
1425 */
1426 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1427 (use_cmd12 || use_cmd23)) {
1428 *mode |= SDHCI_TRNS_AUTO_SEL;
1429
1430 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1431 if (use_cmd23)
1432 ctrl2 |= SDHCI_CMD23_ENABLE;
1433 else
1434 ctrl2 &= ~SDHCI_CMD23_ENABLE;
1435 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
1436
1437 return;
1438 }
1439
1440 /*
1441 * If we are sending CMD23, CMD12 never gets sent
1442 * on successful completion (so no Auto-CMD12).
1443 */
1444 if (use_cmd12)
1445 *mode |= SDHCI_TRNS_AUTO_CMD12;
1446 else if (use_cmd23)
1447 *mode |= SDHCI_TRNS_AUTO_CMD23;
1448}
1449
1450static void sdhci_set_transfer_mode(struct sdhci_host *host,
1451 struct mmc_command *cmd)
1452{
1453 u16 mode = 0;
1454 struct mmc_data *data = cmd->data;
1455
1456 if (data == NULL) {
1457 if (host->quirks2 &
1458 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
1459 /* must not clear SDHCI_TRANSFER_MODE when tuning */
1460 if (!mmc_op_tuning(cmd->opcode))
1461 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1462 } else {
1463 /* clear Auto CMD settings for no data CMDs */
1464 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1465 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
1466 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
1467 }
1468 return;
1469 }
1470
1471 WARN_ON(!host->data);
1472
1473 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1474 mode = SDHCI_TRNS_BLK_CNT_EN;
1475
1476 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
1477 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
1478 sdhci_auto_cmd_select(host, cmd, &mode);
1479 if (sdhci_auto_cmd23(host, cmd->mrq))
1480 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
1481 }
1482
1483 if (data->flags & MMC_DATA_READ)
1484 mode |= SDHCI_TRNS_READ;
1485 if (host->flags & SDHCI_REQ_USE_DMA)
1486 mode |= SDHCI_TRNS_DMA;
1487
1488 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1489}
1490
1491static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
1492{
1493 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1494 ((mrq->cmd && mrq->cmd->error) ||
1495 (mrq->sbc && mrq->sbc->error) ||
1496 (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
1497 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1498}
1499
1500static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq)
1501{
1502 int i;
1503
1504 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1505 if (host->mrqs_done[i] == mrq) {
1506 WARN_ON(1);
1507 return;
1508 }
1509 }
1510
1511 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1512 if (!host->mrqs_done[i]) {
1513 host->mrqs_done[i] = mrq;
1514 break;
1515 }
1516 }
1517
1518 WARN_ON(i >= SDHCI_MAX_MRQS);
1519}
1520
1521static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1522{
1523 if (host->cmd && host->cmd->mrq == mrq)
1524 host->cmd = NULL;
1525
1526 if (host->data_cmd && host->data_cmd->mrq == mrq)
1527 host->data_cmd = NULL;
1528
1529 if (host->deferred_cmd && host->deferred_cmd->mrq == mrq)
1530 host->deferred_cmd = NULL;
1531
1532 if (host->data && host->data->mrq == mrq)
1533 host->data = NULL;
1534
1535 if (sdhci_needs_reset(host, mrq))
1536 host->pending_reset = true;
1537
1538 sdhci_set_mrq_done(host, mrq);
1539
1540 sdhci_del_timer(host, mrq);
1541
1542 if (!sdhci_has_requests(host))
1543 sdhci_led_deactivate(host);
1544}
1545
1546static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1547{
1548 __sdhci_finish_mrq(host, mrq);
1549
1550 queue_work(host->complete_wq, &host->complete_work);
1551}
1552
1553static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout)
1554{
1555 struct mmc_command *data_cmd = host->data_cmd;
1556 struct mmc_data *data = host->data;
1557
1558 host->data = NULL;
1559 host->data_cmd = NULL;
1560
1561 /*
1562 * The controller needs a reset of internal state machines upon error
1563 * conditions.
1564 */
1565 if (data->error) {
1566 if (!host->cmd || host->cmd == data_cmd)
1567 sdhci_reset_for(host, REQUEST_ERROR);
1568 else
1569 sdhci_reset_for(host, REQUEST_ERROR_DATA_ONLY);
1570 }
1571
1572 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1573 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1574 sdhci_adma_table_post(host, data);
1575
1576 /*
1577 * The specification states that the block count register must
1578 * be updated, but it does not specify at what point in the
1579 * data flow. That makes the register entirely useless to read
1580 * back so we have to assume that nothing made it to the card
1581 * in the event of an error.
1582 */
1583 if (data->error)
1584 data->bytes_xfered = 0;
1585 else
1586 data->bytes_xfered = data->blksz * data->blocks;
1587
1588 /*
1589 * Need to send CMD12 if -
1590 * a) open-ended multiblock transfer not using auto CMD12 (no CMD23)
1591 * b) error in multiblock transfer
1592 */
1593 if (data->stop &&
1594 ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) ||
1595 data->error)) {
1596 /*
1597 * 'cap_cmd_during_tfr' request must not use the command line
1598 * after mmc_command_done() has been called. It is upper layer's
1599 * responsibility to send the stop command if required.
1600 */
1601 if (data->mrq->cap_cmd_during_tfr) {
1602 __sdhci_finish_mrq(host, data->mrq);
1603 } else {
1604 /* Avoid triggering warning in sdhci_send_command() */
1605 host->cmd = NULL;
1606 if (!sdhci_send_command(host, data->stop)) {
1607 if (sw_data_timeout) {
1608 /*
1609 * This is anyway a sw data timeout, so
1610 * give up now.
1611 */
1612 data->stop->error = -EIO;
1613 __sdhci_finish_mrq(host, data->mrq);
1614 } else {
1615 WARN_ON(host->deferred_cmd);
1616 host->deferred_cmd = data->stop;
1617 }
1618 }
1619 }
1620 } else {
1621 __sdhci_finish_mrq(host, data->mrq);
1622 }
1623}
1624
1625static void sdhci_finish_data(struct sdhci_host *host)
1626{
1627 __sdhci_finish_data(host, false);
1628}
1629
1630static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1631{
1632 int flags;
1633 u32 mask;
1634 unsigned long timeout;
1635
1636 WARN_ON(host->cmd);
1637
1638 /* Initially, a command has no error */
1639 cmd->error = 0;
1640
1641 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1642 cmd->opcode == MMC_STOP_TRANSMISSION)
1643 cmd->flags |= MMC_RSP_BUSY;
1644
1645 mask = SDHCI_CMD_INHIBIT;
1646 if (sdhci_data_line_cmd(cmd))
1647 mask |= SDHCI_DATA_INHIBIT;
1648
1649 /* We shouldn't wait for data inihibit for stop commands, even
1650 though they might use busy signaling */
1651 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1652 mask &= ~SDHCI_DATA_INHIBIT;
1653
1654 if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)
1655 return false;
1656
1657 host->cmd = cmd;
1658 host->data_timeout = 0;
1659 if (sdhci_data_line_cmd(cmd)) {
1660 WARN_ON(host->data_cmd);
1661 host->data_cmd = cmd;
1662 sdhci_set_timeout(host, cmd);
1663 }
1664
1665 if (cmd->data) {
1666 if (host->use_external_dma)
1667 sdhci_external_dma_prepare_data(host, cmd);
1668 else
1669 sdhci_prepare_data(host, cmd);
1670 }
1671
1672 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1673
1674 sdhci_set_transfer_mode(host, cmd);
1675
1676 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1677 WARN_ONCE(1, "Unsupported response type!\n");
1678 /*
1679 * This does not happen in practice because 136-bit response
1680 * commands never have busy waiting, so rather than complicate
1681 * the error path, just remove busy waiting and continue.
1682 */
1683 cmd->flags &= ~MMC_RSP_BUSY;
1684 }
1685
1686 if (!(cmd->flags & MMC_RSP_PRESENT))
1687 flags = SDHCI_CMD_RESP_NONE;
1688 else if (cmd->flags & MMC_RSP_136)
1689 flags = SDHCI_CMD_RESP_LONG;
1690 else if (cmd->flags & MMC_RSP_BUSY)
1691 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1692 else
1693 flags = SDHCI_CMD_RESP_SHORT;
1694
1695 if (cmd->flags & MMC_RSP_CRC)
1696 flags |= SDHCI_CMD_CRC;
1697 if (cmd->flags & MMC_RSP_OPCODE)
1698 flags |= SDHCI_CMD_INDEX;
1699
1700 /* CMD19 is special in that the Data Present Select should be set */
1701 if (cmd->data || mmc_op_tuning(cmd->opcode))
1702 flags |= SDHCI_CMD_DATA;
1703
1704 timeout = jiffies;
1705 if (host->data_timeout)
1706 timeout += nsecs_to_jiffies(host->data_timeout);
1707 else if (!cmd->data && cmd->busy_timeout > 9000)
1708 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1709 else
1710 timeout += 10 * HZ;
1711 sdhci_mod_timer(host, cmd->mrq, timeout);
1712
1713 if (host->use_external_dma)
1714 sdhci_external_dma_pre_transfer(host, cmd);
1715
1716 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1717
1718 return true;
1719}
1720
1721static bool sdhci_present_error(struct sdhci_host *host,
1722 struct mmc_command *cmd, bool present)
1723{
1724 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1725 cmd->error = -ENOMEDIUM;
1726 return true;
1727 }
1728
1729 return false;
1730}
1731
1732static bool sdhci_send_command_retry(struct sdhci_host *host,
1733 struct mmc_command *cmd,
1734 unsigned long flags)
1735 __releases(host->lock)
1736 __acquires(host->lock)
1737{
1738 struct mmc_command *deferred_cmd = host->deferred_cmd;
1739 int timeout = 10; /* Approx. 10 ms */
1740 bool present;
1741
1742 while (!sdhci_send_command(host, cmd)) {
1743 if (!timeout--) {
1744 pr_err("%s: Controller never released inhibit bit(s).\n",
1745 mmc_hostname(host->mmc));
1746 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
1747 sdhci_dumpregs(host);
1748 cmd->error = -EIO;
1749 return false;
1750 }
1751
1752 spin_unlock_irqrestore(&host->lock, flags);
1753
1754 usleep_range(1000, 1250);
1755
1756 present = host->mmc->ops->get_cd(host->mmc);
1757
1758 spin_lock_irqsave(&host->lock, flags);
1759
1760 /* A deferred command might disappear, handle that */
1761 if (cmd == deferred_cmd && cmd != host->deferred_cmd)
1762 return true;
1763
1764 if (sdhci_present_error(host, cmd, present))
1765 return false;
1766 }
1767
1768 if (cmd == host->deferred_cmd)
1769 host->deferred_cmd = NULL;
1770
1771 return true;
1772}
1773
1774static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1775{
1776 int i, reg;
1777
1778 for (i = 0; i < 4; i++) {
1779 reg = SDHCI_RESPONSE + (3 - i) * 4;
1780 cmd->resp[i] = sdhci_readl(host, reg);
1781 }
1782
1783 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1784 return;
1785
1786 /* CRC is stripped so we need to do some shifting */
1787 for (i = 0; i < 4; i++) {
1788 cmd->resp[i] <<= 8;
1789 if (i != 3)
1790 cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1791 }
1792}
1793
1794static void sdhci_finish_command(struct sdhci_host *host)
1795{
1796 struct mmc_command *cmd = host->cmd;
1797
1798 host->cmd = NULL;
1799
1800 if (cmd->flags & MMC_RSP_PRESENT) {
1801 if (cmd->flags & MMC_RSP_136) {
1802 sdhci_read_rsp_136(host, cmd);
1803 } else {
1804 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1805 }
1806 }
1807
1808 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1809 mmc_command_done(host->mmc, cmd->mrq);
1810
1811 /*
1812 * The host can send and interrupt when the busy state has
1813 * ended, allowing us to wait without wasting CPU cycles.
1814 * The busy signal uses DAT0 so this is similar to waiting
1815 * for data to complete.
1816 *
1817 * Note: The 1.0 specification is a bit ambiguous about this
1818 * feature so there might be some problems with older
1819 * controllers.
1820 */
1821 if (cmd->flags & MMC_RSP_BUSY) {
1822 if (cmd->data) {
1823 DBG("Cannot wait for busy signal when also doing a data transfer");
1824 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1825 cmd == host->data_cmd) {
1826 /* Command complete before busy is ended */
1827 return;
1828 }
1829 }
1830
1831 /* Finished CMD23, now send actual command. */
1832 if (cmd == cmd->mrq->sbc) {
1833 if (!sdhci_send_command(host, cmd->mrq->cmd)) {
1834 WARN_ON(host->deferred_cmd);
1835 host->deferred_cmd = cmd->mrq->cmd;
1836 }
1837 } else {
1838
1839 /* Processed actual command. */
1840 if (host->data && host->data_early)
1841 sdhci_finish_data(host);
1842
1843 if (!cmd->data)
1844 __sdhci_finish_mrq(host, cmd->mrq);
1845 }
1846}
1847
1848static u16 sdhci_get_preset_value(struct sdhci_host *host)
1849{
1850 u16 preset = 0;
1851
1852 switch (host->timing) {
1853 case MMC_TIMING_MMC_HS:
1854 case MMC_TIMING_SD_HS:
1855 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HIGH_SPEED);
1856 break;
1857 case MMC_TIMING_UHS_SDR12:
1858 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1859 break;
1860 case MMC_TIMING_UHS_SDR25:
1861 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1862 break;
1863 case MMC_TIMING_UHS_SDR50:
1864 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1865 break;
1866 case MMC_TIMING_UHS_SDR104:
1867 case MMC_TIMING_MMC_HS200:
1868 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1869 break;
1870 case MMC_TIMING_UHS_DDR50:
1871 case MMC_TIMING_MMC_DDR52:
1872 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1873 break;
1874 case MMC_TIMING_MMC_HS400:
1875 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1876 break;
1877 default:
1878 pr_warn("%s: Invalid UHS-I mode selected\n",
1879 mmc_hostname(host->mmc));
1880 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1881 break;
1882 }
1883 return preset;
1884}
1885
1886u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1887 unsigned int *actual_clock)
1888{
1889 int div = 0; /* Initialized for compiler warning */
1890 int real_div = div, clk_mul = 1;
1891 u16 clk = 0;
1892 bool switch_base_clk = false;
1893
1894 if (host->version >= SDHCI_SPEC_300) {
1895 if (host->preset_enabled) {
1896 u16 pre_val;
1897
1898 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1899 pre_val = sdhci_get_preset_value(host);
1900 div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
1901 if (host->clk_mul &&
1902 (pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
1903 clk = SDHCI_PROG_CLOCK_MODE;
1904 real_div = div + 1;
1905 clk_mul = host->clk_mul;
1906 } else {
1907 real_div = max_t(int, 1, div << 1);
1908 }
1909 goto clock_set;
1910 }
1911
1912 /*
1913 * Check if the Host Controller supports Programmable Clock
1914 * Mode.
1915 */
1916 if (host->clk_mul) {
1917 for (div = 1; div <= 1024; div++) {
1918 if ((host->max_clk * host->clk_mul / div)
1919 <= clock)
1920 break;
1921 }
1922 if ((host->max_clk * host->clk_mul / div) <= clock) {
1923 /*
1924 * Set Programmable Clock Mode in the Clock
1925 * Control register.
1926 */
1927 clk = SDHCI_PROG_CLOCK_MODE;
1928 real_div = div;
1929 clk_mul = host->clk_mul;
1930 div--;
1931 } else {
1932 /*
1933 * Divisor can be too small to reach clock
1934 * speed requirement. Then use the base clock.
1935 */
1936 switch_base_clk = true;
1937 }
1938 }
1939
1940 if (!host->clk_mul || switch_base_clk) {
1941 /* Version 3.00 divisors must be a multiple of 2. */
1942 if (host->max_clk <= clock)
1943 div = 1;
1944 else {
1945 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1946 div += 2) {
1947 if ((host->max_clk / div) <= clock)
1948 break;
1949 }
1950 }
1951 real_div = div;
1952 div >>= 1;
1953 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1954 && !div && host->max_clk <= 25000000)
1955 div = 1;
1956 }
1957 } else {
1958 /* Version 2.00 divisors must be a power of 2. */
1959 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1960 if ((host->max_clk / div) <= clock)
1961 break;
1962 }
1963 real_div = div;
1964 div >>= 1;
1965 }
1966
1967clock_set:
1968 if (real_div)
1969 *actual_clock = (host->max_clk * clk_mul) / real_div;
1970 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1971 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1972 << SDHCI_DIVIDER_HI_SHIFT;
1973
1974 return clk;
1975}
1976EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1977
1978void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1979{
1980 ktime_t timeout;
1981
1982 clk |= SDHCI_CLOCK_INT_EN;
1983 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1984
1985 /* Wait max 150 ms */
1986 timeout = ktime_add_ms(ktime_get(), 150);
1987 while (1) {
1988 bool timedout = ktime_after(ktime_get(), timeout);
1989
1990 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1991 if (clk & SDHCI_CLOCK_INT_STABLE)
1992 break;
1993 if (timedout) {
1994 pr_err("%s: Internal clock never stabilised.\n",
1995 mmc_hostname(host->mmc));
1996 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
1997 sdhci_dumpregs(host);
1998 return;
1999 }
2000 udelay(10);
2001 }
2002
2003 if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
2004 clk |= SDHCI_CLOCK_PLL_EN;
2005 clk &= ~SDHCI_CLOCK_INT_STABLE;
2006 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2007
2008 /* Wait max 150 ms */
2009 timeout = ktime_add_ms(ktime_get(), 150);
2010 while (1) {
2011 bool timedout = ktime_after(ktime_get(), timeout);
2012
2013 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2014 if (clk & SDHCI_CLOCK_INT_STABLE)
2015 break;
2016 if (timedout) {
2017 pr_err("%s: PLL clock never stabilised.\n",
2018 mmc_hostname(host->mmc));
2019 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
2020 sdhci_dumpregs(host);
2021 return;
2022 }
2023 udelay(10);
2024 }
2025 }
2026
2027 clk |= SDHCI_CLOCK_CARD_EN;
2028 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2029}
2030EXPORT_SYMBOL_GPL(sdhci_enable_clk);
2031
2032void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
2033{
2034 u16 clk;
2035
2036 host->mmc->actual_clock = 0;
2037
2038 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
2039
2040 if (clock == 0)
2041 return;
2042
2043 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
2044 sdhci_enable_clk(host, clk);
2045}
2046EXPORT_SYMBOL_GPL(sdhci_set_clock);
2047
2048static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
2049 unsigned short vdd)
2050{
2051 struct mmc_host *mmc = host->mmc;
2052
2053 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2054
2055 if (mode != MMC_POWER_OFF)
2056 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
2057 else
2058 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2059}
2060
2061void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
2062 unsigned short vdd)
2063{
2064 u8 pwr = 0;
2065
2066 if (mode != MMC_POWER_OFF) {
2067 switch (1 << vdd) {
2068 case MMC_VDD_165_195:
2069 /*
2070 * Without a regulator, SDHCI does not support 2.0v
2071 * so we only get here if the driver deliberately
2072 * added the 2.0v range to ocr_avail. Map it to 1.8v
2073 * for the purpose of turning on the power.
2074 */
2075 case MMC_VDD_20_21:
2076 pwr = SDHCI_POWER_180;
2077 break;
2078 case MMC_VDD_29_30:
2079 case MMC_VDD_30_31:
2080 pwr = SDHCI_POWER_300;
2081 break;
2082 case MMC_VDD_32_33:
2083 case MMC_VDD_33_34:
2084 /*
2085 * 3.4 ~ 3.6V are valid only for those platforms where it's
2086 * known that the voltage range is supported by hardware.
2087 */
2088 case MMC_VDD_34_35:
2089 case MMC_VDD_35_36:
2090 pwr = SDHCI_POWER_330;
2091 break;
2092 default:
2093 WARN(1, "%s: Invalid vdd %#x\n",
2094 mmc_hostname(host->mmc), vdd);
2095 break;
2096 }
2097 }
2098
2099 if (host->pwr == pwr)
2100 return;
2101
2102 host->pwr = pwr;
2103
2104 if (pwr == 0) {
2105 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2106 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2107 sdhci_runtime_pm_bus_off(host);
2108 } else {
2109 /*
2110 * Spec says that we should clear the power reg before setting
2111 * a new value. Some controllers don't seem to like this though.
2112 */
2113 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
2114 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2115
2116 /*
2117 * At least the Marvell CaFe chip gets confused if we set the
2118 * voltage and set turn on power at the same time, so set the
2119 * voltage first.
2120 */
2121 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
2122 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2123
2124 pwr |= SDHCI_POWER_ON;
2125
2126 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2127
2128 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2129 sdhci_runtime_pm_bus_on(host);
2130
2131 /*
2132 * Some controllers need an extra 10ms delay of 10ms before
2133 * they can apply clock after applying power
2134 */
2135 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
2136 mdelay(10);
2137 }
2138}
2139EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
2140
2141void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
2142 unsigned short vdd)
2143{
2144 if (IS_ERR(host->mmc->supply.vmmc))
2145 sdhci_set_power_noreg(host, mode, vdd);
2146 else
2147 sdhci_set_power_reg(host, mode, vdd);
2148}
2149EXPORT_SYMBOL_GPL(sdhci_set_power);
2150
2151/*
2152 * Some controllers need to configure a valid bus voltage on their power
2153 * register regardless of whether an external regulator is taking care of power
2154 * supply. This helper function takes care of it if set as the controller's
2155 * sdhci_ops.set_power callback.
2156 */
2157void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
2158 unsigned char mode,
2159 unsigned short vdd)
2160{
2161 if (!IS_ERR(host->mmc->supply.vmmc)) {
2162 struct mmc_host *mmc = host->mmc;
2163
2164 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2165 }
2166 sdhci_set_power_noreg(host, mode, vdd);
2167}
2168EXPORT_SYMBOL_GPL(sdhci_set_power_and_bus_voltage);
2169
2170/*****************************************************************************\
2171 * *
2172 * MMC callbacks *
2173 * *
2174\*****************************************************************************/
2175
2176void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
2177{
2178 struct sdhci_host *host = mmc_priv(mmc);
2179 struct mmc_command *cmd;
2180 unsigned long flags;
2181 bool present;
2182
2183 /* Firstly check card presence */
2184 present = mmc->ops->get_cd(mmc);
2185
2186 spin_lock_irqsave(&host->lock, flags);
2187
2188 sdhci_led_activate(host);
2189
2190 if (sdhci_present_error(host, mrq->cmd, present))
2191 goto out_finish;
2192
2193 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2194
2195 if (!sdhci_send_command_retry(host, cmd, flags))
2196 goto out_finish;
2197
2198 spin_unlock_irqrestore(&host->lock, flags);
2199
2200 return;
2201
2202out_finish:
2203 sdhci_finish_mrq(host, mrq);
2204 spin_unlock_irqrestore(&host->lock, flags);
2205}
2206EXPORT_SYMBOL_GPL(sdhci_request);
2207
2208int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq)
2209{
2210 struct sdhci_host *host = mmc_priv(mmc);
2211 struct mmc_command *cmd;
2212 unsigned long flags;
2213 int ret = 0;
2214
2215 spin_lock_irqsave(&host->lock, flags);
2216
2217 if (sdhci_present_error(host, mrq->cmd, true)) {
2218 sdhci_finish_mrq(host, mrq);
2219 goto out_finish;
2220 }
2221
2222 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2223
2224 /*
2225 * The HSQ may send a command in interrupt context without polling
2226 * the busy signaling, which means we should return BUSY if controller
2227 * has not released inhibit bits to allow HSQ trying to send request
2228 * again in non-atomic context. So we should not finish this request
2229 * here.
2230 */
2231 if (!sdhci_send_command(host, cmd))
2232 ret = -EBUSY;
2233 else
2234 sdhci_led_activate(host);
2235
2236out_finish:
2237 spin_unlock_irqrestore(&host->lock, flags);
2238 return ret;
2239}
2240EXPORT_SYMBOL_GPL(sdhci_request_atomic);
2241
2242void sdhci_set_bus_width(struct sdhci_host *host, int width)
2243{
2244 u8 ctrl;
2245
2246 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2247 if (width == MMC_BUS_WIDTH_8) {
2248 ctrl &= ~SDHCI_CTRL_4BITBUS;
2249 ctrl |= SDHCI_CTRL_8BITBUS;
2250 } else {
2251 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
2252 ctrl &= ~SDHCI_CTRL_8BITBUS;
2253 if (width == MMC_BUS_WIDTH_4)
2254 ctrl |= SDHCI_CTRL_4BITBUS;
2255 else
2256 ctrl &= ~SDHCI_CTRL_4BITBUS;
2257 }
2258 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2259}
2260EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
2261
2262void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
2263{
2264 u16 ctrl_2;
2265
2266 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2267 /* Select Bus Speed Mode for host */
2268 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
2269 if ((timing == MMC_TIMING_MMC_HS200) ||
2270 (timing == MMC_TIMING_UHS_SDR104))
2271 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
2272 else if (timing == MMC_TIMING_UHS_SDR12)
2273 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
2274 else if (timing == MMC_TIMING_UHS_SDR25)
2275 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
2276 else if (timing == MMC_TIMING_UHS_SDR50)
2277 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
2278 else if ((timing == MMC_TIMING_UHS_DDR50) ||
2279 (timing == MMC_TIMING_MMC_DDR52))
2280 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
2281 else if (timing == MMC_TIMING_MMC_HS400)
2282 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
2283 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2284}
2285EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
2286
2287static bool sdhci_timing_has_preset(unsigned char timing)
2288{
2289 switch (timing) {
2290 case MMC_TIMING_UHS_SDR12:
2291 case MMC_TIMING_UHS_SDR25:
2292 case MMC_TIMING_UHS_SDR50:
2293 case MMC_TIMING_UHS_SDR104:
2294 case MMC_TIMING_UHS_DDR50:
2295 case MMC_TIMING_MMC_DDR52:
2296 return true;
2297 }
2298 return false;
2299}
2300
2301static bool sdhci_preset_needed(struct sdhci_host *host, unsigned char timing)
2302{
2303 return !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
2304 sdhci_timing_has_preset(timing);
2305}
2306
2307static bool sdhci_presetable_values_change(struct sdhci_host *host, struct mmc_ios *ios)
2308{
2309 /*
2310 * Preset Values are: Driver Strength, Clock Generator and SDCLK/RCLK
2311 * Frequency. Check if preset values need to be enabled, or the Driver
2312 * Strength needs updating. Note, clock changes are handled separately.
2313 */
2314 return !host->preset_enabled &&
2315 (sdhci_preset_needed(host, ios->timing) || host->drv_type != ios->drv_type);
2316}
2317
2318void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2319{
2320 struct sdhci_host *host = mmc_priv(mmc);
2321 bool reinit_uhs = host->reinit_uhs;
2322 bool turning_on_clk = false;
2323 u8 ctrl;
2324
2325 host->reinit_uhs = false;
2326
2327 if (ios->power_mode == MMC_POWER_UNDEFINED)
2328 return;
2329
2330 if (host->flags & SDHCI_DEVICE_DEAD) {
2331 if (!IS_ERR(mmc->supply.vmmc) &&
2332 ios->power_mode == MMC_POWER_OFF)
2333 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
2334 return;
2335 }
2336
2337 /*
2338 * Reset the chip on each power off.
2339 * Should clear out any weird states.
2340 */
2341 if (ios->power_mode == MMC_POWER_OFF) {
2342 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2343 sdhci_reinit(host);
2344 }
2345
2346 if (host->version >= SDHCI_SPEC_300 &&
2347 (ios->power_mode == MMC_POWER_UP) &&
2348 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
2349 sdhci_enable_preset_value(host, false);
2350
2351 if (!ios->clock || ios->clock != host->clock) {
2352 turning_on_clk = ios->clock && !host->clock;
2353
2354 host->ops->set_clock(host, ios->clock);
2355 host->clock = ios->clock;
2356
2357 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
2358 host->clock) {
2359 host->timeout_clk = mmc->actual_clock ?
2360 mmc->actual_clock / 1000 :
2361 host->clock / 1000;
2362 mmc->max_busy_timeout =
2363 host->ops->get_max_timeout_count ?
2364 host->ops->get_max_timeout_count(host) :
2365 1 << 27;
2366 mmc->max_busy_timeout /= host->timeout_clk;
2367 }
2368 }
2369
2370 if (host->ops->set_power)
2371 host->ops->set_power(host, ios->power_mode, ios->vdd);
2372 else
2373 sdhci_set_power(host, ios->power_mode, ios->vdd);
2374
2375 if (host->ops->platform_send_init_74_clocks)
2376 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
2377
2378 host->ops->set_bus_width(host, ios->bus_width);
2379
2380 /*
2381 * Special case to avoid multiple clock changes during voltage
2382 * switching.
2383 */
2384 if (!reinit_uhs &&
2385 turning_on_clk &&
2386 host->timing == ios->timing &&
2387 host->version >= SDHCI_SPEC_300 &&
2388 !sdhci_presetable_values_change(host, ios))
2389 return;
2390
2391 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2392
2393 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
2394 if (ios->timing == MMC_TIMING_SD_HS ||
2395 ios->timing == MMC_TIMING_MMC_HS ||
2396 ios->timing == MMC_TIMING_MMC_HS400 ||
2397 ios->timing == MMC_TIMING_MMC_HS200 ||
2398 ios->timing == MMC_TIMING_MMC_DDR52 ||
2399 ios->timing == MMC_TIMING_UHS_SDR50 ||
2400 ios->timing == MMC_TIMING_UHS_SDR104 ||
2401 ios->timing == MMC_TIMING_UHS_DDR50 ||
2402 ios->timing == MMC_TIMING_UHS_SDR25)
2403 ctrl |= SDHCI_CTRL_HISPD;
2404 else
2405 ctrl &= ~SDHCI_CTRL_HISPD;
2406 }
2407
2408 if (host->version >= SDHCI_SPEC_300) {
2409 u16 clk, ctrl_2;
2410
2411 /*
2412 * According to SDHCI Spec v3.00, if the Preset Value
2413 * Enable in the Host Control 2 register is set, we
2414 * need to reset SD Clock Enable before changing High
2415 * Speed Enable to avoid generating clock glitches.
2416 */
2417 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2418 if (clk & SDHCI_CLOCK_CARD_EN) {
2419 clk &= ~SDHCI_CLOCK_CARD_EN;
2420 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2421 }
2422
2423 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2424
2425 if (!host->preset_enabled) {
2426 /*
2427 * We only need to set Driver Strength if the
2428 * preset value enable is not set.
2429 */
2430 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2431 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
2432 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
2433 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
2434 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
2435 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2436 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
2437 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
2438 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
2439 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
2440 else {
2441 pr_warn("%s: invalid driver type, default to driver type B\n",
2442 mmc_hostname(mmc));
2443 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2444 }
2445
2446 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2447 host->drv_type = ios->drv_type;
2448 }
2449
2450 host->ops->set_uhs_signaling(host, ios->timing);
2451 host->timing = ios->timing;
2452
2453 if (sdhci_preset_needed(host, ios->timing)) {
2454 u16 preset;
2455
2456 sdhci_enable_preset_value(host, true);
2457 preset = sdhci_get_preset_value(host);
2458 ios->drv_type = FIELD_GET(SDHCI_PRESET_DRV_MASK,
2459 preset);
2460 host->drv_type = ios->drv_type;
2461 }
2462
2463 /* Re-enable SD Clock */
2464 host->ops->set_clock(host, host->clock);
2465 } else
2466 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2467}
2468EXPORT_SYMBOL_GPL(sdhci_set_ios);
2469
2470static int sdhci_get_cd(struct mmc_host *mmc)
2471{
2472 struct sdhci_host *host = mmc_priv(mmc);
2473 int gpio_cd = mmc_gpio_get_cd(mmc);
2474
2475 if (host->flags & SDHCI_DEVICE_DEAD)
2476 return 0;
2477
2478 /* If nonremovable, assume that the card is always present. */
2479 if (!mmc_card_is_removable(mmc))
2480 return 1;
2481
2482 /*
2483 * Try slot gpio detect, if defined it take precedence
2484 * over build in controller functionality
2485 */
2486 if (gpio_cd >= 0)
2487 return !!gpio_cd;
2488
2489 /* If polling, assume that the card is always present. */
2490 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2491 return 1;
2492
2493 /* Host native card detect */
2494 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2495}
2496
2497int sdhci_get_cd_nogpio(struct mmc_host *mmc)
2498{
2499 struct sdhci_host *host = mmc_priv(mmc);
2500 unsigned long flags;
2501 int ret = 0;
2502
2503 spin_lock_irqsave(&host->lock, flags);
2504
2505 if (host->flags & SDHCI_DEVICE_DEAD)
2506 goto out;
2507
2508 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2509out:
2510 spin_unlock_irqrestore(&host->lock, flags);
2511
2512 return ret;
2513}
2514EXPORT_SYMBOL_GPL(sdhci_get_cd_nogpio);
2515
2516static int sdhci_check_ro(struct sdhci_host *host)
2517{
2518 unsigned long flags;
2519 int is_readonly;
2520
2521 spin_lock_irqsave(&host->lock, flags);
2522
2523 if (host->flags & SDHCI_DEVICE_DEAD)
2524 is_readonly = 0;
2525 else if (host->ops->get_ro)
2526 is_readonly = host->ops->get_ro(host);
2527 else if (mmc_can_gpio_ro(host->mmc))
2528 is_readonly = mmc_gpio_get_ro(host->mmc);
2529 else
2530 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2531 & SDHCI_WRITE_PROTECT);
2532
2533 spin_unlock_irqrestore(&host->lock, flags);
2534
2535 /* This quirk needs to be replaced by a callback-function later */
2536 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
2537 !is_readonly : is_readonly;
2538}
2539
2540#define SAMPLE_COUNT 5
2541
2542static int sdhci_get_ro(struct mmc_host *mmc)
2543{
2544 struct sdhci_host *host = mmc_priv(mmc);
2545 int i, ro_count;
2546
2547 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
2548 return sdhci_check_ro(host);
2549
2550 ro_count = 0;
2551 for (i = 0; i < SAMPLE_COUNT; i++) {
2552 if (sdhci_check_ro(host)) {
2553 if (++ro_count > SAMPLE_COUNT / 2)
2554 return 1;
2555 }
2556 msleep(30);
2557 }
2558 return 0;
2559}
2560
2561static void sdhci_hw_reset(struct mmc_host *mmc)
2562{
2563 struct sdhci_host *host = mmc_priv(mmc);
2564
2565 if (host->ops && host->ops->hw_reset)
2566 host->ops->hw_reset(host);
2567}
2568
2569static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2570{
2571 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
2572 if (enable)
2573 host->ier |= SDHCI_INT_CARD_INT;
2574 else
2575 host->ier &= ~SDHCI_INT_CARD_INT;
2576
2577 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2578 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2579 }
2580}
2581
2582void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
2583{
2584 struct sdhci_host *host = mmc_priv(mmc);
2585 unsigned long flags;
2586
2587 if (enable)
2588 pm_runtime_get_noresume(mmc_dev(mmc));
2589
2590 spin_lock_irqsave(&host->lock, flags);
2591 sdhci_enable_sdio_irq_nolock(host, enable);
2592 spin_unlock_irqrestore(&host->lock, flags);
2593
2594 if (!enable)
2595 pm_runtime_put_noidle(mmc_dev(mmc));
2596}
2597EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
2598
2599static void sdhci_ack_sdio_irq(struct mmc_host *mmc)
2600{
2601 struct sdhci_host *host = mmc_priv(mmc);
2602 unsigned long flags;
2603
2604 spin_lock_irqsave(&host->lock, flags);
2605 sdhci_enable_sdio_irq_nolock(host, true);
2606 spin_unlock_irqrestore(&host->lock, flags);
2607}
2608
2609int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2610 struct mmc_ios *ios)
2611{
2612 struct sdhci_host *host = mmc_priv(mmc);
2613 u16 ctrl;
2614 int ret;
2615
2616 /*
2617 * Signal Voltage Switching is only applicable for Host Controllers
2618 * v3.00 and above.
2619 */
2620 if (host->version < SDHCI_SPEC_300)
2621 return 0;
2622
2623 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2624
2625 switch (ios->signal_voltage) {
2626 case MMC_SIGNAL_VOLTAGE_330:
2627 if (!(host->flags & SDHCI_SIGNALING_330))
2628 return -EINVAL;
2629 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2630 ctrl &= ~SDHCI_CTRL_VDD_180;
2631 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2632
2633 if (!IS_ERR(mmc->supply.vqmmc)) {
2634 ret = mmc_regulator_set_vqmmc(mmc, ios);
2635 if (ret < 0) {
2636 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
2637 mmc_hostname(mmc));
2638 return -EIO;
2639 }
2640 }
2641 /* Wait for 5ms */
2642 usleep_range(5000, 5500);
2643
2644 /* 3.3V regulator output should be stable within 5 ms */
2645 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2646 if (!(ctrl & SDHCI_CTRL_VDD_180))
2647 return 0;
2648
2649 pr_warn("%s: 3.3V regulator output did not become stable\n",
2650 mmc_hostname(mmc));
2651
2652 return -EAGAIN;
2653 case MMC_SIGNAL_VOLTAGE_180:
2654 if (!(host->flags & SDHCI_SIGNALING_180))
2655 return -EINVAL;
2656 if (!IS_ERR(mmc->supply.vqmmc)) {
2657 ret = mmc_regulator_set_vqmmc(mmc, ios);
2658 if (ret < 0) {
2659 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
2660 mmc_hostname(mmc));
2661 return -EIO;
2662 }
2663 }
2664
2665 /*
2666 * Enable 1.8V Signal Enable in the Host Control2
2667 * register
2668 */
2669 ctrl |= SDHCI_CTRL_VDD_180;
2670 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2671
2672 /* Some controller need to do more when switching */
2673 if (host->ops->voltage_switch)
2674 host->ops->voltage_switch(host);
2675
2676 /* 1.8V regulator output should be stable within 5 ms */
2677 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2678 if (ctrl & SDHCI_CTRL_VDD_180)
2679 return 0;
2680
2681 pr_warn("%s: 1.8V regulator output did not become stable\n",
2682 mmc_hostname(mmc));
2683
2684 return -EAGAIN;
2685 case MMC_SIGNAL_VOLTAGE_120:
2686 if (!(host->flags & SDHCI_SIGNALING_120))
2687 return -EINVAL;
2688 if (!IS_ERR(mmc->supply.vqmmc)) {
2689 ret = mmc_regulator_set_vqmmc(mmc, ios);
2690 if (ret < 0) {
2691 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
2692 mmc_hostname(mmc));
2693 return -EIO;
2694 }
2695 }
2696 return 0;
2697 default:
2698 /* No signal voltage switch required */
2699 return 0;
2700 }
2701}
2702EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2703
2704static int sdhci_card_busy(struct mmc_host *mmc)
2705{
2706 struct sdhci_host *host = mmc_priv(mmc);
2707 u32 present_state;
2708
2709 /* Check whether DAT[0] is 0 */
2710 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2711
2712 return !(present_state & SDHCI_DATA_0_LVL_MASK);
2713}
2714
2715static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2716{
2717 struct sdhci_host *host = mmc_priv(mmc);
2718 unsigned long flags;
2719
2720 spin_lock_irqsave(&host->lock, flags);
2721 host->flags |= SDHCI_HS400_TUNING;
2722 spin_unlock_irqrestore(&host->lock, flags);
2723
2724 return 0;
2725}
2726
2727void sdhci_start_tuning(struct sdhci_host *host)
2728{
2729 u16 ctrl;
2730
2731 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2732 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2733 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2734 ctrl |= SDHCI_CTRL_TUNED_CLK;
2735 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2736
2737 /*
2738 * As per the Host Controller spec v3.00, tuning command
2739 * generates Buffer Read Ready interrupt, so enable that.
2740 *
2741 * Note: The spec clearly says that when tuning sequence
2742 * is being performed, the controller does not generate
2743 * interrupts other than Buffer Read Ready interrupt. But
2744 * to make sure we don't hit a controller bug, we _only_
2745 * enable Buffer Read Ready interrupt here.
2746 */
2747 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2748 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2749}
2750EXPORT_SYMBOL_GPL(sdhci_start_tuning);
2751
2752void sdhci_end_tuning(struct sdhci_host *host)
2753{
2754 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2755 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2756}
2757EXPORT_SYMBOL_GPL(sdhci_end_tuning);
2758
2759void sdhci_reset_tuning(struct sdhci_host *host)
2760{
2761 u16 ctrl;
2762
2763 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2764 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2765 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2766 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2767}
2768EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
2769
2770void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2771{
2772 sdhci_reset_tuning(host);
2773
2774 sdhci_reset_for(host, TUNING_ABORT);
2775
2776 sdhci_end_tuning(host);
2777
2778 mmc_send_abort_tuning(host->mmc, opcode);
2779}
2780EXPORT_SYMBOL_GPL(sdhci_abort_tuning);
2781
2782/*
2783 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2784 * tuning command does not have a data payload (or rather the hardware does it
2785 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2786 * interrupt setup is different to other commands and there is no timeout
2787 * interrupt so special handling is needed.
2788 */
2789void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2790{
2791 struct mmc_host *mmc = host->mmc;
2792 struct mmc_command cmd = {};
2793 struct mmc_request mrq = {};
2794 unsigned long flags;
2795 u32 b = host->sdma_boundary;
2796
2797 spin_lock_irqsave(&host->lock, flags);
2798
2799 cmd.opcode = opcode;
2800 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2801 cmd.mrq = &mrq;
2802
2803 mrq.cmd = &cmd;
2804 /*
2805 * In response to CMD19, the card sends 64 bytes of tuning
2806 * block to the Host Controller. So we set the block size
2807 * to 64 here.
2808 */
2809 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2810 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2811 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2812 else
2813 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2814
2815 /*
2816 * The tuning block is sent by the card to the host controller.
2817 * So we set the TRNS_READ bit in the Transfer Mode register.
2818 * This also takes care of setting DMA Enable and Multi Block
2819 * Select in the same register to 0.
2820 */
2821 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2822
2823 if (!sdhci_send_command_retry(host, &cmd, flags)) {
2824 spin_unlock_irqrestore(&host->lock, flags);
2825 host->tuning_done = 0;
2826 return;
2827 }
2828
2829 host->cmd = NULL;
2830
2831 sdhci_del_timer(host, &mrq);
2832
2833 host->tuning_done = 0;
2834
2835 spin_unlock_irqrestore(&host->lock, flags);
2836
2837 /* Wait for Buffer Read Ready interrupt */
2838 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2839 msecs_to_jiffies(50));
2840
2841}
2842EXPORT_SYMBOL_GPL(sdhci_send_tuning);
2843
2844static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2845{
2846 int i;
2847
2848 /*
2849 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2850 * of loops reaches tuning loop count.
2851 */
2852 for (i = 0; i < host->tuning_loop_count; i++) {
2853 u16 ctrl;
2854
2855 sdhci_send_tuning(host, opcode);
2856
2857 if (!host->tuning_done) {
2858 pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
2859 mmc_hostname(host->mmc));
2860 sdhci_abort_tuning(host, opcode);
2861 return -ETIMEDOUT;
2862 }
2863
2864 /* Spec does not require a delay between tuning cycles */
2865 if (host->tuning_delay > 0)
2866 mdelay(host->tuning_delay);
2867
2868 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2869 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2870 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2871 return 0; /* Success! */
2872 break;
2873 }
2874
2875 }
2876
2877 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2878 mmc_hostname(host->mmc));
2879 sdhci_reset_tuning(host);
2880 return -EAGAIN;
2881}
2882
2883int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2884{
2885 struct sdhci_host *host = mmc_priv(mmc);
2886 int err = 0;
2887 unsigned int tuning_count = 0;
2888 bool hs400_tuning;
2889
2890 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2891
2892 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2893 tuning_count = host->tuning_count;
2894
2895 /*
2896 * The Host Controller needs tuning in case of SDR104 and DDR50
2897 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2898 * the Capabilities register.
2899 * If the Host Controller supports the HS200 mode then the
2900 * tuning function has to be executed.
2901 */
2902 switch (host->timing) {
2903 /* HS400 tuning is done in HS200 mode */
2904 case MMC_TIMING_MMC_HS400:
2905 err = -EINVAL;
2906 goto out;
2907
2908 case MMC_TIMING_MMC_HS200:
2909 /*
2910 * Periodic re-tuning for HS400 is not expected to be needed, so
2911 * disable it here.
2912 */
2913 if (hs400_tuning)
2914 tuning_count = 0;
2915 break;
2916
2917 case MMC_TIMING_UHS_SDR104:
2918 case MMC_TIMING_UHS_DDR50:
2919 break;
2920
2921 case MMC_TIMING_UHS_SDR50:
2922 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2923 break;
2924 fallthrough;
2925
2926 default:
2927 goto out;
2928 }
2929
2930 if (host->ops->platform_execute_tuning) {
2931 err = host->ops->platform_execute_tuning(host, opcode);
2932 goto out;
2933 }
2934
2935 mmc->retune_period = tuning_count;
2936
2937 if (host->tuning_delay < 0)
2938 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2939
2940 sdhci_start_tuning(host);
2941
2942 host->tuning_err = __sdhci_execute_tuning(host, opcode);
2943
2944 sdhci_end_tuning(host);
2945out:
2946 host->flags &= ~SDHCI_HS400_TUNING;
2947
2948 return err;
2949}
2950EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2951
2952static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2953{
2954 /* Host Controller v3.00 defines preset value registers */
2955 if (host->version < SDHCI_SPEC_300)
2956 return;
2957
2958 /*
2959 * We only enable or disable Preset Value if they are not already
2960 * enabled or disabled respectively. Otherwise, we bail out.
2961 */
2962 if (host->preset_enabled != enable) {
2963 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2964
2965 if (enable)
2966 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2967 else
2968 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2969
2970 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2971
2972 if (enable)
2973 host->flags |= SDHCI_PV_ENABLED;
2974 else
2975 host->flags &= ~SDHCI_PV_ENABLED;
2976
2977 host->preset_enabled = enable;
2978 }
2979}
2980
2981static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2982 int err)
2983{
2984 struct mmc_data *data = mrq->data;
2985
2986 if (data->host_cookie != COOKIE_UNMAPPED)
2987 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
2988 mmc_get_dma_dir(data));
2989
2990 data->host_cookie = COOKIE_UNMAPPED;
2991}
2992
2993static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2994{
2995 struct sdhci_host *host = mmc_priv(mmc);
2996
2997 mrq->data->host_cookie = COOKIE_UNMAPPED;
2998
2999 /*
3000 * No pre-mapping in the pre hook if we're using the bounce buffer,
3001 * for that we would need two bounce buffers since one buffer is
3002 * in flight when this is getting called.
3003 */
3004 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
3005 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
3006}
3007
3008static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
3009{
3010 if (host->data_cmd) {
3011 host->data_cmd->error = err;
3012 sdhci_finish_mrq(host, host->data_cmd->mrq);
3013 }
3014
3015 if (host->cmd) {
3016 host->cmd->error = err;
3017 sdhci_finish_mrq(host, host->cmd->mrq);
3018 }
3019}
3020
3021static void sdhci_card_event(struct mmc_host *mmc)
3022{
3023 struct sdhci_host *host = mmc_priv(mmc);
3024 unsigned long flags;
3025 int present;
3026
3027 /* First check if client has provided their own card event */
3028 if (host->ops->card_event)
3029 host->ops->card_event(host);
3030
3031 present = mmc->ops->get_cd(mmc);
3032
3033 spin_lock_irqsave(&host->lock, flags);
3034
3035 /* Check sdhci_has_requests() first in case we are runtime suspended */
3036 if (sdhci_has_requests(host) && !present) {
3037 pr_err("%s: Card removed during transfer!\n",
3038 mmc_hostname(mmc));
3039 pr_err("%s: Resetting controller.\n",
3040 mmc_hostname(mmc));
3041
3042 sdhci_reset_for(host, CARD_REMOVED);
3043
3044 sdhci_error_out_mrqs(host, -ENOMEDIUM);
3045 }
3046
3047 spin_unlock_irqrestore(&host->lock, flags);
3048}
3049
3050static const struct mmc_host_ops sdhci_ops = {
3051 .request = sdhci_request,
3052 .post_req = sdhci_post_req,
3053 .pre_req = sdhci_pre_req,
3054 .set_ios = sdhci_set_ios,
3055 .get_cd = sdhci_get_cd,
3056 .get_ro = sdhci_get_ro,
3057 .card_hw_reset = sdhci_hw_reset,
3058 .enable_sdio_irq = sdhci_enable_sdio_irq,
3059 .ack_sdio_irq = sdhci_ack_sdio_irq,
3060 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
3061 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
3062 .execute_tuning = sdhci_execute_tuning,
3063 .card_event = sdhci_card_event,
3064 .card_busy = sdhci_card_busy,
3065};
3066
3067/*****************************************************************************\
3068 * *
3069 * Request done *
3070 * *
3071\*****************************************************************************/
3072
3073static bool sdhci_request_done(struct sdhci_host *host)
3074{
3075 unsigned long flags;
3076 struct mmc_request *mrq;
3077 int i;
3078
3079 spin_lock_irqsave(&host->lock, flags);
3080
3081 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3082 mrq = host->mrqs_done[i];
3083 if (mrq)
3084 break;
3085 }
3086
3087 if (!mrq) {
3088 spin_unlock_irqrestore(&host->lock, flags);
3089 return true;
3090 }
3091
3092 /*
3093 * The controller needs a reset of internal state machines
3094 * upon error conditions.
3095 */
3096 if (sdhci_needs_reset(host, mrq)) {
3097 /*
3098 * Do not finish until command and data lines are available for
3099 * reset. Note there can only be one other mrq, so it cannot
3100 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
3101 * would both be null.
3102 */
3103 if (host->cmd || host->data_cmd) {
3104 spin_unlock_irqrestore(&host->lock, flags);
3105 return true;
3106 }
3107
3108 /* Some controllers need this kick or reset won't work here */
3109 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
3110 /* This is to force an update */
3111 host->ops->set_clock(host, host->clock);
3112
3113 sdhci_reset_for(host, REQUEST_ERROR);
3114
3115 host->pending_reset = false;
3116 }
3117
3118 /*
3119 * Always unmap the data buffers if they were mapped by
3120 * sdhci_prepare_data() whenever we finish with a request.
3121 * This avoids leaking DMA mappings on error.
3122 */
3123 if (host->flags & SDHCI_REQ_USE_DMA) {
3124 struct mmc_data *data = mrq->data;
3125
3126 if (host->use_external_dma && data &&
3127 (mrq->cmd->error || data->error)) {
3128 struct dma_chan *chan = sdhci_external_dma_channel(host, data);
3129
3130 host->mrqs_done[i] = NULL;
3131 spin_unlock_irqrestore(&host->lock, flags);
3132 dmaengine_terminate_sync(chan);
3133 spin_lock_irqsave(&host->lock, flags);
3134 sdhci_set_mrq_done(host, mrq);
3135 }
3136
3137 if (data && data->host_cookie == COOKIE_MAPPED) {
3138 if (host->bounce_buffer) {
3139 /*
3140 * On reads, copy the bounced data into the
3141 * sglist
3142 */
3143 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
3144 unsigned int length = data->bytes_xfered;
3145
3146 if (length > host->bounce_buffer_size) {
3147 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
3148 mmc_hostname(host->mmc),
3149 host->bounce_buffer_size,
3150 data->bytes_xfered);
3151 /* Cap it down and continue */
3152 length = host->bounce_buffer_size;
3153 }
3154 dma_sync_single_for_cpu(
3155 mmc_dev(host->mmc),
3156 host->bounce_addr,
3157 host->bounce_buffer_size,
3158 DMA_FROM_DEVICE);
3159 sg_copy_from_buffer(data->sg,
3160 data->sg_len,
3161 host->bounce_buffer,
3162 length);
3163 } else {
3164 /* No copying, just switch ownership */
3165 dma_sync_single_for_cpu(
3166 mmc_dev(host->mmc),
3167 host->bounce_addr,
3168 host->bounce_buffer_size,
3169 mmc_get_dma_dir(data));
3170 }
3171 } else {
3172 /* Unmap the raw data */
3173 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
3174 data->sg_len,
3175 mmc_get_dma_dir(data));
3176 }
3177 data->host_cookie = COOKIE_UNMAPPED;
3178 }
3179 }
3180
3181 host->mrqs_done[i] = NULL;
3182
3183 spin_unlock_irqrestore(&host->lock, flags);
3184
3185 if (host->ops->request_done)
3186 host->ops->request_done(host, mrq);
3187 else
3188 mmc_request_done(host->mmc, mrq);
3189
3190 return false;
3191}
3192
3193static void sdhci_complete_work(struct work_struct *work)
3194{
3195 struct sdhci_host *host = container_of(work, struct sdhci_host,
3196 complete_work);
3197
3198 while (!sdhci_request_done(host))
3199 ;
3200}
3201
3202static void sdhci_timeout_timer(struct timer_list *t)
3203{
3204 struct sdhci_host *host;
3205 unsigned long flags;
3206
3207 host = from_timer(host, t, timer);
3208
3209 spin_lock_irqsave(&host->lock, flags);
3210
3211 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
3212 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
3213 mmc_hostname(host->mmc));
3214 sdhci_err_stats_inc(host, REQ_TIMEOUT);
3215 sdhci_dumpregs(host);
3216
3217 host->cmd->error = -ETIMEDOUT;
3218 sdhci_finish_mrq(host, host->cmd->mrq);
3219 }
3220
3221 spin_unlock_irqrestore(&host->lock, flags);
3222}
3223
3224static void sdhci_timeout_data_timer(struct timer_list *t)
3225{
3226 struct sdhci_host *host;
3227 unsigned long flags;
3228
3229 host = from_timer(host, t, data_timer);
3230
3231 spin_lock_irqsave(&host->lock, flags);
3232
3233 if (host->data || host->data_cmd ||
3234 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
3235 pr_err("%s: Timeout waiting for hardware interrupt.\n",
3236 mmc_hostname(host->mmc));
3237 sdhci_err_stats_inc(host, REQ_TIMEOUT);
3238 sdhci_dumpregs(host);
3239
3240 if (host->data) {
3241 host->data->error = -ETIMEDOUT;
3242 __sdhci_finish_data(host, true);
3243 queue_work(host->complete_wq, &host->complete_work);
3244 } else if (host->data_cmd) {
3245 host->data_cmd->error = -ETIMEDOUT;
3246 sdhci_finish_mrq(host, host->data_cmd->mrq);
3247 } else {
3248 host->cmd->error = -ETIMEDOUT;
3249 sdhci_finish_mrq(host, host->cmd->mrq);
3250 }
3251 }
3252
3253 spin_unlock_irqrestore(&host->lock, flags);
3254}
3255
3256/*****************************************************************************\
3257 * *
3258 * Interrupt handling *
3259 * *
3260\*****************************************************************************/
3261
3262static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
3263{
3264 /* Handle auto-CMD12 error */
3265 if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
3266 struct mmc_request *mrq = host->data_cmd->mrq;
3267 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3268 int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3269 SDHCI_INT_DATA_TIMEOUT :
3270 SDHCI_INT_DATA_CRC;
3271
3272 /* Treat auto-CMD12 error the same as data error */
3273 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
3274 *intmask_p |= data_err_bit;
3275 return;
3276 }
3277 }
3278
3279 if (!host->cmd) {
3280 /*
3281 * SDHCI recovers from errors by resetting the cmd and data
3282 * circuits. Until that is done, there very well might be more
3283 * interrupts, so ignore them in that case.
3284 */
3285 if (host->pending_reset)
3286 return;
3287 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
3288 mmc_hostname(host->mmc), (unsigned)intmask);
3289 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
3290 sdhci_dumpregs(host);
3291 return;
3292 }
3293
3294 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
3295 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
3296 if (intmask & SDHCI_INT_TIMEOUT) {
3297 host->cmd->error = -ETIMEDOUT;
3298 sdhci_err_stats_inc(host, CMD_TIMEOUT);
3299 } else {
3300 host->cmd->error = -EILSEQ;
3301 if (!mmc_op_tuning(host->cmd->opcode))
3302 sdhci_err_stats_inc(host, CMD_CRC);
3303 }
3304 /* Treat data command CRC error the same as data CRC error */
3305 if (host->cmd->data &&
3306 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
3307 SDHCI_INT_CRC) {
3308 host->cmd = NULL;
3309 *intmask_p |= SDHCI_INT_DATA_CRC;
3310 return;
3311 }
3312
3313 __sdhci_finish_mrq(host, host->cmd->mrq);
3314 return;
3315 }
3316
3317 /* Handle auto-CMD23 error */
3318 if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
3319 struct mmc_request *mrq = host->cmd->mrq;
3320 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3321 int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3322 -ETIMEDOUT :
3323 -EILSEQ;
3324
3325 sdhci_err_stats_inc(host, AUTO_CMD);
3326
3327 if (sdhci_auto_cmd23(host, mrq)) {
3328 mrq->sbc->error = err;
3329 __sdhci_finish_mrq(host, mrq);
3330 return;
3331 }
3332 }
3333
3334 if (intmask & SDHCI_INT_RESPONSE)
3335 sdhci_finish_command(host);
3336}
3337
3338static void sdhci_adma_show_error(struct sdhci_host *host)
3339{
3340 void *desc = host->adma_table;
3341 dma_addr_t dma = host->adma_addr;
3342
3343 sdhci_dumpregs(host);
3344
3345 while (true) {
3346 struct sdhci_adma2_64_desc *dma_desc = desc;
3347
3348 if (host->flags & SDHCI_USE_64_BIT_DMA)
3349 SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
3350 (unsigned long long)dma,
3351 le32_to_cpu(dma_desc->addr_hi),
3352 le32_to_cpu(dma_desc->addr_lo),
3353 le16_to_cpu(dma_desc->len),
3354 le16_to_cpu(dma_desc->cmd));
3355 else
3356 SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
3357 (unsigned long long)dma,
3358 le32_to_cpu(dma_desc->addr_lo),
3359 le16_to_cpu(dma_desc->len),
3360 le16_to_cpu(dma_desc->cmd));
3361
3362 desc += host->desc_sz;
3363 dma += host->desc_sz;
3364
3365 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
3366 break;
3367 }
3368}
3369
3370static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
3371{
3372 /*
3373 * CMD19 generates _only_ Buffer Read Ready interrupt if
3374 * use sdhci_send_tuning.
3375 * Need to exclude this case: PIO mode and use mmc_send_tuning,
3376 * If not, sdhci_transfer_pio will never be called, make the
3377 * SDHCI_INT_DATA_AVAIL always there, stuck in irq storm.
3378 */
3379 if (intmask & SDHCI_INT_DATA_AVAIL && !host->data) {
3380 if (mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)))) {
3381 host->tuning_done = 1;
3382 wake_up(&host->buf_ready_int);
3383 return;
3384 }
3385 }
3386
3387 if (!host->data) {
3388 struct mmc_command *data_cmd = host->data_cmd;
3389
3390 /*
3391 * The "data complete" interrupt is also used to
3392 * indicate that a busy state has ended. See comment
3393 * above in sdhci_cmd_irq().
3394 */
3395 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
3396 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
3397 host->data_cmd = NULL;
3398 data_cmd->error = -ETIMEDOUT;
3399 sdhci_err_stats_inc(host, CMD_TIMEOUT);
3400 __sdhci_finish_mrq(host, data_cmd->mrq);
3401 return;
3402 }
3403 if (intmask & SDHCI_INT_DATA_END) {
3404 host->data_cmd = NULL;
3405 /*
3406 * Some cards handle busy-end interrupt
3407 * before the command completed, so make
3408 * sure we do things in the proper order.
3409 */
3410 if (host->cmd == data_cmd)
3411 return;
3412
3413 __sdhci_finish_mrq(host, data_cmd->mrq);
3414 return;
3415 }
3416 }
3417
3418 /*
3419 * SDHCI recovers from errors by resetting the cmd and data
3420 * circuits. Until that is done, there very well might be more
3421 * interrupts, so ignore them in that case.
3422 */
3423 if (host->pending_reset)
3424 return;
3425
3426 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
3427 mmc_hostname(host->mmc), (unsigned)intmask);
3428 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
3429 sdhci_dumpregs(host);
3430
3431 return;
3432 }
3433
3434 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
3435 host->data->error = -ETIMEDOUT;
3436 sdhci_err_stats_inc(host, DAT_TIMEOUT);
3437 } else if (intmask & SDHCI_INT_DATA_END_BIT) {
3438 host->data->error = -EILSEQ;
3439 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
3440 sdhci_err_stats_inc(host, DAT_CRC);
3441 } else if ((intmask & SDHCI_INT_DATA_CRC) &&
3442 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
3443 != MMC_BUS_TEST_R) {
3444 host->data->error = -EILSEQ;
3445 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
3446 sdhci_err_stats_inc(host, DAT_CRC);
3447 } else if (intmask & SDHCI_INT_ADMA_ERROR) {
3448 pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
3449 intmask);
3450 sdhci_adma_show_error(host);
3451 sdhci_err_stats_inc(host, ADMA);
3452 host->data->error = -EIO;
3453 if (host->ops->adma_workaround)
3454 host->ops->adma_workaround(host, intmask);
3455 }
3456
3457 if (host->data->error)
3458 sdhci_finish_data(host);
3459 else {
3460 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
3461 sdhci_transfer_pio(host);
3462
3463 /*
3464 * We currently don't do anything fancy with DMA
3465 * boundaries, but as we can't disable the feature
3466 * we need to at least restart the transfer.
3467 *
3468 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
3469 * should return a valid address to continue from, but as
3470 * some controllers are faulty, don't trust them.
3471 */
3472 if (intmask & SDHCI_INT_DMA_END) {
3473 dma_addr_t dmastart, dmanow;
3474
3475 dmastart = sdhci_sdma_address(host);
3476 dmanow = dmastart + host->data->bytes_xfered;
3477 /*
3478 * Force update to the next DMA block boundary.
3479 */
3480 dmanow = (dmanow &
3481 ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
3482 SDHCI_DEFAULT_BOUNDARY_SIZE;
3483 host->data->bytes_xfered = dmanow - dmastart;
3484 DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
3485 &dmastart, host->data->bytes_xfered, &dmanow);
3486 sdhci_set_sdma_addr(host, dmanow);
3487 }
3488
3489 if (intmask & SDHCI_INT_DATA_END) {
3490 if (host->cmd == host->data_cmd) {
3491 /*
3492 * Data managed to finish before the
3493 * command completed. Make sure we do
3494 * things in the proper order.
3495 */
3496 host->data_early = 1;
3497 } else {
3498 sdhci_finish_data(host);
3499 }
3500 }
3501 }
3502}
3503
3504static inline bool sdhci_defer_done(struct sdhci_host *host,
3505 struct mmc_request *mrq)
3506{
3507 struct mmc_data *data = mrq->data;
3508
3509 return host->pending_reset || host->always_defer_done ||
3510 ((host->flags & SDHCI_REQ_USE_DMA) && data &&
3511 data->host_cookie == COOKIE_MAPPED);
3512}
3513
3514static irqreturn_t sdhci_irq(int irq, void *dev_id)
3515{
3516 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0};
3517 irqreturn_t result = IRQ_NONE;
3518 struct sdhci_host *host = dev_id;
3519 u32 intmask, mask, unexpected = 0;
3520 int max_loops = 16;
3521 int i;
3522
3523 spin_lock(&host->lock);
3524
3525 if (host->runtime_suspended) {
3526 spin_unlock(&host->lock);
3527 return IRQ_NONE;
3528 }
3529
3530 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3531 if (!intmask || intmask == 0xffffffff) {
3532 result = IRQ_NONE;
3533 goto out;
3534 }
3535
3536 do {
3537 DBG("IRQ status 0x%08x\n", intmask);
3538
3539 if (host->ops->irq) {
3540 intmask = host->ops->irq(host, intmask);
3541 if (!intmask)
3542 goto cont;
3543 }
3544
3545 /* Clear selected interrupts. */
3546 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3547 SDHCI_INT_BUS_POWER);
3548 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3549
3550 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3551 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3552 SDHCI_CARD_PRESENT;
3553
3554 /*
3555 * There is a observation on i.mx esdhc. INSERT
3556 * bit will be immediately set again when it gets
3557 * cleared, if a card is inserted. We have to mask
3558 * the irq to prevent interrupt storm which will
3559 * freeze the system. And the REMOVE gets the
3560 * same situation.
3561 *
3562 * More testing are needed here to ensure it works
3563 * for other platforms though.
3564 */
3565 host->ier &= ~(SDHCI_INT_CARD_INSERT |
3566 SDHCI_INT_CARD_REMOVE);
3567 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
3568 SDHCI_INT_CARD_INSERT;
3569 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3570 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3571
3572 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
3573 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3574
3575 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
3576 SDHCI_INT_CARD_REMOVE);
3577 result = IRQ_WAKE_THREAD;
3578 }
3579
3580 if (intmask & SDHCI_INT_CMD_MASK)
3581 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
3582
3583 if (intmask & SDHCI_INT_DATA_MASK)
3584 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
3585
3586 if (intmask & SDHCI_INT_BUS_POWER)
3587 pr_err("%s: Card is consuming too much power!\n",
3588 mmc_hostname(host->mmc));
3589
3590 if (intmask & SDHCI_INT_RETUNE)
3591 mmc_retune_needed(host->mmc);
3592
3593 if ((intmask & SDHCI_INT_CARD_INT) &&
3594 (host->ier & SDHCI_INT_CARD_INT)) {
3595 sdhci_enable_sdio_irq_nolock(host, false);
3596 sdio_signal_irq(host->mmc);
3597 }
3598
3599 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
3600 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3601 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
3602 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
3603
3604 if (intmask) {
3605 unexpected |= intmask;
3606 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3607 }
3608cont:
3609 if (result == IRQ_NONE)
3610 result = IRQ_HANDLED;
3611
3612 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3613 } while (intmask && --max_loops);
3614
3615 /* Determine if mrqs can be completed immediately */
3616 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3617 struct mmc_request *mrq = host->mrqs_done[i];
3618
3619 if (!mrq)
3620 continue;
3621
3622 if (sdhci_defer_done(host, mrq)) {
3623 result = IRQ_WAKE_THREAD;
3624 } else {
3625 mrqs_done[i] = mrq;
3626 host->mrqs_done[i] = NULL;
3627 }
3628 }
3629out:
3630 if (host->deferred_cmd)
3631 result = IRQ_WAKE_THREAD;
3632
3633 spin_unlock(&host->lock);
3634
3635 /* Process mrqs ready for immediate completion */
3636 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3637 if (!mrqs_done[i])
3638 continue;
3639
3640 if (host->ops->request_done)
3641 host->ops->request_done(host, mrqs_done[i]);
3642 else
3643 mmc_request_done(host->mmc, mrqs_done[i]);
3644 }
3645
3646 if (unexpected) {
3647 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3648 mmc_hostname(host->mmc), unexpected);
3649 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
3650 sdhci_dumpregs(host);
3651 }
3652
3653 return result;
3654}
3655
3656static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
3657{
3658 struct sdhci_host *host = dev_id;
3659 struct mmc_command *cmd;
3660 unsigned long flags;
3661 u32 isr;
3662
3663 while (!sdhci_request_done(host))
3664 ;
3665
3666 spin_lock_irqsave(&host->lock, flags);
3667
3668 isr = host->thread_isr;
3669 host->thread_isr = 0;
3670
3671 cmd = host->deferred_cmd;
3672 if (cmd && !sdhci_send_command_retry(host, cmd, flags))
3673 sdhci_finish_mrq(host, cmd->mrq);
3674
3675 spin_unlock_irqrestore(&host->lock, flags);
3676
3677 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3678 struct mmc_host *mmc = host->mmc;
3679
3680 mmc->ops->card_event(mmc);
3681 mmc_detect_change(mmc, msecs_to_jiffies(200));
3682 }
3683
3684 return IRQ_HANDLED;
3685}
3686
3687/*****************************************************************************\
3688 * *
3689 * Suspend/resume *
3690 * *
3691\*****************************************************************************/
3692
3693#ifdef CONFIG_PM
3694
3695static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
3696{
3697 return mmc_card_is_removable(host->mmc) &&
3698 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3699 !mmc_can_gpio_cd(host->mmc);
3700}
3701
3702/*
3703 * To enable wakeup events, the corresponding events have to be enabled in
3704 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
3705 * Table' in the SD Host Controller Standard Specification.
3706 * It is useless to restore SDHCI_INT_ENABLE state in
3707 * sdhci_disable_irq_wakeups() since it will be set by
3708 * sdhci_enable_card_detection() or sdhci_init().
3709 */
3710static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
3711{
3712 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
3713 SDHCI_WAKE_ON_INT;
3714 u32 irq_val = 0;
3715 u8 wake_val = 0;
3716 u8 val;
3717
3718 if (sdhci_cd_irq_can_wakeup(host)) {
3719 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
3720 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
3721 }
3722
3723 if (mmc_card_wake_sdio_irq(host->mmc)) {
3724 wake_val |= SDHCI_WAKE_ON_INT;
3725 irq_val |= SDHCI_INT_CARD_INT;
3726 }
3727
3728 if (!irq_val)
3729 return false;
3730
3731 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3732 val &= ~mask;
3733 val |= wake_val;
3734 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3735
3736 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
3737
3738 host->irq_wake_enabled = !enable_irq_wake(host->irq);
3739
3740 return host->irq_wake_enabled;
3741}
3742
3743static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3744{
3745 u8 val;
3746 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3747 | SDHCI_WAKE_ON_INT;
3748
3749 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3750 val &= ~mask;
3751 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3752
3753 disable_irq_wake(host->irq);
3754
3755 host->irq_wake_enabled = false;
3756}
3757
3758int sdhci_suspend_host(struct sdhci_host *host)
3759{
3760 sdhci_disable_card_detection(host);
3761
3762 mmc_retune_timer_stop(host->mmc);
3763
3764 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
3765 !sdhci_enable_irq_wakeups(host)) {
3766 host->ier = 0;
3767 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3768 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3769 free_irq(host->irq, host);
3770 }
3771
3772 return 0;
3773}
3774
3775EXPORT_SYMBOL_GPL(sdhci_suspend_host);
3776
3777int sdhci_resume_host(struct sdhci_host *host)
3778{
3779 struct mmc_host *mmc = host->mmc;
3780 int ret = 0;
3781
3782 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3783 if (host->ops->enable_dma)
3784 host->ops->enable_dma(host);
3785 }
3786
3787 if ((mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3788 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3789 /* Card keeps power but host controller does not */
3790 sdhci_init(host, 0);
3791 host->pwr = 0;
3792 host->clock = 0;
3793 host->reinit_uhs = true;
3794 mmc->ops->set_ios(mmc, &mmc->ios);
3795 } else {
3796 sdhci_init(host, (mmc->pm_flags & MMC_PM_KEEP_POWER));
3797 }
3798
3799 if (host->irq_wake_enabled) {
3800 sdhci_disable_irq_wakeups(host);
3801 } else {
3802 ret = request_threaded_irq(host->irq, sdhci_irq,
3803 sdhci_thread_irq, IRQF_SHARED,
3804 mmc_hostname(mmc), host);
3805 if (ret)
3806 return ret;
3807 }
3808
3809 sdhci_enable_card_detection(host);
3810
3811 return ret;
3812}
3813
3814EXPORT_SYMBOL_GPL(sdhci_resume_host);
3815
3816int sdhci_runtime_suspend_host(struct sdhci_host *host)
3817{
3818 unsigned long flags;
3819
3820 mmc_retune_timer_stop(host->mmc);
3821
3822 spin_lock_irqsave(&host->lock, flags);
3823 host->ier &= SDHCI_INT_CARD_INT;
3824 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3825 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3826 spin_unlock_irqrestore(&host->lock, flags);
3827
3828 synchronize_hardirq(host->irq);
3829
3830 spin_lock_irqsave(&host->lock, flags);
3831 host->runtime_suspended = true;
3832 spin_unlock_irqrestore(&host->lock, flags);
3833
3834 return 0;
3835}
3836EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3837
3838int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
3839{
3840 struct mmc_host *mmc = host->mmc;
3841 unsigned long flags;
3842 int host_flags = host->flags;
3843
3844 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3845 if (host->ops->enable_dma)
3846 host->ops->enable_dma(host);
3847 }
3848
3849 sdhci_init(host, soft_reset);
3850
3851 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3852 mmc->ios.power_mode != MMC_POWER_OFF) {
3853 /* Force clock and power re-program */
3854 host->pwr = 0;
3855 host->clock = 0;
3856 host->reinit_uhs = true;
3857 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3858 mmc->ops->set_ios(mmc, &mmc->ios);
3859
3860 if ((host_flags & SDHCI_PV_ENABLED) &&
3861 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3862 spin_lock_irqsave(&host->lock, flags);
3863 sdhci_enable_preset_value(host, true);
3864 spin_unlock_irqrestore(&host->lock, flags);
3865 }
3866
3867 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3868 mmc->ops->hs400_enhanced_strobe)
3869 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3870 }
3871
3872 spin_lock_irqsave(&host->lock, flags);
3873
3874 host->runtime_suspended = false;
3875
3876 /* Enable SDIO IRQ */
3877 if (sdio_irq_claimed(mmc))
3878 sdhci_enable_sdio_irq_nolock(host, true);
3879
3880 /* Enable Card Detection */
3881 sdhci_enable_card_detection(host);
3882
3883 spin_unlock_irqrestore(&host->lock, flags);
3884
3885 return 0;
3886}
3887EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3888
3889#endif /* CONFIG_PM */
3890
3891/*****************************************************************************\
3892 * *
3893 * Command Queue Engine (CQE) helpers *
3894 * *
3895\*****************************************************************************/
3896
3897void sdhci_cqe_enable(struct mmc_host *mmc)
3898{
3899 struct sdhci_host *host = mmc_priv(mmc);
3900 unsigned long flags;
3901 u8 ctrl;
3902
3903 spin_lock_irqsave(&host->lock, flags);
3904
3905 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3906 ctrl &= ~SDHCI_CTRL_DMA_MASK;
3907 /*
3908 * Host from V4.10 supports ADMA3 DMA type.
3909 * ADMA3 performs integrated descriptor which is more suitable
3910 * for cmd queuing to fetch both command and transfer descriptors.
3911 */
3912 if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
3913 ctrl |= SDHCI_CTRL_ADMA3;
3914 else if (host->flags & SDHCI_USE_64_BIT_DMA)
3915 ctrl |= SDHCI_CTRL_ADMA64;
3916 else
3917 ctrl |= SDHCI_CTRL_ADMA32;
3918 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3919
3920 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3921 SDHCI_BLOCK_SIZE);
3922
3923 /* Set maximum timeout */
3924 sdhci_set_timeout(host, NULL);
3925
3926 host->ier = host->cqe_ier;
3927
3928 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3929 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3930
3931 host->cqe_on = true;
3932
3933 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3934 mmc_hostname(mmc), host->ier,
3935 sdhci_readl(host, SDHCI_INT_STATUS));
3936
3937 spin_unlock_irqrestore(&host->lock, flags);
3938}
3939EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3940
3941void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3942{
3943 struct sdhci_host *host = mmc_priv(mmc);
3944 unsigned long flags;
3945
3946 spin_lock_irqsave(&host->lock, flags);
3947
3948 sdhci_set_default_irqs(host);
3949
3950 host->cqe_on = false;
3951
3952 if (recovery)
3953 sdhci_reset_for(host, CQE_RECOVERY);
3954
3955 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3956 mmc_hostname(mmc), host->ier,
3957 sdhci_readl(host, SDHCI_INT_STATUS));
3958
3959 spin_unlock_irqrestore(&host->lock, flags);
3960}
3961EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3962
3963bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3964 int *data_error)
3965{
3966 u32 mask;
3967
3968 if (!host->cqe_on)
3969 return false;
3970
3971 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC)) {
3972 *cmd_error = -EILSEQ;
3973 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
3974 sdhci_err_stats_inc(host, CMD_CRC);
3975 } else if (intmask & SDHCI_INT_TIMEOUT) {
3976 *cmd_error = -ETIMEDOUT;
3977 sdhci_err_stats_inc(host, CMD_TIMEOUT);
3978 } else
3979 *cmd_error = 0;
3980
3981 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC)) {
3982 *data_error = -EILSEQ;
3983 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
3984 sdhci_err_stats_inc(host, DAT_CRC);
3985 } else if (intmask & SDHCI_INT_DATA_TIMEOUT) {
3986 *data_error = -ETIMEDOUT;
3987 sdhci_err_stats_inc(host, DAT_TIMEOUT);
3988 } else if (intmask & SDHCI_INT_ADMA_ERROR) {
3989 *data_error = -EIO;
3990 sdhci_err_stats_inc(host, ADMA);
3991 } else
3992 *data_error = 0;
3993
3994 /* Clear selected interrupts. */
3995 mask = intmask & host->cqe_ier;
3996 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3997
3998 if (intmask & SDHCI_INT_BUS_POWER)
3999 pr_err("%s: Card is consuming too much power!\n",
4000 mmc_hostname(host->mmc));
4001
4002 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
4003 if (intmask) {
4004 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
4005 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
4006 mmc_hostname(host->mmc), intmask);
4007 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
4008 sdhci_dumpregs(host);
4009 }
4010
4011 return true;
4012}
4013EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
4014
4015/*****************************************************************************\
4016 * *
4017 * Device allocation/registration *
4018 * *
4019\*****************************************************************************/
4020
4021struct sdhci_host *sdhci_alloc_host(struct device *dev,
4022 size_t priv_size)
4023{
4024 struct mmc_host *mmc;
4025 struct sdhci_host *host;
4026
4027 WARN_ON(dev == NULL);
4028
4029 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
4030 if (!mmc)
4031 return ERR_PTR(-ENOMEM);
4032
4033 host = mmc_priv(mmc);
4034 host->mmc = mmc;
4035 host->mmc_host_ops = sdhci_ops;
4036 mmc->ops = &host->mmc_host_ops;
4037
4038 host->flags = SDHCI_SIGNALING_330;
4039
4040 host->cqe_ier = SDHCI_CQE_INT_MASK;
4041 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
4042
4043 host->tuning_delay = -1;
4044 host->tuning_loop_count = MAX_TUNING_LOOP;
4045
4046 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
4047
4048 /*
4049 * The DMA table descriptor count is calculated as the maximum
4050 * number of segments times 2, to allow for an alignment
4051 * descriptor for each segment, plus 1 for a nop end descriptor.
4052 */
4053 host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
4054 host->max_adma = 65536;
4055
4056 host->max_timeout_count = 0xE;
4057
4058 return host;
4059}
4060
4061EXPORT_SYMBOL_GPL(sdhci_alloc_host);
4062
4063static int sdhci_set_dma_mask(struct sdhci_host *host)
4064{
4065 struct mmc_host *mmc = host->mmc;
4066 struct device *dev = mmc_dev(mmc);
4067 int ret = -EINVAL;
4068
4069 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
4070 host->flags &= ~SDHCI_USE_64_BIT_DMA;
4071
4072 /* Try 64-bit mask if hardware is capable of it */
4073 if (host->flags & SDHCI_USE_64_BIT_DMA) {
4074 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
4075 if (ret) {
4076 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
4077 mmc_hostname(mmc));
4078 host->flags &= ~SDHCI_USE_64_BIT_DMA;
4079 }
4080 }
4081
4082 /* 32-bit mask as default & fallback */
4083 if (ret) {
4084 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
4085 if (ret)
4086 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
4087 mmc_hostname(mmc));
4088 }
4089
4090 return ret;
4091}
4092
4093void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
4094 const u32 *caps, const u32 *caps1)
4095{
4096 u16 v;
4097 u64 dt_caps_mask = 0;
4098 u64 dt_caps = 0;
4099
4100 if (host->read_caps)
4101 return;
4102
4103 host->read_caps = true;
4104
4105 if (debug_quirks)
4106 host->quirks = debug_quirks;
4107
4108 if (debug_quirks2)
4109 host->quirks2 = debug_quirks2;
4110
4111 sdhci_reset_for_all(host);
4112
4113 if (host->v4_mode)
4114 sdhci_do_enable_v4_mode(host);
4115
4116 device_property_read_u64(mmc_dev(host->mmc),
4117 "sdhci-caps-mask", &dt_caps_mask);
4118 device_property_read_u64(mmc_dev(host->mmc),
4119 "sdhci-caps", &dt_caps);
4120
4121 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
4122 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
4123
4124 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
4125 return;
4126
4127 if (caps) {
4128 host->caps = *caps;
4129 } else {
4130 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
4131 host->caps &= ~lower_32_bits(dt_caps_mask);
4132 host->caps |= lower_32_bits(dt_caps);
4133 }
4134
4135 if (host->version < SDHCI_SPEC_300)
4136 return;
4137
4138 if (caps1) {
4139 host->caps1 = *caps1;
4140 } else {
4141 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
4142 host->caps1 &= ~upper_32_bits(dt_caps_mask);
4143 host->caps1 |= upper_32_bits(dt_caps);
4144 }
4145}
4146EXPORT_SYMBOL_GPL(__sdhci_read_caps);
4147
4148static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
4149{
4150 struct mmc_host *mmc = host->mmc;
4151 unsigned int max_blocks;
4152 unsigned int bounce_size;
4153 int ret;
4154
4155 /*
4156 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
4157 * has diminishing returns, this is probably because SD/MMC
4158 * cards are usually optimized to handle this size of requests.
4159 */
4160 bounce_size = SZ_64K;
4161 /*
4162 * Adjust downwards to maximum request size if this is less
4163 * than our segment size, else hammer down the maximum
4164 * request size to the maximum buffer size.
4165 */
4166 if (mmc->max_req_size < bounce_size)
4167 bounce_size = mmc->max_req_size;
4168 max_blocks = bounce_size / 512;
4169
4170 /*
4171 * When we just support one segment, we can get significant
4172 * speedups by the help of a bounce buffer to group scattered
4173 * reads/writes together.
4174 */
4175 host->bounce_buffer = devm_kmalloc(mmc_dev(mmc),
4176 bounce_size,
4177 GFP_KERNEL);
4178 if (!host->bounce_buffer) {
4179 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
4180 mmc_hostname(mmc),
4181 bounce_size);
4182 /*
4183 * Exiting with zero here makes sure we proceed with
4184 * mmc->max_segs == 1.
4185 */
4186 return;
4187 }
4188
4189 host->bounce_addr = dma_map_single(mmc_dev(mmc),
4190 host->bounce_buffer,
4191 bounce_size,
4192 DMA_BIDIRECTIONAL);
4193 ret = dma_mapping_error(mmc_dev(mmc), host->bounce_addr);
4194 if (ret) {
4195 devm_kfree(mmc_dev(mmc), host->bounce_buffer);
4196 host->bounce_buffer = NULL;
4197 /* Again fall back to max_segs == 1 */
4198 return;
4199 }
4200
4201 host->bounce_buffer_size = bounce_size;
4202
4203 /* Lie about this since we're bouncing */
4204 mmc->max_segs = max_blocks;
4205 mmc->max_seg_size = bounce_size;
4206 mmc->max_req_size = bounce_size;
4207
4208 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
4209 mmc_hostname(mmc), max_blocks, bounce_size);
4210}
4211
4212static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
4213{
4214 /*
4215 * According to SD Host Controller spec v4.10, bit[27] added from
4216 * version 4.10 in Capabilities Register is used as 64-bit System
4217 * Address support for V4 mode.
4218 */
4219 if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
4220 return host->caps & SDHCI_CAN_64BIT_V4;
4221
4222 return host->caps & SDHCI_CAN_64BIT;
4223}
4224
4225int sdhci_setup_host(struct sdhci_host *host)
4226{
4227 struct mmc_host *mmc;
4228 u32 max_current_caps;
4229 unsigned int ocr_avail;
4230 unsigned int override_timeout_clk;
4231 u32 max_clk;
4232 int ret = 0;
4233 bool enable_vqmmc = false;
4234
4235 WARN_ON(host == NULL);
4236 if (host == NULL)
4237 return -EINVAL;
4238
4239 mmc = host->mmc;
4240
4241 /*
4242 * If there are external regulators, get them. Note this must be done
4243 * early before resetting the host and reading the capabilities so that
4244 * the host can take the appropriate action if regulators are not
4245 * available.
4246 */
4247 if (!mmc->supply.vqmmc) {
4248 ret = mmc_regulator_get_supply(mmc);
4249 if (ret)
4250 return ret;
4251 enable_vqmmc = true;
4252 }
4253
4254 DBG("Version: 0x%08x | Present: 0x%08x\n",
4255 sdhci_readw(host, SDHCI_HOST_VERSION),
4256 sdhci_readl(host, SDHCI_PRESENT_STATE));
4257 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
4258 sdhci_readl(host, SDHCI_CAPABILITIES),
4259 sdhci_readl(host, SDHCI_CAPABILITIES_1));
4260
4261 sdhci_read_caps(host);
4262
4263 override_timeout_clk = host->timeout_clk;
4264
4265 if (host->version > SDHCI_SPEC_420) {
4266 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
4267 mmc_hostname(mmc), host->version);
4268 }
4269
4270 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
4271 host->flags |= SDHCI_USE_SDMA;
4272 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
4273 DBG("Controller doesn't have SDMA capability\n");
4274 else
4275 host->flags |= SDHCI_USE_SDMA;
4276
4277 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
4278 (host->flags & SDHCI_USE_SDMA)) {
4279 DBG("Disabling DMA as it is marked broken\n");
4280 host->flags &= ~SDHCI_USE_SDMA;
4281 }
4282
4283 if ((host->version >= SDHCI_SPEC_200) &&
4284 (host->caps & SDHCI_CAN_DO_ADMA2))
4285 host->flags |= SDHCI_USE_ADMA;
4286
4287 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
4288 (host->flags & SDHCI_USE_ADMA)) {
4289 DBG("Disabling ADMA as it is marked broken\n");
4290 host->flags &= ~SDHCI_USE_ADMA;
4291 }
4292
4293 if (sdhci_can_64bit_dma(host))
4294 host->flags |= SDHCI_USE_64_BIT_DMA;
4295
4296 if (host->use_external_dma) {
4297 ret = sdhci_external_dma_init(host);
4298 if (ret == -EPROBE_DEFER)
4299 goto unreg;
4300 /*
4301 * Fall back to use the DMA/PIO integrated in standard SDHCI
4302 * instead of external DMA devices.
4303 */
4304 else if (ret)
4305 sdhci_switch_external_dma(host, false);
4306 /* Disable internal DMA sources */
4307 else
4308 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4309 }
4310
4311 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
4312 if (host->ops->set_dma_mask)
4313 ret = host->ops->set_dma_mask(host);
4314 else
4315 ret = sdhci_set_dma_mask(host);
4316
4317 if (!ret && host->ops->enable_dma)
4318 ret = host->ops->enable_dma(host);
4319
4320 if (ret) {
4321 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
4322 mmc_hostname(mmc));
4323 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4324
4325 ret = 0;
4326 }
4327 }
4328
4329 /* SDMA does not support 64-bit DMA if v4 mode not set */
4330 if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
4331 host->flags &= ~SDHCI_USE_SDMA;
4332
4333 if (host->flags & SDHCI_USE_ADMA) {
4334 dma_addr_t dma;
4335 void *buf;
4336
4337 if (!(host->flags & SDHCI_USE_64_BIT_DMA))
4338 host->alloc_desc_sz = SDHCI_ADMA2_32_DESC_SZ;
4339 else if (!host->alloc_desc_sz)
4340 host->alloc_desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
4341
4342 host->desc_sz = host->alloc_desc_sz;
4343 host->adma_table_sz = host->adma_table_cnt * host->desc_sz;
4344
4345 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
4346 /*
4347 * Use zalloc to zero the reserved high 32-bits of 128-bit
4348 * descriptors so that they never need to be written.
4349 */
4350 buf = dma_alloc_coherent(mmc_dev(mmc),
4351 host->align_buffer_sz + host->adma_table_sz,
4352 &dma, GFP_KERNEL);
4353 if (!buf) {
4354 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
4355 mmc_hostname(mmc));
4356 host->flags &= ~SDHCI_USE_ADMA;
4357 } else if ((dma + host->align_buffer_sz) &
4358 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
4359 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
4360 mmc_hostname(mmc));
4361 host->flags &= ~SDHCI_USE_ADMA;
4362 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4363 host->adma_table_sz, buf, dma);
4364 } else {
4365 host->align_buffer = buf;
4366 host->align_addr = dma;
4367
4368 host->adma_table = buf + host->align_buffer_sz;
4369 host->adma_addr = dma + host->align_buffer_sz;
4370 }
4371 }
4372
4373 /*
4374 * If we use DMA, then it's up to the caller to set the DMA
4375 * mask, but PIO does not need the hw shim so we set a new
4376 * mask here in that case.
4377 */
4378 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
4379 host->dma_mask = DMA_BIT_MASK(64);
4380 mmc_dev(mmc)->dma_mask = &host->dma_mask;
4381 }
4382
4383 if (host->version >= SDHCI_SPEC_300)
4384 host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps);
4385 else
4386 host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps);
4387
4388 host->max_clk *= 1000000;
4389 if (host->max_clk == 0 || host->quirks &
4390 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4391 if (!host->ops->get_max_clock) {
4392 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
4393 mmc_hostname(mmc));
4394 ret = -ENODEV;
4395 goto undma;
4396 }
4397 host->max_clk = host->ops->get_max_clock(host);
4398 }
4399
4400 /*
4401 * In case of Host Controller v3.00, find out whether clock
4402 * multiplier is supported.
4403 */
4404 host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1);
4405
4406 /*
4407 * In case the value in Clock Multiplier is 0, then programmable
4408 * clock mode is not supported, otherwise the actual clock
4409 * multiplier is one more than the value of Clock Multiplier
4410 * in the Capabilities Register.
4411 */
4412 if (host->clk_mul)
4413 host->clk_mul += 1;
4414
4415 /*
4416 * Set host parameters.
4417 */
4418 max_clk = host->max_clk;
4419
4420 if (host->ops->get_min_clock)
4421 mmc->f_min = host->ops->get_min_clock(host);
4422 else if (host->version >= SDHCI_SPEC_300) {
4423 if (host->clk_mul)
4424 max_clk = host->max_clk * host->clk_mul;
4425 /*
4426 * Divided Clock Mode minimum clock rate is always less than
4427 * Programmable Clock Mode minimum clock rate.
4428 */
4429 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
4430 } else
4431 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
4432
4433 if (!mmc->f_max || mmc->f_max > max_clk)
4434 mmc->f_max = max_clk;
4435
4436 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4437 host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps);
4438
4439 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
4440 host->timeout_clk *= 1000;
4441
4442 if (host->timeout_clk == 0) {
4443 if (!host->ops->get_timeout_clock) {
4444 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
4445 mmc_hostname(mmc));
4446 ret = -ENODEV;
4447 goto undma;
4448 }
4449
4450 host->timeout_clk =
4451 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
4452 1000);
4453 }
4454
4455 if (override_timeout_clk)
4456 host->timeout_clk = override_timeout_clk;
4457
4458 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
4459 host->ops->get_max_timeout_count(host) : 1 << 27;
4460 mmc->max_busy_timeout /= host->timeout_clk;
4461 }
4462
4463 if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
4464 !host->ops->get_max_timeout_count)
4465 mmc->max_busy_timeout = 0;
4466
4467 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_CMD23;
4468 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
4469
4470 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
4471 host->flags |= SDHCI_AUTO_CMD12;
4472
4473 /*
4474 * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
4475 * For v4 mode, SDMA may use Auto-CMD23 as well.
4476 */
4477 if ((host->version >= SDHCI_SPEC_300) &&
4478 ((host->flags & SDHCI_USE_ADMA) ||
4479 !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
4480 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
4481 host->flags |= SDHCI_AUTO_CMD23;
4482 DBG("Auto-CMD23 available\n");
4483 } else {
4484 DBG("Auto-CMD23 unavailable\n");
4485 }
4486
4487 /*
4488 * A controller may support 8-bit width, but the board itself
4489 * might not have the pins brought out. Boards that support
4490 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
4491 * their platform code before calling sdhci_add_host(), and we
4492 * won't assume 8-bit width for hosts without that CAP.
4493 */
4494 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
4495 mmc->caps |= MMC_CAP_4_BIT_DATA;
4496
4497 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
4498 mmc->caps &= ~MMC_CAP_CMD23;
4499
4500 if (host->caps & SDHCI_CAN_DO_HISPD)
4501 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
4502
4503 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4504 mmc_card_is_removable(mmc) &&
4505 mmc_gpio_get_cd(mmc) < 0)
4506 mmc->caps |= MMC_CAP_NEEDS_POLL;
4507
4508 if (!IS_ERR(mmc->supply.vqmmc)) {
4509 if (enable_vqmmc) {
4510 ret = regulator_enable(mmc->supply.vqmmc);
4511 host->sdhci_core_to_disable_vqmmc = !ret;
4512 }
4513
4514 /* If vqmmc provides no 1.8V signalling, then there's no UHS */
4515 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
4516 1950000))
4517 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
4518 SDHCI_SUPPORT_SDR50 |
4519 SDHCI_SUPPORT_DDR50);
4520
4521 /* In eMMC case vqmmc might be a fixed 1.8V regulator */
4522 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
4523 3600000))
4524 host->flags &= ~SDHCI_SIGNALING_330;
4525
4526 if (ret) {
4527 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
4528 mmc_hostname(mmc), ret);
4529 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
4530 }
4531
4532 }
4533
4534 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
4535 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4536 SDHCI_SUPPORT_DDR50);
4537 /*
4538 * The SDHCI controller in a SoC might support HS200/HS400
4539 * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
4540 * but if the board is modeled such that the IO lines are not
4541 * connected to 1.8v then HS200/HS400 cannot be supported.
4542 * Disable HS200/HS400 if the board does not have 1.8v connected
4543 * to the IO lines. (Applicable for other modes in 1.8v)
4544 */
4545 mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
4546 mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
4547 }
4548
4549 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
4550 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4551 SDHCI_SUPPORT_DDR50))
4552 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
4553
4554 /* SDR104 supports also implies SDR50 support */
4555 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
4556 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
4557 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
4558 * field can be promoted to support HS200.
4559 */
4560 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
4561 mmc->caps2 |= MMC_CAP2_HS200;
4562 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
4563 mmc->caps |= MMC_CAP_UHS_SDR50;
4564 }
4565
4566 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
4567 (host->caps1 & SDHCI_SUPPORT_HS400))
4568 mmc->caps2 |= MMC_CAP2_HS400;
4569
4570 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
4571 (IS_ERR(mmc->supply.vqmmc) ||
4572 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
4573 1300000)))
4574 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
4575
4576 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
4577 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
4578 mmc->caps |= MMC_CAP_UHS_DDR50;
4579
4580 /* Does the host need tuning for SDR50? */
4581 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
4582 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
4583
4584 /* Driver Type(s) (A, C, D) supported by the host */
4585 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
4586 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
4587 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
4588 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
4589 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
4590 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
4591
4592 /* Initial value for re-tuning timer count */
4593 host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK,
4594 host->caps1);
4595
4596 /*
4597 * In case Re-tuning Timer is not disabled, the actual value of
4598 * re-tuning timer will be 2 ^ (n - 1).
4599 */
4600 if (host->tuning_count)
4601 host->tuning_count = 1 << (host->tuning_count - 1);
4602
4603 /* Re-tuning mode supported by the Host Controller */
4604 host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1);
4605
4606 ocr_avail = 0;
4607
4608 /*
4609 * According to SD Host Controller spec v3.00, if the Host System
4610 * can afford more than 150mA, Host Driver should set XPC to 1. Also
4611 * the value is meaningful only if Voltage Support in the Capabilities
4612 * register is set. The actual current value is 4 times the register
4613 * value.
4614 */
4615 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
4616 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
4617 int curr = regulator_get_current_limit(mmc->supply.vmmc);
4618 if (curr > 0) {
4619
4620 /* convert to SDHCI_MAX_CURRENT format */
4621 curr = curr/1000; /* convert to mA */
4622 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
4623
4624 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
4625 max_current_caps =
4626 FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, curr) |
4627 FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, curr) |
4628 FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, curr);
4629 }
4630 }
4631
4632 if (host->caps & SDHCI_CAN_VDD_330) {
4633 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
4634
4635 mmc->max_current_330 = FIELD_GET(SDHCI_MAX_CURRENT_330_MASK,
4636 max_current_caps) *
4637 SDHCI_MAX_CURRENT_MULTIPLIER;
4638 }
4639 if (host->caps & SDHCI_CAN_VDD_300) {
4640 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
4641
4642 mmc->max_current_300 = FIELD_GET(SDHCI_MAX_CURRENT_300_MASK,
4643 max_current_caps) *
4644 SDHCI_MAX_CURRENT_MULTIPLIER;
4645 }
4646 if (host->caps & SDHCI_CAN_VDD_180) {
4647 ocr_avail |= MMC_VDD_165_195;
4648
4649 mmc->max_current_180 = FIELD_GET(SDHCI_MAX_CURRENT_180_MASK,
4650 max_current_caps) *
4651 SDHCI_MAX_CURRENT_MULTIPLIER;
4652 }
4653
4654 /* If OCR set by host, use it instead. */
4655 if (host->ocr_mask)
4656 ocr_avail = host->ocr_mask;
4657
4658 /* If OCR set by external regulators, give it highest prio. */
4659 if (mmc->ocr_avail)
4660 ocr_avail = mmc->ocr_avail;
4661
4662 mmc->ocr_avail = ocr_avail;
4663 mmc->ocr_avail_sdio = ocr_avail;
4664 if (host->ocr_avail_sdio)
4665 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
4666 mmc->ocr_avail_sd = ocr_avail;
4667 if (host->ocr_avail_sd)
4668 mmc->ocr_avail_sd &= host->ocr_avail_sd;
4669 else /* normal SD controllers don't support 1.8V */
4670 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
4671 mmc->ocr_avail_mmc = ocr_avail;
4672 if (host->ocr_avail_mmc)
4673 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
4674
4675 if (mmc->ocr_avail == 0) {
4676 pr_err("%s: Hardware doesn't report any support voltages.\n",
4677 mmc_hostname(mmc));
4678 ret = -ENODEV;
4679 goto unreg;
4680 }
4681
4682 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
4683 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
4684 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
4685 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
4686 host->flags |= SDHCI_SIGNALING_180;
4687
4688 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
4689 host->flags |= SDHCI_SIGNALING_120;
4690
4691 spin_lock_init(&host->lock);
4692
4693 /*
4694 * Maximum number of sectors in one transfer. Limited by SDMA boundary
4695 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
4696 * is less anyway.
4697 */
4698 mmc->max_req_size = 524288;
4699
4700 /*
4701 * Maximum number of segments. Depends on if the hardware
4702 * can do scatter/gather or not.
4703 */
4704 if (host->flags & SDHCI_USE_ADMA) {
4705 mmc->max_segs = SDHCI_MAX_SEGS;
4706 } else if (host->flags & SDHCI_USE_SDMA) {
4707 mmc->max_segs = 1;
4708 mmc->max_req_size = min_t(size_t, mmc->max_req_size,
4709 dma_max_mapping_size(mmc_dev(mmc)));
4710 } else { /* PIO */
4711 mmc->max_segs = SDHCI_MAX_SEGS;
4712 }
4713
4714 /*
4715 * Maximum segment size. Could be one segment with the maximum number
4716 * of bytes. When doing hardware scatter/gather, each entry cannot
4717 * be larger than 64 KiB though.
4718 */
4719 if (host->flags & SDHCI_USE_ADMA) {
4720 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) {
4721 host->max_adma = 65532; /* 32-bit alignment */
4722 mmc->max_seg_size = 65535;
4723 } else {
4724 mmc->max_seg_size = 65536;
4725 }
4726 } else {
4727 mmc->max_seg_size = mmc->max_req_size;
4728 }
4729
4730 /*
4731 * Maximum block size. This varies from controller to controller and
4732 * is specified in the capabilities register.
4733 */
4734 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4735 mmc->max_blk_size = 2;
4736 } else {
4737 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
4738 SDHCI_MAX_BLOCK_SHIFT;
4739 if (mmc->max_blk_size >= 3) {
4740 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
4741 mmc_hostname(mmc));
4742 mmc->max_blk_size = 0;
4743 }
4744 }
4745
4746 mmc->max_blk_size = 512 << mmc->max_blk_size;
4747
4748 /*
4749 * Maximum block count.
4750 */
4751 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
4752
4753 if (mmc->max_segs == 1)
4754 /* This may alter mmc->*_blk_* parameters */
4755 sdhci_allocate_bounce_buffer(host);
4756
4757 return 0;
4758
4759unreg:
4760 if (host->sdhci_core_to_disable_vqmmc)
4761 regulator_disable(mmc->supply.vqmmc);
4762undma:
4763 if (host->align_buffer)
4764 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4765 host->adma_table_sz, host->align_buffer,
4766 host->align_addr);
4767 host->adma_table = NULL;
4768 host->align_buffer = NULL;
4769
4770 return ret;
4771}
4772EXPORT_SYMBOL_GPL(sdhci_setup_host);
4773
4774void sdhci_cleanup_host(struct sdhci_host *host)
4775{
4776 struct mmc_host *mmc = host->mmc;
4777
4778 if (host->sdhci_core_to_disable_vqmmc)
4779 regulator_disable(mmc->supply.vqmmc);
4780
4781 if (host->align_buffer)
4782 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4783 host->adma_table_sz, host->align_buffer,
4784 host->align_addr);
4785
4786 if (host->use_external_dma)
4787 sdhci_external_dma_release(host);
4788
4789 host->adma_table = NULL;
4790 host->align_buffer = NULL;
4791}
4792EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
4793
4794int __sdhci_add_host(struct sdhci_host *host)
4795{
4796 unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI;
4797 struct mmc_host *mmc = host->mmc;
4798 int ret;
4799
4800 if ((mmc->caps2 & MMC_CAP2_CQE) &&
4801 (host->quirks & SDHCI_QUIRK_BROKEN_CQE)) {
4802 mmc->caps2 &= ~MMC_CAP2_CQE;
4803 mmc->cqe_ops = NULL;
4804 }
4805
4806 host->complete_wq = alloc_workqueue("sdhci", flags, 0);
4807 if (!host->complete_wq)
4808 return -ENOMEM;
4809
4810 INIT_WORK(&host->complete_work, sdhci_complete_work);
4811
4812 timer_setup(&host->timer, sdhci_timeout_timer, 0);
4813 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
4814
4815 init_waitqueue_head(&host->buf_ready_int);
4816
4817 sdhci_init(host, 0);
4818
4819 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
4820 IRQF_SHARED, mmc_hostname(mmc), host);
4821 if (ret) {
4822 pr_err("%s: Failed to request IRQ %d: %d\n",
4823 mmc_hostname(mmc), host->irq, ret);
4824 goto unwq;
4825 }
4826
4827 ret = sdhci_led_register(host);
4828 if (ret) {
4829 pr_err("%s: Failed to register LED device: %d\n",
4830 mmc_hostname(mmc), ret);
4831 goto unirq;
4832 }
4833
4834 ret = mmc_add_host(mmc);
4835 if (ret)
4836 goto unled;
4837
4838 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
4839 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
4840 host->use_external_dma ? "External DMA" :
4841 (host->flags & SDHCI_USE_ADMA) ?
4842 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
4843 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4844
4845 sdhci_enable_card_detection(host);
4846
4847 return 0;
4848
4849unled:
4850 sdhci_led_unregister(host);
4851unirq:
4852 sdhci_reset_for_all(host);
4853 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4854 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4855 free_irq(host->irq, host);
4856unwq:
4857 destroy_workqueue(host->complete_wq);
4858
4859 return ret;
4860}
4861EXPORT_SYMBOL_GPL(__sdhci_add_host);
4862
4863int sdhci_add_host(struct sdhci_host *host)
4864{
4865 int ret;
4866
4867 ret = sdhci_setup_host(host);
4868 if (ret)
4869 return ret;
4870
4871 ret = __sdhci_add_host(host);
4872 if (ret)
4873 goto cleanup;
4874
4875 return 0;
4876
4877cleanup:
4878 sdhci_cleanup_host(host);
4879
4880 return ret;
4881}
4882EXPORT_SYMBOL_GPL(sdhci_add_host);
4883
4884void sdhci_remove_host(struct sdhci_host *host, int dead)
4885{
4886 struct mmc_host *mmc = host->mmc;
4887 unsigned long flags;
4888
4889 if (dead) {
4890 spin_lock_irqsave(&host->lock, flags);
4891
4892 host->flags |= SDHCI_DEVICE_DEAD;
4893
4894 if (sdhci_has_requests(host)) {
4895 pr_err("%s: Controller removed during "
4896 " transfer!\n", mmc_hostname(mmc));
4897 sdhci_error_out_mrqs(host, -ENOMEDIUM);
4898 }
4899
4900 spin_unlock_irqrestore(&host->lock, flags);
4901 }
4902
4903 sdhci_disable_card_detection(host);
4904
4905 mmc_remove_host(mmc);
4906
4907 sdhci_led_unregister(host);
4908
4909 if (!dead)
4910 sdhci_reset_for_all(host);
4911
4912 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4913 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4914 free_irq(host->irq, host);
4915
4916 del_timer_sync(&host->timer);
4917 del_timer_sync(&host->data_timer);
4918
4919 destroy_workqueue(host->complete_wq);
4920
4921 if (host->sdhci_core_to_disable_vqmmc)
4922 regulator_disable(mmc->supply.vqmmc);
4923
4924 if (host->align_buffer)
4925 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4926 host->adma_table_sz, host->align_buffer,
4927 host->align_addr);
4928
4929 if (host->use_external_dma)
4930 sdhci_external_dma_release(host);
4931
4932 host->adma_table = NULL;
4933 host->align_buffer = NULL;
4934}
4935
4936EXPORT_SYMBOL_GPL(sdhci_remove_host);
4937
4938void sdhci_free_host(struct sdhci_host *host)
4939{
4940 mmc_free_host(host->mmc);
4941}
4942
4943EXPORT_SYMBOL_GPL(sdhci_free_host);
4944
4945/*****************************************************************************\
4946 * *
4947 * Driver init/exit *
4948 * *
4949\*****************************************************************************/
4950
4951static int __init sdhci_drv_init(void)
4952{
4953 pr_info(DRIVER_NAME
4954 ": Secure Digital Host Controller Interface driver\n");
4955 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4956
4957 return 0;
4958}
4959
4960static void __exit sdhci_drv_exit(void)
4961{
4962}
4963
4964module_init(sdhci_drv_init);
4965module_exit(sdhci_drv_exit);
4966
4967module_param(debug_quirks, uint, 0444);
4968module_param(debug_quirks2, uint, 0444);
4969
4970MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4971MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4972MODULE_LICENSE("GPL");
4973
4974MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4975MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 *
5 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 *
7 * Thanks to the following companies for their support:
8 *
9 * - JMicron (hardware and technical support)
10 */
11
12#include <linux/bitfield.h>
13#include <linux/delay.h>
14#include <linux/dmaengine.h>
15#include <linux/ktime.h>
16#include <linux/highmem.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/dma-mapping.h>
20#include <linux/slab.h>
21#include <linux/scatterlist.h>
22#include <linux/sizes.h>
23#include <linux/regulator/consumer.h>
24#include <linux/pm_runtime.h>
25#include <linux/of.h>
26#include <linux/bug.h>
27#include <linux/leds.h>
28
29#include <linux/mmc/mmc.h>
30#include <linux/mmc/host.h>
31#include <linux/mmc/card.h>
32#include <linux/mmc/sdio.h>
33#include <linux/mmc/slot-gpio.h>
34
35#include "sdhci.h"
36
37#define DRIVER_NAME "sdhci"
38
39#define DBG(f, x...) \
40 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
41
42#define SDHCI_DUMP(f, x...) \
43 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
44
45#define MAX_TUNING_LOOP 40
46
47static unsigned int debug_quirks = 0;
48static unsigned int debug_quirks2;
49
50static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
51
52void sdhci_dumpregs(struct sdhci_host *host)
53{
54 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
55
56 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
57 sdhci_readl(host, SDHCI_DMA_ADDRESS),
58 sdhci_readw(host, SDHCI_HOST_VERSION));
59 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
60 sdhci_readw(host, SDHCI_BLOCK_SIZE),
61 sdhci_readw(host, SDHCI_BLOCK_COUNT));
62 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
63 sdhci_readl(host, SDHCI_ARGUMENT),
64 sdhci_readw(host, SDHCI_TRANSFER_MODE));
65 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
66 sdhci_readl(host, SDHCI_PRESENT_STATE),
67 sdhci_readb(host, SDHCI_HOST_CONTROL));
68 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
69 sdhci_readb(host, SDHCI_POWER_CONTROL),
70 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
71 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
72 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
73 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
74 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
75 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
76 sdhci_readl(host, SDHCI_INT_STATUS));
77 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
78 sdhci_readl(host, SDHCI_INT_ENABLE),
79 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
80 SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
81 sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
82 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
83 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
84 sdhci_readl(host, SDHCI_CAPABILITIES),
85 sdhci_readl(host, SDHCI_CAPABILITIES_1));
86 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
87 sdhci_readw(host, SDHCI_COMMAND),
88 sdhci_readl(host, SDHCI_MAX_CURRENT));
89 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
90 sdhci_readl(host, SDHCI_RESPONSE),
91 sdhci_readl(host, SDHCI_RESPONSE + 4));
92 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
93 sdhci_readl(host, SDHCI_RESPONSE + 8),
94 sdhci_readl(host, SDHCI_RESPONSE + 12));
95 SDHCI_DUMP("Host ctl2: 0x%08x\n",
96 sdhci_readw(host, SDHCI_HOST_CONTROL2));
97
98 if (host->flags & SDHCI_USE_ADMA) {
99 if (host->flags & SDHCI_USE_64_BIT_DMA) {
100 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
101 sdhci_readl(host, SDHCI_ADMA_ERROR),
102 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
103 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
104 } else {
105 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
106 sdhci_readl(host, SDHCI_ADMA_ERROR),
107 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
108 }
109 }
110
111 if (host->ops->dump_uhs2_regs)
112 host->ops->dump_uhs2_regs(host);
113
114 if (host->ops->dump_vendor_regs)
115 host->ops->dump_vendor_regs(host);
116
117 SDHCI_DUMP("============================================\n");
118}
119EXPORT_SYMBOL_GPL(sdhci_dumpregs);
120
121/*****************************************************************************\
122 * *
123 * Low level functions *
124 * *
125\*****************************************************************************/
126
127static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
128{
129 u16 ctrl2;
130
131 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
132 if (ctrl2 & SDHCI_CTRL_V4_MODE)
133 return;
134
135 ctrl2 |= SDHCI_CTRL_V4_MODE;
136 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
137}
138
139/*
140 * This can be called before sdhci_add_host() by Vendor's host controller
141 * driver to enable v4 mode if supported.
142 */
143void sdhci_enable_v4_mode(struct sdhci_host *host)
144{
145 host->v4_mode = true;
146 sdhci_do_enable_v4_mode(host);
147}
148EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
149
150bool sdhci_data_line_cmd(struct mmc_command *cmd)
151{
152 return cmd->data || cmd->flags & MMC_RSP_BUSY;
153}
154EXPORT_SYMBOL_GPL(sdhci_data_line_cmd);
155
156static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
157{
158 u32 present;
159
160 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
161 !mmc_card_is_removable(host->mmc) || mmc_can_gpio_cd(host->mmc))
162 return;
163
164 if (enable) {
165 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
166 SDHCI_CARD_PRESENT;
167
168 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
169 SDHCI_INT_CARD_INSERT;
170 } else {
171 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
172 }
173
174 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
175 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
176}
177
178static void sdhci_enable_card_detection(struct sdhci_host *host)
179{
180 sdhci_set_card_detection(host, true);
181}
182
183static void sdhci_disable_card_detection(struct sdhci_host *host)
184{
185 sdhci_set_card_detection(host, false);
186}
187
188static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
189{
190 if (host->bus_on)
191 return;
192 host->bus_on = true;
193 pm_runtime_get_noresume(mmc_dev(host->mmc));
194}
195
196static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
197{
198 if (!host->bus_on)
199 return;
200 host->bus_on = false;
201 pm_runtime_put_noidle(mmc_dev(host->mmc));
202}
203
204void sdhci_reset(struct sdhci_host *host, u8 mask)
205{
206 ktime_t timeout;
207
208 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
209
210 if (mask & SDHCI_RESET_ALL) {
211 host->clock = 0;
212 /* Reset-all turns off SD Bus Power */
213 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
214 sdhci_runtime_pm_bus_off(host);
215 }
216
217 /* Wait max 100 ms */
218 timeout = ktime_add_ms(ktime_get(), 100);
219
220 /* hw clears the bit when it's done */
221 while (1) {
222 bool timedout = ktime_after(ktime_get(), timeout);
223
224 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
225 break;
226 if (timedout) {
227 pr_err("%s: Reset 0x%x never completed.\n",
228 mmc_hostname(host->mmc), (int)mask);
229 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
230 sdhci_dumpregs(host);
231 return;
232 }
233 udelay(10);
234 }
235}
236EXPORT_SYMBOL_GPL(sdhci_reset);
237
238bool sdhci_do_reset(struct sdhci_host *host, u8 mask)
239{
240 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
241 struct mmc_host *mmc = host->mmc;
242
243 if (!mmc->ops->get_cd(mmc))
244 return false;
245 }
246
247 host->ops->reset(host, mask);
248
249 return true;
250}
251EXPORT_SYMBOL_GPL(sdhci_do_reset);
252
253static void sdhci_reset_for_all(struct sdhci_host *host)
254{
255 if (sdhci_do_reset(host, SDHCI_RESET_ALL)) {
256 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
257 if (host->ops->enable_dma)
258 host->ops->enable_dma(host);
259 }
260 /* Resetting the controller clears many */
261 host->preset_enabled = false;
262 }
263}
264
265enum sdhci_reset_reason {
266 SDHCI_RESET_FOR_INIT,
267 SDHCI_RESET_FOR_REQUEST_ERROR,
268 SDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY,
269 SDHCI_RESET_FOR_TUNING_ABORT,
270 SDHCI_RESET_FOR_CARD_REMOVED,
271 SDHCI_RESET_FOR_CQE_RECOVERY,
272};
273
274static void sdhci_reset_for_reason(struct sdhci_host *host, enum sdhci_reset_reason reason)
275{
276 if (host->quirks2 & SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER) {
277 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
278 return;
279 }
280
281 switch (reason) {
282 case SDHCI_RESET_FOR_INIT:
283 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
284 break;
285 case SDHCI_RESET_FOR_REQUEST_ERROR:
286 case SDHCI_RESET_FOR_TUNING_ABORT:
287 case SDHCI_RESET_FOR_CARD_REMOVED:
288 case SDHCI_RESET_FOR_CQE_RECOVERY:
289 sdhci_do_reset(host, SDHCI_RESET_CMD);
290 sdhci_do_reset(host, SDHCI_RESET_DATA);
291 break;
292 case SDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY:
293 sdhci_do_reset(host, SDHCI_RESET_DATA);
294 break;
295 }
296}
297
298#define sdhci_reset_for(h, r) sdhci_reset_for_reason((h), SDHCI_RESET_FOR_##r)
299
300static void sdhci_set_default_irqs(struct sdhci_host *host)
301{
302 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
303 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
304 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
305 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
306 SDHCI_INT_RESPONSE;
307
308 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
309 host->tuning_mode == SDHCI_TUNING_MODE_3)
310 host->ier |= SDHCI_INT_RETUNE;
311
312 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
313 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
314}
315
316static void sdhci_config_dma(struct sdhci_host *host)
317{
318 u8 ctrl;
319 u16 ctrl2;
320
321 if (host->version < SDHCI_SPEC_200)
322 return;
323
324 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
325
326 /*
327 * Always adjust the DMA selection as some controllers
328 * (e.g. JMicron) can't do PIO properly when the selection
329 * is ADMA.
330 */
331 ctrl &= ~SDHCI_CTRL_DMA_MASK;
332 if (!(host->flags & SDHCI_REQ_USE_DMA))
333 goto out;
334
335 /* Note if DMA Select is zero then SDMA is selected */
336 if (host->flags & SDHCI_USE_ADMA)
337 ctrl |= SDHCI_CTRL_ADMA32;
338
339 if (host->flags & SDHCI_USE_64_BIT_DMA) {
340 /*
341 * If v4 mode, all supported DMA can be 64-bit addressing if
342 * controller supports 64-bit system address, otherwise only
343 * ADMA can support 64-bit addressing.
344 */
345 if (host->v4_mode) {
346 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
347 ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
348 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
349 } else if (host->flags & SDHCI_USE_ADMA) {
350 /*
351 * Don't need to undo SDHCI_CTRL_ADMA32 in order to
352 * set SDHCI_CTRL_ADMA64.
353 */
354 ctrl |= SDHCI_CTRL_ADMA64;
355 }
356 }
357
358out:
359 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
360}
361
362static void sdhci_init(struct sdhci_host *host, int soft)
363{
364 struct mmc_host *mmc = host->mmc;
365 unsigned long flags;
366
367 if (soft)
368 sdhci_reset_for(host, INIT);
369 else
370 sdhci_reset_for_all(host);
371
372 if (host->v4_mode)
373 sdhci_do_enable_v4_mode(host);
374
375 spin_lock_irqsave(&host->lock, flags);
376 sdhci_set_default_irqs(host);
377 spin_unlock_irqrestore(&host->lock, flags);
378
379 host->cqe_on = false;
380
381 if (soft) {
382 /* force clock reconfiguration */
383 host->clock = 0;
384 host->reinit_uhs = true;
385 mmc->ops->set_ios(mmc, &mmc->ios);
386 }
387}
388
389static void sdhci_reinit(struct sdhci_host *host)
390{
391 u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
392
393 sdhci_init(host, 0);
394 sdhci_enable_card_detection(host);
395
396 /*
397 * A change to the card detect bits indicates a change in present state,
398 * refer sdhci_set_card_detection(). A card detect interrupt might have
399 * been missed while the host controller was being reset, so trigger a
400 * rescan to check.
401 */
402 if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT)))
403 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
404}
405
406static void __sdhci_led_activate(struct sdhci_host *host)
407{
408 u8 ctrl;
409
410 if (host->quirks & SDHCI_QUIRK_NO_LED)
411 return;
412
413 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
414 ctrl |= SDHCI_CTRL_LED;
415 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
416}
417
418static void __sdhci_led_deactivate(struct sdhci_host *host)
419{
420 u8 ctrl;
421
422 if (host->quirks & SDHCI_QUIRK_NO_LED)
423 return;
424
425 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
426 ctrl &= ~SDHCI_CTRL_LED;
427 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
428}
429
430#if IS_REACHABLE(CONFIG_LEDS_CLASS)
431static void sdhci_led_control(struct led_classdev *led,
432 enum led_brightness brightness)
433{
434 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
435 unsigned long flags;
436
437 spin_lock_irqsave(&host->lock, flags);
438
439 if (host->runtime_suspended)
440 goto out;
441
442 if (brightness == LED_OFF)
443 __sdhci_led_deactivate(host);
444 else
445 __sdhci_led_activate(host);
446out:
447 spin_unlock_irqrestore(&host->lock, flags);
448}
449
450static int sdhci_led_register(struct sdhci_host *host)
451{
452 struct mmc_host *mmc = host->mmc;
453
454 if (host->quirks & SDHCI_QUIRK_NO_LED)
455 return 0;
456
457 snprintf(host->led_name, sizeof(host->led_name),
458 "%s::", mmc_hostname(mmc));
459
460 host->led.name = host->led_name;
461 host->led.brightness = LED_OFF;
462 host->led.default_trigger = mmc_hostname(mmc);
463 host->led.brightness_set = sdhci_led_control;
464
465 return led_classdev_register(mmc_dev(mmc), &host->led);
466}
467
468static void sdhci_led_unregister(struct sdhci_host *host)
469{
470 if (host->quirks & SDHCI_QUIRK_NO_LED)
471 return;
472
473 led_classdev_unregister(&host->led);
474}
475
476static inline void sdhci_led_activate(struct sdhci_host *host)
477{
478}
479
480static inline void sdhci_led_deactivate(struct sdhci_host *host)
481{
482}
483
484#else
485
486static inline int sdhci_led_register(struct sdhci_host *host)
487{
488 return 0;
489}
490
491static inline void sdhci_led_unregister(struct sdhci_host *host)
492{
493}
494
495static inline void sdhci_led_activate(struct sdhci_host *host)
496{
497 __sdhci_led_activate(host);
498}
499
500static inline void sdhci_led_deactivate(struct sdhci_host *host)
501{
502 __sdhci_led_deactivate(host);
503}
504
505#endif
506
507void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
508 unsigned long timeout)
509{
510 if (sdhci_data_line_cmd(mrq->cmd))
511 mod_timer(&host->data_timer, timeout);
512 else
513 mod_timer(&host->timer, timeout);
514}
515EXPORT_SYMBOL_GPL(sdhci_mod_timer);
516
517static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
518{
519 if (sdhci_data_line_cmd(mrq->cmd))
520 del_timer(&host->data_timer);
521 else
522 del_timer(&host->timer);
523}
524
525static inline bool sdhci_has_requests(struct sdhci_host *host)
526{
527 return host->cmd || host->data_cmd;
528}
529
530/*****************************************************************************\
531 * *
532 * Core functions *
533 * *
534\*****************************************************************************/
535
536static void sdhci_read_block_pio(struct sdhci_host *host)
537{
538 size_t blksize, len, chunk;
539 u32 scratch;
540 u8 *buf;
541
542 DBG("PIO reading\n");
543
544 blksize = host->data->blksz;
545 chunk = 0;
546
547 while (blksize) {
548 BUG_ON(!sg_miter_next(&host->sg_miter));
549
550 len = min(host->sg_miter.length, blksize);
551
552 blksize -= len;
553 host->sg_miter.consumed = len;
554
555 buf = host->sg_miter.addr;
556
557 while (len) {
558 if (chunk == 0) {
559 scratch = sdhci_readl(host, SDHCI_BUFFER);
560 chunk = 4;
561 }
562
563 *buf = scratch & 0xFF;
564
565 buf++;
566 scratch >>= 8;
567 chunk--;
568 len--;
569 }
570 }
571
572 sg_miter_stop(&host->sg_miter);
573}
574
575static void sdhci_write_block_pio(struct sdhci_host *host)
576{
577 size_t blksize, len, chunk;
578 u32 scratch;
579 u8 *buf;
580
581 DBG("PIO writing\n");
582
583 blksize = host->data->blksz;
584 chunk = 0;
585 scratch = 0;
586
587 while (blksize) {
588 BUG_ON(!sg_miter_next(&host->sg_miter));
589
590 len = min(host->sg_miter.length, blksize);
591
592 blksize -= len;
593 host->sg_miter.consumed = len;
594
595 buf = host->sg_miter.addr;
596
597 while (len) {
598 scratch |= (u32)*buf << (chunk * 8);
599
600 buf++;
601 chunk++;
602 len--;
603
604 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
605 sdhci_writel(host, scratch, SDHCI_BUFFER);
606 chunk = 0;
607 scratch = 0;
608 }
609 }
610 }
611
612 sg_miter_stop(&host->sg_miter);
613}
614
615static void sdhci_transfer_pio(struct sdhci_host *host)
616{
617 u32 mask;
618
619 if (host->blocks == 0)
620 return;
621
622 if (host->data->flags & MMC_DATA_READ)
623 mask = SDHCI_DATA_AVAILABLE;
624 else
625 mask = SDHCI_SPACE_AVAILABLE;
626
627 /*
628 * Some controllers (JMicron JMB38x) mess up the buffer bits
629 * for transfers < 4 bytes. As long as it is just one block,
630 * we can ignore the bits.
631 */
632 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
633 (host->data->blocks == 1))
634 mask = ~0;
635
636 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
637 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
638 udelay(100);
639
640 if (host->data->flags & MMC_DATA_READ)
641 sdhci_read_block_pio(host);
642 else
643 sdhci_write_block_pio(host);
644
645 host->blocks--;
646 if (host->blocks == 0)
647 break;
648 }
649
650 DBG("PIO transfer complete.\n");
651}
652
653static int sdhci_pre_dma_transfer(struct sdhci_host *host,
654 struct mmc_data *data, int cookie)
655{
656 int sg_count;
657
658 /*
659 * If the data buffers are already mapped, return the previous
660 * dma_map_sg() result.
661 */
662 if (data->host_cookie == COOKIE_PRE_MAPPED)
663 return data->sg_count;
664
665 /* Bounce write requests to the bounce buffer */
666 if (host->bounce_buffer) {
667 unsigned int length = data->blksz * data->blocks;
668
669 if (length > host->bounce_buffer_size) {
670 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
671 mmc_hostname(host->mmc), length,
672 host->bounce_buffer_size);
673 return -EIO;
674 }
675 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
676 /* Copy the data to the bounce buffer */
677 if (host->ops->copy_to_bounce_buffer) {
678 host->ops->copy_to_bounce_buffer(host,
679 data, length);
680 } else {
681 sg_copy_to_buffer(data->sg, data->sg_len,
682 host->bounce_buffer, length);
683 }
684 }
685 /* Switch ownership to the DMA */
686 dma_sync_single_for_device(mmc_dev(host->mmc),
687 host->bounce_addr,
688 host->bounce_buffer_size,
689 mmc_get_dma_dir(data));
690 /* Just a dummy value */
691 sg_count = 1;
692 } else {
693 /* Just access the data directly from memory */
694 sg_count = dma_map_sg(mmc_dev(host->mmc),
695 data->sg, data->sg_len,
696 mmc_get_dma_dir(data));
697 }
698
699 if (sg_count == 0)
700 return -ENOSPC;
701
702 data->sg_count = sg_count;
703 data->host_cookie = cookie;
704
705 return sg_count;
706}
707
708static char *sdhci_kmap_atomic(struct scatterlist *sg)
709{
710 return kmap_local_page(sg_page(sg)) + sg->offset;
711}
712
713static void sdhci_kunmap_atomic(void *buffer)
714{
715 kunmap_local(buffer);
716}
717
718void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
719 dma_addr_t addr, int len, unsigned int cmd)
720{
721 struct sdhci_adma2_64_desc *dma_desc = *desc;
722
723 /* 32-bit and 64-bit descriptors have these members in same position */
724 dma_desc->cmd = cpu_to_le16(cmd);
725 dma_desc->len = cpu_to_le16(len);
726 dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr));
727
728 if (host->flags & SDHCI_USE_64_BIT_DMA)
729 dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr));
730
731 *desc += host->desc_sz;
732}
733EXPORT_SYMBOL_GPL(sdhci_adma_write_desc);
734
735static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
736 void **desc, dma_addr_t addr,
737 int len, unsigned int cmd)
738{
739 if (host->ops->adma_write_desc)
740 host->ops->adma_write_desc(host, desc, addr, len, cmd);
741 else
742 sdhci_adma_write_desc(host, desc, addr, len, cmd);
743}
744
745static void sdhci_adma_mark_end(void *desc)
746{
747 struct sdhci_adma2_64_desc *dma_desc = desc;
748
749 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
750 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
751}
752
753static void sdhci_adma_table_pre(struct sdhci_host *host,
754 struct mmc_data *data, int sg_count)
755{
756 struct scatterlist *sg;
757 dma_addr_t addr, align_addr;
758 void *desc, *align;
759 char *buffer;
760 int len, offset, i;
761
762 /*
763 * The spec does not specify endianness of descriptor table.
764 * We currently guess that it is LE.
765 */
766
767 host->sg_count = sg_count;
768
769 desc = host->adma_table;
770 align = host->align_buffer;
771
772 align_addr = host->align_addr;
773
774 for_each_sg(data->sg, sg, host->sg_count, i) {
775 addr = sg_dma_address(sg);
776 len = sg_dma_len(sg);
777
778 /*
779 * The SDHCI specification states that ADMA addresses must
780 * be 32-bit aligned. If they aren't, then we use a bounce
781 * buffer for the (up to three) bytes that screw up the
782 * alignment.
783 */
784 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
785 SDHCI_ADMA2_MASK;
786 if (offset) {
787 if (data->flags & MMC_DATA_WRITE) {
788 buffer = sdhci_kmap_atomic(sg);
789 memcpy(align, buffer, offset);
790 sdhci_kunmap_atomic(buffer);
791 }
792
793 /* tran, valid */
794 __sdhci_adma_write_desc(host, &desc, align_addr,
795 offset, ADMA2_TRAN_VALID);
796
797 BUG_ON(offset > 65536);
798
799 align += SDHCI_ADMA2_ALIGN;
800 align_addr += SDHCI_ADMA2_ALIGN;
801
802 addr += offset;
803 len -= offset;
804 }
805
806 /*
807 * The block layer forces a minimum segment size of PAGE_SIZE,
808 * so 'len' can be too big here if PAGE_SIZE >= 64KiB. Write
809 * multiple descriptors, noting that the ADMA table is sized
810 * for 4KiB chunks anyway, so it will be big enough.
811 */
812 while (len > host->max_adma) {
813 int n = 32 * 1024; /* 32KiB*/
814
815 __sdhci_adma_write_desc(host, &desc, addr, n, ADMA2_TRAN_VALID);
816 addr += n;
817 len -= n;
818 }
819
820 /* tran, valid */
821 if (len)
822 __sdhci_adma_write_desc(host, &desc, addr, len,
823 ADMA2_TRAN_VALID);
824
825 /*
826 * If this triggers then we have a calculation bug
827 * somewhere. :/
828 */
829 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
830 }
831
832 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
833 /* Mark the last descriptor as the terminating descriptor */
834 if (desc != host->adma_table) {
835 desc -= host->desc_sz;
836 sdhci_adma_mark_end(desc);
837 }
838 } else {
839 /* Add a terminating entry - nop, end, valid */
840 __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
841 }
842}
843
844static void sdhci_adma_table_post(struct sdhci_host *host,
845 struct mmc_data *data)
846{
847 struct scatterlist *sg;
848 int i, size;
849 void *align;
850 char *buffer;
851
852 if (data->flags & MMC_DATA_READ) {
853 bool has_unaligned = false;
854
855 /* Do a quick scan of the SG list for any unaligned mappings */
856 for_each_sg(data->sg, sg, host->sg_count, i)
857 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
858 has_unaligned = true;
859 break;
860 }
861
862 if (has_unaligned) {
863 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
864 data->sg_len, DMA_FROM_DEVICE);
865
866 align = host->align_buffer;
867
868 for_each_sg(data->sg, sg, host->sg_count, i) {
869 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
870 size = SDHCI_ADMA2_ALIGN -
871 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
872
873 buffer = sdhci_kmap_atomic(sg);
874 memcpy(buffer, align, size);
875 sdhci_kunmap_atomic(buffer);
876
877 align += SDHCI_ADMA2_ALIGN;
878 }
879 }
880 }
881 }
882}
883
884static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
885{
886 sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
887 if (host->flags & SDHCI_USE_64_BIT_DMA)
888 sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
889}
890
891static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
892{
893 if (host->bounce_buffer)
894 return host->bounce_addr;
895 else
896 return sg_dma_address(host->data->sg);
897}
898
899static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
900{
901 if (host->v4_mode)
902 sdhci_set_adma_addr(host, addr);
903 else
904 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
905}
906
907static unsigned int sdhci_target_timeout(struct sdhci_host *host,
908 struct mmc_command *cmd,
909 struct mmc_data *data)
910{
911 unsigned int target_timeout;
912
913 /* timeout in us */
914 if (!data) {
915 target_timeout = cmd->busy_timeout * 1000;
916 } else {
917 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
918 if (host->clock && data->timeout_clks) {
919 unsigned long long val;
920
921 /*
922 * data->timeout_clks is in units of clock cycles.
923 * host->clock is in Hz. target_timeout is in us.
924 * Hence, us = 1000000 * cycles / Hz. Round up.
925 */
926 val = 1000000ULL * data->timeout_clks;
927 if (do_div(val, host->clock))
928 target_timeout++;
929 target_timeout += val;
930 }
931 }
932
933 return target_timeout;
934}
935
936static void sdhci_calc_sw_timeout(struct sdhci_host *host,
937 struct mmc_command *cmd)
938{
939 struct mmc_data *data = cmd->data;
940 struct mmc_host *mmc = host->mmc;
941 struct mmc_ios *ios = &mmc->ios;
942 unsigned char bus_width = 1 << ios->bus_width;
943 unsigned int blksz;
944 unsigned int freq;
945 u64 target_timeout;
946 u64 transfer_time;
947
948 target_timeout = sdhci_target_timeout(host, cmd, data);
949 target_timeout *= NSEC_PER_USEC;
950
951 if (data) {
952 blksz = data->blksz;
953 freq = mmc->actual_clock ? : host->clock;
954 transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
955 do_div(transfer_time, freq);
956 /* multiply by '2' to account for any unknowns */
957 transfer_time = transfer_time * 2;
958 /* calculate timeout for the entire data */
959 host->data_timeout = data->blocks * target_timeout +
960 transfer_time;
961 } else {
962 host->data_timeout = target_timeout;
963 }
964
965 if (host->data_timeout)
966 host->data_timeout += MMC_CMD_TRANSFER_TIME;
967}
968
969static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
970 bool *too_big)
971{
972 u8 count;
973 struct mmc_data *data;
974 unsigned target_timeout, current_timeout;
975
976 *too_big = false;
977
978 /*
979 * If the host controller provides us with an incorrect timeout
980 * value, just skip the check and use the maximum. The hardware may take
981 * longer to time out, but that's much better than having a too-short
982 * timeout value.
983 */
984 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
985 return host->max_timeout_count;
986
987 /* Unspecified command, assume max */
988 if (cmd == NULL)
989 return host->max_timeout_count;
990
991 data = cmd->data;
992 /* Unspecified timeout, assume max */
993 if (!data && !cmd->busy_timeout)
994 return host->max_timeout_count;
995
996 /* timeout in us */
997 target_timeout = sdhci_target_timeout(host, cmd, data);
998
999 /*
1000 * Figure out needed cycles.
1001 * We do this in steps in order to fit inside a 32 bit int.
1002 * The first step is the minimum timeout, which will have a
1003 * minimum resolution of 6 bits:
1004 * (1) 2^13*1000 > 2^22,
1005 * (2) host->timeout_clk < 2^16
1006 * =>
1007 * (1) / (2) > 2^6
1008 */
1009 count = 0;
1010 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
1011 while (current_timeout < target_timeout) {
1012 count++;
1013 current_timeout <<= 1;
1014 if (count > host->max_timeout_count) {
1015 if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
1016 DBG("Too large timeout 0x%x requested for CMD%d!\n",
1017 count, cmd->opcode);
1018 count = host->max_timeout_count;
1019 *too_big = true;
1020 break;
1021 }
1022 }
1023
1024 return count;
1025}
1026
1027static void sdhci_set_transfer_irqs(struct sdhci_host *host)
1028{
1029 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
1030 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
1031
1032 if (host->flags & SDHCI_REQ_USE_DMA)
1033 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
1034 else
1035 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
1036
1037 if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
1038 host->ier |= SDHCI_INT_AUTO_CMD_ERR;
1039 else
1040 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
1041
1042 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1043 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1044}
1045
1046void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
1047{
1048 if (enable)
1049 host->ier |= SDHCI_INT_DATA_TIMEOUT;
1050 else
1051 host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
1052 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1053 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1054}
1055EXPORT_SYMBOL_GPL(sdhci_set_data_timeout_irq);
1056
1057void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1058{
1059 bool too_big = false;
1060 u8 count = sdhci_calc_timeout(host, cmd, &too_big);
1061
1062 if (too_big &&
1063 host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
1064 sdhci_calc_sw_timeout(host, cmd);
1065 sdhci_set_data_timeout_irq(host, false);
1066 } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
1067 sdhci_set_data_timeout_irq(host, true);
1068 }
1069
1070 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
1071}
1072EXPORT_SYMBOL_GPL(__sdhci_set_timeout);
1073
1074static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1075{
1076 if (host->ops->set_timeout)
1077 host->ops->set_timeout(host, cmd);
1078 else
1079 __sdhci_set_timeout(host, cmd);
1080}
1081
1082void sdhci_initialize_data(struct sdhci_host *host, struct mmc_data *data)
1083{
1084 WARN_ON(host->data);
1085
1086 /* Sanity checks */
1087 BUG_ON(data->blksz * data->blocks > 524288);
1088 BUG_ON(data->blksz > host->mmc->max_blk_size);
1089 BUG_ON(data->blocks > 65535);
1090
1091 host->data = data;
1092 host->data_early = 0;
1093 host->data->bytes_xfered = 0;
1094}
1095EXPORT_SYMBOL_GPL(sdhci_initialize_data);
1096
1097static inline void sdhci_set_block_info(struct sdhci_host *host,
1098 struct mmc_data *data)
1099{
1100 /* Set the DMA boundary value and block size */
1101 sdhci_writew(host,
1102 SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
1103 SDHCI_BLOCK_SIZE);
1104 /*
1105 * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
1106 * can be supported, in that case 16-bit block count register must be 0.
1107 */
1108 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1109 (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
1110 if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
1111 sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
1112 sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
1113 } else {
1114 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1115 }
1116}
1117
1118void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data)
1119{
1120 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1121 struct scatterlist *sg;
1122 unsigned int length_mask, offset_mask;
1123 int i;
1124
1125 host->flags |= SDHCI_REQ_USE_DMA;
1126
1127 /*
1128 * FIXME: This doesn't account for merging when mapping the
1129 * scatterlist.
1130 *
1131 * The assumption here being that alignment and lengths are
1132 * the same after DMA mapping to device address space.
1133 */
1134 length_mask = 0;
1135 offset_mask = 0;
1136 if (host->flags & SDHCI_USE_ADMA) {
1137 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
1138 length_mask = 3;
1139 /*
1140 * As we use up to 3 byte chunks to work
1141 * around alignment problems, we need to
1142 * check the offset as well.
1143 */
1144 offset_mask = 3;
1145 }
1146 } else {
1147 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
1148 length_mask = 3;
1149 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
1150 offset_mask = 3;
1151 }
1152
1153 if (unlikely(length_mask | offset_mask)) {
1154 for_each_sg(data->sg, sg, data->sg_len, i) {
1155 if (sg->length & length_mask) {
1156 DBG("Reverting to PIO because of transfer size (%d)\n",
1157 sg->length);
1158 host->flags &= ~SDHCI_REQ_USE_DMA;
1159 break;
1160 }
1161 if (sg->offset & offset_mask) {
1162 DBG("Reverting to PIO because of bad alignment\n");
1163 host->flags &= ~SDHCI_REQ_USE_DMA;
1164 break;
1165 }
1166 }
1167 }
1168 }
1169
1170 sdhci_config_dma(host);
1171
1172 if (host->flags & SDHCI_REQ_USE_DMA) {
1173 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1174
1175 if (sg_cnt <= 0) {
1176 /*
1177 * This only happens when someone fed
1178 * us an invalid request.
1179 */
1180 WARN_ON(1);
1181 host->flags &= ~SDHCI_REQ_USE_DMA;
1182 } else if (host->flags & SDHCI_USE_ADMA) {
1183 sdhci_adma_table_pre(host, data, sg_cnt);
1184 sdhci_set_adma_addr(host, host->adma_addr);
1185 } else {
1186 WARN_ON(sg_cnt != 1);
1187 sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
1188 }
1189 }
1190
1191 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
1192 int flags;
1193
1194 flags = SG_MITER_ATOMIC;
1195 if (host->data->flags & MMC_DATA_READ)
1196 flags |= SG_MITER_TO_SG;
1197 else
1198 flags |= SG_MITER_FROM_SG;
1199 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1200 host->blocks = data->blocks;
1201 }
1202
1203 sdhci_set_transfer_irqs(host);
1204}
1205EXPORT_SYMBOL_GPL(sdhci_prepare_dma);
1206
1207static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
1208{
1209 struct mmc_data *data = cmd->data;
1210
1211 sdhci_initialize_data(host, data);
1212
1213 sdhci_prepare_dma(host, data);
1214
1215 sdhci_set_block_info(host, data);
1216}
1217
1218#if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
1219
1220static int sdhci_external_dma_init(struct sdhci_host *host)
1221{
1222 int ret = 0;
1223 struct mmc_host *mmc = host->mmc;
1224
1225 host->tx_chan = dma_request_chan(mmc_dev(mmc), "tx");
1226 if (IS_ERR(host->tx_chan)) {
1227 ret = PTR_ERR(host->tx_chan);
1228 if (ret != -EPROBE_DEFER)
1229 pr_warn("Failed to request TX DMA channel.\n");
1230 host->tx_chan = NULL;
1231 return ret;
1232 }
1233
1234 host->rx_chan = dma_request_chan(mmc_dev(mmc), "rx");
1235 if (IS_ERR(host->rx_chan)) {
1236 if (host->tx_chan) {
1237 dma_release_channel(host->tx_chan);
1238 host->tx_chan = NULL;
1239 }
1240
1241 ret = PTR_ERR(host->rx_chan);
1242 if (ret != -EPROBE_DEFER)
1243 pr_warn("Failed to request RX DMA channel.\n");
1244 host->rx_chan = NULL;
1245 }
1246
1247 return ret;
1248}
1249
1250static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1251 struct mmc_data *data)
1252{
1253 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
1254}
1255
1256static int sdhci_external_dma_setup(struct sdhci_host *host,
1257 struct mmc_command *cmd)
1258{
1259 int ret, i;
1260 enum dma_transfer_direction dir;
1261 struct dma_async_tx_descriptor *desc;
1262 struct mmc_data *data = cmd->data;
1263 struct dma_chan *chan;
1264 struct dma_slave_config cfg;
1265 dma_cookie_t cookie;
1266 int sg_cnt;
1267
1268 if (!host->mapbase)
1269 return -EINVAL;
1270
1271 memset(&cfg, 0, sizeof(cfg));
1272 cfg.src_addr = host->mapbase + SDHCI_BUFFER;
1273 cfg.dst_addr = host->mapbase + SDHCI_BUFFER;
1274 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1275 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1276 cfg.src_maxburst = data->blksz / 4;
1277 cfg.dst_maxburst = data->blksz / 4;
1278
1279 /* Sanity check: all the SG entries must be aligned by block size. */
1280 for (i = 0; i < data->sg_len; i++) {
1281 if ((data->sg + i)->length % data->blksz)
1282 return -EINVAL;
1283 }
1284
1285 chan = sdhci_external_dma_channel(host, data);
1286
1287 ret = dmaengine_slave_config(chan, &cfg);
1288 if (ret)
1289 return ret;
1290
1291 sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1292 if (sg_cnt <= 0)
1293 return -EINVAL;
1294
1295 dir = data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
1296 desc = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, dir,
1297 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1298 if (!desc)
1299 return -EINVAL;
1300
1301 desc->callback = NULL;
1302 desc->callback_param = NULL;
1303
1304 cookie = dmaengine_submit(desc);
1305 if (dma_submit_error(cookie))
1306 ret = cookie;
1307
1308 return ret;
1309}
1310
1311static void sdhci_external_dma_release(struct sdhci_host *host)
1312{
1313 if (host->tx_chan) {
1314 dma_release_channel(host->tx_chan);
1315 host->tx_chan = NULL;
1316 }
1317
1318 if (host->rx_chan) {
1319 dma_release_channel(host->rx_chan);
1320 host->rx_chan = NULL;
1321 }
1322
1323 sdhci_switch_external_dma(host, false);
1324}
1325
1326static void __sdhci_external_dma_prepare_data(struct sdhci_host *host,
1327 struct mmc_command *cmd)
1328{
1329 struct mmc_data *data = cmd->data;
1330
1331 sdhci_initialize_data(host, data);
1332
1333 host->flags |= SDHCI_REQ_USE_DMA;
1334 sdhci_set_transfer_irqs(host);
1335
1336 sdhci_set_block_info(host, data);
1337}
1338
1339static void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1340 struct mmc_command *cmd)
1341{
1342 if (!sdhci_external_dma_setup(host, cmd)) {
1343 __sdhci_external_dma_prepare_data(host, cmd);
1344 } else {
1345 sdhci_external_dma_release(host);
1346 pr_err("%s: Cannot use external DMA, switch to the DMA/PIO which standard SDHCI provides.\n",
1347 mmc_hostname(host->mmc));
1348 sdhci_prepare_data(host, cmd);
1349 }
1350}
1351
1352static void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1353 struct mmc_command *cmd)
1354{
1355 struct dma_chan *chan;
1356
1357 if (!cmd->data)
1358 return;
1359
1360 chan = sdhci_external_dma_channel(host, cmd->data);
1361 if (chan)
1362 dma_async_issue_pending(chan);
1363}
1364
1365#else
1366
1367static inline int sdhci_external_dma_init(struct sdhci_host *host)
1368{
1369 return -EOPNOTSUPP;
1370}
1371
1372static inline void sdhci_external_dma_release(struct sdhci_host *host)
1373{
1374}
1375
1376static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1377 struct mmc_command *cmd)
1378{
1379 /* This should never happen */
1380 WARN_ON_ONCE(1);
1381}
1382
1383static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1384 struct mmc_command *cmd)
1385{
1386}
1387
1388static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1389 struct mmc_data *data)
1390{
1391 return NULL;
1392}
1393
1394#endif
1395
1396void sdhci_switch_external_dma(struct sdhci_host *host, bool en)
1397{
1398 host->use_external_dma = en;
1399}
1400EXPORT_SYMBOL_GPL(sdhci_switch_external_dma);
1401
1402static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
1403 struct mmc_request *mrq)
1404{
1405 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
1406 !mrq->cap_cmd_during_tfr;
1407}
1408
1409static inline bool sdhci_auto_cmd23(struct sdhci_host *host,
1410 struct mmc_request *mrq)
1411{
1412 return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
1413}
1414
1415static inline bool sdhci_manual_cmd23(struct sdhci_host *host,
1416 struct mmc_request *mrq)
1417{
1418 return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23);
1419}
1420
1421static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
1422 struct mmc_command *cmd,
1423 u16 *mode)
1424{
1425 bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
1426 (cmd->opcode != SD_IO_RW_EXTENDED);
1427 bool use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq);
1428 u16 ctrl2;
1429
1430 /*
1431 * In case of Version 4.10 or later, use of 'Auto CMD Auto
1432 * Select' is recommended rather than use of 'Auto CMD12
1433 * Enable' or 'Auto CMD23 Enable'. We require Version 4 Mode
1434 * here because some controllers (e.g sdhci-of-dwmshc) expect it.
1435 */
1436 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1437 (use_cmd12 || use_cmd23)) {
1438 *mode |= SDHCI_TRNS_AUTO_SEL;
1439
1440 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1441 if (use_cmd23)
1442 ctrl2 |= SDHCI_CMD23_ENABLE;
1443 else
1444 ctrl2 &= ~SDHCI_CMD23_ENABLE;
1445 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
1446
1447 return;
1448 }
1449
1450 /*
1451 * If we are sending CMD23, CMD12 never gets sent
1452 * on successful completion (so no Auto-CMD12).
1453 */
1454 if (use_cmd12)
1455 *mode |= SDHCI_TRNS_AUTO_CMD12;
1456 else if (use_cmd23)
1457 *mode |= SDHCI_TRNS_AUTO_CMD23;
1458}
1459
1460static void sdhci_set_transfer_mode(struct sdhci_host *host,
1461 struct mmc_command *cmd)
1462{
1463 u16 mode = 0;
1464 struct mmc_data *data = cmd->data;
1465
1466 if (data == NULL) {
1467 if (host->quirks2 &
1468 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
1469 /* must not clear SDHCI_TRANSFER_MODE when tuning */
1470 if (!mmc_op_tuning(cmd->opcode))
1471 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1472 } else {
1473 /* clear Auto CMD settings for no data CMDs */
1474 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1475 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
1476 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
1477 }
1478 return;
1479 }
1480
1481 WARN_ON(!host->data);
1482
1483 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1484 mode = SDHCI_TRNS_BLK_CNT_EN;
1485
1486 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
1487 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
1488 sdhci_auto_cmd_select(host, cmd, &mode);
1489 if (sdhci_auto_cmd23(host, cmd->mrq))
1490 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
1491 }
1492
1493 if (data->flags & MMC_DATA_READ)
1494 mode |= SDHCI_TRNS_READ;
1495 if (host->flags & SDHCI_REQ_USE_DMA)
1496 mode |= SDHCI_TRNS_DMA;
1497
1498 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1499}
1500
1501bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
1502{
1503 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1504 ((mrq->cmd && mrq->cmd->error) ||
1505 (mrq->sbc && mrq->sbc->error) ||
1506 (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
1507 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1508}
1509EXPORT_SYMBOL_GPL(sdhci_needs_reset);
1510
1511static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq)
1512{
1513 int i;
1514
1515 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1516 if (host->mrqs_done[i] == mrq) {
1517 WARN_ON(1);
1518 return;
1519 }
1520 }
1521
1522 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1523 if (!host->mrqs_done[i]) {
1524 host->mrqs_done[i] = mrq;
1525 break;
1526 }
1527 }
1528
1529 WARN_ON(i >= SDHCI_MAX_MRQS);
1530}
1531
1532void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1533{
1534 if (host->cmd && host->cmd->mrq == mrq)
1535 host->cmd = NULL;
1536
1537 if (host->data_cmd && host->data_cmd->mrq == mrq)
1538 host->data_cmd = NULL;
1539
1540 if (host->deferred_cmd && host->deferred_cmd->mrq == mrq)
1541 host->deferred_cmd = NULL;
1542
1543 if (host->data && host->data->mrq == mrq)
1544 host->data = NULL;
1545
1546 if (sdhci_needs_reset(host, mrq))
1547 host->pending_reset = true;
1548
1549 sdhci_set_mrq_done(host, mrq);
1550
1551 sdhci_del_timer(host, mrq);
1552
1553 if (!sdhci_has_requests(host))
1554 sdhci_led_deactivate(host);
1555}
1556EXPORT_SYMBOL_GPL(__sdhci_finish_mrq);
1557
1558void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1559{
1560 __sdhci_finish_mrq(host, mrq);
1561
1562 queue_work(host->complete_wq, &host->complete_work);
1563}
1564EXPORT_SYMBOL_GPL(sdhci_finish_mrq);
1565
1566void __sdhci_finish_data_common(struct sdhci_host *host, bool defer_reset)
1567{
1568 struct mmc_command *data_cmd = host->data_cmd;
1569 struct mmc_data *data = host->data;
1570
1571 host->data = NULL;
1572 host->data_cmd = NULL;
1573
1574 /*
1575 * The controller needs a reset of internal state machines upon error
1576 * conditions.
1577 */
1578 if (data->error) {
1579 if (defer_reset)
1580 host->pending_reset = true;
1581 else if (!host->cmd || host->cmd == data_cmd)
1582 sdhci_reset_for(host, REQUEST_ERROR);
1583 else
1584 sdhci_reset_for(host, REQUEST_ERROR_DATA_ONLY);
1585 }
1586
1587 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1588 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1589 sdhci_adma_table_post(host, data);
1590
1591 /*
1592 * The specification states that the block count register must
1593 * be updated, but it does not specify at what point in the
1594 * data flow. That makes the register entirely useless to read
1595 * back so we have to assume that nothing made it to the card
1596 * in the event of an error.
1597 */
1598 if (data->error)
1599 data->bytes_xfered = 0;
1600 else
1601 data->bytes_xfered = data->blksz * data->blocks;
1602}
1603EXPORT_SYMBOL_GPL(__sdhci_finish_data_common);
1604
1605static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout)
1606{
1607 struct mmc_data *data = host->data;
1608
1609 __sdhci_finish_data_common(host, false);
1610
1611 /*
1612 * Need to send CMD12 if -
1613 * a) open-ended multiblock transfer not using auto CMD12 (no CMD23)
1614 * b) error in multiblock transfer
1615 */
1616 if (data->stop &&
1617 ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) ||
1618 data->error)) {
1619 /*
1620 * 'cap_cmd_during_tfr' request must not use the command line
1621 * after mmc_command_done() has been called. It is upper layer's
1622 * responsibility to send the stop command if required.
1623 */
1624 if (data->mrq->cap_cmd_during_tfr) {
1625 __sdhci_finish_mrq(host, data->mrq);
1626 } else {
1627 /* Avoid triggering warning in sdhci_send_command() */
1628 host->cmd = NULL;
1629 if (!sdhci_send_command(host, data->stop)) {
1630 if (sw_data_timeout) {
1631 /*
1632 * This is anyway a sw data timeout, so
1633 * give up now.
1634 */
1635 data->stop->error = -EIO;
1636 __sdhci_finish_mrq(host, data->mrq);
1637 } else {
1638 WARN_ON(host->deferred_cmd);
1639 host->deferred_cmd = data->stop;
1640 }
1641 }
1642 }
1643 } else {
1644 __sdhci_finish_mrq(host, data->mrq);
1645 }
1646}
1647
1648static void sdhci_finish_data(struct sdhci_host *host)
1649{
1650 __sdhci_finish_data(host, false);
1651}
1652
1653static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1654{
1655 int flags;
1656 u32 mask;
1657 unsigned long timeout;
1658
1659 WARN_ON(host->cmd);
1660
1661 /* Initially, a command has no error */
1662 cmd->error = 0;
1663
1664 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1665 cmd->opcode == MMC_STOP_TRANSMISSION)
1666 cmd->flags |= MMC_RSP_BUSY;
1667
1668 mask = SDHCI_CMD_INHIBIT;
1669 if (sdhci_data_line_cmd(cmd))
1670 mask |= SDHCI_DATA_INHIBIT;
1671
1672 /* We shouldn't wait for data inihibit for stop commands, even
1673 though they might use busy signaling */
1674 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1675 mask &= ~SDHCI_DATA_INHIBIT;
1676
1677 if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)
1678 return false;
1679
1680 host->cmd = cmd;
1681 host->data_timeout = 0;
1682 if (sdhci_data_line_cmd(cmd)) {
1683 WARN_ON(host->data_cmd);
1684 host->data_cmd = cmd;
1685 sdhci_set_timeout(host, cmd);
1686 }
1687
1688 if (cmd->data) {
1689 if (host->use_external_dma)
1690 sdhci_external_dma_prepare_data(host, cmd);
1691 else
1692 sdhci_prepare_data(host, cmd);
1693 }
1694
1695 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1696
1697 sdhci_set_transfer_mode(host, cmd);
1698
1699 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1700 WARN_ONCE(1, "Unsupported response type!\n");
1701 /*
1702 * This does not happen in practice because 136-bit response
1703 * commands never have busy waiting, so rather than complicate
1704 * the error path, just remove busy waiting and continue.
1705 */
1706 cmd->flags &= ~MMC_RSP_BUSY;
1707 }
1708
1709 if (!(cmd->flags & MMC_RSP_PRESENT))
1710 flags = SDHCI_CMD_RESP_NONE;
1711 else if (cmd->flags & MMC_RSP_136)
1712 flags = SDHCI_CMD_RESP_LONG;
1713 else if (cmd->flags & MMC_RSP_BUSY)
1714 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1715 else
1716 flags = SDHCI_CMD_RESP_SHORT;
1717
1718 if (cmd->flags & MMC_RSP_CRC)
1719 flags |= SDHCI_CMD_CRC;
1720 if (cmd->flags & MMC_RSP_OPCODE)
1721 flags |= SDHCI_CMD_INDEX;
1722
1723 /* CMD19 is special in that the Data Present Select should be set */
1724 if (cmd->data || mmc_op_tuning(cmd->opcode))
1725 flags |= SDHCI_CMD_DATA;
1726
1727 timeout = jiffies;
1728 if (host->data_timeout)
1729 timeout += nsecs_to_jiffies(host->data_timeout);
1730 else if (!cmd->data && cmd->busy_timeout > 9000)
1731 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1732 else
1733 timeout += 10 * HZ;
1734 sdhci_mod_timer(host, cmd->mrq, timeout);
1735
1736 if (host->use_external_dma)
1737 sdhci_external_dma_pre_transfer(host, cmd);
1738
1739 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1740
1741 return true;
1742}
1743
1744bool sdhci_present_error(struct sdhci_host *host,
1745 struct mmc_command *cmd, bool present)
1746{
1747 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1748 cmd->error = -ENOMEDIUM;
1749 return true;
1750 }
1751
1752 return false;
1753}
1754EXPORT_SYMBOL_GPL(sdhci_present_error);
1755
1756static bool sdhci_send_command_retry(struct sdhci_host *host,
1757 struct mmc_command *cmd,
1758 unsigned long flags)
1759 __releases(host->lock)
1760 __acquires(host->lock)
1761{
1762 struct mmc_command *deferred_cmd = host->deferred_cmd;
1763 int timeout = 10; /* Approx. 10 ms */
1764 bool present;
1765
1766 while (!sdhci_send_command(host, cmd)) {
1767 if (!timeout--) {
1768 pr_err("%s: Controller never released inhibit bit(s).\n",
1769 mmc_hostname(host->mmc));
1770 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
1771 sdhci_dumpregs(host);
1772 cmd->error = -EIO;
1773 return false;
1774 }
1775
1776 spin_unlock_irqrestore(&host->lock, flags);
1777
1778 usleep_range(1000, 1250);
1779
1780 present = host->mmc->ops->get_cd(host->mmc);
1781
1782 spin_lock_irqsave(&host->lock, flags);
1783
1784 /* A deferred command might disappear, handle that */
1785 if (cmd == deferred_cmd && cmd != host->deferred_cmd)
1786 return true;
1787
1788 if (sdhci_present_error(host, cmd, present))
1789 return false;
1790 }
1791
1792 if (cmd == host->deferred_cmd)
1793 host->deferred_cmd = NULL;
1794
1795 return true;
1796}
1797
1798static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1799{
1800 int i, reg;
1801
1802 for (i = 0; i < 4; i++) {
1803 reg = SDHCI_RESPONSE + (3 - i) * 4;
1804 cmd->resp[i] = sdhci_readl(host, reg);
1805 }
1806
1807 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1808 return;
1809
1810 /* CRC is stripped so we need to do some shifting */
1811 for (i = 0; i < 4; i++) {
1812 cmd->resp[i] <<= 8;
1813 if (i != 3)
1814 cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1815 }
1816}
1817
1818static void sdhci_finish_command(struct sdhci_host *host)
1819{
1820 struct mmc_command *cmd = host->cmd;
1821
1822 host->cmd = NULL;
1823
1824 if (cmd->flags & MMC_RSP_PRESENT) {
1825 if (cmd->flags & MMC_RSP_136) {
1826 sdhci_read_rsp_136(host, cmd);
1827 } else {
1828 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1829 }
1830 }
1831
1832 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1833 mmc_command_done(host->mmc, cmd->mrq);
1834
1835 /*
1836 * The host can send and interrupt when the busy state has
1837 * ended, allowing us to wait without wasting CPU cycles.
1838 * The busy signal uses DAT0 so this is similar to waiting
1839 * for data to complete.
1840 *
1841 * Note: The 1.0 specification is a bit ambiguous about this
1842 * feature so there might be some problems with older
1843 * controllers.
1844 */
1845 if (cmd->flags & MMC_RSP_BUSY) {
1846 if (cmd->data) {
1847 DBG("Cannot wait for busy signal when also doing a data transfer");
1848 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1849 cmd == host->data_cmd) {
1850 /* Command complete before busy is ended */
1851 return;
1852 }
1853 }
1854
1855 /* Finished CMD23, now send actual command. */
1856 if (cmd == cmd->mrq->sbc) {
1857 if (!sdhci_send_command(host, cmd->mrq->cmd)) {
1858 WARN_ON(host->deferred_cmd);
1859 host->deferred_cmd = cmd->mrq->cmd;
1860 }
1861 } else {
1862
1863 /* Processed actual command. */
1864 if (host->data && host->data_early)
1865 sdhci_finish_data(host);
1866
1867 if (!cmd->data)
1868 __sdhci_finish_mrq(host, cmd->mrq);
1869 }
1870}
1871
1872static u16 sdhci_get_preset_value(struct sdhci_host *host)
1873{
1874 u16 preset = 0;
1875
1876 switch (host->timing) {
1877 case MMC_TIMING_MMC_HS:
1878 case MMC_TIMING_SD_HS:
1879 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HIGH_SPEED);
1880 break;
1881 case MMC_TIMING_UHS_SDR12:
1882 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1883 break;
1884 case MMC_TIMING_UHS_SDR25:
1885 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1886 break;
1887 case MMC_TIMING_UHS_SDR50:
1888 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1889 break;
1890 case MMC_TIMING_UHS_SDR104:
1891 case MMC_TIMING_MMC_HS200:
1892 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1893 break;
1894 case MMC_TIMING_UHS_DDR50:
1895 case MMC_TIMING_MMC_DDR52:
1896 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1897 break;
1898 case MMC_TIMING_MMC_HS400:
1899 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1900 break;
1901 case MMC_TIMING_UHS2_SPEED_A:
1902 case MMC_TIMING_UHS2_SPEED_A_HD:
1903 case MMC_TIMING_UHS2_SPEED_B:
1904 case MMC_TIMING_UHS2_SPEED_B_HD:
1905 preset = sdhci_readw(host, SDHCI_PRESET_FOR_UHS2);
1906 break;
1907 default:
1908 pr_warn("%s: Invalid UHS-I mode selected\n",
1909 mmc_hostname(host->mmc));
1910 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1911 break;
1912 }
1913 return preset;
1914}
1915
1916u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1917 unsigned int *actual_clock)
1918{
1919 int div = 0; /* Initialized for compiler warning */
1920 int real_div = div, clk_mul = 1;
1921 u16 clk = 0;
1922 bool switch_base_clk = false;
1923
1924 if (host->version >= SDHCI_SPEC_300) {
1925 if (host->preset_enabled) {
1926 u16 pre_val;
1927
1928 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1929 pre_val = sdhci_get_preset_value(host);
1930 div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
1931 if (host->clk_mul &&
1932 (pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
1933 clk = SDHCI_PROG_CLOCK_MODE;
1934 real_div = div + 1;
1935 clk_mul = host->clk_mul;
1936 } else {
1937 real_div = max_t(int, 1, div << 1);
1938 }
1939 goto clock_set;
1940 }
1941
1942 /*
1943 * Check if the Host Controller supports Programmable Clock
1944 * Mode.
1945 */
1946 if (host->clk_mul) {
1947 for (div = 1; div <= 1024; div++) {
1948 if ((host->max_clk * host->clk_mul / div)
1949 <= clock)
1950 break;
1951 }
1952 if ((host->max_clk * host->clk_mul / div) <= clock) {
1953 /*
1954 * Set Programmable Clock Mode in the Clock
1955 * Control register.
1956 */
1957 clk = SDHCI_PROG_CLOCK_MODE;
1958 real_div = div;
1959 clk_mul = host->clk_mul;
1960 div--;
1961 } else {
1962 /*
1963 * Divisor can be too small to reach clock
1964 * speed requirement. Then use the base clock.
1965 */
1966 switch_base_clk = true;
1967 }
1968 }
1969
1970 if (!host->clk_mul || switch_base_clk) {
1971 /* Version 3.00 divisors must be a multiple of 2. */
1972 if (host->max_clk <= clock)
1973 div = 1;
1974 else {
1975 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1976 div += 2) {
1977 if ((host->max_clk / div) <= clock)
1978 break;
1979 }
1980 }
1981 real_div = div;
1982 div >>= 1;
1983 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1984 && !div && host->max_clk <= 25000000)
1985 div = 1;
1986 }
1987 } else {
1988 /* Version 2.00 divisors must be a power of 2. */
1989 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1990 if ((host->max_clk / div) <= clock)
1991 break;
1992 }
1993 real_div = div;
1994 div >>= 1;
1995 }
1996
1997clock_set:
1998 if (real_div)
1999 *actual_clock = (host->max_clk * clk_mul) / real_div;
2000 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
2001 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
2002 << SDHCI_DIVIDER_HI_SHIFT;
2003
2004 return clk;
2005}
2006EXPORT_SYMBOL_GPL(sdhci_calc_clk);
2007
2008void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
2009{
2010 ktime_t timeout;
2011
2012 clk |= SDHCI_CLOCK_INT_EN;
2013 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2014
2015 /* Wait max 150 ms */
2016 timeout = ktime_add_ms(ktime_get(), 150);
2017 while (1) {
2018 bool timedout = ktime_after(ktime_get(), timeout);
2019
2020 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2021 if (clk & SDHCI_CLOCK_INT_STABLE)
2022 break;
2023 if (timedout) {
2024 pr_err("%s: Internal clock never stabilised.\n",
2025 mmc_hostname(host->mmc));
2026 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
2027 sdhci_dumpregs(host);
2028 return;
2029 }
2030 udelay(10);
2031 }
2032
2033 if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
2034 clk |= SDHCI_CLOCK_PLL_EN;
2035 clk &= ~SDHCI_CLOCK_INT_STABLE;
2036 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2037
2038 /* Wait max 150 ms */
2039 timeout = ktime_add_ms(ktime_get(), 150);
2040 while (1) {
2041 bool timedout = ktime_after(ktime_get(), timeout);
2042
2043 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2044 if (clk & SDHCI_CLOCK_INT_STABLE)
2045 break;
2046 if (timedout) {
2047 pr_err("%s: PLL clock never stabilised.\n",
2048 mmc_hostname(host->mmc));
2049 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
2050 sdhci_dumpregs(host);
2051 return;
2052 }
2053 udelay(10);
2054 }
2055 }
2056
2057 clk |= SDHCI_CLOCK_CARD_EN;
2058 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2059}
2060EXPORT_SYMBOL_GPL(sdhci_enable_clk);
2061
2062void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
2063{
2064 u16 clk;
2065
2066 host->mmc->actual_clock = 0;
2067
2068 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
2069
2070 if (clock == 0)
2071 return;
2072
2073 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
2074 sdhci_enable_clk(host, clk);
2075}
2076EXPORT_SYMBOL_GPL(sdhci_set_clock);
2077
2078static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
2079 unsigned short vdd)
2080{
2081 struct mmc_host *mmc = host->mmc;
2082
2083 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2084
2085 if (mode != MMC_POWER_OFF)
2086 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
2087 else
2088 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2089}
2090
2091unsigned short sdhci_get_vdd_value(unsigned short vdd)
2092{
2093 switch (1 << vdd) {
2094 case MMC_VDD_165_195:
2095 /*
2096 * Without a regulator, SDHCI does not support 2.0v
2097 * so we only get here if the driver deliberately
2098 * added the 2.0v range to ocr_avail. Map it to 1.8v
2099 * for the purpose of turning on the power.
2100 */
2101 case MMC_VDD_20_21:
2102 return SDHCI_POWER_180;
2103 case MMC_VDD_29_30:
2104 case MMC_VDD_30_31:
2105 return SDHCI_POWER_300;
2106 case MMC_VDD_32_33:
2107 case MMC_VDD_33_34:
2108 /*
2109 * 3.4V ~ 3.6V are valid only for those platforms where it's
2110 * known that the voltage range is supported by hardware.
2111 */
2112 case MMC_VDD_34_35:
2113 case MMC_VDD_35_36:
2114 return SDHCI_POWER_330;
2115 default:
2116 return 0;
2117 }
2118}
2119EXPORT_SYMBOL_GPL(sdhci_get_vdd_value);
2120
2121void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
2122 unsigned short vdd)
2123{
2124 u8 pwr = 0;
2125
2126 if (mode != MMC_POWER_OFF) {
2127 pwr = sdhci_get_vdd_value(vdd);
2128 if (!pwr) {
2129 WARN(1, "%s: Invalid vdd %#x\n",
2130 mmc_hostname(host->mmc), vdd);
2131 }
2132 }
2133
2134 if (host->pwr == pwr)
2135 return;
2136
2137 host->pwr = pwr;
2138
2139 if (pwr == 0) {
2140 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2141 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2142 sdhci_runtime_pm_bus_off(host);
2143 } else {
2144 /*
2145 * Spec says that we should clear the power reg before setting
2146 * a new value. Some controllers don't seem to like this though.
2147 */
2148 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
2149 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2150
2151 /*
2152 * At least the Marvell CaFe chip gets confused if we set the
2153 * voltage and set turn on power at the same time, so set the
2154 * voltage first.
2155 */
2156 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
2157 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2158
2159 pwr |= SDHCI_POWER_ON;
2160
2161 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2162
2163 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2164 sdhci_runtime_pm_bus_on(host);
2165
2166 /*
2167 * Some controllers need an extra 10ms delay of 10ms before
2168 * they can apply clock after applying power
2169 */
2170 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
2171 mdelay(10);
2172 }
2173}
2174EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
2175
2176void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
2177 unsigned short vdd)
2178{
2179 if (IS_ERR(host->mmc->supply.vmmc))
2180 sdhci_set_power_noreg(host, mode, vdd);
2181 else
2182 sdhci_set_power_reg(host, mode, vdd);
2183}
2184EXPORT_SYMBOL_GPL(sdhci_set_power);
2185
2186/*
2187 * Some controllers need to configure a valid bus voltage on their power
2188 * register regardless of whether an external regulator is taking care of power
2189 * supply. This helper function takes care of it if set as the controller's
2190 * sdhci_ops.set_power callback.
2191 */
2192void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
2193 unsigned char mode,
2194 unsigned short vdd)
2195{
2196 if (!IS_ERR(host->mmc->supply.vmmc)) {
2197 struct mmc_host *mmc = host->mmc;
2198
2199 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2200 }
2201 sdhci_set_power_noreg(host, mode, vdd);
2202}
2203EXPORT_SYMBOL_GPL(sdhci_set_power_and_bus_voltage);
2204
2205/*****************************************************************************\
2206 * *
2207 * MMC callbacks *
2208 * *
2209\*****************************************************************************/
2210
2211void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
2212{
2213 struct sdhci_host *host = mmc_priv(mmc);
2214 struct mmc_command *cmd;
2215 unsigned long flags;
2216 bool present;
2217
2218 /* Firstly check card presence */
2219 present = mmc->ops->get_cd(mmc);
2220
2221 spin_lock_irqsave(&host->lock, flags);
2222
2223 sdhci_led_activate(host);
2224
2225 if (sdhci_present_error(host, mrq->cmd, present))
2226 goto out_finish;
2227
2228 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2229
2230 if (!sdhci_send_command_retry(host, cmd, flags))
2231 goto out_finish;
2232
2233 spin_unlock_irqrestore(&host->lock, flags);
2234
2235 return;
2236
2237out_finish:
2238 sdhci_finish_mrq(host, mrq);
2239 spin_unlock_irqrestore(&host->lock, flags);
2240}
2241EXPORT_SYMBOL_GPL(sdhci_request);
2242
2243int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq)
2244{
2245 struct sdhci_host *host = mmc_priv(mmc);
2246 struct mmc_command *cmd;
2247 unsigned long flags;
2248 int ret = 0;
2249
2250 spin_lock_irqsave(&host->lock, flags);
2251
2252 if (sdhci_present_error(host, mrq->cmd, true)) {
2253 sdhci_finish_mrq(host, mrq);
2254 goto out_finish;
2255 }
2256
2257 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2258
2259 /*
2260 * The HSQ may send a command in interrupt context without polling
2261 * the busy signaling, which means we should return BUSY if controller
2262 * has not released inhibit bits to allow HSQ trying to send request
2263 * again in non-atomic context. So we should not finish this request
2264 * here.
2265 */
2266 if (!sdhci_send_command(host, cmd))
2267 ret = -EBUSY;
2268 else
2269 sdhci_led_activate(host);
2270
2271out_finish:
2272 spin_unlock_irqrestore(&host->lock, flags);
2273 return ret;
2274}
2275EXPORT_SYMBOL_GPL(sdhci_request_atomic);
2276
2277void sdhci_set_bus_width(struct sdhci_host *host, int width)
2278{
2279 u8 ctrl;
2280
2281 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2282 if (width == MMC_BUS_WIDTH_8) {
2283 ctrl &= ~SDHCI_CTRL_4BITBUS;
2284 ctrl |= SDHCI_CTRL_8BITBUS;
2285 } else {
2286 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
2287 ctrl &= ~SDHCI_CTRL_8BITBUS;
2288 if (width == MMC_BUS_WIDTH_4)
2289 ctrl |= SDHCI_CTRL_4BITBUS;
2290 else
2291 ctrl &= ~SDHCI_CTRL_4BITBUS;
2292 }
2293 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2294}
2295EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
2296
2297void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
2298{
2299 u16 ctrl_2;
2300
2301 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2302 /* Select Bus Speed Mode for host */
2303 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
2304 if ((timing == MMC_TIMING_MMC_HS200) ||
2305 (timing == MMC_TIMING_UHS_SDR104))
2306 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
2307 else if (timing == MMC_TIMING_UHS_SDR12)
2308 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
2309 else if (timing == MMC_TIMING_UHS_SDR25)
2310 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
2311 else if (timing == MMC_TIMING_UHS_SDR50)
2312 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
2313 else if ((timing == MMC_TIMING_UHS_DDR50) ||
2314 (timing == MMC_TIMING_MMC_DDR52))
2315 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
2316 else if (timing == MMC_TIMING_MMC_HS400)
2317 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
2318 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2319}
2320EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
2321
2322static bool sdhci_timing_has_preset(unsigned char timing)
2323{
2324 switch (timing) {
2325 case MMC_TIMING_UHS_SDR12:
2326 case MMC_TIMING_UHS_SDR25:
2327 case MMC_TIMING_UHS_SDR50:
2328 case MMC_TIMING_UHS_SDR104:
2329 case MMC_TIMING_UHS_DDR50:
2330 case MMC_TIMING_MMC_DDR52:
2331 return true;
2332 }
2333 return false;
2334}
2335
2336static bool sdhci_preset_needed(struct sdhci_host *host, unsigned char timing)
2337{
2338 return !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
2339 sdhci_timing_has_preset(timing);
2340}
2341
2342static bool sdhci_presetable_values_change(struct sdhci_host *host, struct mmc_ios *ios)
2343{
2344 /*
2345 * Preset Values are: Driver Strength, Clock Generator and SDCLK/RCLK
2346 * Frequency. Check if preset values need to be enabled, or the Driver
2347 * Strength needs updating. Note, clock changes are handled separately.
2348 */
2349 return !host->preset_enabled &&
2350 (sdhci_preset_needed(host, ios->timing) || host->drv_type != ios->drv_type);
2351}
2352
2353void sdhci_set_ios_common(struct mmc_host *mmc, struct mmc_ios *ios)
2354{
2355 struct sdhci_host *host = mmc_priv(mmc);
2356
2357 /*
2358 * Reset the chip on each power off.
2359 * Should clear out any weird states.
2360 */
2361 if (ios->power_mode == MMC_POWER_OFF) {
2362 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2363 sdhci_reinit(host);
2364 }
2365
2366 if (host->version >= SDHCI_SPEC_300 &&
2367 (ios->power_mode == MMC_POWER_UP) &&
2368 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
2369 sdhci_enable_preset_value(host, false);
2370
2371 if (!ios->clock || ios->clock != host->clock) {
2372 host->ops->set_clock(host, ios->clock);
2373 host->clock = ios->clock;
2374
2375 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
2376 host->clock) {
2377 host->timeout_clk = mmc->actual_clock ?
2378 mmc->actual_clock / 1000 :
2379 host->clock / 1000;
2380 mmc->max_busy_timeout =
2381 host->ops->get_max_timeout_count ?
2382 host->ops->get_max_timeout_count(host) :
2383 1 << 27;
2384 mmc->max_busy_timeout /= host->timeout_clk;
2385 }
2386 }
2387}
2388EXPORT_SYMBOL_GPL(sdhci_set_ios_common);
2389
2390void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2391{
2392 struct sdhci_host *host = mmc_priv(mmc);
2393 bool reinit_uhs = host->reinit_uhs;
2394 bool turning_on_clk;
2395 u8 ctrl;
2396
2397 host->reinit_uhs = false;
2398
2399 if (ios->power_mode == MMC_POWER_UNDEFINED)
2400 return;
2401
2402 if (host->flags & SDHCI_DEVICE_DEAD) {
2403 if (!IS_ERR(mmc->supply.vmmc) &&
2404 ios->power_mode == MMC_POWER_OFF)
2405 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
2406 return;
2407 }
2408
2409 turning_on_clk = ios->clock != host->clock && ios->clock && !host->clock;
2410
2411 sdhci_set_ios_common(mmc, ios);
2412
2413 if (host->ops->set_power)
2414 host->ops->set_power(host, ios->power_mode, ios->vdd);
2415 else
2416 sdhci_set_power(host, ios->power_mode, ios->vdd);
2417
2418 if (host->ops->platform_send_init_74_clocks)
2419 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
2420
2421 host->ops->set_bus_width(host, ios->bus_width);
2422
2423 /*
2424 * Special case to avoid multiple clock changes during voltage
2425 * switching.
2426 */
2427 if (!reinit_uhs &&
2428 turning_on_clk &&
2429 host->timing == ios->timing &&
2430 host->version >= SDHCI_SPEC_300 &&
2431 !sdhci_presetable_values_change(host, ios))
2432 return;
2433
2434 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2435
2436 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
2437 if (ios->timing == MMC_TIMING_SD_HS ||
2438 ios->timing == MMC_TIMING_MMC_HS ||
2439 ios->timing == MMC_TIMING_MMC_HS400 ||
2440 ios->timing == MMC_TIMING_MMC_HS200 ||
2441 ios->timing == MMC_TIMING_MMC_DDR52 ||
2442 ios->timing == MMC_TIMING_UHS_SDR50 ||
2443 ios->timing == MMC_TIMING_UHS_SDR104 ||
2444 ios->timing == MMC_TIMING_UHS_DDR50 ||
2445 ios->timing == MMC_TIMING_UHS_SDR25)
2446 ctrl |= SDHCI_CTRL_HISPD;
2447 else
2448 ctrl &= ~SDHCI_CTRL_HISPD;
2449 }
2450
2451 if (host->version >= SDHCI_SPEC_300) {
2452 u16 clk, ctrl_2;
2453
2454 /*
2455 * According to SDHCI Spec v3.00, if the Preset Value
2456 * Enable in the Host Control 2 register is set, we
2457 * need to reset SD Clock Enable before changing High
2458 * Speed Enable to avoid generating clock glitches.
2459 */
2460 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2461 if (clk & SDHCI_CLOCK_CARD_EN) {
2462 clk &= ~SDHCI_CLOCK_CARD_EN;
2463 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2464 }
2465
2466 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2467
2468 if (!host->preset_enabled) {
2469 /*
2470 * We only need to set Driver Strength if the
2471 * preset value enable is not set.
2472 */
2473 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2474 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
2475 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
2476 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
2477 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
2478 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2479 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
2480 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
2481 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
2482 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
2483 else {
2484 pr_warn("%s: invalid driver type, default to driver type B\n",
2485 mmc_hostname(mmc));
2486 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2487 }
2488
2489 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2490 host->drv_type = ios->drv_type;
2491 }
2492
2493 host->ops->set_uhs_signaling(host, ios->timing);
2494 host->timing = ios->timing;
2495
2496 if (sdhci_preset_needed(host, ios->timing)) {
2497 u16 preset;
2498
2499 sdhci_enable_preset_value(host, true);
2500 preset = sdhci_get_preset_value(host);
2501 ios->drv_type = FIELD_GET(SDHCI_PRESET_DRV_MASK,
2502 preset);
2503 host->drv_type = ios->drv_type;
2504 }
2505
2506 /* Re-enable SD Clock */
2507 host->ops->set_clock(host, host->clock);
2508 } else
2509 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2510}
2511EXPORT_SYMBOL_GPL(sdhci_set_ios);
2512
2513static int sdhci_get_cd(struct mmc_host *mmc)
2514{
2515 struct sdhci_host *host = mmc_priv(mmc);
2516 int gpio_cd = mmc_gpio_get_cd(mmc);
2517
2518 if (host->flags & SDHCI_DEVICE_DEAD)
2519 return 0;
2520
2521 /* If nonremovable, assume that the card is always present. */
2522 if (!mmc_card_is_removable(mmc))
2523 return 1;
2524
2525 /*
2526 * Try slot gpio detect, if defined it take precedence
2527 * over build in controller functionality
2528 */
2529 if (gpio_cd >= 0)
2530 return !!gpio_cd;
2531
2532 /* If polling, assume that the card is always present. */
2533 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2534 return 1;
2535
2536 /* Host native card detect */
2537 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2538}
2539
2540int sdhci_get_cd_nogpio(struct mmc_host *mmc)
2541{
2542 struct sdhci_host *host = mmc_priv(mmc);
2543 unsigned long flags;
2544 int ret = 0;
2545
2546 spin_lock_irqsave(&host->lock, flags);
2547
2548 if (host->flags & SDHCI_DEVICE_DEAD)
2549 goto out;
2550
2551 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2552out:
2553 spin_unlock_irqrestore(&host->lock, flags);
2554
2555 return ret;
2556}
2557EXPORT_SYMBOL_GPL(sdhci_get_cd_nogpio);
2558
2559int sdhci_get_ro(struct mmc_host *mmc)
2560{
2561 struct sdhci_host *host = mmc_priv(mmc);
2562 bool allow_invert = false;
2563 int is_readonly;
2564
2565 if (host->flags & SDHCI_DEVICE_DEAD) {
2566 is_readonly = 0;
2567 } else if (host->ops->get_ro) {
2568 is_readonly = host->ops->get_ro(host);
2569 } else if (mmc_can_gpio_ro(mmc)) {
2570 is_readonly = mmc_gpio_get_ro(mmc);
2571 /* Do not invert twice */
2572 allow_invert = !(mmc->caps2 & MMC_CAP2_RO_ACTIVE_HIGH);
2573 } else {
2574 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2575 & SDHCI_WRITE_PROTECT);
2576 allow_invert = true;
2577 }
2578
2579 if (is_readonly >= 0 &&
2580 allow_invert &&
2581 (host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT))
2582 is_readonly = !is_readonly;
2583
2584 return is_readonly;
2585}
2586EXPORT_SYMBOL_GPL(sdhci_get_ro);
2587
2588static void sdhci_hw_reset(struct mmc_host *mmc)
2589{
2590 struct sdhci_host *host = mmc_priv(mmc);
2591
2592 if (host->ops && host->ops->hw_reset)
2593 host->ops->hw_reset(host);
2594}
2595
2596static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2597{
2598 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
2599 if (enable)
2600 host->ier |= SDHCI_INT_CARD_INT;
2601 else
2602 host->ier &= ~SDHCI_INT_CARD_INT;
2603
2604 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2605 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2606 }
2607}
2608
2609void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
2610{
2611 struct sdhci_host *host = mmc_priv(mmc);
2612 unsigned long flags;
2613
2614 if (enable)
2615 pm_runtime_get_noresume(mmc_dev(mmc));
2616
2617 spin_lock_irqsave(&host->lock, flags);
2618 sdhci_enable_sdio_irq_nolock(host, enable);
2619 spin_unlock_irqrestore(&host->lock, flags);
2620
2621 if (!enable)
2622 pm_runtime_put_noidle(mmc_dev(mmc));
2623}
2624EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
2625
2626static void sdhci_ack_sdio_irq(struct mmc_host *mmc)
2627{
2628 struct sdhci_host *host = mmc_priv(mmc);
2629 unsigned long flags;
2630
2631 spin_lock_irqsave(&host->lock, flags);
2632 sdhci_enable_sdio_irq_nolock(host, true);
2633 spin_unlock_irqrestore(&host->lock, flags);
2634}
2635
2636int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2637 struct mmc_ios *ios)
2638{
2639 struct sdhci_host *host = mmc_priv(mmc);
2640 u16 ctrl;
2641 int ret;
2642
2643 /*
2644 * Signal Voltage Switching is only applicable for Host Controllers
2645 * v3.00 and above.
2646 */
2647 if (host->version < SDHCI_SPEC_300)
2648 return 0;
2649
2650 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2651
2652 switch (ios->signal_voltage) {
2653 case MMC_SIGNAL_VOLTAGE_330:
2654 if (!(host->flags & SDHCI_SIGNALING_330))
2655 return -EINVAL;
2656 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2657 ctrl &= ~SDHCI_CTRL_VDD_180;
2658 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2659
2660 if (!IS_ERR(mmc->supply.vqmmc)) {
2661 ret = mmc_regulator_set_vqmmc(mmc, ios);
2662 if (ret < 0) {
2663 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
2664 mmc_hostname(mmc));
2665 return -EIO;
2666 }
2667 }
2668 /* Wait for 5ms */
2669 usleep_range(5000, 5500);
2670
2671 /* 3.3V regulator output should be stable within 5 ms */
2672 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2673 if (!(ctrl & SDHCI_CTRL_VDD_180))
2674 return 0;
2675
2676 pr_warn("%s: 3.3V regulator output did not become stable\n",
2677 mmc_hostname(mmc));
2678
2679 return -EAGAIN;
2680 case MMC_SIGNAL_VOLTAGE_180:
2681 if (!(host->flags & SDHCI_SIGNALING_180))
2682 return -EINVAL;
2683 if (!IS_ERR(mmc->supply.vqmmc)) {
2684 ret = mmc_regulator_set_vqmmc(mmc, ios);
2685 if (ret < 0) {
2686 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
2687 mmc_hostname(mmc));
2688 return -EIO;
2689 }
2690 }
2691
2692 /*
2693 * Enable 1.8V Signal Enable in the Host Control2
2694 * register
2695 */
2696 ctrl |= SDHCI_CTRL_VDD_180;
2697 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2698
2699 /* Some controller need to do more when switching */
2700 if (host->ops->voltage_switch)
2701 host->ops->voltage_switch(host);
2702
2703 /* 1.8V regulator output should be stable within 5 ms */
2704 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2705 if (ctrl & SDHCI_CTRL_VDD_180)
2706 return 0;
2707
2708 pr_warn("%s: 1.8V regulator output did not become stable\n",
2709 mmc_hostname(mmc));
2710
2711 return -EAGAIN;
2712 case MMC_SIGNAL_VOLTAGE_120:
2713 if (!(host->flags & SDHCI_SIGNALING_120))
2714 return -EINVAL;
2715 if (!IS_ERR(mmc->supply.vqmmc)) {
2716 ret = mmc_regulator_set_vqmmc(mmc, ios);
2717 if (ret < 0) {
2718 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
2719 mmc_hostname(mmc));
2720 return -EIO;
2721 }
2722 }
2723 return 0;
2724 default:
2725 /* No signal voltage switch required */
2726 return 0;
2727 }
2728}
2729EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2730
2731static int sdhci_card_busy(struct mmc_host *mmc)
2732{
2733 struct sdhci_host *host = mmc_priv(mmc);
2734 u32 present_state;
2735
2736 /* Check whether DAT[0] is 0 */
2737 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2738
2739 return !(present_state & SDHCI_DATA_0_LVL_MASK);
2740}
2741
2742static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2743{
2744 struct sdhci_host *host = mmc_priv(mmc);
2745 unsigned long flags;
2746
2747 spin_lock_irqsave(&host->lock, flags);
2748 host->flags |= SDHCI_HS400_TUNING;
2749 spin_unlock_irqrestore(&host->lock, flags);
2750
2751 return 0;
2752}
2753
2754void sdhci_start_tuning(struct sdhci_host *host)
2755{
2756 u16 ctrl;
2757
2758 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2759 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2760 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2761 ctrl |= SDHCI_CTRL_TUNED_CLK;
2762 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2763
2764 /*
2765 * As per the Host Controller spec v3.00, tuning command
2766 * generates Buffer Read Ready interrupt, so enable that.
2767 *
2768 * Note: The spec clearly says that when tuning sequence
2769 * is being performed, the controller does not generate
2770 * interrupts other than Buffer Read Ready interrupt. But
2771 * to make sure we don't hit a controller bug, we _only_
2772 * enable Buffer Read Ready interrupt here.
2773 */
2774 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2775 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2776}
2777EXPORT_SYMBOL_GPL(sdhci_start_tuning);
2778
2779void sdhci_end_tuning(struct sdhci_host *host)
2780{
2781 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2782 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2783}
2784EXPORT_SYMBOL_GPL(sdhci_end_tuning);
2785
2786void sdhci_reset_tuning(struct sdhci_host *host)
2787{
2788 u16 ctrl;
2789
2790 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2791 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2792 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2793 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2794}
2795EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
2796
2797void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2798{
2799 sdhci_reset_tuning(host);
2800
2801 sdhci_reset_for(host, TUNING_ABORT);
2802
2803 sdhci_end_tuning(host);
2804
2805 mmc_send_abort_tuning(host->mmc, opcode);
2806}
2807EXPORT_SYMBOL_GPL(sdhci_abort_tuning);
2808
2809/*
2810 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2811 * tuning command does not have a data payload (or rather the hardware does it
2812 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2813 * interrupt setup is different to other commands and there is no timeout
2814 * interrupt so special handling is needed.
2815 */
2816void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2817{
2818 struct mmc_host *mmc = host->mmc;
2819 struct mmc_command cmd = {};
2820 struct mmc_request mrq = {};
2821 unsigned long flags;
2822 u32 b = host->sdma_boundary;
2823
2824 spin_lock_irqsave(&host->lock, flags);
2825
2826 cmd.opcode = opcode;
2827 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2828 cmd.mrq = &mrq;
2829
2830 mrq.cmd = &cmd;
2831 /*
2832 * In response to CMD19, the card sends 64 bytes of tuning
2833 * block to the Host Controller. So we set the block size
2834 * to 64 here.
2835 */
2836 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2837 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2838 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2839 else
2840 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2841
2842 /*
2843 * The tuning block is sent by the card to the host controller.
2844 * So we set the TRNS_READ bit in the Transfer Mode register.
2845 * This also takes care of setting DMA Enable and Multi Block
2846 * Select in the same register to 0.
2847 */
2848 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2849
2850 if (!sdhci_send_command_retry(host, &cmd, flags)) {
2851 spin_unlock_irqrestore(&host->lock, flags);
2852 host->tuning_done = 0;
2853 return;
2854 }
2855
2856 host->cmd = NULL;
2857
2858 sdhci_del_timer(host, &mrq);
2859
2860 host->tuning_done = 0;
2861
2862 spin_unlock_irqrestore(&host->lock, flags);
2863
2864 /* Wait for Buffer Read Ready interrupt */
2865 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2866 msecs_to_jiffies(50));
2867
2868}
2869EXPORT_SYMBOL_GPL(sdhci_send_tuning);
2870
2871int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2872{
2873 int i;
2874
2875 /*
2876 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2877 * of loops reaches tuning loop count.
2878 */
2879 for (i = 0; i < host->tuning_loop_count; i++) {
2880 u16 ctrl;
2881
2882 sdhci_send_tuning(host, opcode);
2883
2884 if (!host->tuning_done) {
2885 pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
2886 mmc_hostname(host->mmc));
2887 sdhci_abort_tuning(host, opcode);
2888 return -ETIMEDOUT;
2889 }
2890
2891 /* Spec does not require a delay between tuning cycles */
2892 if (host->tuning_delay > 0)
2893 mdelay(host->tuning_delay);
2894
2895 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2896 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2897 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2898 return 0; /* Success! */
2899 break;
2900 }
2901
2902 }
2903
2904 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2905 mmc_hostname(host->mmc));
2906 sdhci_reset_tuning(host);
2907 return -EAGAIN;
2908}
2909EXPORT_SYMBOL_GPL(__sdhci_execute_tuning);
2910
2911int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2912{
2913 struct sdhci_host *host = mmc_priv(mmc);
2914 int err = 0;
2915 unsigned int tuning_count = 0;
2916 bool hs400_tuning;
2917
2918 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2919
2920 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2921 tuning_count = host->tuning_count;
2922
2923 /*
2924 * The Host Controller needs tuning in case of SDR104 and DDR50
2925 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2926 * the Capabilities register.
2927 * If the Host Controller supports the HS200 mode then the
2928 * tuning function has to be executed.
2929 */
2930 switch (host->timing) {
2931 /* HS400 tuning is done in HS200 mode */
2932 case MMC_TIMING_MMC_HS400:
2933 err = -EINVAL;
2934 goto out;
2935
2936 case MMC_TIMING_MMC_HS200:
2937 /*
2938 * Periodic re-tuning for HS400 is not expected to be needed, so
2939 * disable it here.
2940 */
2941 if (hs400_tuning)
2942 tuning_count = 0;
2943 break;
2944
2945 case MMC_TIMING_UHS_SDR104:
2946 case MMC_TIMING_UHS_DDR50:
2947 break;
2948
2949 case MMC_TIMING_UHS_SDR50:
2950 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2951 break;
2952 fallthrough;
2953
2954 default:
2955 goto out;
2956 }
2957
2958 if (host->ops->platform_execute_tuning) {
2959 err = host->ops->platform_execute_tuning(host, opcode);
2960 goto out;
2961 }
2962
2963 mmc->retune_period = tuning_count;
2964
2965 if (host->tuning_delay < 0)
2966 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2967
2968 sdhci_start_tuning(host);
2969
2970 host->tuning_err = __sdhci_execute_tuning(host, opcode);
2971
2972 sdhci_end_tuning(host);
2973out:
2974 host->flags &= ~SDHCI_HS400_TUNING;
2975
2976 return err;
2977}
2978EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2979
2980void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2981{
2982 /* Host Controller v3.00 defines preset value registers */
2983 if (host->version < SDHCI_SPEC_300)
2984 return;
2985
2986 /*
2987 * We only enable or disable Preset Value if they are not already
2988 * enabled or disabled respectively. Otherwise, we bail out.
2989 */
2990 if (host->preset_enabled != enable) {
2991 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2992
2993 if (enable)
2994 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2995 else
2996 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2997
2998 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2999
3000 if (enable)
3001 host->flags |= SDHCI_PV_ENABLED;
3002 else
3003 host->flags &= ~SDHCI_PV_ENABLED;
3004
3005 host->preset_enabled = enable;
3006 }
3007}
3008EXPORT_SYMBOL_GPL(sdhci_enable_preset_value);
3009
3010static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
3011 int err)
3012{
3013 struct mmc_data *data = mrq->data;
3014
3015 if (data->host_cookie != COOKIE_UNMAPPED)
3016 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
3017 mmc_get_dma_dir(data));
3018
3019 data->host_cookie = COOKIE_UNMAPPED;
3020}
3021
3022static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
3023{
3024 struct sdhci_host *host = mmc_priv(mmc);
3025
3026 mrq->data->host_cookie = COOKIE_UNMAPPED;
3027
3028 /*
3029 * No pre-mapping in the pre hook if we're using the bounce buffer,
3030 * for that we would need two bounce buffers since one buffer is
3031 * in flight when this is getting called.
3032 */
3033 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
3034 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
3035}
3036
3037static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
3038{
3039 if (host->data_cmd) {
3040 host->data_cmd->error = err;
3041 sdhci_finish_mrq(host, host->data_cmd->mrq);
3042 }
3043
3044 if (host->cmd) {
3045 host->cmd->error = err;
3046 sdhci_finish_mrq(host, host->cmd->mrq);
3047 }
3048}
3049
3050static void sdhci_card_event(struct mmc_host *mmc)
3051{
3052 struct sdhci_host *host = mmc_priv(mmc);
3053 unsigned long flags;
3054 int present;
3055
3056 /* First check if client has provided their own card event */
3057 if (host->ops->card_event)
3058 host->ops->card_event(host);
3059
3060 present = mmc->ops->get_cd(mmc);
3061
3062 spin_lock_irqsave(&host->lock, flags);
3063
3064 /* Check sdhci_has_requests() first in case we are runtime suspended */
3065 if (sdhci_has_requests(host) && !present) {
3066 pr_err("%s: Card removed during transfer!\n",
3067 mmc_hostname(mmc));
3068 pr_err("%s: Resetting controller.\n",
3069 mmc_hostname(mmc));
3070
3071 sdhci_reset_for(host, CARD_REMOVED);
3072
3073 sdhci_error_out_mrqs(host, -ENOMEDIUM);
3074 }
3075
3076 spin_unlock_irqrestore(&host->lock, flags);
3077}
3078
3079static const struct mmc_host_ops sdhci_ops = {
3080 .request = sdhci_request,
3081 .post_req = sdhci_post_req,
3082 .pre_req = sdhci_pre_req,
3083 .set_ios = sdhci_set_ios,
3084 .get_cd = sdhci_get_cd,
3085 .get_ro = sdhci_get_ro,
3086 .card_hw_reset = sdhci_hw_reset,
3087 .enable_sdio_irq = sdhci_enable_sdio_irq,
3088 .ack_sdio_irq = sdhci_ack_sdio_irq,
3089 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
3090 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
3091 .execute_tuning = sdhci_execute_tuning,
3092 .card_event = sdhci_card_event,
3093 .card_busy = sdhci_card_busy,
3094};
3095
3096/*****************************************************************************\
3097 * *
3098 * Request done *
3099 * *
3100\*****************************************************************************/
3101
3102void sdhci_request_done_dma(struct sdhci_host *host, struct mmc_request *mrq)
3103{
3104 struct mmc_data *data = mrq->data;
3105
3106 if (data && data->host_cookie == COOKIE_MAPPED) {
3107 if (host->bounce_buffer) {
3108 /*
3109 * On reads, copy the bounced data into the
3110 * sglist
3111 */
3112 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
3113 unsigned int length = data->bytes_xfered;
3114
3115 if (length > host->bounce_buffer_size) {
3116 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
3117 mmc_hostname(host->mmc),
3118 host->bounce_buffer_size,
3119 data->bytes_xfered);
3120 /* Cap it down and continue */
3121 length = host->bounce_buffer_size;
3122 }
3123 dma_sync_single_for_cpu(mmc_dev(host->mmc),
3124 host->bounce_addr,
3125 host->bounce_buffer_size,
3126 DMA_FROM_DEVICE);
3127 sg_copy_from_buffer(data->sg,
3128 data->sg_len,
3129 host->bounce_buffer,
3130 length);
3131 } else {
3132 /* No copying, just switch ownership */
3133 dma_sync_single_for_cpu(mmc_dev(host->mmc),
3134 host->bounce_addr,
3135 host->bounce_buffer_size,
3136 mmc_get_dma_dir(data));
3137 }
3138 } else {
3139 /* Unmap the raw data */
3140 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
3141 data->sg_len,
3142 mmc_get_dma_dir(data));
3143 }
3144 data->host_cookie = COOKIE_UNMAPPED;
3145 }
3146}
3147EXPORT_SYMBOL_GPL(sdhci_request_done_dma);
3148
3149static bool sdhci_request_done(struct sdhci_host *host)
3150{
3151 unsigned long flags;
3152 struct mmc_request *mrq;
3153 int i;
3154
3155 spin_lock_irqsave(&host->lock, flags);
3156
3157 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3158 mrq = host->mrqs_done[i];
3159 if (mrq)
3160 break;
3161 }
3162
3163 if (!mrq) {
3164 spin_unlock_irqrestore(&host->lock, flags);
3165 return true;
3166 }
3167
3168 /*
3169 * The controller needs a reset of internal state machines
3170 * upon error conditions.
3171 */
3172 if (sdhci_needs_reset(host, mrq)) {
3173 /*
3174 * Do not finish until command and data lines are available for
3175 * reset. Note there can only be one other mrq, so it cannot
3176 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
3177 * would both be null.
3178 */
3179 if (host->cmd || host->data_cmd) {
3180 spin_unlock_irqrestore(&host->lock, flags);
3181 return true;
3182 }
3183
3184 /* Some controllers need this kick or reset won't work here */
3185 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
3186 /* This is to force an update */
3187 host->ops->set_clock(host, host->clock);
3188
3189 sdhci_reset_for(host, REQUEST_ERROR);
3190
3191 host->pending_reset = false;
3192 }
3193
3194 /*
3195 * Always unmap the data buffers if they were mapped by
3196 * sdhci_prepare_data() whenever we finish with a request.
3197 * This avoids leaking DMA mappings on error.
3198 */
3199 if (host->flags & SDHCI_REQ_USE_DMA) {
3200 struct mmc_data *data = mrq->data;
3201
3202 if (host->use_external_dma && data &&
3203 (mrq->cmd->error || data->error)) {
3204 struct dma_chan *chan = sdhci_external_dma_channel(host, data);
3205
3206 host->mrqs_done[i] = NULL;
3207 spin_unlock_irqrestore(&host->lock, flags);
3208 dmaengine_terminate_sync(chan);
3209 spin_lock_irqsave(&host->lock, flags);
3210 sdhci_set_mrq_done(host, mrq);
3211 }
3212
3213 sdhci_request_done_dma(host, mrq);
3214 }
3215
3216 host->mrqs_done[i] = NULL;
3217
3218 spin_unlock_irqrestore(&host->lock, flags);
3219
3220 if (host->ops->request_done)
3221 host->ops->request_done(host, mrq);
3222 else
3223 mmc_request_done(host->mmc, mrq);
3224
3225 return false;
3226}
3227
3228void sdhci_complete_work(struct work_struct *work)
3229{
3230 struct sdhci_host *host = container_of(work, struct sdhci_host,
3231 complete_work);
3232
3233 while (!sdhci_request_done(host))
3234 ;
3235}
3236EXPORT_SYMBOL_GPL(sdhci_complete_work);
3237
3238static void sdhci_timeout_timer(struct timer_list *t)
3239{
3240 struct sdhci_host *host;
3241 unsigned long flags;
3242
3243 host = from_timer(host, t, timer);
3244
3245 spin_lock_irqsave(&host->lock, flags);
3246
3247 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
3248 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
3249 mmc_hostname(host->mmc));
3250 sdhci_err_stats_inc(host, REQ_TIMEOUT);
3251 sdhci_dumpregs(host);
3252
3253 host->cmd->error = -ETIMEDOUT;
3254 sdhci_finish_mrq(host, host->cmd->mrq);
3255 }
3256
3257 spin_unlock_irqrestore(&host->lock, flags);
3258}
3259
3260static void sdhci_timeout_data_timer(struct timer_list *t)
3261{
3262 struct sdhci_host *host;
3263 unsigned long flags;
3264
3265 host = from_timer(host, t, data_timer);
3266
3267 spin_lock_irqsave(&host->lock, flags);
3268
3269 if (host->data || host->data_cmd ||
3270 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
3271 pr_err("%s: Timeout waiting for hardware interrupt.\n",
3272 mmc_hostname(host->mmc));
3273 sdhci_err_stats_inc(host, REQ_TIMEOUT);
3274 sdhci_dumpregs(host);
3275
3276 if (host->data) {
3277 host->data->error = -ETIMEDOUT;
3278 __sdhci_finish_data(host, true);
3279 queue_work(host->complete_wq, &host->complete_work);
3280 } else if (host->data_cmd) {
3281 host->data_cmd->error = -ETIMEDOUT;
3282 sdhci_finish_mrq(host, host->data_cmd->mrq);
3283 } else {
3284 host->cmd->error = -ETIMEDOUT;
3285 sdhci_finish_mrq(host, host->cmd->mrq);
3286 }
3287 }
3288
3289 spin_unlock_irqrestore(&host->lock, flags);
3290}
3291
3292/*****************************************************************************\
3293 * *
3294 * Interrupt handling *
3295 * *
3296\*****************************************************************************/
3297
3298static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
3299{
3300 /* Handle auto-CMD12 error */
3301 if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
3302 struct mmc_request *mrq = host->data_cmd->mrq;
3303 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3304 int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3305 SDHCI_INT_DATA_TIMEOUT :
3306 SDHCI_INT_DATA_CRC;
3307
3308 /* Treat auto-CMD12 error the same as data error */
3309 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
3310 *intmask_p |= data_err_bit;
3311 return;
3312 }
3313 }
3314
3315 if (!host->cmd) {
3316 /*
3317 * SDHCI recovers from errors by resetting the cmd and data
3318 * circuits. Until that is done, there very well might be more
3319 * interrupts, so ignore them in that case.
3320 */
3321 if (host->pending_reset)
3322 return;
3323 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
3324 mmc_hostname(host->mmc), (unsigned)intmask);
3325 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
3326 sdhci_dumpregs(host);
3327 return;
3328 }
3329
3330 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
3331 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
3332 if (intmask & SDHCI_INT_TIMEOUT) {
3333 host->cmd->error = -ETIMEDOUT;
3334 sdhci_err_stats_inc(host, CMD_TIMEOUT);
3335 } else {
3336 host->cmd->error = -EILSEQ;
3337 if (!mmc_op_tuning(host->cmd->opcode))
3338 sdhci_err_stats_inc(host, CMD_CRC);
3339 }
3340 /* Treat data command CRC error the same as data CRC error */
3341 if (host->cmd->data &&
3342 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
3343 SDHCI_INT_CRC) {
3344 host->cmd = NULL;
3345 *intmask_p |= SDHCI_INT_DATA_CRC;
3346 return;
3347 }
3348
3349 __sdhci_finish_mrq(host, host->cmd->mrq);
3350 return;
3351 }
3352
3353 /* Handle auto-CMD23 error */
3354 if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
3355 struct mmc_request *mrq = host->cmd->mrq;
3356 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3357 int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3358 -ETIMEDOUT :
3359 -EILSEQ;
3360
3361 sdhci_err_stats_inc(host, AUTO_CMD);
3362
3363 if (sdhci_auto_cmd23(host, mrq)) {
3364 mrq->sbc->error = err;
3365 __sdhci_finish_mrq(host, mrq);
3366 return;
3367 }
3368 }
3369
3370 if (intmask & SDHCI_INT_RESPONSE)
3371 sdhci_finish_command(host);
3372}
3373
3374static void sdhci_adma_show_error(struct sdhci_host *host)
3375{
3376 void *desc = host->adma_table;
3377 dma_addr_t dma = host->adma_addr;
3378
3379 sdhci_dumpregs(host);
3380
3381 while (true) {
3382 struct sdhci_adma2_64_desc *dma_desc = desc;
3383
3384 if (host->flags & SDHCI_USE_64_BIT_DMA)
3385 SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
3386 (unsigned long long)dma,
3387 le32_to_cpu(dma_desc->addr_hi),
3388 le32_to_cpu(dma_desc->addr_lo),
3389 le16_to_cpu(dma_desc->len),
3390 le16_to_cpu(dma_desc->cmd));
3391 else
3392 SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
3393 (unsigned long long)dma,
3394 le32_to_cpu(dma_desc->addr_lo),
3395 le16_to_cpu(dma_desc->len),
3396 le16_to_cpu(dma_desc->cmd));
3397
3398 desc += host->desc_sz;
3399 dma += host->desc_sz;
3400
3401 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
3402 break;
3403 }
3404}
3405
3406static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
3407{
3408 /*
3409 * CMD19 generates _only_ Buffer Read Ready interrupt if
3410 * use sdhci_send_tuning.
3411 * Need to exclude this case: PIO mode and use mmc_send_tuning,
3412 * If not, sdhci_transfer_pio will never be called, make the
3413 * SDHCI_INT_DATA_AVAIL always there, stuck in irq storm.
3414 */
3415 if (intmask & SDHCI_INT_DATA_AVAIL && !host->data) {
3416 if (mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)))) {
3417 host->tuning_done = 1;
3418 wake_up(&host->buf_ready_int);
3419 return;
3420 }
3421 }
3422
3423 if (!host->data) {
3424 struct mmc_command *data_cmd = host->data_cmd;
3425
3426 /*
3427 * The "data complete" interrupt is also used to
3428 * indicate that a busy state has ended. See comment
3429 * above in sdhci_cmd_irq().
3430 */
3431 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
3432 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
3433 host->data_cmd = NULL;
3434 data_cmd->error = -ETIMEDOUT;
3435 sdhci_err_stats_inc(host, CMD_TIMEOUT);
3436 __sdhci_finish_mrq(host, data_cmd->mrq);
3437 return;
3438 }
3439 if (intmask & SDHCI_INT_DATA_END) {
3440 host->data_cmd = NULL;
3441 /*
3442 * Some cards handle busy-end interrupt
3443 * before the command completed, so make
3444 * sure we do things in the proper order.
3445 */
3446 if (host->cmd == data_cmd)
3447 return;
3448
3449 __sdhci_finish_mrq(host, data_cmd->mrq);
3450 return;
3451 }
3452 }
3453
3454 /*
3455 * SDHCI recovers from errors by resetting the cmd and data
3456 * circuits. Until that is done, there very well might be more
3457 * interrupts, so ignore them in that case.
3458 */
3459 if (host->pending_reset)
3460 return;
3461
3462 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
3463 mmc_hostname(host->mmc), (unsigned)intmask);
3464 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
3465 sdhci_dumpregs(host);
3466
3467 return;
3468 }
3469
3470 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
3471 host->data->error = -ETIMEDOUT;
3472 sdhci_err_stats_inc(host, DAT_TIMEOUT);
3473 } else if (intmask & SDHCI_INT_DATA_END_BIT) {
3474 host->data->error = -EILSEQ;
3475 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
3476 sdhci_err_stats_inc(host, DAT_CRC);
3477 } else if ((intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_TUNING_ERROR)) &&
3478 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
3479 != MMC_BUS_TEST_R) {
3480 host->data->error = -EILSEQ;
3481 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
3482 sdhci_err_stats_inc(host, DAT_CRC);
3483 if (intmask & SDHCI_INT_TUNING_ERROR) {
3484 u16 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
3485
3486 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
3487 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
3488 }
3489 } else if (intmask & SDHCI_INT_ADMA_ERROR) {
3490 pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
3491 intmask);
3492 sdhci_adma_show_error(host);
3493 sdhci_err_stats_inc(host, ADMA);
3494 host->data->error = -EIO;
3495 if (host->ops->adma_workaround)
3496 host->ops->adma_workaround(host, intmask);
3497 }
3498
3499 if (host->data->error)
3500 sdhci_finish_data(host);
3501 else {
3502 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
3503 sdhci_transfer_pio(host);
3504
3505 /*
3506 * We currently don't do anything fancy with DMA
3507 * boundaries, but as we can't disable the feature
3508 * we need to at least restart the transfer.
3509 *
3510 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
3511 * should return a valid address to continue from, but as
3512 * some controllers are faulty, don't trust them.
3513 */
3514 if (intmask & SDHCI_INT_DMA_END) {
3515 dma_addr_t dmastart, dmanow;
3516
3517 dmastart = sdhci_sdma_address(host);
3518 dmanow = dmastart + host->data->bytes_xfered;
3519 /*
3520 * Force update to the next DMA block boundary.
3521 */
3522 dmanow = (dmanow &
3523 ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
3524 SDHCI_DEFAULT_BOUNDARY_SIZE;
3525 host->data->bytes_xfered = dmanow - dmastart;
3526 DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
3527 &dmastart, host->data->bytes_xfered, &dmanow);
3528 sdhci_set_sdma_addr(host, dmanow);
3529 }
3530
3531 if (intmask & SDHCI_INT_DATA_END) {
3532 if (host->cmd == host->data_cmd) {
3533 /*
3534 * Data managed to finish before the
3535 * command completed. Make sure we do
3536 * things in the proper order.
3537 */
3538 host->data_early = 1;
3539 } else {
3540 sdhci_finish_data(host);
3541 }
3542 }
3543 }
3544}
3545
3546static inline bool sdhci_defer_done(struct sdhci_host *host,
3547 struct mmc_request *mrq)
3548{
3549 struct mmc_data *data = mrq->data;
3550
3551 return host->pending_reset || host->always_defer_done ||
3552 ((host->flags & SDHCI_REQ_USE_DMA) && data &&
3553 data->host_cookie == COOKIE_MAPPED);
3554}
3555
3556static irqreturn_t sdhci_irq(int irq, void *dev_id)
3557{
3558 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0};
3559 irqreturn_t result = IRQ_NONE;
3560 struct sdhci_host *host = dev_id;
3561 u32 intmask, mask, unexpected = 0;
3562 int max_loops = 16;
3563 int i;
3564
3565 spin_lock(&host->lock);
3566
3567 if (host->runtime_suspended) {
3568 spin_unlock(&host->lock);
3569 return IRQ_NONE;
3570 }
3571
3572 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3573 if (!intmask || intmask == 0xffffffff) {
3574 result = IRQ_NONE;
3575 goto out;
3576 }
3577
3578 do {
3579 DBG("IRQ status 0x%08x\n", intmask);
3580
3581 if (host->ops->irq) {
3582 intmask = host->ops->irq(host, intmask);
3583 if (!intmask)
3584 goto cont;
3585 }
3586
3587 /* Clear selected interrupts. */
3588 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3589 SDHCI_INT_BUS_POWER);
3590 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3591
3592 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3593 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3594 SDHCI_CARD_PRESENT;
3595
3596 /*
3597 * There is a observation on i.mx esdhc. INSERT
3598 * bit will be immediately set again when it gets
3599 * cleared, if a card is inserted. We have to mask
3600 * the irq to prevent interrupt storm which will
3601 * freeze the system. And the REMOVE gets the
3602 * same situation.
3603 *
3604 * More testing are needed here to ensure it works
3605 * for other platforms though.
3606 */
3607 host->ier &= ~(SDHCI_INT_CARD_INSERT |
3608 SDHCI_INT_CARD_REMOVE);
3609 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
3610 SDHCI_INT_CARD_INSERT;
3611 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3612 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3613
3614 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
3615 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3616
3617 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
3618 SDHCI_INT_CARD_REMOVE);
3619 result = IRQ_WAKE_THREAD;
3620 }
3621
3622 if (intmask & SDHCI_INT_CMD_MASK)
3623 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
3624
3625 if (intmask & SDHCI_INT_DATA_MASK)
3626 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
3627
3628 if (intmask & SDHCI_INT_BUS_POWER)
3629 pr_err("%s: Card is consuming too much power!\n",
3630 mmc_hostname(host->mmc));
3631
3632 if (intmask & SDHCI_INT_RETUNE)
3633 mmc_retune_needed(host->mmc);
3634
3635 if ((intmask & SDHCI_INT_CARD_INT) &&
3636 (host->ier & SDHCI_INT_CARD_INT)) {
3637 sdhci_enable_sdio_irq_nolock(host, false);
3638 sdio_signal_irq(host->mmc);
3639 }
3640
3641 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
3642 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3643 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
3644 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
3645
3646 if (intmask) {
3647 unexpected |= intmask;
3648 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3649 }
3650cont:
3651 if (result == IRQ_NONE)
3652 result = IRQ_HANDLED;
3653
3654 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3655 } while (intmask && --max_loops);
3656
3657 /* Determine if mrqs can be completed immediately */
3658 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3659 struct mmc_request *mrq = host->mrqs_done[i];
3660
3661 if (!mrq)
3662 continue;
3663
3664 if (sdhci_defer_done(host, mrq)) {
3665 result = IRQ_WAKE_THREAD;
3666 } else {
3667 mrqs_done[i] = mrq;
3668 host->mrqs_done[i] = NULL;
3669 }
3670 }
3671out:
3672 if (host->deferred_cmd)
3673 result = IRQ_WAKE_THREAD;
3674
3675 spin_unlock(&host->lock);
3676
3677 /* Process mrqs ready for immediate completion */
3678 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3679 if (!mrqs_done[i])
3680 continue;
3681
3682 if (host->ops->request_done)
3683 host->ops->request_done(host, mrqs_done[i]);
3684 else
3685 mmc_request_done(host->mmc, mrqs_done[i]);
3686 }
3687
3688 if (unexpected) {
3689 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3690 mmc_hostname(host->mmc), unexpected);
3691 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
3692 sdhci_dumpregs(host);
3693 }
3694
3695 return result;
3696}
3697
3698irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
3699{
3700 struct sdhci_host *host = dev_id;
3701 struct mmc_command *cmd;
3702 unsigned long flags;
3703 u32 isr;
3704
3705 while (!sdhci_request_done(host))
3706 ;
3707
3708 spin_lock_irqsave(&host->lock, flags);
3709
3710 isr = host->thread_isr;
3711 host->thread_isr = 0;
3712
3713 cmd = host->deferred_cmd;
3714 if (cmd && !sdhci_send_command_retry(host, cmd, flags))
3715 sdhci_finish_mrq(host, cmd->mrq);
3716
3717 spin_unlock_irqrestore(&host->lock, flags);
3718
3719 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3720 struct mmc_host *mmc = host->mmc;
3721
3722 mmc->ops->card_event(mmc);
3723 mmc_detect_change(mmc, msecs_to_jiffies(200));
3724 }
3725
3726 return IRQ_HANDLED;
3727}
3728EXPORT_SYMBOL_GPL(sdhci_thread_irq);
3729
3730/*****************************************************************************\
3731 * *
3732 * Suspend/resume *
3733 * *
3734\*****************************************************************************/
3735
3736#ifdef CONFIG_PM
3737
3738static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
3739{
3740 return mmc_card_is_removable(host->mmc) &&
3741 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3742 !mmc_can_gpio_cd(host->mmc);
3743}
3744
3745/*
3746 * To enable wakeup events, the corresponding events have to be enabled in
3747 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
3748 * Table' in the SD Host Controller Standard Specification.
3749 * It is useless to restore SDHCI_INT_ENABLE state in
3750 * sdhci_disable_irq_wakeups() since it will be set by
3751 * sdhci_enable_card_detection() or sdhci_init().
3752 */
3753static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
3754{
3755 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
3756 SDHCI_WAKE_ON_INT;
3757 u32 irq_val = 0;
3758 u8 wake_val = 0;
3759 u8 val;
3760
3761 if (sdhci_cd_irq_can_wakeup(host)) {
3762 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
3763 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
3764 }
3765
3766 if (mmc_card_wake_sdio_irq(host->mmc)) {
3767 wake_val |= SDHCI_WAKE_ON_INT;
3768 irq_val |= SDHCI_INT_CARD_INT;
3769 }
3770
3771 if (!irq_val)
3772 return false;
3773
3774 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3775 val &= ~mask;
3776 val |= wake_val;
3777 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3778
3779 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
3780
3781 host->irq_wake_enabled = !enable_irq_wake(host->irq);
3782
3783 return host->irq_wake_enabled;
3784}
3785
3786static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3787{
3788 u8 val;
3789 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3790 | SDHCI_WAKE_ON_INT;
3791
3792 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3793 val &= ~mask;
3794 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3795
3796 disable_irq_wake(host->irq);
3797
3798 host->irq_wake_enabled = false;
3799}
3800
3801int sdhci_suspend_host(struct sdhci_host *host)
3802{
3803 sdhci_disable_card_detection(host);
3804
3805 mmc_retune_timer_stop(host->mmc);
3806
3807 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
3808 !sdhci_enable_irq_wakeups(host)) {
3809 host->ier = 0;
3810 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3811 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3812 free_irq(host->irq, host);
3813 }
3814
3815 return 0;
3816}
3817
3818EXPORT_SYMBOL_GPL(sdhci_suspend_host);
3819
3820int sdhci_resume_host(struct sdhci_host *host)
3821{
3822 struct mmc_host *mmc = host->mmc;
3823 int ret = 0;
3824
3825 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3826 if (host->ops->enable_dma)
3827 host->ops->enable_dma(host);
3828 }
3829
3830 if ((mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3831 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3832 /* Card keeps power but host controller does not */
3833 sdhci_init(host, 0);
3834 host->pwr = 0;
3835 host->clock = 0;
3836 host->reinit_uhs = true;
3837 mmc->ops->set_ios(mmc, &mmc->ios);
3838 } else {
3839 sdhci_init(host, (mmc->pm_flags & MMC_PM_KEEP_POWER));
3840 }
3841
3842 if (host->irq_wake_enabled) {
3843 sdhci_disable_irq_wakeups(host);
3844 } else {
3845 ret = request_threaded_irq(host->irq, sdhci_irq,
3846 sdhci_thread_irq, IRQF_SHARED,
3847 mmc_hostname(mmc), host);
3848 if (ret)
3849 return ret;
3850 }
3851
3852 sdhci_enable_card_detection(host);
3853
3854 return ret;
3855}
3856
3857EXPORT_SYMBOL_GPL(sdhci_resume_host);
3858
3859int sdhci_runtime_suspend_host(struct sdhci_host *host)
3860{
3861 unsigned long flags;
3862
3863 mmc_retune_timer_stop(host->mmc);
3864
3865 spin_lock_irqsave(&host->lock, flags);
3866 host->ier &= SDHCI_INT_CARD_INT;
3867 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3868 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3869 spin_unlock_irqrestore(&host->lock, flags);
3870
3871 synchronize_hardirq(host->irq);
3872
3873 spin_lock_irqsave(&host->lock, flags);
3874 host->runtime_suspended = true;
3875 spin_unlock_irqrestore(&host->lock, flags);
3876
3877 return 0;
3878}
3879EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3880
3881int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
3882{
3883 struct mmc_host *mmc = host->mmc;
3884 unsigned long flags;
3885 int host_flags = host->flags;
3886
3887 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3888 if (host->ops->enable_dma)
3889 host->ops->enable_dma(host);
3890 }
3891
3892 sdhci_init(host, soft_reset);
3893
3894 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3895 mmc->ios.power_mode != MMC_POWER_OFF) {
3896 /* Force clock and power re-program */
3897 host->pwr = 0;
3898 host->clock = 0;
3899 host->reinit_uhs = true;
3900 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3901 mmc->ops->set_ios(mmc, &mmc->ios);
3902
3903 if ((host_flags & SDHCI_PV_ENABLED) &&
3904 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3905 spin_lock_irqsave(&host->lock, flags);
3906 sdhci_enable_preset_value(host, true);
3907 spin_unlock_irqrestore(&host->lock, flags);
3908 }
3909
3910 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3911 mmc->ops->hs400_enhanced_strobe)
3912 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3913 }
3914
3915 spin_lock_irqsave(&host->lock, flags);
3916
3917 host->runtime_suspended = false;
3918
3919 /* Enable SDIO IRQ */
3920 if (sdio_irq_claimed(mmc))
3921 sdhci_enable_sdio_irq_nolock(host, true);
3922
3923 /* Enable Card Detection */
3924 sdhci_enable_card_detection(host);
3925
3926 spin_unlock_irqrestore(&host->lock, flags);
3927
3928 return 0;
3929}
3930EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3931
3932#endif /* CONFIG_PM */
3933
3934/*****************************************************************************\
3935 * *
3936 * Command Queue Engine (CQE) helpers *
3937 * *
3938\*****************************************************************************/
3939
3940void sdhci_cqe_enable(struct mmc_host *mmc)
3941{
3942 struct sdhci_host *host = mmc_priv(mmc);
3943 unsigned long flags;
3944 u8 ctrl;
3945
3946 spin_lock_irqsave(&host->lock, flags);
3947
3948 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3949 ctrl &= ~SDHCI_CTRL_DMA_MASK;
3950 /*
3951 * Host from V4.10 supports ADMA3 DMA type.
3952 * ADMA3 performs integrated descriptor which is more suitable
3953 * for cmd queuing to fetch both command and transfer descriptors.
3954 */
3955 if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
3956 ctrl |= SDHCI_CTRL_ADMA3;
3957 else if (host->flags & SDHCI_USE_64_BIT_DMA)
3958 ctrl |= SDHCI_CTRL_ADMA64;
3959 else
3960 ctrl |= SDHCI_CTRL_ADMA32;
3961 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3962
3963 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3964 SDHCI_BLOCK_SIZE);
3965
3966 /* Set maximum timeout */
3967 sdhci_set_timeout(host, NULL);
3968
3969 host->ier = host->cqe_ier;
3970
3971 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3972 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3973
3974 host->cqe_on = true;
3975
3976 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3977 mmc_hostname(mmc), host->ier,
3978 sdhci_readl(host, SDHCI_INT_STATUS));
3979
3980 spin_unlock_irqrestore(&host->lock, flags);
3981}
3982EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3983
3984void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3985{
3986 struct sdhci_host *host = mmc_priv(mmc);
3987 unsigned long flags;
3988
3989 spin_lock_irqsave(&host->lock, flags);
3990
3991 sdhci_set_default_irqs(host);
3992
3993 host->cqe_on = false;
3994
3995 if (recovery)
3996 sdhci_reset_for(host, CQE_RECOVERY);
3997
3998 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3999 mmc_hostname(mmc), host->ier,
4000 sdhci_readl(host, SDHCI_INT_STATUS));
4001
4002 spin_unlock_irqrestore(&host->lock, flags);
4003}
4004EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
4005
4006bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
4007 int *data_error)
4008{
4009 u32 mask;
4010
4011 if (!host->cqe_on)
4012 return false;
4013
4014 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC)) {
4015 *cmd_error = -EILSEQ;
4016 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
4017 sdhci_err_stats_inc(host, CMD_CRC);
4018 } else if (intmask & SDHCI_INT_TIMEOUT) {
4019 *cmd_error = -ETIMEDOUT;
4020 sdhci_err_stats_inc(host, CMD_TIMEOUT);
4021 } else
4022 *cmd_error = 0;
4023
4024 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC | SDHCI_INT_TUNING_ERROR)) {
4025 *data_error = -EILSEQ;
4026 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
4027 sdhci_err_stats_inc(host, DAT_CRC);
4028 } else if (intmask & SDHCI_INT_DATA_TIMEOUT) {
4029 *data_error = -ETIMEDOUT;
4030 sdhci_err_stats_inc(host, DAT_TIMEOUT);
4031 } else if (intmask & SDHCI_INT_ADMA_ERROR) {
4032 *data_error = -EIO;
4033 sdhci_err_stats_inc(host, ADMA);
4034 } else
4035 *data_error = 0;
4036
4037 /* Clear selected interrupts. */
4038 mask = intmask & host->cqe_ier;
4039 sdhci_writel(host, mask, SDHCI_INT_STATUS);
4040
4041 if (intmask & SDHCI_INT_BUS_POWER)
4042 pr_err("%s: Card is consuming too much power!\n",
4043 mmc_hostname(host->mmc));
4044
4045 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
4046 if (intmask) {
4047 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
4048 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
4049 mmc_hostname(host->mmc), intmask);
4050 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
4051 sdhci_dumpregs(host);
4052 }
4053
4054 return true;
4055}
4056EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
4057
4058/*****************************************************************************\
4059 * *
4060 * Device allocation/registration *
4061 * *
4062\*****************************************************************************/
4063
4064struct sdhci_host *sdhci_alloc_host(struct device *dev,
4065 size_t priv_size)
4066{
4067 struct mmc_host *mmc;
4068 struct sdhci_host *host;
4069
4070 WARN_ON(dev == NULL);
4071
4072 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
4073 if (!mmc)
4074 return ERR_PTR(-ENOMEM);
4075
4076 host = mmc_priv(mmc);
4077 host->mmc = mmc;
4078 host->mmc_host_ops = sdhci_ops;
4079 mmc->ops = &host->mmc_host_ops;
4080
4081 host->flags = SDHCI_SIGNALING_330;
4082
4083 host->cqe_ier = SDHCI_CQE_INT_MASK;
4084 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
4085
4086 host->tuning_delay = -1;
4087 host->tuning_loop_count = MAX_TUNING_LOOP;
4088
4089 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
4090
4091 /*
4092 * The DMA table descriptor count is calculated as the maximum
4093 * number of segments times 2, to allow for an alignment
4094 * descriptor for each segment, plus 1 for a nop end descriptor.
4095 */
4096 host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
4097 host->max_adma = 65536;
4098
4099 host->max_timeout_count = 0xE;
4100
4101 host->complete_work_fn = sdhci_complete_work;
4102 host->thread_irq_fn = sdhci_thread_irq;
4103
4104 return host;
4105}
4106
4107EXPORT_SYMBOL_GPL(sdhci_alloc_host);
4108
4109static int sdhci_set_dma_mask(struct sdhci_host *host)
4110{
4111 struct mmc_host *mmc = host->mmc;
4112 struct device *dev = mmc_dev(mmc);
4113 int ret = -EINVAL;
4114
4115 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
4116 host->flags &= ~SDHCI_USE_64_BIT_DMA;
4117
4118 /* Try 64-bit mask if hardware is capable of it */
4119 if (host->flags & SDHCI_USE_64_BIT_DMA) {
4120 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
4121 if (ret) {
4122 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
4123 mmc_hostname(mmc));
4124 host->flags &= ~SDHCI_USE_64_BIT_DMA;
4125 }
4126 }
4127
4128 /* 32-bit mask as default & fallback */
4129 if (ret) {
4130 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
4131 if (ret)
4132 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
4133 mmc_hostname(mmc));
4134 }
4135
4136 return ret;
4137}
4138
4139void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
4140 const u32 *caps, const u32 *caps1)
4141{
4142 u16 v;
4143 u64 dt_caps_mask = 0;
4144 u64 dt_caps = 0;
4145
4146 if (host->read_caps)
4147 return;
4148
4149 host->read_caps = true;
4150
4151 if (debug_quirks)
4152 host->quirks = debug_quirks;
4153
4154 if (debug_quirks2)
4155 host->quirks2 = debug_quirks2;
4156
4157 sdhci_reset_for_all(host);
4158
4159 if (host->v4_mode)
4160 sdhci_do_enable_v4_mode(host);
4161
4162 device_property_read_u64(mmc_dev(host->mmc),
4163 "sdhci-caps-mask", &dt_caps_mask);
4164 device_property_read_u64(mmc_dev(host->mmc),
4165 "sdhci-caps", &dt_caps);
4166
4167 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
4168 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
4169
4170 if (caps) {
4171 host->caps = *caps;
4172 } else {
4173 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
4174 host->caps &= ~lower_32_bits(dt_caps_mask);
4175 host->caps |= lower_32_bits(dt_caps);
4176 }
4177
4178 if (host->version < SDHCI_SPEC_300)
4179 return;
4180
4181 if (caps1) {
4182 host->caps1 = *caps1;
4183 } else {
4184 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
4185 host->caps1 &= ~upper_32_bits(dt_caps_mask);
4186 host->caps1 |= upper_32_bits(dt_caps);
4187 }
4188}
4189EXPORT_SYMBOL_GPL(__sdhci_read_caps);
4190
4191static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
4192{
4193 struct mmc_host *mmc = host->mmc;
4194 unsigned int max_blocks;
4195 unsigned int bounce_size;
4196 int ret;
4197
4198 /*
4199 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
4200 * has diminishing returns, this is probably because SD/MMC
4201 * cards are usually optimized to handle this size of requests.
4202 */
4203 bounce_size = SZ_64K;
4204 /*
4205 * Adjust downwards to maximum request size if this is less
4206 * than our segment size, else hammer down the maximum
4207 * request size to the maximum buffer size.
4208 */
4209 if (mmc->max_req_size < bounce_size)
4210 bounce_size = mmc->max_req_size;
4211 max_blocks = bounce_size / 512;
4212
4213 /*
4214 * When we just support one segment, we can get significant
4215 * speedups by the help of a bounce buffer to group scattered
4216 * reads/writes together.
4217 */
4218 host->bounce_buffer = devm_kmalloc(mmc_dev(mmc),
4219 bounce_size,
4220 GFP_KERNEL);
4221 if (!host->bounce_buffer) {
4222 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
4223 mmc_hostname(mmc),
4224 bounce_size);
4225 /*
4226 * Exiting with zero here makes sure we proceed with
4227 * mmc->max_segs == 1.
4228 */
4229 return;
4230 }
4231
4232 host->bounce_addr = dma_map_single(mmc_dev(mmc),
4233 host->bounce_buffer,
4234 bounce_size,
4235 DMA_BIDIRECTIONAL);
4236 ret = dma_mapping_error(mmc_dev(mmc), host->bounce_addr);
4237 if (ret) {
4238 devm_kfree(mmc_dev(mmc), host->bounce_buffer);
4239 host->bounce_buffer = NULL;
4240 /* Again fall back to max_segs == 1 */
4241 return;
4242 }
4243
4244 host->bounce_buffer_size = bounce_size;
4245
4246 /* Lie about this since we're bouncing */
4247 mmc->max_segs = max_blocks;
4248 mmc->max_seg_size = bounce_size;
4249 mmc->max_req_size = bounce_size;
4250
4251 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
4252 mmc_hostname(mmc), max_blocks, bounce_size);
4253}
4254
4255static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
4256{
4257 /*
4258 * According to SD Host Controller spec v4.10, bit[27] added from
4259 * version 4.10 in Capabilities Register is used as 64-bit System
4260 * Address support for V4 mode.
4261 */
4262 if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
4263 return host->caps & SDHCI_CAN_64BIT_V4;
4264
4265 return host->caps & SDHCI_CAN_64BIT;
4266}
4267
4268int sdhci_setup_host(struct sdhci_host *host)
4269{
4270 struct mmc_host *mmc;
4271 u32 max_current_caps;
4272 unsigned int ocr_avail;
4273 unsigned int override_timeout_clk;
4274 u32 max_clk;
4275 int ret = 0;
4276 bool enable_vqmmc = false;
4277
4278 WARN_ON(host == NULL);
4279 if (host == NULL)
4280 return -EINVAL;
4281
4282 mmc = host->mmc;
4283
4284 /*
4285 * If there are external regulators, get them. Note this must be done
4286 * early before resetting the host and reading the capabilities so that
4287 * the host can take the appropriate action if regulators are not
4288 * available.
4289 */
4290 if (!mmc->supply.vqmmc) {
4291 ret = mmc_regulator_get_supply(mmc);
4292 if (ret)
4293 return ret;
4294 enable_vqmmc = true;
4295 }
4296
4297 DBG("Version: 0x%08x | Present: 0x%08x\n",
4298 sdhci_readw(host, SDHCI_HOST_VERSION),
4299 sdhci_readl(host, SDHCI_PRESENT_STATE));
4300 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
4301 sdhci_readl(host, SDHCI_CAPABILITIES),
4302 sdhci_readl(host, SDHCI_CAPABILITIES_1));
4303
4304 sdhci_read_caps(host);
4305
4306 override_timeout_clk = host->timeout_clk;
4307
4308 if (host->version > SDHCI_SPEC_420) {
4309 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
4310 mmc_hostname(mmc), host->version);
4311 }
4312
4313 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
4314 host->flags |= SDHCI_USE_SDMA;
4315 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
4316 DBG("Controller doesn't have SDMA capability\n");
4317 else
4318 host->flags |= SDHCI_USE_SDMA;
4319
4320 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
4321 (host->flags & SDHCI_USE_SDMA)) {
4322 DBG("Disabling DMA as it is marked broken\n");
4323 host->flags &= ~SDHCI_USE_SDMA;
4324 }
4325
4326 if ((host->version >= SDHCI_SPEC_200) &&
4327 (host->caps & SDHCI_CAN_DO_ADMA2))
4328 host->flags |= SDHCI_USE_ADMA;
4329
4330 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
4331 (host->flags & SDHCI_USE_ADMA)) {
4332 DBG("Disabling ADMA as it is marked broken\n");
4333 host->flags &= ~SDHCI_USE_ADMA;
4334 }
4335
4336 if (sdhci_can_64bit_dma(host))
4337 host->flags |= SDHCI_USE_64_BIT_DMA;
4338
4339 if (host->use_external_dma) {
4340 ret = sdhci_external_dma_init(host);
4341 if (ret == -EPROBE_DEFER)
4342 goto unreg;
4343 /*
4344 * Fall back to use the DMA/PIO integrated in standard SDHCI
4345 * instead of external DMA devices.
4346 */
4347 else if (ret)
4348 sdhci_switch_external_dma(host, false);
4349 /* Disable internal DMA sources */
4350 else
4351 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4352 }
4353
4354 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
4355 if (host->ops->set_dma_mask)
4356 ret = host->ops->set_dma_mask(host);
4357 else
4358 ret = sdhci_set_dma_mask(host);
4359
4360 if (!ret && host->ops->enable_dma)
4361 ret = host->ops->enable_dma(host);
4362
4363 if (ret) {
4364 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
4365 mmc_hostname(mmc));
4366 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4367
4368 ret = 0;
4369 }
4370 }
4371
4372 /* SDMA does not support 64-bit DMA if v4 mode not set */
4373 if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
4374 host->flags &= ~SDHCI_USE_SDMA;
4375
4376 if (host->flags & SDHCI_USE_ADMA) {
4377 dma_addr_t dma;
4378 void *buf;
4379
4380 if (!(host->flags & SDHCI_USE_64_BIT_DMA))
4381 host->alloc_desc_sz = SDHCI_ADMA2_32_DESC_SZ;
4382 else if (!host->alloc_desc_sz)
4383 host->alloc_desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
4384
4385 host->desc_sz = host->alloc_desc_sz;
4386 host->adma_table_sz = host->adma_table_cnt * host->desc_sz;
4387
4388 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
4389 /*
4390 * Use zalloc to zero the reserved high 32-bits of 128-bit
4391 * descriptors so that they never need to be written.
4392 */
4393 buf = dma_alloc_coherent(mmc_dev(mmc),
4394 host->align_buffer_sz + host->adma_table_sz,
4395 &dma, GFP_KERNEL);
4396 if (!buf) {
4397 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
4398 mmc_hostname(mmc));
4399 host->flags &= ~SDHCI_USE_ADMA;
4400 } else if ((dma + host->align_buffer_sz) &
4401 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
4402 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
4403 mmc_hostname(mmc));
4404 host->flags &= ~SDHCI_USE_ADMA;
4405 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4406 host->adma_table_sz, buf, dma);
4407 } else {
4408 host->align_buffer = buf;
4409 host->align_addr = dma;
4410
4411 host->adma_table = buf + host->align_buffer_sz;
4412 host->adma_addr = dma + host->align_buffer_sz;
4413 }
4414 }
4415
4416 /*
4417 * If we use DMA, then it's up to the caller to set the DMA
4418 * mask, but PIO does not need the hw shim so we set a new
4419 * mask here in that case.
4420 */
4421 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
4422 host->dma_mask = DMA_BIT_MASK(64);
4423 mmc_dev(mmc)->dma_mask = &host->dma_mask;
4424 }
4425
4426 if (host->version >= SDHCI_SPEC_300)
4427 host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps);
4428 else
4429 host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps);
4430
4431 host->max_clk *= 1000000;
4432 if (host->max_clk == 0 || host->quirks &
4433 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4434 if (!host->ops->get_max_clock) {
4435 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
4436 mmc_hostname(mmc));
4437 ret = -ENODEV;
4438 goto undma;
4439 }
4440 host->max_clk = host->ops->get_max_clock(host);
4441 }
4442
4443 /*
4444 * In case of Host Controller v3.00, find out whether clock
4445 * multiplier is supported.
4446 */
4447 host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1);
4448
4449 /*
4450 * In case the value in Clock Multiplier is 0, then programmable
4451 * clock mode is not supported, otherwise the actual clock
4452 * multiplier is one more than the value of Clock Multiplier
4453 * in the Capabilities Register.
4454 */
4455 if (host->clk_mul)
4456 host->clk_mul += 1;
4457
4458 /*
4459 * Set host parameters.
4460 */
4461 max_clk = host->max_clk;
4462
4463 if (host->ops->get_min_clock)
4464 mmc->f_min = host->ops->get_min_clock(host);
4465 else if (host->version >= SDHCI_SPEC_300) {
4466 if (host->clk_mul)
4467 max_clk = host->max_clk * host->clk_mul;
4468 /*
4469 * Divided Clock Mode minimum clock rate is always less than
4470 * Programmable Clock Mode minimum clock rate.
4471 */
4472 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
4473 } else
4474 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
4475
4476 if (!mmc->f_max || mmc->f_max > max_clk)
4477 mmc->f_max = max_clk;
4478
4479 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4480 host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps);
4481
4482 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
4483 host->timeout_clk *= 1000;
4484
4485 if (host->timeout_clk == 0) {
4486 if (!host->ops->get_timeout_clock) {
4487 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
4488 mmc_hostname(mmc));
4489 ret = -ENODEV;
4490 goto undma;
4491 }
4492
4493 host->timeout_clk =
4494 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
4495 1000);
4496 }
4497
4498 if (override_timeout_clk)
4499 host->timeout_clk = override_timeout_clk;
4500
4501 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
4502 host->ops->get_max_timeout_count(host) : 1 << 27;
4503 mmc->max_busy_timeout /= host->timeout_clk;
4504 }
4505
4506 if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
4507 !host->ops->get_max_timeout_count)
4508 mmc->max_busy_timeout = 0;
4509
4510 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_CMD23;
4511 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
4512
4513 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
4514 host->flags |= SDHCI_AUTO_CMD12;
4515
4516 /*
4517 * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
4518 * For v4 mode, SDMA may use Auto-CMD23 as well.
4519 */
4520 if ((host->version >= SDHCI_SPEC_300) &&
4521 ((host->flags & SDHCI_USE_ADMA) ||
4522 !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
4523 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
4524 host->flags |= SDHCI_AUTO_CMD23;
4525 DBG("Auto-CMD23 available\n");
4526 } else {
4527 DBG("Auto-CMD23 unavailable\n");
4528 }
4529
4530 /*
4531 * A controller may support 8-bit width, but the board itself
4532 * might not have the pins brought out. Boards that support
4533 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
4534 * their platform code before calling sdhci_add_host(), and we
4535 * won't assume 8-bit width for hosts without that CAP.
4536 */
4537 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
4538 mmc->caps |= MMC_CAP_4_BIT_DATA;
4539
4540 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
4541 mmc->caps &= ~MMC_CAP_CMD23;
4542
4543 if (host->caps & SDHCI_CAN_DO_HISPD)
4544 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
4545
4546 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4547 mmc_card_is_removable(mmc) &&
4548 mmc_gpio_get_cd(mmc) < 0)
4549 mmc->caps |= MMC_CAP_NEEDS_POLL;
4550
4551 if (!IS_ERR(mmc->supply.vqmmc)) {
4552 if (enable_vqmmc) {
4553 ret = regulator_enable(mmc->supply.vqmmc);
4554 host->sdhci_core_to_disable_vqmmc = !ret;
4555 }
4556
4557 /* If vqmmc provides no 1.8V signalling, then there's no UHS */
4558 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
4559 1950000))
4560 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
4561 SDHCI_SUPPORT_SDR50 |
4562 SDHCI_SUPPORT_DDR50);
4563
4564 /* In eMMC case vqmmc might be a fixed 1.8V regulator */
4565 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
4566 3600000))
4567 host->flags &= ~SDHCI_SIGNALING_330;
4568
4569 if (ret) {
4570 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
4571 mmc_hostname(mmc), ret);
4572 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
4573 }
4574
4575 }
4576
4577 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
4578 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4579 SDHCI_SUPPORT_DDR50);
4580 /*
4581 * The SDHCI controller in a SoC might support HS200/HS400
4582 * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
4583 * but if the board is modeled such that the IO lines are not
4584 * connected to 1.8v then HS200/HS400 cannot be supported.
4585 * Disable HS200/HS400 if the board does not have 1.8v connected
4586 * to the IO lines. (Applicable for other modes in 1.8v)
4587 */
4588 mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
4589 mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
4590 }
4591
4592 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
4593 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4594 SDHCI_SUPPORT_DDR50))
4595 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
4596
4597 /* SDR104 supports also implies SDR50 support */
4598 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
4599 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
4600 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
4601 * field can be promoted to support HS200.
4602 */
4603 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
4604 mmc->caps2 |= MMC_CAP2_HS200;
4605 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
4606 mmc->caps |= MMC_CAP_UHS_SDR50;
4607 }
4608
4609 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
4610 (host->caps1 & SDHCI_SUPPORT_HS400))
4611 mmc->caps2 |= MMC_CAP2_HS400;
4612
4613 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
4614 (IS_ERR(mmc->supply.vqmmc) ||
4615 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
4616 1300000)))
4617 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
4618
4619 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
4620 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
4621 mmc->caps |= MMC_CAP_UHS_DDR50;
4622
4623 /* Does the host need tuning for SDR50? */
4624 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
4625 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
4626
4627 /* Driver Type(s) (A, C, D) supported by the host */
4628 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
4629 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
4630 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
4631 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
4632 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
4633 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
4634
4635 /* Initial value for re-tuning timer count */
4636 host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK,
4637 host->caps1);
4638
4639 /*
4640 * In case Re-tuning Timer is not disabled, the actual value of
4641 * re-tuning timer will be 2 ^ (n - 1).
4642 */
4643 if (host->tuning_count)
4644 host->tuning_count = 1 << (host->tuning_count - 1);
4645
4646 /* Re-tuning mode supported by the Host Controller */
4647 host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1);
4648
4649 ocr_avail = 0;
4650
4651 /*
4652 * According to SD Host Controller spec v3.00, if the Host System
4653 * can afford more than 150mA, Host Driver should set XPC to 1. Also
4654 * the value is meaningful only if Voltage Support in the Capabilities
4655 * register is set. The actual current value is 4 times the register
4656 * value.
4657 */
4658 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
4659 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
4660 int curr = regulator_get_current_limit(mmc->supply.vmmc);
4661 if (curr > 0) {
4662
4663 /* convert to SDHCI_MAX_CURRENT format */
4664 curr = curr/1000; /* convert to mA */
4665 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
4666
4667 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
4668 max_current_caps =
4669 FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, curr) |
4670 FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, curr) |
4671 FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, curr);
4672 }
4673 }
4674
4675 if (host->caps & SDHCI_CAN_VDD_330) {
4676 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
4677
4678 mmc->max_current_330 = FIELD_GET(SDHCI_MAX_CURRENT_330_MASK,
4679 max_current_caps) *
4680 SDHCI_MAX_CURRENT_MULTIPLIER;
4681 }
4682 if (host->caps & SDHCI_CAN_VDD_300) {
4683 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
4684
4685 mmc->max_current_300 = FIELD_GET(SDHCI_MAX_CURRENT_300_MASK,
4686 max_current_caps) *
4687 SDHCI_MAX_CURRENT_MULTIPLIER;
4688 }
4689 if (host->caps & SDHCI_CAN_VDD_180) {
4690 ocr_avail |= MMC_VDD_165_195;
4691
4692 mmc->max_current_180 = FIELD_GET(SDHCI_MAX_CURRENT_180_MASK,
4693 max_current_caps) *
4694 SDHCI_MAX_CURRENT_MULTIPLIER;
4695 }
4696
4697 /* If OCR set by host, use it instead. */
4698 if (host->ocr_mask)
4699 ocr_avail = host->ocr_mask;
4700
4701 /* If OCR set by external regulators, give it highest prio. */
4702 if (mmc->ocr_avail)
4703 ocr_avail = mmc->ocr_avail;
4704
4705 mmc->ocr_avail = ocr_avail;
4706 mmc->ocr_avail_sdio = ocr_avail;
4707 if (host->ocr_avail_sdio)
4708 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
4709 mmc->ocr_avail_sd = ocr_avail;
4710 if (host->ocr_avail_sd)
4711 mmc->ocr_avail_sd &= host->ocr_avail_sd;
4712 else /* normal SD controllers don't support 1.8V */
4713 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
4714 mmc->ocr_avail_mmc = ocr_avail;
4715 if (host->ocr_avail_mmc)
4716 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
4717
4718 if (mmc->ocr_avail == 0) {
4719 pr_err("%s: Hardware doesn't report any support voltages.\n",
4720 mmc_hostname(mmc));
4721 ret = -ENODEV;
4722 goto unreg;
4723 }
4724
4725 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
4726 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
4727 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
4728 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
4729 host->flags |= SDHCI_SIGNALING_180;
4730
4731 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
4732 host->flags |= SDHCI_SIGNALING_120;
4733
4734 spin_lock_init(&host->lock);
4735
4736 /*
4737 * Maximum number of sectors in one transfer. Limited by SDMA boundary
4738 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
4739 * is less anyway.
4740 */
4741 mmc->max_req_size = 524288;
4742
4743 /*
4744 * Maximum number of segments. Depends on if the hardware
4745 * can do scatter/gather or not.
4746 */
4747 if (host->flags & SDHCI_USE_ADMA) {
4748 mmc->max_segs = SDHCI_MAX_SEGS;
4749 } else if (host->flags & SDHCI_USE_SDMA) {
4750 mmc->max_segs = 1;
4751 mmc->max_req_size = min_t(size_t, mmc->max_req_size,
4752 dma_max_mapping_size(mmc_dev(mmc)));
4753 } else { /* PIO */
4754 mmc->max_segs = SDHCI_MAX_SEGS;
4755 }
4756
4757 /*
4758 * Maximum segment size. Could be one segment with the maximum number
4759 * of bytes. When doing hardware scatter/gather, each entry cannot
4760 * be larger than 64 KiB though.
4761 */
4762 if (host->flags & SDHCI_USE_ADMA) {
4763 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) {
4764 host->max_adma = 65532; /* 32-bit alignment */
4765 mmc->max_seg_size = 65535;
4766 /*
4767 * sdhci_adma_table_pre() expects to define 1 DMA
4768 * descriptor per segment, so the maximum segment size
4769 * is set accordingly. SDHCI allows up to 64KiB per DMA
4770 * descriptor (16-bit field), but some controllers do
4771 * not support "zero means 65536" reducing the maximum
4772 * for them to 65535. That is a problem if PAGE_SIZE is
4773 * 64KiB because the block layer does not support
4774 * max_seg_size < PAGE_SIZE, however
4775 * sdhci_adma_table_pre() has a workaround to handle
4776 * that case, and split the descriptor. Refer also
4777 * comment in sdhci_adma_table_pre().
4778 */
4779 if (mmc->max_seg_size < PAGE_SIZE)
4780 mmc->max_seg_size = PAGE_SIZE;
4781 } else {
4782 mmc->max_seg_size = 65536;
4783 }
4784 } else {
4785 mmc->max_seg_size = mmc->max_req_size;
4786 }
4787
4788 /*
4789 * Maximum block size. This varies from controller to controller and
4790 * is specified in the capabilities register.
4791 */
4792 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4793 mmc->max_blk_size = 2;
4794 } else {
4795 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
4796 SDHCI_MAX_BLOCK_SHIFT;
4797 if (mmc->max_blk_size >= 3) {
4798 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
4799 mmc_hostname(mmc));
4800 mmc->max_blk_size = 0;
4801 }
4802 }
4803
4804 mmc->max_blk_size = 512 << mmc->max_blk_size;
4805
4806 /*
4807 * Maximum block count.
4808 */
4809 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
4810
4811 if (mmc->max_segs == 1)
4812 /* This may alter mmc->*_blk_* parameters */
4813 sdhci_allocate_bounce_buffer(host);
4814
4815 return 0;
4816
4817unreg:
4818 if (host->sdhci_core_to_disable_vqmmc)
4819 regulator_disable(mmc->supply.vqmmc);
4820undma:
4821 if (host->align_buffer)
4822 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4823 host->adma_table_sz, host->align_buffer,
4824 host->align_addr);
4825 host->adma_table = NULL;
4826 host->align_buffer = NULL;
4827
4828 return ret;
4829}
4830EXPORT_SYMBOL_GPL(sdhci_setup_host);
4831
4832void sdhci_cleanup_host(struct sdhci_host *host)
4833{
4834 struct mmc_host *mmc = host->mmc;
4835
4836 if (host->sdhci_core_to_disable_vqmmc)
4837 regulator_disable(mmc->supply.vqmmc);
4838
4839 if (host->align_buffer)
4840 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4841 host->adma_table_sz, host->align_buffer,
4842 host->align_addr);
4843
4844 if (host->use_external_dma)
4845 sdhci_external_dma_release(host);
4846
4847 host->adma_table = NULL;
4848 host->align_buffer = NULL;
4849}
4850EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
4851
4852int __sdhci_add_host(struct sdhci_host *host)
4853{
4854 unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI;
4855 struct mmc_host *mmc = host->mmc;
4856 int ret;
4857
4858 if ((mmc->caps2 & MMC_CAP2_CQE) &&
4859 (host->quirks & SDHCI_QUIRK_BROKEN_CQE)) {
4860 mmc->caps2 &= ~MMC_CAP2_CQE;
4861 mmc->cqe_ops = NULL;
4862 }
4863
4864 host->complete_wq = alloc_workqueue("sdhci", flags, 0);
4865 if (!host->complete_wq)
4866 return -ENOMEM;
4867
4868 INIT_WORK(&host->complete_work, host->complete_work_fn);
4869
4870 timer_setup(&host->timer, sdhci_timeout_timer, 0);
4871 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
4872
4873 init_waitqueue_head(&host->buf_ready_int);
4874
4875 sdhci_init(host, 0);
4876
4877 ret = request_threaded_irq(host->irq, sdhci_irq, host->thread_irq_fn,
4878 IRQF_SHARED, mmc_hostname(mmc), host);
4879 if (ret) {
4880 pr_err("%s: Failed to request IRQ %d: %d\n",
4881 mmc_hostname(mmc), host->irq, ret);
4882 goto unwq;
4883 }
4884
4885 ret = sdhci_led_register(host);
4886 if (ret) {
4887 pr_err("%s: Failed to register LED device: %d\n",
4888 mmc_hostname(mmc), ret);
4889 goto unirq;
4890 }
4891
4892 ret = mmc_add_host(mmc);
4893 if (ret)
4894 goto unled;
4895
4896 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
4897 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
4898 host->use_external_dma ? "External DMA" :
4899 (host->flags & SDHCI_USE_ADMA) ?
4900 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
4901 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4902
4903 sdhci_enable_card_detection(host);
4904
4905 return 0;
4906
4907unled:
4908 sdhci_led_unregister(host);
4909unirq:
4910 sdhci_reset_for_all(host);
4911 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4912 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4913 free_irq(host->irq, host);
4914unwq:
4915 destroy_workqueue(host->complete_wq);
4916
4917 return ret;
4918}
4919EXPORT_SYMBOL_GPL(__sdhci_add_host);
4920
4921int sdhci_add_host(struct sdhci_host *host)
4922{
4923 int ret;
4924
4925 ret = sdhci_setup_host(host);
4926 if (ret)
4927 return ret;
4928
4929 ret = __sdhci_add_host(host);
4930 if (ret)
4931 goto cleanup;
4932
4933 return 0;
4934
4935cleanup:
4936 sdhci_cleanup_host(host);
4937
4938 return ret;
4939}
4940EXPORT_SYMBOL_GPL(sdhci_add_host);
4941
4942void sdhci_remove_host(struct sdhci_host *host, int dead)
4943{
4944 struct mmc_host *mmc = host->mmc;
4945 unsigned long flags;
4946
4947 if (dead) {
4948 spin_lock_irqsave(&host->lock, flags);
4949
4950 host->flags |= SDHCI_DEVICE_DEAD;
4951
4952 if (sdhci_has_requests(host)) {
4953 pr_err("%s: Controller removed during "
4954 " transfer!\n", mmc_hostname(mmc));
4955 sdhci_error_out_mrqs(host, -ENOMEDIUM);
4956 }
4957
4958 spin_unlock_irqrestore(&host->lock, flags);
4959 }
4960
4961 sdhci_disable_card_detection(host);
4962
4963 mmc_remove_host(mmc);
4964
4965 sdhci_led_unregister(host);
4966
4967 if (!dead)
4968 sdhci_reset_for_all(host);
4969
4970 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4971 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4972 free_irq(host->irq, host);
4973
4974 del_timer_sync(&host->timer);
4975 del_timer_sync(&host->data_timer);
4976
4977 destroy_workqueue(host->complete_wq);
4978
4979 if (host->sdhci_core_to_disable_vqmmc)
4980 regulator_disable(mmc->supply.vqmmc);
4981
4982 if (host->align_buffer)
4983 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4984 host->adma_table_sz, host->align_buffer,
4985 host->align_addr);
4986
4987 if (host->use_external_dma)
4988 sdhci_external_dma_release(host);
4989
4990 host->adma_table = NULL;
4991 host->align_buffer = NULL;
4992}
4993
4994EXPORT_SYMBOL_GPL(sdhci_remove_host);
4995
4996void sdhci_free_host(struct sdhci_host *host)
4997{
4998 mmc_free_host(host->mmc);
4999}
5000
5001EXPORT_SYMBOL_GPL(sdhci_free_host);
5002
5003/*****************************************************************************\
5004 * *
5005 * Driver init/exit *
5006 * *
5007\*****************************************************************************/
5008
5009static int __init sdhci_drv_init(void)
5010{
5011 pr_info(DRIVER_NAME
5012 ": Secure Digital Host Controller Interface driver\n");
5013 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
5014
5015 return 0;
5016}
5017
5018static void __exit sdhci_drv_exit(void)
5019{
5020}
5021
5022module_init(sdhci_drv_init);
5023module_exit(sdhci_drv_exit);
5024
5025module_param(debug_quirks, uint, 0444);
5026module_param(debug_quirks2, uint, 0444);
5027
5028MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
5029MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
5030MODULE_LICENSE("GPL");
5031
5032MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
5033MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");