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1// SPDX-License-Identifier: GPL-2.0-only
2#include <linux/extable.h>
3#include <linux/uaccess.h>
4#include <linux/sched/debug.h>
5#include <linux/bitfield.h>
6#include <xen/xen.h>
7
8#include <asm/fpu/api.h>
9#include <asm/sev.h>
10#include <asm/traps.h>
11#include <asm/kdebug.h>
12#include <asm/insn-eval.h>
13#include <asm/sgx.h>
14
15static inline unsigned long *pt_regs_nr(struct pt_regs *regs, int nr)
16{
17 int reg_offset = pt_regs_offset(regs, nr);
18 static unsigned long __dummy;
19
20 if (WARN_ON_ONCE(reg_offset < 0))
21 return &__dummy;
22
23 return (unsigned long *)((unsigned long)regs + reg_offset);
24}
25
26static inline unsigned long
27ex_fixup_addr(const struct exception_table_entry *x)
28{
29 return (unsigned long)&x->fixup + x->fixup;
30}
31
32static bool ex_handler_default(const struct exception_table_entry *e,
33 struct pt_regs *regs)
34{
35 if (e->data & EX_FLAG_CLEAR_AX)
36 regs->ax = 0;
37 if (e->data & EX_FLAG_CLEAR_DX)
38 regs->dx = 0;
39
40 regs->ip = ex_fixup_addr(e);
41 return true;
42}
43
44/*
45 * This is the *very* rare case where we do a "load_unaligned_zeropad()"
46 * and it's a page crosser into a non-existent page.
47 *
48 * This happens when we optimistically load a pathname a word-at-a-time
49 * and the name is less than the full word and the next page is not
50 * mapped. Typically that only happens for CONFIG_DEBUG_PAGEALLOC.
51 *
52 * NOTE! The faulting address is always a 'mov mem,reg' type instruction
53 * of size 'long', and the exception fixup must always point to right
54 * after the instruction.
55 */
56static bool ex_handler_zeropad(const struct exception_table_entry *e,
57 struct pt_regs *regs,
58 unsigned long fault_addr)
59{
60 struct insn insn;
61 const unsigned long mask = sizeof(long) - 1;
62 unsigned long offset, addr, next_ip, len;
63 unsigned long *reg;
64
65 next_ip = ex_fixup_addr(e);
66 len = next_ip - regs->ip;
67 if (len > MAX_INSN_SIZE)
68 return false;
69
70 if (insn_decode(&insn, (void *) regs->ip, len, INSN_MODE_KERN))
71 return false;
72 if (insn.length != len)
73 return false;
74
75 if (insn.opcode.bytes[0] != 0x8b)
76 return false;
77 if (insn.opnd_bytes != sizeof(long))
78 return false;
79
80 addr = (unsigned long) insn_get_addr_ref(&insn, regs);
81 if (addr == ~0ul)
82 return false;
83
84 offset = addr & mask;
85 addr = addr & ~mask;
86 if (fault_addr != addr + sizeof(long))
87 return false;
88
89 reg = insn_get_modrm_reg_ptr(&insn, regs);
90 if (!reg)
91 return false;
92
93 *reg = *(unsigned long *)addr >> (offset * 8);
94 return ex_handler_default(e, regs);
95}
96
97static bool ex_handler_fault(const struct exception_table_entry *fixup,
98 struct pt_regs *regs, int trapnr)
99{
100 regs->ax = trapnr;
101 return ex_handler_default(fixup, regs);
102}
103
104static bool ex_handler_sgx(const struct exception_table_entry *fixup,
105 struct pt_regs *regs, int trapnr)
106{
107 regs->ax = trapnr | SGX_ENCLS_FAULT_FLAG;
108 return ex_handler_default(fixup, regs);
109}
110
111/*
112 * Handler for when we fail to restore a task's FPU state. We should never get
113 * here because the FPU state of a task using the FPU (task->thread.fpu.state)
114 * should always be valid. However, past bugs have allowed userspace to set
115 * reserved bits in the XSAVE area using PTRACE_SETREGSET or sys_rt_sigreturn().
116 * These caused XRSTOR to fail when switching to the task, leaking the FPU
117 * registers of the task previously executing on the CPU. Mitigate this class
118 * of vulnerability by restoring from the initial state (essentially, zeroing
119 * out all the FPU registers) if we can't restore from the task's FPU state.
120 */
121static bool ex_handler_fprestore(const struct exception_table_entry *fixup,
122 struct pt_regs *regs)
123{
124 regs->ip = ex_fixup_addr(fixup);
125
126 WARN_ONCE(1, "Bad FPU state detected at %pB, reinitializing FPU registers.",
127 (void *)instruction_pointer(regs));
128
129 fpu_reset_from_exception_fixup();
130 return true;
131}
132
133static bool ex_handler_uaccess(const struct exception_table_entry *fixup,
134 struct pt_regs *regs, int trapnr)
135{
136 WARN_ONCE(trapnr == X86_TRAP_GP, "General protection fault in user access. Non-canonical address?");
137 return ex_handler_default(fixup, regs);
138}
139
140static bool ex_handler_copy(const struct exception_table_entry *fixup,
141 struct pt_regs *regs, int trapnr)
142{
143 WARN_ONCE(trapnr == X86_TRAP_GP, "General protection fault in user access. Non-canonical address?");
144 return ex_handler_fault(fixup, regs, trapnr);
145}
146
147static bool ex_handler_msr(const struct exception_table_entry *fixup,
148 struct pt_regs *regs, bool wrmsr, bool safe, int reg)
149{
150 if (__ONCE_LITE_IF(!safe && wrmsr)) {
151 pr_warn("unchecked MSR access error: WRMSR to 0x%x (tried to write 0x%08x%08x) at rIP: 0x%lx (%pS)\n",
152 (unsigned int)regs->cx, (unsigned int)regs->dx,
153 (unsigned int)regs->ax, regs->ip, (void *)regs->ip);
154 show_stack_regs(regs);
155 }
156
157 if (__ONCE_LITE_IF(!safe && !wrmsr)) {
158 pr_warn("unchecked MSR access error: RDMSR from 0x%x at rIP: 0x%lx (%pS)\n",
159 (unsigned int)regs->cx, regs->ip, (void *)regs->ip);
160 show_stack_regs(regs);
161 }
162
163 if (!wrmsr) {
164 /* Pretend that the read succeeded and returned 0. */
165 regs->ax = 0;
166 regs->dx = 0;
167 }
168
169 if (safe)
170 *pt_regs_nr(regs, reg) = -EIO;
171
172 return ex_handler_default(fixup, regs);
173}
174
175static bool ex_handler_clear_fs(const struct exception_table_entry *fixup,
176 struct pt_regs *regs)
177{
178 if (static_cpu_has(X86_BUG_NULL_SEG))
179 asm volatile ("mov %0, %%fs" : : "rm" (__USER_DS));
180 asm volatile ("mov %0, %%fs" : : "rm" (0));
181 return ex_handler_default(fixup, regs);
182}
183
184static bool ex_handler_imm_reg(const struct exception_table_entry *fixup,
185 struct pt_regs *regs, int reg, int imm)
186{
187 *pt_regs_nr(regs, reg) = (long)imm;
188 return ex_handler_default(fixup, regs);
189}
190
191static bool ex_handler_ucopy_len(const struct exception_table_entry *fixup,
192 struct pt_regs *regs, int trapnr, int reg, int imm)
193{
194 regs->cx = imm * regs->cx + *pt_regs_nr(regs, reg);
195 return ex_handler_uaccess(fixup, regs, trapnr);
196}
197
198int ex_get_fixup_type(unsigned long ip)
199{
200 const struct exception_table_entry *e = search_exception_tables(ip);
201
202 return e ? FIELD_GET(EX_DATA_TYPE_MASK, e->data) : EX_TYPE_NONE;
203}
204
205int fixup_exception(struct pt_regs *regs, int trapnr, unsigned long error_code,
206 unsigned long fault_addr)
207{
208 const struct exception_table_entry *e;
209 int type, reg, imm;
210
211#ifdef CONFIG_PNPBIOS
212 if (unlikely(SEGMENT_IS_PNP_CODE(regs->cs))) {
213 extern u32 pnp_bios_fault_eip, pnp_bios_fault_esp;
214 extern u32 pnp_bios_is_utter_crap;
215 pnp_bios_is_utter_crap = 1;
216 printk(KERN_CRIT "PNPBIOS fault.. attempting recovery.\n");
217 __asm__ volatile(
218 "movl %0, %%esp\n\t"
219 "jmp *%1\n\t"
220 : : "g" (pnp_bios_fault_esp), "g" (pnp_bios_fault_eip));
221 panic("do_trap: can't hit this");
222 }
223#endif
224
225 e = search_exception_tables(regs->ip);
226 if (!e)
227 return 0;
228
229 type = FIELD_GET(EX_DATA_TYPE_MASK, e->data);
230 reg = FIELD_GET(EX_DATA_REG_MASK, e->data);
231 imm = FIELD_GET(EX_DATA_IMM_MASK, e->data);
232
233 switch (type) {
234 case EX_TYPE_DEFAULT:
235 case EX_TYPE_DEFAULT_MCE_SAFE:
236 return ex_handler_default(e, regs);
237 case EX_TYPE_FAULT:
238 case EX_TYPE_FAULT_MCE_SAFE:
239 return ex_handler_fault(e, regs, trapnr);
240 case EX_TYPE_UACCESS:
241 return ex_handler_uaccess(e, regs, trapnr);
242 case EX_TYPE_COPY:
243 return ex_handler_copy(e, regs, trapnr);
244 case EX_TYPE_CLEAR_FS:
245 return ex_handler_clear_fs(e, regs);
246 case EX_TYPE_FPU_RESTORE:
247 return ex_handler_fprestore(e, regs);
248 case EX_TYPE_BPF:
249 return ex_handler_bpf(e, regs);
250 case EX_TYPE_WRMSR:
251 return ex_handler_msr(e, regs, true, false, reg);
252 case EX_TYPE_RDMSR:
253 return ex_handler_msr(e, regs, false, false, reg);
254 case EX_TYPE_WRMSR_SAFE:
255 return ex_handler_msr(e, regs, true, true, reg);
256 case EX_TYPE_RDMSR_SAFE:
257 return ex_handler_msr(e, regs, false, true, reg);
258 case EX_TYPE_WRMSR_IN_MCE:
259 ex_handler_msr_mce(regs, true);
260 break;
261 case EX_TYPE_RDMSR_IN_MCE:
262 ex_handler_msr_mce(regs, false);
263 break;
264 case EX_TYPE_POP_REG:
265 regs->sp += sizeof(long);
266 fallthrough;
267 case EX_TYPE_IMM_REG:
268 return ex_handler_imm_reg(e, regs, reg, imm);
269 case EX_TYPE_FAULT_SGX:
270 return ex_handler_sgx(e, regs, trapnr);
271 case EX_TYPE_UCOPY_LEN:
272 return ex_handler_ucopy_len(e, regs, trapnr, reg, imm);
273 case EX_TYPE_ZEROPAD:
274 return ex_handler_zeropad(e, regs, fault_addr);
275 }
276 BUG();
277}
278
279extern unsigned int early_recursion_flag;
280
281/* Restricted version used during very early boot */
282void __init early_fixup_exception(struct pt_regs *regs, int trapnr)
283{
284 /* Ignore early NMIs. */
285 if (trapnr == X86_TRAP_NMI)
286 return;
287
288 if (early_recursion_flag > 2)
289 goto halt_loop;
290
291 /*
292 * Old CPUs leave the high bits of CS on the stack
293 * undefined. I'm not sure which CPUs do this, but at least
294 * the 486 DX works this way.
295 * Xen pv domains are not using the default __KERNEL_CS.
296 */
297 if (!xen_pv_domain() && regs->cs != __KERNEL_CS)
298 goto fail;
299
300 /*
301 * The full exception fixup machinery is available as soon as
302 * the early IDT is loaded. This means that it is the
303 * responsibility of extable users to either function correctly
304 * when handlers are invoked early or to simply avoid causing
305 * exceptions before they're ready to handle them.
306 *
307 * This is better than filtering which handlers can be used,
308 * because refusing to call a handler here is guaranteed to
309 * result in a hard-to-debug panic.
310 *
311 * Keep in mind that not all vectors actually get here. Early
312 * page faults, for example, are special.
313 */
314 if (fixup_exception(regs, trapnr, regs->orig_ax, 0))
315 return;
316
317 if (trapnr == X86_TRAP_UD) {
318 if (report_bug(regs->ip, regs) == BUG_TRAP_TYPE_WARN) {
319 /* Skip the ud2. */
320 regs->ip += LEN_UD2;
321 return;
322 }
323
324 /*
325 * If this was a BUG and report_bug returns or if this
326 * was just a normal #UD, we want to continue onward and
327 * crash.
328 */
329 }
330
331fail:
332 early_printk("PANIC: early exception 0x%02x IP %lx:%lx error %lx cr2 0x%lx\n",
333 (unsigned)trapnr, (unsigned long)regs->cs, regs->ip,
334 regs->orig_ax, read_cr2());
335
336 show_regs(regs);
337
338halt_loop:
339 while (true)
340 halt();
341}
1#include <linux/extable.h>
2#include <linux/uaccess.h>
3#include <linux/sched/debug.h>
4#include <xen/xen.h>
5
6#include <asm/fpu/internal.h>
7#include <asm/traps.h>
8#include <asm/kdebug.h>
9
10typedef bool (*ex_handler_t)(const struct exception_table_entry *,
11 struct pt_regs *, int);
12
13static inline unsigned long
14ex_fixup_addr(const struct exception_table_entry *x)
15{
16 return (unsigned long)&x->fixup + x->fixup;
17}
18static inline ex_handler_t
19ex_fixup_handler(const struct exception_table_entry *x)
20{
21 return (ex_handler_t)((unsigned long)&x->handler + x->handler);
22}
23
24__visible bool ex_handler_default(const struct exception_table_entry *fixup,
25 struct pt_regs *regs, int trapnr)
26{
27 regs->ip = ex_fixup_addr(fixup);
28 return true;
29}
30EXPORT_SYMBOL(ex_handler_default);
31
32__visible bool ex_handler_fault(const struct exception_table_entry *fixup,
33 struct pt_regs *regs, int trapnr)
34{
35 regs->ip = ex_fixup_addr(fixup);
36 regs->ax = trapnr;
37 return true;
38}
39EXPORT_SYMBOL_GPL(ex_handler_fault);
40
41/*
42 * Handler for UD0 exception following a failed test against the
43 * result of a refcount inc/dec/add/sub.
44 */
45__visible bool ex_handler_refcount(const struct exception_table_entry *fixup,
46 struct pt_regs *regs, int trapnr)
47{
48 /* First unconditionally saturate the refcount. */
49 *(int *)regs->cx = INT_MIN / 2;
50
51 /*
52 * Strictly speaking, this reports the fixup destination, not
53 * the fault location, and not the actually overflowing
54 * instruction, which is the instruction before the "js", but
55 * since that instruction could be a variety of lengths, just
56 * report the location after the overflow, which should be close
57 * enough for finding the overflow, as it's at least back in
58 * the function, having returned from .text.unlikely.
59 */
60 regs->ip = ex_fixup_addr(fixup);
61
62 /*
63 * This function has been called because either a negative refcount
64 * value was seen by any of the refcount functions, or a zero
65 * refcount value was seen by refcount_dec().
66 *
67 * If we crossed from INT_MAX to INT_MIN, OF (Overflow Flag: result
68 * wrapped around) will be set. Additionally, seeing the refcount
69 * reach 0 will set ZF (Zero Flag: result was zero). In each of
70 * these cases we want a report, since it's a boundary condition.
71 * The SF case is not reported since it indicates post-boundary
72 * manipulations below zero or above INT_MAX. And if none of the
73 * flags are set, something has gone very wrong, so report it.
74 */
75 if (regs->flags & (X86_EFLAGS_OF | X86_EFLAGS_ZF)) {
76 bool zero = regs->flags & X86_EFLAGS_ZF;
77
78 refcount_error_report(regs, zero ? "hit zero" : "overflow");
79 } else if ((regs->flags & X86_EFLAGS_SF) == 0) {
80 /* Report if none of OF, ZF, nor SF are set. */
81 refcount_error_report(regs, "unexpected saturation");
82 }
83
84 return true;
85}
86EXPORT_SYMBOL(ex_handler_refcount);
87
88/*
89 * Handler for when we fail to restore a task's FPU state. We should never get
90 * here because the FPU state of a task using the FPU (task->thread.fpu.state)
91 * should always be valid. However, past bugs have allowed userspace to set
92 * reserved bits in the XSAVE area using PTRACE_SETREGSET or sys_rt_sigreturn().
93 * These caused XRSTOR to fail when switching to the task, leaking the FPU
94 * registers of the task previously executing on the CPU. Mitigate this class
95 * of vulnerability by restoring from the initial state (essentially, zeroing
96 * out all the FPU registers) if we can't restore from the task's FPU state.
97 */
98__visible bool ex_handler_fprestore(const struct exception_table_entry *fixup,
99 struct pt_regs *regs, int trapnr)
100{
101 regs->ip = ex_fixup_addr(fixup);
102
103 WARN_ONCE(1, "Bad FPU state detected at %pB, reinitializing FPU registers.",
104 (void *)instruction_pointer(regs));
105
106 __copy_kernel_to_fpregs(&init_fpstate, -1);
107 return true;
108}
109EXPORT_SYMBOL_GPL(ex_handler_fprestore);
110
111__visible bool ex_handler_ext(const struct exception_table_entry *fixup,
112 struct pt_regs *regs, int trapnr)
113{
114 /* Special hack for uaccess_err */
115 current->thread.uaccess_err = 1;
116 regs->ip = ex_fixup_addr(fixup);
117 return true;
118}
119EXPORT_SYMBOL(ex_handler_ext);
120
121__visible bool ex_handler_rdmsr_unsafe(const struct exception_table_entry *fixup,
122 struct pt_regs *regs, int trapnr)
123{
124 if (pr_warn_once("unchecked MSR access error: RDMSR from 0x%x at rIP: 0x%lx (%pF)\n",
125 (unsigned int)regs->cx, regs->ip, (void *)regs->ip))
126 show_stack_regs(regs);
127
128 /* Pretend that the read succeeded and returned 0. */
129 regs->ip = ex_fixup_addr(fixup);
130 regs->ax = 0;
131 regs->dx = 0;
132 return true;
133}
134EXPORT_SYMBOL(ex_handler_rdmsr_unsafe);
135
136__visible bool ex_handler_wrmsr_unsafe(const struct exception_table_entry *fixup,
137 struct pt_regs *regs, int trapnr)
138{
139 if (pr_warn_once("unchecked MSR access error: WRMSR to 0x%x (tried to write 0x%08x%08x) at rIP: 0x%lx (%pF)\n",
140 (unsigned int)regs->cx, (unsigned int)regs->dx,
141 (unsigned int)regs->ax, regs->ip, (void *)regs->ip))
142 show_stack_regs(regs);
143
144 /* Pretend that the write succeeded. */
145 regs->ip = ex_fixup_addr(fixup);
146 return true;
147}
148EXPORT_SYMBOL(ex_handler_wrmsr_unsafe);
149
150__visible bool ex_handler_clear_fs(const struct exception_table_entry *fixup,
151 struct pt_regs *regs, int trapnr)
152{
153 if (static_cpu_has(X86_BUG_NULL_SEG))
154 asm volatile ("mov %0, %%fs" : : "rm" (__USER_DS));
155 asm volatile ("mov %0, %%fs" : : "rm" (0));
156 return ex_handler_default(fixup, regs, trapnr);
157}
158EXPORT_SYMBOL(ex_handler_clear_fs);
159
160__visible bool ex_has_fault_handler(unsigned long ip)
161{
162 const struct exception_table_entry *e;
163 ex_handler_t handler;
164
165 e = search_exception_tables(ip);
166 if (!e)
167 return false;
168 handler = ex_fixup_handler(e);
169
170 return handler == ex_handler_fault;
171}
172
173int fixup_exception(struct pt_regs *regs, int trapnr)
174{
175 const struct exception_table_entry *e;
176 ex_handler_t handler;
177
178#ifdef CONFIG_PNPBIOS
179 if (unlikely(SEGMENT_IS_PNP_CODE(regs->cs))) {
180 extern u32 pnp_bios_fault_eip, pnp_bios_fault_esp;
181 extern u32 pnp_bios_is_utter_crap;
182 pnp_bios_is_utter_crap = 1;
183 printk(KERN_CRIT "PNPBIOS fault.. attempting recovery.\n");
184 __asm__ volatile(
185 "movl %0, %%esp\n\t"
186 "jmp *%1\n\t"
187 : : "g" (pnp_bios_fault_esp), "g" (pnp_bios_fault_eip));
188 panic("do_trap: can't hit this");
189 }
190#endif
191
192 e = search_exception_tables(regs->ip);
193 if (!e)
194 return 0;
195
196 handler = ex_fixup_handler(e);
197 return handler(e, regs, trapnr);
198}
199
200extern unsigned int early_recursion_flag;
201
202/* Restricted version used during very early boot */
203void __init early_fixup_exception(struct pt_regs *regs, int trapnr)
204{
205 /* Ignore early NMIs. */
206 if (trapnr == X86_TRAP_NMI)
207 return;
208
209 if (early_recursion_flag > 2)
210 goto halt_loop;
211
212 /*
213 * Old CPUs leave the high bits of CS on the stack
214 * undefined. I'm not sure which CPUs do this, but at least
215 * the 486 DX works this way.
216 * Xen pv domains are not using the default __KERNEL_CS.
217 */
218 if (!xen_pv_domain() && regs->cs != __KERNEL_CS)
219 goto fail;
220
221 /*
222 * The full exception fixup machinery is available as soon as
223 * the early IDT is loaded. This means that it is the
224 * responsibility of extable users to either function correctly
225 * when handlers are invoked early or to simply avoid causing
226 * exceptions before they're ready to handle them.
227 *
228 * This is better than filtering which handlers can be used,
229 * because refusing to call a handler here is guaranteed to
230 * result in a hard-to-debug panic.
231 *
232 * Keep in mind that not all vectors actually get here. Early
233 * fage faults, for example, are special.
234 */
235 if (fixup_exception(regs, trapnr))
236 return;
237
238 if (fixup_bug(regs, trapnr))
239 return;
240
241fail:
242 early_printk("PANIC: early exception 0x%02x IP %lx:%lx error %lx cr2 0x%lx\n",
243 (unsigned)trapnr, (unsigned long)regs->cs, regs->ip,
244 regs->orig_ax, read_cr2());
245
246 show_regs(regs);
247
248halt_loop:
249 while (true)
250 halt();
251}