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1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include <uapi/drm/i915_drm.h>
34
35#include <linux/pm_qos.h>
36
37#include <drm/ttm/ttm_device.h>
38
39#include "display/intel_display.h"
40#include "display/intel_display_core.h"
41
42#include "gem/i915_gem_context_types.h"
43#include "gem/i915_gem_shrinker.h"
44#include "gem/i915_gem_stolen.h"
45
46#include "gt/intel_engine.h"
47#include "gt/intel_gt_types.h"
48#include "gt/intel_region_lmem.h"
49#include "gt/intel_workarounds.h"
50#include "gt/uc/intel_uc.h"
51
52#include "i915_drm_client.h"
53#include "i915_gem.h"
54#include "i915_gpu_error.h"
55#include "i915_params.h"
56#include "i915_perf_types.h"
57#include "i915_scheduler.h"
58#include "i915_utils.h"
59#include "intel_device_info.h"
60#include "intel_memory_region.h"
61#include "intel_pch.h"
62#include "intel_runtime_pm.h"
63#include "intel_step.h"
64#include "intel_uncore.h"
65
66struct drm_i915_clock_gating_funcs;
67struct drm_i915_gem_object;
68struct drm_i915_private;
69struct intel_connector;
70struct intel_dp;
71struct intel_encoder;
72struct intel_limit;
73struct intel_overlay_error_state;
74struct vlv_s0ix_state;
75
76#define I915_GEM_GPU_DOMAINS \
77 (I915_GEM_DOMAIN_RENDER | \
78 I915_GEM_DOMAIN_SAMPLER | \
79 I915_GEM_DOMAIN_COMMAND | \
80 I915_GEM_DOMAIN_INSTRUCTION | \
81 I915_GEM_DOMAIN_VERTEX)
82
83#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
84
85#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
86
87struct i915_suspend_saved_registers {
88 u32 saveDSPARB;
89 u32 saveSWF0[16];
90 u32 saveSWF1[16];
91 u32 saveSWF3[3];
92 u16 saveGCDGMBUS;
93};
94
95#define MAX_L3_SLICES 2
96struct intel_l3_parity {
97 u32 *remap_info[MAX_L3_SLICES];
98 struct work_struct error_work;
99 int which_slice;
100};
101
102struct i915_gem_mm {
103 /*
104 * Shortcut for the stolen region. This points to either
105 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or
106 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
107 * support stolen.
108 */
109 struct intel_memory_region *stolen_region;
110 /** Memory allocator for GTT stolen memory */
111 struct drm_mm stolen;
112 /** Protects the usage of the GTT stolen memory allocator. This is
113 * always the inner lock when overlapping with struct_mutex. */
114 struct mutex stolen_lock;
115
116 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
117 spinlock_t obj_lock;
118
119 /**
120 * List of objects which are purgeable.
121 */
122 struct list_head purge_list;
123
124 /**
125 * List of objects which have allocated pages and are shrinkable.
126 */
127 struct list_head shrink_list;
128
129 /**
130 * List of objects which are pending destruction.
131 */
132 struct llist_head free_list;
133 struct work_struct free_work;
134 /**
135 * Count of objects pending destructions. Used to skip needlessly
136 * waiting on an RCU barrier if no objects are waiting to be freed.
137 */
138 atomic_t free_count;
139
140 /**
141 * tmpfs instance used for shmem backed objects
142 */
143 struct vfsmount *gemfs;
144
145 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
146
147 struct notifier_block oom_notifier;
148 struct notifier_block vmap_notifier;
149 struct shrinker shrinker;
150
151#ifdef CONFIG_MMU_NOTIFIER
152 /**
153 * notifier_lock for mmu notifiers, memory may not be allocated
154 * while holding this lock.
155 */
156 rwlock_t notifier_lock;
157#endif
158
159 /* shrinker accounting, also useful for userland debugging */
160 u64 shrink_memory;
161 u32 shrink_count;
162};
163
164#define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
165
166unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
167 u64 context);
168
169static inline unsigned long
170i915_fence_timeout(const struct drm_i915_private *i915)
171{
172 return i915_fence_context_timeout(i915, U64_MAX);
173}
174
175#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
176
177struct i915_virtual_gpu {
178 struct mutex lock; /* serialises sending of g2v_notify command pkts */
179 bool active;
180 u32 caps;
181 u32 *initial_mmio;
182 u8 *initial_cfg_space;
183 struct list_head entry;
184};
185
186struct i915_selftest_stash {
187 atomic_t counter;
188 struct ida mock_region_instances;
189};
190
191struct drm_i915_private {
192 struct drm_device drm;
193
194 struct intel_display display;
195
196 /* FIXME: Device release actions should all be moved to drmm_ */
197 bool do_release;
198
199 /* i915 device parameters */
200 struct i915_params params;
201
202 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
203 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
204 struct intel_driver_caps caps;
205
206 /**
207 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
208 * end of stolen which we can optionally use to create GEM objects
209 * backed by stolen memory. Note that stolen_usable_size tells us
210 * exactly how much of this we are actually allowed to use, given that
211 * some portion of it is in fact reserved for use by hardware functions.
212 */
213 struct resource dsm;
214 /**
215 * Reseved portion of Data Stolen Memory
216 */
217 struct resource dsm_reserved;
218
219 /*
220 * Stolen memory is segmented in hardware with different portions
221 * offlimits to certain functions.
222 *
223 * The drm_mm is initialised to the total accessible range, as found
224 * from the PCI config. On Broadwell+, this is further restricted to
225 * avoid the first page! The upper end of stolen memory is reserved for
226 * hardware functions and similarly removed from the accessible range.
227 */
228 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
229
230 struct intel_uncore uncore;
231 struct intel_uncore_mmio_debug mmio_debug;
232
233 struct i915_virtual_gpu vgpu;
234
235 struct intel_gvt *gvt;
236
237 struct pci_dev *bridge_dev;
238
239 struct rb_root uabi_engines;
240 unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];
241
242 struct resource mch_res;
243
244 /* protects the irq masks */
245 spinlock_t irq_lock;
246
247 bool display_irqs_enabled;
248
249 /* Sideband mailbox protection */
250 struct mutex sb_lock;
251 struct pm_qos_request sb_qos;
252
253 /** Cached value of IMR to avoid reads in updating the bitfield */
254 union {
255 u32 irq_mask;
256 u32 de_irq_mask[I915_MAX_PIPES];
257 };
258 u32 pipestat_irq_mask[I915_MAX_PIPES];
259
260 bool preserve_bios_swizzle;
261
262 unsigned int fsb_freq, mem_freq, is_ddr3;
263 unsigned int skl_preferred_vco_freq;
264
265 unsigned int max_dotclk_freq;
266 unsigned int hpll_freq;
267 unsigned int czclk_freq;
268
269 /**
270 * wq - Driver workqueue for GEM.
271 *
272 * NOTE: Work items scheduled here are not allowed to grab any modeset
273 * locks, for otherwise the flushing done in the pageflip code will
274 * result in deadlocks.
275 */
276 struct workqueue_struct *wq;
277
278 /* pm private clock gating functions */
279 const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
280
281 /* PCH chipset type */
282 enum intel_pch pch_type;
283 unsigned short pch_id;
284
285 unsigned long gem_quirks;
286
287 struct i915_gem_mm mm;
288
289 bool mchbar_need_disable;
290
291 struct intel_l3_parity l3_parity;
292
293 /*
294 * edram size in MB.
295 * Cannot be determined by PCIID. You must always read a register.
296 */
297 u32 edram_size_mb;
298
299 struct i915_gpu_error gpu_error;
300
301 /*
302 * Shadows for CHV DPLL_MD regs to keep the state
303 * checker somewhat working in the presence hardware
304 * crappiness (can't read out DPLL_MD for pipes B & C).
305 */
306 u32 chv_dpll_md[I915_MAX_PIPES];
307 u32 bxt_phy_grc;
308
309 u32 suspend_count;
310 struct i915_suspend_saved_registers regfile;
311 struct vlv_s0ix_state *vlv_s0ix_state;
312
313 struct dram_info {
314 bool wm_lv_0_adjust_needed;
315 u8 num_channels;
316 bool symmetric_memory;
317 enum intel_dram_type {
318 INTEL_DRAM_UNKNOWN,
319 INTEL_DRAM_DDR3,
320 INTEL_DRAM_DDR4,
321 INTEL_DRAM_LPDDR3,
322 INTEL_DRAM_LPDDR4,
323 INTEL_DRAM_DDR5,
324 INTEL_DRAM_LPDDR5,
325 } type;
326 u8 num_qgv_points;
327 u8 num_psf_gv_points;
328 } dram_info;
329
330 struct intel_runtime_pm runtime_pm;
331
332 struct i915_perf perf;
333
334 struct i915_hwmon *hwmon;
335
336 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
337 struct intel_gt gt0;
338
339 /*
340 * i915->gt[0] == &i915->gt0
341 */
342#define I915_MAX_GT 4
343 struct intel_gt *gt[I915_MAX_GT];
344
345 struct kobject *sysfs_gt;
346
347 /* Quick lookup of media GT (current platforms only have one) */
348 struct intel_gt *media_gt;
349
350 struct {
351 struct i915_gem_contexts {
352 spinlock_t lock; /* locks list */
353 struct list_head list;
354 } contexts;
355
356 /*
357 * We replace the local file with a global mappings as the
358 * backing storage for the mmap is on the device and not
359 * on the struct file, and we do not want to prolong the
360 * lifetime of the local fd. To minimise the number of
361 * anonymous inodes we create, we use a global singleton to
362 * share the global mapping.
363 */
364 struct file *mmap_singleton;
365 } gem;
366
367 u8 pch_ssc_use;
368
369 /* For i915gm/i945gm vblank irq workaround */
370 u8 vblank_enabled;
371
372 bool irq_enabled;
373
374 /*
375 * DG2: Mask of PHYs that were not calibrated by the firmware
376 * and should not be used.
377 */
378 u8 snps_phy_failed_calibration;
379
380 struct i915_pmu pmu;
381
382 struct i915_drm_clients clients;
383
384 /* The TTM device structure. */
385 struct ttm_device bdev;
386
387 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
388
389 /*
390 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
391 * will be rejected. Instead look for a better place.
392 */
393};
394
395static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
396{
397 return container_of(dev, struct drm_i915_private, drm);
398}
399
400static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
401{
402 return dev_get_drvdata(kdev);
403}
404
405static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
406{
407 return pci_get_drvdata(pdev);
408}
409
410static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
411{
412 return &i915->gt0;
413}
414
415/* Simple iterator over all initialised engines */
416#define for_each_engine(engine__, dev_priv__, id__) \
417 for ((id__) = 0; \
418 (id__) < I915_NUM_ENGINES; \
419 (id__)++) \
420 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
421
422/* Iterator over subset of engines selected by mask */
423#define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
424 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
425 (tmp__) ? \
426 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
427 0;)
428
429#define rb_to_uabi_engine(rb) \
430 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
431
432#define for_each_uabi_engine(engine__, i915__) \
433 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
434 (engine__); \
435 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
436
437#define for_each_uabi_class_engine(engine__, class__, i915__) \
438 for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
439 (engine__) && (engine__)->uabi_class == (class__); \
440 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
441
442#define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
443#define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
444#define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
445
446#define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
447
448#define IP_VER(ver, rel) ((ver) << 8 | (rel))
449
450#define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver)
451#define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
452 RUNTIME_INFO(i915)->graphics.ip.rel)
453#define IS_GRAPHICS_VER(i915, from, until) \
454 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
455
456#define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver)
457#define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
458 RUNTIME_INFO(i915)->media.ip.rel)
459#define IS_MEDIA_VER(i915, from, until) \
460 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
461
462#define DISPLAY_VER(i915) (RUNTIME_INFO(i915)->display.ip.ver)
463#define IS_DISPLAY_VER(i915, from, until) \
464 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
465
466#define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
467
468#define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
469
470#define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
471#define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
472#define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
473#define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step)
474
475#define IS_DISPLAY_STEP(__i915, since, until) \
476 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
477 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
478
479#define IS_GRAPHICS_STEP(__i915, since, until) \
480 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \
481 INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until))
482
483#define IS_MEDIA_STEP(__i915, since, until) \
484 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
485 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until))
486
487#define IS_BASEDIE_STEP(__i915, since, until) \
488 (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \
489 INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until))
490
491static __always_inline unsigned int
492__platform_mask_index(const struct intel_runtime_info *info,
493 enum intel_platform p)
494{
495 const unsigned int pbits =
496 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
497
498 /* Expand the platform_mask array if this fails. */
499 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
500 pbits * ARRAY_SIZE(info->platform_mask));
501
502 return p / pbits;
503}
504
505static __always_inline unsigned int
506__platform_mask_bit(const struct intel_runtime_info *info,
507 enum intel_platform p)
508{
509 const unsigned int pbits =
510 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
511
512 return p % pbits + INTEL_SUBPLATFORM_BITS;
513}
514
515static inline u32
516intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
517{
518 const unsigned int pi = __platform_mask_index(info, p);
519
520 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
521}
522
523static __always_inline bool
524IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
525{
526 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
527 const unsigned int pi = __platform_mask_index(info, p);
528 const unsigned int pb = __platform_mask_bit(info, p);
529
530 BUILD_BUG_ON(!__builtin_constant_p(p));
531
532 return info->platform_mask[pi] & BIT(pb);
533}
534
535static __always_inline bool
536IS_SUBPLATFORM(const struct drm_i915_private *i915,
537 enum intel_platform p, unsigned int s)
538{
539 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
540 const unsigned int pi = __platform_mask_index(info, p);
541 const unsigned int pb = __platform_mask_bit(info, p);
542 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
543 const u32 mask = info->platform_mask[pi];
544
545 BUILD_BUG_ON(!__builtin_constant_p(p));
546 BUILD_BUG_ON(!__builtin_constant_p(s));
547 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
548
549 /* Shift and test on the MSB position so sign flag can be used. */
550 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
551}
552
553#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
554#define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx)
555
556#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
557#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
558#define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
559#define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
560#define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
561#define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
562#define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
563#define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
564#define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
565#define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
566#define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
567#define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
568#define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
569#define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
570#define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
571#define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
572#define IS_IRONLAKE_M(dev_priv) \
573 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
574#define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
575#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
576#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
577 INTEL_INFO(dev_priv)->gt == 1)
578#define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
579#define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
580#define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
581#define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
582#define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
583#define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
584#define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
585#define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
586#define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
587#define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
588#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
589#define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
590 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
591#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
592#define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
593#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
594#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
595#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
596#define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
597#define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2)
598#define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
599#define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)
600
601#define IS_METEORLAKE_M(dev_priv) \
602 IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
603#define IS_METEORLAKE_P(dev_priv) \
604 IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
605#define IS_DG2_G10(dev_priv) \
606 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
607#define IS_DG2_G11(dev_priv) \
608 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
609#define IS_DG2_G12(dev_priv) \
610 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
611#define IS_ADLS_RPLS(dev_priv) \
612 IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
613#define IS_ADLP_N(dev_priv) \
614 IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
615#define IS_ADLP_RPLP(dev_priv) \
616 IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
617#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
618 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
619#define IS_BDW_ULT(dev_priv) \
620 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
621#define IS_BDW_ULX(dev_priv) \
622 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
623#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
624 INTEL_INFO(dev_priv)->gt == 3)
625#define IS_HSW_ULT(dev_priv) \
626 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
627#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
628 INTEL_INFO(dev_priv)->gt == 3)
629#define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
630 INTEL_INFO(dev_priv)->gt == 1)
631/* ULX machines are also considered ULT. */
632#define IS_HSW_ULX(dev_priv) \
633 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
634#define IS_SKL_ULT(dev_priv) \
635 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
636#define IS_SKL_ULX(dev_priv) \
637 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
638#define IS_KBL_ULT(dev_priv) \
639 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
640#define IS_KBL_ULX(dev_priv) \
641 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
642#define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
643 INTEL_INFO(dev_priv)->gt == 2)
644#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
645 INTEL_INFO(dev_priv)->gt == 3)
646#define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
647 INTEL_INFO(dev_priv)->gt == 4)
648#define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
649 INTEL_INFO(dev_priv)->gt == 2)
650#define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
651 INTEL_INFO(dev_priv)->gt == 3)
652#define IS_CFL_ULT(dev_priv) \
653 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
654#define IS_CFL_ULX(dev_priv) \
655 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
656#define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
657 INTEL_INFO(dev_priv)->gt == 2)
658#define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
659 INTEL_INFO(dev_priv)->gt == 3)
660
661#define IS_CML_ULT(dev_priv) \
662 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
663#define IS_CML_ULX(dev_priv) \
664 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
665#define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \
666 INTEL_INFO(dev_priv)->gt == 2)
667
668#define IS_ICL_WITH_PORT_F(dev_priv) \
669 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
670
671#define IS_TGL_UY(dev_priv) \
672 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
673
674#define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
675
676#define IS_KBL_GRAPHICS_STEP(dev_priv, since, until) \
677 (IS_KABYLAKE(dev_priv) && IS_GRAPHICS_STEP(dev_priv, since, until))
678#define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
679 (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
680
681#define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \
682 (IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
683#define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
684 (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
685
686#define IS_TGL_DISPLAY_STEP(__i915, since, until) \
687 (IS_TIGERLAKE(__i915) && \
688 IS_DISPLAY_STEP(__i915, since, until))
689
690#define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until) \
691 (IS_TGL_UY(__i915) && \
692 IS_GRAPHICS_STEP(__i915, since, until))
693
694#define IS_TGL_GRAPHICS_STEP(__i915, since, until) \
695 (IS_TIGERLAKE(__i915) && !IS_TGL_UY(__i915)) && \
696 IS_GRAPHICS_STEP(__i915, since, until))
697
698#define IS_RKL_DISPLAY_STEP(p, since, until) \
699 (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
700
701#define IS_DG1_GRAPHICS_STEP(p, since, until) \
702 (IS_DG1(p) && IS_GRAPHICS_STEP(p, since, until))
703#define IS_DG1_DISPLAY_STEP(p, since, until) \
704 (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
705
706#define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
707 (IS_ALDERLAKE_S(__i915) && \
708 IS_DISPLAY_STEP(__i915, since, until))
709
710#define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \
711 (IS_ALDERLAKE_S(__i915) && \
712 IS_GRAPHICS_STEP(__i915, since, until))
713
714#define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
715 (IS_ALDERLAKE_P(__i915) && \
716 IS_DISPLAY_STEP(__i915, since, until))
717
718#define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \
719 (IS_ALDERLAKE_P(__i915) && \
720 IS_GRAPHICS_STEP(__i915, since, until))
721
722#define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
723 (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
724
725#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
726 (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
727 IS_GRAPHICS_STEP(__i915, since, until))
728
729/*
730 * DG2 hardware steppings are a bit unusual. The hardware design was forked to
731 * create three variants (G10, G11, and G12) which each have distinct
732 * workaround sets. The G11 and G12 forks of the DG2 design reset the GT
733 * stepping back to "A0" for their first iterations, even though they're more
734 * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of
735 * functionality and workarounds. However the display stepping does not reset
736 * in the same manner --- a specific stepping like "B0" has a consistent
737 * meaning regardless of whether it belongs to a G10, G11, or G12 DG2.
738 *
739 * TLDR: All GT workarounds and stepping-specific logic must be applied in
740 * relation to a specific subplatform (G10/G11/G12), whereas display workarounds
741 * and stepping-specific logic will be applied with a general DG2-wide stepping
742 * number.
743 */
744#define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \
745 (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
746 IS_GRAPHICS_STEP(__i915, since, until))
747
748#define IS_DG2_DISPLAY_STEP(__i915, since, until) \
749 (IS_DG2(__i915) && \
750 IS_DISPLAY_STEP(__i915, since, until))
751
752#define IS_PVC_BD_STEP(__i915, since, until) \
753 (IS_PONTEVECCHIO(__i915) && \
754 IS_BASEDIE_STEP(__i915, since, until))
755
756#define IS_PVC_CT_STEP(__i915, since, until) \
757 (IS_PONTEVECCHIO(__i915) && \
758 IS_GRAPHICS_STEP(__i915, since, until))
759
760#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
761#define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
762#define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
763
764#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
765#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
766
767#define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \
768 unsigned int first__ = (first); \
769 unsigned int count__ = (count); \
770 ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \
771})
772
773#define ENGINE_INSTANCES_MASK(gt, first, count) \
774 __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
775
776#define RCS_MASK(gt) \
777 ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
778#define BCS_MASK(gt) \
779 ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
780#define VDBOX_MASK(gt) \
781 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
782#define VEBOX_MASK(gt) \
783 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
784#define CCS_MASK(gt) \
785 ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
786
787#define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode)
788
789/*
790 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
791 * All later gens can run the final buffer from the ppgtt
792 */
793#define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
794
795#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
796#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
797#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
798#define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
799#define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
800#define HAS_WT(dev_priv) HAS_EDRAM(dev_priv)
801
802#define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
803
804#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
805 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
806#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
807 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
808
809#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
810
811#define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type)
812#define HAS_PPGTT(dev_priv) \
813 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
814#define HAS_FULL_PPGTT(dev_priv) \
815 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
816
817#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
818 GEM_BUG_ON((sizes) == 0); \
819 ((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \
820})
821
822#define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
823#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
824 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
825
826/* Early gen2 have a totally busted CS tlb and require pinned batches. */
827#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
828
829#define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \
830 (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
831
832/* WaRsDisableCoarsePowerGating:skl,cnl */
833#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
834 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
835
836#define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4)
837#define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \
838 IS_GEMINILAKE(dev_priv) || \
839 IS_KABYLAKE(dev_priv))
840
841/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
842 * rows, which changed the alignment requirements and fence programming.
843 */
844#define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
845 !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
846#define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
847#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
848
849#define HAS_FW_BLC(dev_priv) (DISPLAY_VER(dev_priv) > 2)
850#define HAS_FBC(dev_priv) (RUNTIME_INFO(dev_priv)->fbc_mask != 0)
851#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7)
852
853#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
854
855#define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
856#define HAS_DP20(dev_priv) (IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
857
858#define HAS_DOUBLE_BUFFERED_M_N(dev_priv) (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
859
860#define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
861#define HAS_CDCLK_SQUASH(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_squash)
862#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
863#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
864#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
865#define HAS_PSR_HW_TRACKING(dev_priv) \
866 (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
867#define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12)
868#define HAS_TRANSCODER(dev_priv, trans) ((RUNTIME_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
869
870#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
871#define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
872#define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
873
874#define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
875
876#define HAS_DMC(dev_priv) (RUNTIME_INFO(dev_priv)->has_dmc)
877
878#define HAS_HECI_PXP(dev_priv) \
879 (INTEL_INFO(dev_priv)->has_heci_pxp)
880
881#define HAS_HECI_GSCFI(dev_priv) \
882 (INTEL_INFO(dev_priv)->has_heci_gscfi)
883
884#define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv))
885
886#define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
887
888#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
889#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
890
891#define HAS_OA_BPC_REPORTING(dev_priv) \
892 (INTEL_INFO(dev_priv)->has_oa_bpc_reporting)
893#define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \
894 (INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits)
895
896/*
897 * Set this flag, when platform requires 64K GTT page sizes or larger for
898 * device local memory access.
899 */
900#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
901
902#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
903
904#define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
905#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
906
907#define HAS_EXTRA_GT_LIST(dev_priv) (INTEL_INFO(dev_priv)->extra_gt_list)
908
909/*
910 * Platform has the dedicated compression control state for each lmem surfaces
911 * stored in lmem to support the 3D and media compression formats.
912 */
913#define HAS_FLAT_CCS(dev_priv) (INTEL_INFO(dev_priv)->has_flat_ccs)
914
915#define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
916
917#define HAS_POOLED_EU(dev_priv) (RUNTIME_INFO(dev_priv)->has_pooled_eu)
918
919#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
920
921#define HAS_PXP(dev_priv) ((IS_ENABLED(CONFIG_DRM_I915_PXP) && \
922 INTEL_INFO(dev_priv)->has_pxp) && \
923 VDBOX_MASK(to_gt(dev_priv)))
924
925#define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
926
927#define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
928
929#define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
930
931#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
932
933/* DPF == dynamic parity feature */
934#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
935#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
936 2 : HAS_L3_DPF(dev_priv))
937
938#define GT_FREQUENCY_MULTIPLIER 50
939#define GEN9_FREQ_SCALER 3
940
941#define INTEL_NUM_PIPES(dev_priv) (hweight8(RUNTIME_INFO(dev_priv)->pipe_mask))
942
943#define HAS_DISPLAY(dev_priv) (RUNTIME_INFO(dev_priv)->pipe_mask != 0)
944
945#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
946
947#define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
948
949/* Only valid when HAS_DISPLAY() is true */
950#define INTEL_DISPLAY_ENABLED(dev_priv) \
951 (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), \
952 !(dev_priv)->params.disable_display && \
953 !intel_opregion_headless_sku(dev_priv))
954
955#define HAS_GUC_DEPRIVILEGE(dev_priv) \
956 (INTEL_INFO(dev_priv)->has_guc_deprivilege)
957
958#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
959 IS_ALDERLAKE_S(dev_priv))
960
961#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
962
963#define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
964
965#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
966
967#define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
968 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
969
970/* intel_device_info.c */
971static inline struct intel_device_info *
972mkwrite_device_info(struct drm_i915_private *dev_priv)
973{
974 return (struct intel_device_info *)INTEL_INFO(dev_priv);
975}
976
977#endif
1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include "i915_reg.h"
34#include "intel_bios.h"
35#include "intel_ringbuffer.h"
36#include <linux/io-mapping.h>
37#include <linux/i2c.h>
38#include <linux/i2c-algo-bit.h>
39#include <drm/intel-gtt.h>
40#include <linux/backlight.h>
41#include <linux/intel-iommu.h>
42#include <linux/kref.h>
43
44/* General customization:
45 */
46
47#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
48
49#define DRIVER_NAME "i915"
50#define DRIVER_DESC "Intel Graphics"
51#define DRIVER_DATE "20080730"
52
53enum pipe {
54 PIPE_A = 0,
55 PIPE_B,
56 PIPE_C,
57 I915_MAX_PIPES
58};
59#define pipe_name(p) ((p) + 'A')
60
61enum plane {
62 PLANE_A = 0,
63 PLANE_B,
64 PLANE_C,
65};
66#define plane_name(p) ((p) + 'A')
67
68enum port {
69 PORT_A = 0,
70 PORT_B,
71 PORT_C,
72 PORT_D,
73 PORT_E,
74 I915_MAX_PORTS
75};
76#define port_name(p) ((p) + 'A')
77
78#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
79
80#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
81
82struct intel_pch_pll {
83 int refcount; /* count of number of CRTCs sharing this PLL */
84 int active; /* count of number of active CRTCs (i.e. DPMS on) */
85 bool on; /* is the PLL actually active? Disabled during modeset */
86 int pll_reg;
87 int fp0_reg;
88 int fp1_reg;
89};
90#define I915_NUM_PLLS 2
91
92/* Interface history:
93 *
94 * 1.1: Original.
95 * 1.2: Add Power Management
96 * 1.3: Add vblank support
97 * 1.4: Fix cmdbuffer path, add heap destroy
98 * 1.5: Add vblank pipe configuration
99 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
100 * - Support vertical blank on secondary display pipe
101 */
102#define DRIVER_MAJOR 1
103#define DRIVER_MINOR 6
104#define DRIVER_PATCHLEVEL 0
105
106#define WATCH_COHERENCY 0
107#define WATCH_LISTS 0
108
109#define I915_GEM_PHYS_CURSOR_0 1
110#define I915_GEM_PHYS_CURSOR_1 2
111#define I915_GEM_PHYS_OVERLAY_REGS 3
112#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
113
114struct drm_i915_gem_phys_object {
115 int id;
116 struct page **page_list;
117 drm_dma_handle_t *handle;
118 struct drm_i915_gem_object *cur_obj;
119};
120
121struct mem_block {
122 struct mem_block *next;
123 struct mem_block *prev;
124 int start;
125 int size;
126 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
127};
128
129struct opregion_header;
130struct opregion_acpi;
131struct opregion_swsci;
132struct opregion_asle;
133struct drm_i915_private;
134
135struct intel_opregion {
136 struct opregion_header __iomem *header;
137 struct opregion_acpi __iomem *acpi;
138 struct opregion_swsci __iomem *swsci;
139 struct opregion_asle __iomem *asle;
140 void __iomem *vbt;
141 u32 __iomem *lid_state;
142};
143#define OPREGION_SIZE (8*1024)
144
145struct intel_overlay;
146struct intel_overlay_error_state;
147
148struct drm_i915_master_private {
149 drm_local_map_t *sarea;
150 struct _drm_i915_sarea *sarea_priv;
151};
152#define I915_FENCE_REG_NONE -1
153#define I915_MAX_NUM_FENCES 16
154/* 16 fences + sign bit for FENCE_REG_NONE */
155#define I915_MAX_NUM_FENCE_BITS 5
156
157struct drm_i915_fence_reg {
158 struct list_head lru_list;
159 struct drm_i915_gem_object *obj;
160 int pin_count;
161};
162
163struct sdvo_device_mapping {
164 u8 initialized;
165 u8 dvo_port;
166 u8 slave_addr;
167 u8 dvo_wiring;
168 u8 i2c_pin;
169 u8 ddc_pin;
170};
171
172struct intel_display_error_state;
173
174struct drm_i915_error_state {
175 struct kref ref;
176 u32 eir;
177 u32 pgtbl_er;
178 u32 ier;
179 bool waiting[I915_NUM_RINGS];
180 u32 pipestat[I915_MAX_PIPES];
181 u32 tail[I915_NUM_RINGS];
182 u32 head[I915_NUM_RINGS];
183 u32 ipeir[I915_NUM_RINGS];
184 u32 ipehr[I915_NUM_RINGS];
185 u32 instdone[I915_NUM_RINGS];
186 u32 acthd[I915_NUM_RINGS];
187 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
188 /* our own tracking of ring head and tail */
189 u32 cpu_ring_head[I915_NUM_RINGS];
190 u32 cpu_ring_tail[I915_NUM_RINGS];
191 u32 error; /* gen6+ */
192 u32 instpm[I915_NUM_RINGS];
193 u32 instps[I915_NUM_RINGS];
194 u32 instdone1;
195 u32 seqno[I915_NUM_RINGS];
196 u64 bbaddr;
197 u32 fault_reg[I915_NUM_RINGS];
198 u32 done_reg;
199 u32 faddr[I915_NUM_RINGS];
200 u64 fence[I915_MAX_NUM_FENCES];
201 struct timeval time;
202 struct drm_i915_error_ring {
203 struct drm_i915_error_object {
204 int page_count;
205 u32 gtt_offset;
206 u32 *pages[0];
207 } *ringbuffer, *batchbuffer;
208 struct drm_i915_error_request {
209 long jiffies;
210 u32 seqno;
211 u32 tail;
212 } *requests;
213 int num_requests;
214 } ring[I915_NUM_RINGS];
215 struct drm_i915_error_buffer {
216 u32 size;
217 u32 name;
218 u32 seqno;
219 u32 gtt_offset;
220 u32 read_domains;
221 u32 write_domain;
222 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
223 s32 pinned:2;
224 u32 tiling:2;
225 u32 dirty:1;
226 u32 purgeable:1;
227 s32 ring:4;
228 u32 cache_level:2;
229 } *active_bo, *pinned_bo;
230 u32 active_bo_count, pinned_bo_count;
231 struct intel_overlay_error_state *overlay;
232 struct intel_display_error_state *display;
233};
234
235struct drm_i915_display_funcs {
236 void (*dpms)(struct drm_crtc *crtc, int mode);
237 bool (*fbc_enabled)(struct drm_device *dev);
238 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
239 void (*disable_fbc)(struct drm_device *dev);
240 int (*get_display_clock_speed)(struct drm_device *dev);
241 int (*get_fifo_size)(struct drm_device *dev, int plane);
242 void (*update_wm)(struct drm_device *dev);
243 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
244 uint32_t sprite_width, int pixel_size);
245 void (*sanitize_pm)(struct drm_device *dev);
246 void (*update_linetime_wm)(struct drm_device *dev, int pipe,
247 struct drm_display_mode *mode);
248 int (*crtc_mode_set)(struct drm_crtc *crtc,
249 struct drm_display_mode *mode,
250 struct drm_display_mode *adjusted_mode,
251 int x, int y,
252 struct drm_framebuffer *old_fb);
253 void (*off)(struct drm_crtc *crtc);
254 void (*write_eld)(struct drm_connector *connector,
255 struct drm_crtc *crtc);
256 void (*fdi_link_train)(struct drm_crtc *crtc);
257 void (*init_clock_gating)(struct drm_device *dev);
258 void (*init_pch_clock_gating)(struct drm_device *dev);
259 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
260 struct drm_framebuffer *fb,
261 struct drm_i915_gem_object *obj);
262 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
263 int x, int y);
264 void (*force_wake_get)(struct drm_i915_private *dev_priv);
265 void (*force_wake_put)(struct drm_i915_private *dev_priv);
266 /* clock updates for mode set */
267 /* cursor updates */
268 /* render clock increase/decrease */
269 /* display clock increase/decrease */
270 /* pll clock increase/decrease */
271};
272
273struct intel_device_info {
274 u8 gen;
275 u8 is_mobile:1;
276 u8 is_i85x:1;
277 u8 is_i915g:1;
278 u8 is_i945gm:1;
279 u8 is_g33:1;
280 u8 need_gfx_hws:1;
281 u8 is_g4x:1;
282 u8 is_pineview:1;
283 u8 is_broadwater:1;
284 u8 is_crestline:1;
285 u8 is_ivybridge:1;
286 u8 is_valleyview:1;
287 u8 has_pch_split:1;
288 u8 has_force_wake:1;
289 u8 is_haswell:1;
290 u8 has_fbc:1;
291 u8 has_pipe_cxsr:1;
292 u8 has_hotplug:1;
293 u8 cursor_needs_physical:1;
294 u8 has_overlay:1;
295 u8 overlay_needs_physical:1;
296 u8 supports_tv:1;
297 u8 has_bsd_ring:1;
298 u8 has_blt_ring:1;
299 u8 has_llc:1;
300};
301
302#define I915_PPGTT_PD_ENTRIES 512
303#define I915_PPGTT_PT_ENTRIES 1024
304struct i915_hw_ppgtt {
305 unsigned num_pd_entries;
306 struct page **pt_pages;
307 uint32_t pd_offset;
308 dma_addr_t *pt_dma_addr;
309 dma_addr_t scratch_page_dma_addr;
310};
311
312enum no_fbc_reason {
313 FBC_NO_OUTPUT, /* no outputs enabled to compress */
314 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
315 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
316 FBC_MODE_TOO_LARGE, /* mode too large for compression */
317 FBC_BAD_PLANE, /* fbc not supported on plane */
318 FBC_NOT_TILED, /* buffer not tiled */
319 FBC_MULTIPLE_PIPES, /* more than one pipe active */
320 FBC_MODULE_PARAM,
321};
322
323enum intel_pch {
324 PCH_IBX, /* Ibexpeak PCH */
325 PCH_CPT, /* Cougarpoint PCH */
326 PCH_LPT, /* Lynxpoint PCH */
327};
328
329#define QUIRK_PIPEA_FORCE (1<<0)
330#define QUIRK_LVDS_SSC_DISABLE (1<<1)
331#define QUIRK_INVERT_BRIGHTNESS (1<<2)
332
333struct intel_fbdev;
334struct intel_fbc_work;
335
336struct intel_gmbus {
337 struct i2c_adapter adapter;
338 bool force_bit;
339 u32 reg0;
340 u32 gpio_reg;
341 struct i2c_algo_bit_data bit_algo;
342 struct drm_i915_private *dev_priv;
343};
344
345typedef struct drm_i915_private {
346 struct drm_device *dev;
347
348 const struct intel_device_info *info;
349
350 int relative_constants_mode;
351
352 void __iomem *regs;
353 /** gt_fifo_count and the subsequent register write are synchronized
354 * with dev->struct_mutex. */
355 unsigned gt_fifo_count;
356 /** forcewake_count is protected by gt_lock */
357 unsigned forcewake_count;
358 /** gt_lock is also taken in irq contexts. */
359 struct spinlock gt_lock;
360
361 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
362
363 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
364 * controller on different i2c buses. */
365 struct mutex gmbus_mutex;
366
367 /**
368 * Base address of the gmbus and gpio block.
369 */
370 uint32_t gpio_mmio_base;
371
372 struct pci_dev *bridge_dev;
373 struct intel_ring_buffer ring[I915_NUM_RINGS];
374 uint32_t next_seqno;
375
376 drm_dma_handle_t *status_page_dmah;
377 uint32_t counter;
378 struct drm_i915_gem_object *pwrctx;
379 struct drm_i915_gem_object *renderctx;
380
381 struct resource mch_res;
382
383 unsigned int cpp;
384 int back_offset;
385 int front_offset;
386 int current_page;
387 int page_flipping;
388
389 atomic_t irq_received;
390
391 /* protects the irq masks */
392 spinlock_t irq_lock;
393
394 /* DPIO indirect register protection */
395 spinlock_t dpio_lock;
396
397 /** Cached value of IMR to avoid reads in updating the bitfield */
398 u32 pipestat[2];
399 u32 irq_mask;
400 u32 gt_irq_mask;
401 u32 pch_irq_mask;
402
403 u32 hotplug_supported_mask;
404 struct work_struct hotplug_work;
405
406 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
407 int num_pipe;
408 int num_pch_pll;
409
410 /* For hangcheck timer */
411#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
412 struct timer_list hangcheck_timer;
413 int hangcheck_count;
414 uint32_t last_acthd[I915_NUM_RINGS];
415 uint32_t last_instdone;
416 uint32_t last_instdone1;
417
418 unsigned int stop_rings;
419
420 unsigned long cfb_size;
421 unsigned int cfb_fb;
422 enum plane cfb_plane;
423 int cfb_y;
424 struct intel_fbc_work *fbc_work;
425
426 struct intel_opregion opregion;
427
428 /* overlay */
429 struct intel_overlay *overlay;
430 bool sprite_scaling_enabled;
431
432 /* LVDS info */
433 int backlight_level; /* restore backlight to this value */
434 bool backlight_enabled;
435 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
436 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
437
438 /* Feature bits from the VBIOS */
439 unsigned int int_tv_support:1;
440 unsigned int lvds_dither:1;
441 unsigned int lvds_vbt:1;
442 unsigned int int_crt_support:1;
443 unsigned int lvds_use_ssc:1;
444 unsigned int display_clock_mode:1;
445 int lvds_ssc_freq;
446 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
447 unsigned int lvds_val; /* used for checking LVDS channel mode */
448 struct {
449 int rate;
450 int lanes;
451 int preemphasis;
452 int vswing;
453
454 bool initialized;
455 bool support;
456 int bpp;
457 struct edp_power_seq pps;
458 } edp;
459 bool no_aux_handshake;
460
461 struct notifier_block lid_notifier;
462
463 int crt_ddc_pin;
464 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
465 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
466 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
467
468 unsigned int fsb_freq, mem_freq, is_ddr3;
469
470 spinlock_t error_lock;
471 /* Protected by dev->error_lock. */
472 struct drm_i915_error_state *first_error;
473 struct work_struct error_work;
474 struct completion error_completion;
475 struct workqueue_struct *wq;
476
477 /* Display functions */
478 struct drm_i915_display_funcs display;
479
480 /* PCH chipset type */
481 enum intel_pch pch_type;
482
483 unsigned long quirks;
484
485 /* Register state */
486 bool modeset_on_lid;
487 u8 saveLBB;
488 u32 saveDSPACNTR;
489 u32 saveDSPBCNTR;
490 u32 saveDSPARB;
491 u32 saveHWS;
492 u32 savePIPEACONF;
493 u32 savePIPEBCONF;
494 u32 savePIPEASRC;
495 u32 savePIPEBSRC;
496 u32 saveFPA0;
497 u32 saveFPA1;
498 u32 saveDPLL_A;
499 u32 saveDPLL_A_MD;
500 u32 saveHTOTAL_A;
501 u32 saveHBLANK_A;
502 u32 saveHSYNC_A;
503 u32 saveVTOTAL_A;
504 u32 saveVBLANK_A;
505 u32 saveVSYNC_A;
506 u32 saveBCLRPAT_A;
507 u32 saveTRANSACONF;
508 u32 saveTRANS_HTOTAL_A;
509 u32 saveTRANS_HBLANK_A;
510 u32 saveTRANS_HSYNC_A;
511 u32 saveTRANS_VTOTAL_A;
512 u32 saveTRANS_VBLANK_A;
513 u32 saveTRANS_VSYNC_A;
514 u32 savePIPEASTAT;
515 u32 saveDSPASTRIDE;
516 u32 saveDSPASIZE;
517 u32 saveDSPAPOS;
518 u32 saveDSPAADDR;
519 u32 saveDSPASURF;
520 u32 saveDSPATILEOFF;
521 u32 savePFIT_PGM_RATIOS;
522 u32 saveBLC_HIST_CTL;
523 u32 saveBLC_PWM_CTL;
524 u32 saveBLC_PWM_CTL2;
525 u32 saveBLC_CPU_PWM_CTL;
526 u32 saveBLC_CPU_PWM_CTL2;
527 u32 saveFPB0;
528 u32 saveFPB1;
529 u32 saveDPLL_B;
530 u32 saveDPLL_B_MD;
531 u32 saveHTOTAL_B;
532 u32 saveHBLANK_B;
533 u32 saveHSYNC_B;
534 u32 saveVTOTAL_B;
535 u32 saveVBLANK_B;
536 u32 saveVSYNC_B;
537 u32 saveBCLRPAT_B;
538 u32 saveTRANSBCONF;
539 u32 saveTRANS_HTOTAL_B;
540 u32 saveTRANS_HBLANK_B;
541 u32 saveTRANS_HSYNC_B;
542 u32 saveTRANS_VTOTAL_B;
543 u32 saveTRANS_VBLANK_B;
544 u32 saveTRANS_VSYNC_B;
545 u32 savePIPEBSTAT;
546 u32 saveDSPBSTRIDE;
547 u32 saveDSPBSIZE;
548 u32 saveDSPBPOS;
549 u32 saveDSPBADDR;
550 u32 saveDSPBSURF;
551 u32 saveDSPBTILEOFF;
552 u32 saveVGA0;
553 u32 saveVGA1;
554 u32 saveVGA_PD;
555 u32 saveVGACNTRL;
556 u32 saveADPA;
557 u32 saveLVDS;
558 u32 savePP_ON_DELAYS;
559 u32 savePP_OFF_DELAYS;
560 u32 saveDVOA;
561 u32 saveDVOB;
562 u32 saveDVOC;
563 u32 savePP_ON;
564 u32 savePP_OFF;
565 u32 savePP_CONTROL;
566 u32 savePP_DIVISOR;
567 u32 savePFIT_CONTROL;
568 u32 save_palette_a[256];
569 u32 save_palette_b[256];
570 u32 saveDPFC_CB_BASE;
571 u32 saveFBC_CFB_BASE;
572 u32 saveFBC_LL_BASE;
573 u32 saveFBC_CONTROL;
574 u32 saveFBC_CONTROL2;
575 u32 saveIER;
576 u32 saveIIR;
577 u32 saveIMR;
578 u32 saveDEIER;
579 u32 saveDEIMR;
580 u32 saveGTIER;
581 u32 saveGTIMR;
582 u32 saveFDI_RXA_IMR;
583 u32 saveFDI_RXB_IMR;
584 u32 saveCACHE_MODE_0;
585 u32 saveMI_ARB_STATE;
586 u32 saveSWF0[16];
587 u32 saveSWF1[16];
588 u32 saveSWF2[3];
589 u8 saveMSR;
590 u8 saveSR[8];
591 u8 saveGR[25];
592 u8 saveAR_INDEX;
593 u8 saveAR[21];
594 u8 saveDACMASK;
595 u8 saveCR[37];
596 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
597 u32 saveCURACNTR;
598 u32 saveCURAPOS;
599 u32 saveCURABASE;
600 u32 saveCURBCNTR;
601 u32 saveCURBPOS;
602 u32 saveCURBBASE;
603 u32 saveCURSIZE;
604 u32 saveDP_B;
605 u32 saveDP_C;
606 u32 saveDP_D;
607 u32 savePIPEA_GMCH_DATA_M;
608 u32 savePIPEB_GMCH_DATA_M;
609 u32 savePIPEA_GMCH_DATA_N;
610 u32 savePIPEB_GMCH_DATA_N;
611 u32 savePIPEA_DP_LINK_M;
612 u32 savePIPEB_DP_LINK_M;
613 u32 savePIPEA_DP_LINK_N;
614 u32 savePIPEB_DP_LINK_N;
615 u32 saveFDI_RXA_CTL;
616 u32 saveFDI_TXA_CTL;
617 u32 saveFDI_RXB_CTL;
618 u32 saveFDI_TXB_CTL;
619 u32 savePFA_CTL_1;
620 u32 savePFB_CTL_1;
621 u32 savePFA_WIN_SZ;
622 u32 savePFB_WIN_SZ;
623 u32 savePFA_WIN_POS;
624 u32 savePFB_WIN_POS;
625 u32 savePCH_DREF_CONTROL;
626 u32 saveDISP_ARB_CTL;
627 u32 savePIPEA_DATA_M1;
628 u32 savePIPEA_DATA_N1;
629 u32 savePIPEA_LINK_M1;
630 u32 savePIPEA_LINK_N1;
631 u32 savePIPEB_DATA_M1;
632 u32 savePIPEB_DATA_N1;
633 u32 savePIPEB_LINK_M1;
634 u32 savePIPEB_LINK_N1;
635 u32 saveMCHBAR_RENDER_STANDBY;
636 u32 savePCH_PORT_HOTPLUG;
637
638 struct {
639 /** Bridge to intel-gtt-ko */
640 const struct intel_gtt *gtt;
641 /** Memory allocator for GTT stolen memory */
642 struct drm_mm stolen;
643 /** Memory allocator for GTT */
644 struct drm_mm gtt_space;
645 /** List of all objects in gtt_space. Used to restore gtt
646 * mappings on resume */
647 struct list_head gtt_list;
648
649 /** Usable portion of the GTT for GEM */
650 unsigned long gtt_start;
651 unsigned long gtt_mappable_end;
652 unsigned long gtt_end;
653
654 struct io_mapping *gtt_mapping;
655 int gtt_mtrr;
656
657 /** PPGTT used for aliasing the PPGTT with the GTT */
658 struct i915_hw_ppgtt *aliasing_ppgtt;
659
660 struct shrinker inactive_shrinker;
661
662 /**
663 * List of objects currently involved in rendering.
664 *
665 * Includes buffers having the contents of their GPU caches
666 * flushed, not necessarily primitives. last_rendering_seqno
667 * represents when the rendering involved will be completed.
668 *
669 * A reference is held on the buffer while on this list.
670 */
671 struct list_head active_list;
672
673 /**
674 * List of objects which are not in the ringbuffer but which
675 * still have a write_domain which needs to be flushed before
676 * unbinding.
677 *
678 * last_rendering_seqno is 0 while an object is in this list.
679 *
680 * A reference is held on the buffer while on this list.
681 */
682 struct list_head flushing_list;
683
684 /**
685 * LRU list of objects which are not in the ringbuffer and
686 * are ready to unbind, but are still in the GTT.
687 *
688 * last_rendering_seqno is 0 while an object is in this list.
689 *
690 * A reference is not held on the buffer while on this list,
691 * as merely being GTT-bound shouldn't prevent its being
692 * freed, and we'll pull it off the list in the free path.
693 */
694 struct list_head inactive_list;
695
696 /** LRU list of objects with fence regs on them. */
697 struct list_head fence_list;
698
699 /**
700 * We leave the user IRQ off as much as possible,
701 * but this means that requests will finish and never
702 * be retired once the system goes idle. Set a timer to
703 * fire periodically while the ring is running. When it
704 * fires, go retire requests.
705 */
706 struct delayed_work retire_work;
707
708 /**
709 * Are we in a non-interruptible section of code like
710 * modesetting?
711 */
712 bool interruptible;
713
714 /**
715 * Flag if the X Server, and thus DRM, is not currently in
716 * control of the device.
717 *
718 * This is set between LeaveVT and EnterVT. It needs to be
719 * replaced with a semaphore. It also needs to be
720 * transitioned away from for kernel modesetting.
721 */
722 int suspended;
723
724 /**
725 * Flag if the hardware appears to be wedged.
726 *
727 * This is set when attempts to idle the device timeout.
728 * It prevents command submission from occurring and makes
729 * every pending request fail
730 */
731 atomic_t wedged;
732
733 /** Bit 6 swizzling required for X tiling */
734 uint32_t bit_6_swizzle_x;
735 /** Bit 6 swizzling required for Y tiling */
736 uint32_t bit_6_swizzle_y;
737
738 /* storage for physical objects */
739 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
740
741 /* accounting, useful for userland debugging */
742 size_t gtt_total;
743 size_t mappable_gtt_total;
744 size_t object_memory;
745 u32 object_count;
746 } mm;
747
748 /* Old dri1 support infrastructure, beware the dragons ya fools entering
749 * here! */
750 struct {
751 unsigned allow_batchbuffer : 1;
752 u32 __iomem *gfx_hws_cpu_addr;
753 } dri1;
754
755 /* Kernel Modesetting */
756
757 struct sdvo_device_mapping sdvo_mappings[2];
758 /* indicate whether the LVDS_BORDER should be enabled or not */
759 unsigned int lvds_border_bits;
760 /* Panel fitter placement and size for Ironlake+ */
761 u32 pch_pf_pos, pch_pf_size;
762
763 struct drm_crtc *plane_to_crtc_mapping[3];
764 struct drm_crtc *pipe_to_crtc_mapping[3];
765 wait_queue_head_t pending_flip_queue;
766
767 struct intel_pch_pll pch_plls[I915_NUM_PLLS];
768
769 /* Reclocking support */
770 bool render_reclock_avail;
771 bool lvds_downclock_avail;
772 /* indicates the reduced downclock for LVDS*/
773 int lvds_downclock;
774 struct work_struct idle_work;
775 struct timer_list idle_timer;
776 bool busy;
777 u16 orig_clock;
778 int child_dev_num;
779 struct child_device_config *child_dev;
780 struct drm_connector *int_lvds_connector;
781 struct drm_connector *int_edp_connector;
782
783 bool mchbar_need_disable;
784
785 struct work_struct rps_work;
786 spinlock_t rps_lock;
787 u32 pm_iir;
788
789 u8 cur_delay;
790 u8 min_delay;
791 u8 max_delay;
792 u8 fmax;
793 u8 fstart;
794
795 u64 last_count1;
796 unsigned long last_time1;
797 unsigned long chipset_power;
798 u64 last_count2;
799 struct timespec last_time2;
800 unsigned long gfx_power;
801 int c_m;
802 int r_t;
803 u8 corr;
804 spinlock_t *mchdev_lock;
805
806 enum no_fbc_reason no_fbc_reason;
807
808 struct drm_mm_node *compressed_fb;
809 struct drm_mm_node *compressed_llb;
810
811 unsigned long last_gpu_reset;
812
813 /* list of fbdev register on this device */
814 struct intel_fbdev *fbdev;
815
816 struct backlight_device *backlight;
817
818 struct drm_property *broadcast_rgb_property;
819 struct drm_property *force_audio_property;
820} drm_i915_private_t;
821
822/* Iterate over initialised rings */
823#define for_each_ring(ring__, dev_priv__, i__) \
824 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
825 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
826
827enum hdmi_force_audio {
828 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
829 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
830 HDMI_AUDIO_AUTO, /* trust EDID */
831 HDMI_AUDIO_ON, /* force turn on HDMI audio */
832};
833
834enum i915_cache_level {
835 I915_CACHE_NONE,
836 I915_CACHE_LLC,
837 I915_CACHE_LLC_MLC, /* gen6+ */
838};
839
840struct drm_i915_gem_object {
841 struct drm_gem_object base;
842
843 /** Current space allocated to this object in the GTT, if any. */
844 struct drm_mm_node *gtt_space;
845 struct list_head gtt_list;
846
847 /** This object's place on the active/flushing/inactive lists */
848 struct list_head ring_list;
849 struct list_head mm_list;
850 /** This object's place on GPU write list */
851 struct list_head gpu_write_list;
852 /** This object's place in the batchbuffer or on the eviction list */
853 struct list_head exec_list;
854
855 /**
856 * This is set if the object is on the active or flushing lists
857 * (has pending rendering), and is not set if it's on inactive (ready
858 * to be unbound).
859 */
860 unsigned int active:1;
861
862 /**
863 * This is set if the object has been written to since last bound
864 * to the GTT
865 */
866 unsigned int dirty:1;
867
868 /**
869 * This is set if the object has been written to since the last
870 * GPU flush.
871 */
872 unsigned int pending_gpu_write:1;
873
874 /**
875 * Fence register bits (if any) for this object. Will be set
876 * as needed when mapped into the GTT.
877 * Protected by dev->struct_mutex.
878 */
879 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
880
881 /**
882 * Advice: are the backing pages purgeable?
883 */
884 unsigned int madv:2;
885
886 /**
887 * Current tiling mode for the object.
888 */
889 unsigned int tiling_mode:2;
890 /**
891 * Whether the tiling parameters for the currently associated fence
892 * register have changed. Note that for the purposes of tracking
893 * tiling changes we also treat the unfenced register, the register
894 * slot that the object occupies whilst it executes a fenced
895 * command (such as BLT on gen2/3), as a "fence".
896 */
897 unsigned int fence_dirty:1;
898
899 /** How many users have pinned this object in GTT space. The following
900 * users can each hold at most one reference: pwrite/pread, pin_ioctl
901 * (via user_pin_count), execbuffer (objects are not allowed multiple
902 * times for the same batchbuffer), and the framebuffer code. When
903 * switching/pageflipping, the framebuffer code has at most two buffers
904 * pinned per crtc.
905 *
906 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
907 * bits with absolutely no headroom. So use 4 bits. */
908 unsigned int pin_count:4;
909#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
910
911 /**
912 * Is the object at the current location in the gtt mappable and
913 * fenceable? Used to avoid costly recalculations.
914 */
915 unsigned int map_and_fenceable:1;
916
917 /**
918 * Whether the current gtt mapping needs to be mappable (and isn't just
919 * mappable by accident). Track pin and fault separate for a more
920 * accurate mappable working set.
921 */
922 unsigned int fault_mappable:1;
923 unsigned int pin_mappable:1;
924
925 /*
926 * Is the GPU currently using a fence to access this buffer,
927 */
928 unsigned int pending_fenced_gpu_access:1;
929 unsigned int fenced_gpu_access:1;
930
931 unsigned int cache_level:2;
932
933 unsigned int has_aliasing_ppgtt_mapping:1;
934 unsigned int has_global_gtt_mapping:1;
935
936 struct page **pages;
937
938 /**
939 * DMAR support
940 */
941 struct scatterlist *sg_list;
942 int num_sg;
943
944 /* prime dma-buf support */
945 struct sg_table *sg_table;
946 void *dma_buf_vmapping;
947 int vmapping_count;
948
949 /**
950 * Used for performing relocations during execbuffer insertion.
951 */
952 struct hlist_node exec_node;
953 unsigned long exec_handle;
954 struct drm_i915_gem_exec_object2 *exec_entry;
955
956 /**
957 * Current offset of the object in GTT space.
958 *
959 * This is the same as gtt_space->start
960 */
961 uint32_t gtt_offset;
962
963 struct intel_ring_buffer *ring;
964
965 /** Breadcrumb of last rendering to the buffer. */
966 uint32_t last_rendering_seqno;
967 /** Breadcrumb of last fenced GPU access to the buffer. */
968 uint32_t last_fenced_seqno;
969
970 /** Current tiling stride for the object, if it's tiled. */
971 uint32_t stride;
972
973 /** Record of address bit 17 of each page at last unbind. */
974 unsigned long *bit_17;
975
976 /** User space pin count and filp owning the pin */
977 uint32_t user_pin_count;
978 struct drm_file *pin_filp;
979
980 /** for phy allocated objects */
981 struct drm_i915_gem_phys_object *phys_obj;
982
983 /**
984 * Number of crtcs where this object is currently the fb, but
985 * will be page flipped away on the next vblank. When it
986 * reaches 0, dev_priv->pending_flip_queue will be woken up.
987 */
988 atomic_t pending_flip;
989};
990
991#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
992
993/**
994 * Request queue structure.
995 *
996 * The request queue allows us to note sequence numbers that have been emitted
997 * and may be associated with active buffers to be retired.
998 *
999 * By keeping this list, we can avoid having to do questionable
1000 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1001 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1002 */
1003struct drm_i915_gem_request {
1004 /** On Which ring this request was generated */
1005 struct intel_ring_buffer *ring;
1006
1007 /** GEM sequence number associated with this request. */
1008 uint32_t seqno;
1009
1010 /** Postion in the ringbuffer of the end of the request */
1011 u32 tail;
1012
1013 /** Time at which this request was emitted, in jiffies. */
1014 unsigned long emitted_jiffies;
1015
1016 /** global list entry for this request */
1017 struct list_head list;
1018
1019 struct drm_i915_file_private *file_priv;
1020 /** file_priv list entry for this request */
1021 struct list_head client_list;
1022};
1023
1024struct drm_i915_file_private {
1025 struct {
1026 struct spinlock lock;
1027 struct list_head request_list;
1028 } mm;
1029};
1030
1031#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1032
1033#define IS_I830(dev) ((dev)->pci_device == 0x3577)
1034#define IS_845G(dev) ((dev)->pci_device == 0x2562)
1035#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1036#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1037#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1038#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1039#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1040#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1041#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1042#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1043#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1044#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1045#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1046#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1047#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1048#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1049#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1050#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1051#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1052#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1053#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1054#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1055
1056/*
1057 * The genX designation typically refers to the render engine, so render
1058 * capability related checks should use IS_GEN, while display and other checks
1059 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1060 * chips, etc.).
1061 */
1062#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1063#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1064#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1065#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1066#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1067#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1068
1069#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1070#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1071#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1072#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1073
1074#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6)
1075
1076#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1077#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1078
1079/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1080 * rows, which changed the alignment requirements and fence programming.
1081 */
1082#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1083 IS_I915GM(dev)))
1084#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1085#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1086#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1087#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1088#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1089#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1090/* dsparb controlled by hw only */
1091#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1092
1093#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1094#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1095#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1096
1097#define HAS_PCH_SPLIT(dev) (INTEL_INFO(dev)->has_pch_split)
1098#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1099
1100#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1101#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1102#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1103#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1104
1105#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1106
1107#include "i915_trace.h"
1108
1109/**
1110 * RC6 is a special power stage which allows the GPU to enter an very
1111 * low-voltage mode when idle, using down to 0V while at this stage. This
1112 * stage is entered automatically when the GPU is idle when RC6 support is
1113 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1114 *
1115 * There are different RC6 modes available in Intel GPU, which differentiate
1116 * among each other with the latency required to enter and leave RC6 and
1117 * voltage consumed by the GPU in different states.
1118 *
1119 * The combination of the following flags define which states GPU is allowed
1120 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1121 * RC6pp is deepest RC6. Their support by hardware varies according to the
1122 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1123 * which brings the most power savings; deeper states save more power, but
1124 * require higher latency to switch to and wake up.
1125 */
1126#define INTEL_RC6_ENABLE (1<<0)
1127#define INTEL_RC6p_ENABLE (1<<1)
1128#define INTEL_RC6pp_ENABLE (1<<2)
1129
1130extern struct drm_ioctl_desc i915_ioctls[];
1131extern int i915_max_ioctl;
1132extern unsigned int i915_fbpercrtc __always_unused;
1133extern int i915_panel_ignore_lid __read_mostly;
1134extern unsigned int i915_powersave __read_mostly;
1135extern int i915_semaphores __read_mostly;
1136extern unsigned int i915_lvds_downclock __read_mostly;
1137extern int i915_lvds_channel_mode __read_mostly;
1138extern int i915_panel_use_ssc __read_mostly;
1139extern int i915_vbt_sdvo_panel_type __read_mostly;
1140extern int i915_enable_rc6 __read_mostly;
1141extern int i915_enable_fbc __read_mostly;
1142extern bool i915_enable_hangcheck __read_mostly;
1143extern int i915_enable_ppgtt __read_mostly;
1144
1145extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1146extern int i915_resume(struct drm_device *dev);
1147extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1148extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1149
1150 /* i915_dma.c */
1151void i915_update_dri1_breadcrumb(struct drm_device *dev);
1152extern void i915_kernel_lost_context(struct drm_device * dev);
1153extern int i915_driver_load(struct drm_device *, unsigned long flags);
1154extern int i915_driver_unload(struct drm_device *);
1155extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1156extern void i915_driver_lastclose(struct drm_device * dev);
1157extern void i915_driver_preclose(struct drm_device *dev,
1158 struct drm_file *file_priv);
1159extern void i915_driver_postclose(struct drm_device *dev,
1160 struct drm_file *file_priv);
1161extern int i915_driver_device_is_agp(struct drm_device * dev);
1162#ifdef CONFIG_COMPAT
1163extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1164 unsigned long arg);
1165#endif
1166extern int i915_emit_box(struct drm_device *dev,
1167 struct drm_clip_rect *box,
1168 int DR1, int DR4);
1169extern int i915_reset(struct drm_device *dev);
1170extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1171extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1172extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1173extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1174
1175
1176/* i915_irq.c */
1177void i915_hangcheck_elapsed(unsigned long data);
1178void i915_handle_error(struct drm_device *dev, bool wedged);
1179
1180extern void intel_irq_init(struct drm_device *dev);
1181
1182void i915_error_state_free(struct kref *error_ref);
1183
1184void
1185i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1186
1187void
1188i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1189
1190void intel_enable_asle(struct drm_device *dev);
1191
1192#ifdef CONFIG_DEBUG_FS
1193extern void i915_destroy_error_state(struct drm_device *dev);
1194#else
1195#define i915_destroy_error_state(x)
1196#endif
1197
1198
1199/* i915_gem.c */
1200int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1201 struct drm_file *file_priv);
1202int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1203 struct drm_file *file_priv);
1204int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1205 struct drm_file *file_priv);
1206int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1207 struct drm_file *file_priv);
1208int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1209 struct drm_file *file_priv);
1210int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1211 struct drm_file *file_priv);
1212int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1213 struct drm_file *file_priv);
1214int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1215 struct drm_file *file_priv);
1216int i915_gem_execbuffer(struct drm_device *dev, void *data,
1217 struct drm_file *file_priv);
1218int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1219 struct drm_file *file_priv);
1220int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1221 struct drm_file *file_priv);
1222int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1223 struct drm_file *file_priv);
1224int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1225 struct drm_file *file_priv);
1226int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1227 struct drm_file *file_priv);
1228int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1229 struct drm_file *file_priv);
1230int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1231 struct drm_file *file_priv);
1232int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1233 struct drm_file *file_priv);
1234int i915_gem_set_tiling(struct drm_device *dev, void *data,
1235 struct drm_file *file_priv);
1236int i915_gem_get_tiling(struct drm_device *dev, void *data,
1237 struct drm_file *file_priv);
1238int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1239 struct drm_file *file_priv);
1240void i915_gem_load(struct drm_device *dev);
1241int i915_gem_init_object(struct drm_gem_object *obj);
1242int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
1243 uint32_t invalidate_domains,
1244 uint32_t flush_domains);
1245struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1246 size_t size);
1247void i915_gem_free_object(struct drm_gem_object *obj);
1248int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1249 uint32_t alignment,
1250 bool map_and_fenceable);
1251void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1252int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1253void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1254void i915_gem_lastclose(struct drm_device *dev);
1255
1256int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1257 gfp_t gfpmask);
1258int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1259int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
1260int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1261 struct intel_ring_buffer *to);
1262void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1263 struct intel_ring_buffer *ring,
1264 u32 seqno);
1265
1266int i915_gem_dumb_create(struct drm_file *file_priv,
1267 struct drm_device *dev,
1268 struct drm_mode_create_dumb *args);
1269int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1270 uint32_t handle, uint64_t *offset);
1271int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1272 uint32_t handle);
1273/**
1274 * Returns true if seq1 is later than seq2.
1275 */
1276static inline bool
1277i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1278{
1279 return (int32_t)(seq1 - seq2) >= 0;
1280}
1281
1282u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring);
1283
1284int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1285int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1286
1287static inline bool
1288i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1289{
1290 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1291 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1292 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1293 return true;
1294 } else
1295 return false;
1296}
1297
1298static inline void
1299i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1300{
1301 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1302 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1303 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1304 }
1305}
1306
1307void i915_gem_retire_requests(struct drm_device *dev);
1308void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1309
1310void i915_gem_reset(struct drm_device *dev);
1311void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1312int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1313 uint32_t read_domains,
1314 uint32_t write_domain);
1315int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1316int __must_check i915_gem_init(struct drm_device *dev);
1317int __must_check i915_gem_init_hw(struct drm_device *dev);
1318void i915_gem_init_swizzling(struct drm_device *dev);
1319void i915_gem_init_ppgtt(struct drm_device *dev);
1320void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1321int __must_check i915_gpu_idle(struct drm_device *dev);
1322int __must_check i915_gem_idle(struct drm_device *dev);
1323int __must_check i915_add_request(struct intel_ring_buffer *ring,
1324 struct drm_file *file,
1325 struct drm_i915_gem_request *request);
1326int __must_check i915_wait_request(struct intel_ring_buffer *ring,
1327 uint32_t seqno);
1328int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1329int __must_check
1330i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1331 bool write);
1332int __must_check
1333i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1334int __must_check
1335i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1336 u32 alignment,
1337 struct intel_ring_buffer *pipelined);
1338int i915_gem_attach_phys_object(struct drm_device *dev,
1339 struct drm_i915_gem_object *obj,
1340 int id,
1341 int align);
1342void i915_gem_detach_phys_object(struct drm_device *dev,
1343 struct drm_i915_gem_object *obj);
1344void i915_gem_free_all_phys_object(struct drm_device *dev);
1345void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1346
1347uint32_t
1348i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1349 uint32_t size,
1350 int tiling_mode);
1351
1352int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1353 enum i915_cache_level cache_level);
1354
1355struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1356 struct dma_buf *dma_buf);
1357
1358struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1359 struct drm_gem_object *gem_obj, int flags);
1360
1361
1362/* i915_gem_gtt.c */
1363int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1364void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1365void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1366 struct drm_i915_gem_object *obj,
1367 enum i915_cache_level cache_level);
1368void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1369 struct drm_i915_gem_object *obj);
1370
1371void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1372int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1373void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1374 enum i915_cache_level cache_level);
1375void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1376void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1377void i915_gem_init_global_gtt(struct drm_device *dev,
1378 unsigned long start,
1379 unsigned long mappable_end,
1380 unsigned long end);
1381
1382/* i915_gem_evict.c */
1383int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1384 unsigned alignment, bool mappable);
1385int i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only);
1386
1387/* i915_gem_stolen.c */
1388int i915_gem_init_stolen(struct drm_device *dev);
1389void i915_gem_cleanup_stolen(struct drm_device *dev);
1390
1391/* i915_gem_tiling.c */
1392void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1393void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1394void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1395
1396/* i915_gem_debug.c */
1397void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1398 const char *where, uint32_t mark);
1399#if WATCH_LISTS
1400int i915_verify_lists(struct drm_device *dev);
1401#else
1402#define i915_verify_lists(dev) 0
1403#endif
1404void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1405 int handle);
1406void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1407 const char *where, uint32_t mark);
1408
1409/* i915_debugfs.c */
1410int i915_debugfs_init(struct drm_minor *minor);
1411void i915_debugfs_cleanup(struct drm_minor *minor);
1412
1413/* i915_suspend.c */
1414extern int i915_save_state(struct drm_device *dev);
1415extern int i915_restore_state(struct drm_device *dev);
1416
1417/* i915_suspend.c */
1418extern int i915_save_state(struct drm_device *dev);
1419extern int i915_restore_state(struct drm_device *dev);
1420
1421/* i915_sysfs.c */
1422void i915_setup_sysfs(struct drm_device *dev_priv);
1423void i915_teardown_sysfs(struct drm_device *dev_priv);
1424
1425/* intel_i2c.c */
1426extern int intel_setup_gmbus(struct drm_device *dev);
1427extern void intel_teardown_gmbus(struct drm_device *dev);
1428extern inline bool intel_gmbus_is_port_valid(unsigned port)
1429{
1430 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1431}
1432
1433extern struct i2c_adapter *intel_gmbus_get_adapter(
1434 struct drm_i915_private *dev_priv, unsigned port);
1435extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1436extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1437extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1438{
1439 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1440}
1441extern void intel_i2c_reset(struct drm_device *dev);
1442
1443/* intel_opregion.c */
1444extern int intel_opregion_setup(struct drm_device *dev);
1445#ifdef CONFIG_ACPI
1446extern void intel_opregion_init(struct drm_device *dev);
1447extern void intel_opregion_fini(struct drm_device *dev);
1448extern void intel_opregion_asle_intr(struct drm_device *dev);
1449extern void intel_opregion_gse_intr(struct drm_device *dev);
1450extern void intel_opregion_enable_asle(struct drm_device *dev);
1451#else
1452static inline void intel_opregion_init(struct drm_device *dev) { return; }
1453static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1454static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1455static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1456static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1457#endif
1458
1459/* intel_acpi.c */
1460#ifdef CONFIG_ACPI
1461extern void intel_register_dsm_handler(void);
1462extern void intel_unregister_dsm_handler(void);
1463#else
1464static inline void intel_register_dsm_handler(void) { return; }
1465static inline void intel_unregister_dsm_handler(void) { return; }
1466#endif /* CONFIG_ACPI */
1467
1468/* modesetting */
1469extern void intel_modeset_init_hw(struct drm_device *dev);
1470extern void intel_modeset_init(struct drm_device *dev);
1471extern void intel_modeset_gem_init(struct drm_device *dev);
1472extern void intel_modeset_cleanup(struct drm_device *dev);
1473extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1474extern bool intel_fbc_enabled(struct drm_device *dev);
1475extern void intel_disable_fbc(struct drm_device *dev);
1476extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1477extern void ironlake_init_pch_refclk(struct drm_device *dev);
1478extern void ironlake_enable_rc6(struct drm_device *dev);
1479extern void gen6_set_rps(struct drm_device *dev, u8 val);
1480extern void intel_detect_pch(struct drm_device *dev);
1481extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1482extern int intel_enable_rc6(const struct drm_device *dev);
1483
1484extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1485extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1486extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv);
1487extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1488extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
1489
1490extern void vlv_force_wake_get(struct drm_i915_private *dev_priv);
1491extern void vlv_force_wake_put(struct drm_i915_private *dev_priv);
1492
1493/* overlay */
1494#ifdef CONFIG_DEBUG_FS
1495extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1496extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1497
1498extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1499extern void intel_display_print_error_state(struct seq_file *m,
1500 struct drm_device *dev,
1501 struct intel_display_error_state *error);
1502#endif
1503
1504/* On SNB platform, before reading ring registers forcewake bit
1505 * must be set to prevent GT core from power down and stale values being
1506 * returned.
1507 */
1508void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1509void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1510int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1511
1512#define __i915_read(x, y) \
1513 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1514
1515__i915_read(8, b)
1516__i915_read(16, w)
1517__i915_read(32, l)
1518__i915_read(64, q)
1519#undef __i915_read
1520
1521#define __i915_write(x, y) \
1522 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1523
1524__i915_write(8, b)
1525__i915_write(16, w)
1526__i915_write(32, l)
1527__i915_write(64, q)
1528#undef __i915_write
1529
1530#define I915_READ8(reg) i915_read8(dev_priv, (reg))
1531#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1532
1533#define I915_READ16(reg) i915_read16(dev_priv, (reg))
1534#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1535#define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1536#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1537
1538#define I915_READ(reg) i915_read32(dev_priv, (reg))
1539#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1540#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1541#define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1542
1543#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1544#define I915_READ64(reg) i915_read64(dev_priv, (reg))
1545
1546#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1547#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1548
1549
1550#endif