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1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include <uapi/drm/i915_drm.h>
34
35#include <linux/pm_qos.h>
36
37#include <drm/ttm/ttm_device.h>
38
39#include "display/intel_display_limits.h"
40#include "display/intel_display_core.h"
41
42#include "gem/i915_gem_context_types.h"
43#include "gem/i915_gem_shrinker.h"
44#include "gem/i915_gem_stolen.h"
45
46#include "gt/intel_engine.h"
47#include "gt/intel_gt_types.h"
48#include "gt/intel_region_lmem.h"
49#include "gt/intel_workarounds.h"
50#include "gt/uc/intel_uc.h"
51
52#include "soc/intel_pch.h"
53
54#include "i915_drm_client.h"
55#include "i915_gem.h"
56#include "i915_gpu_error.h"
57#include "i915_params.h"
58#include "i915_perf_types.h"
59#include "i915_scheduler.h"
60#include "i915_utils.h"
61#include "intel_device_info.h"
62#include "intel_memory_region.h"
63#include "intel_runtime_pm.h"
64#include "intel_step.h"
65#include "intel_uncore.h"
66
67struct drm_i915_clock_gating_funcs;
68struct vlv_s0ix_state;
69struct intel_pxp;
70
71#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
72
73/* Data Stolen Memory (DSM) aka "i915 stolen memory" */
74struct i915_dsm {
75 /*
76 * The start and end of DSM which we can optionally use to create GEM
77 * objects backed by stolen memory.
78 *
79 * Note that usable_size tells us exactly how much of this we are
80 * actually allowed to use, given that some portion of it is in fact
81 * reserved for use by hardware functions.
82 */
83 struct resource stolen;
84
85 /*
86 * Reserved portion of DSM.
87 */
88 struct resource reserved;
89
90 /*
91 * Total size minus reserved ranges.
92 *
93 * DSM is segmented in hardware with different portions offlimits to
94 * certain functions.
95 *
96 * The drm_mm is initialised to the total accessible range, as found
97 * from the PCI config. On Broadwell+, this is further restricted to
98 * avoid the first page! The upper end of DSM is reserved for hardware
99 * functions and similarly removed from the accessible range.
100 */
101 resource_size_t usable_size;
102};
103
104struct i915_suspend_saved_registers {
105 u32 saveDSPARB;
106 u32 saveSWF0[16];
107 u32 saveSWF1[16];
108 u32 saveSWF3[3];
109 u16 saveGCDGMBUS;
110};
111
112#define MAX_L3_SLICES 2
113struct intel_l3_parity {
114 u32 *remap_info[MAX_L3_SLICES];
115 struct work_struct error_work;
116 int which_slice;
117};
118
119struct i915_gem_mm {
120 /*
121 * Shortcut for the stolen region. This points to either
122 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or
123 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
124 * support stolen.
125 */
126 struct intel_memory_region *stolen_region;
127 /** Memory allocator for GTT stolen memory */
128 struct drm_mm stolen;
129 /** Protects the usage of the GTT stolen memory allocator. This is
130 * always the inner lock when overlapping with struct_mutex. */
131 struct mutex stolen_lock;
132
133 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
134 spinlock_t obj_lock;
135
136 /**
137 * List of objects which are purgeable.
138 */
139 struct list_head purge_list;
140
141 /**
142 * List of objects which have allocated pages and are shrinkable.
143 */
144 struct list_head shrink_list;
145
146 /**
147 * List of objects which are pending destruction.
148 */
149 struct llist_head free_list;
150 struct work_struct free_work;
151 /**
152 * Count of objects pending destructions. Used to skip needlessly
153 * waiting on an RCU barrier if no objects are waiting to be freed.
154 */
155 atomic_t free_count;
156
157 /**
158 * tmpfs instance used for shmem backed objects
159 */
160 struct vfsmount *gemfs;
161
162 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
163
164 struct notifier_block oom_notifier;
165 struct notifier_block vmap_notifier;
166 struct shrinker *shrinker;
167
168 /* shrinker accounting, also useful for userland debugging */
169 u64 shrink_memory;
170 u32 shrink_count;
171};
172
173struct i915_virtual_gpu {
174 struct mutex lock; /* serialises sending of g2v_notify command pkts */
175 bool active;
176 u32 caps;
177 u32 *initial_mmio;
178 u8 *initial_cfg_space;
179 struct list_head entry;
180};
181
182struct i915_selftest_stash {
183 atomic_t counter;
184 struct ida mock_region_instances;
185};
186
187struct drm_i915_private {
188 struct drm_device drm;
189
190 struct intel_display display;
191
192 /* FIXME: Device release actions should all be moved to drmm_ */
193 bool do_release;
194
195 /* i915 device parameters */
196 struct i915_params params;
197
198 const struct intel_device_info *__info; /* Use INTEL_INFO() to access. */
199 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
200 struct intel_driver_caps caps;
201
202 struct i915_dsm dsm;
203
204 struct intel_uncore uncore;
205 struct intel_uncore_mmio_debug mmio_debug;
206
207 struct i915_virtual_gpu vgpu;
208
209 struct intel_gvt *gvt;
210
211 struct {
212 struct pci_dev *pdev;
213 struct resource mch_res;
214 bool mchbar_need_disable;
215 } gmch;
216
217 /*
218 * Chaining user engines happens in multiple stages, starting with a
219 * simple lock-less linked list created by intel_engine_add_user(),
220 * which later gets sorted and converted to an intermediate regular
221 * list, just to be converted once again to its final rb tree structure
222 * in intel_engines_driver_register().
223 *
224 * Make sure to use the right iterator helper, depending on if the code
225 * in question runs before or after intel_engines_driver_register() --
226 * for_each_uabi_engine() can only be used afterwards!
227 */
228 union {
229 struct llist_head uabi_engines_llist;
230 struct list_head uabi_engines_list;
231 struct rb_root uabi_engines;
232 };
233 unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];
234
235 /* protects the irq masks */
236 spinlock_t irq_lock;
237
238 bool display_irqs_enabled;
239
240 /* Sideband mailbox protection */
241 struct mutex sb_lock;
242 struct pm_qos_request sb_qos;
243
244 /** Cached value of IMR to avoid reads in updating the bitfield */
245 union {
246 u32 irq_mask;
247 u32 de_irq_mask[I915_MAX_PIPES];
248 };
249 u32 pipestat_irq_mask[I915_MAX_PIPES];
250
251 bool preserve_bios_swizzle;
252
253 unsigned int fsb_freq, mem_freq, is_ddr3;
254 unsigned int skl_preferred_vco_freq;
255
256 unsigned int max_dotclk_freq;
257 unsigned int hpll_freq;
258 unsigned int czclk_freq;
259
260 /**
261 * wq - Driver workqueue for GEM.
262 *
263 * NOTE: Work items scheduled here are not allowed to grab any modeset
264 * locks, for otherwise the flushing done in the pageflip code will
265 * result in deadlocks.
266 */
267 struct workqueue_struct *wq;
268
269 /**
270 * unordered_wq - internal workqueue for unordered work
271 *
272 * This workqueue should be used for all unordered work
273 * scheduling within i915, which used to be scheduled on the
274 * system_wq before moving to a driver instance due
275 * deprecation of flush_scheduled_work().
276 */
277 struct workqueue_struct *unordered_wq;
278
279 /* pm private clock gating functions */
280 const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
281
282 /* PCH chipset type */
283 enum intel_pch pch_type;
284 unsigned short pch_id;
285
286 unsigned long gem_quirks;
287
288 struct i915_gem_mm mm;
289
290 struct intel_l3_parity l3_parity;
291
292 /*
293 * edram size in MB.
294 * Cannot be determined by PCIID. You must always read a register.
295 */
296 u32 edram_size_mb;
297
298 struct i915_gpu_error gpu_error;
299
300 u32 suspend_count;
301 struct i915_suspend_saved_registers regfile;
302 struct vlv_s0ix_state *vlv_s0ix_state;
303
304 struct dram_info {
305 bool wm_lv_0_adjust_needed;
306 u8 num_channels;
307 bool symmetric_memory;
308 enum intel_dram_type {
309 INTEL_DRAM_UNKNOWN,
310 INTEL_DRAM_DDR3,
311 INTEL_DRAM_DDR4,
312 INTEL_DRAM_LPDDR3,
313 INTEL_DRAM_LPDDR4,
314 INTEL_DRAM_DDR5,
315 INTEL_DRAM_LPDDR5,
316 } type;
317 u8 num_qgv_points;
318 u8 num_psf_gv_points;
319 } dram_info;
320
321 struct intel_runtime_pm runtime_pm;
322
323 struct i915_perf perf;
324
325 struct i915_hwmon *hwmon;
326
327 struct intel_gt *gt[I915_MAX_GT];
328
329 struct kobject *sysfs_gt;
330
331 /* Quick lookup of media GT (current platforms only have one) */
332 struct intel_gt *media_gt;
333
334 struct {
335 struct i915_gem_contexts {
336 spinlock_t lock; /* locks list */
337 struct list_head list;
338 } contexts;
339
340 /*
341 * We replace the local file with a global mappings as the
342 * backing storage for the mmap is on the device and not
343 * on the struct file, and we do not want to prolong the
344 * lifetime of the local fd. To minimise the number of
345 * anonymous inodes we create, we use a global singleton to
346 * share the global mapping.
347 */
348 struct file *mmap_singleton;
349 } gem;
350
351 struct intel_pxp *pxp;
352
353 /* For i915gm/i945gm vblank irq workaround */
354 u8 vblank_enabled;
355
356 bool irq_enabled;
357
358 struct i915_pmu pmu;
359
360 /* The TTM device structure. */
361 struct ttm_device bdev;
362
363 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
364
365 /*
366 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
367 * will be rejected. Instead look for a better place.
368 */
369};
370
371static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
372{
373 return container_of(dev, struct drm_i915_private, drm);
374}
375
376static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
377{
378 return dev_get_drvdata(kdev);
379}
380
381static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
382{
383 return pci_get_drvdata(pdev);
384}
385
386static inline struct intel_gt *to_gt(const struct drm_i915_private *i915)
387{
388 return i915->gt[0];
389}
390
391#define rb_to_uabi_engine(rb) \
392 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
393
394#define for_each_uabi_engine(engine__, i915__) \
395 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
396 (engine__); \
397 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
398
399#define INTEL_INFO(i915) ((i915)->__info)
400#define RUNTIME_INFO(i915) (&(i915)->__runtime)
401#define DRIVER_CAPS(i915) (&(i915)->caps)
402
403#define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id)
404
405#define IP_VER(ver, rel) ((ver) << 8 | (rel))
406
407#define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver)
408#define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
409 RUNTIME_INFO(i915)->graphics.ip.rel)
410#define IS_GRAPHICS_VER(i915, from, until) \
411 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
412
413#define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver)
414#define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
415 RUNTIME_INFO(i915)->media.ip.rel)
416#define IS_MEDIA_VER(i915, from, until) \
417 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
418
419#define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision)
420
421#define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
422#define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
423#define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
424#define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step)
425
426#define IS_DISPLAY_STEP(__i915, since, until) \
427 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
428 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
429
430#define IS_GRAPHICS_STEP(__i915, since, until) \
431 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \
432 INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until))
433
434#define IS_MEDIA_STEP(__i915, since, until) \
435 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
436 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until))
437
438#define IS_BASEDIE_STEP(__i915, since, until) \
439 (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \
440 INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until))
441
442static __always_inline unsigned int
443__platform_mask_index(const struct intel_runtime_info *info,
444 enum intel_platform p)
445{
446 const unsigned int pbits =
447 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
448
449 /* Expand the platform_mask array if this fails. */
450 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
451 pbits * ARRAY_SIZE(info->platform_mask));
452
453 return p / pbits;
454}
455
456static __always_inline unsigned int
457__platform_mask_bit(const struct intel_runtime_info *info,
458 enum intel_platform p)
459{
460 const unsigned int pbits =
461 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
462
463 return p % pbits + INTEL_SUBPLATFORM_BITS;
464}
465
466static inline u32
467intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
468{
469 const unsigned int pi = __platform_mask_index(info, p);
470
471 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
472}
473
474static __always_inline bool
475IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
476{
477 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
478 const unsigned int pi = __platform_mask_index(info, p);
479 const unsigned int pb = __platform_mask_bit(info, p);
480
481 BUILD_BUG_ON(!__builtin_constant_p(p));
482
483 return info->platform_mask[pi] & BIT(pb);
484}
485
486static __always_inline bool
487IS_SUBPLATFORM(const struct drm_i915_private *i915,
488 enum intel_platform p, unsigned int s)
489{
490 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
491 const unsigned int pi = __platform_mask_index(info, p);
492 const unsigned int pb = __platform_mask_bit(info, p);
493 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
494 const u32 mask = info->platform_mask[pi];
495
496 BUILD_BUG_ON(!__builtin_constant_p(p));
497 BUILD_BUG_ON(!__builtin_constant_p(s));
498 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
499
500 /* Shift and test on the MSB position so sign flag can be used. */
501 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
502}
503
504#define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile)
505#define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx)
506
507#define IS_I830(i915) IS_PLATFORM(i915, INTEL_I830)
508#define IS_I845G(i915) IS_PLATFORM(i915, INTEL_I845G)
509#define IS_I85X(i915) IS_PLATFORM(i915, INTEL_I85X)
510#define IS_I865G(i915) IS_PLATFORM(i915, INTEL_I865G)
511#define IS_I915G(i915) IS_PLATFORM(i915, INTEL_I915G)
512#define IS_I915GM(i915) IS_PLATFORM(i915, INTEL_I915GM)
513#define IS_I945G(i915) IS_PLATFORM(i915, INTEL_I945G)
514#define IS_I945GM(i915) IS_PLATFORM(i915, INTEL_I945GM)
515#define IS_I965G(i915) IS_PLATFORM(i915, INTEL_I965G)
516#define IS_I965GM(i915) IS_PLATFORM(i915, INTEL_I965GM)
517#define IS_G45(i915) IS_PLATFORM(i915, INTEL_G45)
518#define IS_GM45(i915) IS_PLATFORM(i915, INTEL_GM45)
519#define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915))
520#define IS_PINEVIEW(i915) IS_PLATFORM(i915, INTEL_PINEVIEW)
521#define IS_G33(i915) IS_PLATFORM(i915, INTEL_G33)
522#define IS_IRONLAKE(i915) IS_PLATFORM(i915, INTEL_IRONLAKE)
523#define IS_IRONLAKE_M(i915) \
524 (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915))
525#define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE)
526#define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE)
527#define IS_IVB_GT1(i915) (IS_IVYBRIDGE(i915) && \
528 INTEL_INFO(i915)->gt == 1)
529#define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW)
530#define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW)
531#define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL)
532#define IS_BROADWELL(i915) IS_PLATFORM(i915, INTEL_BROADWELL)
533#define IS_SKYLAKE(i915) IS_PLATFORM(i915, INTEL_SKYLAKE)
534#define IS_BROXTON(i915) IS_PLATFORM(i915, INTEL_BROXTON)
535#define IS_KABYLAKE(i915) IS_PLATFORM(i915, INTEL_KABYLAKE)
536#define IS_GEMINILAKE(i915) IS_PLATFORM(i915, INTEL_GEMINILAKE)
537#define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE)
538#define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE)
539#define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE)
540#define IS_JASPERLAKE(i915) IS_PLATFORM(i915, INTEL_JASPERLAKE)
541#define IS_ELKHARTLAKE(i915) IS_PLATFORM(i915, INTEL_ELKHARTLAKE)
542#define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE)
543#define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE)
544#define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1)
545#define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S)
546#define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P)
547#define IS_XEHPSDV(i915) IS_PLATFORM(i915, INTEL_XEHPSDV)
548#define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2)
549#define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
550#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
551#define IS_LUNARLAKE(i915) 0
552
553#define IS_DG2_G10(i915) \
554 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
555#define IS_DG2_G11(i915) \
556 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
557#define IS_DG2_G12(i915) \
558 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
559#define IS_RAPTORLAKE_S(i915) \
560 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
561#define IS_ALDERLAKE_P_N(i915) \
562 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
563#define IS_RAPTORLAKE_P(i915) \
564 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
565#define IS_RAPTORLAKE_U(i915) \
566 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
567#define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \
568 (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
569#define IS_BROADWELL_ULT(i915) \
570 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
571#define IS_BROADWELL_ULX(i915) \
572 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
573#define IS_BROADWELL_GT3(i915) (IS_BROADWELL(i915) && \
574 INTEL_INFO(i915)->gt == 3)
575#define IS_HASWELL_ULT(i915) \
576 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
577#define IS_HASWELL_GT3(i915) (IS_HASWELL(i915) && \
578 INTEL_INFO(i915)->gt == 3)
579#define IS_HASWELL_GT1(i915) (IS_HASWELL(i915) && \
580 INTEL_INFO(i915)->gt == 1)
581/* ULX machines are also considered ULT. */
582#define IS_HASWELL_ULX(i915) \
583 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
584#define IS_SKYLAKE_ULT(i915) \
585 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
586#define IS_SKYLAKE_ULX(i915) \
587 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
588#define IS_KABYLAKE_ULT(i915) \
589 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
590#define IS_KABYLAKE_ULX(i915) \
591 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
592#define IS_SKYLAKE_GT2(i915) (IS_SKYLAKE(i915) && \
593 INTEL_INFO(i915)->gt == 2)
594#define IS_SKYLAKE_GT3(i915) (IS_SKYLAKE(i915) && \
595 INTEL_INFO(i915)->gt == 3)
596#define IS_SKYLAKE_GT4(i915) (IS_SKYLAKE(i915) && \
597 INTEL_INFO(i915)->gt == 4)
598#define IS_KABYLAKE_GT2(i915) (IS_KABYLAKE(i915) && \
599 INTEL_INFO(i915)->gt == 2)
600#define IS_KABYLAKE_GT3(i915) (IS_KABYLAKE(i915) && \
601 INTEL_INFO(i915)->gt == 3)
602#define IS_COFFEELAKE_ULT(i915) \
603 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
604#define IS_COFFEELAKE_ULX(i915) \
605 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
606#define IS_COFFEELAKE_GT2(i915) (IS_COFFEELAKE(i915) && \
607 INTEL_INFO(i915)->gt == 2)
608#define IS_COFFEELAKE_GT3(i915) (IS_COFFEELAKE(i915) && \
609 INTEL_INFO(i915)->gt == 3)
610
611#define IS_COMETLAKE_ULT(i915) \
612 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
613#define IS_COMETLAKE_ULX(i915) \
614 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
615#define IS_COMETLAKE_GT2(i915) (IS_COMETLAKE(i915) && \
616 INTEL_INFO(i915)->gt == 2)
617
618#define IS_ICL_WITH_PORT_F(i915) \
619 IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
620
621#define IS_TIGERLAKE_UY(i915) \
622 IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
623
624#define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
625 (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
626
627#define IS_PVC_BD_STEP(__i915, since, until) \
628 (IS_PONTEVECCHIO(__i915) && \
629 IS_BASEDIE_STEP(__i915, since, until))
630
631#define IS_PVC_CT_STEP(__i915, since, until) \
632 (IS_PONTEVECCHIO(__i915) && \
633 IS_GRAPHICS_STEP(__i915, since, until))
634
635#define IS_LP(i915) (INTEL_INFO(i915)->is_lp)
636#define IS_GEN9_LP(i915) (GRAPHICS_VER(i915) == 9 && IS_LP(i915))
637#define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_LP(i915))
638
639#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
640#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
641
642#define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \
643 unsigned int first__ = (first); \
644 unsigned int count__ = (count); \
645 ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \
646})
647
648#define ENGINE_INSTANCES_MASK(gt, first, count) \
649 __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
650
651#define RCS_MASK(gt) \
652 ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
653#define BCS_MASK(gt) \
654 ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
655#define VDBOX_MASK(gt) \
656 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
657#define VEBOX_MASK(gt) \
658 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
659#define CCS_MASK(gt) \
660 ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
661
662#define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode)
663
664/*
665 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
666 * All later gens can run the final buffer from the ppgtt
667 */
668#define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7)
669
670#define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc)
671#define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop)
672#define HAS_EDRAM(i915) ((i915)->edram_size_mb)
673#define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6)
674#define HAS_WT(i915) HAS_EDRAM(i915)
675
676#define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical)
677
678#define HAS_LOGICAL_RING_CONTEXTS(i915) \
679 (INTEL_INFO(i915)->has_logical_ring_contexts)
680#define HAS_LOGICAL_RING_ELSQ(i915) \
681 (INTEL_INFO(i915)->has_logical_ring_elsq)
682
683#define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915)
684
685#define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type)
686#define HAS_PPGTT(i915) \
687 (INTEL_PPGTT(i915) != INTEL_PPGTT_NONE)
688#define HAS_FULL_PPGTT(i915) \
689 (INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL)
690
691#define HAS_PAGE_SIZES(i915, sizes) ({ \
692 GEM_BUG_ON((sizes) == 0); \
693 ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
694})
695
696/* Early gen2 have a totally busted CS tlb and require pinned batches. */
697#define HAS_BROKEN_CS_TLB(i915) (IS_I830(i915) || IS_I845G(i915))
698
699#define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \
700 (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9)
701
702/* WaRsDisableCoarsePowerGating:skl,cnl */
703#define NEEDS_WaRsDisableCoarsePowerGating(i915) \
704 (IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915))
705
706/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
707 * rows, which changed the alignment requirements and fence programming.
708 */
709#define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
710 !(IS_I915G(i915) || IS_I915GM(i915)))
711
712#define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6)
713#define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p)
714#define HAS_RC6pp(i915) (false) /* HW was never validated */
715
716#define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps)
717
718#define HAS_HECI_PXP(i915) \
719 (INTEL_INFO(i915)->has_heci_pxp)
720
721#define HAS_HECI_GSCFI(i915) \
722 (INTEL_INFO(i915)->has_heci_gscfi)
723
724#define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915))
725
726#define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm)
727#define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc)
728
729#define HAS_OA_BPC_REPORTING(i915) \
730 (INTEL_INFO(i915)->has_oa_bpc_reporting)
731#define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \
732 (INTEL_INFO(i915)->has_oa_slice_contrib_limits)
733#define HAS_OAM(i915) \
734 (INTEL_INFO(i915)->has_oam)
735
736/*
737 * Set this flag, when platform requires 64K GTT page sizes or larger for
738 * device local memory access.
739 */
740#define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
741
742#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
743#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
744
745#define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list)
746
747/*
748 * Platform has the dedicated compression control state for each lmem surfaces
749 * stored in lmem to support the 3D and media compression formats.
750 */
751#define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs)
752
753#define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc)
754
755#define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu)
756
757#define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs)
758
759#define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
760
761#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
762
763/* DPF == dynamic parity feature */
764#define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf)
765#define NUM_L3_SLICES(i915) (IS_HASWELL_GT3(i915) ? \
766 2 : HAS_L3_DPF(i915))
767
768#define HAS_GUC_DEPRIVILEGE(i915) \
769 (INTEL_INFO(i915)->has_guc_deprivilege)
770
771#define HAS_GUC_TLB_INVALIDATION(i915) (INTEL_INFO(i915)->has_guc_tlb_invalidation)
772
773#define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
774
775#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
776
777#define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
778 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
779
780#endif