1/* Common header for intel-gtt.ko and i915.ko */
 2
 3#ifndef _DRM_INTEL_GTT_H
 4#define	_DRM_INTEL_GTT_H
 5
 6const struct intel_gtt {
 7	/* Size of memory reserved for graphics by the BIOS */
 8	unsigned int stolen_size;
 9	/* Total number of gtt entries. */
10	unsigned int gtt_total_entries;
11	/* Part of the gtt that is mappable by the cpu, for those chips where
12	 * this is not the full gtt. */
13	unsigned int gtt_mappable_entries;
14	/* Whether i915 needs to use the dmar apis or not. */
15	unsigned int needs_dmar : 1;
16	/* Whether we idle the gpu before mapping/unmapping */
17	unsigned int do_idle_maps : 1;
18	/* Share the scratch page dma with ppgtts. */
19	dma_addr_t scratch_page_dma;
20	/* for ppgtt PDE access */
21	u32 __iomem *gtt;
22} *intel_gtt_get(void);
23
24void intel_gtt_chipset_flush(void);
25void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg);
26void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries);
27int intel_gtt_map_memory(struct page **pages, unsigned int num_entries,
28			 struct scatterlist **sg_list, int *num_sg);
29void intel_gtt_insert_sg_entries(struct scatterlist *sg_list,
30				 unsigned int sg_len,
31				 unsigned int pg_start,
32				 unsigned int flags);
33void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries,
34			    struct page **pages, unsigned int flags);
35
36/* Special gtt memory types */
37#define AGP_DCACHE_MEMORY	1
38#define AGP_PHYS_MEMORY		2
39
40/* New caching attributes for gen6/sandybridge */
41#define AGP_USER_CACHED_MEMORY_LLC_MLC (AGP_USER_TYPES + 2)
42#define AGP_USER_UNCACHED_MEMORY (AGP_USER_TYPES + 4)
43
44/* flag for GFDT type */
45#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)
46
47#ifdef CONFIG_INTEL_IOMMU
48extern int intel_iommu_gfx_mapped;
49#endif
50
51#endif