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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
5
6#include <linux/module.h>
7#include <linux/types.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/vmalloc.h>
11#include <linux/pagemap.h>
12#include <linux/delay.h>
13#include <linux/netdevice.h>
14#include <linux/interrupt.h>
15#include <linux/tcp.h>
16#include <linux/ipv6.h>
17#include <linux/slab.h>
18#include <net/checksum.h>
19#include <net/ip6_checksum.h>
20#include <linux/ethtool.h>
21#include <linux/if_vlan.h>
22#include <linux/cpu.h>
23#include <linux/smp.h>
24#include <linux/pm_qos.h>
25#include <linux/pm_runtime.h>
26#include <linux/prefetch.h>
27#include <linux/suspend.h>
28
29#include "e1000.h"
30#define CREATE_TRACE_POINTS
31#include "e1000e_trace.h"
32
33char e1000e_driver_name[] = "e1000e";
34
35#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
36static int debug = -1;
37module_param(debug, int, 0);
38MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
39
40static const struct e1000_info *e1000_info_tbl[] = {
41 [board_82571] = &e1000_82571_info,
42 [board_82572] = &e1000_82572_info,
43 [board_82573] = &e1000_82573_info,
44 [board_82574] = &e1000_82574_info,
45 [board_82583] = &e1000_82583_info,
46 [board_80003es2lan] = &e1000_es2_info,
47 [board_ich8lan] = &e1000_ich8_info,
48 [board_ich9lan] = &e1000_ich9_info,
49 [board_ich10lan] = &e1000_ich10_info,
50 [board_pchlan] = &e1000_pch_info,
51 [board_pch2lan] = &e1000_pch2_info,
52 [board_pch_lpt] = &e1000_pch_lpt_info,
53 [board_pch_spt] = &e1000_pch_spt_info,
54 [board_pch_cnp] = &e1000_pch_cnp_info,
55 [board_pch_tgp] = &e1000_pch_tgp_info,
56 [board_pch_adp] = &e1000_pch_adp_info,
57 [board_pch_mtp] = &e1000_pch_mtp_info,
58};
59
60struct e1000_reg_info {
61 u32 ofs;
62 char *name;
63};
64
65static const struct e1000_reg_info e1000_reg_info_tbl[] = {
66 /* General Registers */
67 {E1000_CTRL, "CTRL"},
68 {E1000_STATUS, "STATUS"},
69 {E1000_CTRL_EXT, "CTRL_EXT"},
70
71 /* Interrupt Registers */
72 {E1000_ICR, "ICR"},
73
74 /* Rx Registers */
75 {E1000_RCTL, "RCTL"},
76 {E1000_RDLEN(0), "RDLEN"},
77 {E1000_RDH(0), "RDH"},
78 {E1000_RDT(0), "RDT"},
79 {E1000_RDTR, "RDTR"},
80 {E1000_RXDCTL(0), "RXDCTL"},
81 {E1000_ERT, "ERT"},
82 {E1000_RDBAL(0), "RDBAL"},
83 {E1000_RDBAH(0), "RDBAH"},
84 {E1000_RDFH, "RDFH"},
85 {E1000_RDFT, "RDFT"},
86 {E1000_RDFHS, "RDFHS"},
87 {E1000_RDFTS, "RDFTS"},
88 {E1000_RDFPC, "RDFPC"},
89
90 /* Tx Registers */
91 {E1000_TCTL, "TCTL"},
92 {E1000_TDBAL(0), "TDBAL"},
93 {E1000_TDBAH(0), "TDBAH"},
94 {E1000_TDLEN(0), "TDLEN"},
95 {E1000_TDH(0), "TDH"},
96 {E1000_TDT(0), "TDT"},
97 {E1000_TIDV, "TIDV"},
98 {E1000_TXDCTL(0), "TXDCTL"},
99 {E1000_TADV, "TADV"},
100 {E1000_TARC(0), "TARC"},
101 {E1000_TDFH, "TDFH"},
102 {E1000_TDFT, "TDFT"},
103 {E1000_TDFHS, "TDFHS"},
104 {E1000_TDFTS, "TDFTS"},
105 {E1000_TDFPC, "TDFPC"},
106
107 /* List Terminator */
108 {0, NULL}
109};
110
111/**
112 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
113 * @hw: pointer to the HW structure
114 *
115 * When updating the MAC CSR registers, the Manageability Engine (ME) could
116 * be accessing the registers at the same time. Normally, this is handled in
117 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
118 * accesses later than it should which could result in the register to have
119 * an incorrect value. Workaround this by checking the FWSM register which
120 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
121 * and try again a number of times.
122 **/
123static void __ew32_prepare(struct e1000_hw *hw)
124{
125 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
126
127 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
128 udelay(50);
129}
130
131void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
132{
133 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
134 __ew32_prepare(hw);
135
136 writel(val, hw->hw_addr + reg);
137}
138
139/**
140 * e1000_regdump - register printout routine
141 * @hw: pointer to the HW structure
142 * @reginfo: pointer to the register info table
143 **/
144static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
145{
146 int n = 0;
147 char rname[16];
148 u32 regs[8];
149
150 switch (reginfo->ofs) {
151 case E1000_RXDCTL(0):
152 for (n = 0; n < 2; n++)
153 regs[n] = __er32(hw, E1000_RXDCTL(n));
154 break;
155 case E1000_TXDCTL(0):
156 for (n = 0; n < 2; n++)
157 regs[n] = __er32(hw, E1000_TXDCTL(n));
158 break;
159 case E1000_TARC(0):
160 for (n = 0; n < 2; n++)
161 regs[n] = __er32(hw, E1000_TARC(n));
162 break;
163 default:
164 pr_info("%-15s %08x\n",
165 reginfo->name, __er32(hw, reginfo->ofs));
166 return;
167 }
168
169 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
170 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
171}
172
173static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
174 struct e1000_buffer *bi)
175{
176 int i;
177 struct e1000_ps_page *ps_page;
178
179 for (i = 0; i < adapter->rx_ps_pages; i++) {
180 ps_page = &bi->ps_pages[i];
181
182 if (ps_page->page) {
183 pr_info("packet dump for ps_page %d:\n", i);
184 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
185 16, 1, page_address(ps_page->page),
186 PAGE_SIZE, true);
187 }
188 }
189}
190
191/**
192 * e1000e_dump - Print registers, Tx-ring and Rx-ring
193 * @adapter: board private structure
194 **/
195static void e1000e_dump(struct e1000_adapter *adapter)
196{
197 struct net_device *netdev = adapter->netdev;
198 struct e1000_hw *hw = &adapter->hw;
199 struct e1000_reg_info *reginfo;
200 struct e1000_ring *tx_ring = adapter->tx_ring;
201 struct e1000_tx_desc *tx_desc;
202 struct my_u0 {
203 __le64 a;
204 __le64 b;
205 } *u0;
206 struct e1000_buffer *buffer_info;
207 struct e1000_ring *rx_ring = adapter->rx_ring;
208 union e1000_rx_desc_packet_split *rx_desc_ps;
209 union e1000_rx_desc_extended *rx_desc;
210 struct my_u1 {
211 __le64 a;
212 __le64 b;
213 __le64 c;
214 __le64 d;
215 } *u1;
216 u32 staterr;
217 int i = 0;
218
219 if (!netif_msg_hw(adapter))
220 return;
221
222 /* Print netdevice Info */
223 if (netdev) {
224 dev_info(&adapter->pdev->dev, "Net device Info\n");
225 pr_info("Device Name state trans_start\n");
226 pr_info("%-15s %016lX %016lX\n", netdev->name,
227 netdev->state, dev_trans_start(netdev));
228 }
229
230 /* Print Registers */
231 dev_info(&adapter->pdev->dev, "Register Dump\n");
232 pr_info(" Register Name Value\n");
233 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
234 reginfo->name; reginfo++) {
235 e1000_regdump(hw, reginfo);
236 }
237
238 /* Print Tx Ring Summary */
239 if (!netdev || !netif_running(netdev))
240 return;
241
242 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
243 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
244 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
245 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
246 0, tx_ring->next_to_use, tx_ring->next_to_clean,
247 (unsigned long long)buffer_info->dma,
248 buffer_info->length,
249 buffer_info->next_to_watch,
250 (unsigned long long)buffer_info->time_stamp);
251
252 /* Print Tx Ring */
253 if (!netif_msg_tx_done(adapter))
254 goto rx_ring_summary;
255
256 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
257
258 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
259 *
260 * Legacy Transmit Descriptor
261 * +--------------------------------------------------------------+
262 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
263 * +--------------------------------------------------------------+
264 * 8 | Special | CSS | Status | CMD | CSO | Length |
265 * +--------------------------------------------------------------+
266 * 63 48 47 36 35 32 31 24 23 16 15 0
267 *
268 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
269 * 63 48 47 40 39 32 31 16 15 8 7 0
270 * +----------------------------------------------------------------+
271 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
272 * +----------------------------------------------------------------+
273 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
274 * +----------------------------------------------------------------+
275 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
276 *
277 * Extended Data Descriptor (DTYP=0x1)
278 * +----------------------------------------------------------------+
279 * 0 | Buffer Address [63:0] |
280 * +----------------------------------------------------------------+
281 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
282 * +----------------------------------------------------------------+
283 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
284 */
285 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
286 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
287 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
288 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
289 const char *next_desc;
290 tx_desc = E1000_TX_DESC(*tx_ring, i);
291 buffer_info = &tx_ring->buffer_info[i];
292 u0 = (struct my_u0 *)tx_desc;
293 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
294 next_desc = " NTC/U";
295 else if (i == tx_ring->next_to_use)
296 next_desc = " NTU";
297 else if (i == tx_ring->next_to_clean)
298 next_desc = " NTC";
299 else
300 next_desc = "";
301 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
302 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' :
303 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')),
304 i,
305 (unsigned long long)le64_to_cpu(u0->a),
306 (unsigned long long)le64_to_cpu(u0->b),
307 (unsigned long long)buffer_info->dma,
308 buffer_info->length, buffer_info->next_to_watch,
309 (unsigned long long)buffer_info->time_stamp,
310 buffer_info->skb, next_desc);
311
312 if (netif_msg_pktdata(adapter) && buffer_info->skb)
313 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
314 16, 1, buffer_info->skb->data,
315 buffer_info->skb->len, true);
316 }
317
318 /* Print Rx Ring Summary */
319rx_ring_summary:
320 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
321 pr_info("Queue [NTU] [NTC]\n");
322 pr_info(" %5d %5X %5X\n",
323 0, rx_ring->next_to_use, rx_ring->next_to_clean);
324
325 /* Print Rx Ring */
326 if (!netif_msg_rx_status(adapter))
327 return;
328
329 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
330 switch (adapter->rx_ps_pages) {
331 case 1:
332 case 2:
333 case 3:
334 /* [Extended] Packet Split Receive Descriptor Format
335 *
336 * +-----------------------------------------------------+
337 * 0 | Buffer Address 0 [63:0] |
338 * +-----------------------------------------------------+
339 * 8 | Buffer Address 1 [63:0] |
340 * +-----------------------------------------------------+
341 * 16 | Buffer Address 2 [63:0] |
342 * +-----------------------------------------------------+
343 * 24 | Buffer Address 3 [63:0] |
344 * +-----------------------------------------------------+
345 */
346 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
347 /* [Extended] Receive Descriptor (Write-Back) Format
348 *
349 * 63 48 47 32 31 13 12 8 7 4 3 0
350 * +------------------------------------------------------+
351 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
352 * | Checksum | Ident | | Queue | | Type |
353 * +------------------------------------------------------+
354 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
355 * +------------------------------------------------------+
356 * 63 48 47 32 31 20 19 0
357 */
358 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
359 for (i = 0; i < rx_ring->count; i++) {
360 const char *next_desc;
361 buffer_info = &rx_ring->buffer_info[i];
362 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
363 u1 = (struct my_u1 *)rx_desc_ps;
364 staterr =
365 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
366
367 if (i == rx_ring->next_to_use)
368 next_desc = " NTU";
369 else if (i == rx_ring->next_to_clean)
370 next_desc = " NTC";
371 else
372 next_desc = "";
373
374 if (staterr & E1000_RXD_STAT_DD) {
375 /* Descriptor Done */
376 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
377 "RWB", i,
378 (unsigned long long)le64_to_cpu(u1->a),
379 (unsigned long long)le64_to_cpu(u1->b),
380 (unsigned long long)le64_to_cpu(u1->c),
381 (unsigned long long)le64_to_cpu(u1->d),
382 buffer_info->skb, next_desc);
383 } else {
384 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
385 "R ", i,
386 (unsigned long long)le64_to_cpu(u1->a),
387 (unsigned long long)le64_to_cpu(u1->b),
388 (unsigned long long)le64_to_cpu(u1->c),
389 (unsigned long long)le64_to_cpu(u1->d),
390 (unsigned long long)buffer_info->dma,
391 buffer_info->skb, next_desc);
392
393 if (netif_msg_pktdata(adapter))
394 e1000e_dump_ps_pages(adapter,
395 buffer_info);
396 }
397 }
398 break;
399 default:
400 case 0:
401 /* Extended Receive Descriptor (Read) Format
402 *
403 * +-----------------------------------------------------+
404 * 0 | Buffer Address [63:0] |
405 * +-----------------------------------------------------+
406 * 8 | Reserved |
407 * +-----------------------------------------------------+
408 */
409 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
410 /* Extended Receive Descriptor (Write-Back) Format
411 *
412 * 63 48 47 32 31 24 23 4 3 0
413 * +------------------------------------------------------+
414 * | RSS Hash | | | |
415 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
416 * | Packet | IP | | | Type |
417 * | Checksum | Ident | | | |
418 * +------------------------------------------------------+
419 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
420 * +------------------------------------------------------+
421 * 63 48 47 32 31 20 19 0
422 */
423 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
424
425 for (i = 0; i < rx_ring->count; i++) {
426 const char *next_desc;
427
428 buffer_info = &rx_ring->buffer_info[i];
429 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
430 u1 = (struct my_u1 *)rx_desc;
431 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
432
433 if (i == rx_ring->next_to_use)
434 next_desc = " NTU";
435 else if (i == rx_ring->next_to_clean)
436 next_desc = " NTC";
437 else
438 next_desc = "";
439
440 if (staterr & E1000_RXD_STAT_DD) {
441 /* Descriptor Done */
442 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
443 "RWB", i,
444 (unsigned long long)le64_to_cpu(u1->a),
445 (unsigned long long)le64_to_cpu(u1->b),
446 buffer_info->skb, next_desc);
447 } else {
448 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
449 "R ", i,
450 (unsigned long long)le64_to_cpu(u1->a),
451 (unsigned long long)le64_to_cpu(u1->b),
452 (unsigned long long)buffer_info->dma,
453 buffer_info->skb, next_desc);
454
455 if (netif_msg_pktdata(adapter) &&
456 buffer_info->skb)
457 print_hex_dump(KERN_INFO, "",
458 DUMP_PREFIX_ADDRESS, 16,
459 1,
460 buffer_info->skb->data,
461 adapter->rx_buffer_len,
462 true);
463 }
464 }
465 }
466}
467
468/**
469 * e1000_desc_unused - calculate if we have unused descriptors
470 * @ring: pointer to ring struct to perform calculation on
471 **/
472static int e1000_desc_unused(struct e1000_ring *ring)
473{
474 if (ring->next_to_clean > ring->next_to_use)
475 return ring->next_to_clean - ring->next_to_use - 1;
476
477 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
478}
479
480/**
481 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
482 * @adapter: board private structure
483 * @hwtstamps: time stamp structure to update
484 * @systim: unsigned 64bit system time value.
485 *
486 * Convert the system time value stored in the RX/TXSTMP registers into a
487 * hwtstamp which can be used by the upper level time stamping functions.
488 *
489 * The 'systim_lock' spinlock is used to protect the consistency of the
490 * system time value. This is needed because reading the 64 bit time
491 * value involves reading two 32 bit registers. The first read latches the
492 * value.
493 **/
494static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
495 struct skb_shared_hwtstamps *hwtstamps,
496 u64 systim)
497{
498 u64 ns;
499 unsigned long flags;
500
501 spin_lock_irqsave(&adapter->systim_lock, flags);
502 ns = timecounter_cyc2time(&adapter->tc, systim);
503 spin_unlock_irqrestore(&adapter->systim_lock, flags);
504
505 memset(hwtstamps, 0, sizeof(*hwtstamps));
506 hwtstamps->hwtstamp = ns_to_ktime(ns);
507}
508
509/**
510 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
511 * @adapter: board private structure
512 * @status: descriptor extended error and status field
513 * @skb: particular skb to include time stamp
514 *
515 * If the time stamp is valid, convert it into the timecounter ns value
516 * and store that result into the shhwtstamps structure which is passed
517 * up the network stack.
518 **/
519static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
520 struct sk_buff *skb)
521{
522 struct e1000_hw *hw = &adapter->hw;
523 u64 rxstmp;
524
525 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
526 !(status & E1000_RXDEXT_STATERR_TST) ||
527 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
528 return;
529
530 /* The Rx time stamp registers contain the time stamp. No other
531 * received packet will be time stamped until the Rx time stamp
532 * registers are read. Because only one packet can be time stamped
533 * at a time, the register values must belong to this packet and
534 * therefore none of the other additional attributes need to be
535 * compared.
536 */
537 rxstmp = (u64)er32(RXSTMPL);
538 rxstmp |= (u64)er32(RXSTMPH) << 32;
539 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
540
541 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
542}
543
544/**
545 * e1000_receive_skb - helper function to handle Rx indications
546 * @adapter: board private structure
547 * @netdev: pointer to netdev struct
548 * @staterr: descriptor extended error and status field as written by hardware
549 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
550 * @skb: pointer to sk_buff to be indicated to stack
551 **/
552static void e1000_receive_skb(struct e1000_adapter *adapter,
553 struct net_device *netdev, struct sk_buff *skb,
554 u32 staterr, __le16 vlan)
555{
556 u16 tag = le16_to_cpu(vlan);
557
558 e1000e_rx_hwtstamp(adapter, staterr, skb);
559
560 skb->protocol = eth_type_trans(skb, netdev);
561
562 if (staterr & E1000_RXD_STAT_VP)
563 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
564
565 napi_gro_receive(&adapter->napi, skb);
566}
567
568/**
569 * e1000_rx_checksum - Receive Checksum Offload
570 * @adapter: board private structure
571 * @status_err: receive descriptor status and error fields
572 * @skb: socket buffer with received data
573 **/
574static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
575 struct sk_buff *skb)
576{
577 u16 status = (u16)status_err;
578 u8 errors = (u8)(status_err >> 24);
579
580 skb_checksum_none_assert(skb);
581
582 /* Rx checksum disabled */
583 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
584 return;
585
586 /* Ignore Checksum bit is set */
587 if (status & E1000_RXD_STAT_IXSM)
588 return;
589
590 /* TCP/UDP checksum error bit or IP checksum error bit is set */
591 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
592 /* let the stack verify checksum errors */
593 adapter->hw_csum_err++;
594 return;
595 }
596
597 /* TCP/UDP Checksum has not been calculated */
598 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
599 return;
600
601 /* It must be a TCP or UDP packet with a valid checksum */
602 skb->ip_summed = CHECKSUM_UNNECESSARY;
603 adapter->hw_csum_good++;
604}
605
606static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
607{
608 struct e1000_adapter *adapter = rx_ring->adapter;
609 struct e1000_hw *hw = &adapter->hw;
610
611 __ew32_prepare(hw);
612 writel(i, rx_ring->tail);
613
614 if (unlikely(i != readl(rx_ring->tail))) {
615 u32 rctl = er32(RCTL);
616
617 ew32(RCTL, rctl & ~E1000_RCTL_EN);
618 e_err("ME firmware caused invalid RDT - resetting\n");
619 schedule_work(&adapter->reset_task);
620 }
621}
622
623static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
624{
625 struct e1000_adapter *adapter = tx_ring->adapter;
626 struct e1000_hw *hw = &adapter->hw;
627
628 __ew32_prepare(hw);
629 writel(i, tx_ring->tail);
630
631 if (unlikely(i != readl(tx_ring->tail))) {
632 u32 tctl = er32(TCTL);
633
634 ew32(TCTL, tctl & ~E1000_TCTL_EN);
635 e_err("ME firmware caused invalid TDT - resetting\n");
636 schedule_work(&adapter->reset_task);
637 }
638}
639
640/**
641 * e1000_alloc_rx_buffers - Replace used receive buffers
642 * @rx_ring: Rx descriptor ring
643 * @cleaned_count: number to reallocate
644 * @gfp: flags for allocation
645 **/
646static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
647 int cleaned_count, gfp_t gfp)
648{
649 struct e1000_adapter *adapter = rx_ring->adapter;
650 struct net_device *netdev = adapter->netdev;
651 struct pci_dev *pdev = adapter->pdev;
652 union e1000_rx_desc_extended *rx_desc;
653 struct e1000_buffer *buffer_info;
654 struct sk_buff *skb;
655 unsigned int i;
656 unsigned int bufsz = adapter->rx_buffer_len;
657
658 i = rx_ring->next_to_use;
659 buffer_info = &rx_ring->buffer_info[i];
660
661 while (cleaned_count--) {
662 skb = buffer_info->skb;
663 if (skb) {
664 skb_trim(skb, 0);
665 goto map_skb;
666 }
667
668 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
669 if (!skb) {
670 /* Better luck next round */
671 adapter->alloc_rx_buff_failed++;
672 break;
673 }
674
675 buffer_info->skb = skb;
676map_skb:
677 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
678 adapter->rx_buffer_len,
679 DMA_FROM_DEVICE);
680 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
681 dev_err(&pdev->dev, "Rx DMA map failed\n");
682 adapter->rx_dma_failed++;
683 break;
684 }
685
686 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
687 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
688
689 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
690 /* Force memory writes to complete before letting h/w
691 * know there are new descriptors to fetch. (Only
692 * applicable for weak-ordered memory model archs,
693 * such as IA-64).
694 */
695 wmb();
696 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
697 e1000e_update_rdt_wa(rx_ring, i);
698 else
699 writel(i, rx_ring->tail);
700 }
701 i++;
702 if (i == rx_ring->count)
703 i = 0;
704 buffer_info = &rx_ring->buffer_info[i];
705 }
706
707 rx_ring->next_to_use = i;
708}
709
710/**
711 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
712 * @rx_ring: Rx descriptor ring
713 * @cleaned_count: number to reallocate
714 * @gfp: flags for allocation
715 **/
716static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
717 int cleaned_count, gfp_t gfp)
718{
719 struct e1000_adapter *adapter = rx_ring->adapter;
720 struct net_device *netdev = adapter->netdev;
721 struct pci_dev *pdev = adapter->pdev;
722 union e1000_rx_desc_packet_split *rx_desc;
723 struct e1000_buffer *buffer_info;
724 struct e1000_ps_page *ps_page;
725 struct sk_buff *skb;
726 unsigned int i, j;
727
728 i = rx_ring->next_to_use;
729 buffer_info = &rx_ring->buffer_info[i];
730
731 while (cleaned_count--) {
732 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
733
734 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
735 ps_page = &buffer_info->ps_pages[j];
736 if (j >= adapter->rx_ps_pages) {
737 /* all unused desc entries get hw null ptr */
738 rx_desc->read.buffer_addr[j + 1] =
739 ~cpu_to_le64(0);
740 continue;
741 }
742 if (!ps_page->page) {
743 ps_page->page = alloc_page(gfp);
744 if (!ps_page->page) {
745 adapter->alloc_rx_buff_failed++;
746 goto no_buffers;
747 }
748 ps_page->dma = dma_map_page(&pdev->dev,
749 ps_page->page,
750 0, PAGE_SIZE,
751 DMA_FROM_DEVICE);
752 if (dma_mapping_error(&pdev->dev,
753 ps_page->dma)) {
754 dev_err(&adapter->pdev->dev,
755 "Rx DMA page map failed\n");
756 adapter->rx_dma_failed++;
757 goto no_buffers;
758 }
759 }
760 /* Refresh the desc even if buffer_addrs
761 * didn't change because each write-back
762 * erases this info.
763 */
764 rx_desc->read.buffer_addr[j + 1] =
765 cpu_to_le64(ps_page->dma);
766 }
767
768 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
769 gfp);
770
771 if (!skb) {
772 adapter->alloc_rx_buff_failed++;
773 break;
774 }
775
776 buffer_info->skb = skb;
777 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
778 adapter->rx_ps_bsize0,
779 DMA_FROM_DEVICE);
780 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
781 dev_err(&pdev->dev, "Rx DMA map failed\n");
782 adapter->rx_dma_failed++;
783 /* cleanup skb */
784 dev_kfree_skb_any(skb);
785 buffer_info->skb = NULL;
786 break;
787 }
788
789 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
790
791 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
792 /* Force memory writes to complete before letting h/w
793 * know there are new descriptors to fetch. (Only
794 * applicable for weak-ordered memory model archs,
795 * such as IA-64).
796 */
797 wmb();
798 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
799 e1000e_update_rdt_wa(rx_ring, i << 1);
800 else
801 writel(i << 1, rx_ring->tail);
802 }
803
804 i++;
805 if (i == rx_ring->count)
806 i = 0;
807 buffer_info = &rx_ring->buffer_info[i];
808 }
809
810no_buffers:
811 rx_ring->next_to_use = i;
812}
813
814/**
815 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
816 * @rx_ring: Rx descriptor ring
817 * @cleaned_count: number of buffers to allocate this pass
818 * @gfp: flags for allocation
819 **/
820
821static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
822 int cleaned_count, gfp_t gfp)
823{
824 struct e1000_adapter *adapter = rx_ring->adapter;
825 struct net_device *netdev = adapter->netdev;
826 struct pci_dev *pdev = adapter->pdev;
827 union e1000_rx_desc_extended *rx_desc;
828 struct e1000_buffer *buffer_info;
829 struct sk_buff *skb;
830 unsigned int i;
831 unsigned int bufsz = 256 - 16; /* for skb_reserve */
832
833 i = rx_ring->next_to_use;
834 buffer_info = &rx_ring->buffer_info[i];
835
836 while (cleaned_count--) {
837 skb = buffer_info->skb;
838 if (skb) {
839 skb_trim(skb, 0);
840 goto check_page;
841 }
842
843 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
844 if (unlikely(!skb)) {
845 /* Better luck next round */
846 adapter->alloc_rx_buff_failed++;
847 break;
848 }
849
850 buffer_info->skb = skb;
851check_page:
852 /* allocate a new page if necessary */
853 if (!buffer_info->page) {
854 buffer_info->page = alloc_page(gfp);
855 if (unlikely(!buffer_info->page)) {
856 adapter->alloc_rx_buff_failed++;
857 break;
858 }
859 }
860
861 if (!buffer_info->dma) {
862 buffer_info->dma = dma_map_page(&pdev->dev,
863 buffer_info->page, 0,
864 PAGE_SIZE,
865 DMA_FROM_DEVICE);
866 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
867 adapter->alloc_rx_buff_failed++;
868 break;
869 }
870 }
871
872 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
873 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
874
875 if (unlikely(++i == rx_ring->count))
876 i = 0;
877 buffer_info = &rx_ring->buffer_info[i];
878 }
879
880 if (likely(rx_ring->next_to_use != i)) {
881 rx_ring->next_to_use = i;
882 if (unlikely(i-- == 0))
883 i = (rx_ring->count - 1);
884
885 /* Force memory writes to complete before letting h/w
886 * know there are new descriptors to fetch. (Only
887 * applicable for weak-ordered memory model archs,
888 * such as IA-64).
889 */
890 wmb();
891 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
892 e1000e_update_rdt_wa(rx_ring, i);
893 else
894 writel(i, rx_ring->tail);
895 }
896}
897
898static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
899 struct sk_buff *skb)
900{
901 if (netdev->features & NETIF_F_RXHASH)
902 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3);
903}
904
905/**
906 * e1000_clean_rx_irq - Send received data up the network stack
907 * @rx_ring: Rx descriptor ring
908 * @work_done: output parameter for indicating completed work
909 * @work_to_do: how many packets we can clean
910 *
911 * the return value indicates whether actual cleaning was done, there
912 * is no guarantee that everything was cleaned
913 **/
914static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
915 int work_to_do)
916{
917 struct e1000_adapter *adapter = rx_ring->adapter;
918 struct net_device *netdev = adapter->netdev;
919 struct pci_dev *pdev = adapter->pdev;
920 struct e1000_hw *hw = &adapter->hw;
921 union e1000_rx_desc_extended *rx_desc, *next_rxd;
922 struct e1000_buffer *buffer_info, *next_buffer;
923 u32 length, staterr;
924 unsigned int i;
925 int cleaned_count = 0;
926 bool cleaned = false;
927 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
928
929 i = rx_ring->next_to_clean;
930 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
931 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
932 buffer_info = &rx_ring->buffer_info[i];
933
934 while (staterr & E1000_RXD_STAT_DD) {
935 struct sk_buff *skb;
936
937 if (*work_done >= work_to_do)
938 break;
939 (*work_done)++;
940 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
941
942 skb = buffer_info->skb;
943 buffer_info->skb = NULL;
944
945 prefetch(skb->data - NET_IP_ALIGN);
946
947 i++;
948 if (i == rx_ring->count)
949 i = 0;
950 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
951 prefetch(next_rxd);
952
953 next_buffer = &rx_ring->buffer_info[i];
954
955 cleaned = true;
956 cleaned_count++;
957 dma_unmap_single(&pdev->dev, buffer_info->dma,
958 adapter->rx_buffer_len, DMA_FROM_DEVICE);
959 buffer_info->dma = 0;
960
961 length = le16_to_cpu(rx_desc->wb.upper.length);
962
963 /* !EOP means multiple descriptors were used to store a single
964 * packet, if that's the case we need to toss it. In fact, we
965 * need to toss every packet with the EOP bit clear and the
966 * next frame that _does_ have the EOP bit set, as it is by
967 * definition only a frame fragment
968 */
969 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
970 adapter->flags2 |= FLAG2_IS_DISCARDING;
971
972 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
973 /* All receives must fit into a single buffer */
974 e_dbg("Receive packet consumed multiple buffers\n");
975 /* recycle */
976 buffer_info->skb = skb;
977 if (staterr & E1000_RXD_STAT_EOP)
978 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
979 goto next_desc;
980 }
981
982 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
983 !(netdev->features & NETIF_F_RXALL))) {
984 /* recycle */
985 buffer_info->skb = skb;
986 goto next_desc;
987 }
988
989 /* adjust length to remove Ethernet CRC */
990 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
991 /* If configured to store CRC, don't subtract FCS,
992 * but keep the FCS bytes out of the total_rx_bytes
993 * counter
994 */
995 if (netdev->features & NETIF_F_RXFCS)
996 total_rx_bytes -= 4;
997 else
998 length -= 4;
999 }
1000
1001 total_rx_bytes += length;
1002 total_rx_packets++;
1003
1004 /* code added for copybreak, this should improve
1005 * performance for small packets with large amounts
1006 * of reassembly being done in the stack
1007 */
1008 if (length < copybreak) {
1009 struct sk_buff *new_skb =
1010 napi_alloc_skb(&adapter->napi, length);
1011 if (new_skb) {
1012 skb_copy_to_linear_data_offset(new_skb,
1013 -NET_IP_ALIGN,
1014 (skb->data -
1015 NET_IP_ALIGN),
1016 (length +
1017 NET_IP_ALIGN));
1018 /* save the skb in buffer_info as good */
1019 buffer_info->skb = skb;
1020 skb = new_skb;
1021 }
1022 /* else just continue with the old one */
1023 }
1024 /* end copybreak code */
1025 skb_put(skb, length);
1026
1027 /* Receive Checksum Offload */
1028 e1000_rx_checksum(adapter, staterr, skb);
1029
1030 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1031
1032 e1000_receive_skb(adapter, netdev, skb, staterr,
1033 rx_desc->wb.upper.vlan);
1034
1035next_desc:
1036 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1037
1038 /* return some buffers to hardware, one at a time is too slow */
1039 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1040 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1041 GFP_ATOMIC);
1042 cleaned_count = 0;
1043 }
1044
1045 /* use prefetched values */
1046 rx_desc = next_rxd;
1047 buffer_info = next_buffer;
1048
1049 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1050 }
1051 rx_ring->next_to_clean = i;
1052
1053 cleaned_count = e1000_desc_unused(rx_ring);
1054 if (cleaned_count)
1055 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1056
1057 adapter->total_rx_bytes += total_rx_bytes;
1058 adapter->total_rx_packets += total_rx_packets;
1059 return cleaned;
1060}
1061
1062static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1063 struct e1000_buffer *buffer_info,
1064 bool drop)
1065{
1066 struct e1000_adapter *adapter = tx_ring->adapter;
1067
1068 if (buffer_info->dma) {
1069 if (buffer_info->mapped_as_page)
1070 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1071 buffer_info->length, DMA_TO_DEVICE);
1072 else
1073 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1074 buffer_info->length, DMA_TO_DEVICE);
1075 buffer_info->dma = 0;
1076 }
1077 if (buffer_info->skb) {
1078 if (drop)
1079 dev_kfree_skb_any(buffer_info->skb);
1080 else
1081 dev_consume_skb_any(buffer_info->skb);
1082 buffer_info->skb = NULL;
1083 }
1084 buffer_info->time_stamp = 0;
1085}
1086
1087static void e1000_print_hw_hang(struct work_struct *work)
1088{
1089 struct e1000_adapter *adapter = container_of(work,
1090 struct e1000_adapter,
1091 print_hang_task);
1092 struct net_device *netdev = adapter->netdev;
1093 struct e1000_ring *tx_ring = adapter->tx_ring;
1094 unsigned int i = tx_ring->next_to_clean;
1095 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1096 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
1097 struct e1000_hw *hw = &adapter->hw;
1098 u16 phy_status, phy_1000t_status, phy_ext_status;
1099 u16 pci_status;
1100
1101 if (test_bit(__E1000_DOWN, &adapter->state))
1102 return;
1103
1104 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
1105 /* May be block on write-back, flush and detect again
1106 * flush pending descriptor writebacks to memory
1107 */
1108 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1109 /* execute the writes immediately */
1110 e1e_flush();
1111 /* Due to rare timing issues, write to TIDV again to ensure
1112 * the write is successful
1113 */
1114 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1115 /* execute the writes immediately */
1116 e1e_flush();
1117 adapter->tx_hang_recheck = true;
1118 return;
1119 }
1120 adapter->tx_hang_recheck = false;
1121
1122 if (er32(TDH(0)) == er32(TDT(0))) {
1123 e_dbg("false hang detected, ignoring\n");
1124 return;
1125 }
1126
1127 /* Real hang detected */
1128 netif_stop_queue(netdev);
1129
1130 e1e_rphy(hw, MII_BMSR, &phy_status);
1131 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1132 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
1133
1134 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1135
1136 /* detected Hardware unit hang */
1137 e_err("Detected Hardware Unit Hang:\n"
1138 " TDH <%x>\n"
1139 " TDT <%x>\n"
1140 " next_to_use <%x>\n"
1141 " next_to_clean <%x>\n"
1142 "buffer_info[next_to_clean]:\n"
1143 " time_stamp <%lx>\n"
1144 " next_to_watch <%x>\n"
1145 " jiffies <%lx>\n"
1146 " next_to_watch.status <%x>\n"
1147 "MAC Status <%x>\n"
1148 "PHY Status <%x>\n"
1149 "PHY 1000BASE-T Status <%x>\n"
1150 "PHY Extended Status <%x>\n"
1151 "PCI Status <%x>\n",
1152 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1153 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1154 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1155 phy_status, phy_1000t_status, phy_ext_status, pci_status);
1156
1157 e1000e_dump(adapter);
1158
1159 /* Suggest workaround for known h/w issue */
1160 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1161 e_err("Try turning off Tx pause (flow control) via ethtool\n");
1162}
1163
1164/**
1165 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1166 * @work: pointer to work struct
1167 *
1168 * This work function polls the TSYNCTXCTL valid bit to determine when a
1169 * timestamp has been taken for the current stored skb. The timestamp must
1170 * be for this skb because only one such packet is allowed in the queue.
1171 */
1172static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1173{
1174 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1175 tx_hwtstamp_work);
1176 struct e1000_hw *hw = &adapter->hw;
1177
1178 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1179 struct sk_buff *skb = adapter->tx_hwtstamp_skb;
1180 struct skb_shared_hwtstamps shhwtstamps;
1181 u64 txstmp;
1182
1183 txstmp = er32(TXSTMPL);
1184 txstmp |= (u64)er32(TXSTMPH) << 32;
1185
1186 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1187
1188 /* Clear the global tx_hwtstamp_skb pointer and force writes
1189 * prior to notifying the stack of a Tx timestamp.
1190 */
1191 adapter->tx_hwtstamp_skb = NULL;
1192 wmb(); /* force write prior to skb_tstamp_tx */
1193
1194 skb_tstamp_tx(skb, &shhwtstamps);
1195 dev_consume_skb_any(skb);
1196 } else if (time_after(jiffies, adapter->tx_hwtstamp_start
1197 + adapter->tx_timeout_factor * HZ)) {
1198 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1199 adapter->tx_hwtstamp_skb = NULL;
1200 adapter->tx_hwtstamp_timeouts++;
1201 e_warn("clearing Tx timestamp hang\n");
1202 } else {
1203 /* reschedule to check later */
1204 schedule_work(&adapter->tx_hwtstamp_work);
1205 }
1206}
1207
1208/**
1209 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1210 * @tx_ring: Tx descriptor ring
1211 *
1212 * the return value indicates whether actual cleaning was done, there
1213 * is no guarantee that everything was cleaned
1214 **/
1215static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
1216{
1217 struct e1000_adapter *adapter = tx_ring->adapter;
1218 struct net_device *netdev = adapter->netdev;
1219 struct e1000_hw *hw = &adapter->hw;
1220 struct e1000_tx_desc *tx_desc, *eop_desc;
1221 struct e1000_buffer *buffer_info;
1222 unsigned int i, eop;
1223 unsigned int count = 0;
1224 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
1225 unsigned int bytes_compl = 0, pkts_compl = 0;
1226
1227 i = tx_ring->next_to_clean;
1228 eop = tx_ring->buffer_info[i].next_to_watch;
1229 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1230
1231 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1232 (count < tx_ring->count)) {
1233 bool cleaned = false;
1234
1235 dma_rmb(); /* read buffer_info after eop_desc */
1236 for (; !cleaned; count++) {
1237 tx_desc = E1000_TX_DESC(*tx_ring, i);
1238 buffer_info = &tx_ring->buffer_info[i];
1239 cleaned = (i == eop);
1240
1241 if (cleaned) {
1242 total_tx_packets += buffer_info->segs;
1243 total_tx_bytes += buffer_info->bytecount;
1244 if (buffer_info->skb) {
1245 bytes_compl += buffer_info->skb->len;
1246 pkts_compl++;
1247 }
1248 }
1249
1250 e1000_put_txbuf(tx_ring, buffer_info, false);
1251 tx_desc->upper.data = 0;
1252
1253 i++;
1254 if (i == tx_ring->count)
1255 i = 0;
1256 }
1257
1258 if (i == tx_ring->next_to_use)
1259 break;
1260 eop = tx_ring->buffer_info[i].next_to_watch;
1261 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1262 }
1263
1264 tx_ring->next_to_clean = i;
1265
1266 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1267
1268#define TX_WAKE_THRESHOLD 32
1269 if (count && netif_carrier_ok(netdev) &&
1270 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
1271 /* Make sure that anybody stopping the queue after this
1272 * sees the new next_to_clean.
1273 */
1274 smp_mb();
1275
1276 if (netif_queue_stopped(netdev) &&
1277 !(test_bit(__E1000_DOWN, &adapter->state))) {
1278 netif_wake_queue(netdev);
1279 ++adapter->restart_queue;
1280 }
1281 }
1282
1283 if (adapter->detect_tx_hung) {
1284 /* Detect a transmit hang in hardware, this serializes the
1285 * check with the clearing of time_stamp and movement of i
1286 */
1287 adapter->detect_tx_hung = false;
1288 if (tx_ring->buffer_info[i].time_stamp &&
1289 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
1290 + (adapter->tx_timeout_factor * HZ)) &&
1291 !(er32(STATUS) & E1000_STATUS_TXOFF))
1292 schedule_work(&adapter->print_hang_task);
1293 else
1294 adapter->tx_hang_recheck = false;
1295 }
1296 adapter->total_tx_bytes += total_tx_bytes;
1297 adapter->total_tx_packets += total_tx_packets;
1298 return count < tx_ring->count;
1299}
1300
1301/**
1302 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1303 * @rx_ring: Rx descriptor ring
1304 * @work_done: output parameter for indicating completed work
1305 * @work_to_do: how many packets we can clean
1306 *
1307 * the return value indicates whether actual cleaning was done, there
1308 * is no guarantee that everything was cleaned
1309 **/
1310static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1311 int work_to_do)
1312{
1313 struct e1000_adapter *adapter = rx_ring->adapter;
1314 struct e1000_hw *hw = &adapter->hw;
1315 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1316 struct net_device *netdev = adapter->netdev;
1317 struct pci_dev *pdev = adapter->pdev;
1318 struct e1000_buffer *buffer_info, *next_buffer;
1319 struct e1000_ps_page *ps_page;
1320 struct sk_buff *skb;
1321 unsigned int i, j;
1322 u32 length, staterr;
1323 int cleaned_count = 0;
1324 bool cleaned = false;
1325 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1326
1327 i = rx_ring->next_to_clean;
1328 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1329 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1330 buffer_info = &rx_ring->buffer_info[i];
1331
1332 while (staterr & E1000_RXD_STAT_DD) {
1333 if (*work_done >= work_to_do)
1334 break;
1335 (*work_done)++;
1336 skb = buffer_info->skb;
1337 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1338
1339 /* in the packet split case this is header only */
1340 prefetch(skb->data - NET_IP_ALIGN);
1341
1342 i++;
1343 if (i == rx_ring->count)
1344 i = 0;
1345 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1346 prefetch(next_rxd);
1347
1348 next_buffer = &rx_ring->buffer_info[i];
1349
1350 cleaned = true;
1351 cleaned_count++;
1352 dma_unmap_single(&pdev->dev, buffer_info->dma,
1353 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
1354 buffer_info->dma = 0;
1355
1356 /* see !EOP comment in other Rx routine */
1357 if (!(staterr & E1000_RXD_STAT_EOP))
1358 adapter->flags2 |= FLAG2_IS_DISCARDING;
1359
1360 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
1361 e_dbg("Packet Split buffers didn't pick up the full packet\n");
1362 dev_kfree_skb_irq(skb);
1363 if (staterr & E1000_RXD_STAT_EOP)
1364 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1365 goto next_desc;
1366 }
1367
1368 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1369 !(netdev->features & NETIF_F_RXALL))) {
1370 dev_kfree_skb_irq(skb);
1371 goto next_desc;
1372 }
1373
1374 length = le16_to_cpu(rx_desc->wb.middle.length0);
1375
1376 if (!length) {
1377 e_dbg("Last part of the packet spanning multiple descriptors\n");
1378 dev_kfree_skb_irq(skb);
1379 goto next_desc;
1380 }
1381
1382 /* Good Receive */
1383 skb_put(skb, length);
1384
1385 {
1386 /* this looks ugly, but it seems compiler issues make
1387 * it more efficient than reusing j
1388 */
1389 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
1390
1391 /* page alloc/put takes too long and effects small
1392 * packet throughput, so unsplit small packets and
1393 * save the alloc/put
1394 */
1395 if (l1 && (l1 <= copybreak) &&
1396 ((length + l1) <= adapter->rx_ps_bsize0)) {
1397 ps_page = &buffer_info->ps_pages[0];
1398
1399 dma_sync_single_for_cpu(&pdev->dev,
1400 ps_page->dma,
1401 PAGE_SIZE,
1402 DMA_FROM_DEVICE);
1403 memcpy(skb_tail_pointer(skb),
1404 page_address(ps_page->page), l1);
1405 dma_sync_single_for_device(&pdev->dev,
1406 ps_page->dma,
1407 PAGE_SIZE,
1408 DMA_FROM_DEVICE);
1409
1410 /* remove the CRC */
1411 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1412 if (!(netdev->features & NETIF_F_RXFCS))
1413 l1 -= 4;
1414 }
1415
1416 skb_put(skb, l1);
1417 goto copydone;
1418 } /* if */
1419 }
1420
1421 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1422 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1423 if (!length)
1424 break;
1425
1426 ps_page = &buffer_info->ps_pages[j];
1427 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1428 DMA_FROM_DEVICE);
1429 ps_page->dma = 0;
1430 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1431 ps_page->page = NULL;
1432 skb->len += length;
1433 skb->data_len += length;
1434 skb->truesize += PAGE_SIZE;
1435 }
1436
1437 /* strip the ethernet crc, problem is we're using pages now so
1438 * this whole operation can get a little cpu intensive
1439 */
1440 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1441 if (!(netdev->features & NETIF_F_RXFCS))
1442 pskb_trim(skb, skb->len - 4);
1443 }
1444
1445copydone:
1446 total_rx_bytes += skb->len;
1447 total_rx_packets++;
1448
1449 e1000_rx_checksum(adapter, staterr, skb);
1450
1451 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1452
1453 if (rx_desc->wb.upper.header_status &
1454 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1455 adapter->rx_hdr_split++;
1456
1457 e1000_receive_skb(adapter, netdev, skb, staterr,
1458 rx_desc->wb.middle.vlan);
1459
1460next_desc:
1461 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1462 buffer_info->skb = NULL;
1463
1464 /* return some buffers to hardware, one at a time is too slow */
1465 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1466 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1467 GFP_ATOMIC);
1468 cleaned_count = 0;
1469 }
1470
1471 /* use prefetched values */
1472 rx_desc = next_rxd;
1473 buffer_info = next_buffer;
1474
1475 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1476 }
1477 rx_ring->next_to_clean = i;
1478
1479 cleaned_count = e1000_desc_unused(rx_ring);
1480 if (cleaned_count)
1481 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1482
1483 adapter->total_rx_bytes += total_rx_bytes;
1484 adapter->total_rx_packets += total_rx_packets;
1485 return cleaned;
1486}
1487
1488static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1489 u16 length)
1490{
1491 bi->page = NULL;
1492 skb->len += length;
1493 skb->data_len += length;
1494 skb->truesize += PAGE_SIZE;
1495}
1496
1497/**
1498 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1499 * @rx_ring: Rx descriptor ring
1500 * @work_done: output parameter for indicating completed work
1501 * @work_to_do: how many packets we can clean
1502 *
1503 * the return value indicates whether actual cleaning was done, there
1504 * is no guarantee that everything was cleaned
1505 **/
1506static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1507 int work_to_do)
1508{
1509 struct e1000_adapter *adapter = rx_ring->adapter;
1510 struct net_device *netdev = adapter->netdev;
1511 struct pci_dev *pdev = adapter->pdev;
1512 union e1000_rx_desc_extended *rx_desc, *next_rxd;
1513 struct e1000_buffer *buffer_info, *next_buffer;
1514 u32 length, staterr;
1515 unsigned int i;
1516 int cleaned_count = 0;
1517 bool cleaned = false;
1518 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1519 struct skb_shared_info *shinfo;
1520
1521 i = rx_ring->next_to_clean;
1522 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1524 buffer_info = &rx_ring->buffer_info[i];
1525
1526 while (staterr & E1000_RXD_STAT_DD) {
1527 struct sk_buff *skb;
1528
1529 if (*work_done >= work_to_do)
1530 break;
1531 (*work_done)++;
1532 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1533
1534 skb = buffer_info->skb;
1535 buffer_info->skb = NULL;
1536
1537 ++i;
1538 if (i == rx_ring->count)
1539 i = 0;
1540 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
1541 prefetch(next_rxd);
1542
1543 next_buffer = &rx_ring->buffer_info[i];
1544
1545 cleaned = true;
1546 cleaned_count++;
1547 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1548 DMA_FROM_DEVICE);
1549 buffer_info->dma = 0;
1550
1551 length = le16_to_cpu(rx_desc->wb.upper.length);
1552
1553 /* errors is only valid for DD + EOP descriptors */
1554 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
1555 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1556 !(netdev->features & NETIF_F_RXALL)))) {
1557 /* recycle both page and skb */
1558 buffer_info->skb = skb;
1559 /* an error means any chain goes out the window too */
1560 if (rx_ring->rx_skb_top)
1561 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1562 rx_ring->rx_skb_top = NULL;
1563 goto next_desc;
1564 }
1565#define rxtop (rx_ring->rx_skb_top)
1566 if (!(staterr & E1000_RXD_STAT_EOP)) {
1567 /* this descriptor is only the beginning (or middle) */
1568 if (!rxtop) {
1569 /* this is the beginning of a chain */
1570 rxtop = skb;
1571 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1572 0, length);
1573 } else {
1574 /* this is the middle of a chain */
1575 shinfo = skb_shinfo(rxtop);
1576 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1577 buffer_info->page, 0,
1578 length);
1579 /* re-use the skb, only consumed the page */
1580 buffer_info->skb = skb;
1581 }
1582 e1000_consume_page(buffer_info, rxtop, length);
1583 goto next_desc;
1584 } else {
1585 if (rxtop) {
1586 /* end of the chain */
1587 shinfo = skb_shinfo(rxtop);
1588 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1589 buffer_info->page, 0,
1590 length);
1591 /* re-use the current skb, we only consumed the
1592 * page
1593 */
1594 buffer_info->skb = skb;
1595 skb = rxtop;
1596 rxtop = NULL;
1597 e1000_consume_page(buffer_info, skb, length);
1598 } else {
1599 /* no chain, got EOP, this buf is the packet
1600 * copybreak to save the put_page/alloc_page
1601 */
1602 if (length <= copybreak &&
1603 skb_tailroom(skb) >= length) {
1604 memcpy(skb_tail_pointer(skb),
1605 page_address(buffer_info->page),
1606 length);
1607 /* re-use the page, so don't erase
1608 * buffer_info->page
1609 */
1610 skb_put(skb, length);
1611 } else {
1612 skb_fill_page_desc(skb, 0,
1613 buffer_info->page, 0,
1614 length);
1615 e1000_consume_page(buffer_info, skb,
1616 length);
1617 }
1618 }
1619 }
1620
1621 /* Receive Checksum Offload */
1622 e1000_rx_checksum(adapter, staterr, skb);
1623
1624 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1625
1626 /* probably a little skewed due to removing CRC */
1627 total_rx_bytes += skb->len;
1628 total_rx_packets++;
1629
1630 /* eth type trans needs skb->data to point to something */
1631 if (!pskb_may_pull(skb, ETH_HLEN)) {
1632 e_err("pskb_may_pull failed.\n");
1633 dev_kfree_skb_irq(skb);
1634 goto next_desc;
1635 }
1636
1637 e1000_receive_skb(adapter, netdev, skb, staterr,
1638 rx_desc->wb.upper.vlan);
1639
1640next_desc:
1641 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1642
1643 /* return some buffers to hardware, one at a time is too slow */
1644 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
1645 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1646 GFP_ATOMIC);
1647 cleaned_count = 0;
1648 }
1649
1650 /* use prefetched values */
1651 rx_desc = next_rxd;
1652 buffer_info = next_buffer;
1653
1654 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1655 }
1656 rx_ring->next_to_clean = i;
1657
1658 cleaned_count = e1000_desc_unused(rx_ring);
1659 if (cleaned_count)
1660 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1661
1662 adapter->total_rx_bytes += total_rx_bytes;
1663 adapter->total_rx_packets += total_rx_packets;
1664 return cleaned;
1665}
1666
1667/**
1668 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1669 * @rx_ring: Rx descriptor ring
1670 **/
1671static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
1672{
1673 struct e1000_adapter *adapter = rx_ring->adapter;
1674 struct e1000_buffer *buffer_info;
1675 struct e1000_ps_page *ps_page;
1676 struct pci_dev *pdev = adapter->pdev;
1677 unsigned int i, j;
1678
1679 /* Free all the Rx ring sk_buffs */
1680 for (i = 0; i < rx_ring->count; i++) {
1681 buffer_info = &rx_ring->buffer_info[i];
1682 if (buffer_info->dma) {
1683 if (adapter->clean_rx == e1000_clean_rx_irq)
1684 dma_unmap_single(&pdev->dev, buffer_info->dma,
1685 adapter->rx_buffer_len,
1686 DMA_FROM_DEVICE);
1687 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
1688 dma_unmap_page(&pdev->dev, buffer_info->dma,
1689 PAGE_SIZE, DMA_FROM_DEVICE);
1690 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
1691 dma_unmap_single(&pdev->dev, buffer_info->dma,
1692 adapter->rx_ps_bsize0,
1693 DMA_FROM_DEVICE);
1694 buffer_info->dma = 0;
1695 }
1696
1697 if (buffer_info->page) {
1698 put_page(buffer_info->page);
1699 buffer_info->page = NULL;
1700 }
1701
1702 if (buffer_info->skb) {
1703 dev_kfree_skb(buffer_info->skb);
1704 buffer_info->skb = NULL;
1705 }
1706
1707 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1708 ps_page = &buffer_info->ps_pages[j];
1709 if (!ps_page->page)
1710 break;
1711 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1712 DMA_FROM_DEVICE);
1713 ps_page->dma = 0;
1714 put_page(ps_page->page);
1715 ps_page->page = NULL;
1716 }
1717 }
1718
1719 /* there also may be some cached data from a chained receive */
1720 if (rx_ring->rx_skb_top) {
1721 dev_kfree_skb(rx_ring->rx_skb_top);
1722 rx_ring->rx_skb_top = NULL;
1723 }
1724
1725 /* Zero out the descriptor ring */
1726 memset(rx_ring->desc, 0, rx_ring->size);
1727
1728 rx_ring->next_to_clean = 0;
1729 rx_ring->next_to_use = 0;
1730 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1731}
1732
1733static void e1000e_downshift_workaround(struct work_struct *work)
1734{
1735 struct e1000_adapter *adapter = container_of(work,
1736 struct e1000_adapter,
1737 downshift_task);
1738
1739 if (test_bit(__E1000_DOWN, &adapter->state))
1740 return;
1741
1742 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1743}
1744
1745/**
1746 * e1000_intr_msi - Interrupt Handler
1747 * @irq: interrupt number
1748 * @data: pointer to a network interface device structure
1749 **/
1750static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
1751{
1752 struct net_device *netdev = data;
1753 struct e1000_adapter *adapter = netdev_priv(netdev);
1754 struct e1000_hw *hw = &adapter->hw;
1755 u32 icr = er32(ICR);
1756
1757 /* read ICR disables interrupts using IAM */
1758 if (icr & E1000_ICR_LSC) {
1759 hw->mac.get_link_status = true;
1760 /* ICH8 workaround-- Call gig speed drop workaround on cable
1761 * disconnect (LSC) before accessing any PHY registers
1762 */
1763 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1764 (!(er32(STATUS) & E1000_STATUS_LU)))
1765 schedule_work(&adapter->downshift_task);
1766
1767 /* 80003ES2LAN workaround-- For packet buffer work-around on
1768 * link down event; disable receives here in the ISR and reset
1769 * adapter in watchdog
1770 */
1771 if (netif_carrier_ok(netdev) &&
1772 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1773 /* disable receives */
1774 u32 rctl = er32(RCTL);
1775
1776 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1777 adapter->flags |= FLAG_RESTART_NOW;
1778 }
1779 /* guard against interrupt when we're going down */
1780 if (!test_bit(__E1000_DOWN, &adapter->state))
1781 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1782 }
1783
1784 /* Reset on uncorrectable ECC error */
1785 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1786 u32 pbeccsts = er32(PBECCSTS);
1787
1788 adapter->corr_errors +=
1789 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1790 adapter->uncorr_errors +=
1791 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);
1792
1793 /* Do the reset outside of interrupt context */
1794 schedule_work(&adapter->reset_task);
1795
1796 /* return immediately since reset is imminent */
1797 return IRQ_HANDLED;
1798 }
1799
1800 if (napi_schedule_prep(&adapter->napi)) {
1801 adapter->total_tx_bytes = 0;
1802 adapter->total_tx_packets = 0;
1803 adapter->total_rx_bytes = 0;
1804 adapter->total_rx_packets = 0;
1805 __napi_schedule(&adapter->napi);
1806 }
1807
1808 return IRQ_HANDLED;
1809}
1810
1811/**
1812 * e1000_intr - Interrupt Handler
1813 * @irq: interrupt number
1814 * @data: pointer to a network interface device structure
1815 **/
1816static irqreturn_t e1000_intr(int __always_unused irq, void *data)
1817{
1818 struct net_device *netdev = data;
1819 struct e1000_adapter *adapter = netdev_priv(netdev);
1820 struct e1000_hw *hw = &adapter->hw;
1821 u32 rctl, icr = er32(ICR);
1822
1823 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
1824 return IRQ_NONE; /* Not our interrupt */
1825
1826 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1827 * not set, then the adapter didn't send an interrupt
1828 */
1829 if (!(icr & E1000_ICR_INT_ASSERTED))
1830 return IRQ_NONE;
1831
1832 /* Interrupt Auto-Mask...upon reading ICR,
1833 * interrupts are masked. No need for the
1834 * IMC write
1835 */
1836
1837 if (icr & E1000_ICR_LSC) {
1838 hw->mac.get_link_status = true;
1839 /* ICH8 workaround-- Call gig speed drop workaround on cable
1840 * disconnect (LSC) before accessing any PHY registers
1841 */
1842 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1843 (!(er32(STATUS) & E1000_STATUS_LU)))
1844 schedule_work(&adapter->downshift_task);
1845
1846 /* 80003ES2LAN workaround--
1847 * For packet buffer work-around on link down event;
1848 * disable receives here in the ISR and
1849 * reset adapter in watchdog
1850 */
1851 if (netif_carrier_ok(netdev) &&
1852 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1853 /* disable receives */
1854 rctl = er32(RCTL);
1855 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1856 adapter->flags |= FLAG_RESTART_NOW;
1857 }
1858 /* guard against interrupt when we're going down */
1859 if (!test_bit(__E1000_DOWN, &adapter->state))
1860 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1861 }
1862
1863 /* Reset on uncorrectable ECC error */
1864 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1865 u32 pbeccsts = er32(PBECCSTS);
1866
1867 adapter->corr_errors +=
1868 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1869 adapter->uncorr_errors +=
1870 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);
1871
1872 /* Do the reset outside of interrupt context */
1873 schedule_work(&adapter->reset_task);
1874
1875 /* return immediately since reset is imminent */
1876 return IRQ_HANDLED;
1877 }
1878
1879 if (napi_schedule_prep(&adapter->napi)) {
1880 adapter->total_tx_bytes = 0;
1881 adapter->total_tx_packets = 0;
1882 adapter->total_rx_bytes = 0;
1883 adapter->total_rx_packets = 0;
1884 __napi_schedule(&adapter->napi);
1885 }
1886
1887 return IRQ_HANDLED;
1888}
1889
1890static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
1891{
1892 struct net_device *netdev = data;
1893 struct e1000_adapter *adapter = netdev_priv(netdev);
1894 struct e1000_hw *hw = &adapter->hw;
1895 u32 icr = er32(ICR);
1896
1897 if (icr & adapter->eiac_mask)
1898 ew32(ICS, (icr & adapter->eiac_mask));
1899
1900 if (icr & E1000_ICR_LSC) {
1901 hw->mac.get_link_status = true;
1902 /* guard against interrupt when we're going down */
1903 if (!test_bit(__E1000_DOWN, &adapter->state))
1904 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1905 }
1906
1907 if (!test_bit(__E1000_DOWN, &adapter->state))
1908 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK);
1909
1910 return IRQ_HANDLED;
1911}
1912
1913static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
1914{
1915 struct net_device *netdev = data;
1916 struct e1000_adapter *adapter = netdev_priv(netdev);
1917 struct e1000_hw *hw = &adapter->hw;
1918 struct e1000_ring *tx_ring = adapter->tx_ring;
1919
1920 adapter->total_tx_bytes = 0;
1921 adapter->total_tx_packets = 0;
1922
1923 if (!e1000_clean_tx_irq(tx_ring))
1924 /* Ring was not completely cleaned, so fire another interrupt */
1925 ew32(ICS, tx_ring->ims_val);
1926
1927 if (!test_bit(__E1000_DOWN, &adapter->state))
1928 ew32(IMS, adapter->tx_ring->ims_val);
1929
1930 return IRQ_HANDLED;
1931}
1932
1933static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
1934{
1935 struct net_device *netdev = data;
1936 struct e1000_adapter *adapter = netdev_priv(netdev);
1937 struct e1000_ring *rx_ring = adapter->rx_ring;
1938
1939 /* Write the ITR value calculated at the end of the
1940 * previous interrupt.
1941 */
1942 if (rx_ring->set_itr) {
1943 u32 itr = rx_ring->itr_val ?
1944 1000000000 / (rx_ring->itr_val * 256) : 0;
1945
1946 writel(itr, rx_ring->itr_register);
1947 rx_ring->set_itr = 0;
1948 }
1949
1950 if (napi_schedule_prep(&adapter->napi)) {
1951 adapter->total_rx_bytes = 0;
1952 adapter->total_rx_packets = 0;
1953 __napi_schedule(&adapter->napi);
1954 }
1955 return IRQ_HANDLED;
1956}
1957
1958/**
1959 * e1000_configure_msix - Configure MSI-X hardware
1960 * @adapter: board private structure
1961 *
1962 * e1000_configure_msix sets up the hardware to properly
1963 * generate MSI-X interrupts.
1964 **/
1965static void e1000_configure_msix(struct e1000_adapter *adapter)
1966{
1967 struct e1000_hw *hw = &adapter->hw;
1968 struct e1000_ring *rx_ring = adapter->rx_ring;
1969 struct e1000_ring *tx_ring = adapter->tx_ring;
1970 int vector = 0;
1971 u32 ctrl_ext, ivar = 0;
1972
1973 adapter->eiac_mask = 0;
1974
1975 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1976 if (hw->mac.type == e1000_82574) {
1977 u32 rfctl = er32(RFCTL);
1978
1979 rfctl |= E1000_RFCTL_ACK_DIS;
1980 ew32(RFCTL, rfctl);
1981 }
1982
1983 /* Configure Rx vector */
1984 rx_ring->ims_val = E1000_IMS_RXQ0;
1985 adapter->eiac_mask |= rx_ring->ims_val;
1986 if (rx_ring->itr_val)
1987 writel(1000000000 / (rx_ring->itr_val * 256),
1988 rx_ring->itr_register);
1989 else
1990 writel(1, rx_ring->itr_register);
1991 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1992
1993 /* Configure Tx vector */
1994 tx_ring->ims_val = E1000_IMS_TXQ0;
1995 vector++;
1996 if (tx_ring->itr_val)
1997 writel(1000000000 / (tx_ring->itr_val * 256),
1998 tx_ring->itr_register);
1999 else
2000 writel(1, tx_ring->itr_register);
2001 adapter->eiac_mask |= tx_ring->ims_val;
2002 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
2003
2004 /* set vector for Other Causes, e.g. link changes */
2005 vector++;
2006 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
2007 if (rx_ring->itr_val)
2008 writel(1000000000 / (rx_ring->itr_val * 256),
2009 hw->hw_addr + E1000_EITR_82574(vector));
2010 else
2011 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
2012
2013 /* Cause Tx interrupts on every write back */
2014 ivar |= BIT(31);
2015
2016 ew32(IVAR, ivar);
2017
2018 /* enable MSI-X PBA support */
2019 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME;
2020 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME;
2021 ew32(CTRL_EXT, ctrl_ext);
2022 e1e_flush();
2023}
2024
2025void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2026{
2027 if (adapter->msix_entries) {
2028 pci_disable_msix(adapter->pdev);
2029 kfree(adapter->msix_entries);
2030 adapter->msix_entries = NULL;
2031 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2032 pci_disable_msi(adapter->pdev);
2033 adapter->flags &= ~FLAG_MSI_ENABLED;
2034 }
2035}
2036
2037/**
2038 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2039 * @adapter: board private structure
2040 *
2041 * Attempt to configure interrupts using the best available
2042 * capabilities of the hardware and kernel.
2043 **/
2044void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2045{
2046 int err;
2047 int i;
2048
2049 switch (adapter->int_mode) {
2050 case E1000E_INT_MODE_MSIX:
2051 if (adapter->flags & FLAG_HAS_MSIX) {
2052 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2053 adapter->msix_entries = kcalloc(adapter->num_vectors,
2054 sizeof(struct
2055 msix_entry),
2056 GFP_KERNEL);
2057 if (adapter->msix_entries) {
2058 struct e1000_adapter *a = adapter;
2059
2060 for (i = 0; i < adapter->num_vectors; i++)
2061 adapter->msix_entries[i].entry = i;
2062
2063 err = pci_enable_msix_range(a->pdev,
2064 a->msix_entries,
2065 a->num_vectors,
2066 a->num_vectors);
2067 if (err > 0)
2068 return;
2069 }
2070 /* MSI-X failed, so fall through and try MSI */
2071 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
2072 e1000e_reset_interrupt_capability(adapter);
2073 }
2074 adapter->int_mode = E1000E_INT_MODE_MSI;
2075 fallthrough;
2076 case E1000E_INT_MODE_MSI:
2077 if (!pci_enable_msi(adapter->pdev)) {
2078 adapter->flags |= FLAG_MSI_ENABLED;
2079 } else {
2080 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2081 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
2082 }
2083 fallthrough;
2084 case E1000E_INT_MODE_LEGACY:
2085 /* Don't do anything; this is the system default */
2086 break;
2087 }
2088
2089 /* store the number of vectors being used */
2090 adapter->num_vectors = 1;
2091}
2092
2093/**
2094 * e1000_request_msix - Initialize MSI-X interrupts
2095 * @adapter: board private structure
2096 *
2097 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2098 * kernel.
2099 **/
2100static int e1000_request_msix(struct e1000_adapter *adapter)
2101{
2102 struct net_device *netdev = adapter->netdev;
2103 int err = 0, vector = 0;
2104
2105 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2106 snprintf(adapter->rx_ring->name,
2107 sizeof(adapter->rx_ring->name) - 1,
2108 "%.14s-rx-0", netdev->name);
2109 else
2110 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2111 err = request_irq(adapter->msix_entries[vector].vector,
2112 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
2113 netdev);
2114 if (err)
2115 return err;
2116 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2117 E1000_EITR_82574(vector);
2118 adapter->rx_ring->itr_val = adapter->itr;
2119 vector++;
2120
2121 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2122 snprintf(adapter->tx_ring->name,
2123 sizeof(adapter->tx_ring->name) - 1,
2124 "%.14s-tx-0", netdev->name);
2125 else
2126 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2127 err = request_irq(adapter->msix_entries[vector].vector,
2128 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
2129 netdev);
2130 if (err)
2131 return err;
2132 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2133 E1000_EITR_82574(vector);
2134 adapter->tx_ring->itr_val = adapter->itr;
2135 vector++;
2136
2137 err = request_irq(adapter->msix_entries[vector].vector,
2138 e1000_msix_other, 0, netdev->name, netdev);
2139 if (err)
2140 return err;
2141
2142 e1000_configure_msix(adapter);
2143
2144 return 0;
2145}
2146
2147/**
2148 * e1000_request_irq - initialize interrupts
2149 * @adapter: board private structure
2150 *
2151 * Attempts to configure interrupts using the best available
2152 * capabilities of the hardware and kernel.
2153 **/
2154static int e1000_request_irq(struct e1000_adapter *adapter)
2155{
2156 struct net_device *netdev = adapter->netdev;
2157 int err;
2158
2159 if (adapter->msix_entries) {
2160 err = e1000_request_msix(adapter);
2161 if (!err)
2162 return err;
2163 /* fall back to MSI */
2164 e1000e_reset_interrupt_capability(adapter);
2165 adapter->int_mode = E1000E_INT_MODE_MSI;
2166 e1000e_set_interrupt_capability(adapter);
2167 }
2168 if (adapter->flags & FLAG_MSI_ENABLED) {
2169 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
2170 netdev->name, netdev);
2171 if (!err)
2172 return err;
2173
2174 /* fall back to legacy interrupt */
2175 e1000e_reset_interrupt_capability(adapter);
2176 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2177 }
2178
2179 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
2180 netdev->name, netdev);
2181 if (err)
2182 e_err("Unable to allocate interrupt, Error: %d\n", err);
2183
2184 return err;
2185}
2186
2187static void e1000_free_irq(struct e1000_adapter *adapter)
2188{
2189 struct net_device *netdev = adapter->netdev;
2190
2191 if (adapter->msix_entries) {
2192 int vector = 0;
2193
2194 free_irq(adapter->msix_entries[vector].vector, netdev);
2195 vector++;
2196
2197 free_irq(adapter->msix_entries[vector].vector, netdev);
2198 vector++;
2199
2200 /* Other Causes interrupt vector */
2201 free_irq(adapter->msix_entries[vector].vector, netdev);
2202 return;
2203 }
2204
2205 free_irq(adapter->pdev->irq, netdev);
2206}
2207
2208/**
2209 * e1000_irq_disable - Mask off interrupt generation on the NIC
2210 * @adapter: board private structure
2211 **/
2212static void e1000_irq_disable(struct e1000_adapter *adapter)
2213{
2214 struct e1000_hw *hw = &adapter->hw;
2215
2216 ew32(IMC, ~0);
2217 if (adapter->msix_entries)
2218 ew32(EIAC_82574, 0);
2219 e1e_flush();
2220
2221 if (adapter->msix_entries) {
2222 int i;
2223
2224 for (i = 0; i < adapter->num_vectors; i++)
2225 synchronize_irq(adapter->msix_entries[i].vector);
2226 } else {
2227 synchronize_irq(adapter->pdev->irq);
2228 }
2229}
2230
2231/**
2232 * e1000_irq_enable - Enable default interrupt generation settings
2233 * @adapter: board private structure
2234 **/
2235static void e1000_irq_enable(struct e1000_adapter *adapter)
2236{
2237 struct e1000_hw *hw = &adapter->hw;
2238
2239 if (adapter->msix_entries) {
2240 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2241 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER |
2242 IMS_OTHER_MASK);
2243 } else if (hw->mac.type >= e1000_pch_lpt) {
2244 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
2245 } else {
2246 ew32(IMS, IMS_ENABLE_MASK);
2247 }
2248 e1e_flush();
2249}
2250
2251/**
2252 * e1000e_get_hw_control - get control of the h/w from f/w
2253 * @adapter: address of board private structure
2254 *
2255 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2256 * For ASF and Pass Through versions of f/w this means that
2257 * the driver is loaded. For AMT version (only with 82573)
2258 * of the f/w this means that the network i/f is open.
2259 **/
2260void e1000e_get_hw_control(struct e1000_adapter *adapter)
2261{
2262 struct e1000_hw *hw = &adapter->hw;
2263 u32 ctrl_ext;
2264 u32 swsm;
2265
2266 /* Let firmware know the driver has taken over */
2267 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2268 swsm = er32(SWSM);
2269 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2270 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2271 ctrl_ext = er32(CTRL_EXT);
2272 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2273 }
2274}
2275
2276/**
2277 * e1000e_release_hw_control - release control of the h/w to f/w
2278 * @adapter: address of board private structure
2279 *
2280 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2281 * For ASF and Pass Through versions of f/w this means that the
2282 * driver is no longer loaded. For AMT version (only with 82573) i
2283 * of the f/w this means that the network i/f is closed.
2284 *
2285 **/
2286void e1000e_release_hw_control(struct e1000_adapter *adapter)
2287{
2288 struct e1000_hw *hw = &adapter->hw;
2289 u32 ctrl_ext;
2290 u32 swsm;
2291
2292 /* Let firmware taken over control of h/w */
2293 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2294 swsm = er32(SWSM);
2295 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2296 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2297 ctrl_ext = er32(CTRL_EXT);
2298 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2299 }
2300}
2301
2302/**
2303 * e1000_alloc_ring_dma - allocate memory for a ring structure
2304 * @adapter: board private structure
2305 * @ring: ring struct for which to allocate dma
2306 **/
2307static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2308 struct e1000_ring *ring)
2309{
2310 struct pci_dev *pdev = adapter->pdev;
2311
2312 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2313 GFP_KERNEL);
2314 if (!ring->desc)
2315 return -ENOMEM;
2316
2317 return 0;
2318}
2319
2320/**
2321 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2322 * @tx_ring: Tx descriptor ring
2323 *
2324 * Return 0 on success, negative on failure
2325 **/
2326int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
2327{
2328 struct e1000_adapter *adapter = tx_ring->adapter;
2329 int err = -ENOMEM, size;
2330
2331 size = sizeof(struct e1000_buffer) * tx_ring->count;
2332 tx_ring->buffer_info = vzalloc(size);
2333 if (!tx_ring->buffer_info)
2334 goto err;
2335
2336 /* round up to nearest 4K */
2337 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2338 tx_ring->size = ALIGN(tx_ring->size, 4096);
2339
2340 err = e1000_alloc_ring_dma(adapter, tx_ring);
2341 if (err)
2342 goto err;
2343
2344 tx_ring->next_to_use = 0;
2345 tx_ring->next_to_clean = 0;
2346
2347 return 0;
2348err:
2349 vfree(tx_ring->buffer_info);
2350 e_err("Unable to allocate memory for the transmit descriptor ring\n");
2351 return err;
2352}
2353
2354/**
2355 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2356 * @rx_ring: Rx descriptor ring
2357 *
2358 * Returns 0 on success, negative on failure
2359 **/
2360int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
2361{
2362 struct e1000_adapter *adapter = rx_ring->adapter;
2363 struct e1000_buffer *buffer_info;
2364 int i, size, desc_len, err = -ENOMEM;
2365
2366 size = sizeof(struct e1000_buffer) * rx_ring->count;
2367 rx_ring->buffer_info = vzalloc(size);
2368 if (!rx_ring->buffer_info)
2369 goto err;
2370
2371 for (i = 0; i < rx_ring->count; i++) {
2372 buffer_info = &rx_ring->buffer_info[i];
2373 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2374 sizeof(struct e1000_ps_page),
2375 GFP_KERNEL);
2376 if (!buffer_info->ps_pages)
2377 goto err_pages;
2378 }
2379
2380 desc_len = sizeof(union e1000_rx_desc_packet_split);
2381
2382 /* Round up to nearest 4K */
2383 rx_ring->size = rx_ring->count * desc_len;
2384 rx_ring->size = ALIGN(rx_ring->size, 4096);
2385
2386 err = e1000_alloc_ring_dma(adapter, rx_ring);
2387 if (err)
2388 goto err_pages;
2389
2390 rx_ring->next_to_clean = 0;
2391 rx_ring->next_to_use = 0;
2392 rx_ring->rx_skb_top = NULL;
2393
2394 return 0;
2395
2396err_pages:
2397 for (i = 0; i < rx_ring->count; i++) {
2398 buffer_info = &rx_ring->buffer_info[i];
2399 kfree(buffer_info->ps_pages);
2400 }
2401err:
2402 vfree(rx_ring->buffer_info);
2403 e_err("Unable to allocate memory for the receive descriptor ring\n");
2404 return err;
2405}
2406
2407/**
2408 * e1000_clean_tx_ring - Free Tx Buffers
2409 * @tx_ring: Tx descriptor ring
2410 **/
2411static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
2412{
2413 struct e1000_adapter *adapter = tx_ring->adapter;
2414 struct e1000_buffer *buffer_info;
2415 unsigned long size;
2416 unsigned int i;
2417
2418 for (i = 0; i < tx_ring->count; i++) {
2419 buffer_info = &tx_ring->buffer_info[i];
2420 e1000_put_txbuf(tx_ring, buffer_info, false);
2421 }
2422
2423 netdev_reset_queue(adapter->netdev);
2424 size = sizeof(struct e1000_buffer) * tx_ring->count;
2425 memset(tx_ring->buffer_info, 0, size);
2426
2427 memset(tx_ring->desc, 0, tx_ring->size);
2428
2429 tx_ring->next_to_use = 0;
2430 tx_ring->next_to_clean = 0;
2431}
2432
2433/**
2434 * e1000e_free_tx_resources - Free Tx Resources per Queue
2435 * @tx_ring: Tx descriptor ring
2436 *
2437 * Free all transmit software resources
2438 **/
2439void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
2440{
2441 struct e1000_adapter *adapter = tx_ring->adapter;
2442 struct pci_dev *pdev = adapter->pdev;
2443
2444 e1000_clean_tx_ring(tx_ring);
2445
2446 vfree(tx_ring->buffer_info);
2447 tx_ring->buffer_info = NULL;
2448
2449 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2450 tx_ring->dma);
2451 tx_ring->desc = NULL;
2452}
2453
2454/**
2455 * e1000e_free_rx_resources - Free Rx Resources
2456 * @rx_ring: Rx descriptor ring
2457 *
2458 * Free all receive software resources
2459 **/
2460void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
2461{
2462 struct e1000_adapter *adapter = rx_ring->adapter;
2463 struct pci_dev *pdev = adapter->pdev;
2464 int i;
2465
2466 e1000_clean_rx_ring(rx_ring);
2467
2468 for (i = 0; i < rx_ring->count; i++)
2469 kfree(rx_ring->buffer_info[i].ps_pages);
2470
2471 vfree(rx_ring->buffer_info);
2472 rx_ring->buffer_info = NULL;
2473
2474 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2475 rx_ring->dma);
2476 rx_ring->desc = NULL;
2477}
2478
2479/**
2480 * e1000_update_itr - update the dynamic ITR value based on statistics
2481 * @itr_setting: current adapter->itr
2482 * @packets: the number of packets during this measurement interval
2483 * @bytes: the number of bytes during this measurement interval
2484 *
2485 * Stores a new ITR value based on packets and byte
2486 * counts during the last interrupt. The advantage of per interrupt
2487 * computation is faster updates and more accurate ITR for the current
2488 * traffic pattern. Constants in this function were computed
2489 * based on theoretical maximum wire speed and thresholds were set based
2490 * on testing data as well as attempting to minimize response time
2491 * while increasing bulk throughput. This functionality is controlled
2492 * by the InterruptThrottleRate module parameter.
2493 **/
2494static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
2495{
2496 unsigned int retval = itr_setting;
2497
2498 if (packets == 0)
2499 return itr_setting;
2500
2501 switch (itr_setting) {
2502 case lowest_latency:
2503 /* handle TSO and jumbo frames */
2504 if (bytes / packets > 8000)
2505 retval = bulk_latency;
2506 else if ((packets < 5) && (bytes > 512))
2507 retval = low_latency;
2508 break;
2509 case low_latency: /* 50 usec aka 20000 ints/s */
2510 if (bytes > 10000) {
2511 /* this if handles the TSO accounting */
2512 if (bytes / packets > 8000)
2513 retval = bulk_latency;
2514 else if ((packets < 10) || ((bytes / packets) > 1200))
2515 retval = bulk_latency;
2516 else if ((packets > 35))
2517 retval = lowest_latency;
2518 } else if (bytes / packets > 2000) {
2519 retval = bulk_latency;
2520 } else if (packets <= 2 && bytes < 512) {
2521 retval = lowest_latency;
2522 }
2523 break;
2524 case bulk_latency: /* 250 usec aka 4000 ints/s */
2525 if (bytes > 25000) {
2526 if (packets > 35)
2527 retval = low_latency;
2528 } else if (bytes < 6000) {
2529 retval = low_latency;
2530 }
2531 break;
2532 }
2533
2534 return retval;
2535}
2536
2537static void e1000_set_itr(struct e1000_adapter *adapter)
2538{
2539 u16 current_itr;
2540 u32 new_itr = adapter->itr;
2541
2542 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2543 if (adapter->link_speed != SPEED_1000) {
2544 new_itr = 4000;
2545 goto set_itr_now;
2546 }
2547
2548 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2549 new_itr = 0;
2550 goto set_itr_now;
2551 }
2552
2553 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2554 adapter->total_tx_packets,
2555 adapter->total_tx_bytes);
2556 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2557 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2558 adapter->tx_itr = low_latency;
2559
2560 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2561 adapter->total_rx_packets,
2562 adapter->total_rx_bytes);
2563 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2564 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2565 adapter->rx_itr = low_latency;
2566
2567 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2568
2569 /* counts and packets in update_itr are dependent on these numbers */
2570 switch (current_itr) {
2571 case lowest_latency:
2572 new_itr = 70000;
2573 break;
2574 case low_latency:
2575 new_itr = 20000; /* aka hwitr = ~200 */
2576 break;
2577 case bulk_latency:
2578 new_itr = 4000;
2579 break;
2580 default:
2581 break;
2582 }
2583
2584set_itr_now:
2585 if (new_itr != adapter->itr) {
2586 /* this attempts to bias the interrupt rate towards Bulk
2587 * by adding intermediate steps when interrupt rate is
2588 * increasing
2589 */
2590 new_itr = new_itr > adapter->itr ?
2591 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
2592 adapter->itr = new_itr;
2593 adapter->rx_ring->itr_val = new_itr;
2594 if (adapter->msix_entries)
2595 adapter->rx_ring->set_itr = 1;
2596 else
2597 e1000e_write_itr(adapter, new_itr);
2598 }
2599}
2600
2601/**
2602 * e1000e_write_itr - write the ITR value to the appropriate registers
2603 * @adapter: address of board private structure
2604 * @itr: new ITR value to program
2605 *
2606 * e1000e_write_itr determines if the adapter is in MSI-X mode
2607 * and, if so, writes the EITR registers with the ITR value.
2608 * Otherwise, it writes the ITR value into the ITR register.
2609 **/
2610void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2611{
2612 struct e1000_hw *hw = &adapter->hw;
2613 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2614
2615 if (adapter->msix_entries) {
2616 int vector;
2617
2618 for (vector = 0; vector < adapter->num_vectors; vector++)
2619 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2620 } else {
2621 ew32(ITR, new_itr);
2622 }
2623}
2624
2625/**
2626 * e1000_alloc_queues - Allocate memory for all rings
2627 * @adapter: board private structure to initialize
2628 **/
2629static int e1000_alloc_queues(struct e1000_adapter *adapter)
2630{
2631 int size = sizeof(struct e1000_ring);
2632
2633 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
2634 if (!adapter->tx_ring)
2635 goto err;
2636 adapter->tx_ring->count = adapter->tx_ring_count;
2637 adapter->tx_ring->adapter = adapter;
2638
2639 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
2640 if (!adapter->rx_ring)
2641 goto err;
2642 adapter->rx_ring->count = adapter->rx_ring_count;
2643 adapter->rx_ring->adapter = adapter;
2644
2645 return 0;
2646err:
2647 e_err("Unable to allocate memory for queues\n");
2648 kfree(adapter->rx_ring);
2649 kfree(adapter->tx_ring);
2650 return -ENOMEM;
2651}
2652
2653/**
2654 * e1000e_poll - NAPI Rx polling callback
2655 * @napi: struct associated with this polling callback
2656 * @budget: number of packets driver is allowed to process this poll
2657 **/
2658static int e1000e_poll(struct napi_struct *napi, int budget)
2659{
2660 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2661 napi);
2662 struct e1000_hw *hw = &adapter->hw;
2663 struct net_device *poll_dev = adapter->netdev;
2664 int tx_cleaned = 1, work_done = 0;
2665
2666 adapter = netdev_priv(poll_dev);
2667
2668 if (!adapter->msix_entries ||
2669 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2670 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
2671
2672 adapter->clean_rx(adapter->rx_ring, &work_done, budget);
2673
2674 if (!tx_cleaned || work_done == budget)
2675 return budget;
2676
2677 /* Exit the polling mode, but don't re-enable interrupts if stack might
2678 * poll us due to busy-polling
2679 */
2680 if (likely(napi_complete_done(napi, work_done))) {
2681 if (adapter->itr_setting & 3)
2682 e1000_set_itr(adapter);
2683 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2684 if (adapter->msix_entries)
2685 ew32(IMS, adapter->rx_ring->ims_val);
2686 else
2687 e1000_irq_enable(adapter);
2688 }
2689 }
2690
2691 return work_done;
2692}
2693
2694static int e1000_vlan_rx_add_vid(struct net_device *netdev,
2695 __always_unused __be16 proto, u16 vid)
2696{
2697 struct e1000_adapter *adapter = netdev_priv(netdev);
2698 struct e1000_hw *hw = &adapter->hw;
2699 u32 vfta, index;
2700
2701 /* don't update vlan cookie if already programmed */
2702 if ((adapter->hw.mng_cookie.status &
2703 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2704 (vid == adapter->mng_vlan_id))
2705 return 0;
2706
2707 /* add VID to filter table */
2708 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2709 index = (vid >> 5) & 0x7F;
2710 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2711 vfta |= BIT((vid & 0x1F));
2712 hw->mac.ops.write_vfta(hw, index, vfta);
2713 }
2714
2715 set_bit(vid, adapter->active_vlans);
2716
2717 return 0;
2718}
2719
2720static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
2721 __always_unused __be16 proto, u16 vid)
2722{
2723 struct e1000_adapter *adapter = netdev_priv(netdev);
2724 struct e1000_hw *hw = &adapter->hw;
2725 u32 vfta, index;
2726
2727 if ((adapter->hw.mng_cookie.status &
2728 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2729 (vid == adapter->mng_vlan_id)) {
2730 /* release control to f/w */
2731 e1000e_release_hw_control(adapter);
2732 return 0;
2733 }
2734
2735 /* remove VID from filter table */
2736 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2737 index = (vid >> 5) & 0x7F;
2738 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2739 vfta &= ~BIT((vid & 0x1F));
2740 hw->mac.ops.write_vfta(hw, index, vfta);
2741 }
2742
2743 clear_bit(vid, adapter->active_vlans);
2744
2745 return 0;
2746}
2747
2748/**
2749 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2750 * @adapter: board private structure to initialize
2751 **/
2752static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
2753{
2754 struct net_device *netdev = adapter->netdev;
2755 struct e1000_hw *hw = &adapter->hw;
2756 u32 rctl;
2757
2758 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2759 /* disable VLAN receive filtering */
2760 rctl = er32(RCTL);
2761 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2762 ew32(RCTL, rctl);
2763
2764 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2765 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2766 adapter->mng_vlan_id);
2767 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
2768 }
2769 }
2770}
2771
2772/**
2773 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2774 * @adapter: board private structure to initialize
2775 **/
2776static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2777{
2778 struct e1000_hw *hw = &adapter->hw;
2779 u32 rctl;
2780
2781 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2782 /* enable VLAN receive filtering */
2783 rctl = er32(RCTL);
2784 rctl |= E1000_RCTL_VFE;
2785 rctl &= ~E1000_RCTL_CFIEN;
2786 ew32(RCTL, rctl);
2787 }
2788}
2789
2790/**
2791 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping
2792 * @adapter: board private structure to initialize
2793 **/
2794static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
2795{
2796 struct e1000_hw *hw = &adapter->hw;
2797 u32 ctrl;
2798
2799 /* disable VLAN tag insert/strip */
2800 ctrl = er32(CTRL);
2801 ctrl &= ~E1000_CTRL_VME;
2802 ew32(CTRL, ctrl);
2803}
2804
2805/**
2806 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2807 * @adapter: board private structure to initialize
2808 **/
2809static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2810{
2811 struct e1000_hw *hw = &adapter->hw;
2812 u32 ctrl;
2813
2814 /* enable VLAN tag insert/strip */
2815 ctrl = er32(CTRL);
2816 ctrl |= E1000_CTRL_VME;
2817 ew32(CTRL, ctrl);
2818}
2819
2820static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2821{
2822 struct net_device *netdev = adapter->netdev;
2823 u16 vid = adapter->hw.mng_cookie.vlan_id;
2824 u16 old_vid = adapter->mng_vlan_id;
2825
2826 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2827 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
2828 adapter->mng_vlan_id = vid;
2829 }
2830
2831 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2832 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
2833}
2834
2835static void e1000_restore_vlan(struct e1000_adapter *adapter)
2836{
2837 u16 vid;
2838
2839 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
2840
2841 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2842 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
2843}
2844
2845static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
2846{
2847 struct e1000_hw *hw = &adapter->hw;
2848 u32 manc, manc2h, mdef, i, j;
2849
2850 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2851 return;
2852
2853 manc = er32(MANC);
2854
2855 /* enable receiving management packets to the host. this will probably
2856 * generate destination unreachable messages from the host OS, but
2857 * the packets will be handled on SMBUS
2858 */
2859 manc |= E1000_MANC_EN_MNG2HOST;
2860 manc2h = er32(MANC2H);
2861
2862 switch (hw->mac.type) {
2863 default:
2864 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2865 break;
2866 case e1000_82574:
2867 case e1000_82583:
2868 /* Check if IPMI pass-through decision filter already exists;
2869 * if so, enable it.
2870 */
2871 for (i = 0, j = 0; i < 8; i++) {
2872 mdef = er32(MDEF(i));
2873
2874 /* Ignore filters with anything other than IPMI ports */
2875 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2876 continue;
2877
2878 /* Enable this decision filter in MANC2H */
2879 if (mdef)
2880 manc2h |= BIT(i);
2881
2882 j |= mdef;
2883 }
2884
2885 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2886 break;
2887
2888 /* Create new decision filter in an empty filter */
2889 for (i = 0, j = 0; i < 8; i++)
2890 if (er32(MDEF(i)) == 0) {
2891 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2892 E1000_MDEF_PORT_664));
2893 manc2h |= BIT(1);
2894 j++;
2895 break;
2896 }
2897
2898 if (!j)
2899 e_warn("Unable to create IPMI pass-through filter\n");
2900 break;
2901 }
2902
2903 ew32(MANC2H, manc2h);
2904 ew32(MANC, manc);
2905}
2906
2907/**
2908 * e1000_configure_tx - Configure Transmit Unit after Reset
2909 * @adapter: board private structure
2910 *
2911 * Configure the Tx unit of the MAC after a reset.
2912 **/
2913static void e1000_configure_tx(struct e1000_adapter *adapter)
2914{
2915 struct e1000_hw *hw = &adapter->hw;
2916 struct e1000_ring *tx_ring = adapter->tx_ring;
2917 u64 tdba;
2918 u32 tdlen, tctl, tarc;
2919
2920 /* Setup the HW Tx Head and Tail descriptor pointers */
2921 tdba = tx_ring->dma;
2922 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
2923 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2924 ew32(TDBAH(0), (tdba >> 32));
2925 ew32(TDLEN(0), tdlen);
2926 ew32(TDH(0), 0);
2927 ew32(TDT(0), 0);
2928 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2929 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
2930
2931 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2932 e1000e_update_tdt_wa(tx_ring, 0);
2933
2934 /* Set the Tx Interrupt Delay register */
2935 ew32(TIDV, adapter->tx_int_delay);
2936 /* Tx irq moderation */
2937 ew32(TADV, adapter->tx_abs_int_delay);
2938
2939 if (adapter->flags2 & FLAG2_DMA_BURST) {
2940 u32 txdctl = er32(TXDCTL(0));
2941
2942 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2943 E1000_TXDCTL_WTHRESH);
2944 /* set up some performance related parameters to encourage the
2945 * hardware to use the bus more efficiently in bursts, depends
2946 * on the tx_int_delay to be enabled,
2947 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2948 * hthresh = 1 ==> prefetch when one or more available
2949 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2950 * BEWARE: this seems to work but should be considered first if
2951 * there are Tx hangs or other Tx related bugs
2952 */
2953 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2954 ew32(TXDCTL(0), txdctl);
2955 }
2956 /* erratum work around: set txdctl the same for both queues */
2957 ew32(TXDCTL(1), er32(TXDCTL(0)));
2958
2959 /* Program the Transmit Control Register */
2960 tctl = er32(TCTL);
2961 tctl &= ~E1000_TCTL_CT;
2962 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2963 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2964
2965 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
2966 tarc = er32(TARC(0));
2967 /* set the speed mode bit, we'll clear it if we're not at
2968 * gigabit link later
2969 */
2970#define SPEED_MODE_BIT BIT(21)
2971 tarc |= SPEED_MODE_BIT;
2972 ew32(TARC(0), tarc);
2973 }
2974
2975 /* errata: program both queues to unweighted RR */
2976 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
2977 tarc = er32(TARC(0));
2978 tarc |= 1;
2979 ew32(TARC(0), tarc);
2980 tarc = er32(TARC(1));
2981 tarc |= 1;
2982 ew32(TARC(1), tarc);
2983 }
2984
2985 /* Setup Transmit Descriptor Settings for eop descriptor */
2986 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2987
2988 /* only set IDE if we are delaying interrupts using the timers */
2989 if (adapter->tx_int_delay)
2990 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2991
2992 /* enable Report Status bit */
2993 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2994
2995 ew32(TCTL, tctl);
2996
2997 hw->mac.ops.config_collision_dist(hw);
2998
2999 /* SPT and KBL Si errata workaround to avoid data corruption */
3000 if (hw->mac.type == e1000_pch_spt) {
3001 u32 reg_val;
3002
3003 reg_val = er32(IOSFPC);
3004 reg_val |= E1000_RCTL_RDMTS_HEX;
3005 ew32(IOSFPC, reg_val);
3006
3007 reg_val = er32(TARC(0));
3008 /* SPT and KBL Si errata workaround to avoid Tx hang.
3009 * Dropping the number of outstanding requests from
3010 * 3 to 2 in order to avoid a buffer overrun.
3011 */
3012 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3013 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ;
3014 ew32(TARC(0), reg_val);
3015 }
3016}
3017
3018#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3019 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3020
3021/**
3022 * e1000_setup_rctl - configure the receive control registers
3023 * @adapter: Board private structure
3024 **/
3025static void e1000_setup_rctl(struct e1000_adapter *adapter)
3026{
3027 struct e1000_hw *hw = &adapter->hw;
3028 u32 rctl, rfctl;
3029 u32 pages = 0;
3030
3031 /* Workaround Si errata on PCHx - configure jumbo frame flow.
3032 * If jumbo frames not set, program related MAC/PHY registers
3033 * to h/w defaults
3034 */
3035 if (hw->mac.type >= e1000_pch2lan) {
3036 s32 ret_val;
3037
3038 if (adapter->netdev->mtu > ETH_DATA_LEN)
3039 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
3040 else
3041 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
3042
3043 if (ret_val)
3044 e_dbg("failed to enable|disable jumbo frame workaround mode\n");
3045 }
3046
3047 /* Program MC offset vector base */
3048 rctl = er32(RCTL);
3049 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3050 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3051 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3052 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3053
3054 /* Do not Store bad packets */
3055 rctl &= ~E1000_RCTL_SBP;
3056
3057 /* Enable Long Packet receive */
3058 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3059 rctl &= ~E1000_RCTL_LPE;
3060 else
3061 rctl |= E1000_RCTL_LPE;
3062
3063 /* Some systems expect that the CRC is included in SMBUS traffic. The
3064 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3065 * host memory when this is enabled
3066 */
3067 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3068 rctl |= E1000_RCTL_SECRC;
3069
3070 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3071 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3072 u16 phy_data;
3073
3074 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3075 phy_data &= 0xfff8;
3076 phy_data |= BIT(2);
3077 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3078
3079 e1e_rphy(hw, 22, &phy_data);
3080 phy_data &= 0x0fff;
3081 phy_data |= BIT(14);
3082 e1e_wphy(hw, 0x10, 0x2823);
3083 e1e_wphy(hw, 0x11, 0x0003);
3084 e1e_wphy(hw, 22, phy_data);
3085 }
3086
3087 /* Setup buffer sizes */
3088 rctl &= ~E1000_RCTL_SZ_4096;
3089 rctl |= E1000_RCTL_BSEX;
3090 switch (adapter->rx_buffer_len) {
3091 case 2048:
3092 default:
3093 rctl |= E1000_RCTL_SZ_2048;
3094 rctl &= ~E1000_RCTL_BSEX;
3095 break;
3096 case 4096:
3097 rctl |= E1000_RCTL_SZ_4096;
3098 break;
3099 case 8192:
3100 rctl |= E1000_RCTL_SZ_8192;
3101 break;
3102 case 16384:
3103 rctl |= E1000_RCTL_SZ_16384;
3104 break;
3105 }
3106
3107 /* Enable Extended Status in all Receive Descriptors */
3108 rfctl = er32(RFCTL);
3109 rfctl |= E1000_RFCTL_EXTEN;
3110 ew32(RFCTL, rfctl);
3111
3112 /* 82571 and greater support packet-split where the protocol
3113 * header is placed in skb->data and the packet data is
3114 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3115 * In the case of a non-split, skb->data is linearly filled,
3116 * followed by the page buffers. Therefore, skb->data is
3117 * sized to hold the largest protocol header.
3118 *
3119 * allocations using alloc_page take too long for regular MTU
3120 * so only enable packet split for jumbo frames
3121 *
3122 * Using pages when the page size is greater than 16k wastes
3123 * a lot of memory, since we allocate 3 pages at all times
3124 * per packet.
3125 */
3126 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
3127 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
3128 adapter->rx_ps_pages = pages;
3129 else
3130 adapter->rx_ps_pages = 0;
3131
3132 if (adapter->rx_ps_pages) {
3133 u32 psrctl = 0;
3134
3135 /* Enable Packet split descriptors */
3136 rctl |= E1000_RCTL_DTYP_PS;
3137
3138 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
3139
3140 switch (adapter->rx_ps_pages) {
3141 case 3:
3142 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3143 fallthrough;
3144 case 2:
3145 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3146 fallthrough;
3147 case 1:
3148 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
3149 break;
3150 }
3151
3152 ew32(PSRCTL, psrctl);
3153 }
3154
3155 /* This is useful for sniffing bad packets. */
3156 if (adapter->netdev->features & NETIF_F_RXALL) {
3157 /* UPE and MPE will be handled by normal PROMISC logic
3158 * in e1000e_set_rx_mode
3159 */
3160 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3161 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3162 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3163
3164 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3165 E1000_RCTL_DPF | /* Allow filtered pause */
3166 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3167 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3168 * and that breaks VLANs.
3169 */
3170 }
3171
3172 ew32(RCTL, rctl);
3173 /* just started the receive unit, no need to restart */
3174 adapter->flags &= ~FLAG_RESTART_NOW;
3175}
3176
3177/**
3178 * e1000_configure_rx - Configure Receive Unit after Reset
3179 * @adapter: board private structure
3180 *
3181 * Configure the Rx unit of the MAC after a reset.
3182 **/
3183static void e1000_configure_rx(struct e1000_adapter *adapter)
3184{
3185 struct e1000_hw *hw = &adapter->hw;
3186 struct e1000_ring *rx_ring = adapter->rx_ring;
3187 u64 rdba;
3188 u32 rdlen, rctl, rxcsum, ctrl_ext;
3189
3190 if (adapter->rx_ps_pages) {
3191 /* this is a 32 byte descriptor */
3192 rdlen = rx_ring->count *
3193 sizeof(union e1000_rx_desc_packet_split);
3194 adapter->clean_rx = e1000_clean_rx_irq_ps;
3195 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
3196 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
3197 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3198 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3199 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
3200 } else {
3201 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3202 adapter->clean_rx = e1000_clean_rx_irq;
3203 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3204 }
3205
3206 /* disable receives while setting up the descriptors */
3207 rctl = er32(RCTL);
3208 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3209 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3210 e1e_flush();
3211 usleep_range(10000, 11000);
3212
3213 if (adapter->flags2 & FLAG2_DMA_BURST) {
3214 /* set the writeback threshold (only takes effect if the RDTR
3215 * is set). set GRAN=1 and write back up to 0x4 worth, and
3216 * enable prefetching of 0x20 Rx descriptors
3217 * granularity = 01
3218 * wthresh = 04,
3219 * hthresh = 04,
3220 * pthresh = 0x20
3221 */
3222 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3223 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3224 }
3225
3226 /* set the Receive Delay Timer Register */
3227 ew32(RDTR, adapter->rx_int_delay);
3228
3229 /* irq moderation */
3230 ew32(RADV, adapter->rx_abs_int_delay);
3231 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
3232 e1000e_write_itr(adapter, adapter->itr);
3233
3234 ctrl_ext = er32(CTRL_EXT);
3235 /* Auto-Mask interrupts upon ICR access */
3236 ctrl_ext |= E1000_CTRL_EXT_IAME;
3237 ew32(IAM, 0xffffffff);
3238 ew32(CTRL_EXT, ctrl_ext);
3239 e1e_flush();
3240
3241 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3242 * the Base and Length of the Rx Descriptor Ring
3243 */
3244 rdba = rx_ring->dma;
3245 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3246 ew32(RDBAH(0), (rdba >> 32));
3247 ew32(RDLEN(0), rdlen);
3248 ew32(RDH(0), 0);
3249 ew32(RDT(0), 0);
3250 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3251 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
3252
3253 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
3254 e1000e_update_rdt_wa(rx_ring, 0);
3255
3256 /* Enable Receive Checksum Offload for TCP and UDP */
3257 rxcsum = er32(RXCSUM);
3258 if (adapter->netdev->features & NETIF_F_RXCSUM)
3259 rxcsum |= E1000_RXCSUM_TUOFL;
3260 else
3261 rxcsum &= ~E1000_RXCSUM_TUOFL;
3262 ew32(RXCSUM, rxcsum);
3263
3264 /* With jumbo frames, excessive C-state transition latencies result
3265 * in dropped transactions.
3266 */
3267 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3268 u32 lat =
3269 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3270 adapter->max_frame_size) * 8 / 1000;
3271
3272 if (adapter->flags & FLAG_IS_ICH) {
3273 u32 rxdctl = er32(RXDCTL(0));
3274
3275 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8));
3276 }
3277
3278 dev_info(&adapter->pdev->dev,
3279 "Some CPU C-states have been disabled in order to enable jumbo frames\n");
3280 cpu_latency_qos_update_request(&adapter->pm_qos_req, lat);
3281 } else {
3282 cpu_latency_qos_update_request(&adapter->pm_qos_req,
3283 PM_QOS_DEFAULT_VALUE);
3284 }
3285
3286 /* Enable Receives */
3287 ew32(RCTL, rctl);
3288}
3289
3290/**
3291 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3292 * @netdev: network interface device structure
3293 *
3294 * Writes multicast address list to the MTA hash table.
3295 * Returns: -ENOMEM on failure
3296 * 0 on no addresses written
3297 * X on writing X addresses to MTA
3298 */
3299static int e1000e_write_mc_addr_list(struct net_device *netdev)
3300{
3301 struct e1000_adapter *adapter = netdev_priv(netdev);
3302 struct e1000_hw *hw = &adapter->hw;
3303 struct netdev_hw_addr *ha;
3304 u8 *mta_list;
3305 int i;
3306
3307 if (netdev_mc_empty(netdev)) {
3308 /* nothing to program, so clear mc list */
3309 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3310 return 0;
3311 }
3312
3313 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC);
3314 if (!mta_list)
3315 return -ENOMEM;
3316
3317 /* update_mc_addr_list expects a packed array of only addresses. */
3318 i = 0;
3319 netdev_for_each_mc_addr(ha, netdev)
3320 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3321
3322 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3323 kfree(mta_list);
3324
3325 return netdev_mc_count(netdev);
3326}
3327
3328/**
3329 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3330 * @netdev: network interface device structure
3331 *
3332 * Writes unicast address list to the RAR table.
3333 * Returns: -ENOMEM on failure/insufficient address space
3334 * 0 on no addresses written
3335 * X on writing X addresses to the RAR table
3336 **/
3337static int e1000e_write_uc_addr_list(struct net_device *netdev)
3338{
3339 struct e1000_adapter *adapter = netdev_priv(netdev);
3340 struct e1000_hw *hw = &adapter->hw;
3341 unsigned int rar_entries;
3342 int count = 0;
3343
3344 rar_entries = hw->mac.ops.rar_get_count(hw);
3345
3346 /* save a rar entry for our hardware address */
3347 rar_entries--;
3348
3349 /* save a rar entry for the LAA workaround */
3350 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3351 rar_entries--;
3352
3353 /* return ENOMEM indicating insufficient memory for addresses */
3354 if (netdev_uc_count(netdev) > rar_entries)
3355 return -ENOMEM;
3356
3357 if (!netdev_uc_empty(netdev) && rar_entries) {
3358 struct netdev_hw_addr *ha;
3359
3360 /* write the addresses in reverse order to avoid write
3361 * combining
3362 */
3363 netdev_for_each_uc_addr(ha, netdev) {
3364 int ret_val;
3365
3366 if (!rar_entries)
3367 break;
3368 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
3369 if (ret_val < 0)
3370 return -ENOMEM;
3371 count++;
3372 }
3373 }
3374
3375 /* zero out the remaining RAR entries not used above */
3376 for (; rar_entries > 0; rar_entries--) {
3377 ew32(RAH(rar_entries), 0);
3378 ew32(RAL(rar_entries), 0);
3379 }
3380 e1e_flush();
3381
3382 return count;
3383}
3384
3385/**
3386 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3387 * @netdev: network interface device structure
3388 *
3389 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3390 * address list or the network interface flags are updated. This routine is
3391 * responsible for configuring the hardware for proper unicast, multicast,
3392 * promiscuous mode, and all-multi behavior.
3393 **/
3394static void e1000e_set_rx_mode(struct net_device *netdev)
3395{
3396 struct e1000_adapter *adapter = netdev_priv(netdev);
3397 struct e1000_hw *hw = &adapter->hw;
3398 u32 rctl;
3399
3400 if (pm_runtime_suspended(netdev->dev.parent))
3401 return;
3402
3403 /* Check for Promiscuous and All Multicast modes */
3404 rctl = er32(RCTL);
3405
3406 /* clear the affected bits */
3407 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3408
3409 if (netdev->flags & IFF_PROMISC) {
3410 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3411 /* Do not hardware filter VLANs in promisc mode */
3412 e1000e_vlan_filter_disable(adapter);
3413 } else {
3414 int count;
3415
3416 if (netdev->flags & IFF_ALLMULTI) {
3417 rctl |= E1000_RCTL_MPE;
3418 } else {
3419 /* Write addresses to the MTA, if the attempt fails
3420 * then we should just turn on promiscuous mode so
3421 * that we can at least receive multicast traffic
3422 */
3423 count = e1000e_write_mc_addr_list(netdev);
3424 if (count < 0)
3425 rctl |= E1000_RCTL_MPE;
3426 }
3427 e1000e_vlan_filter_enable(adapter);
3428 /* Write addresses to available RAR registers, if there is not
3429 * sufficient space to store all the addresses then enable
3430 * unicast promiscuous mode
3431 */
3432 count = e1000e_write_uc_addr_list(netdev);
3433 if (count < 0)
3434 rctl |= E1000_RCTL_UPE;
3435 }
3436
3437 ew32(RCTL, rctl);
3438
3439 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3440 e1000e_vlan_strip_enable(adapter);
3441 else
3442 e1000e_vlan_strip_disable(adapter);
3443}
3444
3445static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3446{
3447 struct e1000_hw *hw = &adapter->hw;
3448 u32 mrqc, rxcsum;
3449 u32 rss_key[10];
3450 int i;
3451
3452 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3453 for (i = 0; i < 10; i++)
3454 ew32(RSSRK(i), rss_key[i]);
3455
3456 /* Direct all traffic to queue 0 */
3457 for (i = 0; i < 32; i++)
3458 ew32(RETA(i), 0);
3459
3460 /* Disable raw packet checksumming so that RSS hash is placed in
3461 * descriptor on writeback.
3462 */
3463 rxcsum = er32(RXCSUM);
3464 rxcsum |= E1000_RXCSUM_PCSD;
3465
3466 ew32(RXCSUM, rxcsum);
3467
3468 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3469 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3470 E1000_MRQC_RSS_FIELD_IPV6 |
3471 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3472 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3473
3474 ew32(MRQC, mrqc);
3475}
3476
3477/**
3478 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3479 * @adapter: board private structure
3480 * @timinca: pointer to returned time increment attributes
3481 *
3482 * Get attributes for incrementing the System Time Register SYSTIML/H at
3483 * the default base frequency, and set the cyclecounter shift value.
3484 **/
3485s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
3486{
3487 struct e1000_hw *hw = &adapter->hw;
3488 u32 incvalue, incperiod, shift;
3489
3490 /* Make sure clock is enabled on I217/I218/I219 before checking
3491 * the frequency
3492 */
3493 if ((hw->mac.type >= e1000_pch_lpt) &&
3494 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3495 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3496 u32 fextnvm7 = er32(FEXTNVM7);
3497
3498 if (!(fextnvm7 & BIT(0))) {
3499 ew32(FEXTNVM7, fextnvm7 | BIT(0));
3500 e1e_flush();
3501 }
3502 }
3503
3504 switch (hw->mac.type) {
3505 case e1000_pch2lan:
3506 /* Stable 96MHz frequency */
3507 incperiod = INCPERIOD_96MHZ;
3508 incvalue = INCVALUE_96MHZ;
3509 shift = INCVALUE_SHIFT_96MHZ;
3510 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3511 break;
3512 case e1000_pch_lpt:
3513 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3514 /* Stable 96MHz frequency */
3515 incperiod = INCPERIOD_96MHZ;
3516 incvalue = INCVALUE_96MHZ;
3517 shift = INCVALUE_SHIFT_96MHZ;
3518 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3519 } else {
3520 /* Stable 25MHz frequency */
3521 incperiod = INCPERIOD_25MHZ;
3522 incvalue = INCVALUE_25MHZ;
3523 shift = INCVALUE_SHIFT_25MHZ;
3524 adapter->cc.shift = shift;
3525 }
3526 break;
3527 case e1000_pch_spt:
3528 /* Stable 24MHz frequency */
3529 incperiod = INCPERIOD_24MHZ;
3530 incvalue = INCVALUE_24MHZ;
3531 shift = INCVALUE_SHIFT_24MHZ;
3532 adapter->cc.shift = shift;
3533 break;
3534 case e1000_pch_cnp:
3535 case e1000_pch_tgp:
3536 case e1000_pch_adp:
3537 case e1000_pch_mtp:
3538 case e1000_pch_lnp:
3539 case e1000_pch_ptp:
3540 case e1000_pch_nvp:
3541 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3542 /* Stable 24MHz frequency */
3543 incperiod = INCPERIOD_24MHZ;
3544 incvalue = INCVALUE_24MHZ;
3545 shift = INCVALUE_SHIFT_24MHZ;
3546 adapter->cc.shift = shift;
3547 } else {
3548 /* Stable 38400KHz frequency */
3549 incperiod = INCPERIOD_38400KHZ;
3550 incvalue = INCVALUE_38400KHZ;
3551 shift = INCVALUE_SHIFT_38400KHZ;
3552 adapter->cc.shift = shift;
3553 }
3554 break;
3555 case e1000_82574:
3556 case e1000_82583:
3557 /* Stable 25MHz frequency */
3558 incperiod = INCPERIOD_25MHZ;
3559 incvalue = INCVALUE_25MHZ;
3560 shift = INCVALUE_SHIFT_25MHZ;
3561 adapter->cc.shift = shift;
3562 break;
3563 default:
3564 return -EINVAL;
3565 }
3566
3567 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3568 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3569
3570 return 0;
3571}
3572
3573/**
3574 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3575 * @adapter: board private structure
3576 * @config: timestamp configuration
3577 *
3578 * Outgoing time stamping can be enabled and disabled. Play nice and
3579 * disable it when requested, although it shouldn't cause any overhead
3580 * when no packet needs it. At most one packet in the queue may be
3581 * marked for time stamping, otherwise it would be impossible to tell
3582 * for sure to which packet the hardware time stamp belongs.
3583 *
3584 * Incoming time stamping has to be configured via the hardware filters.
3585 * Not all combinations are supported, in particular event type has to be
3586 * specified. Matching the kind of event packet is not supported, with the
3587 * exception of "all V2 events regardless of level 2 or 4".
3588 **/
3589static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3590 struct hwtstamp_config *config)
3591{
3592 struct e1000_hw *hw = &adapter->hw;
3593 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3594 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
3595 u32 rxmtrl = 0;
3596 u16 rxudp = 0;
3597 bool is_l4 = false;
3598 bool is_l2 = false;
3599 u32 regval;
3600
3601 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3602 return -EINVAL;
3603
3604 switch (config->tx_type) {
3605 case HWTSTAMP_TX_OFF:
3606 tsync_tx_ctl = 0;
3607 break;
3608 case HWTSTAMP_TX_ON:
3609 break;
3610 default:
3611 return -ERANGE;
3612 }
3613
3614 switch (config->rx_filter) {
3615 case HWTSTAMP_FILTER_NONE:
3616 tsync_rx_ctl = 0;
3617 break;
3618 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3619 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3620 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3621 is_l4 = true;
3622 break;
3623 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3624 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3625 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3626 is_l4 = true;
3627 break;
3628 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3629 /* Also time stamps V2 L2 Path Delay Request/Response */
3630 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3631 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3632 is_l2 = true;
3633 break;
3634 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3635 /* Also time stamps V2 L2 Path Delay Request/Response. */
3636 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3637 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3638 is_l2 = true;
3639 break;
3640 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3641 /* Hardware cannot filter just V2 L4 Sync messages */
3642 fallthrough;
3643 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3644 /* Also time stamps V2 Path Delay Request/Response. */
3645 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3646 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3647 is_l2 = true;
3648 is_l4 = true;
3649 break;
3650 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3651 /* Hardware cannot filter just V2 L4 Delay Request messages */
3652 fallthrough;
3653 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3654 /* Also time stamps V2 Path Delay Request/Response. */
3655 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3656 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3657 is_l2 = true;
3658 is_l4 = true;
3659 break;
3660 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3661 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3662 /* Hardware cannot filter just V2 L4 or L2 Event messages */
3663 fallthrough;
3664 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3665 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3666 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3667 is_l2 = true;
3668 is_l4 = true;
3669 break;
3670 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3671 /* For V1, the hardware can only filter Sync messages or
3672 * Delay Request messages but not both so fall-through to
3673 * time stamp all packets.
3674 */
3675 fallthrough;
3676 case HWTSTAMP_FILTER_NTP_ALL:
3677 case HWTSTAMP_FILTER_ALL:
3678 is_l2 = true;
3679 is_l4 = true;
3680 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3681 config->rx_filter = HWTSTAMP_FILTER_ALL;
3682 break;
3683 default:
3684 return -ERANGE;
3685 }
3686
3687 adapter->hwtstamp_config = *config;
3688
3689 /* enable/disable Tx h/w time stamping */
3690 regval = er32(TSYNCTXCTL);
3691 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3692 regval |= tsync_tx_ctl;
3693 ew32(TSYNCTXCTL, regval);
3694 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3695 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3696 e_err("Timesync Tx Control register not set as expected\n");
3697 return -EAGAIN;
3698 }
3699
3700 /* enable/disable Rx h/w time stamping */
3701 regval = er32(TSYNCRXCTL);
3702 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3703 regval |= tsync_rx_ctl;
3704 ew32(TSYNCRXCTL, regval);
3705 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3706 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3707 (regval & (E1000_TSYNCRXCTL_ENABLED |
3708 E1000_TSYNCRXCTL_TYPE_MASK))) {
3709 e_err("Timesync Rx Control register not set as expected\n");
3710 return -EAGAIN;
3711 }
3712
3713 /* L2: define ethertype filter for time stamped packets */
3714 if (is_l2)
3715 rxmtrl |= ETH_P_1588;
3716
3717 /* define which PTP packets get time stamped */
3718 ew32(RXMTRL, rxmtrl);
3719
3720 /* Filter by destination port */
3721 if (is_l4) {
3722 rxudp = PTP_EV_PORT;
3723 cpu_to_be16s(&rxudp);
3724 }
3725 ew32(RXUDP, rxudp);
3726
3727 e1e_flush();
3728
3729 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3730 er32(RXSTMPH);
3731 er32(TXSTMPH);
3732
3733 return 0;
3734}
3735
3736/**
3737 * e1000_configure - configure the hardware for Rx and Tx
3738 * @adapter: private board structure
3739 **/
3740static void e1000_configure(struct e1000_adapter *adapter)
3741{
3742 struct e1000_ring *rx_ring = adapter->rx_ring;
3743
3744 e1000e_set_rx_mode(adapter->netdev);
3745
3746 e1000_restore_vlan(adapter);
3747 e1000_init_manageability_pt(adapter);
3748
3749 e1000_configure_tx(adapter);
3750
3751 if (adapter->netdev->features & NETIF_F_RXHASH)
3752 e1000e_setup_rss_hash(adapter);
3753 e1000_setup_rctl(adapter);
3754 e1000_configure_rx(adapter);
3755 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
3756}
3757
3758/**
3759 * e1000e_power_up_phy - restore link in case the phy was powered down
3760 * @adapter: address of board private structure
3761 *
3762 * The phy may be powered down to save power and turn off link when the
3763 * driver is unloaded and wake on lan is not enabled (among others)
3764 * *** this routine MUST be followed by a call to e1000e_reset ***
3765 **/
3766void e1000e_power_up_phy(struct e1000_adapter *adapter)
3767{
3768 if (adapter->hw.phy.ops.power_up)
3769 adapter->hw.phy.ops.power_up(&adapter->hw);
3770
3771 adapter->hw.mac.ops.setup_link(&adapter->hw);
3772}
3773
3774/**
3775 * e1000_power_down_phy - Power down the PHY
3776 * @adapter: board private structure
3777 *
3778 * Power down the PHY so no link is implied when interface is down.
3779 * The PHY cannot be powered down if management or WoL is active.
3780 */
3781static void e1000_power_down_phy(struct e1000_adapter *adapter)
3782{
3783 if (adapter->hw.phy.ops.power_down)
3784 adapter->hw.phy.ops.power_down(&adapter->hw);
3785}
3786
3787/**
3788 * e1000_flush_tx_ring - remove all descriptors from the tx_ring
3789 * @adapter: board private structure
3790 *
3791 * We want to clear all pending descriptors from the TX ring.
3792 * zeroing happens when the HW reads the regs. We assign the ring itself as
3793 * the data of the next descriptor. We don't care about the data we are about
3794 * to reset the HW.
3795 */
3796static void e1000_flush_tx_ring(struct e1000_adapter *adapter)
3797{
3798 struct e1000_hw *hw = &adapter->hw;
3799 struct e1000_ring *tx_ring = adapter->tx_ring;
3800 struct e1000_tx_desc *tx_desc = NULL;
3801 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
3802 u16 size = 512;
3803
3804 tctl = er32(TCTL);
3805 ew32(TCTL, tctl | E1000_TCTL_EN);
3806 tdt = er32(TDT(0));
3807 BUG_ON(tdt != tx_ring->next_to_use);
3808 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use);
3809 tx_desc->buffer_addr = cpu_to_le64(tx_ring->dma);
3810
3811 tx_desc->lower.data = cpu_to_le32(txd_lower | size);
3812 tx_desc->upper.data = 0;
3813 /* flush descriptors to memory before notifying the HW */
3814 wmb();
3815 tx_ring->next_to_use++;
3816 if (tx_ring->next_to_use == tx_ring->count)
3817 tx_ring->next_to_use = 0;
3818 ew32(TDT(0), tx_ring->next_to_use);
3819 usleep_range(200, 250);
3820}
3821
3822/**
3823 * e1000_flush_rx_ring - remove all descriptors from the rx_ring
3824 * @adapter: board private structure
3825 *
3826 * Mark all descriptors in the RX ring as consumed and disable the rx ring
3827 */
3828static void e1000_flush_rx_ring(struct e1000_adapter *adapter)
3829{
3830 u32 rctl, rxdctl;
3831 struct e1000_hw *hw = &adapter->hw;
3832
3833 rctl = er32(RCTL);
3834 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3835 e1e_flush();
3836 usleep_range(100, 150);
3837
3838 rxdctl = er32(RXDCTL(0));
3839 /* zero the lower 14 bits (prefetch and host thresholds) */
3840 rxdctl &= 0xffffc000;
3841
3842 /* update thresholds: prefetch threshold to 31, host threshold to 1
3843 * and make sure the granularity is "descriptors" and not "cache lines"
3844 */
3845 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC);
3846
3847 ew32(RXDCTL(0), rxdctl);
3848 /* momentarily enable the RX ring for the changes to take effect */
3849 ew32(RCTL, rctl | E1000_RCTL_EN);
3850 e1e_flush();
3851 usleep_range(100, 150);
3852 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3853}
3854
3855/**
3856 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings
3857 * @adapter: board private structure
3858 *
3859 * In i219, the descriptor rings must be emptied before resetting the HW
3860 * or before changing the device state to D3 during runtime (runtime PM).
3861 *
3862 * Failure to do this will cause the HW to enter a unit hang state which can
3863 * only be released by PCI reset on the device
3864 *
3865 */
3866
3867static void e1000_flush_desc_rings(struct e1000_adapter *adapter)
3868{
3869 u16 hang_state;
3870 u32 fext_nvm11, tdlen;
3871 struct e1000_hw *hw = &adapter->hw;
3872
3873 /* First, disable MULR fix in FEXTNVM11 */
3874 fext_nvm11 = er32(FEXTNVM11);
3875 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
3876 ew32(FEXTNVM11, fext_nvm11);
3877 /* do nothing if we're not in faulty state, or if the queue is empty */
3878 tdlen = er32(TDLEN(0));
3879 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3880 &hang_state);
3881 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
3882 return;
3883 e1000_flush_tx_ring(adapter);
3884 /* recheck, maybe the fault is caused by the rx ring */
3885 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3886 &hang_state);
3887 if (hang_state & FLUSH_DESC_REQUIRED)
3888 e1000_flush_rx_ring(adapter);
3889}
3890
3891/**
3892 * e1000e_systim_reset - reset the timesync registers after a hardware reset
3893 * @adapter: board private structure
3894 *
3895 * When the MAC is reset, all hardware bits for timesync will be reset to the
3896 * default values. This function will restore the settings last in place.
3897 * Since the clock SYSTIME registers are reset, we will simply restore the
3898 * cyclecounter to the kernel real clock time.
3899 **/
3900static void e1000e_systim_reset(struct e1000_adapter *adapter)
3901{
3902 struct ptp_clock_info *info = &adapter->ptp_clock_info;
3903 struct e1000_hw *hw = &adapter->hw;
3904 unsigned long flags;
3905 u32 timinca;
3906 s32 ret_val;
3907
3908 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3909 return;
3910
3911 if (info->adjfine) {
3912 /* restore the previous ptp frequency delta */
3913 ret_val = info->adjfine(info, adapter->ptp_delta);
3914 } else {
3915 /* set the default base frequency if no adjustment possible */
3916 ret_val = e1000e_get_base_timinca(adapter, &timinca);
3917 if (!ret_val)
3918 ew32(TIMINCA, timinca);
3919 }
3920
3921 if (ret_val) {
3922 dev_warn(&adapter->pdev->dev,
3923 "Failed to restore TIMINCA clock rate delta: %d\n",
3924 ret_val);
3925 return;
3926 }
3927
3928 /* reset the systim ns time counter */
3929 spin_lock_irqsave(&adapter->systim_lock, flags);
3930 timecounter_init(&adapter->tc, &adapter->cc,
3931 ktime_to_ns(ktime_get_real()));
3932 spin_unlock_irqrestore(&adapter->systim_lock, flags);
3933
3934 /* restore the previous hwtstamp configuration settings */
3935 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config);
3936}
3937
3938/**
3939 * e1000e_reset - bring the hardware into a known good state
3940 * @adapter: board private structure
3941 *
3942 * This function boots the hardware and enables some settings that
3943 * require a configuration cycle of the hardware - those cannot be
3944 * set/changed during runtime. After reset the device needs to be
3945 * properly configured for Rx, Tx etc.
3946 */
3947void e1000e_reset(struct e1000_adapter *adapter)
3948{
3949 struct e1000_mac_info *mac = &adapter->hw.mac;
3950 struct e1000_fc_info *fc = &adapter->hw.fc;
3951 struct e1000_hw *hw = &adapter->hw;
3952 u32 tx_space, min_tx_space, min_rx_space;
3953 u32 pba = adapter->pba;
3954 u16 hwm;
3955
3956 /* reset Packet Buffer Allocation to default */
3957 ew32(PBA, pba);
3958
3959 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) {
3960 /* To maintain wire speed transmits, the Tx FIFO should be
3961 * large enough to accommodate two full transmit packets,
3962 * rounded up to the next 1KB and expressed in KB. Likewise,
3963 * the Rx FIFO should be large enough to accommodate at least
3964 * one full receive packet and is similarly rounded up and
3965 * expressed in KB.
3966 */
3967 pba = er32(PBA);
3968 /* upper 16 bits has Tx packet buffer allocation size in KB */
3969 tx_space = pba >> 16;
3970 /* lower 16 bits has Rx packet buffer allocation size in KB */
3971 pba &= 0xffff;
3972 /* the Tx fifo also stores 16 bytes of information about the Tx
3973 * but don't include ethernet FCS because hardware appends it
3974 */
3975 min_tx_space = (adapter->max_frame_size +
3976 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
3977 min_tx_space = ALIGN(min_tx_space, 1024);
3978 min_tx_space >>= 10;
3979 /* software strips receive CRC, so leave room for it */
3980 min_rx_space = adapter->max_frame_size;
3981 min_rx_space = ALIGN(min_rx_space, 1024);
3982 min_rx_space >>= 10;
3983
3984 /* If current Tx allocation is less than the min Tx FIFO size,
3985 * and the min Tx FIFO size is less than the current Rx FIFO
3986 * allocation, take space away from current Rx allocation
3987 */
3988 if ((tx_space < min_tx_space) &&
3989 ((min_tx_space - tx_space) < pba)) {
3990 pba -= min_tx_space - tx_space;
3991
3992 /* if short on Rx space, Rx wins and must trump Tx
3993 * adjustment
3994 */
3995 if (pba < min_rx_space)
3996 pba = min_rx_space;
3997 }
3998
3999 ew32(PBA, pba);
4000 }
4001
4002 /* flow control settings
4003 *
4004 * The high water mark must be low enough to fit one full frame
4005 * (or the size used for early receive) above it in the Rx FIFO.
4006 * Set it to the lower of:
4007 * - 90% of the Rx FIFO size, and
4008 * - the full Rx FIFO size minus one full frame
4009 */
4010 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
4011 fc->pause_time = 0xFFFF;
4012 else
4013 fc->pause_time = E1000_FC_PAUSE_TIME;
4014 fc->send_xon = true;
4015 fc->current_mode = fc->requested_mode;
4016
4017 switch (hw->mac.type) {
4018 case e1000_ich9lan:
4019 case e1000_ich10lan:
4020 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4021 pba = 14;
4022 ew32(PBA, pba);
4023 fc->high_water = 0x2800;
4024 fc->low_water = fc->high_water - 8;
4025 break;
4026 }
4027 fallthrough;
4028 default:
4029 hwm = min(((pba << 10) * 9 / 10),
4030 ((pba << 10) - adapter->max_frame_size));
4031
4032 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
4033 fc->low_water = fc->high_water - 8;
4034 break;
4035 case e1000_pchlan:
4036 /* Workaround PCH LOM adapter hangs with certain network
4037 * loads. If hangs persist, try disabling Tx flow control.
4038 */
4039 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4040 fc->high_water = 0x3500;
4041 fc->low_water = 0x1500;
4042 } else {
4043 fc->high_water = 0x5000;
4044 fc->low_water = 0x3000;
4045 }
4046 fc->refresh_time = 0x1000;
4047 break;
4048 case e1000_pch2lan:
4049 case e1000_pch_lpt:
4050 case e1000_pch_spt:
4051 case e1000_pch_cnp:
4052 case e1000_pch_tgp:
4053 case e1000_pch_adp:
4054 case e1000_pch_mtp:
4055 case e1000_pch_lnp:
4056 case e1000_pch_ptp:
4057 case e1000_pch_nvp:
4058 fc->refresh_time = 0xFFFF;
4059 fc->pause_time = 0xFFFF;
4060
4061 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
4062 fc->high_water = 0x05C20;
4063 fc->low_water = 0x05048;
4064 break;
4065 }
4066
4067 pba = 14;
4068 ew32(PBA, pba);
4069 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
4070 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
4071 break;
4072 }
4073
4074 /* Alignment of Tx data is on an arbitrary byte boundary with the
4075 * maximum size per Tx descriptor limited only to the transmit
4076 * allocation of the packet buffer minus 96 bytes with an upper
4077 * limit of 24KB due to receive synchronization limitations.
4078 */
4079 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
4080 24 << 10);
4081
4082 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
4083 * fit in receive buffer.
4084 */
4085 if (adapter->itr_setting & 0x3) {
4086 if ((adapter->max_frame_size * 2) > (pba << 10)) {
4087 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
4088 dev_info(&adapter->pdev->dev,
4089 "Interrupt Throttle Rate off\n");
4090 adapter->flags2 |= FLAG2_DISABLE_AIM;
4091 e1000e_write_itr(adapter, 0);
4092 }
4093 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
4094 dev_info(&adapter->pdev->dev,
4095 "Interrupt Throttle Rate on\n");
4096 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
4097 adapter->itr = 20000;
4098 e1000e_write_itr(adapter, adapter->itr);
4099 }
4100 }
4101
4102 if (hw->mac.type >= e1000_pch_spt)
4103 e1000_flush_desc_rings(adapter);
4104 /* Allow time for pending master requests to run */
4105 mac->ops.reset_hw(hw);
4106
4107 /* For parts with AMT enabled, let the firmware know
4108 * that the network interface is in control
4109 */
4110 if (adapter->flags & FLAG_HAS_AMT)
4111 e1000e_get_hw_control(adapter);
4112
4113 ew32(WUC, 0);
4114
4115 if (mac->ops.init_hw(hw))
4116 e_err("Hardware Error\n");
4117
4118 e1000_update_mng_vlan(adapter);
4119
4120 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
4121 ew32(VET, ETH_P_8021Q);
4122
4123 e1000e_reset_adaptive(hw);
4124
4125 /* restore systim and hwtstamp settings */
4126 e1000e_systim_reset(adapter);
4127
4128 /* Set EEE advertisement as appropriate */
4129 if (adapter->flags2 & FLAG2_HAS_EEE) {
4130 s32 ret_val;
4131 u16 adv_addr;
4132
4133 switch (hw->phy.type) {
4134 case e1000_phy_82579:
4135 adv_addr = I82579_EEE_ADVERTISEMENT;
4136 break;
4137 case e1000_phy_i217:
4138 adv_addr = I217_EEE_ADVERTISEMENT;
4139 break;
4140 default:
4141 dev_err(&adapter->pdev->dev,
4142 "Invalid PHY type setting EEE advertisement\n");
4143 return;
4144 }
4145
4146 ret_val = hw->phy.ops.acquire(hw);
4147 if (ret_val) {
4148 dev_err(&adapter->pdev->dev,
4149 "EEE advertisement - unable to acquire PHY\n");
4150 return;
4151 }
4152
4153 e1000_write_emi_reg_locked(hw, adv_addr,
4154 hw->dev_spec.ich8lan.eee_disable ?
4155 0 : adapter->eee_advert);
4156
4157 hw->phy.ops.release(hw);
4158 }
4159
4160 if (!netif_running(adapter->netdev) &&
4161 !test_bit(__E1000_TESTING, &adapter->state))
4162 e1000_power_down_phy(adapter);
4163
4164 e1000_get_phy_info(hw);
4165
4166 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
4167 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
4168 u16 phy_data = 0;
4169 /* speed up time to link by disabling smart power down, ignore
4170 * the return value of this function because there is nothing
4171 * different we would do if it failed
4172 */
4173 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
4174 phy_data &= ~IGP02E1000_PM_SPD;
4175 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
4176 }
4177 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) {
4178 u32 reg;
4179
4180 /* Fextnvm7 @ 0xe4[2] = 1 */
4181 reg = er32(FEXTNVM7);
4182 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE;
4183 ew32(FEXTNVM7, reg);
4184 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */
4185 reg = er32(FEXTNVM9);
4186 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS |
4187 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4188 ew32(FEXTNVM9, reg);
4189 }
4190
4191}
4192
4193/**
4194 * e1000e_trigger_lsc - trigger an LSC interrupt
4195 * @adapter: board private structure
4196 *
4197 * Fire a link status change interrupt to start the watchdog.
4198 **/
4199static void e1000e_trigger_lsc(struct e1000_adapter *adapter)
4200{
4201 struct e1000_hw *hw = &adapter->hw;
4202
4203 if (adapter->msix_entries)
4204 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER);
4205 else
4206 ew32(ICS, E1000_ICS_LSC);
4207}
4208
4209void e1000e_up(struct e1000_adapter *adapter)
4210{
4211 /* hardware has been reset, we need to reload some things */
4212 e1000_configure(adapter);
4213
4214 clear_bit(__E1000_DOWN, &adapter->state);
4215
4216 if (adapter->msix_entries)
4217 e1000_configure_msix(adapter);
4218 e1000_irq_enable(adapter);
4219
4220 /* Tx queue started by watchdog timer when link is up */
4221
4222 e1000e_trigger_lsc(adapter);
4223}
4224
4225static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
4226{
4227 struct e1000_hw *hw = &adapter->hw;
4228
4229 if (!(adapter->flags2 & FLAG2_DMA_BURST))
4230 return;
4231
4232 /* flush pending descriptor writebacks to memory */
4233 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4234 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4235
4236 /* execute the writes immediately */
4237 e1e_flush();
4238
4239 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
4240 * write is successful
4241 */
4242 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4243 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4244
4245 /* execute the writes immediately */
4246 e1e_flush();
4247}
4248
4249static void e1000e_update_stats(struct e1000_adapter *adapter);
4250
4251/**
4252 * e1000e_down - quiesce the device and optionally reset the hardware
4253 * @adapter: board private structure
4254 * @reset: boolean flag to reset the hardware or not
4255 */
4256void e1000e_down(struct e1000_adapter *adapter, bool reset)
4257{
4258 struct net_device *netdev = adapter->netdev;
4259 struct e1000_hw *hw = &adapter->hw;
4260 u32 tctl, rctl;
4261
4262 /* signal that we're down so the interrupt handler does not
4263 * reschedule our watchdog timer
4264 */
4265 set_bit(__E1000_DOWN, &adapter->state);
4266
4267 netif_carrier_off(netdev);
4268
4269 /* disable receives in the hardware */
4270 rctl = er32(RCTL);
4271 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4272 ew32(RCTL, rctl & ~E1000_RCTL_EN);
4273 /* flush and sleep below */
4274
4275 netif_stop_queue(netdev);
4276
4277 /* disable transmits in the hardware */
4278 tctl = er32(TCTL);
4279 tctl &= ~E1000_TCTL_EN;
4280 ew32(TCTL, tctl);
4281
4282 /* flush both disables and wait for them to finish */
4283 e1e_flush();
4284 usleep_range(10000, 11000);
4285
4286 e1000_irq_disable(adapter);
4287
4288 napi_synchronize(&adapter->napi);
4289
4290 del_timer_sync(&adapter->watchdog_timer);
4291 del_timer_sync(&adapter->phy_info_timer);
4292
4293 spin_lock(&adapter->stats64_lock);
4294 e1000e_update_stats(adapter);
4295 spin_unlock(&adapter->stats64_lock);
4296
4297 e1000e_flush_descriptors(adapter);
4298
4299 adapter->link_speed = 0;
4300 adapter->link_duplex = 0;
4301
4302 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4303 if ((hw->mac.type >= e1000_pch2lan) &&
4304 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4305 e1000_lv_jumbo_workaround_ich8lan(hw, false))
4306 e_dbg("failed to disable jumbo frame workaround mode\n");
4307
4308 if (!pci_channel_offline(adapter->pdev)) {
4309 if (reset)
4310 e1000e_reset(adapter);
4311 else if (hw->mac.type >= e1000_pch_spt)
4312 e1000_flush_desc_rings(adapter);
4313 }
4314 e1000_clean_tx_ring(adapter->tx_ring);
4315 e1000_clean_rx_ring(adapter->rx_ring);
4316}
4317
4318void e1000e_reinit_locked(struct e1000_adapter *adapter)
4319{
4320 might_sleep();
4321 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
4322 usleep_range(1000, 1100);
4323 e1000e_down(adapter, true);
4324 e1000e_up(adapter);
4325 clear_bit(__E1000_RESETTING, &adapter->state);
4326}
4327
4328/**
4329 * e1000e_sanitize_systim - sanitize raw cycle counter reads
4330 * @hw: pointer to the HW structure
4331 * @systim: PHC time value read, sanitized and returned
4332 * @sts: structure to hold system time before and after reading SYSTIML,
4333 * may be NULL
4334 *
4335 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L:
4336 * check to see that the time is incrementing at a reasonable
4337 * rate and is a multiple of incvalue.
4338 **/
4339static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim,
4340 struct ptp_system_timestamp *sts)
4341{
4342 u64 time_delta, rem, temp;
4343 u64 systim_next;
4344 u32 incvalue;
4345 int i;
4346
4347 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK;
4348 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) {
4349 /* latch SYSTIMH on read of SYSTIML */
4350 ptp_read_system_prets(sts);
4351 systim_next = (u64)er32(SYSTIML);
4352 ptp_read_system_postts(sts);
4353 systim_next |= (u64)er32(SYSTIMH) << 32;
4354
4355 time_delta = systim_next - systim;
4356 temp = time_delta;
4357 /* VMWare users have seen incvalue of zero, don't div / 0 */
4358 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0);
4359
4360 systim = systim_next;
4361
4362 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0))
4363 break;
4364 }
4365
4366 return systim;
4367}
4368
4369/**
4370 * e1000e_read_systim - read SYSTIM register
4371 * @adapter: board private structure
4372 * @sts: structure which will contain system time before and after reading
4373 * SYSTIML, may be NULL
4374 **/
4375u64 e1000e_read_systim(struct e1000_adapter *adapter,
4376 struct ptp_system_timestamp *sts)
4377{
4378 struct e1000_hw *hw = &adapter->hw;
4379 u32 systimel, systimel_2, systimeh;
4380 u64 systim;
4381 /* SYSTIMH latching upon SYSTIML read does not work well.
4382 * This means that if SYSTIML overflows after we read it but before
4383 * we read SYSTIMH, the value of SYSTIMH has been incremented and we
4384 * will experience a huge non linear increment in the systime value
4385 * to fix that we test for overflow and if true, we re-read systime.
4386 */
4387 ptp_read_system_prets(sts);
4388 systimel = er32(SYSTIML);
4389 ptp_read_system_postts(sts);
4390 systimeh = er32(SYSTIMH);
4391 /* Is systimel is so large that overflow is possible? */
4392 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) {
4393 ptp_read_system_prets(sts);
4394 systimel_2 = er32(SYSTIML);
4395 ptp_read_system_postts(sts);
4396 if (systimel > systimel_2) {
4397 /* There was an overflow, read again SYSTIMH, and use
4398 * systimel_2
4399 */
4400 systimeh = er32(SYSTIMH);
4401 systimel = systimel_2;
4402 }
4403 }
4404 systim = (u64)systimel;
4405 systim |= (u64)systimeh << 32;
4406
4407 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW)
4408 systim = e1000e_sanitize_systim(hw, systim, sts);
4409
4410 return systim;
4411}
4412
4413/**
4414 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4415 * @cc: cyclecounter structure
4416 **/
4417static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc)
4418{
4419 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4420 cc);
4421
4422 return e1000e_read_systim(adapter, NULL);
4423}
4424
4425/**
4426 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4427 * @adapter: board private structure to initialize
4428 *
4429 * e1000_sw_init initializes the Adapter private data structure.
4430 * Fields are initialized based on PCI device information and
4431 * OS network device settings (MTU size).
4432 **/
4433static int e1000_sw_init(struct e1000_adapter *adapter)
4434{
4435 struct net_device *netdev = adapter->netdev;
4436
4437 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
4438 adapter->rx_ps_bsize0 = 128;
4439 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4440 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4441 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4442 adapter->rx_ring_count = E1000_DEFAULT_RXD;
4443
4444 spin_lock_init(&adapter->stats64_lock);
4445
4446 e1000e_set_interrupt_capability(adapter);
4447
4448 if (e1000_alloc_queues(adapter))
4449 return -ENOMEM;
4450
4451 /* Setup hardware time stamping cyclecounter */
4452 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4453 adapter->cc.read = e1000e_cyclecounter_read;
4454 adapter->cc.mask = CYCLECOUNTER_MASK(64);
4455 adapter->cc.mult = 1;
4456 /* cc.shift set in e1000e_get_base_tininca() */
4457
4458 spin_lock_init(&adapter->systim_lock);
4459 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4460 }
4461
4462 /* Explicitly disable IRQ since the NIC can be in any state. */
4463 e1000_irq_disable(adapter);
4464
4465 set_bit(__E1000_DOWN, &adapter->state);
4466 return 0;
4467}
4468
4469/**
4470 * e1000_intr_msi_test - Interrupt Handler
4471 * @irq: interrupt number
4472 * @data: pointer to a network interface device structure
4473 **/
4474static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
4475{
4476 struct net_device *netdev = data;
4477 struct e1000_adapter *adapter = netdev_priv(netdev);
4478 struct e1000_hw *hw = &adapter->hw;
4479 u32 icr = er32(ICR);
4480
4481 e_dbg("icr is %08X\n", icr);
4482 if (icr & E1000_ICR_RXSEQ) {
4483 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
4484 /* Force memory writes to complete before acknowledging the
4485 * interrupt is handled.
4486 */
4487 wmb();
4488 }
4489
4490 return IRQ_HANDLED;
4491}
4492
4493/**
4494 * e1000_test_msi_interrupt - Returns 0 for successful test
4495 * @adapter: board private struct
4496 *
4497 * code flow taken from tg3.c
4498 **/
4499static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4500{
4501 struct net_device *netdev = adapter->netdev;
4502 struct e1000_hw *hw = &adapter->hw;
4503 int err;
4504
4505 /* poll_enable hasn't been called yet, so don't need disable */
4506 /* clear any pending events */
4507 er32(ICR);
4508
4509 /* free the real vector and request a test handler */
4510 e1000_free_irq(adapter);
4511 e1000e_reset_interrupt_capability(adapter);
4512
4513 /* Assume that the test fails, if it succeeds then the test
4514 * MSI irq handler will unset this flag
4515 */
4516 adapter->flags |= FLAG_MSI_TEST_FAILED;
4517
4518 err = pci_enable_msi(adapter->pdev);
4519 if (err)
4520 goto msi_test_failed;
4521
4522 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
4523 netdev->name, netdev);
4524 if (err) {
4525 pci_disable_msi(adapter->pdev);
4526 goto msi_test_failed;
4527 }
4528
4529 /* Force memory writes to complete before enabling and firing an
4530 * interrupt.
4531 */
4532 wmb();
4533
4534 e1000_irq_enable(adapter);
4535
4536 /* fire an unusual interrupt on the test handler */
4537 ew32(ICS, E1000_ICS_RXSEQ);
4538 e1e_flush();
4539 msleep(100);
4540
4541 e1000_irq_disable(adapter);
4542
4543 rmb(); /* read flags after interrupt has been fired */
4544
4545 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4546 adapter->int_mode = E1000E_INT_MODE_LEGACY;
4547 e_info("MSI interrupt test failed, using legacy interrupt.\n");
4548 } else {
4549 e_dbg("MSI interrupt test succeeded!\n");
4550 }
4551
4552 free_irq(adapter->pdev->irq, netdev);
4553 pci_disable_msi(adapter->pdev);
4554
4555msi_test_failed:
4556 e1000e_set_interrupt_capability(adapter);
4557 return e1000_request_irq(adapter);
4558}
4559
4560/**
4561 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4562 * @adapter: board private struct
4563 *
4564 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4565 **/
4566static int e1000_test_msi(struct e1000_adapter *adapter)
4567{
4568 int err;
4569 u16 pci_cmd;
4570
4571 if (!(adapter->flags & FLAG_MSI_ENABLED))
4572 return 0;
4573
4574 /* disable SERR in case the MSI write causes a master abort */
4575 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4576 if (pci_cmd & PCI_COMMAND_SERR)
4577 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4578 pci_cmd & ~PCI_COMMAND_SERR);
4579
4580 err = e1000_test_msi_interrupt(adapter);
4581
4582 /* re-enable SERR */
4583 if (pci_cmd & PCI_COMMAND_SERR) {
4584 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4585 pci_cmd |= PCI_COMMAND_SERR;
4586 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4587 }
4588
4589 return err;
4590}
4591
4592/**
4593 * e1000e_open - Called when a network interface is made active
4594 * @netdev: network interface device structure
4595 *
4596 * Returns 0 on success, negative value on failure
4597 *
4598 * The open entry point is called when a network interface is made
4599 * active by the system (IFF_UP). At this point all resources needed
4600 * for transmit and receive operations are allocated, the interrupt
4601 * handler is registered with the OS, the watchdog timer is started,
4602 * and the stack is notified that the interface is ready.
4603 **/
4604int e1000e_open(struct net_device *netdev)
4605{
4606 struct e1000_adapter *adapter = netdev_priv(netdev);
4607 struct e1000_hw *hw = &adapter->hw;
4608 struct pci_dev *pdev = adapter->pdev;
4609 int err;
4610 int irq;
4611
4612 /* disallow open during test */
4613 if (test_bit(__E1000_TESTING, &adapter->state))
4614 return -EBUSY;
4615
4616 pm_runtime_get_sync(&pdev->dev);
4617
4618 netif_carrier_off(netdev);
4619 netif_stop_queue(netdev);
4620
4621 /* allocate transmit descriptors */
4622 err = e1000e_setup_tx_resources(adapter->tx_ring);
4623 if (err)
4624 goto err_setup_tx;
4625
4626 /* allocate receive descriptors */
4627 err = e1000e_setup_rx_resources(adapter->rx_ring);
4628 if (err)
4629 goto err_setup_rx;
4630
4631 /* If AMT is enabled, let the firmware know that the network
4632 * interface is now open and reset the part to a known state.
4633 */
4634 if (adapter->flags & FLAG_HAS_AMT) {
4635 e1000e_get_hw_control(adapter);
4636 e1000e_reset(adapter);
4637 }
4638
4639 e1000e_power_up_phy(adapter);
4640
4641 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4642 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4643 e1000_update_mng_vlan(adapter);
4644
4645 /* DMA latency requirement to workaround jumbo issue */
4646 cpu_latency_qos_add_request(&adapter->pm_qos_req, PM_QOS_DEFAULT_VALUE);
4647
4648 /* before we allocate an interrupt, we must be ready to handle it.
4649 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4650 * as soon as we call pci_request_irq, so we have to setup our
4651 * clean_rx handler before we do so.
4652 */
4653 e1000_configure(adapter);
4654
4655 err = e1000_request_irq(adapter);
4656 if (err)
4657 goto err_req_irq;
4658
4659 /* Work around PCIe errata with MSI interrupts causing some chipsets to
4660 * ignore e1000e MSI messages, which means we need to test our MSI
4661 * interrupt now
4662 */
4663 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
4664 err = e1000_test_msi(adapter);
4665 if (err) {
4666 e_err("Interrupt allocation failed\n");
4667 goto err_req_irq;
4668 }
4669 }
4670
4671 /* From here on the code is the same as e1000e_up() */
4672 clear_bit(__E1000_DOWN, &adapter->state);
4673
4674 if (adapter->int_mode == E1000E_INT_MODE_MSIX)
4675 irq = adapter->msix_entries[0].vector;
4676 else
4677 irq = adapter->pdev->irq;
4678
4679 netif_napi_set_irq(&adapter->napi, irq);
4680 napi_enable(&adapter->napi);
4681 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_RX, &adapter->napi);
4682 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_TX, &adapter->napi);
4683
4684 e1000_irq_enable(adapter);
4685
4686 adapter->tx_hang_recheck = false;
4687
4688 hw->mac.get_link_status = true;
4689 pm_runtime_put(&pdev->dev);
4690
4691 e1000e_trigger_lsc(adapter);
4692
4693 return 0;
4694
4695err_req_irq:
4696 cpu_latency_qos_remove_request(&adapter->pm_qos_req);
4697 e1000e_release_hw_control(adapter);
4698 e1000_power_down_phy(adapter);
4699 e1000e_free_rx_resources(adapter->rx_ring);
4700err_setup_rx:
4701 e1000e_free_tx_resources(adapter->tx_ring);
4702err_setup_tx:
4703 e1000e_reset(adapter);
4704 pm_runtime_put_sync(&pdev->dev);
4705
4706 return err;
4707}
4708
4709/**
4710 * e1000e_close - Disables a network interface
4711 * @netdev: network interface device structure
4712 *
4713 * Returns 0, this is not allowed to fail
4714 *
4715 * The close entry point is called when an interface is de-activated
4716 * by the OS. The hardware is still under the drivers control, but
4717 * needs to be disabled. A global MAC reset is issued to stop the
4718 * hardware, and all transmit and receive resources are freed.
4719 **/
4720int e1000e_close(struct net_device *netdev)
4721{
4722 struct e1000_adapter *adapter = netdev_priv(netdev);
4723 struct pci_dev *pdev = adapter->pdev;
4724 int count = E1000_CHECK_RESET_COUNT;
4725
4726 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4727 usleep_range(10000, 11000);
4728
4729 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
4730
4731 pm_runtime_get_sync(&pdev->dev);
4732
4733 if (netif_device_present(netdev)) {
4734 e1000e_down(adapter, true);
4735 e1000_free_irq(adapter);
4736
4737 /* Link status message must follow this format */
4738 netdev_info(netdev, "NIC Link is Down\n");
4739 }
4740
4741 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_RX, NULL);
4742 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_TX, NULL);
4743 napi_disable(&adapter->napi);
4744
4745 e1000e_free_tx_resources(adapter->tx_ring);
4746 e1000e_free_rx_resources(adapter->rx_ring);
4747
4748 /* kill manageability vlan ID if supported, but not if a vlan with
4749 * the same ID is registered on the host OS (let 8021q kill it)
4750 */
4751 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
4752 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4753 adapter->mng_vlan_id);
4754
4755 /* If AMT is enabled, let the firmware know that the network
4756 * interface is now closed
4757 */
4758 if ((adapter->flags & FLAG_HAS_AMT) &&
4759 !test_bit(__E1000_TESTING, &adapter->state))
4760 e1000e_release_hw_control(adapter);
4761
4762 cpu_latency_qos_remove_request(&adapter->pm_qos_req);
4763
4764 pm_runtime_put_sync(&pdev->dev);
4765
4766 return 0;
4767}
4768
4769/**
4770 * e1000_set_mac - Change the Ethernet Address of the NIC
4771 * @netdev: network interface device structure
4772 * @p: pointer to an address structure
4773 *
4774 * Returns 0 on success, negative on failure
4775 **/
4776static int e1000_set_mac(struct net_device *netdev, void *p)
4777{
4778 struct e1000_adapter *adapter = netdev_priv(netdev);
4779 struct e1000_hw *hw = &adapter->hw;
4780 struct sockaddr *addr = p;
4781
4782 if (!is_valid_ether_addr(addr->sa_data))
4783 return -EADDRNOTAVAIL;
4784
4785 eth_hw_addr_set(netdev, addr->sa_data);
4786 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4787
4788 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4789
4790 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4791 /* activate the work around */
4792 e1000e_set_laa_state_82571(&adapter->hw, 1);
4793
4794 /* Hold a copy of the LAA in RAR[14] This is done so that
4795 * between the time RAR[0] gets clobbered and the time it
4796 * gets fixed (in e1000_watchdog), the actual LAA is in one
4797 * of the RARs and no incoming packets directed to this port
4798 * are dropped. Eventually the LAA will be in RAR[0] and
4799 * RAR[14]
4800 */
4801 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4802 adapter->hw.mac.rar_entry_count - 1);
4803 }
4804
4805 return 0;
4806}
4807
4808/**
4809 * e1000e_update_phy_task - work thread to update phy
4810 * @work: pointer to our work struct
4811 *
4812 * this worker thread exists because we must acquire a
4813 * semaphore to read the phy, which we could msleep while
4814 * waiting for it, and we can't msleep in a timer.
4815 **/
4816static void e1000e_update_phy_task(struct work_struct *work)
4817{
4818 struct e1000_adapter *adapter = container_of(work,
4819 struct e1000_adapter,
4820 update_phy_task);
4821 struct e1000_hw *hw = &adapter->hw;
4822
4823 if (test_bit(__E1000_DOWN, &adapter->state))
4824 return;
4825
4826 e1000_get_phy_info(hw);
4827
4828 /* Enable EEE on 82579 after link up */
4829 if (hw->phy.type >= e1000_phy_82579)
4830 e1000_set_eee_pchlan(hw);
4831}
4832
4833/**
4834 * e1000_update_phy_info - timre call-back to update PHY info
4835 * @t: pointer to timer_list containing private info adapter
4836 *
4837 * Need to wait a few seconds after link up to get diagnostic information from
4838 * the phy
4839 **/
4840static void e1000_update_phy_info(struct timer_list *t)
4841{
4842 struct e1000_adapter *adapter = from_timer(adapter, t, phy_info_timer);
4843
4844 if (test_bit(__E1000_DOWN, &adapter->state))
4845 return;
4846
4847 schedule_work(&adapter->update_phy_task);
4848}
4849
4850/**
4851 * e1000e_update_phy_stats - Update the PHY statistics counters
4852 * @adapter: board private structure
4853 *
4854 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4855 **/
4856static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4857{
4858 struct e1000_hw *hw = &adapter->hw;
4859 s32 ret_val;
4860 u16 phy_data;
4861
4862 ret_val = hw->phy.ops.acquire(hw);
4863 if (ret_val)
4864 return;
4865
4866 /* A page set is expensive so check if already on desired page.
4867 * If not, set to the page with the PHY status registers.
4868 */
4869 hw->phy.addr = 1;
4870 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4871 &phy_data);
4872 if (ret_val)
4873 goto release;
4874 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4875 ret_val = hw->phy.ops.set_page(hw,
4876 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4877 if (ret_val)
4878 goto release;
4879 }
4880
4881 /* Single Collision Count */
4882 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4883 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4884 if (!ret_val)
4885 adapter->stats.scc += phy_data;
4886
4887 /* Excessive Collision Count */
4888 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4889 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4890 if (!ret_val)
4891 adapter->stats.ecol += phy_data;
4892
4893 /* Multiple Collision Count */
4894 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4895 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4896 if (!ret_val)
4897 adapter->stats.mcc += phy_data;
4898
4899 /* Late Collision Count */
4900 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4901 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4902 if (!ret_val)
4903 adapter->stats.latecol += phy_data;
4904
4905 /* Collision Count - also used for adaptive IFS */
4906 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4907 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4908 if (!ret_val)
4909 hw->mac.collision_delta = phy_data;
4910
4911 /* Defer Count */
4912 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4913 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4914 if (!ret_val)
4915 adapter->stats.dc += phy_data;
4916
4917 /* Transmit with no CRS */
4918 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4919 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4920 if (!ret_val)
4921 adapter->stats.tncrs += phy_data;
4922
4923release:
4924 hw->phy.ops.release(hw);
4925}
4926
4927/**
4928 * e1000e_update_stats - Update the board statistics counters
4929 * @adapter: board private structure
4930 **/
4931static void e1000e_update_stats(struct e1000_adapter *adapter)
4932{
4933 struct net_device *netdev = adapter->netdev;
4934 struct e1000_hw *hw = &adapter->hw;
4935 struct pci_dev *pdev = adapter->pdev;
4936
4937 /* Prevent stats update while adapter is being reset, or if the pci
4938 * connection is down.
4939 */
4940 if (adapter->link_speed == 0)
4941 return;
4942 if (pci_channel_offline(pdev))
4943 return;
4944
4945 adapter->stats.crcerrs += er32(CRCERRS);
4946 adapter->stats.gprc += er32(GPRC);
4947 adapter->stats.gorc += er32(GORCL);
4948 er32(GORCH); /* Clear gorc */
4949 adapter->stats.bprc += er32(BPRC);
4950 adapter->stats.mprc += er32(MPRC);
4951 adapter->stats.roc += er32(ROC);
4952
4953 adapter->stats.mpc += er32(MPC);
4954
4955 /* Half-duplex statistics */
4956 if (adapter->link_duplex == HALF_DUPLEX) {
4957 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4958 e1000e_update_phy_stats(adapter);
4959 } else {
4960 adapter->stats.scc += er32(SCC);
4961 adapter->stats.ecol += er32(ECOL);
4962 adapter->stats.mcc += er32(MCC);
4963 adapter->stats.latecol += er32(LATECOL);
4964 adapter->stats.dc += er32(DC);
4965
4966 hw->mac.collision_delta = er32(COLC);
4967
4968 if ((hw->mac.type != e1000_82574) &&
4969 (hw->mac.type != e1000_82583))
4970 adapter->stats.tncrs += er32(TNCRS);
4971 }
4972 adapter->stats.colc += hw->mac.collision_delta;
4973 }
4974
4975 adapter->stats.xonrxc += er32(XONRXC);
4976 adapter->stats.xontxc += er32(XONTXC);
4977 adapter->stats.xoffrxc += er32(XOFFRXC);
4978 adapter->stats.xofftxc += er32(XOFFTXC);
4979 adapter->stats.gptc += er32(GPTC);
4980 adapter->stats.gotc += er32(GOTCL);
4981 er32(GOTCH); /* Clear gotc */
4982 adapter->stats.rnbc += er32(RNBC);
4983 adapter->stats.ruc += er32(RUC);
4984
4985 adapter->stats.mptc += er32(MPTC);
4986 adapter->stats.bptc += er32(BPTC);
4987
4988 /* used for adaptive IFS */
4989
4990 hw->mac.tx_packet_delta = er32(TPT);
4991 adapter->stats.tpt += hw->mac.tx_packet_delta;
4992
4993 adapter->stats.algnerrc += er32(ALGNERRC);
4994 adapter->stats.rxerrc += er32(RXERRC);
4995 adapter->stats.cexterr += er32(CEXTERR);
4996 adapter->stats.tsctc += er32(TSCTC);
4997 adapter->stats.tsctfc += er32(TSCTFC);
4998
4999 /* Fill out the OS statistics structure */
5000 netdev->stats.multicast = adapter->stats.mprc;
5001 netdev->stats.collisions = adapter->stats.colc;
5002
5003 /* Rx Errors */
5004
5005 /* RLEC on some newer hardware can be incorrect so build
5006 * our own version based on RUC and ROC
5007 */
5008 netdev->stats.rx_errors = adapter->stats.rxerrc +
5009 adapter->stats.crcerrs + adapter->stats.algnerrc +
5010 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5011 netdev->stats.rx_length_errors = adapter->stats.ruc +
5012 adapter->stats.roc;
5013 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5014 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
5015 netdev->stats.rx_missed_errors = adapter->stats.mpc;
5016
5017 /* Tx Errors */
5018 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
5019 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
5020 netdev->stats.tx_window_errors = adapter->stats.latecol;
5021 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
5022
5023 /* Tx Dropped needs to be maintained elsewhere */
5024
5025 /* Management Stats */
5026 adapter->stats.mgptc += er32(MGTPTC);
5027 adapter->stats.mgprc += er32(MGTPRC);
5028 adapter->stats.mgpdc += er32(MGTPDC);
5029
5030 /* Correctable ECC Errors */
5031 if (hw->mac.type >= e1000_pch_lpt) {
5032 u32 pbeccsts = er32(PBECCSTS);
5033
5034 adapter->corr_errors +=
5035 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
5036 adapter->uncorr_errors +=
5037 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);
5038 }
5039}
5040
5041/**
5042 * e1000_phy_read_status - Update the PHY register status snapshot
5043 * @adapter: board private structure
5044 **/
5045static void e1000_phy_read_status(struct e1000_adapter *adapter)
5046{
5047 struct e1000_hw *hw = &adapter->hw;
5048 struct e1000_phy_regs *phy = &adapter->phy_regs;
5049
5050 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
5051 (er32(STATUS) & E1000_STATUS_LU) &&
5052 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
5053 int ret_val;
5054
5055 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
5056 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
5057 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
5058 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
5059 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
5060 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
5061 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
5062 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
5063 if (ret_val)
5064 e_warn("Error reading PHY register\n");
5065 } else {
5066 /* Do not read PHY registers if link is not up
5067 * Set values to typical power-on defaults
5068 */
5069 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
5070 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
5071 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
5072 BMSR_ERCAP);
5073 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
5074 ADVERTISE_ALL | ADVERTISE_CSMA);
5075 phy->lpa = 0;
5076 phy->expansion = EXPANSION_ENABLENPAGE;
5077 phy->ctrl1000 = ADVERTISE_1000FULL;
5078 phy->stat1000 = 0;
5079 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
5080 }
5081}
5082
5083static void e1000_print_link_info(struct e1000_adapter *adapter)
5084{
5085 struct e1000_hw *hw = &adapter->hw;
5086 u32 ctrl = er32(CTRL);
5087
5088 /* Link status message must follow this format for user tools */
5089 netdev_info(adapter->netdev,
5090 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5091 adapter->link_speed,
5092 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
5093 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
5094 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
5095 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
5096}
5097
5098static bool e1000e_has_link(struct e1000_adapter *adapter)
5099{
5100 struct e1000_hw *hw = &adapter->hw;
5101 bool link_active = false;
5102 s32 ret_val = 0;
5103
5104 /* get_link_status is set on LSC (link status) interrupt or
5105 * Rx sequence error interrupt. get_link_status will stay
5106 * true until the check_for_link establishes link
5107 * for copper adapters ONLY
5108 */
5109 switch (hw->phy.media_type) {
5110 case e1000_media_type_copper:
5111 if (hw->mac.get_link_status) {
5112 ret_val = hw->mac.ops.check_for_link(hw);
5113 link_active = !hw->mac.get_link_status;
5114 } else {
5115 link_active = true;
5116 }
5117 break;
5118 case e1000_media_type_fiber:
5119 ret_val = hw->mac.ops.check_for_link(hw);
5120 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
5121 break;
5122 case e1000_media_type_internal_serdes:
5123 ret_val = hw->mac.ops.check_for_link(hw);
5124 link_active = hw->mac.serdes_has_link;
5125 break;
5126 default:
5127 case e1000_media_type_unknown:
5128 break;
5129 }
5130
5131 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
5132 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
5133 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
5134 e_info("Gigabit has been disabled, downgrading speed\n");
5135 }
5136
5137 return link_active;
5138}
5139
5140static void e1000e_enable_receives(struct e1000_adapter *adapter)
5141{
5142 /* make sure the receive unit is started */
5143 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5144 (adapter->flags & FLAG_RESTART_NOW)) {
5145 struct e1000_hw *hw = &adapter->hw;
5146 u32 rctl = er32(RCTL);
5147
5148 ew32(RCTL, rctl | E1000_RCTL_EN);
5149 adapter->flags &= ~FLAG_RESTART_NOW;
5150 }
5151}
5152
5153static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
5154{
5155 struct e1000_hw *hw = &adapter->hw;
5156
5157 /* With 82574 controllers, PHY needs to be checked periodically
5158 * for hung state and reset, if two calls return true
5159 */
5160 if (e1000_check_phy_82574(hw))
5161 adapter->phy_hang_count++;
5162 else
5163 adapter->phy_hang_count = 0;
5164
5165 if (adapter->phy_hang_count > 1) {
5166 adapter->phy_hang_count = 0;
5167 e_dbg("PHY appears hung - resetting\n");
5168 schedule_work(&adapter->reset_task);
5169 }
5170}
5171
5172/**
5173 * e1000_watchdog - Timer Call-back
5174 * @t: pointer to timer_list containing private info adapter
5175 **/
5176static void e1000_watchdog(struct timer_list *t)
5177{
5178 struct e1000_adapter *adapter = from_timer(adapter, t, watchdog_timer);
5179
5180 /* Do the rest outside of interrupt context */
5181 schedule_work(&adapter->watchdog_task);
5182
5183 /* TODO: make this use queue_delayed_work() */
5184}
5185
5186static void e1000_watchdog_task(struct work_struct *work)
5187{
5188 struct e1000_adapter *adapter = container_of(work,
5189 struct e1000_adapter,
5190 watchdog_task);
5191 struct net_device *netdev = adapter->netdev;
5192 struct e1000_mac_info *mac = &adapter->hw.mac;
5193 struct e1000_phy_info *phy = &adapter->hw.phy;
5194 struct e1000_ring *tx_ring = adapter->tx_ring;
5195 u32 dmoff_exit_timeout = 100, tries = 0;
5196 struct e1000_hw *hw = &adapter->hw;
5197 u32 link, tctl, pcim_state;
5198
5199 if (test_bit(__E1000_DOWN, &adapter->state))
5200 return;
5201
5202 link = e1000e_has_link(adapter);
5203 if ((netif_carrier_ok(netdev)) && link) {
5204 /* Cancel scheduled suspend requests. */
5205 pm_runtime_resume(netdev->dev.parent);
5206
5207 e1000e_enable_receives(adapter);
5208 goto link_up;
5209 }
5210
5211 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
5212 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
5213 e1000_update_mng_vlan(adapter);
5214
5215 if (link) {
5216 if (!netif_carrier_ok(netdev)) {
5217 bool txb2b = true;
5218
5219 /* Cancel scheduled suspend requests. */
5220 pm_runtime_resume(netdev->dev.parent);
5221
5222 /* Checking if MAC is in DMoff state*/
5223 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
5224 pcim_state = er32(STATUS);
5225 while (pcim_state & E1000_STATUS_PCIM_STATE) {
5226 if (tries++ == dmoff_exit_timeout) {
5227 e_dbg("Error in exiting dmoff\n");
5228 break;
5229 }
5230 usleep_range(10000, 20000);
5231 pcim_state = er32(STATUS);
5232
5233 /* Checking if MAC exited DMoff state */
5234 if (!(pcim_state & E1000_STATUS_PCIM_STATE))
5235 e1000_phy_hw_reset(&adapter->hw);
5236 }
5237 }
5238
5239 /* update snapshot of PHY registers on LSC */
5240 e1000_phy_read_status(adapter);
5241 mac->ops.get_link_up_info(&adapter->hw,
5242 &adapter->link_speed,
5243 &adapter->link_duplex);
5244 e1000_print_link_info(adapter);
5245
5246 /* check if SmartSpeed worked */
5247 e1000e_check_downshift(hw);
5248 if (phy->speed_downgraded)
5249 netdev_warn(netdev,
5250 "Link Speed was downgraded by SmartSpeed\n");
5251
5252 /* On supported PHYs, check for duplex mismatch only
5253 * if link has autonegotiated at 10/100 half
5254 */
5255 if ((hw->phy.type == e1000_phy_igp_3 ||
5256 hw->phy.type == e1000_phy_bm) &&
5257 hw->mac.autoneg &&
5258 (adapter->link_speed == SPEED_10 ||
5259 adapter->link_speed == SPEED_100) &&
5260 (adapter->link_duplex == HALF_DUPLEX)) {
5261 u16 autoneg_exp;
5262
5263 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
5264
5265 if (!(autoneg_exp & EXPANSION_NWAY))
5266 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
5267 }
5268
5269 /* adjust timeout factor according to speed/duplex */
5270 adapter->tx_timeout_factor = 1;
5271 switch (adapter->link_speed) {
5272 case SPEED_10:
5273 txb2b = false;
5274 adapter->tx_timeout_factor = 16;
5275 break;
5276 case SPEED_100:
5277 txb2b = false;
5278 adapter->tx_timeout_factor = 10;
5279 break;
5280 }
5281
5282 /* workaround: re-program speed mode bit after
5283 * link-up event
5284 */
5285 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
5286 !txb2b) {
5287 u32 tarc0;
5288
5289 tarc0 = er32(TARC(0));
5290 tarc0 &= ~SPEED_MODE_BIT;
5291 ew32(TARC(0), tarc0);
5292 }
5293
5294 /* enable transmits in the hardware, need to do this
5295 * after setting TARC(0)
5296 */
5297 tctl = er32(TCTL);
5298 tctl |= E1000_TCTL_EN;
5299 ew32(TCTL, tctl);
5300
5301 /* Perform any post-link-up configuration before
5302 * reporting link up.
5303 */
5304 if (phy->ops.cfg_on_link_up)
5305 phy->ops.cfg_on_link_up(hw);
5306
5307 netif_wake_queue(netdev);
5308 netif_carrier_on(netdev);
5309
5310 if (!test_bit(__E1000_DOWN, &adapter->state))
5311 mod_timer(&adapter->phy_info_timer,
5312 round_jiffies(jiffies + 2 * HZ));
5313 }
5314 } else {
5315 if (netif_carrier_ok(netdev)) {
5316 adapter->link_speed = 0;
5317 adapter->link_duplex = 0;
5318 /* Link status message must follow this format */
5319 netdev_info(netdev, "NIC Link is Down\n");
5320 netif_carrier_off(netdev);
5321 netif_stop_queue(netdev);
5322 if (!test_bit(__E1000_DOWN, &adapter->state))
5323 mod_timer(&adapter->phy_info_timer,
5324 round_jiffies(jiffies + 2 * HZ));
5325
5326 /* 8000ES2LAN requires a Rx packet buffer work-around
5327 * on link down event; reset the controller to flush
5328 * the Rx packet buffer.
5329 */
5330 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
5331 adapter->flags |= FLAG_RESTART_NOW;
5332 else
5333 pm_schedule_suspend(netdev->dev.parent,
5334 LINK_TIMEOUT);
5335 }
5336 }
5337
5338link_up:
5339 spin_lock(&adapter->stats64_lock);
5340 e1000e_update_stats(adapter);
5341
5342 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
5343 adapter->tpt_old = adapter->stats.tpt;
5344 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
5345 adapter->colc_old = adapter->stats.colc;
5346
5347 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
5348 adapter->gorc_old = adapter->stats.gorc;
5349 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
5350 adapter->gotc_old = adapter->stats.gotc;
5351 spin_unlock(&adapter->stats64_lock);
5352
5353 /* If the link is lost the controller stops DMA, but
5354 * if there is queued Tx work it cannot be done. So
5355 * reset the controller to flush the Tx packet buffers.
5356 */
5357 if (!netif_carrier_ok(netdev) &&
5358 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
5359 adapter->flags |= FLAG_RESTART_NOW;
5360
5361 /* If reset is necessary, do it outside of interrupt context. */
5362 if (adapter->flags & FLAG_RESTART_NOW) {
5363 schedule_work(&adapter->reset_task);
5364 /* return immediately since reset is imminent */
5365 return;
5366 }
5367
5368 e1000e_update_adaptive(&adapter->hw);
5369
5370 /* Simple mode for Interrupt Throttle Rate (ITR) */
5371 if (adapter->itr_setting == 4) {
5372 /* Symmetric Tx/Rx gets a reduced ITR=2000;
5373 * Total asymmetrical Tx or Rx gets ITR=8000;
5374 * everyone else is between 2000-8000.
5375 */
5376 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5377 u32 dif = (adapter->gotc > adapter->gorc ?
5378 adapter->gotc - adapter->gorc :
5379 adapter->gorc - adapter->gotc) / 10000;
5380 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5381
5382 e1000e_write_itr(adapter, itr);
5383 }
5384
5385 /* Cause software interrupt to ensure Rx ring is cleaned */
5386 if (adapter->msix_entries)
5387 ew32(ICS, adapter->rx_ring->ims_val);
5388 else
5389 ew32(ICS, E1000_ICS_RXDMT0);
5390
5391 /* flush pending descriptors to memory before detecting Tx hang */
5392 e1000e_flush_descriptors(adapter);
5393
5394 /* Force detection of hung controller every watchdog period */
5395 adapter->detect_tx_hung = true;
5396
5397 /* With 82571 controllers, LAA may be overwritten due to controller
5398 * reset from the other port. Set the appropriate LAA in RAR[0]
5399 */
5400 if (e1000e_get_laa_state_82571(hw))
5401 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
5402
5403 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5404 e1000e_check_82574_phy_workaround(adapter);
5405
5406 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5407 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5408 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5409 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5410 er32(RXSTMPH);
5411 adapter->rx_hwtstamp_cleared++;
5412 } else {
5413 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5414 }
5415 }
5416
5417 /* Reset the timer */
5418 if (!test_bit(__E1000_DOWN, &adapter->state))
5419 mod_timer(&adapter->watchdog_timer,
5420 round_jiffies(jiffies + 2 * HZ));
5421}
5422
5423#define E1000_TX_FLAGS_CSUM 0x00000001
5424#define E1000_TX_FLAGS_VLAN 0x00000002
5425#define E1000_TX_FLAGS_TSO 0x00000004
5426#define E1000_TX_FLAGS_IPV4 0x00000008
5427#define E1000_TX_FLAGS_NO_FCS 0x00000010
5428#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5429#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5430#define E1000_TX_FLAGS_VLAN_SHIFT 16
5431
5432static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb,
5433 __be16 protocol)
5434{
5435 struct e1000_context_desc *context_desc;
5436 struct e1000_buffer *buffer_info;
5437 unsigned int i;
5438 u32 cmd_length = 0;
5439 u16 ipcse = 0, mss;
5440 u8 ipcss, ipcso, tucss, tucso, hdr_len;
5441 int err;
5442
5443 if (!skb_is_gso(skb))
5444 return 0;
5445
5446 err = skb_cow_head(skb, 0);
5447 if (err < 0)
5448 return err;
5449
5450 hdr_len = skb_tcp_all_headers(skb);
5451 mss = skb_shinfo(skb)->gso_size;
5452 if (protocol == htons(ETH_P_IP)) {
5453 struct iphdr *iph = ip_hdr(skb);
5454 iph->tot_len = 0;
5455 iph->check = 0;
5456 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
5457 0, IPPROTO_TCP, 0);
5458 cmd_length = E1000_TXD_CMD_IP;
5459 ipcse = skb_transport_offset(skb) - 1;
5460 } else if (skb_is_gso_v6(skb)) {
5461 tcp_v6_gso_csum_prep(skb);
5462 ipcse = 0;
5463 }
5464 ipcss = skb_network_offset(skb);
5465 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5466 tucss = skb_transport_offset(skb);
5467 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
5468
5469 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
5470 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
5471
5472 i = tx_ring->next_to_use;
5473 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5474 buffer_info = &tx_ring->buffer_info[i];
5475
5476 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5477 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5478 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
5479 context_desc->upper_setup.tcp_fields.tucss = tucss;
5480 context_desc->upper_setup.tcp_fields.tucso = tucso;
5481 context_desc->upper_setup.tcp_fields.tucse = 0;
5482 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
5483 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5484 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5485
5486 buffer_info->time_stamp = jiffies;
5487 buffer_info->next_to_watch = i;
5488
5489 i++;
5490 if (i == tx_ring->count)
5491 i = 0;
5492 tx_ring->next_to_use = i;
5493
5494 return 1;
5495}
5496
5497static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb,
5498 __be16 protocol)
5499{
5500 struct e1000_adapter *adapter = tx_ring->adapter;
5501 struct e1000_context_desc *context_desc;
5502 struct e1000_buffer *buffer_info;
5503 unsigned int i;
5504 u8 css;
5505 u32 cmd_len = E1000_TXD_CMD_DEXT;
5506
5507 if (skb->ip_summed != CHECKSUM_PARTIAL)
5508 return false;
5509
5510 switch (protocol) {
5511 case cpu_to_be16(ETH_P_IP):
5512 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5513 cmd_len |= E1000_TXD_CMD_TCP;
5514 break;
5515 case cpu_to_be16(ETH_P_IPV6):
5516 /* XXX not handling all IPV6 headers */
5517 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5518 cmd_len |= E1000_TXD_CMD_TCP;
5519 break;
5520 default:
5521 if (unlikely(net_ratelimit()))
5522 e_warn("checksum_partial proto=%x!\n",
5523 be16_to_cpu(protocol));
5524 break;
5525 }
5526
5527 css = skb_checksum_start_offset(skb);
5528
5529 i = tx_ring->next_to_use;
5530 buffer_info = &tx_ring->buffer_info[i];
5531 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5532
5533 context_desc->lower_setup.ip_config = 0;
5534 context_desc->upper_setup.tcp_fields.tucss = css;
5535 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
5536 context_desc->upper_setup.tcp_fields.tucse = 0;
5537 context_desc->tcp_seg_setup.data = 0;
5538 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5539
5540 buffer_info->time_stamp = jiffies;
5541 buffer_info->next_to_watch = i;
5542
5543 i++;
5544 if (i == tx_ring->count)
5545 i = 0;
5546 tx_ring->next_to_use = i;
5547
5548 return true;
5549}
5550
5551static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5552 unsigned int first, unsigned int max_per_txd,
5553 unsigned int nr_frags)
5554{
5555 struct e1000_adapter *adapter = tx_ring->adapter;
5556 struct pci_dev *pdev = adapter->pdev;
5557 struct e1000_buffer *buffer_info;
5558 unsigned int len = skb_headlen(skb);
5559 unsigned int offset = 0, size, count = 0, i;
5560 unsigned int f, bytecount, segs;
5561
5562 i = tx_ring->next_to_use;
5563
5564 while (len) {
5565 buffer_info = &tx_ring->buffer_info[i];
5566 size = min(len, max_per_txd);
5567
5568 buffer_info->length = size;
5569 buffer_info->time_stamp = jiffies;
5570 buffer_info->next_to_watch = i;
5571 buffer_info->dma = dma_map_single(&pdev->dev,
5572 skb->data + offset,
5573 size, DMA_TO_DEVICE);
5574 buffer_info->mapped_as_page = false;
5575 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5576 goto dma_error;
5577
5578 len -= size;
5579 offset += size;
5580 count++;
5581
5582 if (len) {
5583 i++;
5584 if (i == tx_ring->count)
5585 i = 0;
5586 }
5587 }
5588
5589 for (f = 0; f < nr_frags; f++) {
5590 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
5591
5592 len = skb_frag_size(frag);
5593 offset = 0;
5594
5595 while (len) {
5596 i++;
5597 if (i == tx_ring->count)
5598 i = 0;
5599
5600 buffer_info = &tx_ring->buffer_info[i];
5601 size = min(len, max_per_txd);
5602
5603 buffer_info->length = size;
5604 buffer_info->time_stamp = jiffies;
5605 buffer_info->next_to_watch = i;
5606 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
5607 offset, size,
5608 DMA_TO_DEVICE);
5609 buffer_info->mapped_as_page = true;
5610 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5611 goto dma_error;
5612
5613 len -= size;
5614 offset += size;
5615 count++;
5616 }
5617 }
5618
5619 segs = skb_shinfo(skb)->gso_segs ? : 1;
5620 /* multiply data chunks by size of headers */
5621 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5622
5623 tx_ring->buffer_info[i].skb = skb;
5624 tx_ring->buffer_info[i].segs = segs;
5625 tx_ring->buffer_info[i].bytecount = bytecount;
5626 tx_ring->buffer_info[first].next_to_watch = i;
5627
5628 return count;
5629
5630dma_error:
5631 dev_err(&pdev->dev, "Tx DMA map failed\n");
5632 buffer_info->dma = 0;
5633 if (count)
5634 count--;
5635
5636 while (count--) {
5637 if (i == 0)
5638 i += tx_ring->count;
5639 i--;
5640 buffer_info = &tx_ring->buffer_info[i];
5641 e1000_put_txbuf(tx_ring, buffer_info, true);
5642 }
5643
5644 return 0;
5645}
5646
5647static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
5648{
5649 struct e1000_adapter *adapter = tx_ring->adapter;
5650 struct e1000_tx_desc *tx_desc = NULL;
5651 struct e1000_buffer *buffer_info;
5652 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5653 unsigned int i;
5654
5655 if (tx_flags & E1000_TX_FLAGS_TSO) {
5656 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
5657 E1000_TXD_CMD_TSE;
5658 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5659
5660 if (tx_flags & E1000_TX_FLAGS_IPV4)
5661 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5662 }
5663
5664 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5665 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5666 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5667 }
5668
5669 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5670 txd_lower |= E1000_TXD_CMD_VLE;
5671 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5672 }
5673
5674 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5675 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5676
5677 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5678 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5679 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5680 }
5681
5682 i = tx_ring->next_to_use;
5683
5684 do {
5685 buffer_info = &tx_ring->buffer_info[i];
5686 tx_desc = E1000_TX_DESC(*tx_ring, i);
5687 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
5688 tx_desc->lower.data = cpu_to_le32(txd_lower |
5689 buffer_info->length);
5690 tx_desc->upper.data = cpu_to_le32(txd_upper);
5691
5692 i++;
5693 if (i == tx_ring->count)
5694 i = 0;
5695 } while (--count > 0);
5696
5697 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5698
5699 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5700 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5701 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5702
5703 /* Force memory writes to complete before letting h/w
5704 * know there are new descriptors to fetch. (Only
5705 * applicable for weak-ordered memory model archs,
5706 * such as IA-64).
5707 */
5708 wmb();
5709
5710 tx_ring->next_to_use = i;
5711}
5712
5713#define MINIMUM_DHCP_PACKET_SIZE 282
5714static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5715 struct sk_buff *skb)
5716{
5717 struct e1000_hw *hw = &adapter->hw;
5718 u16 length, offset;
5719
5720 if (skb_vlan_tag_present(skb) &&
5721 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5722 (adapter->hw.mng_cookie.status &
5723 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5724 return 0;
5725
5726 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5727 return 0;
5728
5729 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
5730 return 0;
5731
5732 {
5733 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
5734 struct udphdr *udp;
5735
5736 if (ip->protocol != IPPROTO_UDP)
5737 return 0;
5738
5739 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5740 if (ntohs(udp->dest) != 67)
5741 return 0;
5742
5743 offset = (u8 *)udp + 8 - skb->data;
5744 length = skb->len - offset;
5745 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5746 }
5747
5748 return 0;
5749}
5750
5751static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5752{
5753 struct e1000_adapter *adapter = tx_ring->adapter;
5754
5755 netif_stop_queue(adapter->netdev);
5756 /* Herbert's original patch had:
5757 * smp_mb__after_netif_stop_queue();
5758 * but since that doesn't exist yet, just open code it.
5759 */
5760 smp_mb();
5761
5762 /* We need to check again in a case another CPU has just
5763 * made room available.
5764 */
5765 if (e1000_desc_unused(tx_ring) < size)
5766 return -EBUSY;
5767
5768 /* A reprieve! */
5769 netif_start_queue(adapter->netdev);
5770 ++adapter->restart_queue;
5771 return 0;
5772}
5773
5774static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5775{
5776 BUG_ON(size > tx_ring->count);
5777
5778 if (e1000_desc_unused(tx_ring) >= size)
5779 return 0;
5780 return __e1000_maybe_stop_tx(tx_ring, size);
5781}
5782
5783static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5784 struct net_device *netdev)
5785{
5786 struct e1000_adapter *adapter = netdev_priv(netdev);
5787 struct e1000_ring *tx_ring = adapter->tx_ring;
5788 unsigned int first;
5789 unsigned int tx_flags = 0;
5790 unsigned int len = skb_headlen(skb);
5791 unsigned int nr_frags;
5792 unsigned int mss;
5793 int count = 0;
5794 int tso;
5795 unsigned int f;
5796 __be16 protocol = vlan_get_protocol(skb);
5797
5798 if (test_bit(__E1000_DOWN, &adapter->state)) {
5799 dev_kfree_skb_any(skb);
5800 return NETDEV_TX_OK;
5801 }
5802
5803 if (skb->len <= 0) {
5804 dev_kfree_skb_any(skb);
5805 return NETDEV_TX_OK;
5806 }
5807
5808 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5809 * pad skb in order to meet this minimum size requirement
5810 */
5811 if (skb_put_padto(skb, 17))
5812 return NETDEV_TX_OK;
5813
5814 mss = skb_shinfo(skb)->gso_size;
5815 if (mss) {
5816 u8 hdr_len;
5817
5818 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5819 * points to just header, pull a few bytes of payload from
5820 * frags into skb->data
5821 */
5822 hdr_len = skb_tcp_all_headers(skb);
5823 /* we do this workaround for ES2LAN, but it is un-necessary,
5824 * avoiding it could save a lot of cycles
5825 */
5826 if (skb->data_len && (hdr_len == len)) {
5827 unsigned int pull_size;
5828
5829 pull_size = min_t(unsigned int, 4, skb->data_len);
5830 if (!__pskb_pull_tail(skb, pull_size)) {
5831 e_err("__pskb_pull_tail failed.\n");
5832 dev_kfree_skb_any(skb);
5833 return NETDEV_TX_OK;
5834 }
5835 len = skb_headlen(skb);
5836 }
5837 }
5838
5839 /* reserve a descriptor for the offload context */
5840 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5841 count++;
5842 count++;
5843
5844 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
5845
5846 nr_frags = skb_shinfo(skb)->nr_frags;
5847 for (f = 0; f < nr_frags; f++)
5848 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5849 adapter->tx_fifo_limit);
5850
5851 if (adapter->hw.mac.tx_pkt_filtering)
5852 e1000_transfer_dhcp_info(adapter, skb);
5853
5854 /* need: count + 2 desc gap to keep tail from touching
5855 * head, otherwise try next time
5856 */
5857 if (e1000_maybe_stop_tx(tx_ring, count + 2))
5858 return NETDEV_TX_BUSY;
5859
5860 if (skb_vlan_tag_present(skb)) {
5861 tx_flags |= E1000_TX_FLAGS_VLAN;
5862 tx_flags |= (skb_vlan_tag_get(skb) <<
5863 E1000_TX_FLAGS_VLAN_SHIFT);
5864 }
5865
5866 first = tx_ring->next_to_use;
5867
5868 tso = e1000_tso(tx_ring, skb, protocol);
5869 if (tso < 0) {
5870 dev_kfree_skb_any(skb);
5871 return NETDEV_TX_OK;
5872 }
5873
5874 if (tso)
5875 tx_flags |= E1000_TX_FLAGS_TSO;
5876 else if (e1000_tx_csum(tx_ring, skb, protocol))
5877 tx_flags |= E1000_TX_FLAGS_CSUM;
5878
5879 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5880 * 82571 hardware supports TSO capabilities for IPv6 as well...
5881 * no longer assume, we must.
5882 */
5883 if (protocol == htons(ETH_P_IP))
5884 tx_flags |= E1000_TX_FLAGS_IPV4;
5885
5886 if (unlikely(skb->no_fcs))
5887 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5888
5889 /* if count is 0 then mapping error has occurred */
5890 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5891 nr_frags);
5892 if (count) {
5893 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5894 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) {
5895 if (!adapter->tx_hwtstamp_skb) {
5896 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5897 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5898 adapter->tx_hwtstamp_skb = skb_get(skb);
5899 adapter->tx_hwtstamp_start = jiffies;
5900 schedule_work(&adapter->tx_hwtstamp_work);
5901 } else {
5902 adapter->tx_hwtstamp_skipped++;
5903 }
5904 }
5905
5906 skb_tx_timestamp(skb);
5907
5908 netdev_sent_queue(netdev, skb->len);
5909 e1000_tx_queue(tx_ring, tx_flags, count);
5910 /* Make sure there is space in the ring for the next send. */
5911 e1000_maybe_stop_tx(tx_ring,
5912 ((MAX_SKB_FRAGS + 1) *
5913 DIV_ROUND_UP(PAGE_SIZE,
5914 adapter->tx_fifo_limit) + 4));
5915
5916 if (!netdev_xmit_more() ||
5917 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) {
5918 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
5919 e1000e_update_tdt_wa(tx_ring,
5920 tx_ring->next_to_use);
5921 else
5922 writel(tx_ring->next_to_use, tx_ring->tail);
5923 }
5924 } else {
5925 dev_kfree_skb_any(skb);
5926 tx_ring->buffer_info[first].time_stamp = 0;
5927 tx_ring->next_to_use = first;
5928 }
5929
5930 return NETDEV_TX_OK;
5931}
5932
5933/**
5934 * e1000_tx_timeout - Respond to a Tx Hang
5935 * @netdev: network interface device structure
5936 * @txqueue: index of the hung queue (unused)
5937 **/
5938static void e1000_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
5939{
5940 struct e1000_adapter *adapter = netdev_priv(netdev);
5941
5942 /* Do the reset outside of interrupt context */
5943 adapter->tx_timeout_count++;
5944 schedule_work(&adapter->reset_task);
5945}
5946
5947static void e1000_reset_task(struct work_struct *work)
5948{
5949 struct e1000_adapter *adapter;
5950 adapter = container_of(work, struct e1000_adapter, reset_task);
5951
5952 rtnl_lock();
5953 /* don't run the task if already down */
5954 if (test_bit(__E1000_DOWN, &adapter->state)) {
5955 rtnl_unlock();
5956 return;
5957 }
5958
5959 if (!(adapter->flags & FLAG_RESTART_NOW)) {
5960 e1000e_dump(adapter);
5961 e_err("Reset adapter unexpectedly\n");
5962 }
5963 e1000e_reinit_locked(adapter);
5964 rtnl_unlock();
5965}
5966
5967/**
5968 * e1000e_get_stats64 - Get System Network Statistics
5969 * @netdev: network interface device structure
5970 * @stats: rtnl_link_stats64 pointer
5971 *
5972 * Returns the address of the device statistics structure.
5973 **/
5974void e1000e_get_stats64(struct net_device *netdev,
5975 struct rtnl_link_stats64 *stats)
5976{
5977 struct e1000_adapter *adapter = netdev_priv(netdev);
5978
5979 spin_lock(&adapter->stats64_lock);
5980 e1000e_update_stats(adapter);
5981 /* Fill out the OS statistics structure */
5982 stats->rx_bytes = adapter->stats.gorc;
5983 stats->rx_packets = adapter->stats.gprc;
5984 stats->tx_bytes = adapter->stats.gotc;
5985 stats->tx_packets = adapter->stats.gptc;
5986 stats->multicast = adapter->stats.mprc;
5987 stats->collisions = adapter->stats.colc;
5988
5989 /* Rx Errors */
5990
5991 /* RLEC on some newer hardware can be incorrect so build
5992 * our own version based on RUC and ROC
5993 */
5994 stats->rx_errors = adapter->stats.rxerrc +
5995 adapter->stats.crcerrs + adapter->stats.algnerrc +
5996 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5997 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
5998 stats->rx_crc_errors = adapter->stats.crcerrs;
5999 stats->rx_frame_errors = adapter->stats.algnerrc;
6000 stats->rx_missed_errors = adapter->stats.mpc;
6001
6002 /* Tx Errors */
6003 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
6004 stats->tx_aborted_errors = adapter->stats.ecol;
6005 stats->tx_window_errors = adapter->stats.latecol;
6006 stats->tx_carrier_errors = adapter->stats.tncrs;
6007
6008 /* Tx Dropped needs to be maintained elsewhere */
6009
6010 spin_unlock(&adapter->stats64_lock);
6011}
6012
6013/**
6014 * e1000_change_mtu - Change the Maximum Transfer Unit
6015 * @netdev: network interface device structure
6016 * @new_mtu: new value for maximum frame size
6017 *
6018 * Returns 0 on success, negative on failure
6019 **/
6020static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
6021{
6022 struct e1000_adapter *adapter = netdev_priv(netdev);
6023 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6024
6025 /* Jumbo frame support */
6026 if ((new_mtu > ETH_DATA_LEN) &&
6027 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
6028 e_err("Jumbo Frames not supported.\n");
6029 return -EINVAL;
6030 }
6031
6032 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6033 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
6034 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
6035 (new_mtu > ETH_DATA_LEN)) {
6036 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
6037 return -EINVAL;
6038 }
6039
6040 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
6041 usleep_range(1000, 1100);
6042 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
6043 adapter->max_frame_size = max_frame;
6044 netdev_dbg(netdev, "changing MTU from %d to %d\n",
6045 netdev->mtu, new_mtu);
6046 WRITE_ONCE(netdev->mtu, new_mtu);
6047
6048 pm_runtime_get_sync(netdev->dev.parent);
6049
6050 if (netif_running(netdev))
6051 e1000e_down(adapter, true);
6052
6053 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
6054 * means we reserve 2 more, this pushes us to allocate from the next
6055 * larger slab size.
6056 * i.e. RXBUFFER_2048 --> size-4096 slab
6057 * However with the new *_jumbo_rx* routines, jumbo receives will use
6058 * fragmented skbs
6059 */
6060
6061 if (max_frame <= 2048)
6062 adapter->rx_buffer_len = 2048;
6063 else
6064 adapter->rx_buffer_len = 4096;
6065
6066 /* adjust allocation if LPE protects us, and we aren't using SBP */
6067 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN))
6068 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
6069
6070 if (netif_running(netdev))
6071 e1000e_up(adapter);
6072 else
6073 e1000e_reset(adapter);
6074
6075 pm_runtime_put_sync(netdev->dev.parent);
6076
6077 clear_bit(__E1000_RESETTING, &adapter->state);
6078
6079 return 0;
6080}
6081
6082static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
6083 int cmd)
6084{
6085 struct e1000_adapter *adapter = netdev_priv(netdev);
6086 struct mii_ioctl_data *data = if_mii(ifr);
6087
6088 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6089 return -EOPNOTSUPP;
6090
6091 switch (cmd) {
6092 case SIOCGMIIPHY:
6093 data->phy_id = adapter->hw.phy.addr;
6094 break;
6095 case SIOCGMIIREG:
6096 e1000_phy_read_status(adapter);
6097
6098 switch (data->reg_num & 0x1F) {
6099 case MII_BMCR:
6100 data->val_out = adapter->phy_regs.bmcr;
6101 break;
6102 case MII_BMSR:
6103 data->val_out = adapter->phy_regs.bmsr;
6104 break;
6105 case MII_PHYSID1:
6106 data->val_out = (adapter->hw.phy.id >> 16);
6107 break;
6108 case MII_PHYSID2:
6109 data->val_out = (adapter->hw.phy.id & 0xFFFF);
6110 break;
6111 case MII_ADVERTISE:
6112 data->val_out = adapter->phy_regs.advertise;
6113 break;
6114 case MII_LPA:
6115 data->val_out = adapter->phy_regs.lpa;
6116 break;
6117 case MII_EXPANSION:
6118 data->val_out = adapter->phy_regs.expansion;
6119 break;
6120 case MII_CTRL1000:
6121 data->val_out = adapter->phy_regs.ctrl1000;
6122 break;
6123 case MII_STAT1000:
6124 data->val_out = adapter->phy_regs.stat1000;
6125 break;
6126 case MII_ESTATUS:
6127 data->val_out = adapter->phy_regs.estatus;
6128 break;
6129 default:
6130 return -EIO;
6131 }
6132 break;
6133 case SIOCSMIIREG:
6134 default:
6135 return -EOPNOTSUPP;
6136 }
6137 return 0;
6138}
6139
6140/**
6141 * e1000e_hwtstamp_set - control hardware time stamping
6142 * @netdev: network interface device structure
6143 * @ifr: interface request
6144 *
6145 * Outgoing time stamping can be enabled and disabled. Play nice and
6146 * disable it when requested, although it shouldn't cause any overhead
6147 * when no packet needs it. At most one packet in the queue may be
6148 * marked for time stamping, otherwise it would be impossible to tell
6149 * for sure to which packet the hardware time stamp belongs.
6150 *
6151 * Incoming time stamping has to be configured via the hardware filters.
6152 * Not all combinations are supported, in particular event type has to be
6153 * specified. Matching the kind of event packet is not supported, with the
6154 * exception of "all V2 events regardless of level 2 or 4".
6155 **/
6156static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
6157{
6158 struct e1000_adapter *adapter = netdev_priv(netdev);
6159 struct hwtstamp_config config;
6160 int ret_val;
6161
6162 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
6163 return -EFAULT;
6164
6165 ret_val = e1000e_config_hwtstamp(adapter, &config);
6166 if (ret_val)
6167 return ret_val;
6168
6169 switch (config.rx_filter) {
6170 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6171 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6172 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6173 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6174 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6175 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6176 /* With V2 type filters which specify a Sync or Delay Request,
6177 * Path Delay Request/Response messages are also time stamped
6178 * by hardware so notify the caller the requested packets plus
6179 * some others are time stamped.
6180 */
6181 config.rx_filter = HWTSTAMP_FILTER_SOME;
6182 break;
6183 default:
6184 break;
6185 }
6186
6187 return copy_to_user(ifr->ifr_data, &config,
6188 sizeof(config)) ? -EFAULT : 0;
6189}
6190
6191static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
6192{
6193 struct e1000_adapter *adapter = netdev_priv(netdev);
6194
6195 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config,
6196 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0;
6197}
6198
6199static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6200{
6201 switch (cmd) {
6202 case SIOCGMIIPHY:
6203 case SIOCGMIIREG:
6204 case SIOCSMIIREG:
6205 return e1000_mii_ioctl(netdev, ifr, cmd);
6206 case SIOCSHWTSTAMP:
6207 return e1000e_hwtstamp_set(netdev, ifr);
6208 case SIOCGHWTSTAMP:
6209 return e1000e_hwtstamp_get(netdev, ifr);
6210 default:
6211 return -EOPNOTSUPP;
6212 }
6213}
6214
6215static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
6216{
6217 struct e1000_hw *hw = &adapter->hw;
6218 u32 i, mac_reg, wuc;
6219 u16 phy_reg, wuc_enable;
6220 int retval;
6221
6222 /* copy MAC RARs to PHY RARs */
6223 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
6224
6225 retval = hw->phy.ops.acquire(hw);
6226 if (retval) {
6227 e_err("Could not acquire PHY\n");
6228 return retval;
6229 }
6230
6231 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
6232 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6233 if (retval)
6234 goto release;
6235
6236 /* copy MAC MTA to PHY MTA - only needed for pchlan */
6237 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
6238 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
6239 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
6240 (u16)(mac_reg & 0xFFFF));
6241 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
6242 (u16)((mac_reg >> 16) & 0xFFFF));
6243 }
6244
6245 /* configure PHY Rx Control register */
6246 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
6247 mac_reg = er32(RCTL);
6248 if (mac_reg & E1000_RCTL_UPE)
6249 phy_reg |= BM_RCTL_UPE;
6250 if (mac_reg & E1000_RCTL_MPE)
6251 phy_reg |= BM_RCTL_MPE;
6252 phy_reg &= ~(BM_RCTL_MO_MASK);
6253 if (mac_reg & E1000_RCTL_MO_3)
6254 phy_reg |= (FIELD_GET(E1000_RCTL_MO_3, mac_reg)
6255 << BM_RCTL_MO_SHIFT);
6256 if (mac_reg & E1000_RCTL_BAM)
6257 phy_reg |= BM_RCTL_BAM;
6258 if (mac_reg & E1000_RCTL_PMCF)
6259 phy_reg |= BM_RCTL_PMCF;
6260 mac_reg = er32(CTRL);
6261 if (mac_reg & E1000_CTRL_RFCE)
6262 phy_reg |= BM_RCTL_RFCE;
6263 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
6264
6265 wuc = E1000_WUC_PME_EN;
6266 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
6267 wuc |= E1000_WUC_APME;
6268
6269 /* enable PHY wakeup in MAC register */
6270 ew32(WUFC, wufc);
6271 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
6272 E1000_WUC_PME_STATUS | wuc));
6273
6274 /* configure and enable PHY wakeup in PHY registers */
6275 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
6276 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
6277
6278 /* activate PHY wakeup */
6279 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
6280 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6281 if (retval)
6282 e_err("Could not set PHY Host Wakeup bit\n");
6283release:
6284 hw->phy.ops.release(hw);
6285
6286 return retval;
6287}
6288
6289static void e1000e_flush_lpic(struct pci_dev *pdev)
6290{
6291 struct net_device *netdev = pci_get_drvdata(pdev);
6292 struct e1000_adapter *adapter = netdev_priv(netdev);
6293 struct e1000_hw *hw = &adapter->hw;
6294 u32 ret_val;
6295
6296 pm_runtime_get_sync(netdev->dev.parent);
6297
6298 ret_val = hw->phy.ops.acquire(hw);
6299 if (ret_val)
6300 goto fl_out;
6301
6302 pr_info("EEE TX LPI TIMER: %08X\n",
6303 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT);
6304
6305 hw->phy.ops.release(hw);
6306
6307fl_out:
6308 pm_runtime_put_sync(netdev->dev.parent);
6309}
6310
6311/* S0ix implementation */
6312static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter)
6313{
6314 struct e1000_hw *hw = &adapter->hw;
6315 u32 mac_data;
6316 u16 phy_data;
6317
6318 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID &&
6319 hw->mac.type >= e1000_pch_adp) {
6320 /* Request ME configure the device for S0ix */
6321 mac_data = er32(H2ME);
6322 mac_data |= E1000_H2ME_START_DPG;
6323 mac_data &= ~E1000_H2ME_EXIT_DPG;
6324 trace_e1000e_trace_mac_register(mac_data);
6325 ew32(H2ME, mac_data);
6326 } else {
6327 /* Request driver configure the device to S0ix */
6328 /* Disable the periodic inband message,
6329 * don't request PCIe clock in K1 page770_17[10:9] = 10b
6330 */
6331 e1e_rphy(hw, HV_PM_CTRL, &phy_data);
6332 phy_data &= ~HV_PM_CTRL_K1_CLK_REQ;
6333 phy_data |= BIT(10);
6334 e1e_wphy(hw, HV_PM_CTRL, phy_data);
6335
6336 /* Make sure we don't exit K1 every time a new packet arrives
6337 * 772_29[5] = 1 CS_Mode_Stay_In_K1
6338 */
6339 e1e_rphy(hw, I217_CGFREG, &phy_data);
6340 phy_data |= BIT(5);
6341 e1e_wphy(hw, I217_CGFREG, phy_data);
6342
6343 /* Change the MAC/PHY interface to SMBus
6344 * Force the SMBus in PHY page769_23[0] = 1
6345 * Force the SMBus in MAC CTRL_EXT[11] = 1
6346 */
6347 e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
6348 phy_data |= CV_SMB_CTRL_FORCE_SMBUS;
6349 e1e_wphy(hw, CV_SMB_CTRL, phy_data);
6350 mac_data = er32(CTRL_EXT);
6351 mac_data |= E1000_CTRL_EXT_FORCE_SMBUS;
6352 ew32(CTRL_EXT, mac_data);
6353
6354 /* DFT control: PHY bit: page769_20[0] = 1
6355 * page769_20[7] - PHY PLL stop
6356 * page769_20[8] - PHY go to the electrical idle
6357 * page769_20[9] - PHY serdes disable
6358 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1
6359 */
6360 e1e_rphy(hw, I82579_DFT_CTRL, &phy_data);
6361 phy_data |= BIT(0);
6362 phy_data |= BIT(7);
6363 phy_data |= BIT(8);
6364 phy_data |= BIT(9);
6365 e1e_wphy(hw, I82579_DFT_CTRL, phy_data);
6366
6367 mac_data = er32(EXTCNF_CTRL);
6368 mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
6369 ew32(EXTCNF_CTRL, mac_data);
6370
6371 /* Disable disconnected cable conditioning for Power Gating */
6372 mac_data = er32(DPGFR);
6373 mac_data |= BIT(2);
6374 ew32(DPGFR, mac_data);
6375
6376 /* Enable the Dynamic Clock Gating in the DMA and MAC */
6377 mac_data = er32(CTRL_EXT);
6378 mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN;
6379 ew32(CTRL_EXT, mac_data);
6380 }
6381
6382 /* Enable the Dynamic Power Gating in the MAC */
6383 mac_data = er32(FEXTNVM7);
6384 mac_data |= BIT(22);
6385 ew32(FEXTNVM7, mac_data);
6386
6387 /* Don't wake from dynamic Power Gating with clock request */
6388 mac_data = er32(FEXTNVM12);
6389 mac_data |= BIT(12);
6390 ew32(FEXTNVM12, mac_data);
6391
6392 /* Ungate PGCB clock */
6393 mac_data = er32(FEXTNVM9);
6394 mac_data &= ~BIT(28);
6395 ew32(FEXTNVM9, mac_data);
6396
6397 /* Enable K1 off to enable mPHY Power Gating */
6398 mac_data = er32(FEXTNVM6);
6399 mac_data |= BIT(31);
6400 ew32(FEXTNVM6, mac_data);
6401
6402 /* Enable mPHY power gating for any link and speed */
6403 mac_data = er32(FEXTNVM8);
6404 mac_data |= BIT(9);
6405 ew32(FEXTNVM8, mac_data);
6406
6407 /* No MAC DPG gating SLP_S0 in modern standby
6408 * Switch the logic of the lanphypc to use PMC counter
6409 */
6410 mac_data = er32(FEXTNVM5);
6411 mac_data |= BIT(7);
6412 ew32(FEXTNVM5, mac_data);
6413
6414 /* Disable the time synchronization clock */
6415 mac_data = er32(FEXTNVM7);
6416 mac_data |= BIT(31);
6417 mac_data &= ~BIT(0);
6418 ew32(FEXTNVM7, mac_data);
6419
6420 /* Dynamic Power Gating Enable */
6421 mac_data = er32(CTRL_EXT);
6422 mac_data |= BIT(3);
6423 ew32(CTRL_EXT, mac_data);
6424
6425 /* Check MAC Tx/Rx packet buffer pointers.
6426 * Reset MAC Tx/Rx packet buffer pointers to suppress any
6427 * pending traffic indication that would prevent power gating.
6428 */
6429 mac_data = er32(TDFH);
6430 if (mac_data)
6431 ew32(TDFH, 0);
6432 mac_data = er32(TDFT);
6433 if (mac_data)
6434 ew32(TDFT, 0);
6435 mac_data = er32(TDFHS);
6436 if (mac_data)
6437 ew32(TDFHS, 0);
6438 mac_data = er32(TDFTS);
6439 if (mac_data)
6440 ew32(TDFTS, 0);
6441 mac_data = er32(TDFPC);
6442 if (mac_data)
6443 ew32(TDFPC, 0);
6444 mac_data = er32(RDFH);
6445 if (mac_data)
6446 ew32(RDFH, 0);
6447 mac_data = er32(RDFT);
6448 if (mac_data)
6449 ew32(RDFT, 0);
6450 mac_data = er32(RDFHS);
6451 if (mac_data)
6452 ew32(RDFHS, 0);
6453 mac_data = er32(RDFTS);
6454 if (mac_data)
6455 ew32(RDFTS, 0);
6456 mac_data = er32(RDFPC);
6457 if (mac_data)
6458 ew32(RDFPC, 0);
6459}
6460
6461static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter)
6462{
6463 struct e1000_hw *hw = &adapter->hw;
6464 bool firmware_bug = false;
6465 u32 mac_data;
6466 u16 phy_data;
6467 u32 i = 0;
6468
6469 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID &&
6470 hw->mac.type >= e1000_pch_adp) {
6471 /* Keep the GPT clock enabled for CSME */
6472 mac_data = er32(FEXTNVM);
6473 mac_data |= BIT(3);
6474 ew32(FEXTNVM, mac_data);
6475 /* Request ME unconfigure the device from S0ix */
6476 mac_data = er32(H2ME);
6477 mac_data &= ~E1000_H2ME_START_DPG;
6478 mac_data |= E1000_H2ME_EXIT_DPG;
6479 trace_e1000e_trace_mac_register(mac_data);
6480 ew32(H2ME, mac_data);
6481
6482 /* Poll up to 2.5 seconds for ME to unconfigure DPG.
6483 * If this takes more than 1 second, show a warning indicating a
6484 * firmware bug
6485 */
6486 while (!(er32(EXFWSM) & E1000_EXFWSM_DPG_EXIT_DONE)) {
6487 if (i > 100 && !firmware_bug)
6488 firmware_bug = true;
6489
6490 if (i++ == 250) {
6491 e_dbg("Timeout (firmware bug): %d msec\n",
6492 i * 10);
6493 break;
6494 }
6495
6496 usleep_range(10000, 11000);
6497 }
6498 if (firmware_bug)
6499 e_warn("DPG_EXIT_DONE took %d msec. This is a firmware bug\n",
6500 i * 10);
6501 else
6502 e_dbg("DPG_EXIT_DONE cleared after %d msec\n", i * 10);
6503 } else {
6504 /* Request driver unconfigure the device from S0ix */
6505
6506 /* Cancel disable disconnected cable conditioning
6507 * for Power Gating
6508 */
6509 mac_data = er32(DPGFR);
6510 mac_data &= ~BIT(2);
6511 ew32(DPGFR, mac_data);
6512
6513 /* Disable the Dynamic Clock Gating in the DMA and MAC */
6514 mac_data = er32(CTRL_EXT);
6515 mac_data &= 0xFFF7FFFF;
6516 ew32(CTRL_EXT, mac_data);
6517
6518 /* Enable the periodic inband message,
6519 * Request PCIe clock in K1 page770_17[10:9] =01b
6520 */
6521 e1e_rphy(hw, HV_PM_CTRL, &phy_data);
6522 phy_data &= 0xFBFF;
6523 phy_data |= HV_PM_CTRL_K1_CLK_REQ;
6524 e1e_wphy(hw, HV_PM_CTRL, phy_data);
6525
6526 /* Return back configuration
6527 * 772_29[5] = 0 CS_Mode_Stay_In_K1
6528 */
6529 e1e_rphy(hw, I217_CGFREG, &phy_data);
6530 phy_data &= 0xFFDF;
6531 e1e_wphy(hw, I217_CGFREG, phy_data);
6532
6533 /* Change the MAC/PHY interface to Kumeran
6534 * Unforce the SMBus in PHY page769_23[0] = 0
6535 * Unforce the SMBus in MAC CTRL_EXT[11] = 0
6536 */
6537 e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
6538 phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS;
6539 e1e_wphy(hw, CV_SMB_CTRL, phy_data);
6540 mac_data = er32(CTRL_EXT);
6541 mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS;
6542 ew32(CTRL_EXT, mac_data);
6543 }
6544
6545 /* Disable Dynamic Power Gating */
6546 mac_data = er32(CTRL_EXT);
6547 mac_data &= 0xFFFFFFF7;
6548 ew32(CTRL_EXT, mac_data);
6549
6550 /* Enable the time synchronization clock */
6551 mac_data = er32(FEXTNVM7);
6552 mac_data &= ~BIT(31);
6553 mac_data |= BIT(0);
6554 ew32(FEXTNVM7, mac_data);
6555
6556 /* Disable the Dynamic Power Gating in the MAC */
6557 mac_data = er32(FEXTNVM7);
6558 mac_data &= 0xFFBFFFFF;
6559 ew32(FEXTNVM7, mac_data);
6560
6561 /* Disable mPHY power gating for any link and speed */
6562 mac_data = er32(FEXTNVM8);
6563 mac_data &= ~BIT(9);
6564 ew32(FEXTNVM8, mac_data);
6565
6566 /* Disable K1 off */
6567 mac_data = er32(FEXTNVM6);
6568 mac_data &= ~BIT(31);
6569 ew32(FEXTNVM6, mac_data);
6570
6571 /* Disable Ungate PGCB clock */
6572 mac_data = er32(FEXTNVM9);
6573 mac_data |= BIT(28);
6574 ew32(FEXTNVM9, mac_data);
6575
6576 /* Cancel not waking from dynamic
6577 * Power Gating with clock request
6578 */
6579 mac_data = er32(FEXTNVM12);
6580 mac_data &= ~BIT(12);
6581 ew32(FEXTNVM12, mac_data);
6582
6583 /* Revert the lanphypc logic to use the internal Gbe counter
6584 * and not the PMC counter
6585 */
6586 mac_data = er32(FEXTNVM5);
6587 mac_data &= 0xFFFFFF7F;
6588 ew32(FEXTNVM5, mac_data);
6589}
6590
6591static int e1000e_pm_freeze(struct device *dev)
6592{
6593 struct net_device *netdev = dev_get_drvdata(dev);
6594 struct e1000_adapter *adapter = netdev_priv(netdev);
6595 bool present;
6596
6597 rtnl_lock();
6598
6599 present = netif_device_present(netdev);
6600 netif_device_detach(netdev);
6601
6602 if (present && netif_running(netdev)) {
6603 int count = E1000_CHECK_RESET_COUNT;
6604
6605 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6606 usleep_range(10000, 11000);
6607
6608 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6609
6610 /* Quiesce the device without resetting the hardware */
6611 e1000e_down(adapter, false);
6612 e1000_free_irq(adapter);
6613 }
6614 rtnl_unlock();
6615
6616 e1000e_reset_interrupt_capability(adapter);
6617
6618 /* Allow time for pending master requests to run */
6619 e1000e_disable_pcie_master(&adapter->hw);
6620
6621 return 0;
6622}
6623
6624static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
6625{
6626 struct net_device *netdev = pci_get_drvdata(pdev);
6627 struct e1000_adapter *adapter = netdev_priv(netdev);
6628 struct e1000_hw *hw = &adapter->hw;
6629 u32 ctrl, ctrl_ext, rctl, status, wufc;
6630 int retval = 0;
6631
6632 /* Runtime suspend should only enable wakeup for link changes */
6633 if (runtime)
6634 wufc = E1000_WUFC_LNKC;
6635 else if (device_may_wakeup(&pdev->dev))
6636 wufc = adapter->wol;
6637 else
6638 wufc = 0;
6639
6640 status = er32(STATUS);
6641 if (status & E1000_STATUS_LU)
6642 wufc &= ~E1000_WUFC_LNKC;
6643
6644 if (wufc) {
6645 e1000_setup_rctl(adapter);
6646 e1000e_set_rx_mode(netdev);
6647
6648 /* turn on all-multi mode if wake on multicast is enabled */
6649 if (wufc & E1000_WUFC_MC) {
6650 rctl = er32(RCTL);
6651 rctl |= E1000_RCTL_MPE;
6652 ew32(RCTL, rctl);
6653 }
6654
6655 ctrl = er32(CTRL);
6656 ctrl |= E1000_CTRL_ADVD3WUC;
6657 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
6658 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
6659 ew32(CTRL, ctrl);
6660
6661 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
6662 adapter->hw.phy.media_type ==
6663 e1000_media_type_internal_serdes) {
6664 /* keep the laser running in D3 */
6665 ctrl_ext = er32(CTRL_EXT);
6666 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
6667 ew32(CTRL_EXT, ctrl_ext);
6668 }
6669
6670 if (!runtime)
6671 e1000e_power_up_phy(adapter);
6672
6673 if (adapter->flags & FLAG_IS_ICH)
6674 e1000_suspend_workarounds_ich8lan(&adapter->hw);
6675
6676 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6677 /* enable wakeup by the PHY */
6678 retval = e1000_init_phy_wakeup(adapter, wufc);
6679 if (retval) {
6680 e_err("Failed to enable wakeup\n");
6681 goto skip_phy_configurations;
6682 }
6683 } else {
6684 /* enable wakeup by the MAC */
6685 ew32(WUFC, wufc);
6686 ew32(WUC, E1000_WUC_PME_EN);
6687 }
6688 } else {
6689 ew32(WUC, 0);
6690 ew32(WUFC, 0);
6691
6692 e1000_power_down_phy(adapter);
6693 }
6694
6695 if (adapter->hw.phy.type == e1000_phy_igp_3) {
6696 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
6697 } else if (hw->mac.type >= e1000_pch_lpt) {
6698 if (wufc && !(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) {
6699 /* ULP does not support wake from unicast, multicast
6700 * or broadcast.
6701 */
6702 retval = e1000_enable_ulp_lpt_lp(hw, !runtime);
6703 if (retval) {
6704 e_err("Failed to enable ULP\n");
6705 goto skip_phy_configurations;
6706 }
6707 }
6708 }
6709
6710 /* Ensure that the appropriate bits are set in LPI_CTRL
6711 * for EEE in Sx
6712 */
6713 if ((hw->phy.type >= e1000_phy_i217) &&
6714 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) {
6715 u16 lpi_ctrl = 0;
6716
6717 retval = hw->phy.ops.acquire(hw);
6718 if (!retval) {
6719 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL,
6720 &lpi_ctrl);
6721 if (!retval) {
6722 if (adapter->eee_advert &
6723 hw->dev_spec.ich8lan.eee_lp_ability &
6724 I82579_EEE_100_SUPPORTED)
6725 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
6726 if (adapter->eee_advert &
6727 hw->dev_spec.ich8lan.eee_lp_ability &
6728 I82579_EEE_1000_SUPPORTED)
6729 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
6730
6731 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL,
6732 lpi_ctrl);
6733 }
6734 }
6735 hw->phy.ops.release(hw);
6736 }
6737
6738skip_phy_configurations:
6739 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6740 * would have already happened in close and is redundant.
6741 */
6742 e1000e_release_hw_control(adapter);
6743
6744 pci_clear_master(pdev);
6745
6746 /* The pci-e switch on some quad port adapters will report a
6747 * correctable error when the MAC transitions from D0 to D3. To
6748 * prevent this we need to mask off the correctable errors on the
6749 * downstream port of the pci-e switch.
6750 *
6751 * We don't have the associated upstream bridge while assigning
6752 * the PCI device into guest. For example, the KVM on power is
6753 * one of the cases.
6754 */
6755 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6756 struct pci_dev *us_dev = pdev->bus->self;
6757 u16 devctl;
6758
6759 if (!us_dev)
6760 return 0;
6761
6762 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6763 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6764 (devctl & ~PCI_EXP_DEVCTL_CERE));
6765
6766 pci_save_state(pdev);
6767 pci_prepare_to_sleep(pdev);
6768
6769 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
6770 }
6771
6772 return 0;
6773}
6774
6775/**
6776 * __e1000e_disable_aspm - Disable ASPM states
6777 * @pdev: pointer to PCI device struct
6778 * @state: bit-mask of ASPM states to disable
6779 * @locked: indication if this context holds pci_bus_sem locked.
6780 *
6781 * Some devices *must* have certain ASPM states disabled per hardware errata.
6782 **/
6783static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked)
6784{
6785 struct pci_dev *parent = pdev->bus->self;
6786 u16 aspm_dis_mask = 0;
6787 u16 pdev_aspmc, parent_aspmc;
6788
6789 switch (state) {
6790 case PCIE_LINK_STATE_L0S:
6791 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6792 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6793 fallthrough; /* can't have L1 without L0s */
6794 case PCIE_LINK_STATE_L1:
6795 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6796 break;
6797 default:
6798 return;
6799 }
6800
6801 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6802 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6803
6804 if (parent) {
6805 pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6806 &parent_aspmc);
6807 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6808 }
6809
6810 /* Nothing to do if the ASPM states to be disabled already are */
6811 if (!(pdev_aspmc & aspm_dis_mask) &&
6812 (!parent || !(parent_aspmc & aspm_dis_mask)))
6813 return;
6814
6815 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6816 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6817 "L0s" : "",
6818 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6819 "L1" : "");
6820
6821#ifdef CONFIG_PCIEASPM
6822 if (locked)
6823 pci_disable_link_state_locked(pdev, state);
6824 else
6825 pci_disable_link_state(pdev, state);
6826
6827 /* Double-check ASPM control. If not disabled by the above, the
6828 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6829 * not enabled); override by writing PCI config space directly.
6830 */
6831 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6832 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6833
6834 if (!(aspm_dis_mask & pdev_aspmc))
6835 return;
6836#endif
6837
6838 /* Both device and parent should have the same ASPM setting.
6839 * Disable ASPM in downstream component first and then upstream.
6840 */
6841 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6842
6843 if (parent)
6844 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6845 aspm_dis_mask);
6846}
6847
6848/**
6849 * e1000e_disable_aspm - Disable ASPM states.
6850 * @pdev: pointer to PCI device struct
6851 * @state: bit-mask of ASPM states to disable
6852 *
6853 * This function acquires the pci_bus_sem!
6854 * Some devices *must* have certain ASPM states disabled per hardware errata.
6855 **/
6856static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6857{
6858 __e1000e_disable_aspm(pdev, state, 0);
6859}
6860
6861/**
6862 * e1000e_disable_aspm_locked - Disable ASPM states.
6863 * @pdev: pointer to PCI device struct
6864 * @state: bit-mask of ASPM states to disable
6865 *
6866 * This function must be called with pci_bus_sem acquired!
6867 * Some devices *must* have certain ASPM states disabled per hardware errata.
6868 **/
6869static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state)
6870{
6871 __e1000e_disable_aspm(pdev, state, 1);
6872}
6873
6874static int e1000e_pm_thaw(struct device *dev)
6875{
6876 struct net_device *netdev = dev_get_drvdata(dev);
6877 struct e1000_adapter *adapter = netdev_priv(netdev);
6878 int rc = 0;
6879
6880 e1000e_set_interrupt_capability(adapter);
6881
6882 rtnl_lock();
6883 if (netif_running(netdev)) {
6884 rc = e1000_request_irq(adapter);
6885 if (rc)
6886 goto err_irq;
6887
6888 e1000e_up(adapter);
6889 }
6890
6891 netif_device_attach(netdev);
6892err_irq:
6893 rtnl_unlock();
6894
6895 return rc;
6896}
6897
6898static int __e1000_resume(struct pci_dev *pdev)
6899{
6900 struct net_device *netdev = pci_get_drvdata(pdev);
6901 struct e1000_adapter *adapter = netdev_priv(netdev);
6902 struct e1000_hw *hw = &adapter->hw;
6903 u16 aspm_disable_flag = 0;
6904
6905 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6906 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6907 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6908 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6909 if (aspm_disable_flag)
6910 e1000e_disable_aspm(pdev, aspm_disable_flag);
6911
6912 pci_set_master(pdev);
6913
6914 if (hw->mac.type >= e1000_pch2lan)
6915 e1000_resume_workarounds_pchlan(&adapter->hw);
6916
6917 e1000e_power_up_phy(adapter);
6918
6919 /* report the system wakeup cause from S3/S4 */
6920 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6921 u16 phy_data;
6922
6923 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6924 if (phy_data) {
6925 e_info("PHY Wakeup cause - %s\n",
6926 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6927 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6928 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6929 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6930 phy_data & E1000_WUS_LNKC ?
6931 "Link Status Change" : "other");
6932 }
6933 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6934 } else {
6935 u32 wus = er32(WUS);
6936
6937 if (wus) {
6938 e_info("MAC Wakeup cause - %s\n",
6939 wus & E1000_WUS_EX ? "Unicast Packet" :
6940 wus & E1000_WUS_MC ? "Multicast Packet" :
6941 wus & E1000_WUS_BC ? "Broadcast Packet" :
6942 wus & E1000_WUS_MAG ? "Magic Packet" :
6943 wus & E1000_WUS_LNKC ? "Link Status Change" :
6944 "other");
6945 }
6946 ew32(WUS, ~0);
6947 }
6948
6949 e1000e_reset(adapter);
6950
6951 e1000_init_manageability_pt(adapter);
6952
6953 /* If the controller has AMT, do not set DRV_LOAD until the interface
6954 * is up. For all other cases, let the f/w know that the h/w is now
6955 * under the control of the driver.
6956 */
6957 if (!(adapter->flags & FLAG_HAS_AMT))
6958 e1000e_get_hw_control(adapter);
6959
6960 return 0;
6961}
6962
6963static int e1000e_pm_prepare(struct device *dev)
6964{
6965 return pm_runtime_suspended(dev) &&
6966 pm_suspend_via_firmware();
6967}
6968
6969static int e1000e_pm_suspend(struct device *dev)
6970{
6971 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6972 struct e1000_adapter *adapter = netdev_priv(netdev);
6973 struct pci_dev *pdev = to_pci_dev(dev);
6974 int rc;
6975
6976 e1000e_flush_lpic(pdev);
6977
6978 e1000e_pm_freeze(dev);
6979
6980 rc = __e1000_shutdown(pdev, false);
6981 if (!rc) {
6982 /* Introduce S0ix implementation */
6983 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
6984 e1000e_s0ix_entry_flow(adapter);
6985 }
6986
6987 return 0;
6988}
6989
6990static int e1000e_pm_resume(struct device *dev)
6991{
6992 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6993 struct e1000_adapter *adapter = netdev_priv(netdev);
6994 struct pci_dev *pdev = to_pci_dev(dev);
6995 int rc;
6996
6997 /* Introduce S0ix implementation */
6998 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
6999 e1000e_s0ix_exit_flow(adapter);
7000
7001 rc = __e1000_resume(pdev);
7002 if (rc)
7003 return rc;
7004
7005 return e1000e_pm_thaw(dev);
7006}
7007
7008static __maybe_unused int e1000e_pm_runtime_idle(struct device *dev)
7009{
7010 struct net_device *netdev = dev_get_drvdata(dev);
7011 struct e1000_adapter *adapter = netdev_priv(netdev);
7012 u16 eee_lp;
7013
7014 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability;
7015
7016 if (!e1000e_has_link(adapter)) {
7017 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp;
7018 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);
7019 }
7020
7021 return -EBUSY;
7022}
7023
7024static int e1000e_pm_runtime_resume(struct device *dev)
7025{
7026 struct pci_dev *pdev = to_pci_dev(dev);
7027 struct net_device *netdev = pci_get_drvdata(pdev);
7028 struct e1000_adapter *adapter = netdev_priv(netdev);
7029 int rc;
7030
7031 pdev->pme_poll = true;
7032
7033 rc = __e1000_resume(pdev);
7034 if (rc)
7035 return rc;
7036
7037 if (netdev->flags & IFF_UP)
7038 e1000e_up(adapter);
7039
7040 return rc;
7041}
7042
7043static int e1000e_pm_runtime_suspend(struct device *dev)
7044{
7045 struct pci_dev *pdev = to_pci_dev(dev);
7046 struct net_device *netdev = pci_get_drvdata(pdev);
7047 struct e1000_adapter *adapter = netdev_priv(netdev);
7048
7049 if (netdev->flags & IFF_UP) {
7050 int count = E1000_CHECK_RESET_COUNT;
7051
7052 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
7053 usleep_range(10000, 11000);
7054
7055 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
7056
7057 /* Down the device without resetting the hardware */
7058 e1000e_down(adapter, false);
7059 }
7060
7061 if (__e1000_shutdown(pdev, true)) {
7062 e1000e_pm_runtime_resume(dev);
7063 return -EBUSY;
7064 }
7065
7066 return 0;
7067}
7068
7069static void e1000_shutdown(struct pci_dev *pdev)
7070{
7071 e1000e_flush_lpic(pdev);
7072
7073 e1000e_pm_freeze(&pdev->dev);
7074
7075 __e1000_shutdown(pdev, false);
7076}
7077
7078#ifdef CONFIG_NET_POLL_CONTROLLER
7079
7080static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
7081{
7082 struct net_device *netdev = data;
7083 struct e1000_adapter *adapter = netdev_priv(netdev);
7084
7085 if (adapter->msix_entries) {
7086 int vector, msix_irq;
7087
7088 vector = 0;
7089 msix_irq = adapter->msix_entries[vector].vector;
7090 if (disable_hardirq(msix_irq))
7091 e1000_intr_msix_rx(msix_irq, netdev);
7092 enable_irq(msix_irq);
7093
7094 vector++;
7095 msix_irq = adapter->msix_entries[vector].vector;
7096 if (disable_hardirq(msix_irq))
7097 e1000_intr_msix_tx(msix_irq, netdev);
7098 enable_irq(msix_irq);
7099
7100 vector++;
7101 msix_irq = adapter->msix_entries[vector].vector;
7102 if (disable_hardirq(msix_irq))
7103 e1000_msix_other(msix_irq, netdev);
7104 enable_irq(msix_irq);
7105 }
7106
7107 return IRQ_HANDLED;
7108}
7109
7110/**
7111 * e1000_netpoll
7112 * @netdev: network interface device structure
7113 *
7114 * Polling 'interrupt' - used by things like netconsole to send skbs
7115 * without having to re-enable interrupts. It's not called while
7116 * the interrupt routine is executing.
7117 */
7118static void e1000_netpoll(struct net_device *netdev)
7119{
7120 struct e1000_adapter *adapter = netdev_priv(netdev);
7121
7122 switch (adapter->int_mode) {
7123 case E1000E_INT_MODE_MSIX:
7124 e1000_intr_msix(adapter->pdev->irq, netdev);
7125 break;
7126 case E1000E_INT_MODE_MSI:
7127 if (disable_hardirq(adapter->pdev->irq))
7128 e1000_intr_msi(adapter->pdev->irq, netdev);
7129 enable_irq(adapter->pdev->irq);
7130 break;
7131 default: /* E1000E_INT_MODE_LEGACY */
7132 if (disable_hardirq(adapter->pdev->irq))
7133 e1000_intr(adapter->pdev->irq, netdev);
7134 enable_irq(adapter->pdev->irq);
7135 break;
7136 }
7137}
7138#endif
7139
7140/**
7141 * e1000_io_error_detected - called when PCI error is detected
7142 * @pdev: Pointer to PCI device
7143 * @state: The current pci connection state
7144 *
7145 * This function is called after a PCI bus error affecting
7146 * this device has been detected.
7147 */
7148static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
7149 pci_channel_state_t state)
7150{
7151 e1000e_pm_freeze(&pdev->dev);
7152
7153 if (state == pci_channel_io_perm_failure)
7154 return PCI_ERS_RESULT_DISCONNECT;
7155
7156 pci_disable_device(pdev);
7157
7158 /* Request a slot reset. */
7159 return PCI_ERS_RESULT_NEED_RESET;
7160}
7161
7162/**
7163 * e1000_io_slot_reset - called after the pci bus has been reset.
7164 * @pdev: Pointer to PCI device
7165 *
7166 * Restart the card from scratch, as if from a cold-boot. Implementation
7167 * resembles the first-half of the e1000e_pm_resume routine.
7168 */
7169static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
7170{
7171 struct net_device *netdev = pci_get_drvdata(pdev);
7172 struct e1000_adapter *adapter = netdev_priv(netdev);
7173 struct e1000_hw *hw = &adapter->hw;
7174 u16 aspm_disable_flag = 0;
7175 int err;
7176 pci_ers_result_t result;
7177
7178 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
7179 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7180 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
7181 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7182 if (aspm_disable_flag)
7183 e1000e_disable_aspm_locked(pdev, aspm_disable_flag);
7184
7185 err = pci_enable_device_mem(pdev);
7186 if (err) {
7187 dev_err(&pdev->dev,
7188 "Cannot re-enable PCI device after reset.\n");
7189 result = PCI_ERS_RESULT_DISCONNECT;
7190 } else {
7191 pdev->state_saved = true;
7192 pci_restore_state(pdev);
7193 pci_set_master(pdev);
7194
7195 pci_enable_wake(pdev, PCI_D3hot, 0);
7196 pci_enable_wake(pdev, PCI_D3cold, 0);
7197
7198 e1000e_reset(adapter);
7199 ew32(WUS, ~0);
7200 result = PCI_ERS_RESULT_RECOVERED;
7201 }
7202
7203 return result;
7204}
7205
7206/**
7207 * e1000_io_resume - called when traffic can start flowing again.
7208 * @pdev: Pointer to PCI device
7209 *
7210 * This callback is called when the error recovery driver tells us that
7211 * its OK to resume normal operation. Implementation resembles the
7212 * second-half of the e1000e_pm_resume routine.
7213 */
7214static void e1000_io_resume(struct pci_dev *pdev)
7215{
7216 struct net_device *netdev = pci_get_drvdata(pdev);
7217 struct e1000_adapter *adapter = netdev_priv(netdev);
7218
7219 e1000_init_manageability_pt(adapter);
7220
7221 e1000e_pm_thaw(&pdev->dev);
7222
7223 /* If the controller has AMT, do not set DRV_LOAD until the interface
7224 * is up. For all other cases, let the f/w know that the h/w is now
7225 * under the control of the driver.
7226 */
7227 if (!(adapter->flags & FLAG_HAS_AMT))
7228 e1000e_get_hw_control(adapter);
7229}
7230
7231static void e1000_print_device_info(struct e1000_adapter *adapter)
7232{
7233 struct e1000_hw *hw = &adapter->hw;
7234 struct net_device *netdev = adapter->netdev;
7235 u32 ret_val;
7236 u8 pba_str[E1000_PBANUM_LENGTH];
7237
7238 /* print bus type/speed/width info */
7239 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
7240 /* bus width */
7241 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
7242 "Width x1"),
7243 /* MAC address */
7244 netdev->dev_addr);
7245 e_info("Intel(R) PRO/%s Network Connection\n",
7246 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
7247 ret_val = e1000_read_pba_string_generic(hw, pba_str,
7248 E1000_PBANUM_LENGTH);
7249 if (ret_val)
7250 strscpy((char *)pba_str, "Unknown", sizeof(pba_str));
7251 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
7252 hw->mac.type, hw->phy.type, pba_str);
7253}
7254
7255static void e1000_eeprom_checks(struct e1000_adapter *adapter)
7256{
7257 struct e1000_hw *hw = &adapter->hw;
7258 int ret_val;
7259 u16 buf = 0;
7260
7261 if (hw->mac.type != e1000_82573)
7262 return;
7263
7264 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
7265 le16_to_cpus(&buf);
7266 if (!ret_val && (!(buf & BIT(0)))) {
7267 /* Deep Smart Power Down (DSPD) */
7268 dev_warn(&adapter->pdev->dev,
7269 "Warning: detected DSPD enabled in EEPROM\n");
7270 }
7271}
7272
7273static netdev_features_t e1000_fix_features(struct net_device *netdev,
7274 netdev_features_t features)
7275{
7276 struct e1000_adapter *adapter = netdev_priv(netdev);
7277 struct e1000_hw *hw = &adapter->hw;
7278
7279 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
7280 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN))
7281 features &= ~NETIF_F_RXFCS;
7282
7283 /* Since there is no support for separate Rx/Tx vlan accel
7284 * enable/disable make sure Tx flag is always in same state as Rx.
7285 */
7286 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7287 features |= NETIF_F_HW_VLAN_CTAG_TX;
7288 else
7289 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
7290
7291 return features;
7292}
7293
7294static int e1000_set_features(struct net_device *netdev,
7295 netdev_features_t features)
7296{
7297 struct e1000_adapter *adapter = netdev_priv(netdev);
7298 netdev_features_t changed = features ^ netdev->features;
7299
7300 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
7301 adapter->flags |= FLAG_TSO_FORCE;
7302
7303 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
7304 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
7305 NETIF_F_RXALL)))
7306 return 0;
7307
7308 if (changed & NETIF_F_RXFCS) {
7309 if (features & NETIF_F_RXFCS) {
7310 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7311 } else {
7312 /* We need to take it back to defaults, which might mean
7313 * stripping is still disabled at the adapter level.
7314 */
7315 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
7316 adapter->flags2 |= FLAG2_CRC_STRIPPING;
7317 else
7318 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7319 }
7320 }
7321
7322 netdev->features = features;
7323
7324 if (netif_running(netdev))
7325 e1000e_reinit_locked(adapter);
7326 else
7327 e1000e_reset(adapter);
7328
7329 return 1;
7330}
7331
7332static const struct net_device_ops e1000e_netdev_ops = {
7333 .ndo_open = e1000e_open,
7334 .ndo_stop = e1000e_close,
7335 .ndo_start_xmit = e1000_xmit_frame,
7336 .ndo_get_stats64 = e1000e_get_stats64,
7337 .ndo_set_rx_mode = e1000e_set_rx_mode,
7338 .ndo_set_mac_address = e1000_set_mac,
7339 .ndo_change_mtu = e1000_change_mtu,
7340 .ndo_eth_ioctl = e1000_ioctl,
7341 .ndo_tx_timeout = e1000_tx_timeout,
7342 .ndo_validate_addr = eth_validate_addr,
7343
7344 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
7345 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
7346#ifdef CONFIG_NET_POLL_CONTROLLER
7347 .ndo_poll_controller = e1000_netpoll,
7348#endif
7349 .ndo_set_features = e1000_set_features,
7350 .ndo_fix_features = e1000_fix_features,
7351 .ndo_features_check = passthru_features_check,
7352};
7353
7354/**
7355 * e1000_probe - Device Initialization Routine
7356 * @pdev: PCI device information struct
7357 * @ent: entry in e1000_pci_tbl
7358 *
7359 * Returns 0 on success, negative on failure
7360 *
7361 * e1000_probe initializes an adapter identified by a pci_dev structure.
7362 * The OS initialization, configuring of the adapter private structure,
7363 * and a hardware reset occur.
7364 **/
7365static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7366{
7367 struct net_device *netdev;
7368 struct e1000_adapter *adapter;
7369 struct e1000_hw *hw;
7370 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
7371 resource_size_t mmio_start, mmio_len;
7372 resource_size_t flash_start, flash_len;
7373 static int cards_found;
7374 u16 aspm_disable_flag = 0;
7375 u16 eeprom_data = 0;
7376 u16 eeprom_apme_mask = E1000_EEPROM_APME;
7377 int bars, i, err;
7378 s32 ret_val = 0;
7379
7380 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
7381 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7382 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
7383 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7384 if (aspm_disable_flag)
7385 e1000e_disable_aspm(pdev, aspm_disable_flag);
7386
7387 err = pci_enable_device_mem(pdev);
7388 if (err)
7389 return err;
7390
7391 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7392 if (err) {
7393 dev_err(&pdev->dev,
7394 "No usable DMA configuration, aborting\n");
7395 goto err_dma;
7396 }
7397
7398 bars = pci_select_bars(pdev, IORESOURCE_MEM);
7399 err = pci_request_selected_regions_exclusive(pdev, bars,
7400 e1000e_driver_name);
7401 if (err)
7402 goto err_pci_reg;
7403
7404 pci_set_master(pdev);
7405 /* PCI config space info */
7406 err = pci_save_state(pdev);
7407 if (err)
7408 goto err_alloc_etherdev;
7409
7410 err = -ENOMEM;
7411 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
7412 if (!netdev)
7413 goto err_alloc_etherdev;
7414
7415 SET_NETDEV_DEV(netdev, &pdev->dev);
7416
7417 netdev->irq = pdev->irq;
7418
7419 pci_set_drvdata(pdev, netdev);
7420 adapter = netdev_priv(netdev);
7421 hw = &adapter->hw;
7422 adapter->netdev = netdev;
7423 adapter->pdev = pdev;
7424 adapter->ei = ei;
7425 adapter->pba = ei->pba;
7426 adapter->flags = ei->flags;
7427 adapter->flags2 = ei->flags2;
7428 adapter->hw.adapter = adapter;
7429 adapter->hw.mac.type = ei->mac;
7430 adapter->max_hw_frame_size = ei->max_hw_frame_size;
7431 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7432
7433 mmio_start = pci_resource_start(pdev, 0);
7434 mmio_len = pci_resource_len(pdev, 0);
7435
7436 err = -EIO;
7437 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
7438 if (!adapter->hw.hw_addr)
7439 goto err_ioremap;
7440
7441 if ((adapter->flags & FLAG_HAS_FLASH) &&
7442 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) &&
7443 (hw->mac.type < e1000_pch_spt)) {
7444 flash_start = pci_resource_start(pdev, 1);
7445 flash_len = pci_resource_len(pdev, 1);
7446 adapter->hw.flash_address = ioremap(flash_start, flash_len);
7447 if (!adapter->hw.flash_address)
7448 goto err_flashmap;
7449 }
7450
7451 /* Set default EEE advertisement */
7452 if (adapter->flags2 & FLAG2_HAS_EEE)
7453 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
7454
7455 /* construct the net_device struct */
7456 netdev->netdev_ops = &e1000e_netdev_ops;
7457 e1000e_set_ethtool_ops(netdev);
7458 netdev->watchdog_timeo = 5 * HZ;
7459 netif_napi_add(netdev, &adapter->napi, e1000e_poll);
7460 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
7461
7462 netdev->mem_start = mmio_start;
7463 netdev->mem_end = mmio_start + mmio_len;
7464
7465 adapter->bd_number = cards_found++;
7466
7467 e1000e_check_options(adapter);
7468
7469 /* setup adapter struct */
7470 err = e1000_sw_init(adapter);
7471 if (err)
7472 goto err_sw_init;
7473
7474 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
7475 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
7476 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
7477
7478 err = ei->get_variants(adapter);
7479 if (err)
7480 goto err_hw_init;
7481
7482 if ((adapter->flags & FLAG_IS_ICH) &&
7483 (adapter->flags & FLAG_READ_ONLY_NVM) &&
7484 (hw->mac.type < e1000_pch_spt))
7485 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
7486
7487 hw->mac.ops.get_bus_info(&adapter->hw);
7488
7489 adapter->hw.phy.autoneg_wait_to_complete = 0;
7490
7491 /* Copper options */
7492 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
7493 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7494 adapter->hw.phy.disable_polarity_correction = 0;
7495 adapter->hw.phy.ms_type = e1000_ms_hw_default;
7496 }
7497
7498 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
7499 dev_info(&pdev->dev,
7500 "PHY reset is blocked due to SOL/IDER session.\n");
7501
7502 /* Set initial default active device features */
7503 netdev->features = (NETIF_F_SG |
7504 NETIF_F_HW_VLAN_CTAG_RX |
7505 NETIF_F_HW_VLAN_CTAG_TX |
7506 NETIF_F_TSO |
7507 NETIF_F_TSO6 |
7508 NETIF_F_RXHASH |
7509 NETIF_F_RXCSUM |
7510 NETIF_F_HW_CSUM);
7511
7512 /* disable TSO for pcie and 10/100 speeds to avoid
7513 * some hardware issues and for i219 to fix transfer
7514 * speed being capped at 60%
7515 */
7516 if (!(adapter->flags & FLAG_TSO_FORCE)) {
7517 switch (adapter->link_speed) {
7518 case SPEED_10:
7519 case SPEED_100:
7520 e_info("10/100 speed: disabling TSO\n");
7521 netdev->features &= ~NETIF_F_TSO;
7522 netdev->features &= ~NETIF_F_TSO6;
7523 break;
7524 case SPEED_1000:
7525 netdev->features |= NETIF_F_TSO;
7526 netdev->features |= NETIF_F_TSO6;
7527 break;
7528 default:
7529 /* oops */
7530 break;
7531 }
7532 if (hw->mac.type == e1000_pch_spt) {
7533 netdev->features &= ~NETIF_F_TSO;
7534 netdev->features &= ~NETIF_F_TSO6;
7535 }
7536 }
7537
7538 /* Set user-changeable features (subset of all device features) */
7539 netdev->hw_features = netdev->features;
7540 netdev->hw_features |= NETIF_F_RXFCS;
7541 netdev->priv_flags |= IFF_SUPP_NOFCS;
7542 netdev->hw_features |= NETIF_F_RXALL;
7543
7544 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
7545 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
7546
7547 netdev->vlan_features |= (NETIF_F_SG |
7548 NETIF_F_TSO |
7549 NETIF_F_TSO6 |
7550 NETIF_F_HW_CSUM);
7551
7552 netdev->priv_flags |= IFF_UNICAST_FLT;
7553
7554 netdev->features |= NETIF_F_HIGHDMA;
7555 netdev->vlan_features |= NETIF_F_HIGHDMA;
7556
7557 /* MTU range: 68 - max_hw_frame_size */
7558 netdev->min_mtu = ETH_MIN_MTU;
7559 netdev->max_mtu = adapter->max_hw_frame_size -
7560 (VLAN_ETH_HLEN + ETH_FCS_LEN);
7561
7562 if (e1000e_enable_mng_pass_thru(&adapter->hw))
7563 adapter->flags |= FLAG_MNG_PT_ENABLED;
7564
7565 /* before reading the NVM, reset the controller to
7566 * put the device in a known good starting state
7567 */
7568 adapter->hw.mac.ops.reset_hw(&adapter->hw);
7569
7570 /* systems with ASPM and others may see the checksum fail on the first
7571 * attempt. Let's give it a few tries
7572 */
7573 for (i = 0;; i++) {
7574 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
7575 break;
7576 if (i == 2) {
7577 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
7578 err = -EIO;
7579 goto err_eeprom;
7580 }
7581 }
7582
7583 e1000_eeprom_checks(adapter);
7584
7585 /* copy the MAC address */
7586 if (e1000e_read_mac_addr(&adapter->hw))
7587 dev_err(&pdev->dev,
7588 "NVM Read Error while reading MAC address\n");
7589
7590 eth_hw_addr_set(netdev, adapter->hw.mac.addr);
7591
7592 if (!is_valid_ether_addr(netdev->dev_addr)) {
7593 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
7594 netdev->dev_addr);
7595 err = -EIO;
7596 goto err_eeprom;
7597 }
7598
7599 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0);
7600 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0);
7601
7602 INIT_WORK(&adapter->reset_task, e1000_reset_task);
7603 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
7604 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
7605 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
7606 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
7607
7608 /* Initialize link parameters. User can change them with ethtool */
7609 adapter->hw.mac.autoneg = 1;
7610 adapter->fc_autoneg = true;
7611 adapter->hw.fc.requested_mode = e1000_fc_default;
7612 adapter->hw.fc.current_mode = e1000_fc_default;
7613 adapter->hw.phy.autoneg_advertised = 0x2f;
7614
7615 /* Initial Wake on LAN setting - If APM wake is enabled in
7616 * the EEPROM, enable the ACPI Magic Packet filter
7617 */
7618 if (adapter->flags & FLAG_APME_IN_WUC) {
7619 /* APME bit in EEPROM is mapped to WUC.APME */
7620 eeprom_data = er32(WUC);
7621 eeprom_apme_mask = E1000_WUC_APME;
7622 if ((hw->mac.type > e1000_ich10lan) &&
7623 (eeprom_data & E1000_WUC_PHY_WAKE))
7624 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
7625 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
7626 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
7627 (adapter->hw.bus.func == 1))
7628 ret_val = e1000_read_nvm(&adapter->hw,
7629 NVM_INIT_CONTROL3_PORT_B,
7630 1, &eeprom_data);
7631 else
7632 ret_val = e1000_read_nvm(&adapter->hw,
7633 NVM_INIT_CONTROL3_PORT_A,
7634 1, &eeprom_data);
7635 }
7636
7637 /* fetch WoL from EEPROM */
7638 if (ret_val)
7639 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val);
7640 else if (eeprom_data & eeprom_apme_mask)
7641 adapter->eeprom_wol |= E1000_WUFC_MAG;
7642
7643 /* now that we have the eeprom settings, apply the special cases
7644 * where the eeprom may be wrong or the board simply won't support
7645 * wake on lan on a particular port
7646 */
7647 if (!(adapter->flags & FLAG_HAS_WOL))
7648 adapter->eeprom_wol = 0;
7649
7650 /* initialize the wol settings based on the eeprom settings */
7651 adapter->wol = adapter->eeprom_wol;
7652
7653 /* make sure adapter isn't asleep if manageability is enabled */
7654 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
7655 (hw->mac.ops.check_mng_mode(hw)))
7656 device_wakeup_enable(&pdev->dev);
7657
7658 /* save off EEPROM version number */
7659 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
7660
7661 if (ret_val) {
7662 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val);
7663 adapter->eeprom_vers = 0;
7664 }
7665
7666 /* init PTP hardware clock */
7667 e1000e_ptp_init(adapter);
7668
7669 /* reset the hardware with the new settings */
7670 e1000e_reset(adapter);
7671
7672 /* If the controller has AMT, do not set DRV_LOAD until the interface
7673 * is up. For all other cases, let the f/w know that the h/w is now
7674 * under the control of the driver.
7675 */
7676 if (!(adapter->flags & FLAG_HAS_AMT))
7677 e1000e_get_hw_control(adapter);
7678
7679 if (hw->mac.type >= e1000_pch_cnp)
7680 adapter->flags2 |= FLAG2_ENABLE_S0IX_FLOWS;
7681
7682 strscpy(netdev->name, "eth%d", sizeof(netdev->name));
7683 err = register_netdev(netdev);
7684 if (err)
7685 goto err_register;
7686
7687 /* carrier off reporting is important to ethtool even BEFORE open */
7688 netif_carrier_off(netdev);
7689
7690 e1000_print_device_info(adapter);
7691
7692 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_SMART_PREPARE);
7693
7694 if (pci_dev_run_wake(pdev))
7695 pm_runtime_put_noidle(&pdev->dev);
7696
7697 return 0;
7698
7699err_register:
7700 if (!(adapter->flags & FLAG_HAS_AMT))
7701 e1000e_release_hw_control(adapter);
7702err_eeprom:
7703 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
7704 e1000_phy_hw_reset(&adapter->hw);
7705err_hw_init:
7706 kfree(adapter->tx_ring);
7707 kfree(adapter->rx_ring);
7708err_sw_init:
7709 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt))
7710 iounmap(adapter->hw.flash_address);
7711 e1000e_reset_interrupt_capability(adapter);
7712err_flashmap:
7713 iounmap(adapter->hw.hw_addr);
7714err_ioremap:
7715 free_netdev(netdev);
7716err_alloc_etherdev:
7717 pci_release_mem_regions(pdev);
7718err_pci_reg:
7719err_dma:
7720 pci_disable_device(pdev);
7721 return err;
7722}
7723
7724/**
7725 * e1000_remove - Device Removal Routine
7726 * @pdev: PCI device information struct
7727 *
7728 * e1000_remove is called by the PCI subsystem to alert the driver
7729 * that it should release a PCI device. This could be caused by a
7730 * Hot-Plug event, or because the driver is going to be removed from
7731 * memory.
7732 **/
7733static void e1000_remove(struct pci_dev *pdev)
7734{
7735 struct net_device *netdev = pci_get_drvdata(pdev);
7736 struct e1000_adapter *adapter = netdev_priv(netdev);
7737
7738 e1000e_ptp_remove(adapter);
7739
7740 /* The timers may be rescheduled, so explicitly disable them
7741 * from being rescheduled.
7742 */
7743 set_bit(__E1000_DOWN, &adapter->state);
7744 del_timer_sync(&adapter->watchdog_timer);
7745 del_timer_sync(&adapter->phy_info_timer);
7746
7747 cancel_work_sync(&adapter->reset_task);
7748 cancel_work_sync(&adapter->watchdog_task);
7749 cancel_work_sync(&adapter->downshift_task);
7750 cancel_work_sync(&adapter->update_phy_task);
7751 cancel_work_sync(&adapter->print_hang_task);
7752
7753 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
7754 cancel_work_sync(&adapter->tx_hwtstamp_work);
7755 if (adapter->tx_hwtstamp_skb) {
7756 dev_consume_skb_any(adapter->tx_hwtstamp_skb);
7757 adapter->tx_hwtstamp_skb = NULL;
7758 }
7759 }
7760
7761 unregister_netdev(netdev);
7762
7763 if (pci_dev_run_wake(pdev))
7764 pm_runtime_get_noresume(&pdev->dev);
7765
7766 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7767 * would have already happened in close and is redundant.
7768 */
7769 e1000e_release_hw_control(adapter);
7770
7771 e1000e_reset_interrupt_capability(adapter);
7772 kfree(adapter->tx_ring);
7773 kfree(adapter->rx_ring);
7774
7775 iounmap(adapter->hw.hw_addr);
7776 if ((adapter->hw.flash_address) &&
7777 (adapter->hw.mac.type < e1000_pch_spt))
7778 iounmap(adapter->hw.flash_address);
7779 pci_release_mem_regions(pdev);
7780
7781 free_netdev(netdev);
7782
7783 pci_disable_device(pdev);
7784}
7785
7786/* PCI Error Recovery (ERS) */
7787static const struct pci_error_handlers e1000_err_handler = {
7788 .error_detected = e1000_io_error_detected,
7789 .slot_reset = e1000_io_slot_reset,
7790 .resume = e1000_io_resume,
7791};
7792
7793static const struct pci_device_id e1000_pci_tbl[] = {
7794 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
7795 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
7796 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
7797 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7798 board_82571 },
7799 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
7800 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
7801 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
7802 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
7803 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
7804
7805 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
7806 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
7807 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
7808 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
7809
7810 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
7811 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
7812 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
7813
7814 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
7815 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
7816 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
7817
7818 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7819 board_80003es2lan },
7820 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7821 board_80003es2lan },
7822 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7823 board_80003es2lan },
7824 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7825 board_80003es2lan },
7826
7827 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
7828 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
7829 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
7830 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
7831 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
7832 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
7833 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
7834 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
7835
7836 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
7837 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
7838 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
7839 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
7840 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
7841 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
7842 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
7843 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
7844 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
7845
7846 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
7847 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
7848 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
7849
7850 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
7851 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
7852 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
7853
7854 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
7855 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
7856 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7857 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7858
7859 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7860 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7861
7862 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7863 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
7864 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7865 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
7866 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt },
7867 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7868 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7869 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
7870 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt },
7871 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt },
7872 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt },
7873 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt },
7874 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt },
7875 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt },
7876 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt },
7877 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt },
7878 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt },
7879 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp },
7880 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp },
7881 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp },
7882 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp },
7883 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp },
7884 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp },
7885 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp },
7886 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp },
7887 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM10), board_pch_cnp },
7888 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V10), board_pch_cnp },
7889 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM11), board_pch_cnp },
7890 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), board_pch_cnp },
7891 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), board_pch_spt },
7892 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), board_pch_spt },
7893 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_tgp },
7894 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_tgp },
7895 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_tgp },
7896 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_tgp },
7897 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_tgp },
7898 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), board_pch_tgp },
7899 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM23), board_pch_adp },
7900 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V23), board_pch_adp },
7901 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), board_pch_adp },
7902 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), board_pch_adp },
7903 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), board_pch_adp },
7904 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), board_pch_adp },
7905 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM22), board_pch_adp },
7906 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V22), board_pch_adp },
7907 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM19), board_pch_adp },
7908 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V19), board_pch_adp },
7909 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM18), board_pch_mtp },
7910 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V18), board_pch_mtp },
7911 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM20), board_pch_mtp },
7912 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V20), board_pch_mtp },
7913 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM21), board_pch_mtp },
7914 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V21), board_pch_mtp },
7915 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_LM24), board_pch_mtp },
7916 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_V24), board_pch_mtp },
7917 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM25), board_pch_mtp },
7918 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V25), board_pch_mtp },
7919 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM26), board_pch_mtp },
7920 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V26), board_pch_mtp },
7921 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM27), board_pch_mtp },
7922 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V27), board_pch_mtp },
7923 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_LM29), board_pch_mtp },
7924 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_V29), board_pch_mtp },
7925
7926 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
7927};
7928MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7929
7930static const struct dev_pm_ops e1000e_pm_ops = {
7931 .prepare = e1000e_pm_prepare,
7932 .suspend = e1000e_pm_suspend,
7933 .resume = e1000e_pm_resume,
7934 .freeze = e1000e_pm_freeze,
7935 .thaw = e1000e_pm_thaw,
7936 .poweroff = e1000e_pm_suspend,
7937 .restore = e1000e_pm_resume,
7938 RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
7939 e1000e_pm_runtime_idle)
7940};
7941
7942/* PCI Device API Driver */
7943static struct pci_driver e1000_driver = {
7944 .name = e1000e_driver_name,
7945 .id_table = e1000_pci_tbl,
7946 .probe = e1000_probe,
7947 .remove = e1000_remove,
7948 .driver.pm = pm_ptr(&e1000e_pm_ops),
7949 .shutdown = e1000_shutdown,
7950 .err_handler = &e1000_err_handler
7951};
7952
7953/**
7954 * e1000_init_module - Driver Registration Routine
7955 *
7956 * e1000_init_module is the first routine called when the driver is
7957 * loaded. All it does is register with the PCI subsystem.
7958 **/
7959static int __init e1000_init_module(void)
7960{
7961 pr_info("Intel(R) PRO/1000 Network Driver\n");
7962 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n");
7963
7964 return pci_register_driver(&e1000_driver);
7965}
7966module_init(e1000_init_module);
7967
7968/**
7969 * e1000_exit_module - Driver Exit Cleanup Routine
7970 *
7971 * e1000_exit_module is called just before the driver is removed
7972 * from memory.
7973 **/
7974static void __exit e1000_exit_module(void)
7975{
7976 pci_unregister_driver(&e1000_driver);
7977}
7978module_exit(e1000_exit_module);
7979
7980MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7981MODULE_LICENSE("GPL v2");
7982
7983/* netdev.c */
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
5
6#include <linux/module.h>
7#include <linux/types.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/vmalloc.h>
11#include <linux/pagemap.h>
12#include <linux/delay.h>
13#include <linux/netdevice.h>
14#include <linux/interrupt.h>
15#include <linux/tcp.h>
16#include <linux/ipv6.h>
17#include <linux/slab.h>
18#include <net/checksum.h>
19#include <net/ip6_checksum.h>
20#include <linux/ethtool.h>
21#include <linux/if_vlan.h>
22#include <linux/cpu.h>
23#include <linux/smp.h>
24#include <linux/pm_qos.h>
25#include <linux/pm_runtime.h>
26#include <linux/aer.h>
27#include <linux/prefetch.h>
28#include <linux/suspend.h>
29
30#include "e1000.h"
31#define CREATE_TRACE_POINTS
32#include "e1000e_trace.h"
33
34char e1000e_driver_name[] = "e1000e";
35
36#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
37static int debug = -1;
38module_param(debug, int, 0);
39MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
40
41static const struct e1000_info *e1000_info_tbl[] = {
42 [board_82571] = &e1000_82571_info,
43 [board_82572] = &e1000_82572_info,
44 [board_82573] = &e1000_82573_info,
45 [board_82574] = &e1000_82574_info,
46 [board_82583] = &e1000_82583_info,
47 [board_80003es2lan] = &e1000_es2_info,
48 [board_ich8lan] = &e1000_ich8_info,
49 [board_ich9lan] = &e1000_ich9_info,
50 [board_ich10lan] = &e1000_ich10_info,
51 [board_pchlan] = &e1000_pch_info,
52 [board_pch2lan] = &e1000_pch2_info,
53 [board_pch_lpt] = &e1000_pch_lpt_info,
54 [board_pch_spt] = &e1000_pch_spt_info,
55 [board_pch_cnp] = &e1000_pch_cnp_info,
56 [board_pch_tgp] = &e1000_pch_tgp_info,
57 [board_pch_adp] = &e1000_pch_adp_info,
58 [board_pch_mtp] = &e1000_pch_mtp_info,
59};
60
61struct e1000_reg_info {
62 u32 ofs;
63 char *name;
64};
65
66static const struct e1000_reg_info e1000_reg_info_tbl[] = {
67 /* General Registers */
68 {E1000_CTRL, "CTRL"},
69 {E1000_STATUS, "STATUS"},
70 {E1000_CTRL_EXT, "CTRL_EXT"},
71
72 /* Interrupt Registers */
73 {E1000_ICR, "ICR"},
74
75 /* Rx Registers */
76 {E1000_RCTL, "RCTL"},
77 {E1000_RDLEN(0), "RDLEN"},
78 {E1000_RDH(0), "RDH"},
79 {E1000_RDT(0), "RDT"},
80 {E1000_RDTR, "RDTR"},
81 {E1000_RXDCTL(0), "RXDCTL"},
82 {E1000_ERT, "ERT"},
83 {E1000_RDBAL(0), "RDBAL"},
84 {E1000_RDBAH(0), "RDBAH"},
85 {E1000_RDFH, "RDFH"},
86 {E1000_RDFT, "RDFT"},
87 {E1000_RDFHS, "RDFHS"},
88 {E1000_RDFTS, "RDFTS"},
89 {E1000_RDFPC, "RDFPC"},
90
91 /* Tx Registers */
92 {E1000_TCTL, "TCTL"},
93 {E1000_TDBAL(0), "TDBAL"},
94 {E1000_TDBAH(0), "TDBAH"},
95 {E1000_TDLEN(0), "TDLEN"},
96 {E1000_TDH(0), "TDH"},
97 {E1000_TDT(0), "TDT"},
98 {E1000_TIDV, "TIDV"},
99 {E1000_TXDCTL(0), "TXDCTL"},
100 {E1000_TADV, "TADV"},
101 {E1000_TARC(0), "TARC"},
102 {E1000_TDFH, "TDFH"},
103 {E1000_TDFT, "TDFT"},
104 {E1000_TDFHS, "TDFHS"},
105 {E1000_TDFTS, "TDFTS"},
106 {E1000_TDFPC, "TDFPC"},
107
108 /* List Terminator */
109 {0, NULL}
110};
111
112/**
113 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
114 * @hw: pointer to the HW structure
115 *
116 * When updating the MAC CSR registers, the Manageability Engine (ME) could
117 * be accessing the registers at the same time. Normally, this is handled in
118 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
119 * accesses later than it should which could result in the register to have
120 * an incorrect value. Workaround this by checking the FWSM register which
121 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
122 * and try again a number of times.
123 **/
124static void __ew32_prepare(struct e1000_hw *hw)
125{
126 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
127
128 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
129 udelay(50);
130}
131
132void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
133{
134 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
135 __ew32_prepare(hw);
136
137 writel(val, hw->hw_addr + reg);
138}
139
140/**
141 * e1000_regdump - register printout routine
142 * @hw: pointer to the HW structure
143 * @reginfo: pointer to the register info table
144 **/
145static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
146{
147 int n = 0;
148 char rname[16];
149 u32 regs[8];
150
151 switch (reginfo->ofs) {
152 case E1000_RXDCTL(0):
153 for (n = 0; n < 2; n++)
154 regs[n] = __er32(hw, E1000_RXDCTL(n));
155 break;
156 case E1000_TXDCTL(0):
157 for (n = 0; n < 2; n++)
158 regs[n] = __er32(hw, E1000_TXDCTL(n));
159 break;
160 case E1000_TARC(0):
161 for (n = 0; n < 2; n++)
162 regs[n] = __er32(hw, E1000_TARC(n));
163 break;
164 default:
165 pr_info("%-15s %08x\n",
166 reginfo->name, __er32(hw, reginfo->ofs));
167 return;
168 }
169
170 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
171 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
172}
173
174static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
175 struct e1000_buffer *bi)
176{
177 int i;
178 struct e1000_ps_page *ps_page;
179
180 for (i = 0; i < adapter->rx_ps_pages; i++) {
181 ps_page = &bi->ps_pages[i];
182
183 if (ps_page->page) {
184 pr_info("packet dump for ps_page %d:\n", i);
185 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
186 16, 1, page_address(ps_page->page),
187 PAGE_SIZE, true);
188 }
189 }
190}
191
192/**
193 * e1000e_dump - Print registers, Tx-ring and Rx-ring
194 * @adapter: board private structure
195 **/
196static void e1000e_dump(struct e1000_adapter *adapter)
197{
198 struct net_device *netdev = adapter->netdev;
199 struct e1000_hw *hw = &adapter->hw;
200 struct e1000_reg_info *reginfo;
201 struct e1000_ring *tx_ring = adapter->tx_ring;
202 struct e1000_tx_desc *tx_desc;
203 struct my_u0 {
204 __le64 a;
205 __le64 b;
206 } *u0;
207 struct e1000_buffer *buffer_info;
208 struct e1000_ring *rx_ring = adapter->rx_ring;
209 union e1000_rx_desc_packet_split *rx_desc_ps;
210 union e1000_rx_desc_extended *rx_desc;
211 struct my_u1 {
212 __le64 a;
213 __le64 b;
214 __le64 c;
215 __le64 d;
216 } *u1;
217 u32 staterr;
218 int i = 0;
219
220 if (!netif_msg_hw(adapter))
221 return;
222
223 /* Print netdevice Info */
224 if (netdev) {
225 dev_info(&adapter->pdev->dev, "Net device Info\n");
226 pr_info("Device Name state trans_start\n");
227 pr_info("%-15s %016lX %016lX\n", netdev->name,
228 netdev->state, dev_trans_start(netdev));
229 }
230
231 /* Print Registers */
232 dev_info(&adapter->pdev->dev, "Register Dump\n");
233 pr_info(" Register Name Value\n");
234 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
235 reginfo->name; reginfo++) {
236 e1000_regdump(hw, reginfo);
237 }
238
239 /* Print Tx Ring Summary */
240 if (!netdev || !netif_running(netdev))
241 return;
242
243 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
244 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
245 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
246 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
247 0, tx_ring->next_to_use, tx_ring->next_to_clean,
248 (unsigned long long)buffer_info->dma,
249 buffer_info->length,
250 buffer_info->next_to_watch,
251 (unsigned long long)buffer_info->time_stamp);
252
253 /* Print Tx Ring */
254 if (!netif_msg_tx_done(adapter))
255 goto rx_ring_summary;
256
257 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
258
259 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
260 *
261 * Legacy Transmit Descriptor
262 * +--------------------------------------------------------------+
263 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
264 * +--------------------------------------------------------------+
265 * 8 | Special | CSS | Status | CMD | CSO | Length |
266 * +--------------------------------------------------------------+
267 * 63 48 47 36 35 32 31 24 23 16 15 0
268 *
269 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
270 * 63 48 47 40 39 32 31 16 15 8 7 0
271 * +----------------------------------------------------------------+
272 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
273 * +----------------------------------------------------------------+
274 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
275 * +----------------------------------------------------------------+
276 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
277 *
278 * Extended Data Descriptor (DTYP=0x1)
279 * +----------------------------------------------------------------+
280 * 0 | Buffer Address [63:0] |
281 * +----------------------------------------------------------------+
282 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
283 * +----------------------------------------------------------------+
284 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
285 */
286 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
287 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
288 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
289 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
290 const char *next_desc;
291 tx_desc = E1000_TX_DESC(*tx_ring, i);
292 buffer_info = &tx_ring->buffer_info[i];
293 u0 = (struct my_u0 *)tx_desc;
294 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
295 next_desc = " NTC/U";
296 else if (i == tx_ring->next_to_use)
297 next_desc = " NTU";
298 else if (i == tx_ring->next_to_clean)
299 next_desc = " NTC";
300 else
301 next_desc = "";
302 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
303 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' :
304 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')),
305 i,
306 (unsigned long long)le64_to_cpu(u0->a),
307 (unsigned long long)le64_to_cpu(u0->b),
308 (unsigned long long)buffer_info->dma,
309 buffer_info->length, buffer_info->next_to_watch,
310 (unsigned long long)buffer_info->time_stamp,
311 buffer_info->skb, next_desc);
312
313 if (netif_msg_pktdata(adapter) && buffer_info->skb)
314 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
315 16, 1, buffer_info->skb->data,
316 buffer_info->skb->len, true);
317 }
318
319 /* Print Rx Ring Summary */
320rx_ring_summary:
321 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
322 pr_info("Queue [NTU] [NTC]\n");
323 pr_info(" %5d %5X %5X\n",
324 0, rx_ring->next_to_use, rx_ring->next_to_clean);
325
326 /* Print Rx Ring */
327 if (!netif_msg_rx_status(adapter))
328 return;
329
330 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
331 switch (adapter->rx_ps_pages) {
332 case 1:
333 case 2:
334 case 3:
335 /* [Extended] Packet Split Receive Descriptor Format
336 *
337 * +-----------------------------------------------------+
338 * 0 | Buffer Address 0 [63:0] |
339 * +-----------------------------------------------------+
340 * 8 | Buffer Address 1 [63:0] |
341 * +-----------------------------------------------------+
342 * 16 | Buffer Address 2 [63:0] |
343 * +-----------------------------------------------------+
344 * 24 | Buffer Address 3 [63:0] |
345 * +-----------------------------------------------------+
346 */
347 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
348 /* [Extended] Receive Descriptor (Write-Back) Format
349 *
350 * 63 48 47 32 31 13 12 8 7 4 3 0
351 * +------------------------------------------------------+
352 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
353 * | Checksum | Ident | | Queue | | Type |
354 * +------------------------------------------------------+
355 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
356 * +------------------------------------------------------+
357 * 63 48 47 32 31 20 19 0
358 */
359 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
360 for (i = 0; i < rx_ring->count; i++) {
361 const char *next_desc;
362 buffer_info = &rx_ring->buffer_info[i];
363 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
364 u1 = (struct my_u1 *)rx_desc_ps;
365 staterr =
366 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
367
368 if (i == rx_ring->next_to_use)
369 next_desc = " NTU";
370 else if (i == rx_ring->next_to_clean)
371 next_desc = " NTC";
372 else
373 next_desc = "";
374
375 if (staterr & E1000_RXD_STAT_DD) {
376 /* Descriptor Done */
377 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
378 "RWB", i,
379 (unsigned long long)le64_to_cpu(u1->a),
380 (unsigned long long)le64_to_cpu(u1->b),
381 (unsigned long long)le64_to_cpu(u1->c),
382 (unsigned long long)le64_to_cpu(u1->d),
383 buffer_info->skb, next_desc);
384 } else {
385 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
386 "R ", i,
387 (unsigned long long)le64_to_cpu(u1->a),
388 (unsigned long long)le64_to_cpu(u1->b),
389 (unsigned long long)le64_to_cpu(u1->c),
390 (unsigned long long)le64_to_cpu(u1->d),
391 (unsigned long long)buffer_info->dma,
392 buffer_info->skb, next_desc);
393
394 if (netif_msg_pktdata(adapter))
395 e1000e_dump_ps_pages(adapter,
396 buffer_info);
397 }
398 }
399 break;
400 default:
401 case 0:
402 /* Extended Receive Descriptor (Read) Format
403 *
404 * +-----------------------------------------------------+
405 * 0 | Buffer Address [63:0] |
406 * +-----------------------------------------------------+
407 * 8 | Reserved |
408 * +-----------------------------------------------------+
409 */
410 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
411 /* Extended Receive Descriptor (Write-Back) Format
412 *
413 * 63 48 47 32 31 24 23 4 3 0
414 * +------------------------------------------------------+
415 * | RSS Hash | | | |
416 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
417 * | Packet | IP | | | Type |
418 * | Checksum | Ident | | | |
419 * +------------------------------------------------------+
420 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
421 * +------------------------------------------------------+
422 * 63 48 47 32 31 20 19 0
423 */
424 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
425
426 for (i = 0; i < rx_ring->count; i++) {
427 const char *next_desc;
428
429 buffer_info = &rx_ring->buffer_info[i];
430 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
431 u1 = (struct my_u1 *)rx_desc;
432 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
433
434 if (i == rx_ring->next_to_use)
435 next_desc = " NTU";
436 else if (i == rx_ring->next_to_clean)
437 next_desc = " NTC";
438 else
439 next_desc = "";
440
441 if (staterr & E1000_RXD_STAT_DD) {
442 /* Descriptor Done */
443 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
444 "RWB", i,
445 (unsigned long long)le64_to_cpu(u1->a),
446 (unsigned long long)le64_to_cpu(u1->b),
447 buffer_info->skb, next_desc);
448 } else {
449 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
450 "R ", i,
451 (unsigned long long)le64_to_cpu(u1->a),
452 (unsigned long long)le64_to_cpu(u1->b),
453 (unsigned long long)buffer_info->dma,
454 buffer_info->skb, next_desc);
455
456 if (netif_msg_pktdata(adapter) &&
457 buffer_info->skb)
458 print_hex_dump(KERN_INFO, "",
459 DUMP_PREFIX_ADDRESS, 16,
460 1,
461 buffer_info->skb->data,
462 adapter->rx_buffer_len,
463 true);
464 }
465 }
466 }
467}
468
469/**
470 * e1000_desc_unused - calculate if we have unused descriptors
471 * @ring: pointer to ring struct to perform calculation on
472 **/
473static int e1000_desc_unused(struct e1000_ring *ring)
474{
475 if (ring->next_to_clean > ring->next_to_use)
476 return ring->next_to_clean - ring->next_to_use - 1;
477
478 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
479}
480
481/**
482 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
483 * @adapter: board private structure
484 * @hwtstamps: time stamp structure to update
485 * @systim: unsigned 64bit system time value.
486 *
487 * Convert the system time value stored in the RX/TXSTMP registers into a
488 * hwtstamp which can be used by the upper level time stamping functions.
489 *
490 * The 'systim_lock' spinlock is used to protect the consistency of the
491 * system time value. This is needed because reading the 64 bit time
492 * value involves reading two 32 bit registers. The first read latches the
493 * value.
494 **/
495static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
496 struct skb_shared_hwtstamps *hwtstamps,
497 u64 systim)
498{
499 u64 ns;
500 unsigned long flags;
501
502 spin_lock_irqsave(&adapter->systim_lock, flags);
503 ns = timecounter_cyc2time(&adapter->tc, systim);
504 spin_unlock_irqrestore(&adapter->systim_lock, flags);
505
506 memset(hwtstamps, 0, sizeof(*hwtstamps));
507 hwtstamps->hwtstamp = ns_to_ktime(ns);
508}
509
510/**
511 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
512 * @adapter: board private structure
513 * @status: descriptor extended error and status field
514 * @skb: particular skb to include time stamp
515 *
516 * If the time stamp is valid, convert it into the timecounter ns value
517 * and store that result into the shhwtstamps structure which is passed
518 * up the network stack.
519 **/
520static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
521 struct sk_buff *skb)
522{
523 struct e1000_hw *hw = &adapter->hw;
524 u64 rxstmp;
525
526 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
527 !(status & E1000_RXDEXT_STATERR_TST) ||
528 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
529 return;
530
531 /* The Rx time stamp registers contain the time stamp. No other
532 * received packet will be time stamped until the Rx time stamp
533 * registers are read. Because only one packet can be time stamped
534 * at a time, the register values must belong to this packet and
535 * therefore none of the other additional attributes need to be
536 * compared.
537 */
538 rxstmp = (u64)er32(RXSTMPL);
539 rxstmp |= (u64)er32(RXSTMPH) << 32;
540 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
541
542 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
543}
544
545/**
546 * e1000_receive_skb - helper function to handle Rx indications
547 * @adapter: board private structure
548 * @netdev: pointer to netdev struct
549 * @staterr: descriptor extended error and status field as written by hardware
550 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
551 * @skb: pointer to sk_buff to be indicated to stack
552 **/
553static void e1000_receive_skb(struct e1000_adapter *adapter,
554 struct net_device *netdev, struct sk_buff *skb,
555 u32 staterr, __le16 vlan)
556{
557 u16 tag = le16_to_cpu(vlan);
558
559 e1000e_rx_hwtstamp(adapter, staterr, skb);
560
561 skb->protocol = eth_type_trans(skb, netdev);
562
563 if (staterr & E1000_RXD_STAT_VP)
564 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
565
566 napi_gro_receive(&adapter->napi, skb);
567}
568
569/**
570 * e1000_rx_checksum - Receive Checksum Offload
571 * @adapter: board private structure
572 * @status_err: receive descriptor status and error fields
573 * @skb: socket buffer with received data
574 **/
575static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
576 struct sk_buff *skb)
577{
578 u16 status = (u16)status_err;
579 u8 errors = (u8)(status_err >> 24);
580
581 skb_checksum_none_assert(skb);
582
583 /* Rx checksum disabled */
584 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
585 return;
586
587 /* Ignore Checksum bit is set */
588 if (status & E1000_RXD_STAT_IXSM)
589 return;
590
591 /* TCP/UDP checksum error bit or IP checksum error bit is set */
592 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
593 /* let the stack verify checksum errors */
594 adapter->hw_csum_err++;
595 return;
596 }
597
598 /* TCP/UDP Checksum has not been calculated */
599 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
600 return;
601
602 /* It must be a TCP or UDP packet with a valid checksum */
603 skb->ip_summed = CHECKSUM_UNNECESSARY;
604 adapter->hw_csum_good++;
605}
606
607static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
608{
609 struct e1000_adapter *adapter = rx_ring->adapter;
610 struct e1000_hw *hw = &adapter->hw;
611
612 __ew32_prepare(hw);
613 writel(i, rx_ring->tail);
614
615 if (unlikely(i != readl(rx_ring->tail))) {
616 u32 rctl = er32(RCTL);
617
618 ew32(RCTL, rctl & ~E1000_RCTL_EN);
619 e_err("ME firmware caused invalid RDT - resetting\n");
620 schedule_work(&adapter->reset_task);
621 }
622}
623
624static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
625{
626 struct e1000_adapter *adapter = tx_ring->adapter;
627 struct e1000_hw *hw = &adapter->hw;
628
629 __ew32_prepare(hw);
630 writel(i, tx_ring->tail);
631
632 if (unlikely(i != readl(tx_ring->tail))) {
633 u32 tctl = er32(TCTL);
634
635 ew32(TCTL, tctl & ~E1000_TCTL_EN);
636 e_err("ME firmware caused invalid TDT - resetting\n");
637 schedule_work(&adapter->reset_task);
638 }
639}
640
641/**
642 * e1000_alloc_rx_buffers - Replace used receive buffers
643 * @rx_ring: Rx descriptor ring
644 * @cleaned_count: number to reallocate
645 * @gfp: flags for allocation
646 **/
647static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
648 int cleaned_count, gfp_t gfp)
649{
650 struct e1000_adapter *adapter = rx_ring->adapter;
651 struct net_device *netdev = adapter->netdev;
652 struct pci_dev *pdev = adapter->pdev;
653 union e1000_rx_desc_extended *rx_desc;
654 struct e1000_buffer *buffer_info;
655 struct sk_buff *skb;
656 unsigned int i;
657 unsigned int bufsz = adapter->rx_buffer_len;
658
659 i = rx_ring->next_to_use;
660 buffer_info = &rx_ring->buffer_info[i];
661
662 while (cleaned_count--) {
663 skb = buffer_info->skb;
664 if (skb) {
665 skb_trim(skb, 0);
666 goto map_skb;
667 }
668
669 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
670 if (!skb) {
671 /* Better luck next round */
672 adapter->alloc_rx_buff_failed++;
673 break;
674 }
675
676 buffer_info->skb = skb;
677map_skb:
678 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
679 adapter->rx_buffer_len,
680 DMA_FROM_DEVICE);
681 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
682 dev_err(&pdev->dev, "Rx DMA map failed\n");
683 adapter->rx_dma_failed++;
684 break;
685 }
686
687 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
688 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
689
690 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
691 /* Force memory writes to complete before letting h/w
692 * know there are new descriptors to fetch. (Only
693 * applicable for weak-ordered memory model archs,
694 * such as IA-64).
695 */
696 wmb();
697 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
698 e1000e_update_rdt_wa(rx_ring, i);
699 else
700 writel(i, rx_ring->tail);
701 }
702 i++;
703 if (i == rx_ring->count)
704 i = 0;
705 buffer_info = &rx_ring->buffer_info[i];
706 }
707
708 rx_ring->next_to_use = i;
709}
710
711/**
712 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
713 * @rx_ring: Rx descriptor ring
714 * @cleaned_count: number to reallocate
715 * @gfp: flags for allocation
716 **/
717static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
718 int cleaned_count, gfp_t gfp)
719{
720 struct e1000_adapter *adapter = rx_ring->adapter;
721 struct net_device *netdev = adapter->netdev;
722 struct pci_dev *pdev = adapter->pdev;
723 union e1000_rx_desc_packet_split *rx_desc;
724 struct e1000_buffer *buffer_info;
725 struct e1000_ps_page *ps_page;
726 struct sk_buff *skb;
727 unsigned int i, j;
728
729 i = rx_ring->next_to_use;
730 buffer_info = &rx_ring->buffer_info[i];
731
732 while (cleaned_count--) {
733 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
734
735 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
736 ps_page = &buffer_info->ps_pages[j];
737 if (j >= adapter->rx_ps_pages) {
738 /* all unused desc entries get hw null ptr */
739 rx_desc->read.buffer_addr[j + 1] =
740 ~cpu_to_le64(0);
741 continue;
742 }
743 if (!ps_page->page) {
744 ps_page->page = alloc_page(gfp);
745 if (!ps_page->page) {
746 adapter->alloc_rx_buff_failed++;
747 goto no_buffers;
748 }
749 ps_page->dma = dma_map_page(&pdev->dev,
750 ps_page->page,
751 0, PAGE_SIZE,
752 DMA_FROM_DEVICE);
753 if (dma_mapping_error(&pdev->dev,
754 ps_page->dma)) {
755 dev_err(&adapter->pdev->dev,
756 "Rx DMA page map failed\n");
757 adapter->rx_dma_failed++;
758 goto no_buffers;
759 }
760 }
761 /* Refresh the desc even if buffer_addrs
762 * didn't change because each write-back
763 * erases this info.
764 */
765 rx_desc->read.buffer_addr[j + 1] =
766 cpu_to_le64(ps_page->dma);
767 }
768
769 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
770 gfp);
771
772 if (!skb) {
773 adapter->alloc_rx_buff_failed++;
774 break;
775 }
776
777 buffer_info->skb = skb;
778 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
779 adapter->rx_ps_bsize0,
780 DMA_FROM_DEVICE);
781 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
782 dev_err(&pdev->dev, "Rx DMA map failed\n");
783 adapter->rx_dma_failed++;
784 /* cleanup skb */
785 dev_kfree_skb_any(skb);
786 buffer_info->skb = NULL;
787 break;
788 }
789
790 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
791
792 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
793 /* Force memory writes to complete before letting h/w
794 * know there are new descriptors to fetch. (Only
795 * applicable for weak-ordered memory model archs,
796 * such as IA-64).
797 */
798 wmb();
799 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
800 e1000e_update_rdt_wa(rx_ring, i << 1);
801 else
802 writel(i << 1, rx_ring->tail);
803 }
804
805 i++;
806 if (i == rx_ring->count)
807 i = 0;
808 buffer_info = &rx_ring->buffer_info[i];
809 }
810
811no_buffers:
812 rx_ring->next_to_use = i;
813}
814
815/**
816 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
817 * @rx_ring: Rx descriptor ring
818 * @cleaned_count: number of buffers to allocate this pass
819 * @gfp: flags for allocation
820 **/
821
822static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
823 int cleaned_count, gfp_t gfp)
824{
825 struct e1000_adapter *adapter = rx_ring->adapter;
826 struct net_device *netdev = adapter->netdev;
827 struct pci_dev *pdev = adapter->pdev;
828 union e1000_rx_desc_extended *rx_desc;
829 struct e1000_buffer *buffer_info;
830 struct sk_buff *skb;
831 unsigned int i;
832 unsigned int bufsz = 256 - 16; /* for skb_reserve */
833
834 i = rx_ring->next_to_use;
835 buffer_info = &rx_ring->buffer_info[i];
836
837 while (cleaned_count--) {
838 skb = buffer_info->skb;
839 if (skb) {
840 skb_trim(skb, 0);
841 goto check_page;
842 }
843
844 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
845 if (unlikely(!skb)) {
846 /* Better luck next round */
847 adapter->alloc_rx_buff_failed++;
848 break;
849 }
850
851 buffer_info->skb = skb;
852check_page:
853 /* allocate a new page if necessary */
854 if (!buffer_info->page) {
855 buffer_info->page = alloc_page(gfp);
856 if (unlikely(!buffer_info->page)) {
857 adapter->alloc_rx_buff_failed++;
858 break;
859 }
860 }
861
862 if (!buffer_info->dma) {
863 buffer_info->dma = dma_map_page(&pdev->dev,
864 buffer_info->page, 0,
865 PAGE_SIZE,
866 DMA_FROM_DEVICE);
867 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
868 adapter->alloc_rx_buff_failed++;
869 break;
870 }
871 }
872
873 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
874 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
875
876 if (unlikely(++i == rx_ring->count))
877 i = 0;
878 buffer_info = &rx_ring->buffer_info[i];
879 }
880
881 if (likely(rx_ring->next_to_use != i)) {
882 rx_ring->next_to_use = i;
883 if (unlikely(i-- == 0))
884 i = (rx_ring->count - 1);
885
886 /* Force memory writes to complete before letting h/w
887 * know there are new descriptors to fetch. (Only
888 * applicable for weak-ordered memory model archs,
889 * such as IA-64).
890 */
891 wmb();
892 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
893 e1000e_update_rdt_wa(rx_ring, i);
894 else
895 writel(i, rx_ring->tail);
896 }
897}
898
899static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
900 struct sk_buff *skb)
901{
902 if (netdev->features & NETIF_F_RXHASH)
903 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3);
904}
905
906/**
907 * e1000_clean_rx_irq - Send received data up the network stack
908 * @rx_ring: Rx descriptor ring
909 * @work_done: output parameter for indicating completed work
910 * @work_to_do: how many packets we can clean
911 *
912 * the return value indicates whether actual cleaning was done, there
913 * is no guarantee that everything was cleaned
914 **/
915static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
916 int work_to_do)
917{
918 struct e1000_adapter *adapter = rx_ring->adapter;
919 struct net_device *netdev = adapter->netdev;
920 struct pci_dev *pdev = adapter->pdev;
921 struct e1000_hw *hw = &adapter->hw;
922 union e1000_rx_desc_extended *rx_desc, *next_rxd;
923 struct e1000_buffer *buffer_info, *next_buffer;
924 u32 length, staterr;
925 unsigned int i;
926 int cleaned_count = 0;
927 bool cleaned = false;
928 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
929
930 i = rx_ring->next_to_clean;
931 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
932 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
933 buffer_info = &rx_ring->buffer_info[i];
934
935 while (staterr & E1000_RXD_STAT_DD) {
936 struct sk_buff *skb;
937
938 if (*work_done >= work_to_do)
939 break;
940 (*work_done)++;
941 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
942
943 skb = buffer_info->skb;
944 buffer_info->skb = NULL;
945
946 prefetch(skb->data - NET_IP_ALIGN);
947
948 i++;
949 if (i == rx_ring->count)
950 i = 0;
951 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
952 prefetch(next_rxd);
953
954 next_buffer = &rx_ring->buffer_info[i];
955
956 cleaned = true;
957 cleaned_count++;
958 dma_unmap_single(&pdev->dev, buffer_info->dma,
959 adapter->rx_buffer_len, DMA_FROM_DEVICE);
960 buffer_info->dma = 0;
961
962 length = le16_to_cpu(rx_desc->wb.upper.length);
963
964 /* !EOP means multiple descriptors were used to store a single
965 * packet, if that's the case we need to toss it. In fact, we
966 * need to toss every packet with the EOP bit clear and the
967 * next frame that _does_ have the EOP bit set, as it is by
968 * definition only a frame fragment
969 */
970 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
971 adapter->flags2 |= FLAG2_IS_DISCARDING;
972
973 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
974 /* All receives must fit into a single buffer */
975 e_dbg("Receive packet consumed multiple buffers\n");
976 /* recycle */
977 buffer_info->skb = skb;
978 if (staterr & E1000_RXD_STAT_EOP)
979 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
980 goto next_desc;
981 }
982
983 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
984 !(netdev->features & NETIF_F_RXALL))) {
985 /* recycle */
986 buffer_info->skb = skb;
987 goto next_desc;
988 }
989
990 /* adjust length to remove Ethernet CRC */
991 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
992 /* If configured to store CRC, don't subtract FCS,
993 * but keep the FCS bytes out of the total_rx_bytes
994 * counter
995 */
996 if (netdev->features & NETIF_F_RXFCS)
997 total_rx_bytes -= 4;
998 else
999 length -= 4;
1000 }
1001
1002 total_rx_bytes += length;
1003 total_rx_packets++;
1004
1005 /* code added for copybreak, this should improve
1006 * performance for small packets with large amounts
1007 * of reassembly being done in the stack
1008 */
1009 if (length < copybreak) {
1010 struct sk_buff *new_skb =
1011 napi_alloc_skb(&adapter->napi, length);
1012 if (new_skb) {
1013 skb_copy_to_linear_data_offset(new_skb,
1014 -NET_IP_ALIGN,
1015 (skb->data -
1016 NET_IP_ALIGN),
1017 (length +
1018 NET_IP_ALIGN));
1019 /* save the skb in buffer_info as good */
1020 buffer_info->skb = skb;
1021 skb = new_skb;
1022 }
1023 /* else just continue with the old one */
1024 }
1025 /* end copybreak code */
1026 skb_put(skb, length);
1027
1028 /* Receive Checksum Offload */
1029 e1000_rx_checksum(adapter, staterr, skb);
1030
1031 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1032
1033 e1000_receive_skb(adapter, netdev, skb, staterr,
1034 rx_desc->wb.upper.vlan);
1035
1036next_desc:
1037 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1038
1039 /* return some buffers to hardware, one at a time is too slow */
1040 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1041 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1042 GFP_ATOMIC);
1043 cleaned_count = 0;
1044 }
1045
1046 /* use prefetched values */
1047 rx_desc = next_rxd;
1048 buffer_info = next_buffer;
1049
1050 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1051 }
1052 rx_ring->next_to_clean = i;
1053
1054 cleaned_count = e1000_desc_unused(rx_ring);
1055 if (cleaned_count)
1056 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1057
1058 adapter->total_rx_bytes += total_rx_bytes;
1059 adapter->total_rx_packets += total_rx_packets;
1060 return cleaned;
1061}
1062
1063static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1064 struct e1000_buffer *buffer_info,
1065 bool drop)
1066{
1067 struct e1000_adapter *adapter = tx_ring->adapter;
1068
1069 if (buffer_info->dma) {
1070 if (buffer_info->mapped_as_page)
1071 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1072 buffer_info->length, DMA_TO_DEVICE);
1073 else
1074 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1075 buffer_info->length, DMA_TO_DEVICE);
1076 buffer_info->dma = 0;
1077 }
1078 if (buffer_info->skb) {
1079 if (drop)
1080 dev_kfree_skb_any(buffer_info->skb);
1081 else
1082 dev_consume_skb_any(buffer_info->skb);
1083 buffer_info->skb = NULL;
1084 }
1085 buffer_info->time_stamp = 0;
1086}
1087
1088static void e1000_print_hw_hang(struct work_struct *work)
1089{
1090 struct e1000_adapter *adapter = container_of(work,
1091 struct e1000_adapter,
1092 print_hang_task);
1093 struct net_device *netdev = adapter->netdev;
1094 struct e1000_ring *tx_ring = adapter->tx_ring;
1095 unsigned int i = tx_ring->next_to_clean;
1096 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1097 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
1098 struct e1000_hw *hw = &adapter->hw;
1099 u16 phy_status, phy_1000t_status, phy_ext_status;
1100 u16 pci_status;
1101
1102 if (test_bit(__E1000_DOWN, &adapter->state))
1103 return;
1104
1105 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
1106 /* May be block on write-back, flush and detect again
1107 * flush pending descriptor writebacks to memory
1108 */
1109 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1110 /* execute the writes immediately */
1111 e1e_flush();
1112 /* Due to rare timing issues, write to TIDV again to ensure
1113 * the write is successful
1114 */
1115 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1116 /* execute the writes immediately */
1117 e1e_flush();
1118 adapter->tx_hang_recheck = true;
1119 return;
1120 }
1121 adapter->tx_hang_recheck = false;
1122
1123 if (er32(TDH(0)) == er32(TDT(0))) {
1124 e_dbg("false hang detected, ignoring\n");
1125 return;
1126 }
1127
1128 /* Real hang detected */
1129 netif_stop_queue(netdev);
1130
1131 e1e_rphy(hw, MII_BMSR, &phy_status);
1132 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1133 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
1134
1135 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1136
1137 /* detected Hardware unit hang */
1138 e_err("Detected Hardware Unit Hang:\n"
1139 " TDH <%x>\n"
1140 " TDT <%x>\n"
1141 " next_to_use <%x>\n"
1142 " next_to_clean <%x>\n"
1143 "buffer_info[next_to_clean]:\n"
1144 " time_stamp <%lx>\n"
1145 " next_to_watch <%x>\n"
1146 " jiffies <%lx>\n"
1147 " next_to_watch.status <%x>\n"
1148 "MAC Status <%x>\n"
1149 "PHY Status <%x>\n"
1150 "PHY 1000BASE-T Status <%x>\n"
1151 "PHY Extended Status <%x>\n"
1152 "PCI Status <%x>\n",
1153 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1154 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1155 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1156 phy_status, phy_1000t_status, phy_ext_status, pci_status);
1157
1158 e1000e_dump(adapter);
1159
1160 /* Suggest workaround for known h/w issue */
1161 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1162 e_err("Try turning off Tx pause (flow control) via ethtool\n");
1163}
1164
1165/**
1166 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1167 * @work: pointer to work struct
1168 *
1169 * This work function polls the TSYNCTXCTL valid bit to determine when a
1170 * timestamp has been taken for the current stored skb. The timestamp must
1171 * be for this skb because only one such packet is allowed in the queue.
1172 */
1173static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1174{
1175 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1176 tx_hwtstamp_work);
1177 struct e1000_hw *hw = &adapter->hw;
1178
1179 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1180 struct sk_buff *skb = adapter->tx_hwtstamp_skb;
1181 struct skb_shared_hwtstamps shhwtstamps;
1182 u64 txstmp;
1183
1184 txstmp = er32(TXSTMPL);
1185 txstmp |= (u64)er32(TXSTMPH) << 32;
1186
1187 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1188
1189 /* Clear the global tx_hwtstamp_skb pointer and force writes
1190 * prior to notifying the stack of a Tx timestamp.
1191 */
1192 adapter->tx_hwtstamp_skb = NULL;
1193 wmb(); /* force write prior to skb_tstamp_tx */
1194
1195 skb_tstamp_tx(skb, &shhwtstamps);
1196 dev_consume_skb_any(skb);
1197 } else if (time_after(jiffies, adapter->tx_hwtstamp_start
1198 + adapter->tx_timeout_factor * HZ)) {
1199 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1200 adapter->tx_hwtstamp_skb = NULL;
1201 adapter->tx_hwtstamp_timeouts++;
1202 e_warn("clearing Tx timestamp hang\n");
1203 } else {
1204 /* reschedule to check later */
1205 schedule_work(&adapter->tx_hwtstamp_work);
1206 }
1207}
1208
1209/**
1210 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1211 * @tx_ring: Tx descriptor ring
1212 *
1213 * the return value indicates whether actual cleaning was done, there
1214 * is no guarantee that everything was cleaned
1215 **/
1216static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
1217{
1218 struct e1000_adapter *adapter = tx_ring->adapter;
1219 struct net_device *netdev = adapter->netdev;
1220 struct e1000_hw *hw = &adapter->hw;
1221 struct e1000_tx_desc *tx_desc, *eop_desc;
1222 struct e1000_buffer *buffer_info;
1223 unsigned int i, eop;
1224 unsigned int count = 0;
1225 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
1226 unsigned int bytes_compl = 0, pkts_compl = 0;
1227
1228 i = tx_ring->next_to_clean;
1229 eop = tx_ring->buffer_info[i].next_to_watch;
1230 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1231
1232 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1233 (count < tx_ring->count)) {
1234 bool cleaned = false;
1235
1236 dma_rmb(); /* read buffer_info after eop_desc */
1237 for (; !cleaned; count++) {
1238 tx_desc = E1000_TX_DESC(*tx_ring, i);
1239 buffer_info = &tx_ring->buffer_info[i];
1240 cleaned = (i == eop);
1241
1242 if (cleaned) {
1243 total_tx_packets += buffer_info->segs;
1244 total_tx_bytes += buffer_info->bytecount;
1245 if (buffer_info->skb) {
1246 bytes_compl += buffer_info->skb->len;
1247 pkts_compl++;
1248 }
1249 }
1250
1251 e1000_put_txbuf(tx_ring, buffer_info, false);
1252 tx_desc->upper.data = 0;
1253
1254 i++;
1255 if (i == tx_ring->count)
1256 i = 0;
1257 }
1258
1259 if (i == tx_ring->next_to_use)
1260 break;
1261 eop = tx_ring->buffer_info[i].next_to_watch;
1262 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1263 }
1264
1265 tx_ring->next_to_clean = i;
1266
1267 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1268
1269#define TX_WAKE_THRESHOLD 32
1270 if (count && netif_carrier_ok(netdev) &&
1271 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
1272 /* Make sure that anybody stopping the queue after this
1273 * sees the new next_to_clean.
1274 */
1275 smp_mb();
1276
1277 if (netif_queue_stopped(netdev) &&
1278 !(test_bit(__E1000_DOWN, &adapter->state))) {
1279 netif_wake_queue(netdev);
1280 ++adapter->restart_queue;
1281 }
1282 }
1283
1284 if (adapter->detect_tx_hung) {
1285 /* Detect a transmit hang in hardware, this serializes the
1286 * check with the clearing of time_stamp and movement of i
1287 */
1288 adapter->detect_tx_hung = false;
1289 if (tx_ring->buffer_info[i].time_stamp &&
1290 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
1291 + (adapter->tx_timeout_factor * HZ)) &&
1292 !(er32(STATUS) & E1000_STATUS_TXOFF))
1293 schedule_work(&adapter->print_hang_task);
1294 else
1295 adapter->tx_hang_recheck = false;
1296 }
1297 adapter->total_tx_bytes += total_tx_bytes;
1298 adapter->total_tx_packets += total_tx_packets;
1299 return count < tx_ring->count;
1300}
1301
1302/**
1303 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1304 * @rx_ring: Rx descriptor ring
1305 * @work_done: output parameter for indicating completed work
1306 * @work_to_do: how many packets we can clean
1307 *
1308 * the return value indicates whether actual cleaning was done, there
1309 * is no guarantee that everything was cleaned
1310 **/
1311static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1312 int work_to_do)
1313{
1314 struct e1000_adapter *adapter = rx_ring->adapter;
1315 struct e1000_hw *hw = &adapter->hw;
1316 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1317 struct net_device *netdev = adapter->netdev;
1318 struct pci_dev *pdev = adapter->pdev;
1319 struct e1000_buffer *buffer_info, *next_buffer;
1320 struct e1000_ps_page *ps_page;
1321 struct sk_buff *skb;
1322 unsigned int i, j;
1323 u32 length, staterr;
1324 int cleaned_count = 0;
1325 bool cleaned = false;
1326 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1327
1328 i = rx_ring->next_to_clean;
1329 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1330 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1331 buffer_info = &rx_ring->buffer_info[i];
1332
1333 while (staterr & E1000_RXD_STAT_DD) {
1334 if (*work_done >= work_to_do)
1335 break;
1336 (*work_done)++;
1337 skb = buffer_info->skb;
1338 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1339
1340 /* in the packet split case this is header only */
1341 prefetch(skb->data - NET_IP_ALIGN);
1342
1343 i++;
1344 if (i == rx_ring->count)
1345 i = 0;
1346 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1347 prefetch(next_rxd);
1348
1349 next_buffer = &rx_ring->buffer_info[i];
1350
1351 cleaned = true;
1352 cleaned_count++;
1353 dma_unmap_single(&pdev->dev, buffer_info->dma,
1354 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
1355 buffer_info->dma = 0;
1356
1357 /* see !EOP comment in other Rx routine */
1358 if (!(staterr & E1000_RXD_STAT_EOP))
1359 adapter->flags2 |= FLAG2_IS_DISCARDING;
1360
1361 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
1362 e_dbg("Packet Split buffers didn't pick up the full packet\n");
1363 dev_kfree_skb_irq(skb);
1364 if (staterr & E1000_RXD_STAT_EOP)
1365 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1366 goto next_desc;
1367 }
1368
1369 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1370 !(netdev->features & NETIF_F_RXALL))) {
1371 dev_kfree_skb_irq(skb);
1372 goto next_desc;
1373 }
1374
1375 length = le16_to_cpu(rx_desc->wb.middle.length0);
1376
1377 if (!length) {
1378 e_dbg("Last part of the packet spanning multiple descriptors\n");
1379 dev_kfree_skb_irq(skb);
1380 goto next_desc;
1381 }
1382
1383 /* Good Receive */
1384 skb_put(skb, length);
1385
1386 {
1387 /* this looks ugly, but it seems compiler issues make
1388 * it more efficient than reusing j
1389 */
1390 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
1391
1392 /* page alloc/put takes too long and effects small
1393 * packet throughput, so unsplit small packets and
1394 * save the alloc/put
1395 */
1396 if (l1 && (l1 <= copybreak) &&
1397 ((length + l1) <= adapter->rx_ps_bsize0)) {
1398 ps_page = &buffer_info->ps_pages[0];
1399
1400 dma_sync_single_for_cpu(&pdev->dev,
1401 ps_page->dma,
1402 PAGE_SIZE,
1403 DMA_FROM_DEVICE);
1404 memcpy(skb_tail_pointer(skb),
1405 page_address(ps_page->page), l1);
1406 dma_sync_single_for_device(&pdev->dev,
1407 ps_page->dma,
1408 PAGE_SIZE,
1409 DMA_FROM_DEVICE);
1410
1411 /* remove the CRC */
1412 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1413 if (!(netdev->features & NETIF_F_RXFCS))
1414 l1 -= 4;
1415 }
1416
1417 skb_put(skb, l1);
1418 goto copydone;
1419 } /* if */
1420 }
1421
1422 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1423 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1424 if (!length)
1425 break;
1426
1427 ps_page = &buffer_info->ps_pages[j];
1428 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1429 DMA_FROM_DEVICE);
1430 ps_page->dma = 0;
1431 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1432 ps_page->page = NULL;
1433 skb->len += length;
1434 skb->data_len += length;
1435 skb->truesize += PAGE_SIZE;
1436 }
1437
1438 /* strip the ethernet crc, problem is we're using pages now so
1439 * this whole operation can get a little cpu intensive
1440 */
1441 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1442 if (!(netdev->features & NETIF_F_RXFCS))
1443 pskb_trim(skb, skb->len - 4);
1444 }
1445
1446copydone:
1447 total_rx_bytes += skb->len;
1448 total_rx_packets++;
1449
1450 e1000_rx_checksum(adapter, staterr, skb);
1451
1452 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1453
1454 if (rx_desc->wb.upper.header_status &
1455 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1456 adapter->rx_hdr_split++;
1457
1458 e1000_receive_skb(adapter, netdev, skb, staterr,
1459 rx_desc->wb.middle.vlan);
1460
1461next_desc:
1462 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1463 buffer_info->skb = NULL;
1464
1465 /* return some buffers to hardware, one at a time is too slow */
1466 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1467 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1468 GFP_ATOMIC);
1469 cleaned_count = 0;
1470 }
1471
1472 /* use prefetched values */
1473 rx_desc = next_rxd;
1474 buffer_info = next_buffer;
1475
1476 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1477 }
1478 rx_ring->next_to_clean = i;
1479
1480 cleaned_count = e1000_desc_unused(rx_ring);
1481 if (cleaned_count)
1482 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1483
1484 adapter->total_rx_bytes += total_rx_bytes;
1485 adapter->total_rx_packets += total_rx_packets;
1486 return cleaned;
1487}
1488
1489static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1490 u16 length)
1491{
1492 bi->page = NULL;
1493 skb->len += length;
1494 skb->data_len += length;
1495 skb->truesize += PAGE_SIZE;
1496}
1497
1498/**
1499 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1500 * @rx_ring: Rx descriptor ring
1501 * @work_done: output parameter for indicating completed work
1502 * @work_to_do: how many packets we can clean
1503 *
1504 * the return value indicates whether actual cleaning was done, there
1505 * is no guarantee that everything was cleaned
1506 **/
1507static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1508 int work_to_do)
1509{
1510 struct e1000_adapter *adapter = rx_ring->adapter;
1511 struct net_device *netdev = adapter->netdev;
1512 struct pci_dev *pdev = adapter->pdev;
1513 union e1000_rx_desc_extended *rx_desc, *next_rxd;
1514 struct e1000_buffer *buffer_info, *next_buffer;
1515 u32 length, staterr;
1516 unsigned int i;
1517 int cleaned_count = 0;
1518 bool cleaned = false;
1519 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1520 struct skb_shared_info *shinfo;
1521
1522 i = rx_ring->next_to_clean;
1523 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1524 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1525 buffer_info = &rx_ring->buffer_info[i];
1526
1527 while (staterr & E1000_RXD_STAT_DD) {
1528 struct sk_buff *skb;
1529
1530 if (*work_done >= work_to_do)
1531 break;
1532 (*work_done)++;
1533 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1534
1535 skb = buffer_info->skb;
1536 buffer_info->skb = NULL;
1537
1538 ++i;
1539 if (i == rx_ring->count)
1540 i = 0;
1541 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
1542 prefetch(next_rxd);
1543
1544 next_buffer = &rx_ring->buffer_info[i];
1545
1546 cleaned = true;
1547 cleaned_count++;
1548 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1549 DMA_FROM_DEVICE);
1550 buffer_info->dma = 0;
1551
1552 length = le16_to_cpu(rx_desc->wb.upper.length);
1553
1554 /* errors is only valid for DD + EOP descriptors */
1555 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
1556 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1557 !(netdev->features & NETIF_F_RXALL)))) {
1558 /* recycle both page and skb */
1559 buffer_info->skb = skb;
1560 /* an error means any chain goes out the window too */
1561 if (rx_ring->rx_skb_top)
1562 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1563 rx_ring->rx_skb_top = NULL;
1564 goto next_desc;
1565 }
1566#define rxtop (rx_ring->rx_skb_top)
1567 if (!(staterr & E1000_RXD_STAT_EOP)) {
1568 /* this descriptor is only the beginning (or middle) */
1569 if (!rxtop) {
1570 /* this is the beginning of a chain */
1571 rxtop = skb;
1572 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1573 0, length);
1574 } else {
1575 /* this is the middle of a chain */
1576 shinfo = skb_shinfo(rxtop);
1577 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1578 buffer_info->page, 0,
1579 length);
1580 /* re-use the skb, only consumed the page */
1581 buffer_info->skb = skb;
1582 }
1583 e1000_consume_page(buffer_info, rxtop, length);
1584 goto next_desc;
1585 } else {
1586 if (rxtop) {
1587 /* end of the chain */
1588 shinfo = skb_shinfo(rxtop);
1589 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1590 buffer_info->page, 0,
1591 length);
1592 /* re-use the current skb, we only consumed the
1593 * page
1594 */
1595 buffer_info->skb = skb;
1596 skb = rxtop;
1597 rxtop = NULL;
1598 e1000_consume_page(buffer_info, skb, length);
1599 } else {
1600 /* no chain, got EOP, this buf is the packet
1601 * copybreak to save the put_page/alloc_page
1602 */
1603 if (length <= copybreak &&
1604 skb_tailroom(skb) >= length) {
1605 memcpy(skb_tail_pointer(skb),
1606 page_address(buffer_info->page),
1607 length);
1608 /* re-use the page, so don't erase
1609 * buffer_info->page
1610 */
1611 skb_put(skb, length);
1612 } else {
1613 skb_fill_page_desc(skb, 0,
1614 buffer_info->page, 0,
1615 length);
1616 e1000_consume_page(buffer_info, skb,
1617 length);
1618 }
1619 }
1620 }
1621
1622 /* Receive Checksum Offload */
1623 e1000_rx_checksum(adapter, staterr, skb);
1624
1625 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1626
1627 /* probably a little skewed due to removing CRC */
1628 total_rx_bytes += skb->len;
1629 total_rx_packets++;
1630
1631 /* eth type trans needs skb->data to point to something */
1632 if (!pskb_may_pull(skb, ETH_HLEN)) {
1633 e_err("pskb_may_pull failed.\n");
1634 dev_kfree_skb_irq(skb);
1635 goto next_desc;
1636 }
1637
1638 e1000_receive_skb(adapter, netdev, skb, staterr,
1639 rx_desc->wb.upper.vlan);
1640
1641next_desc:
1642 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1643
1644 /* return some buffers to hardware, one at a time is too slow */
1645 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
1646 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1647 GFP_ATOMIC);
1648 cleaned_count = 0;
1649 }
1650
1651 /* use prefetched values */
1652 rx_desc = next_rxd;
1653 buffer_info = next_buffer;
1654
1655 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1656 }
1657 rx_ring->next_to_clean = i;
1658
1659 cleaned_count = e1000_desc_unused(rx_ring);
1660 if (cleaned_count)
1661 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1662
1663 adapter->total_rx_bytes += total_rx_bytes;
1664 adapter->total_rx_packets += total_rx_packets;
1665 return cleaned;
1666}
1667
1668/**
1669 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1670 * @rx_ring: Rx descriptor ring
1671 **/
1672static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
1673{
1674 struct e1000_adapter *adapter = rx_ring->adapter;
1675 struct e1000_buffer *buffer_info;
1676 struct e1000_ps_page *ps_page;
1677 struct pci_dev *pdev = adapter->pdev;
1678 unsigned int i, j;
1679
1680 /* Free all the Rx ring sk_buffs */
1681 for (i = 0; i < rx_ring->count; i++) {
1682 buffer_info = &rx_ring->buffer_info[i];
1683 if (buffer_info->dma) {
1684 if (adapter->clean_rx == e1000_clean_rx_irq)
1685 dma_unmap_single(&pdev->dev, buffer_info->dma,
1686 adapter->rx_buffer_len,
1687 DMA_FROM_DEVICE);
1688 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
1689 dma_unmap_page(&pdev->dev, buffer_info->dma,
1690 PAGE_SIZE, DMA_FROM_DEVICE);
1691 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
1692 dma_unmap_single(&pdev->dev, buffer_info->dma,
1693 adapter->rx_ps_bsize0,
1694 DMA_FROM_DEVICE);
1695 buffer_info->dma = 0;
1696 }
1697
1698 if (buffer_info->page) {
1699 put_page(buffer_info->page);
1700 buffer_info->page = NULL;
1701 }
1702
1703 if (buffer_info->skb) {
1704 dev_kfree_skb(buffer_info->skb);
1705 buffer_info->skb = NULL;
1706 }
1707
1708 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1709 ps_page = &buffer_info->ps_pages[j];
1710 if (!ps_page->page)
1711 break;
1712 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1713 DMA_FROM_DEVICE);
1714 ps_page->dma = 0;
1715 put_page(ps_page->page);
1716 ps_page->page = NULL;
1717 }
1718 }
1719
1720 /* there also may be some cached data from a chained receive */
1721 if (rx_ring->rx_skb_top) {
1722 dev_kfree_skb(rx_ring->rx_skb_top);
1723 rx_ring->rx_skb_top = NULL;
1724 }
1725
1726 /* Zero out the descriptor ring */
1727 memset(rx_ring->desc, 0, rx_ring->size);
1728
1729 rx_ring->next_to_clean = 0;
1730 rx_ring->next_to_use = 0;
1731 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1732}
1733
1734static void e1000e_downshift_workaround(struct work_struct *work)
1735{
1736 struct e1000_adapter *adapter = container_of(work,
1737 struct e1000_adapter,
1738 downshift_task);
1739
1740 if (test_bit(__E1000_DOWN, &adapter->state))
1741 return;
1742
1743 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1744}
1745
1746/**
1747 * e1000_intr_msi - Interrupt Handler
1748 * @irq: interrupt number
1749 * @data: pointer to a network interface device structure
1750 **/
1751static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
1752{
1753 struct net_device *netdev = data;
1754 struct e1000_adapter *adapter = netdev_priv(netdev);
1755 struct e1000_hw *hw = &adapter->hw;
1756 u32 icr = er32(ICR);
1757
1758 /* read ICR disables interrupts using IAM */
1759 if (icr & E1000_ICR_LSC) {
1760 hw->mac.get_link_status = true;
1761 /* ICH8 workaround-- Call gig speed drop workaround on cable
1762 * disconnect (LSC) before accessing any PHY registers
1763 */
1764 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1765 (!(er32(STATUS) & E1000_STATUS_LU)))
1766 schedule_work(&adapter->downshift_task);
1767
1768 /* 80003ES2LAN workaround-- For packet buffer work-around on
1769 * link down event; disable receives here in the ISR and reset
1770 * adapter in watchdog
1771 */
1772 if (netif_carrier_ok(netdev) &&
1773 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1774 /* disable receives */
1775 u32 rctl = er32(RCTL);
1776
1777 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1778 adapter->flags |= FLAG_RESTART_NOW;
1779 }
1780 /* guard against interrupt when we're going down */
1781 if (!test_bit(__E1000_DOWN, &adapter->state))
1782 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1783 }
1784
1785 /* Reset on uncorrectable ECC error */
1786 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1787 u32 pbeccsts = er32(PBECCSTS);
1788
1789 adapter->corr_errors +=
1790 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1791 adapter->uncorr_errors +=
1792 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1793 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1794
1795 /* Do the reset outside of interrupt context */
1796 schedule_work(&adapter->reset_task);
1797
1798 /* return immediately since reset is imminent */
1799 return IRQ_HANDLED;
1800 }
1801
1802 if (napi_schedule_prep(&adapter->napi)) {
1803 adapter->total_tx_bytes = 0;
1804 adapter->total_tx_packets = 0;
1805 adapter->total_rx_bytes = 0;
1806 adapter->total_rx_packets = 0;
1807 __napi_schedule(&adapter->napi);
1808 }
1809
1810 return IRQ_HANDLED;
1811}
1812
1813/**
1814 * e1000_intr - Interrupt Handler
1815 * @irq: interrupt number
1816 * @data: pointer to a network interface device structure
1817 **/
1818static irqreturn_t e1000_intr(int __always_unused irq, void *data)
1819{
1820 struct net_device *netdev = data;
1821 struct e1000_adapter *adapter = netdev_priv(netdev);
1822 struct e1000_hw *hw = &adapter->hw;
1823 u32 rctl, icr = er32(ICR);
1824
1825 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
1826 return IRQ_NONE; /* Not our interrupt */
1827
1828 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1829 * not set, then the adapter didn't send an interrupt
1830 */
1831 if (!(icr & E1000_ICR_INT_ASSERTED))
1832 return IRQ_NONE;
1833
1834 /* Interrupt Auto-Mask...upon reading ICR,
1835 * interrupts are masked. No need for the
1836 * IMC write
1837 */
1838
1839 if (icr & E1000_ICR_LSC) {
1840 hw->mac.get_link_status = true;
1841 /* ICH8 workaround-- Call gig speed drop workaround on cable
1842 * disconnect (LSC) before accessing any PHY registers
1843 */
1844 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1845 (!(er32(STATUS) & E1000_STATUS_LU)))
1846 schedule_work(&adapter->downshift_task);
1847
1848 /* 80003ES2LAN workaround--
1849 * For packet buffer work-around on link down event;
1850 * disable receives here in the ISR and
1851 * reset adapter in watchdog
1852 */
1853 if (netif_carrier_ok(netdev) &&
1854 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1855 /* disable receives */
1856 rctl = er32(RCTL);
1857 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1858 adapter->flags |= FLAG_RESTART_NOW;
1859 }
1860 /* guard against interrupt when we're going down */
1861 if (!test_bit(__E1000_DOWN, &adapter->state))
1862 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1863 }
1864
1865 /* Reset on uncorrectable ECC error */
1866 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1867 u32 pbeccsts = er32(PBECCSTS);
1868
1869 adapter->corr_errors +=
1870 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1871 adapter->uncorr_errors +=
1872 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1873 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1874
1875 /* Do the reset outside of interrupt context */
1876 schedule_work(&adapter->reset_task);
1877
1878 /* return immediately since reset is imminent */
1879 return IRQ_HANDLED;
1880 }
1881
1882 if (napi_schedule_prep(&adapter->napi)) {
1883 adapter->total_tx_bytes = 0;
1884 adapter->total_tx_packets = 0;
1885 adapter->total_rx_bytes = 0;
1886 adapter->total_rx_packets = 0;
1887 __napi_schedule(&adapter->napi);
1888 }
1889
1890 return IRQ_HANDLED;
1891}
1892
1893static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
1894{
1895 struct net_device *netdev = data;
1896 struct e1000_adapter *adapter = netdev_priv(netdev);
1897 struct e1000_hw *hw = &adapter->hw;
1898 u32 icr = er32(ICR);
1899
1900 if (icr & adapter->eiac_mask)
1901 ew32(ICS, (icr & adapter->eiac_mask));
1902
1903 if (icr & E1000_ICR_LSC) {
1904 hw->mac.get_link_status = true;
1905 /* guard against interrupt when we're going down */
1906 if (!test_bit(__E1000_DOWN, &adapter->state))
1907 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1908 }
1909
1910 if (!test_bit(__E1000_DOWN, &adapter->state))
1911 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK);
1912
1913 return IRQ_HANDLED;
1914}
1915
1916static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
1917{
1918 struct net_device *netdev = data;
1919 struct e1000_adapter *adapter = netdev_priv(netdev);
1920 struct e1000_hw *hw = &adapter->hw;
1921 struct e1000_ring *tx_ring = adapter->tx_ring;
1922
1923 adapter->total_tx_bytes = 0;
1924 adapter->total_tx_packets = 0;
1925
1926 if (!e1000_clean_tx_irq(tx_ring))
1927 /* Ring was not completely cleaned, so fire another interrupt */
1928 ew32(ICS, tx_ring->ims_val);
1929
1930 if (!test_bit(__E1000_DOWN, &adapter->state))
1931 ew32(IMS, adapter->tx_ring->ims_val);
1932
1933 return IRQ_HANDLED;
1934}
1935
1936static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
1937{
1938 struct net_device *netdev = data;
1939 struct e1000_adapter *adapter = netdev_priv(netdev);
1940 struct e1000_ring *rx_ring = adapter->rx_ring;
1941
1942 /* Write the ITR value calculated at the end of the
1943 * previous interrupt.
1944 */
1945 if (rx_ring->set_itr) {
1946 u32 itr = rx_ring->itr_val ?
1947 1000000000 / (rx_ring->itr_val * 256) : 0;
1948
1949 writel(itr, rx_ring->itr_register);
1950 rx_ring->set_itr = 0;
1951 }
1952
1953 if (napi_schedule_prep(&adapter->napi)) {
1954 adapter->total_rx_bytes = 0;
1955 adapter->total_rx_packets = 0;
1956 __napi_schedule(&adapter->napi);
1957 }
1958 return IRQ_HANDLED;
1959}
1960
1961/**
1962 * e1000_configure_msix - Configure MSI-X hardware
1963 * @adapter: board private structure
1964 *
1965 * e1000_configure_msix sets up the hardware to properly
1966 * generate MSI-X interrupts.
1967 **/
1968static void e1000_configure_msix(struct e1000_adapter *adapter)
1969{
1970 struct e1000_hw *hw = &adapter->hw;
1971 struct e1000_ring *rx_ring = adapter->rx_ring;
1972 struct e1000_ring *tx_ring = adapter->tx_ring;
1973 int vector = 0;
1974 u32 ctrl_ext, ivar = 0;
1975
1976 adapter->eiac_mask = 0;
1977
1978 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1979 if (hw->mac.type == e1000_82574) {
1980 u32 rfctl = er32(RFCTL);
1981
1982 rfctl |= E1000_RFCTL_ACK_DIS;
1983 ew32(RFCTL, rfctl);
1984 }
1985
1986 /* Configure Rx vector */
1987 rx_ring->ims_val = E1000_IMS_RXQ0;
1988 adapter->eiac_mask |= rx_ring->ims_val;
1989 if (rx_ring->itr_val)
1990 writel(1000000000 / (rx_ring->itr_val * 256),
1991 rx_ring->itr_register);
1992 else
1993 writel(1, rx_ring->itr_register);
1994 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1995
1996 /* Configure Tx vector */
1997 tx_ring->ims_val = E1000_IMS_TXQ0;
1998 vector++;
1999 if (tx_ring->itr_val)
2000 writel(1000000000 / (tx_ring->itr_val * 256),
2001 tx_ring->itr_register);
2002 else
2003 writel(1, tx_ring->itr_register);
2004 adapter->eiac_mask |= tx_ring->ims_val;
2005 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
2006
2007 /* set vector for Other Causes, e.g. link changes */
2008 vector++;
2009 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
2010 if (rx_ring->itr_val)
2011 writel(1000000000 / (rx_ring->itr_val * 256),
2012 hw->hw_addr + E1000_EITR_82574(vector));
2013 else
2014 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
2015
2016 /* Cause Tx interrupts on every write back */
2017 ivar |= BIT(31);
2018
2019 ew32(IVAR, ivar);
2020
2021 /* enable MSI-X PBA support */
2022 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME;
2023 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME;
2024 ew32(CTRL_EXT, ctrl_ext);
2025 e1e_flush();
2026}
2027
2028void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2029{
2030 if (adapter->msix_entries) {
2031 pci_disable_msix(adapter->pdev);
2032 kfree(adapter->msix_entries);
2033 adapter->msix_entries = NULL;
2034 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2035 pci_disable_msi(adapter->pdev);
2036 adapter->flags &= ~FLAG_MSI_ENABLED;
2037 }
2038}
2039
2040/**
2041 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2042 * @adapter: board private structure
2043 *
2044 * Attempt to configure interrupts using the best available
2045 * capabilities of the hardware and kernel.
2046 **/
2047void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2048{
2049 int err;
2050 int i;
2051
2052 switch (adapter->int_mode) {
2053 case E1000E_INT_MODE_MSIX:
2054 if (adapter->flags & FLAG_HAS_MSIX) {
2055 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2056 adapter->msix_entries = kcalloc(adapter->num_vectors,
2057 sizeof(struct
2058 msix_entry),
2059 GFP_KERNEL);
2060 if (adapter->msix_entries) {
2061 struct e1000_adapter *a = adapter;
2062
2063 for (i = 0; i < adapter->num_vectors; i++)
2064 adapter->msix_entries[i].entry = i;
2065
2066 err = pci_enable_msix_range(a->pdev,
2067 a->msix_entries,
2068 a->num_vectors,
2069 a->num_vectors);
2070 if (err > 0)
2071 return;
2072 }
2073 /* MSI-X failed, so fall through and try MSI */
2074 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
2075 e1000e_reset_interrupt_capability(adapter);
2076 }
2077 adapter->int_mode = E1000E_INT_MODE_MSI;
2078 fallthrough;
2079 case E1000E_INT_MODE_MSI:
2080 if (!pci_enable_msi(adapter->pdev)) {
2081 adapter->flags |= FLAG_MSI_ENABLED;
2082 } else {
2083 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2084 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
2085 }
2086 fallthrough;
2087 case E1000E_INT_MODE_LEGACY:
2088 /* Don't do anything; this is the system default */
2089 break;
2090 }
2091
2092 /* store the number of vectors being used */
2093 adapter->num_vectors = 1;
2094}
2095
2096/**
2097 * e1000_request_msix - Initialize MSI-X interrupts
2098 * @adapter: board private structure
2099 *
2100 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2101 * kernel.
2102 **/
2103static int e1000_request_msix(struct e1000_adapter *adapter)
2104{
2105 struct net_device *netdev = adapter->netdev;
2106 int err = 0, vector = 0;
2107
2108 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2109 snprintf(adapter->rx_ring->name,
2110 sizeof(adapter->rx_ring->name) - 1,
2111 "%.14s-rx-0", netdev->name);
2112 else
2113 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2114 err = request_irq(adapter->msix_entries[vector].vector,
2115 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
2116 netdev);
2117 if (err)
2118 return err;
2119 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2120 E1000_EITR_82574(vector);
2121 adapter->rx_ring->itr_val = adapter->itr;
2122 vector++;
2123
2124 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2125 snprintf(adapter->tx_ring->name,
2126 sizeof(adapter->tx_ring->name) - 1,
2127 "%.14s-tx-0", netdev->name);
2128 else
2129 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2130 err = request_irq(adapter->msix_entries[vector].vector,
2131 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
2132 netdev);
2133 if (err)
2134 return err;
2135 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2136 E1000_EITR_82574(vector);
2137 adapter->tx_ring->itr_val = adapter->itr;
2138 vector++;
2139
2140 err = request_irq(adapter->msix_entries[vector].vector,
2141 e1000_msix_other, 0, netdev->name, netdev);
2142 if (err)
2143 return err;
2144
2145 e1000_configure_msix(adapter);
2146
2147 return 0;
2148}
2149
2150/**
2151 * e1000_request_irq - initialize interrupts
2152 * @adapter: board private structure
2153 *
2154 * Attempts to configure interrupts using the best available
2155 * capabilities of the hardware and kernel.
2156 **/
2157static int e1000_request_irq(struct e1000_adapter *adapter)
2158{
2159 struct net_device *netdev = adapter->netdev;
2160 int err;
2161
2162 if (adapter->msix_entries) {
2163 err = e1000_request_msix(adapter);
2164 if (!err)
2165 return err;
2166 /* fall back to MSI */
2167 e1000e_reset_interrupt_capability(adapter);
2168 adapter->int_mode = E1000E_INT_MODE_MSI;
2169 e1000e_set_interrupt_capability(adapter);
2170 }
2171 if (adapter->flags & FLAG_MSI_ENABLED) {
2172 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
2173 netdev->name, netdev);
2174 if (!err)
2175 return err;
2176
2177 /* fall back to legacy interrupt */
2178 e1000e_reset_interrupt_capability(adapter);
2179 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2180 }
2181
2182 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
2183 netdev->name, netdev);
2184 if (err)
2185 e_err("Unable to allocate interrupt, Error: %d\n", err);
2186
2187 return err;
2188}
2189
2190static void e1000_free_irq(struct e1000_adapter *adapter)
2191{
2192 struct net_device *netdev = adapter->netdev;
2193
2194 if (adapter->msix_entries) {
2195 int vector = 0;
2196
2197 free_irq(adapter->msix_entries[vector].vector, netdev);
2198 vector++;
2199
2200 free_irq(adapter->msix_entries[vector].vector, netdev);
2201 vector++;
2202
2203 /* Other Causes interrupt vector */
2204 free_irq(adapter->msix_entries[vector].vector, netdev);
2205 return;
2206 }
2207
2208 free_irq(adapter->pdev->irq, netdev);
2209}
2210
2211/**
2212 * e1000_irq_disable - Mask off interrupt generation on the NIC
2213 * @adapter: board private structure
2214 **/
2215static void e1000_irq_disable(struct e1000_adapter *adapter)
2216{
2217 struct e1000_hw *hw = &adapter->hw;
2218
2219 ew32(IMC, ~0);
2220 if (adapter->msix_entries)
2221 ew32(EIAC_82574, 0);
2222 e1e_flush();
2223
2224 if (adapter->msix_entries) {
2225 int i;
2226
2227 for (i = 0; i < adapter->num_vectors; i++)
2228 synchronize_irq(adapter->msix_entries[i].vector);
2229 } else {
2230 synchronize_irq(adapter->pdev->irq);
2231 }
2232}
2233
2234/**
2235 * e1000_irq_enable - Enable default interrupt generation settings
2236 * @adapter: board private structure
2237 **/
2238static void e1000_irq_enable(struct e1000_adapter *adapter)
2239{
2240 struct e1000_hw *hw = &adapter->hw;
2241
2242 if (adapter->msix_entries) {
2243 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2244 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER |
2245 IMS_OTHER_MASK);
2246 } else if (hw->mac.type >= e1000_pch_lpt) {
2247 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
2248 } else {
2249 ew32(IMS, IMS_ENABLE_MASK);
2250 }
2251 e1e_flush();
2252}
2253
2254/**
2255 * e1000e_get_hw_control - get control of the h/w from f/w
2256 * @adapter: address of board private structure
2257 *
2258 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2259 * For ASF and Pass Through versions of f/w this means that
2260 * the driver is loaded. For AMT version (only with 82573)
2261 * of the f/w this means that the network i/f is open.
2262 **/
2263void e1000e_get_hw_control(struct e1000_adapter *adapter)
2264{
2265 struct e1000_hw *hw = &adapter->hw;
2266 u32 ctrl_ext;
2267 u32 swsm;
2268
2269 /* Let firmware know the driver has taken over */
2270 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2271 swsm = er32(SWSM);
2272 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2273 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2274 ctrl_ext = er32(CTRL_EXT);
2275 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2276 }
2277}
2278
2279/**
2280 * e1000e_release_hw_control - release control of the h/w to f/w
2281 * @adapter: address of board private structure
2282 *
2283 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2284 * For ASF and Pass Through versions of f/w this means that the
2285 * driver is no longer loaded. For AMT version (only with 82573) i
2286 * of the f/w this means that the network i/f is closed.
2287 *
2288 **/
2289void e1000e_release_hw_control(struct e1000_adapter *adapter)
2290{
2291 struct e1000_hw *hw = &adapter->hw;
2292 u32 ctrl_ext;
2293 u32 swsm;
2294
2295 /* Let firmware taken over control of h/w */
2296 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2297 swsm = er32(SWSM);
2298 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2299 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2300 ctrl_ext = er32(CTRL_EXT);
2301 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2302 }
2303}
2304
2305/**
2306 * e1000_alloc_ring_dma - allocate memory for a ring structure
2307 * @adapter: board private structure
2308 * @ring: ring struct for which to allocate dma
2309 **/
2310static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2311 struct e1000_ring *ring)
2312{
2313 struct pci_dev *pdev = adapter->pdev;
2314
2315 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2316 GFP_KERNEL);
2317 if (!ring->desc)
2318 return -ENOMEM;
2319
2320 return 0;
2321}
2322
2323/**
2324 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2325 * @tx_ring: Tx descriptor ring
2326 *
2327 * Return 0 on success, negative on failure
2328 **/
2329int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
2330{
2331 struct e1000_adapter *adapter = tx_ring->adapter;
2332 int err = -ENOMEM, size;
2333
2334 size = sizeof(struct e1000_buffer) * tx_ring->count;
2335 tx_ring->buffer_info = vzalloc(size);
2336 if (!tx_ring->buffer_info)
2337 goto err;
2338
2339 /* round up to nearest 4K */
2340 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2341 tx_ring->size = ALIGN(tx_ring->size, 4096);
2342
2343 err = e1000_alloc_ring_dma(adapter, tx_ring);
2344 if (err)
2345 goto err;
2346
2347 tx_ring->next_to_use = 0;
2348 tx_ring->next_to_clean = 0;
2349
2350 return 0;
2351err:
2352 vfree(tx_ring->buffer_info);
2353 e_err("Unable to allocate memory for the transmit descriptor ring\n");
2354 return err;
2355}
2356
2357/**
2358 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2359 * @rx_ring: Rx descriptor ring
2360 *
2361 * Returns 0 on success, negative on failure
2362 **/
2363int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
2364{
2365 struct e1000_adapter *adapter = rx_ring->adapter;
2366 struct e1000_buffer *buffer_info;
2367 int i, size, desc_len, err = -ENOMEM;
2368
2369 size = sizeof(struct e1000_buffer) * rx_ring->count;
2370 rx_ring->buffer_info = vzalloc(size);
2371 if (!rx_ring->buffer_info)
2372 goto err;
2373
2374 for (i = 0; i < rx_ring->count; i++) {
2375 buffer_info = &rx_ring->buffer_info[i];
2376 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2377 sizeof(struct e1000_ps_page),
2378 GFP_KERNEL);
2379 if (!buffer_info->ps_pages)
2380 goto err_pages;
2381 }
2382
2383 desc_len = sizeof(union e1000_rx_desc_packet_split);
2384
2385 /* Round up to nearest 4K */
2386 rx_ring->size = rx_ring->count * desc_len;
2387 rx_ring->size = ALIGN(rx_ring->size, 4096);
2388
2389 err = e1000_alloc_ring_dma(adapter, rx_ring);
2390 if (err)
2391 goto err_pages;
2392
2393 rx_ring->next_to_clean = 0;
2394 rx_ring->next_to_use = 0;
2395 rx_ring->rx_skb_top = NULL;
2396
2397 return 0;
2398
2399err_pages:
2400 for (i = 0; i < rx_ring->count; i++) {
2401 buffer_info = &rx_ring->buffer_info[i];
2402 kfree(buffer_info->ps_pages);
2403 }
2404err:
2405 vfree(rx_ring->buffer_info);
2406 e_err("Unable to allocate memory for the receive descriptor ring\n");
2407 return err;
2408}
2409
2410/**
2411 * e1000_clean_tx_ring - Free Tx Buffers
2412 * @tx_ring: Tx descriptor ring
2413 **/
2414static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
2415{
2416 struct e1000_adapter *adapter = tx_ring->adapter;
2417 struct e1000_buffer *buffer_info;
2418 unsigned long size;
2419 unsigned int i;
2420
2421 for (i = 0; i < tx_ring->count; i++) {
2422 buffer_info = &tx_ring->buffer_info[i];
2423 e1000_put_txbuf(tx_ring, buffer_info, false);
2424 }
2425
2426 netdev_reset_queue(adapter->netdev);
2427 size = sizeof(struct e1000_buffer) * tx_ring->count;
2428 memset(tx_ring->buffer_info, 0, size);
2429
2430 memset(tx_ring->desc, 0, tx_ring->size);
2431
2432 tx_ring->next_to_use = 0;
2433 tx_ring->next_to_clean = 0;
2434}
2435
2436/**
2437 * e1000e_free_tx_resources - Free Tx Resources per Queue
2438 * @tx_ring: Tx descriptor ring
2439 *
2440 * Free all transmit software resources
2441 **/
2442void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
2443{
2444 struct e1000_adapter *adapter = tx_ring->adapter;
2445 struct pci_dev *pdev = adapter->pdev;
2446
2447 e1000_clean_tx_ring(tx_ring);
2448
2449 vfree(tx_ring->buffer_info);
2450 tx_ring->buffer_info = NULL;
2451
2452 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2453 tx_ring->dma);
2454 tx_ring->desc = NULL;
2455}
2456
2457/**
2458 * e1000e_free_rx_resources - Free Rx Resources
2459 * @rx_ring: Rx descriptor ring
2460 *
2461 * Free all receive software resources
2462 **/
2463void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
2464{
2465 struct e1000_adapter *adapter = rx_ring->adapter;
2466 struct pci_dev *pdev = adapter->pdev;
2467 int i;
2468
2469 e1000_clean_rx_ring(rx_ring);
2470
2471 for (i = 0; i < rx_ring->count; i++)
2472 kfree(rx_ring->buffer_info[i].ps_pages);
2473
2474 vfree(rx_ring->buffer_info);
2475 rx_ring->buffer_info = NULL;
2476
2477 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2478 rx_ring->dma);
2479 rx_ring->desc = NULL;
2480}
2481
2482/**
2483 * e1000_update_itr - update the dynamic ITR value based on statistics
2484 * @itr_setting: current adapter->itr
2485 * @packets: the number of packets during this measurement interval
2486 * @bytes: the number of bytes during this measurement interval
2487 *
2488 * Stores a new ITR value based on packets and byte
2489 * counts during the last interrupt. The advantage of per interrupt
2490 * computation is faster updates and more accurate ITR for the current
2491 * traffic pattern. Constants in this function were computed
2492 * based on theoretical maximum wire speed and thresholds were set based
2493 * on testing data as well as attempting to minimize response time
2494 * while increasing bulk throughput. This functionality is controlled
2495 * by the InterruptThrottleRate module parameter.
2496 **/
2497static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
2498{
2499 unsigned int retval = itr_setting;
2500
2501 if (packets == 0)
2502 return itr_setting;
2503
2504 switch (itr_setting) {
2505 case lowest_latency:
2506 /* handle TSO and jumbo frames */
2507 if (bytes / packets > 8000)
2508 retval = bulk_latency;
2509 else if ((packets < 5) && (bytes > 512))
2510 retval = low_latency;
2511 break;
2512 case low_latency: /* 50 usec aka 20000 ints/s */
2513 if (bytes > 10000) {
2514 /* this if handles the TSO accounting */
2515 if (bytes / packets > 8000)
2516 retval = bulk_latency;
2517 else if ((packets < 10) || ((bytes / packets) > 1200))
2518 retval = bulk_latency;
2519 else if ((packets > 35))
2520 retval = lowest_latency;
2521 } else if (bytes / packets > 2000) {
2522 retval = bulk_latency;
2523 } else if (packets <= 2 && bytes < 512) {
2524 retval = lowest_latency;
2525 }
2526 break;
2527 case bulk_latency: /* 250 usec aka 4000 ints/s */
2528 if (bytes > 25000) {
2529 if (packets > 35)
2530 retval = low_latency;
2531 } else if (bytes < 6000) {
2532 retval = low_latency;
2533 }
2534 break;
2535 }
2536
2537 return retval;
2538}
2539
2540static void e1000_set_itr(struct e1000_adapter *adapter)
2541{
2542 u16 current_itr;
2543 u32 new_itr = adapter->itr;
2544
2545 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2546 if (adapter->link_speed != SPEED_1000) {
2547 new_itr = 4000;
2548 goto set_itr_now;
2549 }
2550
2551 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2552 new_itr = 0;
2553 goto set_itr_now;
2554 }
2555
2556 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2557 adapter->total_tx_packets,
2558 adapter->total_tx_bytes);
2559 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2560 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2561 adapter->tx_itr = low_latency;
2562
2563 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2564 adapter->total_rx_packets,
2565 adapter->total_rx_bytes);
2566 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2567 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2568 adapter->rx_itr = low_latency;
2569
2570 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2571
2572 /* counts and packets in update_itr are dependent on these numbers */
2573 switch (current_itr) {
2574 case lowest_latency:
2575 new_itr = 70000;
2576 break;
2577 case low_latency:
2578 new_itr = 20000; /* aka hwitr = ~200 */
2579 break;
2580 case bulk_latency:
2581 new_itr = 4000;
2582 break;
2583 default:
2584 break;
2585 }
2586
2587set_itr_now:
2588 if (new_itr != adapter->itr) {
2589 /* this attempts to bias the interrupt rate towards Bulk
2590 * by adding intermediate steps when interrupt rate is
2591 * increasing
2592 */
2593 new_itr = new_itr > adapter->itr ?
2594 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
2595 adapter->itr = new_itr;
2596 adapter->rx_ring->itr_val = new_itr;
2597 if (adapter->msix_entries)
2598 adapter->rx_ring->set_itr = 1;
2599 else
2600 e1000e_write_itr(adapter, new_itr);
2601 }
2602}
2603
2604/**
2605 * e1000e_write_itr - write the ITR value to the appropriate registers
2606 * @adapter: address of board private structure
2607 * @itr: new ITR value to program
2608 *
2609 * e1000e_write_itr determines if the adapter is in MSI-X mode
2610 * and, if so, writes the EITR registers with the ITR value.
2611 * Otherwise, it writes the ITR value into the ITR register.
2612 **/
2613void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2614{
2615 struct e1000_hw *hw = &adapter->hw;
2616 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2617
2618 if (adapter->msix_entries) {
2619 int vector;
2620
2621 for (vector = 0; vector < adapter->num_vectors; vector++)
2622 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2623 } else {
2624 ew32(ITR, new_itr);
2625 }
2626}
2627
2628/**
2629 * e1000_alloc_queues - Allocate memory for all rings
2630 * @adapter: board private structure to initialize
2631 **/
2632static int e1000_alloc_queues(struct e1000_adapter *adapter)
2633{
2634 int size = sizeof(struct e1000_ring);
2635
2636 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
2637 if (!adapter->tx_ring)
2638 goto err;
2639 adapter->tx_ring->count = adapter->tx_ring_count;
2640 adapter->tx_ring->adapter = adapter;
2641
2642 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
2643 if (!adapter->rx_ring)
2644 goto err;
2645 adapter->rx_ring->count = adapter->rx_ring_count;
2646 adapter->rx_ring->adapter = adapter;
2647
2648 return 0;
2649err:
2650 e_err("Unable to allocate memory for queues\n");
2651 kfree(adapter->rx_ring);
2652 kfree(adapter->tx_ring);
2653 return -ENOMEM;
2654}
2655
2656/**
2657 * e1000e_poll - NAPI Rx polling callback
2658 * @napi: struct associated with this polling callback
2659 * @budget: number of packets driver is allowed to process this poll
2660 **/
2661static int e1000e_poll(struct napi_struct *napi, int budget)
2662{
2663 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2664 napi);
2665 struct e1000_hw *hw = &adapter->hw;
2666 struct net_device *poll_dev = adapter->netdev;
2667 int tx_cleaned = 1, work_done = 0;
2668
2669 adapter = netdev_priv(poll_dev);
2670
2671 if (!adapter->msix_entries ||
2672 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2673 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
2674
2675 adapter->clean_rx(adapter->rx_ring, &work_done, budget);
2676
2677 if (!tx_cleaned || work_done == budget)
2678 return budget;
2679
2680 /* Exit the polling mode, but don't re-enable interrupts if stack might
2681 * poll us due to busy-polling
2682 */
2683 if (likely(napi_complete_done(napi, work_done))) {
2684 if (adapter->itr_setting & 3)
2685 e1000_set_itr(adapter);
2686 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2687 if (adapter->msix_entries)
2688 ew32(IMS, adapter->rx_ring->ims_val);
2689 else
2690 e1000_irq_enable(adapter);
2691 }
2692 }
2693
2694 return work_done;
2695}
2696
2697static int e1000_vlan_rx_add_vid(struct net_device *netdev,
2698 __always_unused __be16 proto, u16 vid)
2699{
2700 struct e1000_adapter *adapter = netdev_priv(netdev);
2701 struct e1000_hw *hw = &adapter->hw;
2702 u32 vfta, index;
2703
2704 /* don't update vlan cookie if already programmed */
2705 if ((adapter->hw.mng_cookie.status &
2706 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2707 (vid == adapter->mng_vlan_id))
2708 return 0;
2709
2710 /* add VID to filter table */
2711 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2712 index = (vid >> 5) & 0x7F;
2713 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2714 vfta |= BIT((vid & 0x1F));
2715 hw->mac.ops.write_vfta(hw, index, vfta);
2716 }
2717
2718 set_bit(vid, adapter->active_vlans);
2719
2720 return 0;
2721}
2722
2723static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
2724 __always_unused __be16 proto, u16 vid)
2725{
2726 struct e1000_adapter *adapter = netdev_priv(netdev);
2727 struct e1000_hw *hw = &adapter->hw;
2728 u32 vfta, index;
2729
2730 if ((adapter->hw.mng_cookie.status &
2731 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2732 (vid == adapter->mng_vlan_id)) {
2733 /* release control to f/w */
2734 e1000e_release_hw_control(adapter);
2735 return 0;
2736 }
2737
2738 /* remove VID from filter table */
2739 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2740 index = (vid >> 5) & 0x7F;
2741 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2742 vfta &= ~BIT((vid & 0x1F));
2743 hw->mac.ops.write_vfta(hw, index, vfta);
2744 }
2745
2746 clear_bit(vid, adapter->active_vlans);
2747
2748 return 0;
2749}
2750
2751/**
2752 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2753 * @adapter: board private structure to initialize
2754 **/
2755static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
2756{
2757 struct net_device *netdev = adapter->netdev;
2758 struct e1000_hw *hw = &adapter->hw;
2759 u32 rctl;
2760
2761 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2762 /* disable VLAN receive filtering */
2763 rctl = er32(RCTL);
2764 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2765 ew32(RCTL, rctl);
2766
2767 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2768 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2769 adapter->mng_vlan_id);
2770 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
2771 }
2772 }
2773}
2774
2775/**
2776 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2777 * @adapter: board private structure to initialize
2778 **/
2779static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2780{
2781 struct e1000_hw *hw = &adapter->hw;
2782 u32 rctl;
2783
2784 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2785 /* enable VLAN receive filtering */
2786 rctl = er32(RCTL);
2787 rctl |= E1000_RCTL_VFE;
2788 rctl &= ~E1000_RCTL_CFIEN;
2789 ew32(RCTL, rctl);
2790 }
2791}
2792
2793/**
2794 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping
2795 * @adapter: board private structure to initialize
2796 **/
2797static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
2798{
2799 struct e1000_hw *hw = &adapter->hw;
2800 u32 ctrl;
2801
2802 /* disable VLAN tag insert/strip */
2803 ctrl = er32(CTRL);
2804 ctrl &= ~E1000_CTRL_VME;
2805 ew32(CTRL, ctrl);
2806}
2807
2808/**
2809 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2810 * @adapter: board private structure to initialize
2811 **/
2812static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2813{
2814 struct e1000_hw *hw = &adapter->hw;
2815 u32 ctrl;
2816
2817 /* enable VLAN tag insert/strip */
2818 ctrl = er32(CTRL);
2819 ctrl |= E1000_CTRL_VME;
2820 ew32(CTRL, ctrl);
2821}
2822
2823static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2824{
2825 struct net_device *netdev = adapter->netdev;
2826 u16 vid = adapter->hw.mng_cookie.vlan_id;
2827 u16 old_vid = adapter->mng_vlan_id;
2828
2829 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2830 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
2831 adapter->mng_vlan_id = vid;
2832 }
2833
2834 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2835 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
2836}
2837
2838static void e1000_restore_vlan(struct e1000_adapter *adapter)
2839{
2840 u16 vid;
2841
2842 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
2843
2844 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2845 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
2846}
2847
2848static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
2849{
2850 struct e1000_hw *hw = &adapter->hw;
2851 u32 manc, manc2h, mdef, i, j;
2852
2853 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2854 return;
2855
2856 manc = er32(MANC);
2857
2858 /* enable receiving management packets to the host. this will probably
2859 * generate destination unreachable messages from the host OS, but
2860 * the packets will be handled on SMBUS
2861 */
2862 manc |= E1000_MANC_EN_MNG2HOST;
2863 manc2h = er32(MANC2H);
2864
2865 switch (hw->mac.type) {
2866 default:
2867 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2868 break;
2869 case e1000_82574:
2870 case e1000_82583:
2871 /* Check if IPMI pass-through decision filter already exists;
2872 * if so, enable it.
2873 */
2874 for (i = 0, j = 0; i < 8; i++) {
2875 mdef = er32(MDEF(i));
2876
2877 /* Ignore filters with anything other than IPMI ports */
2878 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2879 continue;
2880
2881 /* Enable this decision filter in MANC2H */
2882 if (mdef)
2883 manc2h |= BIT(i);
2884
2885 j |= mdef;
2886 }
2887
2888 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2889 break;
2890
2891 /* Create new decision filter in an empty filter */
2892 for (i = 0, j = 0; i < 8; i++)
2893 if (er32(MDEF(i)) == 0) {
2894 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2895 E1000_MDEF_PORT_664));
2896 manc2h |= BIT(1);
2897 j++;
2898 break;
2899 }
2900
2901 if (!j)
2902 e_warn("Unable to create IPMI pass-through filter\n");
2903 break;
2904 }
2905
2906 ew32(MANC2H, manc2h);
2907 ew32(MANC, manc);
2908}
2909
2910/**
2911 * e1000_configure_tx - Configure Transmit Unit after Reset
2912 * @adapter: board private structure
2913 *
2914 * Configure the Tx unit of the MAC after a reset.
2915 **/
2916static void e1000_configure_tx(struct e1000_adapter *adapter)
2917{
2918 struct e1000_hw *hw = &adapter->hw;
2919 struct e1000_ring *tx_ring = adapter->tx_ring;
2920 u64 tdba;
2921 u32 tdlen, tctl, tarc;
2922
2923 /* Setup the HW Tx Head and Tail descriptor pointers */
2924 tdba = tx_ring->dma;
2925 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
2926 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2927 ew32(TDBAH(0), (tdba >> 32));
2928 ew32(TDLEN(0), tdlen);
2929 ew32(TDH(0), 0);
2930 ew32(TDT(0), 0);
2931 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2932 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
2933
2934 writel(0, tx_ring->head);
2935 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2936 e1000e_update_tdt_wa(tx_ring, 0);
2937 else
2938 writel(0, tx_ring->tail);
2939
2940 /* Set the Tx Interrupt Delay register */
2941 ew32(TIDV, adapter->tx_int_delay);
2942 /* Tx irq moderation */
2943 ew32(TADV, adapter->tx_abs_int_delay);
2944
2945 if (adapter->flags2 & FLAG2_DMA_BURST) {
2946 u32 txdctl = er32(TXDCTL(0));
2947
2948 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2949 E1000_TXDCTL_WTHRESH);
2950 /* set up some performance related parameters to encourage the
2951 * hardware to use the bus more efficiently in bursts, depends
2952 * on the tx_int_delay to be enabled,
2953 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2954 * hthresh = 1 ==> prefetch when one or more available
2955 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2956 * BEWARE: this seems to work but should be considered first if
2957 * there are Tx hangs or other Tx related bugs
2958 */
2959 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2960 ew32(TXDCTL(0), txdctl);
2961 }
2962 /* erratum work around: set txdctl the same for both queues */
2963 ew32(TXDCTL(1), er32(TXDCTL(0)));
2964
2965 /* Program the Transmit Control Register */
2966 tctl = er32(TCTL);
2967 tctl &= ~E1000_TCTL_CT;
2968 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2969 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2970
2971 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
2972 tarc = er32(TARC(0));
2973 /* set the speed mode bit, we'll clear it if we're not at
2974 * gigabit link later
2975 */
2976#define SPEED_MODE_BIT BIT(21)
2977 tarc |= SPEED_MODE_BIT;
2978 ew32(TARC(0), tarc);
2979 }
2980
2981 /* errata: program both queues to unweighted RR */
2982 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
2983 tarc = er32(TARC(0));
2984 tarc |= 1;
2985 ew32(TARC(0), tarc);
2986 tarc = er32(TARC(1));
2987 tarc |= 1;
2988 ew32(TARC(1), tarc);
2989 }
2990
2991 /* Setup Transmit Descriptor Settings for eop descriptor */
2992 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2993
2994 /* only set IDE if we are delaying interrupts using the timers */
2995 if (adapter->tx_int_delay)
2996 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2997
2998 /* enable Report Status bit */
2999 adapter->txd_cmd |= E1000_TXD_CMD_RS;
3000
3001 ew32(TCTL, tctl);
3002
3003 hw->mac.ops.config_collision_dist(hw);
3004
3005 /* SPT and KBL Si errata workaround to avoid data corruption */
3006 if (hw->mac.type == e1000_pch_spt) {
3007 u32 reg_val;
3008
3009 reg_val = er32(IOSFPC);
3010 reg_val |= E1000_RCTL_RDMTS_HEX;
3011 ew32(IOSFPC, reg_val);
3012
3013 reg_val = er32(TARC(0));
3014 /* SPT and KBL Si errata workaround to avoid Tx hang.
3015 * Dropping the number of outstanding requests from
3016 * 3 to 2 in order to avoid a buffer overrun.
3017 */
3018 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3019 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ;
3020 ew32(TARC(0), reg_val);
3021 }
3022}
3023
3024#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3025 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3026
3027/**
3028 * e1000_setup_rctl - configure the receive control registers
3029 * @adapter: Board private structure
3030 **/
3031static void e1000_setup_rctl(struct e1000_adapter *adapter)
3032{
3033 struct e1000_hw *hw = &adapter->hw;
3034 u32 rctl, rfctl;
3035 u32 pages = 0;
3036
3037 /* Workaround Si errata on PCHx - configure jumbo frame flow.
3038 * If jumbo frames not set, program related MAC/PHY registers
3039 * to h/w defaults
3040 */
3041 if (hw->mac.type >= e1000_pch2lan) {
3042 s32 ret_val;
3043
3044 if (adapter->netdev->mtu > ETH_DATA_LEN)
3045 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
3046 else
3047 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
3048
3049 if (ret_val)
3050 e_dbg("failed to enable|disable jumbo frame workaround mode\n");
3051 }
3052
3053 /* Program MC offset vector base */
3054 rctl = er32(RCTL);
3055 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3056 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3057 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3058 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3059
3060 /* Do not Store bad packets */
3061 rctl &= ~E1000_RCTL_SBP;
3062
3063 /* Enable Long Packet receive */
3064 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3065 rctl &= ~E1000_RCTL_LPE;
3066 else
3067 rctl |= E1000_RCTL_LPE;
3068
3069 /* Some systems expect that the CRC is included in SMBUS traffic. The
3070 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3071 * host memory when this is enabled
3072 */
3073 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3074 rctl |= E1000_RCTL_SECRC;
3075
3076 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3077 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3078 u16 phy_data;
3079
3080 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3081 phy_data &= 0xfff8;
3082 phy_data |= BIT(2);
3083 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3084
3085 e1e_rphy(hw, 22, &phy_data);
3086 phy_data &= 0x0fff;
3087 phy_data |= BIT(14);
3088 e1e_wphy(hw, 0x10, 0x2823);
3089 e1e_wphy(hw, 0x11, 0x0003);
3090 e1e_wphy(hw, 22, phy_data);
3091 }
3092
3093 /* Setup buffer sizes */
3094 rctl &= ~E1000_RCTL_SZ_4096;
3095 rctl |= E1000_RCTL_BSEX;
3096 switch (adapter->rx_buffer_len) {
3097 case 2048:
3098 default:
3099 rctl |= E1000_RCTL_SZ_2048;
3100 rctl &= ~E1000_RCTL_BSEX;
3101 break;
3102 case 4096:
3103 rctl |= E1000_RCTL_SZ_4096;
3104 break;
3105 case 8192:
3106 rctl |= E1000_RCTL_SZ_8192;
3107 break;
3108 case 16384:
3109 rctl |= E1000_RCTL_SZ_16384;
3110 break;
3111 }
3112
3113 /* Enable Extended Status in all Receive Descriptors */
3114 rfctl = er32(RFCTL);
3115 rfctl |= E1000_RFCTL_EXTEN;
3116 ew32(RFCTL, rfctl);
3117
3118 /* 82571 and greater support packet-split where the protocol
3119 * header is placed in skb->data and the packet data is
3120 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3121 * In the case of a non-split, skb->data is linearly filled,
3122 * followed by the page buffers. Therefore, skb->data is
3123 * sized to hold the largest protocol header.
3124 *
3125 * allocations using alloc_page take too long for regular MTU
3126 * so only enable packet split for jumbo frames
3127 *
3128 * Using pages when the page size is greater than 16k wastes
3129 * a lot of memory, since we allocate 3 pages at all times
3130 * per packet.
3131 */
3132 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
3133 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
3134 adapter->rx_ps_pages = pages;
3135 else
3136 adapter->rx_ps_pages = 0;
3137
3138 if (adapter->rx_ps_pages) {
3139 u32 psrctl = 0;
3140
3141 /* Enable Packet split descriptors */
3142 rctl |= E1000_RCTL_DTYP_PS;
3143
3144 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
3145
3146 switch (adapter->rx_ps_pages) {
3147 case 3:
3148 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3149 fallthrough;
3150 case 2:
3151 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3152 fallthrough;
3153 case 1:
3154 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
3155 break;
3156 }
3157
3158 ew32(PSRCTL, psrctl);
3159 }
3160
3161 /* This is useful for sniffing bad packets. */
3162 if (adapter->netdev->features & NETIF_F_RXALL) {
3163 /* UPE and MPE will be handled by normal PROMISC logic
3164 * in e1000e_set_rx_mode
3165 */
3166 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3167 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3168 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3169
3170 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3171 E1000_RCTL_DPF | /* Allow filtered pause */
3172 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3173 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3174 * and that breaks VLANs.
3175 */
3176 }
3177
3178 ew32(RCTL, rctl);
3179 /* just started the receive unit, no need to restart */
3180 adapter->flags &= ~FLAG_RESTART_NOW;
3181}
3182
3183/**
3184 * e1000_configure_rx - Configure Receive Unit after Reset
3185 * @adapter: board private structure
3186 *
3187 * Configure the Rx unit of the MAC after a reset.
3188 **/
3189static void e1000_configure_rx(struct e1000_adapter *adapter)
3190{
3191 struct e1000_hw *hw = &adapter->hw;
3192 struct e1000_ring *rx_ring = adapter->rx_ring;
3193 u64 rdba;
3194 u32 rdlen, rctl, rxcsum, ctrl_ext;
3195
3196 if (adapter->rx_ps_pages) {
3197 /* this is a 32 byte descriptor */
3198 rdlen = rx_ring->count *
3199 sizeof(union e1000_rx_desc_packet_split);
3200 adapter->clean_rx = e1000_clean_rx_irq_ps;
3201 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
3202 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
3203 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3204 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3205 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
3206 } else {
3207 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3208 adapter->clean_rx = e1000_clean_rx_irq;
3209 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3210 }
3211
3212 /* disable receives while setting up the descriptors */
3213 rctl = er32(RCTL);
3214 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3215 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3216 e1e_flush();
3217 usleep_range(10000, 11000);
3218
3219 if (adapter->flags2 & FLAG2_DMA_BURST) {
3220 /* set the writeback threshold (only takes effect if the RDTR
3221 * is set). set GRAN=1 and write back up to 0x4 worth, and
3222 * enable prefetching of 0x20 Rx descriptors
3223 * granularity = 01
3224 * wthresh = 04,
3225 * hthresh = 04,
3226 * pthresh = 0x20
3227 */
3228 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3229 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3230 }
3231
3232 /* set the Receive Delay Timer Register */
3233 ew32(RDTR, adapter->rx_int_delay);
3234
3235 /* irq moderation */
3236 ew32(RADV, adapter->rx_abs_int_delay);
3237 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
3238 e1000e_write_itr(adapter, adapter->itr);
3239
3240 ctrl_ext = er32(CTRL_EXT);
3241 /* Auto-Mask interrupts upon ICR access */
3242 ctrl_ext |= E1000_CTRL_EXT_IAME;
3243 ew32(IAM, 0xffffffff);
3244 ew32(CTRL_EXT, ctrl_ext);
3245 e1e_flush();
3246
3247 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3248 * the Base and Length of the Rx Descriptor Ring
3249 */
3250 rdba = rx_ring->dma;
3251 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3252 ew32(RDBAH(0), (rdba >> 32));
3253 ew32(RDLEN(0), rdlen);
3254 ew32(RDH(0), 0);
3255 ew32(RDT(0), 0);
3256 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3257 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
3258
3259 writel(0, rx_ring->head);
3260 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
3261 e1000e_update_rdt_wa(rx_ring, 0);
3262 else
3263 writel(0, rx_ring->tail);
3264
3265 /* Enable Receive Checksum Offload for TCP and UDP */
3266 rxcsum = er32(RXCSUM);
3267 if (adapter->netdev->features & NETIF_F_RXCSUM)
3268 rxcsum |= E1000_RXCSUM_TUOFL;
3269 else
3270 rxcsum &= ~E1000_RXCSUM_TUOFL;
3271 ew32(RXCSUM, rxcsum);
3272
3273 /* With jumbo frames, excessive C-state transition latencies result
3274 * in dropped transactions.
3275 */
3276 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3277 u32 lat =
3278 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3279 adapter->max_frame_size) * 8 / 1000;
3280
3281 if (adapter->flags & FLAG_IS_ICH) {
3282 u32 rxdctl = er32(RXDCTL(0));
3283
3284 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8));
3285 }
3286
3287 dev_info(&adapter->pdev->dev,
3288 "Some CPU C-states have been disabled in order to enable jumbo frames\n");
3289 cpu_latency_qos_update_request(&adapter->pm_qos_req, lat);
3290 } else {
3291 cpu_latency_qos_update_request(&adapter->pm_qos_req,
3292 PM_QOS_DEFAULT_VALUE);
3293 }
3294
3295 /* Enable Receives */
3296 ew32(RCTL, rctl);
3297}
3298
3299/**
3300 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3301 * @netdev: network interface device structure
3302 *
3303 * Writes multicast address list to the MTA hash table.
3304 * Returns: -ENOMEM on failure
3305 * 0 on no addresses written
3306 * X on writing X addresses to MTA
3307 */
3308static int e1000e_write_mc_addr_list(struct net_device *netdev)
3309{
3310 struct e1000_adapter *adapter = netdev_priv(netdev);
3311 struct e1000_hw *hw = &adapter->hw;
3312 struct netdev_hw_addr *ha;
3313 u8 *mta_list;
3314 int i;
3315
3316 if (netdev_mc_empty(netdev)) {
3317 /* nothing to program, so clear mc list */
3318 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3319 return 0;
3320 }
3321
3322 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC);
3323 if (!mta_list)
3324 return -ENOMEM;
3325
3326 /* update_mc_addr_list expects a packed array of only addresses. */
3327 i = 0;
3328 netdev_for_each_mc_addr(ha, netdev)
3329 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3330
3331 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3332 kfree(mta_list);
3333
3334 return netdev_mc_count(netdev);
3335}
3336
3337/**
3338 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3339 * @netdev: network interface device structure
3340 *
3341 * Writes unicast address list to the RAR table.
3342 * Returns: -ENOMEM on failure/insufficient address space
3343 * 0 on no addresses written
3344 * X on writing X addresses to the RAR table
3345 **/
3346static int e1000e_write_uc_addr_list(struct net_device *netdev)
3347{
3348 struct e1000_adapter *adapter = netdev_priv(netdev);
3349 struct e1000_hw *hw = &adapter->hw;
3350 unsigned int rar_entries;
3351 int count = 0;
3352
3353 rar_entries = hw->mac.ops.rar_get_count(hw);
3354
3355 /* save a rar entry for our hardware address */
3356 rar_entries--;
3357
3358 /* save a rar entry for the LAA workaround */
3359 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3360 rar_entries--;
3361
3362 /* return ENOMEM indicating insufficient memory for addresses */
3363 if (netdev_uc_count(netdev) > rar_entries)
3364 return -ENOMEM;
3365
3366 if (!netdev_uc_empty(netdev) && rar_entries) {
3367 struct netdev_hw_addr *ha;
3368
3369 /* write the addresses in reverse order to avoid write
3370 * combining
3371 */
3372 netdev_for_each_uc_addr(ha, netdev) {
3373 int ret_val;
3374
3375 if (!rar_entries)
3376 break;
3377 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
3378 if (ret_val < 0)
3379 return -ENOMEM;
3380 count++;
3381 }
3382 }
3383
3384 /* zero out the remaining RAR entries not used above */
3385 for (; rar_entries > 0; rar_entries--) {
3386 ew32(RAH(rar_entries), 0);
3387 ew32(RAL(rar_entries), 0);
3388 }
3389 e1e_flush();
3390
3391 return count;
3392}
3393
3394/**
3395 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3396 * @netdev: network interface device structure
3397 *
3398 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3399 * address list or the network interface flags are updated. This routine is
3400 * responsible for configuring the hardware for proper unicast, multicast,
3401 * promiscuous mode, and all-multi behavior.
3402 **/
3403static void e1000e_set_rx_mode(struct net_device *netdev)
3404{
3405 struct e1000_adapter *adapter = netdev_priv(netdev);
3406 struct e1000_hw *hw = &adapter->hw;
3407 u32 rctl;
3408
3409 if (pm_runtime_suspended(netdev->dev.parent))
3410 return;
3411
3412 /* Check for Promiscuous and All Multicast modes */
3413 rctl = er32(RCTL);
3414
3415 /* clear the affected bits */
3416 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3417
3418 if (netdev->flags & IFF_PROMISC) {
3419 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3420 /* Do not hardware filter VLANs in promisc mode */
3421 e1000e_vlan_filter_disable(adapter);
3422 } else {
3423 int count;
3424
3425 if (netdev->flags & IFF_ALLMULTI) {
3426 rctl |= E1000_RCTL_MPE;
3427 } else {
3428 /* Write addresses to the MTA, if the attempt fails
3429 * then we should just turn on promiscuous mode so
3430 * that we can at least receive multicast traffic
3431 */
3432 count = e1000e_write_mc_addr_list(netdev);
3433 if (count < 0)
3434 rctl |= E1000_RCTL_MPE;
3435 }
3436 e1000e_vlan_filter_enable(adapter);
3437 /* Write addresses to available RAR registers, if there is not
3438 * sufficient space to store all the addresses then enable
3439 * unicast promiscuous mode
3440 */
3441 count = e1000e_write_uc_addr_list(netdev);
3442 if (count < 0)
3443 rctl |= E1000_RCTL_UPE;
3444 }
3445
3446 ew32(RCTL, rctl);
3447
3448 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3449 e1000e_vlan_strip_enable(adapter);
3450 else
3451 e1000e_vlan_strip_disable(adapter);
3452}
3453
3454static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3455{
3456 struct e1000_hw *hw = &adapter->hw;
3457 u32 mrqc, rxcsum;
3458 u32 rss_key[10];
3459 int i;
3460
3461 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3462 for (i = 0; i < 10; i++)
3463 ew32(RSSRK(i), rss_key[i]);
3464
3465 /* Direct all traffic to queue 0 */
3466 for (i = 0; i < 32; i++)
3467 ew32(RETA(i), 0);
3468
3469 /* Disable raw packet checksumming so that RSS hash is placed in
3470 * descriptor on writeback.
3471 */
3472 rxcsum = er32(RXCSUM);
3473 rxcsum |= E1000_RXCSUM_PCSD;
3474
3475 ew32(RXCSUM, rxcsum);
3476
3477 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3478 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3479 E1000_MRQC_RSS_FIELD_IPV6 |
3480 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3481 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3482
3483 ew32(MRQC, mrqc);
3484}
3485
3486/**
3487 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3488 * @adapter: board private structure
3489 * @timinca: pointer to returned time increment attributes
3490 *
3491 * Get attributes for incrementing the System Time Register SYSTIML/H at
3492 * the default base frequency, and set the cyclecounter shift value.
3493 **/
3494s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
3495{
3496 struct e1000_hw *hw = &adapter->hw;
3497 u32 incvalue, incperiod, shift;
3498
3499 /* Make sure clock is enabled on I217/I218/I219 before checking
3500 * the frequency
3501 */
3502 if ((hw->mac.type >= e1000_pch_lpt) &&
3503 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3504 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3505 u32 fextnvm7 = er32(FEXTNVM7);
3506
3507 if (!(fextnvm7 & BIT(0))) {
3508 ew32(FEXTNVM7, fextnvm7 | BIT(0));
3509 e1e_flush();
3510 }
3511 }
3512
3513 switch (hw->mac.type) {
3514 case e1000_pch2lan:
3515 /* Stable 96MHz frequency */
3516 incperiod = INCPERIOD_96MHZ;
3517 incvalue = INCVALUE_96MHZ;
3518 shift = INCVALUE_SHIFT_96MHZ;
3519 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3520 break;
3521 case e1000_pch_lpt:
3522 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3523 /* Stable 96MHz frequency */
3524 incperiod = INCPERIOD_96MHZ;
3525 incvalue = INCVALUE_96MHZ;
3526 shift = INCVALUE_SHIFT_96MHZ;
3527 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3528 } else {
3529 /* Stable 25MHz frequency */
3530 incperiod = INCPERIOD_25MHZ;
3531 incvalue = INCVALUE_25MHZ;
3532 shift = INCVALUE_SHIFT_25MHZ;
3533 adapter->cc.shift = shift;
3534 }
3535 break;
3536 case e1000_pch_spt:
3537 /* Stable 24MHz frequency */
3538 incperiod = INCPERIOD_24MHZ;
3539 incvalue = INCVALUE_24MHZ;
3540 shift = INCVALUE_SHIFT_24MHZ;
3541 adapter->cc.shift = shift;
3542 break;
3543 case e1000_pch_cnp:
3544 case e1000_pch_tgp:
3545 case e1000_pch_adp:
3546 case e1000_pch_mtp:
3547 case e1000_pch_lnp:
3548 case e1000_pch_ptp:
3549 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3550 /* Stable 24MHz frequency */
3551 incperiod = INCPERIOD_24MHZ;
3552 incvalue = INCVALUE_24MHZ;
3553 shift = INCVALUE_SHIFT_24MHZ;
3554 adapter->cc.shift = shift;
3555 } else {
3556 /* Stable 38400KHz frequency */
3557 incperiod = INCPERIOD_38400KHZ;
3558 incvalue = INCVALUE_38400KHZ;
3559 shift = INCVALUE_SHIFT_38400KHZ;
3560 adapter->cc.shift = shift;
3561 }
3562 break;
3563 case e1000_82574:
3564 case e1000_82583:
3565 /* Stable 25MHz frequency */
3566 incperiod = INCPERIOD_25MHZ;
3567 incvalue = INCVALUE_25MHZ;
3568 shift = INCVALUE_SHIFT_25MHZ;
3569 adapter->cc.shift = shift;
3570 break;
3571 default:
3572 return -EINVAL;
3573 }
3574
3575 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3576 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3577
3578 return 0;
3579}
3580
3581/**
3582 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3583 * @adapter: board private structure
3584 * @config: timestamp configuration
3585 *
3586 * Outgoing time stamping can be enabled and disabled. Play nice and
3587 * disable it when requested, although it shouldn't cause any overhead
3588 * when no packet needs it. At most one packet in the queue may be
3589 * marked for time stamping, otherwise it would be impossible to tell
3590 * for sure to which packet the hardware time stamp belongs.
3591 *
3592 * Incoming time stamping has to be configured via the hardware filters.
3593 * Not all combinations are supported, in particular event type has to be
3594 * specified. Matching the kind of event packet is not supported, with the
3595 * exception of "all V2 events regardless of level 2 or 4".
3596 **/
3597static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3598 struct hwtstamp_config *config)
3599{
3600 struct e1000_hw *hw = &adapter->hw;
3601 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3602 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
3603 u32 rxmtrl = 0;
3604 u16 rxudp = 0;
3605 bool is_l4 = false;
3606 bool is_l2 = false;
3607 u32 regval;
3608
3609 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3610 return -EINVAL;
3611
3612 switch (config->tx_type) {
3613 case HWTSTAMP_TX_OFF:
3614 tsync_tx_ctl = 0;
3615 break;
3616 case HWTSTAMP_TX_ON:
3617 break;
3618 default:
3619 return -ERANGE;
3620 }
3621
3622 switch (config->rx_filter) {
3623 case HWTSTAMP_FILTER_NONE:
3624 tsync_rx_ctl = 0;
3625 break;
3626 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3627 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3628 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3629 is_l4 = true;
3630 break;
3631 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3632 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3633 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3634 is_l4 = true;
3635 break;
3636 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3637 /* Also time stamps V2 L2 Path Delay Request/Response */
3638 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3639 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3640 is_l2 = true;
3641 break;
3642 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3643 /* Also time stamps V2 L2 Path Delay Request/Response. */
3644 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3645 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3646 is_l2 = true;
3647 break;
3648 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3649 /* Hardware cannot filter just V2 L4 Sync messages */
3650 fallthrough;
3651 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3652 /* Also time stamps V2 Path Delay Request/Response. */
3653 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3654 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3655 is_l2 = true;
3656 is_l4 = true;
3657 break;
3658 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3659 /* Hardware cannot filter just V2 L4 Delay Request messages */
3660 fallthrough;
3661 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3662 /* Also time stamps V2 Path Delay Request/Response. */
3663 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3664 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3665 is_l2 = true;
3666 is_l4 = true;
3667 break;
3668 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3669 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3670 /* Hardware cannot filter just V2 L4 or L2 Event messages */
3671 fallthrough;
3672 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3673 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3674 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3675 is_l2 = true;
3676 is_l4 = true;
3677 break;
3678 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3679 /* For V1, the hardware can only filter Sync messages or
3680 * Delay Request messages but not both so fall-through to
3681 * time stamp all packets.
3682 */
3683 fallthrough;
3684 case HWTSTAMP_FILTER_NTP_ALL:
3685 case HWTSTAMP_FILTER_ALL:
3686 is_l2 = true;
3687 is_l4 = true;
3688 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3689 config->rx_filter = HWTSTAMP_FILTER_ALL;
3690 break;
3691 default:
3692 return -ERANGE;
3693 }
3694
3695 adapter->hwtstamp_config = *config;
3696
3697 /* enable/disable Tx h/w time stamping */
3698 regval = er32(TSYNCTXCTL);
3699 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3700 regval |= tsync_tx_ctl;
3701 ew32(TSYNCTXCTL, regval);
3702 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3703 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3704 e_err("Timesync Tx Control register not set as expected\n");
3705 return -EAGAIN;
3706 }
3707
3708 /* enable/disable Rx h/w time stamping */
3709 regval = er32(TSYNCRXCTL);
3710 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3711 regval |= tsync_rx_ctl;
3712 ew32(TSYNCRXCTL, regval);
3713 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3714 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3715 (regval & (E1000_TSYNCRXCTL_ENABLED |
3716 E1000_TSYNCRXCTL_TYPE_MASK))) {
3717 e_err("Timesync Rx Control register not set as expected\n");
3718 return -EAGAIN;
3719 }
3720
3721 /* L2: define ethertype filter for time stamped packets */
3722 if (is_l2)
3723 rxmtrl |= ETH_P_1588;
3724
3725 /* define which PTP packets get time stamped */
3726 ew32(RXMTRL, rxmtrl);
3727
3728 /* Filter by destination port */
3729 if (is_l4) {
3730 rxudp = PTP_EV_PORT;
3731 cpu_to_be16s(&rxudp);
3732 }
3733 ew32(RXUDP, rxudp);
3734
3735 e1e_flush();
3736
3737 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3738 er32(RXSTMPH);
3739 er32(TXSTMPH);
3740
3741 return 0;
3742}
3743
3744/**
3745 * e1000_configure - configure the hardware for Rx and Tx
3746 * @adapter: private board structure
3747 **/
3748static void e1000_configure(struct e1000_adapter *adapter)
3749{
3750 struct e1000_ring *rx_ring = adapter->rx_ring;
3751
3752 e1000e_set_rx_mode(adapter->netdev);
3753
3754 e1000_restore_vlan(adapter);
3755 e1000_init_manageability_pt(adapter);
3756
3757 e1000_configure_tx(adapter);
3758
3759 if (adapter->netdev->features & NETIF_F_RXHASH)
3760 e1000e_setup_rss_hash(adapter);
3761 e1000_setup_rctl(adapter);
3762 e1000_configure_rx(adapter);
3763 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
3764}
3765
3766/**
3767 * e1000e_power_up_phy - restore link in case the phy was powered down
3768 * @adapter: address of board private structure
3769 *
3770 * The phy may be powered down to save power and turn off link when the
3771 * driver is unloaded and wake on lan is not enabled (among others)
3772 * *** this routine MUST be followed by a call to e1000e_reset ***
3773 **/
3774void e1000e_power_up_phy(struct e1000_adapter *adapter)
3775{
3776 if (adapter->hw.phy.ops.power_up)
3777 adapter->hw.phy.ops.power_up(&adapter->hw);
3778
3779 adapter->hw.mac.ops.setup_link(&adapter->hw);
3780}
3781
3782/**
3783 * e1000_power_down_phy - Power down the PHY
3784 * @adapter: board private structure
3785 *
3786 * Power down the PHY so no link is implied when interface is down.
3787 * The PHY cannot be powered down if management or WoL is active.
3788 */
3789static void e1000_power_down_phy(struct e1000_adapter *adapter)
3790{
3791 if (adapter->hw.phy.ops.power_down)
3792 adapter->hw.phy.ops.power_down(&adapter->hw);
3793}
3794
3795/**
3796 * e1000_flush_tx_ring - remove all descriptors from the tx_ring
3797 * @adapter: board private structure
3798 *
3799 * We want to clear all pending descriptors from the TX ring.
3800 * zeroing happens when the HW reads the regs. We assign the ring itself as
3801 * the data of the next descriptor. We don't care about the data we are about
3802 * to reset the HW.
3803 */
3804static void e1000_flush_tx_ring(struct e1000_adapter *adapter)
3805{
3806 struct e1000_hw *hw = &adapter->hw;
3807 struct e1000_ring *tx_ring = adapter->tx_ring;
3808 struct e1000_tx_desc *tx_desc = NULL;
3809 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
3810 u16 size = 512;
3811
3812 tctl = er32(TCTL);
3813 ew32(TCTL, tctl | E1000_TCTL_EN);
3814 tdt = er32(TDT(0));
3815 BUG_ON(tdt != tx_ring->next_to_use);
3816 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use);
3817 tx_desc->buffer_addr = cpu_to_le64(tx_ring->dma);
3818
3819 tx_desc->lower.data = cpu_to_le32(txd_lower | size);
3820 tx_desc->upper.data = 0;
3821 /* flush descriptors to memory before notifying the HW */
3822 wmb();
3823 tx_ring->next_to_use++;
3824 if (tx_ring->next_to_use == tx_ring->count)
3825 tx_ring->next_to_use = 0;
3826 ew32(TDT(0), tx_ring->next_to_use);
3827 usleep_range(200, 250);
3828}
3829
3830/**
3831 * e1000_flush_rx_ring - remove all descriptors from the rx_ring
3832 * @adapter: board private structure
3833 *
3834 * Mark all descriptors in the RX ring as consumed and disable the rx ring
3835 */
3836static void e1000_flush_rx_ring(struct e1000_adapter *adapter)
3837{
3838 u32 rctl, rxdctl;
3839 struct e1000_hw *hw = &adapter->hw;
3840
3841 rctl = er32(RCTL);
3842 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3843 e1e_flush();
3844 usleep_range(100, 150);
3845
3846 rxdctl = er32(RXDCTL(0));
3847 /* zero the lower 14 bits (prefetch and host thresholds) */
3848 rxdctl &= 0xffffc000;
3849
3850 /* update thresholds: prefetch threshold to 31, host threshold to 1
3851 * and make sure the granularity is "descriptors" and not "cache lines"
3852 */
3853 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC);
3854
3855 ew32(RXDCTL(0), rxdctl);
3856 /* momentarily enable the RX ring for the changes to take effect */
3857 ew32(RCTL, rctl | E1000_RCTL_EN);
3858 e1e_flush();
3859 usleep_range(100, 150);
3860 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3861}
3862
3863/**
3864 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings
3865 * @adapter: board private structure
3866 *
3867 * In i219, the descriptor rings must be emptied before resetting the HW
3868 * or before changing the device state to D3 during runtime (runtime PM).
3869 *
3870 * Failure to do this will cause the HW to enter a unit hang state which can
3871 * only be released by PCI reset on the device
3872 *
3873 */
3874
3875static void e1000_flush_desc_rings(struct e1000_adapter *adapter)
3876{
3877 u16 hang_state;
3878 u32 fext_nvm11, tdlen;
3879 struct e1000_hw *hw = &adapter->hw;
3880
3881 /* First, disable MULR fix in FEXTNVM11 */
3882 fext_nvm11 = er32(FEXTNVM11);
3883 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
3884 ew32(FEXTNVM11, fext_nvm11);
3885 /* do nothing if we're not in faulty state, or if the queue is empty */
3886 tdlen = er32(TDLEN(0));
3887 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3888 &hang_state);
3889 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
3890 return;
3891 e1000_flush_tx_ring(adapter);
3892 /* recheck, maybe the fault is caused by the rx ring */
3893 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3894 &hang_state);
3895 if (hang_state & FLUSH_DESC_REQUIRED)
3896 e1000_flush_rx_ring(adapter);
3897}
3898
3899/**
3900 * e1000e_systim_reset - reset the timesync registers after a hardware reset
3901 * @adapter: board private structure
3902 *
3903 * When the MAC is reset, all hardware bits for timesync will be reset to the
3904 * default values. This function will restore the settings last in place.
3905 * Since the clock SYSTIME registers are reset, we will simply restore the
3906 * cyclecounter to the kernel real clock time.
3907 **/
3908static void e1000e_systim_reset(struct e1000_adapter *adapter)
3909{
3910 struct ptp_clock_info *info = &adapter->ptp_clock_info;
3911 struct e1000_hw *hw = &adapter->hw;
3912 unsigned long flags;
3913 u32 timinca;
3914 s32 ret_val;
3915
3916 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3917 return;
3918
3919 if (info->adjfine) {
3920 /* restore the previous ptp frequency delta */
3921 ret_val = info->adjfine(info, adapter->ptp_delta);
3922 } else {
3923 /* set the default base frequency if no adjustment possible */
3924 ret_val = e1000e_get_base_timinca(adapter, &timinca);
3925 if (!ret_val)
3926 ew32(TIMINCA, timinca);
3927 }
3928
3929 if (ret_val) {
3930 dev_warn(&adapter->pdev->dev,
3931 "Failed to restore TIMINCA clock rate delta: %d\n",
3932 ret_val);
3933 return;
3934 }
3935
3936 /* reset the systim ns time counter */
3937 spin_lock_irqsave(&adapter->systim_lock, flags);
3938 timecounter_init(&adapter->tc, &adapter->cc,
3939 ktime_to_ns(ktime_get_real()));
3940 spin_unlock_irqrestore(&adapter->systim_lock, flags);
3941
3942 /* restore the previous hwtstamp configuration settings */
3943 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config);
3944}
3945
3946/**
3947 * e1000e_reset - bring the hardware into a known good state
3948 * @adapter: board private structure
3949 *
3950 * This function boots the hardware and enables some settings that
3951 * require a configuration cycle of the hardware - those cannot be
3952 * set/changed during runtime. After reset the device needs to be
3953 * properly configured for Rx, Tx etc.
3954 */
3955void e1000e_reset(struct e1000_adapter *adapter)
3956{
3957 struct e1000_mac_info *mac = &adapter->hw.mac;
3958 struct e1000_fc_info *fc = &adapter->hw.fc;
3959 struct e1000_hw *hw = &adapter->hw;
3960 u32 tx_space, min_tx_space, min_rx_space;
3961 u32 pba = adapter->pba;
3962 u16 hwm;
3963
3964 /* reset Packet Buffer Allocation to default */
3965 ew32(PBA, pba);
3966
3967 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) {
3968 /* To maintain wire speed transmits, the Tx FIFO should be
3969 * large enough to accommodate two full transmit packets,
3970 * rounded up to the next 1KB and expressed in KB. Likewise,
3971 * the Rx FIFO should be large enough to accommodate at least
3972 * one full receive packet and is similarly rounded up and
3973 * expressed in KB.
3974 */
3975 pba = er32(PBA);
3976 /* upper 16 bits has Tx packet buffer allocation size in KB */
3977 tx_space = pba >> 16;
3978 /* lower 16 bits has Rx packet buffer allocation size in KB */
3979 pba &= 0xffff;
3980 /* the Tx fifo also stores 16 bytes of information about the Tx
3981 * but don't include ethernet FCS because hardware appends it
3982 */
3983 min_tx_space = (adapter->max_frame_size +
3984 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
3985 min_tx_space = ALIGN(min_tx_space, 1024);
3986 min_tx_space >>= 10;
3987 /* software strips receive CRC, so leave room for it */
3988 min_rx_space = adapter->max_frame_size;
3989 min_rx_space = ALIGN(min_rx_space, 1024);
3990 min_rx_space >>= 10;
3991
3992 /* If current Tx allocation is less than the min Tx FIFO size,
3993 * and the min Tx FIFO size is less than the current Rx FIFO
3994 * allocation, take space away from current Rx allocation
3995 */
3996 if ((tx_space < min_tx_space) &&
3997 ((min_tx_space - tx_space) < pba)) {
3998 pba -= min_tx_space - tx_space;
3999
4000 /* if short on Rx space, Rx wins and must trump Tx
4001 * adjustment
4002 */
4003 if (pba < min_rx_space)
4004 pba = min_rx_space;
4005 }
4006
4007 ew32(PBA, pba);
4008 }
4009
4010 /* flow control settings
4011 *
4012 * The high water mark must be low enough to fit one full frame
4013 * (or the size used for early receive) above it in the Rx FIFO.
4014 * Set it to the lower of:
4015 * - 90% of the Rx FIFO size, and
4016 * - the full Rx FIFO size minus one full frame
4017 */
4018 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
4019 fc->pause_time = 0xFFFF;
4020 else
4021 fc->pause_time = E1000_FC_PAUSE_TIME;
4022 fc->send_xon = true;
4023 fc->current_mode = fc->requested_mode;
4024
4025 switch (hw->mac.type) {
4026 case e1000_ich9lan:
4027 case e1000_ich10lan:
4028 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4029 pba = 14;
4030 ew32(PBA, pba);
4031 fc->high_water = 0x2800;
4032 fc->low_water = fc->high_water - 8;
4033 break;
4034 }
4035 fallthrough;
4036 default:
4037 hwm = min(((pba << 10) * 9 / 10),
4038 ((pba << 10) - adapter->max_frame_size));
4039
4040 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
4041 fc->low_water = fc->high_water - 8;
4042 break;
4043 case e1000_pchlan:
4044 /* Workaround PCH LOM adapter hangs with certain network
4045 * loads. If hangs persist, try disabling Tx flow control.
4046 */
4047 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4048 fc->high_water = 0x3500;
4049 fc->low_water = 0x1500;
4050 } else {
4051 fc->high_water = 0x5000;
4052 fc->low_water = 0x3000;
4053 }
4054 fc->refresh_time = 0x1000;
4055 break;
4056 case e1000_pch2lan:
4057 case e1000_pch_lpt:
4058 case e1000_pch_spt:
4059 case e1000_pch_cnp:
4060 case e1000_pch_tgp:
4061 case e1000_pch_adp:
4062 case e1000_pch_mtp:
4063 case e1000_pch_lnp:
4064 case e1000_pch_ptp:
4065 fc->refresh_time = 0xFFFF;
4066 fc->pause_time = 0xFFFF;
4067
4068 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
4069 fc->high_water = 0x05C20;
4070 fc->low_water = 0x05048;
4071 break;
4072 }
4073
4074 pba = 14;
4075 ew32(PBA, pba);
4076 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
4077 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
4078 break;
4079 }
4080
4081 /* Alignment of Tx data is on an arbitrary byte boundary with the
4082 * maximum size per Tx descriptor limited only to the transmit
4083 * allocation of the packet buffer minus 96 bytes with an upper
4084 * limit of 24KB due to receive synchronization limitations.
4085 */
4086 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
4087 24 << 10);
4088
4089 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
4090 * fit in receive buffer.
4091 */
4092 if (adapter->itr_setting & 0x3) {
4093 if ((adapter->max_frame_size * 2) > (pba << 10)) {
4094 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
4095 dev_info(&adapter->pdev->dev,
4096 "Interrupt Throttle Rate off\n");
4097 adapter->flags2 |= FLAG2_DISABLE_AIM;
4098 e1000e_write_itr(adapter, 0);
4099 }
4100 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
4101 dev_info(&adapter->pdev->dev,
4102 "Interrupt Throttle Rate on\n");
4103 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
4104 adapter->itr = 20000;
4105 e1000e_write_itr(adapter, adapter->itr);
4106 }
4107 }
4108
4109 if (hw->mac.type >= e1000_pch_spt)
4110 e1000_flush_desc_rings(adapter);
4111 /* Allow time for pending master requests to run */
4112 mac->ops.reset_hw(hw);
4113
4114 /* For parts with AMT enabled, let the firmware know
4115 * that the network interface is in control
4116 */
4117 if (adapter->flags & FLAG_HAS_AMT)
4118 e1000e_get_hw_control(adapter);
4119
4120 ew32(WUC, 0);
4121
4122 if (mac->ops.init_hw(hw))
4123 e_err("Hardware Error\n");
4124
4125 e1000_update_mng_vlan(adapter);
4126
4127 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
4128 ew32(VET, ETH_P_8021Q);
4129
4130 e1000e_reset_adaptive(hw);
4131
4132 /* restore systim and hwtstamp settings */
4133 e1000e_systim_reset(adapter);
4134
4135 /* Set EEE advertisement as appropriate */
4136 if (adapter->flags2 & FLAG2_HAS_EEE) {
4137 s32 ret_val;
4138 u16 adv_addr;
4139
4140 switch (hw->phy.type) {
4141 case e1000_phy_82579:
4142 adv_addr = I82579_EEE_ADVERTISEMENT;
4143 break;
4144 case e1000_phy_i217:
4145 adv_addr = I217_EEE_ADVERTISEMENT;
4146 break;
4147 default:
4148 dev_err(&adapter->pdev->dev,
4149 "Invalid PHY type setting EEE advertisement\n");
4150 return;
4151 }
4152
4153 ret_val = hw->phy.ops.acquire(hw);
4154 if (ret_val) {
4155 dev_err(&adapter->pdev->dev,
4156 "EEE advertisement - unable to acquire PHY\n");
4157 return;
4158 }
4159
4160 e1000_write_emi_reg_locked(hw, adv_addr,
4161 hw->dev_spec.ich8lan.eee_disable ?
4162 0 : adapter->eee_advert);
4163
4164 hw->phy.ops.release(hw);
4165 }
4166
4167 if (!netif_running(adapter->netdev) &&
4168 !test_bit(__E1000_TESTING, &adapter->state))
4169 e1000_power_down_phy(adapter);
4170
4171 e1000_get_phy_info(hw);
4172
4173 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
4174 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
4175 u16 phy_data = 0;
4176 /* speed up time to link by disabling smart power down, ignore
4177 * the return value of this function because there is nothing
4178 * different we would do if it failed
4179 */
4180 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
4181 phy_data &= ~IGP02E1000_PM_SPD;
4182 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
4183 }
4184 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) {
4185 u32 reg;
4186
4187 /* Fextnvm7 @ 0xe4[2] = 1 */
4188 reg = er32(FEXTNVM7);
4189 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE;
4190 ew32(FEXTNVM7, reg);
4191 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */
4192 reg = er32(FEXTNVM9);
4193 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS |
4194 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4195 ew32(FEXTNVM9, reg);
4196 }
4197
4198}
4199
4200/**
4201 * e1000e_trigger_lsc - trigger an LSC interrupt
4202 * @adapter:
4203 *
4204 * Fire a link status change interrupt to start the watchdog.
4205 **/
4206static void e1000e_trigger_lsc(struct e1000_adapter *adapter)
4207{
4208 struct e1000_hw *hw = &adapter->hw;
4209
4210 if (adapter->msix_entries)
4211 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER);
4212 else
4213 ew32(ICS, E1000_ICS_LSC);
4214}
4215
4216void e1000e_up(struct e1000_adapter *adapter)
4217{
4218 /* hardware has been reset, we need to reload some things */
4219 e1000_configure(adapter);
4220
4221 clear_bit(__E1000_DOWN, &adapter->state);
4222
4223 if (adapter->msix_entries)
4224 e1000_configure_msix(adapter);
4225 e1000_irq_enable(adapter);
4226
4227 /* Tx queue started by watchdog timer when link is up */
4228
4229 e1000e_trigger_lsc(adapter);
4230}
4231
4232static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
4233{
4234 struct e1000_hw *hw = &adapter->hw;
4235
4236 if (!(adapter->flags2 & FLAG2_DMA_BURST))
4237 return;
4238
4239 /* flush pending descriptor writebacks to memory */
4240 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4241 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4242
4243 /* execute the writes immediately */
4244 e1e_flush();
4245
4246 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
4247 * write is successful
4248 */
4249 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4250 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4251
4252 /* execute the writes immediately */
4253 e1e_flush();
4254}
4255
4256static void e1000e_update_stats(struct e1000_adapter *adapter);
4257
4258/**
4259 * e1000e_down - quiesce the device and optionally reset the hardware
4260 * @adapter: board private structure
4261 * @reset: boolean flag to reset the hardware or not
4262 */
4263void e1000e_down(struct e1000_adapter *adapter, bool reset)
4264{
4265 struct net_device *netdev = adapter->netdev;
4266 struct e1000_hw *hw = &adapter->hw;
4267 u32 tctl, rctl;
4268
4269 /* signal that we're down so the interrupt handler does not
4270 * reschedule our watchdog timer
4271 */
4272 set_bit(__E1000_DOWN, &adapter->state);
4273
4274 netif_carrier_off(netdev);
4275
4276 /* disable receives in the hardware */
4277 rctl = er32(RCTL);
4278 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4279 ew32(RCTL, rctl & ~E1000_RCTL_EN);
4280 /* flush and sleep below */
4281
4282 netif_stop_queue(netdev);
4283
4284 /* disable transmits in the hardware */
4285 tctl = er32(TCTL);
4286 tctl &= ~E1000_TCTL_EN;
4287 ew32(TCTL, tctl);
4288
4289 /* flush both disables and wait for them to finish */
4290 e1e_flush();
4291 usleep_range(10000, 11000);
4292
4293 e1000_irq_disable(adapter);
4294
4295 napi_synchronize(&adapter->napi);
4296
4297 del_timer_sync(&adapter->watchdog_timer);
4298 del_timer_sync(&adapter->phy_info_timer);
4299
4300 spin_lock(&adapter->stats64_lock);
4301 e1000e_update_stats(adapter);
4302 spin_unlock(&adapter->stats64_lock);
4303
4304 e1000e_flush_descriptors(adapter);
4305
4306 adapter->link_speed = 0;
4307 adapter->link_duplex = 0;
4308
4309 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4310 if ((hw->mac.type >= e1000_pch2lan) &&
4311 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4312 e1000_lv_jumbo_workaround_ich8lan(hw, false))
4313 e_dbg("failed to disable jumbo frame workaround mode\n");
4314
4315 if (!pci_channel_offline(adapter->pdev)) {
4316 if (reset)
4317 e1000e_reset(adapter);
4318 else if (hw->mac.type >= e1000_pch_spt)
4319 e1000_flush_desc_rings(adapter);
4320 }
4321 e1000_clean_tx_ring(adapter->tx_ring);
4322 e1000_clean_rx_ring(adapter->rx_ring);
4323}
4324
4325void e1000e_reinit_locked(struct e1000_adapter *adapter)
4326{
4327 might_sleep();
4328 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
4329 usleep_range(1000, 1100);
4330 e1000e_down(adapter, true);
4331 e1000e_up(adapter);
4332 clear_bit(__E1000_RESETTING, &adapter->state);
4333}
4334
4335/**
4336 * e1000e_sanitize_systim - sanitize raw cycle counter reads
4337 * @hw: pointer to the HW structure
4338 * @systim: PHC time value read, sanitized and returned
4339 * @sts: structure to hold system time before and after reading SYSTIML,
4340 * may be NULL
4341 *
4342 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L:
4343 * check to see that the time is incrementing at a reasonable
4344 * rate and is a multiple of incvalue.
4345 **/
4346static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim,
4347 struct ptp_system_timestamp *sts)
4348{
4349 u64 time_delta, rem, temp;
4350 u64 systim_next;
4351 u32 incvalue;
4352 int i;
4353
4354 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK;
4355 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) {
4356 /* latch SYSTIMH on read of SYSTIML */
4357 ptp_read_system_prets(sts);
4358 systim_next = (u64)er32(SYSTIML);
4359 ptp_read_system_postts(sts);
4360 systim_next |= (u64)er32(SYSTIMH) << 32;
4361
4362 time_delta = systim_next - systim;
4363 temp = time_delta;
4364 /* VMWare users have seen incvalue of zero, don't div / 0 */
4365 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0);
4366
4367 systim = systim_next;
4368
4369 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0))
4370 break;
4371 }
4372
4373 return systim;
4374}
4375
4376/**
4377 * e1000e_read_systim - read SYSTIM register
4378 * @adapter: board private structure
4379 * @sts: structure which will contain system time before and after reading
4380 * SYSTIML, may be NULL
4381 **/
4382u64 e1000e_read_systim(struct e1000_adapter *adapter,
4383 struct ptp_system_timestamp *sts)
4384{
4385 struct e1000_hw *hw = &adapter->hw;
4386 u32 systimel, systimel_2, systimeh;
4387 u64 systim;
4388 /* SYSTIMH latching upon SYSTIML read does not work well.
4389 * This means that if SYSTIML overflows after we read it but before
4390 * we read SYSTIMH, the value of SYSTIMH has been incremented and we
4391 * will experience a huge non linear increment in the systime value
4392 * to fix that we test for overflow and if true, we re-read systime.
4393 */
4394 ptp_read_system_prets(sts);
4395 systimel = er32(SYSTIML);
4396 ptp_read_system_postts(sts);
4397 systimeh = er32(SYSTIMH);
4398 /* Is systimel is so large that overflow is possible? */
4399 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) {
4400 ptp_read_system_prets(sts);
4401 systimel_2 = er32(SYSTIML);
4402 ptp_read_system_postts(sts);
4403 if (systimel > systimel_2) {
4404 /* There was an overflow, read again SYSTIMH, and use
4405 * systimel_2
4406 */
4407 systimeh = er32(SYSTIMH);
4408 systimel = systimel_2;
4409 }
4410 }
4411 systim = (u64)systimel;
4412 systim |= (u64)systimeh << 32;
4413
4414 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW)
4415 systim = e1000e_sanitize_systim(hw, systim, sts);
4416
4417 return systim;
4418}
4419
4420/**
4421 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4422 * @cc: cyclecounter structure
4423 **/
4424static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc)
4425{
4426 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4427 cc);
4428
4429 return e1000e_read_systim(adapter, NULL);
4430}
4431
4432/**
4433 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4434 * @adapter: board private structure to initialize
4435 *
4436 * e1000_sw_init initializes the Adapter private data structure.
4437 * Fields are initialized based on PCI device information and
4438 * OS network device settings (MTU size).
4439 **/
4440static int e1000_sw_init(struct e1000_adapter *adapter)
4441{
4442 struct net_device *netdev = adapter->netdev;
4443
4444 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
4445 adapter->rx_ps_bsize0 = 128;
4446 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4447 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4448 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4449 adapter->rx_ring_count = E1000_DEFAULT_RXD;
4450
4451 spin_lock_init(&adapter->stats64_lock);
4452
4453 e1000e_set_interrupt_capability(adapter);
4454
4455 if (e1000_alloc_queues(adapter))
4456 return -ENOMEM;
4457
4458 /* Setup hardware time stamping cyclecounter */
4459 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4460 adapter->cc.read = e1000e_cyclecounter_read;
4461 adapter->cc.mask = CYCLECOUNTER_MASK(64);
4462 adapter->cc.mult = 1;
4463 /* cc.shift set in e1000e_get_base_tininca() */
4464
4465 spin_lock_init(&adapter->systim_lock);
4466 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4467 }
4468
4469 /* Explicitly disable IRQ since the NIC can be in any state. */
4470 e1000_irq_disable(adapter);
4471
4472 set_bit(__E1000_DOWN, &adapter->state);
4473 return 0;
4474}
4475
4476/**
4477 * e1000_intr_msi_test - Interrupt Handler
4478 * @irq: interrupt number
4479 * @data: pointer to a network interface device structure
4480 **/
4481static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
4482{
4483 struct net_device *netdev = data;
4484 struct e1000_adapter *adapter = netdev_priv(netdev);
4485 struct e1000_hw *hw = &adapter->hw;
4486 u32 icr = er32(ICR);
4487
4488 e_dbg("icr is %08X\n", icr);
4489 if (icr & E1000_ICR_RXSEQ) {
4490 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
4491 /* Force memory writes to complete before acknowledging the
4492 * interrupt is handled.
4493 */
4494 wmb();
4495 }
4496
4497 return IRQ_HANDLED;
4498}
4499
4500/**
4501 * e1000_test_msi_interrupt - Returns 0 for successful test
4502 * @adapter: board private struct
4503 *
4504 * code flow taken from tg3.c
4505 **/
4506static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4507{
4508 struct net_device *netdev = adapter->netdev;
4509 struct e1000_hw *hw = &adapter->hw;
4510 int err;
4511
4512 /* poll_enable hasn't been called yet, so don't need disable */
4513 /* clear any pending events */
4514 er32(ICR);
4515
4516 /* free the real vector and request a test handler */
4517 e1000_free_irq(adapter);
4518 e1000e_reset_interrupt_capability(adapter);
4519
4520 /* Assume that the test fails, if it succeeds then the test
4521 * MSI irq handler will unset this flag
4522 */
4523 adapter->flags |= FLAG_MSI_TEST_FAILED;
4524
4525 err = pci_enable_msi(adapter->pdev);
4526 if (err)
4527 goto msi_test_failed;
4528
4529 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
4530 netdev->name, netdev);
4531 if (err) {
4532 pci_disable_msi(adapter->pdev);
4533 goto msi_test_failed;
4534 }
4535
4536 /* Force memory writes to complete before enabling and firing an
4537 * interrupt.
4538 */
4539 wmb();
4540
4541 e1000_irq_enable(adapter);
4542
4543 /* fire an unusual interrupt on the test handler */
4544 ew32(ICS, E1000_ICS_RXSEQ);
4545 e1e_flush();
4546 msleep(100);
4547
4548 e1000_irq_disable(adapter);
4549
4550 rmb(); /* read flags after interrupt has been fired */
4551
4552 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4553 adapter->int_mode = E1000E_INT_MODE_LEGACY;
4554 e_info("MSI interrupt test failed, using legacy interrupt.\n");
4555 } else {
4556 e_dbg("MSI interrupt test succeeded!\n");
4557 }
4558
4559 free_irq(adapter->pdev->irq, netdev);
4560 pci_disable_msi(adapter->pdev);
4561
4562msi_test_failed:
4563 e1000e_set_interrupt_capability(adapter);
4564 return e1000_request_irq(adapter);
4565}
4566
4567/**
4568 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4569 * @adapter: board private struct
4570 *
4571 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4572 **/
4573static int e1000_test_msi(struct e1000_adapter *adapter)
4574{
4575 int err;
4576 u16 pci_cmd;
4577
4578 if (!(adapter->flags & FLAG_MSI_ENABLED))
4579 return 0;
4580
4581 /* disable SERR in case the MSI write causes a master abort */
4582 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4583 if (pci_cmd & PCI_COMMAND_SERR)
4584 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4585 pci_cmd & ~PCI_COMMAND_SERR);
4586
4587 err = e1000_test_msi_interrupt(adapter);
4588
4589 /* re-enable SERR */
4590 if (pci_cmd & PCI_COMMAND_SERR) {
4591 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4592 pci_cmd |= PCI_COMMAND_SERR;
4593 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4594 }
4595
4596 return err;
4597}
4598
4599/**
4600 * e1000e_open - Called when a network interface is made active
4601 * @netdev: network interface device structure
4602 *
4603 * Returns 0 on success, negative value on failure
4604 *
4605 * The open entry point is called when a network interface is made
4606 * active by the system (IFF_UP). At this point all resources needed
4607 * for transmit and receive operations are allocated, the interrupt
4608 * handler is registered with the OS, the watchdog timer is started,
4609 * and the stack is notified that the interface is ready.
4610 **/
4611int e1000e_open(struct net_device *netdev)
4612{
4613 struct e1000_adapter *adapter = netdev_priv(netdev);
4614 struct e1000_hw *hw = &adapter->hw;
4615 struct pci_dev *pdev = adapter->pdev;
4616 int err;
4617
4618 /* disallow open during test */
4619 if (test_bit(__E1000_TESTING, &adapter->state))
4620 return -EBUSY;
4621
4622 pm_runtime_get_sync(&pdev->dev);
4623
4624 netif_carrier_off(netdev);
4625 netif_stop_queue(netdev);
4626
4627 /* allocate transmit descriptors */
4628 err = e1000e_setup_tx_resources(adapter->tx_ring);
4629 if (err)
4630 goto err_setup_tx;
4631
4632 /* allocate receive descriptors */
4633 err = e1000e_setup_rx_resources(adapter->rx_ring);
4634 if (err)
4635 goto err_setup_rx;
4636
4637 /* If AMT is enabled, let the firmware know that the network
4638 * interface is now open and reset the part to a known state.
4639 */
4640 if (adapter->flags & FLAG_HAS_AMT) {
4641 e1000e_get_hw_control(adapter);
4642 e1000e_reset(adapter);
4643 }
4644
4645 e1000e_power_up_phy(adapter);
4646
4647 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4648 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4649 e1000_update_mng_vlan(adapter);
4650
4651 /* DMA latency requirement to workaround jumbo issue */
4652 cpu_latency_qos_add_request(&adapter->pm_qos_req, PM_QOS_DEFAULT_VALUE);
4653
4654 /* before we allocate an interrupt, we must be ready to handle it.
4655 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4656 * as soon as we call pci_request_irq, so we have to setup our
4657 * clean_rx handler before we do so.
4658 */
4659 e1000_configure(adapter);
4660
4661 err = e1000_request_irq(adapter);
4662 if (err)
4663 goto err_req_irq;
4664
4665 /* Work around PCIe errata with MSI interrupts causing some chipsets to
4666 * ignore e1000e MSI messages, which means we need to test our MSI
4667 * interrupt now
4668 */
4669 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
4670 err = e1000_test_msi(adapter);
4671 if (err) {
4672 e_err("Interrupt allocation failed\n");
4673 goto err_req_irq;
4674 }
4675 }
4676
4677 /* From here on the code is the same as e1000e_up() */
4678 clear_bit(__E1000_DOWN, &adapter->state);
4679
4680 napi_enable(&adapter->napi);
4681
4682 e1000_irq_enable(adapter);
4683
4684 adapter->tx_hang_recheck = false;
4685
4686 hw->mac.get_link_status = true;
4687 pm_runtime_put(&pdev->dev);
4688
4689 e1000e_trigger_lsc(adapter);
4690
4691 return 0;
4692
4693err_req_irq:
4694 cpu_latency_qos_remove_request(&adapter->pm_qos_req);
4695 e1000e_release_hw_control(adapter);
4696 e1000_power_down_phy(adapter);
4697 e1000e_free_rx_resources(adapter->rx_ring);
4698err_setup_rx:
4699 e1000e_free_tx_resources(adapter->tx_ring);
4700err_setup_tx:
4701 e1000e_reset(adapter);
4702 pm_runtime_put_sync(&pdev->dev);
4703
4704 return err;
4705}
4706
4707/**
4708 * e1000e_close - Disables a network interface
4709 * @netdev: network interface device structure
4710 *
4711 * Returns 0, this is not allowed to fail
4712 *
4713 * The close entry point is called when an interface is de-activated
4714 * by the OS. The hardware is still under the drivers control, but
4715 * needs to be disabled. A global MAC reset is issued to stop the
4716 * hardware, and all transmit and receive resources are freed.
4717 **/
4718int e1000e_close(struct net_device *netdev)
4719{
4720 struct e1000_adapter *adapter = netdev_priv(netdev);
4721 struct pci_dev *pdev = adapter->pdev;
4722 int count = E1000_CHECK_RESET_COUNT;
4723
4724 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4725 usleep_range(10000, 11000);
4726
4727 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
4728
4729 pm_runtime_get_sync(&pdev->dev);
4730
4731 if (netif_device_present(netdev)) {
4732 e1000e_down(adapter, true);
4733 e1000_free_irq(adapter);
4734
4735 /* Link status message must follow this format */
4736 netdev_info(netdev, "NIC Link is Down\n");
4737 }
4738
4739 napi_disable(&adapter->napi);
4740
4741 e1000e_free_tx_resources(adapter->tx_ring);
4742 e1000e_free_rx_resources(adapter->rx_ring);
4743
4744 /* kill manageability vlan ID if supported, but not if a vlan with
4745 * the same ID is registered on the host OS (let 8021q kill it)
4746 */
4747 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
4748 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4749 adapter->mng_vlan_id);
4750
4751 /* If AMT is enabled, let the firmware know that the network
4752 * interface is now closed
4753 */
4754 if ((adapter->flags & FLAG_HAS_AMT) &&
4755 !test_bit(__E1000_TESTING, &adapter->state))
4756 e1000e_release_hw_control(adapter);
4757
4758 cpu_latency_qos_remove_request(&adapter->pm_qos_req);
4759
4760 pm_runtime_put_sync(&pdev->dev);
4761
4762 return 0;
4763}
4764
4765/**
4766 * e1000_set_mac - Change the Ethernet Address of the NIC
4767 * @netdev: network interface device structure
4768 * @p: pointer to an address structure
4769 *
4770 * Returns 0 on success, negative on failure
4771 **/
4772static int e1000_set_mac(struct net_device *netdev, void *p)
4773{
4774 struct e1000_adapter *adapter = netdev_priv(netdev);
4775 struct e1000_hw *hw = &adapter->hw;
4776 struct sockaddr *addr = p;
4777
4778 if (!is_valid_ether_addr(addr->sa_data))
4779 return -EADDRNOTAVAIL;
4780
4781 eth_hw_addr_set(netdev, addr->sa_data);
4782 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4783
4784 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4785
4786 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4787 /* activate the work around */
4788 e1000e_set_laa_state_82571(&adapter->hw, 1);
4789
4790 /* Hold a copy of the LAA in RAR[14] This is done so that
4791 * between the time RAR[0] gets clobbered and the time it
4792 * gets fixed (in e1000_watchdog), the actual LAA is in one
4793 * of the RARs and no incoming packets directed to this port
4794 * are dropped. Eventually the LAA will be in RAR[0] and
4795 * RAR[14]
4796 */
4797 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4798 adapter->hw.mac.rar_entry_count - 1);
4799 }
4800
4801 return 0;
4802}
4803
4804/**
4805 * e1000e_update_phy_task - work thread to update phy
4806 * @work: pointer to our work struct
4807 *
4808 * this worker thread exists because we must acquire a
4809 * semaphore to read the phy, which we could msleep while
4810 * waiting for it, and we can't msleep in a timer.
4811 **/
4812static void e1000e_update_phy_task(struct work_struct *work)
4813{
4814 struct e1000_adapter *adapter = container_of(work,
4815 struct e1000_adapter,
4816 update_phy_task);
4817 struct e1000_hw *hw = &adapter->hw;
4818
4819 if (test_bit(__E1000_DOWN, &adapter->state))
4820 return;
4821
4822 e1000_get_phy_info(hw);
4823
4824 /* Enable EEE on 82579 after link up */
4825 if (hw->phy.type >= e1000_phy_82579)
4826 e1000_set_eee_pchlan(hw);
4827}
4828
4829/**
4830 * e1000_update_phy_info - timre call-back to update PHY info
4831 * @t: pointer to timer_list containing private info adapter
4832 *
4833 * Need to wait a few seconds after link up to get diagnostic information from
4834 * the phy
4835 **/
4836static void e1000_update_phy_info(struct timer_list *t)
4837{
4838 struct e1000_adapter *adapter = from_timer(adapter, t, phy_info_timer);
4839
4840 if (test_bit(__E1000_DOWN, &adapter->state))
4841 return;
4842
4843 schedule_work(&adapter->update_phy_task);
4844}
4845
4846/**
4847 * e1000e_update_phy_stats - Update the PHY statistics counters
4848 * @adapter: board private structure
4849 *
4850 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4851 **/
4852static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4853{
4854 struct e1000_hw *hw = &adapter->hw;
4855 s32 ret_val;
4856 u16 phy_data;
4857
4858 ret_val = hw->phy.ops.acquire(hw);
4859 if (ret_val)
4860 return;
4861
4862 /* A page set is expensive so check if already on desired page.
4863 * If not, set to the page with the PHY status registers.
4864 */
4865 hw->phy.addr = 1;
4866 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4867 &phy_data);
4868 if (ret_val)
4869 goto release;
4870 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4871 ret_val = hw->phy.ops.set_page(hw,
4872 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4873 if (ret_val)
4874 goto release;
4875 }
4876
4877 /* Single Collision Count */
4878 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4879 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4880 if (!ret_val)
4881 adapter->stats.scc += phy_data;
4882
4883 /* Excessive Collision Count */
4884 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4885 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4886 if (!ret_val)
4887 adapter->stats.ecol += phy_data;
4888
4889 /* Multiple Collision Count */
4890 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4891 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4892 if (!ret_val)
4893 adapter->stats.mcc += phy_data;
4894
4895 /* Late Collision Count */
4896 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4897 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4898 if (!ret_val)
4899 adapter->stats.latecol += phy_data;
4900
4901 /* Collision Count - also used for adaptive IFS */
4902 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4903 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4904 if (!ret_val)
4905 hw->mac.collision_delta = phy_data;
4906
4907 /* Defer Count */
4908 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4909 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4910 if (!ret_val)
4911 adapter->stats.dc += phy_data;
4912
4913 /* Transmit with no CRS */
4914 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4915 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4916 if (!ret_val)
4917 adapter->stats.tncrs += phy_data;
4918
4919release:
4920 hw->phy.ops.release(hw);
4921}
4922
4923/**
4924 * e1000e_update_stats - Update the board statistics counters
4925 * @adapter: board private structure
4926 **/
4927static void e1000e_update_stats(struct e1000_adapter *adapter)
4928{
4929 struct net_device *netdev = adapter->netdev;
4930 struct e1000_hw *hw = &adapter->hw;
4931 struct pci_dev *pdev = adapter->pdev;
4932
4933 /* Prevent stats update while adapter is being reset, or if the pci
4934 * connection is down.
4935 */
4936 if (adapter->link_speed == 0)
4937 return;
4938 if (pci_channel_offline(pdev))
4939 return;
4940
4941 adapter->stats.crcerrs += er32(CRCERRS);
4942 adapter->stats.gprc += er32(GPRC);
4943 adapter->stats.gorc += er32(GORCL);
4944 er32(GORCH); /* Clear gorc */
4945 adapter->stats.bprc += er32(BPRC);
4946 adapter->stats.mprc += er32(MPRC);
4947 adapter->stats.roc += er32(ROC);
4948
4949 adapter->stats.mpc += er32(MPC);
4950
4951 /* Half-duplex statistics */
4952 if (adapter->link_duplex == HALF_DUPLEX) {
4953 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4954 e1000e_update_phy_stats(adapter);
4955 } else {
4956 adapter->stats.scc += er32(SCC);
4957 adapter->stats.ecol += er32(ECOL);
4958 adapter->stats.mcc += er32(MCC);
4959 adapter->stats.latecol += er32(LATECOL);
4960 adapter->stats.dc += er32(DC);
4961
4962 hw->mac.collision_delta = er32(COLC);
4963
4964 if ((hw->mac.type != e1000_82574) &&
4965 (hw->mac.type != e1000_82583))
4966 adapter->stats.tncrs += er32(TNCRS);
4967 }
4968 adapter->stats.colc += hw->mac.collision_delta;
4969 }
4970
4971 adapter->stats.xonrxc += er32(XONRXC);
4972 adapter->stats.xontxc += er32(XONTXC);
4973 adapter->stats.xoffrxc += er32(XOFFRXC);
4974 adapter->stats.xofftxc += er32(XOFFTXC);
4975 adapter->stats.gptc += er32(GPTC);
4976 adapter->stats.gotc += er32(GOTCL);
4977 er32(GOTCH); /* Clear gotc */
4978 adapter->stats.rnbc += er32(RNBC);
4979 adapter->stats.ruc += er32(RUC);
4980
4981 adapter->stats.mptc += er32(MPTC);
4982 adapter->stats.bptc += er32(BPTC);
4983
4984 /* used for adaptive IFS */
4985
4986 hw->mac.tx_packet_delta = er32(TPT);
4987 adapter->stats.tpt += hw->mac.tx_packet_delta;
4988
4989 adapter->stats.algnerrc += er32(ALGNERRC);
4990 adapter->stats.rxerrc += er32(RXERRC);
4991 adapter->stats.cexterr += er32(CEXTERR);
4992 adapter->stats.tsctc += er32(TSCTC);
4993 adapter->stats.tsctfc += er32(TSCTFC);
4994
4995 /* Fill out the OS statistics structure */
4996 netdev->stats.multicast = adapter->stats.mprc;
4997 netdev->stats.collisions = adapter->stats.colc;
4998
4999 /* Rx Errors */
5000
5001 /* RLEC on some newer hardware can be incorrect so build
5002 * our own version based on RUC and ROC
5003 */
5004 netdev->stats.rx_errors = adapter->stats.rxerrc +
5005 adapter->stats.crcerrs + adapter->stats.algnerrc +
5006 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5007 netdev->stats.rx_length_errors = adapter->stats.ruc +
5008 adapter->stats.roc;
5009 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5010 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
5011 netdev->stats.rx_missed_errors = adapter->stats.mpc;
5012
5013 /* Tx Errors */
5014 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
5015 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
5016 netdev->stats.tx_window_errors = adapter->stats.latecol;
5017 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
5018
5019 /* Tx Dropped needs to be maintained elsewhere */
5020
5021 /* Management Stats */
5022 adapter->stats.mgptc += er32(MGTPTC);
5023 adapter->stats.mgprc += er32(MGTPRC);
5024 adapter->stats.mgpdc += er32(MGTPDC);
5025
5026 /* Correctable ECC Errors */
5027 if (hw->mac.type >= e1000_pch_lpt) {
5028 u32 pbeccsts = er32(PBECCSTS);
5029
5030 adapter->corr_errors +=
5031 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
5032 adapter->uncorr_errors +=
5033 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
5034 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
5035 }
5036}
5037
5038/**
5039 * e1000_phy_read_status - Update the PHY register status snapshot
5040 * @adapter: board private structure
5041 **/
5042static void e1000_phy_read_status(struct e1000_adapter *adapter)
5043{
5044 struct e1000_hw *hw = &adapter->hw;
5045 struct e1000_phy_regs *phy = &adapter->phy_regs;
5046
5047 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
5048 (er32(STATUS) & E1000_STATUS_LU) &&
5049 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
5050 int ret_val;
5051
5052 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
5053 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
5054 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
5055 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
5056 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
5057 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
5058 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
5059 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
5060 if (ret_val)
5061 e_warn("Error reading PHY register\n");
5062 } else {
5063 /* Do not read PHY registers if link is not up
5064 * Set values to typical power-on defaults
5065 */
5066 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
5067 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
5068 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
5069 BMSR_ERCAP);
5070 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
5071 ADVERTISE_ALL | ADVERTISE_CSMA);
5072 phy->lpa = 0;
5073 phy->expansion = EXPANSION_ENABLENPAGE;
5074 phy->ctrl1000 = ADVERTISE_1000FULL;
5075 phy->stat1000 = 0;
5076 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
5077 }
5078}
5079
5080static void e1000_print_link_info(struct e1000_adapter *adapter)
5081{
5082 struct e1000_hw *hw = &adapter->hw;
5083 u32 ctrl = er32(CTRL);
5084
5085 /* Link status message must follow this format for user tools */
5086 netdev_info(adapter->netdev,
5087 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5088 adapter->link_speed,
5089 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
5090 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
5091 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
5092 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
5093}
5094
5095static bool e1000e_has_link(struct e1000_adapter *adapter)
5096{
5097 struct e1000_hw *hw = &adapter->hw;
5098 bool link_active = false;
5099 s32 ret_val = 0;
5100
5101 /* get_link_status is set on LSC (link status) interrupt or
5102 * Rx sequence error interrupt. get_link_status will stay
5103 * true until the check_for_link establishes link
5104 * for copper adapters ONLY
5105 */
5106 switch (hw->phy.media_type) {
5107 case e1000_media_type_copper:
5108 if (hw->mac.get_link_status) {
5109 ret_val = hw->mac.ops.check_for_link(hw);
5110 link_active = !hw->mac.get_link_status;
5111 } else {
5112 link_active = true;
5113 }
5114 break;
5115 case e1000_media_type_fiber:
5116 ret_val = hw->mac.ops.check_for_link(hw);
5117 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
5118 break;
5119 case e1000_media_type_internal_serdes:
5120 ret_val = hw->mac.ops.check_for_link(hw);
5121 link_active = hw->mac.serdes_has_link;
5122 break;
5123 default:
5124 case e1000_media_type_unknown:
5125 break;
5126 }
5127
5128 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
5129 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
5130 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
5131 e_info("Gigabit has been disabled, downgrading speed\n");
5132 }
5133
5134 return link_active;
5135}
5136
5137static void e1000e_enable_receives(struct e1000_adapter *adapter)
5138{
5139 /* make sure the receive unit is started */
5140 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5141 (adapter->flags & FLAG_RESTART_NOW)) {
5142 struct e1000_hw *hw = &adapter->hw;
5143 u32 rctl = er32(RCTL);
5144
5145 ew32(RCTL, rctl | E1000_RCTL_EN);
5146 adapter->flags &= ~FLAG_RESTART_NOW;
5147 }
5148}
5149
5150static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
5151{
5152 struct e1000_hw *hw = &adapter->hw;
5153
5154 /* With 82574 controllers, PHY needs to be checked periodically
5155 * for hung state and reset, if two calls return true
5156 */
5157 if (e1000_check_phy_82574(hw))
5158 adapter->phy_hang_count++;
5159 else
5160 adapter->phy_hang_count = 0;
5161
5162 if (adapter->phy_hang_count > 1) {
5163 adapter->phy_hang_count = 0;
5164 e_dbg("PHY appears hung - resetting\n");
5165 schedule_work(&adapter->reset_task);
5166 }
5167}
5168
5169/**
5170 * e1000_watchdog - Timer Call-back
5171 * @t: pointer to timer_list containing private info adapter
5172 **/
5173static void e1000_watchdog(struct timer_list *t)
5174{
5175 struct e1000_adapter *adapter = from_timer(adapter, t, watchdog_timer);
5176
5177 /* Do the rest outside of interrupt context */
5178 schedule_work(&adapter->watchdog_task);
5179
5180 /* TODO: make this use queue_delayed_work() */
5181}
5182
5183static void e1000_watchdog_task(struct work_struct *work)
5184{
5185 struct e1000_adapter *adapter = container_of(work,
5186 struct e1000_adapter,
5187 watchdog_task);
5188 struct net_device *netdev = adapter->netdev;
5189 struct e1000_mac_info *mac = &adapter->hw.mac;
5190 struct e1000_phy_info *phy = &adapter->hw.phy;
5191 struct e1000_ring *tx_ring = adapter->tx_ring;
5192 u32 dmoff_exit_timeout = 100, tries = 0;
5193 struct e1000_hw *hw = &adapter->hw;
5194 u32 link, tctl, pcim_state;
5195
5196 if (test_bit(__E1000_DOWN, &adapter->state))
5197 return;
5198
5199 link = e1000e_has_link(adapter);
5200 if ((netif_carrier_ok(netdev)) && link) {
5201 /* Cancel scheduled suspend requests. */
5202 pm_runtime_resume(netdev->dev.parent);
5203
5204 e1000e_enable_receives(adapter);
5205 goto link_up;
5206 }
5207
5208 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
5209 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
5210 e1000_update_mng_vlan(adapter);
5211
5212 if (link) {
5213 if (!netif_carrier_ok(netdev)) {
5214 bool txb2b = true;
5215
5216 /* Cancel scheduled suspend requests. */
5217 pm_runtime_resume(netdev->dev.parent);
5218
5219 /* Checking if MAC is in DMoff state*/
5220 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
5221 pcim_state = er32(STATUS);
5222 while (pcim_state & E1000_STATUS_PCIM_STATE) {
5223 if (tries++ == dmoff_exit_timeout) {
5224 e_dbg("Error in exiting dmoff\n");
5225 break;
5226 }
5227 usleep_range(10000, 20000);
5228 pcim_state = er32(STATUS);
5229
5230 /* Checking if MAC exited DMoff state */
5231 if (!(pcim_state & E1000_STATUS_PCIM_STATE))
5232 e1000_phy_hw_reset(&adapter->hw);
5233 }
5234 }
5235
5236 /* update snapshot of PHY registers on LSC */
5237 e1000_phy_read_status(adapter);
5238 mac->ops.get_link_up_info(&adapter->hw,
5239 &adapter->link_speed,
5240 &adapter->link_duplex);
5241 e1000_print_link_info(adapter);
5242
5243 /* check if SmartSpeed worked */
5244 e1000e_check_downshift(hw);
5245 if (phy->speed_downgraded)
5246 netdev_warn(netdev,
5247 "Link Speed was downgraded by SmartSpeed\n");
5248
5249 /* On supported PHYs, check for duplex mismatch only
5250 * if link has autonegotiated at 10/100 half
5251 */
5252 if ((hw->phy.type == e1000_phy_igp_3 ||
5253 hw->phy.type == e1000_phy_bm) &&
5254 hw->mac.autoneg &&
5255 (adapter->link_speed == SPEED_10 ||
5256 adapter->link_speed == SPEED_100) &&
5257 (adapter->link_duplex == HALF_DUPLEX)) {
5258 u16 autoneg_exp;
5259
5260 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
5261
5262 if (!(autoneg_exp & EXPANSION_NWAY))
5263 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
5264 }
5265
5266 /* adjust timeout factor according to speed/duplex */
5267 adapter->tx_timeout_factor = 1;
5268 switch (adapter->link_speed) {
5269 case SPEED_10:
5270 txb2b = false;
5271 adapter->tx_timeout_factor = 16;
5272 break;
5273 case SPEED_100:
5274 txb2b = false;
5275 adapter->tx_timeout_factor = 10;
5276 break;
5277 }
5278
5279 /* workaround: re-program speed mode bit after
5280 * link-up event
5281 */
5282 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
5283 !txb2b) {
5284 u32 tarc0;
5285
5286 tarc0 = er32(TARC(0));
5287 tarc0 &= ~SPEED_MODE_BIT;
5288 ew32(TARC(0), tarc0);
5289 }
5290
5291 /* disable TSO for pcie and 10/100 speeds, to avoid
5292 * some hardware issues
5293 */
5294 if (!(adapter->flags & FLAG_TSO_FORCE)) {
5295 switch (adapter->link_speed) {
5296 case SPEED_10:
5297 case SPEED_100:
5298 e_info("10/100 speed: disabling TSO\n");
5299 netdev->features &= ~NETIF_F_TSO;
5300 netdev->features &= ~NETIF_F_TSO6;
5301 break;
5302 case SPEED_1000:
5303 netdev->features |= NETIF_F_TSO;
5304 netdev->features |= NETIF_F_TSO6;
5305 break;
5306 default:
5307 /* oops */
5308 break;
5309 }
5310 if (hw->mac.type == e1000_pch_spt) {
5311 netdev->features &= ~NETIF_F_TSO;
5312 netdev->features &= ~NETIF_F_TSO6;
5313 }
5314 }
5315
5316 /* enable transmits in the hardware, need to do this
5317 * after setting TARC(0)
5318 */
5319 tctl = er32(TCTL);
5320 tctl |= E1000_TCTL_EN;
5321 ew32(TCTL, tctl);
5322
5323 /* Perform any post-link-up configuration before
5324 * reporting link up.
5325 */
5326 if (phy->ops.cfg_on_link_up)
5327 phy->ops.cfg_on_link_up(hw);
5328
5329 netif_wake_queue(netdev);
5330 netif_carrier_on(netdev);
5331
5332 if (!test_bit(__E1000_DOWN, &adapter->state))
5333 mod_timer(&adapter->phy_info_timer,
5334 round_jiffies(jiffies + 2 * HZ));
5335 }
5336 } else {
5337 if (netif_carrier_ok(netdev)) {
5338 adapter->link_speed = 0;
5339 adapter->link_duplex = 0;
5340 /* Link status message must follow this format */
5341 netdev_info(netdev, "NIC Link is Down\n");
5342 netif_carrier_off(netdev);
5343 netif_stop_queue(netdev);
5344 if (!test_bit(__E1000_DOWN, &adapter->state))
5345 mod_timer(&adapter->phy_info_timer,
5346 round_jiffies(jiffies + 2 * HZ));
5347
5348 /* 8000ES2LAN requires a Rx packet buffer work-around
5349 * on link down event; reset the controller to flush
5350 * the Rx packet buffer.
5351 */
5352 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
5353 adapter->flags |= FLAG_RESTART_NOW;
5354 else
5355 pm_schedule_suspend(netdev->dev.parent,
5356 LINK_TIMEOUT);
5357 }
5358 }
5359
5360link_up:
5361 spin_lock(&adapter->stats64_lock);
5362 e1000e_update_stats(adapter);
5363
5364 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
5365 adapter->tpt_old = adapter->stats.tpt;
5366 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
5367 adapter->colc_old = adapter->stats.colc;
5368
5369 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
5370 adapter->gorc_old = adapter->stats.gorc;
5371 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
5372 adapter->gotc_old = adapter->stats.gotc;
5373 spin_unlock(&adapter->stats64_lock);
5374
5375 /* If the link is lost the controller stops DMA, but
5376 * if there is queued Tx work it cannot be done. So
5377 * reset the controller to flush the Tx packet buffers.
5378 */
5379 if (!netif_carrier_ok(netdev) &&
5380 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
5381 adapter->flags |= FLAG_RESTART_NOW;
5382
5383 /* If reset is necessary, do it outside of interrupt context. */
5384 if (adapter->flags & FLAG_RESTART_NOW) {
5385 schedule_work(&adapter->reset_task);
5386 /* return immediately since reset is imminent */
5387 return;
5388 }
5389
5390 e1000e_update_adaptive(&adapter->hw);
5391
5392 /* Simple mode for Interrupt Throttle Rate (ITR) */
5393 if (adapter->itr_setting == 4) {
5394 /* Symmetric Tx/Rx gets a reduced ITR=2000;
5395 * Total asymmetrical Tx or Rx gets ITR=8000;
5396 * everyone else is between 2000-8000.
5397 */
5398 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5399 u32 dif = (adapter->gotc > adapter->gorc ?
5400 adapter->gotc - adapter->gorc :
5401 adapter->gorc - adapter->gotc) / 10000;
5402 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5403
5404 e1000e_write_itr(adapter, itr);
5405 }
5406
5407 /* Cause software interrupt to ensure Rx ring is cleaned */
5408 if (adapter->msix_entries)
5409 ew32(ICS, adapter->rx_ring->ims_val);
5410 else
5411 ew32(ICS, E1000_ICS_RXDMT0);
5412
5413 /* flush pending descriptors to memory before detecting Tx hang */
5414 e1000e_flush_descriptors(adapter);
5415
5416 /* Force detection of hung controller every watchdog period */
5417 adapter->detect_tx_hung = true;
5418
5419 /* With 82571 controllers, LAA may be overwritten due to controller
5420 * reset from the other port. Set the appropriate LAA in RAR[0]
5421 */
5422 if (e1000e_get_laa_state_82571(hw))
5423 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
5424
5425 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5426 e1000e_check_82574_phy_workaround(adapter);
5427
5428 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5429 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5430 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5431 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5432 er32(RXSTMPH);
5433 adapter->rx_hwtstamp_cleared++;
5434 } else {
5435 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5436 }
5437 }
5438
5439 /* Reset the timer */
5440 if (!test_bit(__E1000_DOWN, &adapter->state))
5441 mod_timer(&adapter->watchdog_timer,
5442 round_jiffies(jiffies + 2 * HZ));
5443}
5444
5445#define E1000_TX_FLAGS_CSUM 0x00000001
5446#define E1000_TX_FLAGS_VLAN 0x00000002
5447#define E1000_TX_FLAGS_TSO 0x00000004
5448#define E1000_TX_FLAGS_IPV4 0x00000008
5449#define E1000_TX_FLAGS_NO_FCS 0x00000010
5450#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5451#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5452#define E1000_TX_FLAGS_VLAN_SHIFT 16
5453
5454static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb,
5455 __be16 protocol)
5456{
5457 struct e1000_context_desc *context_desc;
5458 struct e1000_buffer *buffer_info;
5459 unsigned int i;
5460 u32 cmd_length = 0;
5461 u16 ipcse = 0, mss;
5462 u8 ipcss, ipcso, tucss, tucso, hdr_len;
5463 int err;
5464
5465 if (!skb_is_gso(skb))
5466 return 0;
5467
5468 err = skb_cow_head(skb, 0);
5469 if (err < 0)
5470 return err;
5471
5472 hdr_len = skb_tcp_all_headers(skb);
5473 mss = skb_shinfo(skb)->gso_size;
5474 if (protocol == htons(ETH_P_IP)) {
5475 struct iphdr *iph = ip_hdr(skb);
5476 iph->tot_len = 0;
5477 iph->check = 0;
5478 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
5479 0, IPPROTO_TCP, 0);
5480 cmd_length = E1000_TXD_CMD_IP;
5481 ipcse = skb_transport_offset(skb) - 1;
5482 } else if (skb_is_gso_v6(skb)) {
5483 tcp_v6_gso_csum_prep(skb);
5484 ipcse = 0;
5485 }
5486 ipcss = skb_network_offset(skb);
5487 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5488 tucss = skb_transport_offset(skb);
5489 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
5490
5491 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
5492 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
5493
5494 i = tx_ring->next_to_use;
5495 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5496 buffer_info = &tx_ring->buffer_info[i];
5497
5498 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5499 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5500 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
5501 context_desc->upper_setup.tcp_fields.tucss = tucss;
5502 context_desc->upper_setup.tcp_fields.tucso = tucso;
5503 context_desc->upper_setup.tcp_fields.tucse = 0;
5504 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
5505 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5506 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5507
5508 buffer_info->time_stamp = jiffies;
5509 buffer_info->next_to_watch = i;
5510
5511 i++;
5512 if (i == tx_ring->count)
5513 i = 0;
5514 tx_ring->next_to_use = i;
5515
5516 return 1;
5517}
5518
5519static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb,
5520 __be16 protocol)
5521{
5522 struct e1000_adapter *adapter = tx_ring->adapter;
5523 struct e1000_context_desc *context_desc;
5524 struct e1000_buffer *buffer_info;
5525 unsigned int i;
5526 u8 css;
5527 u32 cmd_len = E1000_TXD_CMD_DEXT;
5528
5529 if (skb->ip_summed != CHECKSUM_PARTIAL)
5530 return false;
5531
5532 switch (protocol) {
5533 case cpu_to_be16(ETH_P_IP):
5534 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5535 cmd_len |= E1000_TXD_CMD_TCP;
5536 break;
5537 case cpu_to_be16(ETH_P_IPV6):
5538 /* XXX not handling all IPV6 headers */
5539 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5540 cmd_len |= E1000_TXD_CMD_TCP;
5541 break;
5542 default:
5543 if (unlikely(net_ratelimit()))
5544 e_warn("checksum_partial proto=%x!\n",
5545 be16_to_cpu(protocol));
5546 break;
5547 }
5548
5549 css = skb_checksum_start_offset(skb);
5550
5551 i = tx_ring->next_to_use;
5552 buffer_info = &tx_ring->buffer_info[i];
5553 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5554
5555 context_desc->lower_setup.ip_config = 0;
5556 context_desc->upper_setup.tcp_fields.tucss = css;
5557 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
5558 context_desc->upper_setup.tcp_fields.tucse = 0;
5559 context_desc->tcp_seg_setup.data = 0;
5560 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5561
5562 buffer_info->time_stamp = jiffies;
5563 buffer_info->next_to_watch = i;
5564
5565 i++;
5566 if (i == tx_ring->count)
5567 i = 0;
5568 tx_ring->next_to_use = i;
5569
5570 return true;
5571}
5572
5573static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5574 unsigned int first, unsigned int max_per_txd,
5575 unsigned int nr_frags)
5576{
5577 struct e1000_adapter *adapter = tx_ring->adapter;
5578 struct pci_dev *pdev = adapter->pdev;
5579 struct e1000_buffer *buffer_info;
5580 unsigned int len = skb_headlen(skb);
5581 unsigned int offset = 0, size, count = 0, i;
5582 unsigned int f, bytecount, segs;
5583
5584 i = tx_ring->next_to_use;
5585
5586 while (len) {
5587 buffer_info = &tx_ring->buffer_info[i];
5588 size = min(len, max_per_txd);
5589
5590 buffer_info->length = size;
5591 buffer_info->time_stamp = jiffies;
5592 buffer_info->next_to_watch = i;
5593 buffer_info->dma = dma_map_single(&pdev->dev,
5594 skb->data + offset,
5595 size, DMA_TO_DEVICE);
5596 buffer_info->mapped_as_page = false;
5597 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5598 goto dma_error;
5599
5600 len -= size;
5601 offset += size;
5602 count++;
5603
5604 if (len) {
5605 i++;
5606 if (i == tx_ring->count)
5607 i = 0;
5608 }
5609 }
5610
5611 for (f = 0; f < nr_frags; f++) {
5612 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
5613
5614 len = skb_frag_size(frag);
5615 offset = 0;
5616
5617 while (len) {
5618 i++;
5619 if (i == tx_ring->count)
5620 i = 0;
5621
5622 buffer_info = &tx_ring->buffer_info[i];
5623 size = min(len, max_per_txd);
5624
5625 buffer_info->length = size;
5626 buffer_info->time_stamp = jiffies;
5627 buffer_info->next_to_watch = i;
5628 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
5629 offset, size,
5630 DMA_TO_DEVICE);
5631 buffer_info->mapped_as_page = true;
5632 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5633 goto dma_error;
5634
5635 len -= size;
5636 offset += size;
5637 count++;
5638 }
5639 }
5640
5641 segs = skb_shinfo(skb)->gso_segs ? : 1;
5642 /* multiply data chunks by size of headers */
5643 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5644
5645 tx_ring->buffer_info[i].skb = skb;
5646 tx_ring->buffer_info[i].segs = segs;
5647 tx_ring->buffer_info[i].bytecount = bytecount;
5648 tx_ring->buffer_info[first].next_to_watch = i;
5649
5650 return count;
5651
5652dma_error:
5653 dev_err(&pdev->dev, "Tx DMA map failed\n");
5654 buffer_info->dma = 0;
5655 if (count)
5656 count--;
5657
5658 while (count--) {
5659 if (i == 0)
5660 i += tx_ring->count;
5661 i--;
5662 buffer_info = &tx_ring->buffer_info[i];
5663 e1000_put_txbuf(tx_ring, buffer_info, true);
5664 }
5665
5666 return 0;
5667}
5668
5669static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
5670{
5671 struct e1000_adapter *adapter = tx_ring->adapter;
5672 struct e1000_tx_desc *tx_desc = NULL;
5673 struct e1000_buffer *buffer_info;
5674 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5675 unsigned int i;
5676
5677 if (tx_flags & E1000_TX_FLAGS_TSO) {
5678 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
5679 E1000_TXD_CMD_TSE;
5680 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5681
5682 if (tx_flags & E1000_TX_FLAGS_IPV4)
5683 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5684 }
5685
5686 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5687 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5688 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5689 }
5690
5691 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5692 txd_lower |= E1000_TXD_CMD_VLE;
5693 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5694 }
5695
5696 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5697 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5698
5699 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5700 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5701 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5702 }
5703
5704 i = tx_ring->next_to_use;
5705
5706 do {
5707 buffer_info = &tx_ring->buffer_info[i];
5708 tx_desc = E1000_TX_DESC(*tx_ring, i);
5709 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
5710 tx_desc->lower.data = cpu_to_le32(txd_lower |
5711 buffer_info->length);
5712 tx_desc->upper.data = cpu_to_le32(txd_upper);
5713
5714 i++;
5715 if (i == tx_ring->count)
5716 i = 0;
5717 } while (--count > 0);
5718
5719 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5720
5721 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5722 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5723 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5724
5725 /* Force memory writes to complete before letting h/w
5726 * know there are new descriptors to fetch. (Only
5727 * applicable for weak-ordered memory model archs,
5728 * such as IA-64).
5729 */
5730 wmb();
5731
5732 tx_ring->next_to_use = i;
5733}
5734
5735#define MINIMUM_DHCP_PACKET_SIZE 282
5736static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5737 struct sk_buff *skb)
5738{
5739 struct e1000_hw *hw = &adapter->hw;
5740 u16 length, offset;
5741
5742 if (skb_vlan_tag_present(skb) &&
5743 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5744 (adapter->hw.mng_cookie.status &
5745 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5746 return 0;
5747
5748 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5749 return 0;
5750
5751 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
5752 return 0;
5753
5754 {
5755 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
5756 struct udphdr *udp;
5757
5758 if (ip->protocol != IPPROTO_UDP)
5759 return 0;
5760
5761 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5762 if (ntohs(udp->dest) != 67)
5763 return 0;
5764
5765 offset = (u8 *)udp + 8 - skb->data;
5766 length = skb->len - offset;
5767 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5768 }
5769
5770 return 0;
5771}
5772
5773static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5774{
5775 struct e1000_adapter *adapter = tx_ring->adapter;
5776
5777 netif_stop_queue(adapter->netdev);
5778 /* Herbert's original patch had:
5779 * smp_mb__after_netif_stop_queue();
5780 * but since that doesn't exist yet, just open code it.
5781 */
5782 smp_mb();
5783
5784 /* We need to check again in a case another CPU has just
5785 * made room available.
5786 */
5787 if (e1000_desc_unused(tx_ring) < size)
5788 return -EBUSY;
5789
5790 /* A reprieve! */
5791 netif_start_queue(adapter->netdev);
5792 ++adapter->restart_queue;
5793 return 0;
5794}
5795
5796static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5797{
5798 BUG_ON(size > tx_ring->count);
5799
5800 if (e1000_desc_unused(tx_ring) >= size)
5801 return 0;
5802 return __e1000_maybe_stop_tx(tx_ring, size);
5803}
5804
5805static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5806 struct net_device *netdev)
5807{
5808 struct e1000_adapter *adapter = netdev_priv(netdev);
5809 struct e1000_ring *tx_ring = adapter->tx_ring;
5810 unsigned int first;
5811 unsigned int tx_flags = 0;
5812 unsigned int len = skb_headlen(skb);
5813 unsigned int nr_frags;
5814 unsigned int mss;
5815 int count = 0;
5816 int tso;
5817 unsigned int f;
5818 __be16 protocol = vlan_get_protocol(skb);
5819
5820 if (test_bit(__E1000_DOWN, &adapter->state)) {
5821 dev_kfree_skb_any(skb);
5822 return NETDEV_TX_OK;
5823 }
5824
5825 if (skb->len <= 0) {
5826 dev_kfree_skb_any(skb);
5827 return NETDEV_TX_OK;
5828 }
5829
5830 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5831 * pad skb in order to meet this minimum size requirement
5832 */
5833 if (skb_put_padto(skb, 17))
5834 return NETDEV_TX_OK;
5835
5836 mss = skb_shinfo(skb)->gso_size;
5837 if (mss) {
5838 u8 hdr_len;
5839
5840 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5841 * points to just header, pull a few bytes of payload from
5842 * frags into skb->data
5843 */
5844 hdr_len = skb_tcp_all_headers(skb);
5845 /* we do this workaround for ES2LAN, but it is un-necessary,
5846 * avoiding it could save a lot of cycles
5847 */
5848 if (skb->data_len && (hdr_len == len)) {
5849 unsigned int pull_size;
5850
5851 pull_size = min_t(unsigned int, 4, skb->data_len);
5852 if (!__pskb_pull_tail(skb, pull_size)) {
5853 e_err("__pskb_pull_tail failed.\n");
5854 dev_kfree_skb_any(skb);
5855 return NETDEV_TX_OK;
5856 }
5857 len = skb_headlen(skb);
5858 }
5859 }
5860
5861 /* reserve a descriptor for the offload context */
5862 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5863 count++;
5864 count++;
5865
5866 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
5867
5868 nr_frags = skb_shinfo(skb)->nr_frags;
5869 for (f = 0; f < nr_frags; f++)
5870 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5871 adapter->tx_fifo_limit);
5872
5873 if (adapter->hw.mac.tx_pkt_filtering)
5874 e1000_transfer_dhcp_info(adapter, skb);
5875
5876 /* need: count + 2 desc gap to keep tail from touching
5877 * head, otherwise try next time
5878 */
5879 if (e1000_maybe_stop_tx(tx_ring, count + 2))
5880 return NETDEV_TX_BUSY;
5881
5882 if (skb_vlan_tag_present(skb)) {
5883 tx_flags |= E1000_TX_FLAGS_VLAN;
5884 tx_flags |= (skb_vlan_tag_get(skb) <<
5885 E1000_TX_FLAGS_VLAN_SHIFT);
5886 }
5887
5888 first = tx_ring->next_to_use;
5889
5890 tso = e1000_tso(tx_ring, skb, protocol);
5891 if (tso < 0) {
5892 dev_kfree_skb_any(skb);
5893 return NETDEV_TX_OK;
5894 }
5895
5896 if (tso)
5897 tx_flags |= E1000_TX_FLAGS_TSO;
5898 else if (e1000_tx_csum(tx_ring, skb, protocol))
5899 tx_flags |= E1000_TX_FLAGS_CSUM;
5900
5901 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5902 * 82571 hardware supports TSO capabilities for IPv6 as well...
5903 * no longer assume, we must.
5904 */
5905 if (protocol == htons(ETH_P_IP))
5906 tx_flags |= E1000_TX_FLAGS_IPV4;
5907
5908 if (unlikely(skb->no_fcs))
5909 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5910
5911 /* if count is 0 then mapping error has occurred */
5912 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5913 nr_frags);
5914 if (count) {
5915 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5916 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) {
5917 if (!adapter->tx_hwtstamp_skb) {
5918 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5919 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5920 adapter->tx_hwtstamp_skb = skb_get(skb);
5921 adapter->tx_hwtstamp_start = jiffies;
5922 schedule_work(&adapter->tx_hwtstamp_work);
5923 } else {
5924 adapter->tx_hwtstamp_skipped++;
5925 }
5926 }
5927
5928 skb_tx_timestamp(skb);
5929
5930 netdev_sent_queue(netdev, skb->len);
5931 e1000_tx_queue(tx_ring, tx_flags, count);
5932 /* Make sure there is space in the ring for the next send. */
5933 e1000_maybe_stop_tx(tx_ring,
5934 ((MAX_SKB_FRAGS + 1) *
5935 DIV_ROUND_UP(PAGE_SIZE,
5936 adapter->tx_fifo_limit) + 4));
5937
5938 if (!netdev_xmit_more() ||
5939 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) {
5940 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
5941 e1000e_update_tdt_wa(tx_ring,
5942 tx_ring->next_to_use);
5943 else
5944 writel(tx_ring->next_to_use, tx_ring->tail);
5945 }
5946 } else {
5947 dev_kfree_skb_any(skb);
5948 tx_ring->buffer_info[first].time_stamp = 0;
5949 tx_ring->next_to_use = first;
5950 }
5951
5952 return NETDEV_TX_OK;
5953}
5954
5955/**
5956 * e1000_tx_timeout - Respond to a Tx Hang
5957 * @netdev: network interface device structure
5958 * @txqueue: index of the hung queue (unused)
5959 **/
5960static void e1000_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
5961{
5962 struct e1000_adapter *adapter = netdev_priv(netdev);
5963
5964 /* Do the reset outside of interrupt context */
5965 adapter->tx_timeout_count++;
5966 schedule_work(&adapter->reset_task);
5967}
5968
5969static void e1000_reset_task(struct work_struct *work)
5970{
5971 struct e1000_adapter *adapter;
5972 adapter = container_of(work, struct e1000_adapter, reset_task);
5973
5974 rtnl_lock();
5975 /* don't run the task if already down */
5976 if (test_bit(__E1000_DOWN, &adapter->state)) {
5977 rtnl_unlock();
5978 return;
5979 }
5980
5981 if (!(adapter->flags & FLAG_RESTART_NOW)) {
5982 e1000e_dump(adapter);
5983 e_err("Reset adapter unexpectedly\n");
5984 }
5985 e1000e_reinit_locked(adapter);
5986 rtnl_unlock();
5987}
5988
5989/**
5990 * e1000e_get_stats64 - Get System Network Statistics
5991 * @netdev: network interface device structure
5992 * @stats: rtnl_link_stats64 pointer
5993 *
5994 * Returns the address of the device statistics structure.
5995 **/
5996void e1000e_get_stats64(struct net_device *netdev,
5997 struct rtnl_link_stats64 *stats)
5998{
5999 struct e1000_adapter *adapter = netdev_priv(netdev);
6000
6001 spin_lock(&adapter->stats64_lock);
6002 e1000e_update_stats(adapter);
6003 /* Fill out the OS statistics structure */
6004 stats->rx_bytes = adapter->stats.gorc;
6005 stats->rx_packets = adapter->stats.gprc;
6006 stats->tx_bytes = adapter->stats.gotc;
6007 stats->tx_packets = adapter->stats.gptc;
6008 stats->multicast = adapter->stats.mprc;
6009 stats->collisions = adapter->stats.colc;
6010
6011 /* Rx Errors */
6012
6013 /* RLEC on some newer hardware can be incorrect so build
6014 * our own version based on RUC and ROC
6015 */
6016 stats->rx_errors = adapter->stats.rxerrc +
6017 adapter->stats.crcerrs + adapter->stats.algnerrc +
6018 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
6019 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
6020 stats->rx_crc_errors = adapter->stats.crcerrs;
6021 stats->rx_frame_errors = adapter->stats.algnerrc;
6022 stats->rx_missed_errors = adapter->stats.mpc;
6023
6024 /* Tx Errors */
6025 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
6026 stats->tx_aborted_errors = adapter->stats.ecol;
6027 stats->tx_window_errors = adapter->stats.latecol;
6028 stats->tx_carrier_errors = adapter->stats.tncrs;
6029
6030 /* Tx Dropped needs to be maintained elsewhere */
6031
6032 spin_unlock(&adapter->stats64_lock);
6033}
6034
6035/**
6036 * e1000_change_mtu - Change the Maximum Transfer Unit
6037 * @netdev: network interface device structure
6038 * @new_mtu: new value for maximum frame size
6039 *
6040 * Returns 0 on success, negative on failure
6041 **/
6042static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
6043{
6044 struct e1000_adapter *adapter = netdev_priv(netdev);
6045 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6046
6047 /* Jumbo frame support */
6048 if ((new_mtu > ETH_DATA_LEN) &&
6049 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
6050 e_err("Jumbo Frames not supported.\n");
6051 return -EINVAL;
6052 }
6053
6054 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6055 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
6056 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
6057 (new_mtu > ETH_DATA_LEN)) {
6058 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
6059 return -EINVAL;
6060 }
6061
6062 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
6063 usleep_range(1000, 1100);
6064 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
6065 adapter->max_frame_size = max_frame;
6066 netdev_dbg(netdev, "changing MTU from %d to %d\n",
6067 netdev->mtu, new_mtu);
6068 netdev->mtu = new_mtu;
6069
6070 pm_runtime_get_sync(netdev->dev.parent);
6071
6072 if (netif_running(netdev))
6073 e1000e_down(adapter, true);
6074
6075 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
6076 * means we reserve 2 more, this pushes us to allocate from the next
6077 * larger slab size.
6078 * i.e. RXBUFFER_2048 --> size-4096 slab
6079 * However with the new *_jumbo_rx* routines, jumbo receives will use
6080 * fragmented skbs
6081 */
6082
6083 if (max_frame <= 2048)
6084 adapter->rx_buffer_len = 2048;
6085 else
6086 adapter->rx_buffer_len = 4096;
6087
6088 /* adjust allocation if LPE protects us, and we aren't using SBP */
6089 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN))
6090 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
6091
6092 if (netif_running(netdev))
6093 e1000e_up(adapter);
6094 else
6095 e1000e_reset(adapter);
6096
6097 pm_runtime_put_sync(netdev->dev.parent);
6098
6099 clear_bit(__E1000_RESETTING, &adapter->state);
6100
6101 return 0;
6102}
6103
6104static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
6105 int cmd)
6106{
6107 struct e1000_adapter *adapter = netdev_priv(netdev);
6108 struct mii_ioctl_data *data = if_mii(ifr);
6109
6110 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6111 return -EOPNOTSUPP;
6112
6113 switch (cmd) {
6114 case SIOCGMIIPHY:
6115 data->phy_id = adapter->hw.phy.addr;
6116 break;
6117 case SIOCGMIIREG:
6118 e1000_phy_read_status(adapter);
6119
6120 switch (data->reg_num & 0x1F) {
6121 case MII_BMCR:
6122 data->val_out = adapter->phy_regs.bmcr;
6123 break;
6124 case MII_BMSR:
6125 data->val_out = adapter->phy_regs.bmsr;
6126 break;
6127 case MII_PHYSID1:
6128 data->val_out = (adapter->hw.phy.id >> 16);
6129 break;
6130 case MII_PHYSID2:
6131 data->val_out = (adapter->hw.phy.id & 0xFFFF);
6132 break;
6133 case MII_ADVERTISE:
6134 data->val_out = adapter->phy_regs.advertise;
6135 break;
6136 case MII_LPA:
6137 data->val_out = adapter->phy_regs.lpa;
6138 break;
6139 case MII_EXPANSION:
6140 data->val_out = adapter->phy_regs.expansion;
6141 break;
6142 case MII_CTRL1000:
6143 data->val_out = adapter->phy_regs.ctrl1000;
6144 break;
6145 case MII_STAT1000:
6146 data->val_out = adapter->phy_regs.stat1000;
6147 break;
6148 case MII_ESTATUS:
6149 data->val_out = adapter->phy_regs.estatus;
6150 break;
6151 default:
6152 return -EIO;
6153 }
6154 break;
6155 case SIOCSMIIREG:
6156 default:
6157 return -EOPNOTSUPP;
6158 }
6159 return 0;
6160}
6161
6162/**
6163 * e1000e_hwtstamp_set - control hardware time stamping
6164 * @netdev: network interface device structure
6165 * @ifr: interface request
6166 *
6167 * Outgoing time stamping can be enabled and disabled. Play nice and
6168 * disable it when requested, although it shouldn't cause any overhead
6169 * when no packet needs it. At most one packet in the queue may be
6170 * marked for time stamping, otherwise it would be impossible to tell
6171 * for sure to which packet the hardware time stamp belongs.
6172 *
6173 * Incoming time stamping has to be configured via the hardware filters.
6174 * Not all combinations are supported, in particular event type has to be
6175 * specified. Matching the kind of event packet is not supported, with the
6176 * exception of "all V2 events regardless of level 2 or 4".
6177 **/
6178static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
6179{
6180 struct e1000_adapter *adapter = netdev_priv(netdev);
6181 struct hwtstamp_config config;
6182 int ret_val;
6183
6184 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
6185 return -EFAULT;
6186
6187 ret_val = e1000e_config_hwtstamp(adapter, &config);
6188 if (ret_val)
6189 return ret_val;
6190
6191 switch (config.rx_filter) {
6192 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6193 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6194 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6195 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6196 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6197 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6198 /* With V2 type filters which specify a Sync or Delay Request,
6199 * Path Delay Request/Response messages are also time stamped
6200 * by hardware so notify the caller the requested packets plus
6201 * some others are time stamped.
6202 */
6203 config.rx_filter = HWTSTAMP_FILTER_SOME;
6204 break;
6205 default:
6206 break;
6207 }
6208
6209 return copy_to_user(ifr->ifr_data, &config,
6210 sizeof(config)) ? -EFAULT : 0;
6211}
6212
6213static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
6214{
6215 struct e1000_adapter *adapter = netdev_priv(netdev);
6216
6217 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config,
6218 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0;
6219}
6220
6221static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6222{
6223 switch (cmd) {
6224 case SIOCGMIIPHY:
6225 case SIOCGMIIREG:
6226 case SIOCSMIIREG:
6227 return e1000_mii_ioctl(netdev, ifr, cmd);
6228 case SIOCSHWTSTAMP:
6229 return e1000e_hwtstamp_set(netdev, ifr);
6230 case SIOCGHWTSTAMP:
6231 return e1000e_hwtstamp_get(netdev, ifr);
6232 default:
6233 return -EOPNOTSUPP;
6234 }
6235}
6236
6237static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
6238{
6239 struct e1000_hw *hw = &adapter->hw;
6240 u32 i, mac_reg, wuc;
6241 u16 phy_reg, wuc_enable;
6242 int retval;
6243
6244 /* copy MAC RARs to PHY RARs */
6245 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
6246
6247 retval = hw->phy.ops.acquire(hw);
6248 if (retval) {
6249 e_err("Could not acquire PHY\n");
6250 return retval;
6251 }
6252
6253 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
6254 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6255 if (retval)
6256 goto release;
6257
6258 /* copy MAC MTA to PHY MTA - only needed for pchlan */
6259 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
6260 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
6261 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
6262 (u16)(mac_reg & 0xFFFF));
6263 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
6264 (u16)((mac_reg >> 16) & 0xFFFF));
6265 }
6266
6267 /* configure PHY Rx Control register */
6268 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
6269 mac_reg = er32(RCTL);
6270 if (mac_reg & E1000_RCTL_UPE)
6271 phy_reg |= BM_RCTL_UPE;
6272 if (mac_reg & E1000_RCTL_MPE)
6273 phy_reg |= BM_RCTL_MPE;
6274 phy_reg &= ~(BM_RCTL_MO_MASK);
6275 if (mac_reg & E1000_RCTL_MO_3)
6276 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
6277 << BM_RCTL_MO_SHIFT);
6278 if (mac_reg & E1000_RCTL_BAM)
6279 phy_reg |= BM_RCTL_BAM;
6280 if (mac_reg & E1000_RCTL_PMCF)
6281 phy_reg |= BM_RCTL_PMCF;
6282 mac_reg = er32(CTRL);
6283 if (mac_reg & E1000_CTRL_RFCE)
6284 phy_reg |= BM_RCTL_RFCE;
6285 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
6286
6287 wuc = E1000_WUC_PME_EN;
6288 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
6289 wuc |= E1000_WUC_APME;
6290
6291 /* enable PHY wakeup in MAC register */
6292 ew32(WUFC, wufc);
6293 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
6294 E1000_WUC_PME_STATUS | wuc));
6295
6296 /* configure and enable PHY wakeup in PHY registers */
6297 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
6298 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
6299
6300 /* activate PHY wakeup */
6301 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
6302 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6303 if (retval)
6304 e_err("Could not set PHY Host Wakeup bit\n");
6305release:
6306 hw->phy.ops.release(hw);
6307
6308 return retval;
6309}
6310
6311static void e1000e_flush_lpic(struct pci_dev *pdev)
6312{
6313 struct net_device *netdev = pci_get_drvdata(pdev);
6314 struct e1000_adapter *adapter = netdev_priv(netdev);
6315 struct e1000_hw *hw = &adapter->hw;
6316 u32 ret_val;
6317
6318 pm_runtime_get_sync(netdev->dev.parent);
6319
6320 ret_val = hw->phy.ops.acquire(hw);
6321 if (ret_val)
6322 goto fl_out;
6323
6324 pr_info("EEE TX LPI TIMER: %08X\n",
6325 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT);
6326
6327 hw->phy.ops.release(hw);
6328
6329fl_out:
6330 pm_runtime_put_sync(netdev->dev.parent);
6331}
6332
6333/* S0ix implementation */
6334static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter)
6335{
6336 struct e1000_hw *hw = &adapter->hw;
6337 u32 mac_data;
6338 u16 phy_data;
6339
6340 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID &&
6341 hw->mac.type >= e1000_pch_adp) {
6342 /* Request ME configure the device for S0ix */
6343 mac_data = er32(H2ME);
6344 mac_data |= E1000_H2ME_START_DPG;
6345 mac_data &= ~E1000_H2ME_EXIT_DPG;
6346 trace_e1000e_trace_mac_register(mac_data);
6347 ew32(H2ME, mac_data);
6348 } else {
6349 /* Request driver configure the device to S0ix */
6350 /* Disable the periodic inband message,
6351 * don't request PCIe clock in K1 page770_17[10:9] = 10b
6352 */
6353 e1e_rphy(hw, HV_PM_CTRL, &phy_data);
6354 phy_data &= ~HV_PM_CTRL_K1_CLK_REQ;
6355 phy_data |= BIT(10);
6356 e1e_wphy(hw, HV_PM_CTRL, phy_data);
6357
6358 /* Make sure we don't exit K1 every time a new packet arrives
6359 * 772_29[5] = 1 CS_Mode_Stay_In_K1
6360 */
6361 e1e_rphy(hw, I217_CGFREG, &phy_data);
6362 phy_data |= BIT(5);
6363 e1e_wphy(hw, I217_CGFREG, phy_data);
6364
6365 /* Change the MAC/PHY interface to SMBus
6366 * Force the SMBus in PHY page769_23[0] = 1
6367 * Force the SMBus in MAC CTRL_EXT[11] = 1
6368 */
6369 e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
6370 phy_data |= CV_SMB_CTRL_FORCE_SMBUS;
6371 e1e_wphy(hw, CV_SMB_CTRL, phy_data);
6372 mac_data = er32(CTRL_EXT);
6373 mac_data |= E1000_CTRL_EXT_FORCE_SMBUS;
6374 ew32(CTRL_EXT, mac_data);
6375
6376 /* DFT control: PHY bit: page769_20[0] = 1
6377 * page769_20[7] - PHY PLL stop
6378 * page769_20[8] - PHY go to the electrical idle
6379 * page769_20[9] - PHY serdes disable
6380 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1
6381 */
6382 e1e_rphy(hw, I82579_DFT_CTRL, &phy_data);
6383 phy_data |= BIT(0);
6384 phy_data |= BIT(7);
6385 phy_data |= BIT(8);
6386 phy_data |= BIT(9);
6387 e1e_wphy(hw, I82579_DFT_CTRL, phy_data);
6388
6389 mac_data = er32(EXTCNF_CTRL);
6390 mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
6391 ew32(EXTCNF_CTRL, mac_data);
6392
6393 /* Enable the Dynamic Power Gating in the MAC */
6394 mac_data = er32(FEXTNVM7);
6395 mac_data |= BIT(22);
6396 ew32(FEXTNVM7, mac_data);
6397
6398 /* Disable disconnected cable conditioning for Power Gating */
6399 mac_data = er32(DPGFR);
6400 mac_data |= BIT(2);
6401 ew32(DPGFR, mac_data);
6402
6403 /* Don't wake from dynamic Power Gating with clock request */
6404 mac_data = er32(FEXTNVM12);
6405 mac_data |= BIT(12);
6406 ew32(FEXTNVM12, mac_data);
6407
6408 /* Ungate PGCB clock */
6409 mac_data = er32(FEXTNVM9);
6410 mac_data &= ~BIT(28);
6411 ew32(FEXTNVM9, mac_data);
6412
6413 /* Enable K1 off to enable mPHY Power Gating */
6414 mac_data = er32(FEXTNVM6);
6415 mac_data |= BIT(31);
6416 ew32(FEXTNVM6, mac_data);
6417
6418 /* Enable mPHY power gating for any link and speed */
6419 mac_data = er32(FEXTNVM8);
6420 mac_data |= BIT(9);
6421 ew32(FEXTNVM8, mac_data);
6422
6423 /* Enable the Dynamic Clock Gating in the DMA and MAC */
6424 mac_data = er32(CTRL_EXT);
6425 mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN;
6426 ew32(CTRL_EXT, mac_data);
6427
6428 /* No MAC DPG gating SLP_S0 in modern standby
6429 * Switch the logic of the lanphypc to use PMC counter
6430 */
6431 mac_data = er32(FEXTNVM5);
6432 mac_data |= BIT(7);
6433 ew32(FEXTNVM5, mac_data);
6434 }
6435
6436 /* Disable the time synchronization clock */
6437 mac_data = er32(FEXTNVM7);
6438 mac_data |= BIT(31);
6439 mac_data &= ~BIT(0);
6440 ew32(FEXTNVM7, mac_data);
6441
6442 /* Dynamic Power Gating Enable */
6443 mac_data = er32(CTRL_EXT);
6444 mac_data |= BIT(3);
6445 ew32(CTRL_EXT, mac_data);
6446
6447 /* Check MAC Tx/Rx packet buffer pointers.
6448 * Reset MAC Tx/Rx packet buffer pointers to suppress any
6449 * pending traffic indication that would prevent power gating.
6450 */
6451 mac_data = er32(TDFH);
6452 if (mac_data)
6453 ew32(TDFH, 0);
6454 mac_data = er32(TDFT);
6455 if (mac_data)
6456 ew32(TDFT, 0);
6457 mac_data = er32(TDFHS);
6458 if (mac_data)
6459 ew32(TDFHS, 0);
6460 mac_data = er32(TDFTS);
6461 if (mac_data)
6462 ew32(TDFTS, 0);
6463 mac_data = er32(TDFPC);
6464 if (mac_data)
6465 ew32(TDFPC, 0);
6466 mac_data = er32(RDFH);
6467 if (mac_data)
6468 ew32(RDFH, 0);
6469 mac_data = er32(RDFT);
6470 if (mac_data)
6471 ew32(RDFT, 0);
6472 mac_data = er32(RDFHS);
6473 if (mac_data)
6474 ew32(RDFHS, 0);
6475 mac_data = er32(RDFTS);
6476 if (mac_data)
6477 ew32(RDFTS, 0);
6478 mac_data = er32(RDFPC);
6479 if (mac_data)
6480 ew32(RDFPC, 0);
6481}
6482
6483static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter)
6484{
6485 struct e1000_hw *hw = &adapter->hw;
6486 bool firmware_bug = false;
6487 u32 mac_data;
6488 u16 phy_data;
6489 u32 i = 0;
6490
6491 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID &&
6492 hw->mac.type >= e1000_pch_adp) {
6493 /* Keep the GPT clock enabled for CSME */
6494 mac_data = er32(FEXTNVM);
6495 mac_data |= BIT(3);
6496 ew32(FEXTNVM, mac_data);
6497 /* Request ME unconfigure the device from S0ix */
6498 mac_data = er32(H2ME);
6499 mac_data &= ~E1000_H2ME_START_DPG;
6500 mac_data |= E1000_H2ME_EXIT_DPG;
6501 trace_e1000e_trace_mac_register(mac_data);
6502 ew32(H2ME, mac_data);
6503
6504 /* Poll up to 2.5 seconds for ME to unconfigure DPG.
6505 * If this takes more than 1 second, show a warning indicating a
6506 * firmware bug
6507 */
6508 while (!(er32(EXFWSM) & E1000_EXFWSM_DPG_EXIT_DONE)) {
6509 if (i > 100 && !firmware_bug)
6510 firmware_bug = true;
6511
6512 if (i++ == 250) {
6513 e_dbg("Timeout (firmware bug): %d msec\n",
6514 i * 10);
6515 break;
6516 }
6517
6518 usleep_range(10000, 11000);
6519 }
6520 if (firmware_bug)
6521 e_warn("DPG_EXIT_DONE took %d msec. This is a firmware bug\n",
6522 i * 10);
6523 else
6524 e_dbg("DPG_EXIT_DONE cleared after %d msec\n", i * 10);
6525 } else {
6526 /* Request driver unconfigure the device from S0ix */
6527
6528 /* Disable the Dynamic Power Gating in the MAC */
6529 mac_data = er32(FEXTNVM7);
6530 mac_data &= 0xFFBFFFFF;
6531 ew32(FEXTNVM7, mac_data);
6532
6533 /* Disable mPHY power gating for any link and speed */
6534 mac_data = er32(FEXTNVM8);
6535 mac_data &= ~BIT(9);
6536 ew32(FEXTNVM8, mac_data);
6537
6538 /* Disable K1 off */
6539 mac_data = er32(FEXTNVM6);
6540 mac_data &= ~BIT(31);
6541 ew32(FEXTNVM6, mac_data);
6542
6543 /* Disable Ungate PGCB clock */
6544 mac_data = er32(FEXTNVM9);
6545 mac_data |= BIT(28);
6546 ew32(FEXTNVM9, mac_data);
6547
6548 /* Cancel not waking from dynamic
6549 * Power Gating with clock request
6550 */
6551 mac_data = er32(FEXTNVM12);
6552 mac_data &= ~BIT(12);
6553 ew32(FEXTNVM12, mac_data);
6554
6555 /* Cancel disable disconnected cable conditioning
6556 * for Power Gating
6557 */
6558 mac_data = er32(DPGFR);
6559 mac_data &= ~BIT(2);
6560 ew32(DPGFR, mac_data);
6561
6562 /* Disable the Dynamic Clock Gating in the DMA and MAC */
6563 mac_data = er32(CTRL_EXT);
6564 mac_data &= 0xFFF7FFFF;
6565 ew32(CTRL_EXT, mac_data);
6566
6567 /* Revert the lanphypc logic to use the internal Gbe counter
6568 * and not the PMC counter
6569 */
6570 mac_data = er32(FEXTNVM5);
6571 mac_data &= 0xFFFFFF7F;
6572 ew32(FEXTNVM5, mac_data);
6573
6574 /* Enable the periodic inband message,
6575 * Request PCIe clock in K1 page770_17[10:9] =01b
6576 */
6577 e1e_rphy(hw, HV_PM_CTRL, &phy_data);
6578 phy_data &= 0xFBFF;
6579 phy_data |= HV_PM_CTRL_K1_CLK_REQ;
6580 e1e_wphy(hw, HV_PM_CTRL, phy_data);
6581
6582 /* Return back configuration
6583 * 772_29[5] = 0 CS_Mode_Stay_In_K1
6584 */
6585 e1e_rphy(hw, I217_CGFREG, &phy_data);
6586 phy_data &= 0xFFDF;
6587 e1e_wphy(hw, I217_CGFREG, phy_data);
6588
6589 /* Change the MAC/PHY interface to Kumeran
6590 * Unforce the SMBus in PHY page769_23[0] = 0
6591 * Unforce the SMBus in MAC CTRL_EXT[11] = 0
6592 */
6593 e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
6594 phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS;
6595 e1e_wphy(hw, CV_SMB_CTRL, phy_data);
6596 mac_data = er32(CTRL_EXT);
6597 mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS;
6598 ew32(CTRL_EXT, mac_data);
6599 }
6600
6601 /* Disable Dynamic Power Gating */
6602 mac_data = er32(CTRL_EXT);
6603 mac_data &= 0xFFFFFFF7;
6604 ew32(CTRL_EXT, mac_data);
6605
6606 /* Enable the time synchronization clock */
6607 mac_data = er32(FEXTNVM7);
6608 mac_data &= ~BIT(31);
6609 mac_data |= BIT(0);
6610 ew32(FEXTNVM7, mac_data);
6611}
6612
6613static int e1000e_pm_freeze(struct device *dev)
6614{
6615 struct net_device *netdev = dev_get_drvdata(dev);
6616 struct e1000_adapter *adapter = netdev_priv(netdev);
6617 bool present;
6618
6619 rtnl_lock();
6620
6621 present = netif_device_present(netdev);
6622 netif_device_detach(netdev);
6623
6624 if (present && netif_running(netdev)) {
6625 int count = E1000_CHECK_RESET_COUNT;
6626
6627 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6628 usleep_range(10000, 11000);
6629
6630 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6631
6632 /* Quiesce the device without resetting the hardware */
6633 e1000e_down(adapter, false);
6634 e1000_free_irq(adapter);
6635 }
6636 rtnl_unlock();
6637
6638 e1000e_reset_interrupt_capability(adapter);
6639
6640 /* Allow time for pending master requests to run */
6641 e1000e_disable_pcie_master(&adapter->hw);
6642
6643 return 0;
6644}
6645
6646static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
6647{
6648 struct net_device *netdev = pci_get_drvdata(pdev);
6649 struct e1000_adapter *adapter = netdev_priv(netdev);
6650 struct e1000_hw *hw = &adapter->hw;
6651 u32 ctrl, ctrl_ext, rctl, status, wufc;
6652 int retval = 0;
6653
6654 /* Runtime suspend should only enable wakeup for link changes */
6655 if (runtime)
6656 wufc = E1000_WUFC_LNKC;
6657 else if (device_may_wakeup(&pdev->dev))
6658 wufc = adapter->wol;
6659 else
6660 wufc = 0;
6661
6662 status = er32(STATUS);
6663 if (status & E1000_STATUS_LU)
6664 wufc &= ~E1000_WUFC_LNKC;
6665
6666 if (wufc) {
6667 e1000_setup_rctl(adapter);
6668 e1000e_set_rx_mode(netdev);
6669
6670 /* turn on all-multi mode if wake on multicast is enabled */
6671 if (wufc & E1000_WUFC_MC) {
6672 rctl = er32(RCTL);
6673 rctl |= E1000_RCTL_MPE;
6674 ew32(RCTL, rctl);
6675 }
6676
6677 ctrl = er32(CTRL);
6678 ctrl |= E1000_CTRL_ADVD3WUC;
6679 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
6680 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
6681 ew32(CTRL, ctrl);
6682
6683 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
6684 adapter->hw.phy.media_type ==
6685 e1000_media_type_internal_serdes) {
6686 /* keep the laser running in D3 */
6687 ctrl_ext = er32(CTRL_EXT);
6688 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
6689 ew32(CTRL_EXT, ctrl_ext);
6690 }
6691
6692 if (!runtime)
6693 e1000e_power_up_phy(adapter);
6694
6695 if (adapter->flags & FLAG_IS_ICH)
6696 e1000_suspend_workarounds_ich8lan(&adapter->hw);
6697
6698 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6699 /* enable wakeup by the PHY */
6700 retval = e1000_init_phy_wakeup(adapter, wufc);
6701 if (retval)
6702 return retval;
6703 } else {
6704 /* enable wakeup by the MAC */
6705 ew32(WUFC, wufc);
6706 ew32(WUC, E1000_WUC_PME_EN);
6707 }
6708 } else {
6709 ew32(WUC, 0);
6710 ew32(WUFC, 0);
6711
6712 e1000_power_down_phy(adapter);
6713 }
6714
6715 if (adapter->hw.phy.type == e1000_phy_igp_3) {
6716 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
6717 } else if (hw->mac.type >= e1000_pch_lpt) {
6718 if (wufc && !(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC)))
6719 /* ULP does not support wake from unicast, multicast
6720 * or broadcast.
6721 */
6722 retval = e1000_enable_ulp_lpt_lp(hw, !runtime);
6723
6724 if (retval)
6725 return retval;
6726 }
6727
6728 /* Ensure that the appropriate bits are set in LPI_CTRL
6729 * for EEE in Sx
6730 */
6731 if ((hw->phy.type >= e1000_phy_i217) &&
6732 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) {
6733 u16 lpi_ctrl = 0;
6734
6735 retval = hw->phy.ops.acquire(hw);
6736 if (!retval) {
6737 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL,
6738 &lpi_ctrl);
6739 if (!retval) {
6740 if (adapter->eee_advert &
6741 hw->dev_spec.ich8lan.eee_lp_ability &
6742 I82579_EEE_100_SUPPORTED)
6743 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
6744 if (adapter->eee_advert &
6745 hw->dev_spec.ich8lan.eee_lp_ability &
6746 I82579_EEE_1000_SUPPORTED)
6747 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
6748
6749 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL,
6750 lpi_ctrl);
6751 }
6752 }
6753 hw->phy.ops.release(hw);
6754 }
6755
6756 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6757 * would have already happened in close and is redundant.
6758 */
6759 e1000e_release_hw_control(adapter);
6760
6761 pci_clear_master(pdev);
6762
6763 /* The pci-e switch on some quad port adapters will report a
6764 * correctable error when the MAC transitions from D0 to D3. To
6765 * prevent this we need to mask off the correctable errors on the
6766 * downstream port of the pci-e switch.
6767 *
6768 * We don't have the associated upstream bridge while assigning
6769 * the PCI device into guest. For example, the KVM on power is
6770 * one of the cases.
6771 */
6772 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6773 struct pci_dev *us_dev = pdev->bus->self;
6774 u16 devctl;
6775
6776 if (!us_dev)
6777 return 0;
6778
6779 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6780 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6781 (devctl & ~PCI_EXP_DEVCTL_CERE));
6782
6783 pci_save_state(pdev);
6784 pci_prepare_to_sleep(pdev);
6785
6786 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
6787 }
6788
6789 return 0;
6790}
6791
6792/**
6793 * __e1000e_disable_aspm - Disable ASPM states
6794 * @pdev: pointer to PCI device struct
6795 * @state: bit-mask of ASPM states to disable
6796 * @locked: indication if this context holds pci_bus_sem locked.
6797 *
6798 * Some devices *must* have certain ASPM states disabled per hardware errata.
6799 **/
6800static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked)
6801{
6802 struct pci_dev *parent = pdev->bus->self;
6803 u16 aspm_dis_mask = 0;
6804 u16 pdev_aspmc, parent_aspmc;
6805
6806 switch (state) {
6807 case PCIE_LINK_STATE_L0S:
6808 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6809 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6810 fallthrough; /* can't have L1 without L0s */
6811 case PCIE_LINK_STATE_L1:
6812 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6813 break;
6814 default:
6815 return;
6816 }
6817
6818 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6819 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6820
6821 if (parent) {
6822 pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6823 &parent_aspmc);
6824 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6825 }
6826
6827 /* Nothing to do if the ASPM states to be disabled already are */
6828 if (!(pdev_aspmc & aspm_dis_mask) &&
6829 (!parent || !(parent_aspmc & aspm_dis_mask)))
6830 return;
6831
6832 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6833 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6834 "L0s" : "",
6835 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6836 "L1" : "");
6837
6838#ifdef CONFIG_PCIEASPM
6839 if (locked)
6840 pci_disable_link_state_locked(pdev, state);
6841 else
6842 pci_disable_link_state(pdev, state);
6843
6844 /* Double-check ASPM control. If not disabled by the above, the
6845 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6846 * not enabled); override by writing PCI config space directly.
6847 */
6848 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6849 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6850
6851 if (!(aspm_dis_mask & pdev_aspmc))
6852 return;
6853#endif
6854
6855 /* Both device and parent should have the same ASPM setting.
6856 * Disable ASPM in downstream component first and then upstream.
6857 */
6858 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6859
6860 if (parent)
6861 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6862 aspm_dis_mask);
6863}
6864
6865/**
6866 * e1000e_disable_aspm - Disable ASPM states.
6867 * @pdev: pointer to PCI device struct
6868 * @state: bit-mask of ASPM states to disable
6869 *
6870 * This function acquires the pci_bus_sem!
6871 * Some devices *must* have certain ASPM states disabled per hardware errata.
6872 **/
6873static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6874{
6875 __e1000e_disable_aspm(pdev, state, 0);
6876}
6877
6878/**
6879 * e1000e_disable_aspm_locked - Disable ASPM states.
6880 * @pdev: pointer to PCI device struct
6881 * @state: bit-mask of ASPM states to disable
6882 *
6883 * This function must be called with pci_bus_sem acquired!
6884 * Some devices *must* have certain ASPM states disabled per hardware errata.
6885 **/
6886static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state)
6887{
6888 __e1000e_disable_aspm(pdev, state, 1);
6889}
6890
6891static int e1000e_pm_thaw(struct device *dev)
6892{
6893 struct net_device *netdev = dev_get_drvdata(dev);
6894 struct e1000_adapter *adapter = netdev_priv(netdev);
6895 int rc = 0;
6896
6897 e1000e_set_interrupt_capability(adapter);
6898
6899 rtnl_lock();
6900 if (netif_running(netdev)) {
6901 rc = e1000_request_irq(adapter);
6902 if (rc)
6903 goto err_irq;
6904
6905 e1000e_up(adapter);
6906 }
6907
6908 netif_device_attach(netdev);
6909err_irq:
6910 rtnl_unlock();
6911
6912 return rc;
6913}
6914
6915static int __e1000_resume(struct pci_dev *pdev)
6916{
6917 struct net_device *netdev = pci_get_drvdata(pdev);
6918 struct e1000_adapter *adapter = netdev_priv(netdev);
6919 struct e1000_hw *hw = &adapter->hw;
6920 u16 aspm_disable_flag = 0;
6921
6922 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6923 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6924 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6925 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6926 if (aspm_disable_flag)
6927 e1000e_disable_aspm(pdev, aspm_disable_flag);
6928
6929 pci_set_master(pdev);
6930
6931 if (hw->mac.type >= e1000_pch2lan)
6932 e1000_resume_workarounds_pchlan(&adapter->hw);
6933
6934 e1000e_power_up_phy(adapter);
6935
6936 /* report the system wakeup cause from S3/S4 */
6937 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6938 u16 phy_data;
6939
6940 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6941 if (phy_data) {
6942 e_info("PHY Wakeup cause - %s\n",
6943 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6944 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6945 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6946 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6947 phy_data & E1000_WUS_LNKC ?
6948 "Link Status Change" : "other");
6949 }
6950 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6951 } else {
6952 u32 wus = er32(WUS);
6953
6954 if (wus) {
6955 e_info("MAC Wakeup cause - %s\n",
6956 wus & E1000_WUS_EX ? "Unicast Packet" :
6957 wus & E1000_WUS_MC ? "Multicast Packet" :
6958 wus & E1000_WUS_BC ? "Broadcast Packet" :
6959 wus & E1000_WUS_MAG ? "Magic Packet" :
6960 wus & E1000_WUS_LNKC ? "Link Status Change" :
6961 "other");
6962 }
6963 ew32(WUS, ~0);
6964 }
6965
6966 e1000e_reset(adapter);
6967
6968 e1000_init_manageability_pt(adapter);
6969
6970 /* If the controller has AMT, do not set DRV_LOAD until the interface
6971 * is up. For all other cases, let the f/w know that the h/w is now
6972 * under the control of the driver.
6973 */
6974 if (!(adapter->flags & FLAG_HAS_AMT))
6975 e1000e_get_hw_control(adapter);
6976
6977 return 0;
6978}
6979
6980static __maybe_unused int e1000e_pm_prepare(struct device *dev)
6981{
6982 return pm_runtime_suspended(dev) &&
6983 pm_suspend_via_firmware();
6984}
6985
6986static __maybe_unused int e1000e_pm_suspend(struct device *dev)
6987{
6988 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6989 struct e1000_adapter *adapter = netdev_priv(netdev);
6990 struct pci_dev *pdev = to_pci_dev(dev);
6991 int rc;
6992
6993 e1000e_flush_lpic(pdev);
6994
6995 e1000e_pm_freeze(dev);
6996
6997 rc = __e1000_shutdown(pdev, false);
6998 if (rc) {
6999 e1000e_pm_thaw(dev);
7000 } else {
7001 /* Introduce S0ix implementation */
7002 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
7003 e1000e_s0ix_entry_flow(adapter);
7004 }
7005
7006 return rc;
7007}
7008
7009static __maybe_unused int e1000e_pm_resume(struct device *dev)
7010{
7011 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
7012 struct e1000_adapter *adapter = netdev_priv(netdev);
7013 struct pci_dev *pdev = to_pci_dev(dev);
7014 int rc;
7015
7016 /* Introduce S0ix implementation */
7017 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
7018 e1000e_s0ix_exit_flow(adapter);
7019
7020 rc = __e1000_resume(pdev);
7021 if (rc)
7022 return rc;
7023
7024 return e1000e_pm_thaw(dev);
7025}
7026
7027static __maybe_unused int e1000e_pm_runtime_idle(struct device *dev)
7028{
7029 struct net_device *netdev = dev_get_drvdata(dev);
7030 struct e1000_adapter *adapter = netdev_priv(netdev);
7031 u16 eee_lp;
7032
7033 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability;
7034
7035 if (!e1000e_has_link(adapter)) {
7036 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp;
7037 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);
7038 }
7039
7040 return -EBUSY;
7041}
7042
7043static __maybe_unused int e1000e_pm_runtime_resume(struct device *dev)
7044{
7045 struct pci_dev *pdev = to_pci_dev(dev);
7046 struct net_device *netdev = pci_get_drvdata(pdev);
7047 struct e1000_adapter *adapter = netdev_priv(netdev);
7048 int rc;
7049
7050 rc = __e1000_resume(pdev);
7051 if (rc)
7052 return rc;
7053
7054 if (netdev->flags & IFF_UP)
7055 e1000e_up(adapter);
7056
7057 return rc;
7058}
7059
7060static __maybe_unused int e1000e_pm_runtime_suspend(struct device *dev)
7061{
7062 struct pci_dev *pdev = to_pci_dev(dev);
7063 struct net_device *netdev = pci_get_drvdata(pdev);
7064 struct e1000_adapter *adapter = netdev_priv(netdev);
7065
7066 if (netdev->flags & IFF_UP) {
7067 int count = E1000_CHECK_RESET_COUNT;
7068
7069 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
7070 usleep_range(10000, 11000);
7071
7072 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
7073
7074 /* Down the device without resetting the hardware */
7075 e1000e_down(adapter, false);
7076 }
7077
7078 if (__e1000_shutdown(pdev, true)) {
7079 e1000e_pm_runtime_resume(dev);
7080 return -EBUSY;
7081 }
7082
7083 return 0;
7084}
7085
7086static void e1000_shutdown(struct pci_dev *pdev)
7087{
7088 e1000e_flush_lpic(pdev);
7089
7090 e1000e_pm_freeze(&pdev->dev);
7091
7092 __e1000_shutdown(pdev, false);
7093}
7094
7095#ifdef CONFIG_NET_POLL_CONTROLLER
7096
7097static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
7098{
7099 struct net_device *netdev = data;
7100 struct e1000_adapter *adapter = netdev_priv(netdev);
7101
7102 if (adapter->msix_entries) {
7103 int vector, msix_irq;
7104
7105 vector = 0;
7106 msix_irq = adapter->msix_entries[vector].vector;
7107 if (disable_hardirq(msix_irq))
7108 e1000_intr_msix_rx(msix_irq, netdev);
7109 enable_irq(msix_irq);
7110
7111 vector++;
7112 msix_irq = adapter->msix_entries[vector].vector;
7113 if (disable_hardirq(msix_irq))
7114 e1000_intr_msix_tx(msix_irq, netdev);
7115 enable_irq(msix_irq);
7116
7117 vector++;
7118 msix_irq = adapter->msix_entries[vector].vector;
7119 if (disable_hardirq(msix_irq))
7120 e1000_msix_other(msix_irq, netdev);
7121 enable_irq(msix_irq);
7122 }
7123
7124 return IRQ_HANDLED;
7125}
7126
7127/**
7128 * e1000_netpoll
7129 * @netdev: network interface device structure
7130 *
7131 * Polling 'interrupt' - used by things like netconsole to send skbs
7132 * without having to re-enable interrupts. It's not called while
7133 * the interrupt routine is executing.
7134 */
7135static void e1000_netpoll(struct net_device *netdev)
7136{
7137 struct e1000_adapter *adapter = netdev_priv(netdev);
7138
7139 switch (adapter->int_mode) {
7140 case E1000E_INT_MODE_MSIX:
7141 e1000_intr_msix(adapter->pdev->irq, netdev);
7142 break;
7143 case E1000E_INT_MODE_MSI:
7144 if (disable_hardirq(adapter->pdev->irq))
7145 e1000_intr_msi(adapter->pdev->irq, netdev);
7146 enable_irq(adapter->pdev->irq);
7147 break;
7148 default: /* E1000E_INT_MODE_LEGACY */
7149 if (disable_hardirq(adapter->pdev->irq))
7150 e1000_intr(adapter->pdev->irq, netdev);
7151 enable_irq(adapter->pdev->irq);
7152 break;
7153 }
7154}
7155#endif
7156
7157/**
7158 * e1000_io_error_detected - called when PCI error is detected
7159 * @pdev: Pointer to PCI device
7160 * @state: The current pci connection state
7161 *
7162 * This function is called after a PCI bus error affecting
7163 * this device has been detected.
7164 */
7165static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
7166 pci_channel_state_t state)
7167{
7168 e1000e_pm_freeze(&pdev->dev);
7169
7170 if (state == pci_channel_io_perm_failure)
7171 return PCI_ERS_RESULT_DISCONNECT;
7172
7173 pci_disable_device(pdev);
7174
7175 /* Request a slot reset. */
7176 return PCI_ERS_RESULT_NEED_RESET;
7177}
7178
7179/**
7180 * e1000_io_slot_reset - called after the pci bus has been reset.
7181 * @pdev: Pointer to PCI device
7182 *
7183 * Restart the card from scratch, as if from a cold-boot. Implementation
7184 * resembles the first-half of the e1000e_pm_resume routine.
7185 */
7186static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
7187{
7188 struct net_device *netdev = pci_get_drvdata(pdev);
7189 struct e1000_adapter *adapter = netdev_priv(netdev);
7190 struct e1000_hw *hw = &adapter->hw;
7191 u16 aspm_disable_flag = 0;
7192 int err;
7193 pci_ers_result_t result;
7194
7195 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
7196 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7197 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
7198 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7199 if (aspm_disable_flag)
7200 e1000e_disable_aspm_locked(pdev, aspm_disable_flag);
7201
7202 err = pci_enable_device_mem(pdev);
7203 if (err) {
7204 dev_err(&pdev->dev,
7205 "Cannot re-enable PCI device after reset.\n");
7206 result = PCI_ERS_RESULT_DISCONNECT;
7207 } else {
7208 pdev->state_saved = true;
7209 pci_restore_state(pdev);
7210 pci_set_master(pdev);
7211
7212 pci_enable_wake(pdev, PCI_D3hot, 0);
7213 pci_enable_wake(pdev, PCI_D3cold, 0);
7214
7215 e1000e_reset(adapter);
7216 ew32(WUS, ~0);
7217 result = PCI_ERS_RESULT_RECOVERED;
7218 }
7219
7220 return result;
7221}
7222
7223/**
7224 * e1000_io_resume - called when traffic can start flowing again.
7225 * @pdev: Pointer to PCI device
7226 *
7227 * This callback is called when the error recovery driver tells us that
7228 * its OK to resume normal operation. Implementation resembles the
7229 * second-half of the e1000e_pm_resume routine.
7230 */
7231static void e1000_io_resume(struct pci_dev *pdev)
7232{
7233 struct net_device *netdev = pci_get_drvdata(pdev);
7234 struct e1000_adapter *adapter = netdev_priv(netdev);
7235
7236 e1000_init_manageability_pt(adapter);
7237
7238 e1000e_pm_thaw(&pdev->dev);
7239
7240 /* If the controller has AMT, do not set DRV_LOAD until the interface
7241 * is up. For all other cases, let the f/w know that the h/w is now
7242 * under the control of the driver.
7243 */
7244 if (!(adapter->flags & FLAG_HAS_AMT))
7245 e1000e_get_hw_control(adapter);
7246}
7247
7248static void e1000_print_device_info(struct e1000_adapter *adapter)
7249{
7250 struct e1000_hw *hw = &adapter->hw;
7251 struct net_device *netdev = adapter->netdev;
7252 u32 ret_val;
7253 u8 pba_str[E1000_PBANUM_LENGTH];
7254
7255 /* print bus type/speed/width info */
7256 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
7257 /* bus width */
7258 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
7259 "Width x1"),
7260 /* MAC address */
7261 netdev->dev_addr);
7262 e_info("Intel(R) PRO/%s Network Connection\n",
7263 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
7264 ret_val = e1000_read_pba_string_generic(hw, pba_str,
7265 E1000_PBANUM_LENGTH);
7266 if (ret_val)
7267 strscpy((char *)pba_str, "Unknown", sizeof(pba_str));
7268 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
7269 hw->mac.type, hw->phy.type, pba_str);
7270}
7271
7272static void e1000_eeprom_checks(struct e1000_adapter *adapter)
7273{
7274 struct e1000_hw *hw = &adapter->hw;
7275 int ret_val;
7276 u16 buf = 0;
7277
7278 if (hw->mac.type != e1000_82573)
7279 return;
7280
7281 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
7282 le16_to_cpus(&buf);
7283 if (!ret_val && (!(buf & BIT(0)))) {
7284 /* Deep Smart Power Down (DSPD) */
7285 dev_warn(&adapter->pdev->dev,
7286 "Warning: detected DSPD enabled in EEPROM\n");
7287 }
7288}
7289
7290static netdev_features_t e1000_fix_features(struct net_device *netdev,
7291 netdev_features_t features)
7292{
7293 struct e1000_adapter *adapter = netdev_priv(netdev);
7294 struct e1000_hw *hw = &adapter->hw;
7295
7296 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
7297 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN))
7298 features &= ~NETIF_F_RXFCS;
7299
7300 /* Since there is no support for separate Rx/Tx vlan accel
7301 * enable/disable make sure Tx flag is always in same state as Rx.
7302 */
7303 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7304 features |= NETIF_F_HW_VLAN_CTAG_TX;
7305 else
7306 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
7307
7308 return features;
7309}
7310
7311static int e1000_set_features(struct net_device *netdev,
7312 netdev_features_t features)
7313{
7314 struct e1000_adapter *adapter = netdev_priv(netdev);
7315 netdev_features_t changed = features ^ netdev->features;
7316
7317 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
7318 adapter->flags |= FLAG_TSO_FORCE;
7319
7320 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
7321 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
7322 NETIF_F_RXALL)))
7323 return 0;
7324
7325 if (changed & NETIF_F_RXFCS) {
7326 if (features & NETIF_F_RXFCS) {
7327 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7328 } else {
7329 /* We need to take it back to defaults, which might mean
7330 * stripping is still disabled at the adapter level.
7331 */
7332 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
7333 adapter->flags2 |= FLAG2_CRC_STRIPPING;
7334 else
7335 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7336 }
7337 }
7338
7339 netdev->features = features;
7340
7341 if (netif_running(netdev))
7342 e1000e_reinit_locked(adapter);
7343 else
7344 e1000e_reset(adapter);
7345
7346 return 1;
7347}
7348
7349static const struct net_device_ops e1000e_netdev_ops = {
7350 .ndo_open = e1000e_open,
7351 .ndo_stop = e1000e_close,
7352 .ndo_start_xmit = e1000_xmit_frame,
7353 .ndo_get_stats64 = e1000e_get_stats64,
7354 .ndo_set_rx_mode = e1000e_set_rx_mode,
7355 .ndo_set_mac_address = e1000_set_mac,
7356 .ndo_change_mtu = e1000_change_mtu,
7357 .ndo_eth_ioctl = e1000_ioctl,
7358 .ndo_tx_timeout = e1000_tx_timeout,
7359 .ndo_validate_addr = eth_validate_addr,
7360
7361 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
7362 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
7363#ifdef CONFIG_NET_POLL_CONTROLLER
7364 .ndo_poll_controller = e1000_netpoll,
7365#endif
7366 .ndo_set_features = e1000_set_features,
7367 .ndo_fix_features = e1000_fix_features,
7368 .ndo_features_check = passthru_features_check,
7369};
7370
7371/**
7372 * e1000_probe - Device Initialization Routine
7373 * @pdev: PCI device information struct
7374 * @ent: entry in e1000_pci_tbl
7375 *
7376 * Returns 0 on success, negative on failure
7377 *
7378 * e1000_probe initializes an adapter identified by a pci_dev structure.
7379 * The OS initialization, configuring of the adapter private structure,
7380 * and a hardware reset occur.
7381 **/
7382static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7383{
7384 struct net_device *netdev;
7385 struct e1000_adapter *adapter;
7386 struct e1000_hw *hw;
7387 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
7388 resource_size_t mmio_start, mmio_len;
7389 resource_size_t flash_start, flash_len;
7390 static int cards_found;
7391 u16 aspm_disable_flag = 0;
7392 u16 eeprom_data = 0;
7393 u16 eeprom_apme_mask = E1000_EEPROM_APME;
7394 int bars, i, err;
7395 s32 ret_val = 0;
7396
7397 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
7398 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7399 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
7400 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7401 if (aspm_disable_flag)
7402 e1000e_disable_aspm(pdev, aspm_disable_flag);
7403
7404 err = pci_enable_device_mem(pdev);
7405 if (err)
7406 return err;
7407
7408 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7409 if (err) {
7410 dev_err(&pdev->dev,
7411 "No usable DMA configuration, aborting\n");
7412 goto err_dma;
7413 }
7414
7415 bars = pci_select_bars(pdev, IORESOURCE_MEM);
7416 err = pci_request_selected_regions_exclusive(pdev, bars,
7417 e1000e_driver_name);
7418 if (err)
7419 goto err_pci_reg;
7420
7421 /* AER (Advanced Error Reporting) hooks */
7422 pci_enable_pcie_error_reporting(pdev);
7423
7424 pci_set_master(pdev);
7425 /* PCI config space info */
7426 err = pci_save_state(pdev);
7427 if (err)
7428 goto err_alloc_etherdev;
7429
7430 err = -ENOMEM;
7431 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
7432 if (!netdev)
7433 goto err_alloc_etherdev;
7434
7435 SET_NETDEV_DEV(netdev, &pdev->dev);
7436
7437 netdev->irq = pdev->irq;
7438
7439 pci_set_drvdata(pdev, netdev);
7440 adapter = netdev_priv(netdev);
7441 hw = &adapter->hw;
7442 adapter->netdev = netdev;
7443 adapter->pdev = pdev;
7444 adapter->ei = ei;
7445 adapter->pba = ei->pba;
7446 adapter->flags = ei->flags;
7447 adapter->flags2 = ei->flags2;
7448 adapter->hw.adapter = adapter;
7449 adapter->hw.mac.type = ei->mac;
7450 adapter->max_hw_frame_size = ei->max_hw_frame_size;
7451 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7452
7453 mmio_start = pci_resource_start(pdev, 0);
7454 mmio_len = pci_resource_len(pdev, 0);
7455
7456 err = -EIO;
7457 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
7458 if (!adapter->hw.hw_addr)
7459 goto err_ioremap;
7460
7461 if ((adapter->flags & FLAG_HAS_FLASH) &&
7462 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) &&
7463 (hw->mac.type < e1000_pch_spt)) {
7464 flash_start = pci_resource_start(pdev, 1);
7465 flash_len = pci_resource_len(pdev, 1);
7466 adapter->hw.flash_address = ioremap(flash_start, flash_len);
7467 if (!adapter->hw.flash_address)
7468 goto err_flashmap;
7469 }
7470
7471 /* Set default EEE advertisement */
7472 if (adapter->flags2 & FLAG2_HAS_EEE)
7473 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
7474
7475 /* construct the net_device struct */
7476 netdev->netdev_ops = &e1000e_netdev_ops;
7477 e1000e_set_ethtool_ops(netdev);
7478 netdev->watchdog_timeo = 5 * HZ;
7479 netif_napi_add(netdev, &adapter->napi, e1000e_poll);
7480 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
7481
7482 netdev->mem_start = mmio_start;
7483 netdev->mem_end = mmio_start + mmio_len;
7484
7485 adapter->bd_number = cards_found++;
7486
7487 e1000e_check_options(adapter);
7488
7489 /* setup adapter struct */
7490 err = e1000_sw_init(adapter);
7491 if (err)
7492 goto err_sw_init;
7493
7494 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
7495 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
7496 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
7497
7498 err = ei->get_variants(adapter);
7499 if (err)
7500 goto err_hw_init;
7501
7502 if ((adapter->flags & FLAG_IS_ICH) &&
7503 (adapter->flags & FLAG_READ_ONLY_NVM) &&
7504 (hw->mac.type < e1000_pch_spt))
7505 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
7506
7507 hw->mac.ops.get_bus_info(&adapter->hw);
7508
7509 adapter->hw.phy.autoneg_wait_to_complete = 0;
7510
7511 /* Copper options */
7512 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
7513 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7514 adapter->hw.phy.disable_polarity_correction = 0;
7515 adapter->hw.phy.ms_type = e1000_ms_hw_default;
7516 }
7517
7518 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
7519 dev_info(&pdev->dev,
7520 "PHY reset is blocked due to SOL/IDER session.\n");
7521
7522 /* Set initial default active device features */
7523 netdev->features = (NETIF_F_SG |
7524 NETIF_F_HW_VLAN_CTAG_RX |
7525 NETIF_F_HW_VLAN_CTAG_TX |
7526 NETIF_F_TSO |
7527 NETIF_F_TSO6 |
7528 NETIF_F_RXHASH |
7529 NETIF_F_RXCSUM |
7530 NETIF_F_HW_CSUM);
7531
7532 /* Set user-changeable features (subset of all device features) */
7533 netdev->hw_features = netdev->features;
7534 netdev->hw_features |= NETIF_F_RXFCS;
7535 netdev->priv_flags |= IFF_SUPP_NOFCS;
7536 netdev->hw_features |= NETIF_F_RXALL;
7537
7538 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
7539 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
7540
7541 netdev->vlan_features |= (NETIF_F_SG |
7542 NETIF_F_TSO |
7543 NETIF_F_TSO6 |
7544 NETIF_F_HW_CSUM);
7545
7546 netdev->priv_flags |= IFF_UNICAST_FLT;
7547
7548 netdev->features |= NETIF_F_HIGHDMA;
7549 netdev->vlan_features |= NETIF_F_HIGHDMA;
7550
7551 /* MTU range: 68 - max_hw_frame_size */
7552 netdev->min_mtu = ETH_MIN_MTU;
7553 netdev->max_mtu = adapter->max_hw_frame_size -
7554 (VLAN_ETH_HLEN + ETH_FCS_LEN);
7555
7556 if (e1000e_enable_mng_pass_thru(&adapter->hw))
7557 adapter->flags |= FLAG_MNG_PT_ENABLED;
7558
7559 /* before reading the NVM, reset the controller to
7560 * put the device in a known good starting state
7561 */
7562 adapter->hw.mac.ops.reset_hw(&adapter->hw);
7563
7564 /* systems with ASPM and others may see the checksum fail on the first
7565 * attempt. Let's give it a few tries
7566 */
7567 for (i = 0;; i++) {
7568 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
7569 break;
7570 if (i == 2) {
7571 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
7572 err = -EIO;
7573 goto err_eeprom;
7574 }
7575 }
7576
7577 e1000_eeprom_checks(adapter);
7578
7579 /* copy the MAC address */
7580 if (e1000e_read_mac_addr(&adapter->hw))
7581 dev_err(&pdev->dev,
7582 "NVM Read Error while reading MAC address\n");
7583
7584 eth_hw_addr_set(netdev, adapter->hw.mac.addr);
7585
7586 if (!is_valid_ether_addr(netdev->dev_addr)) {
7587 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
7588 netdev->dev_addr);
7589 err = -EIO;
7590 goto err_eeprom;
7591 }
7592
7593 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0);
7594 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0);
7595
7596 INIT_WORK(&adapter->reset_task, e1000_reset_task);
7597 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
7598 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
7599 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
7600 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
7601
7602 /* Initialize link parameters. User can change them with ethtool */
7603 adapter->hw.mac.autoneg = 1;
7604 adapter->fc_autoneg = true;
7605 adapter->hw.fc.requested_mode = e1000_fc_default;
7606 adapter->hw.fc.current_mode = e1000_fc_default;
7607 adapter->hw.phy.autoneg_advertised = 0x2f;
7608
7609 /* Initial Wake on LAN setting - If APM wake is enabled in
7610 * the EEPROM, enable the ACPI Magic Packet filter
7611 */
7612 if (adapter->flags & FLAG_APME_IN_WUC) {
7613 /* APME bit in EEPROM is mapped to WUC.APME */
7614 eeprom_data = er32(WUC);
7615 eeprom_apme_mask = E1000_WUC_APME;
7616 if ((hw->mac.type > e1000_ich10lan) &&
7617 (eeprom_data & E1000_WUC_PHY_WAKE))
7618 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
7619 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
7620 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
7621 (adapter->hw.bus.func == 1))
7622 ret_val = e1000_read_nvm(&adapter->hw,
7623 NVM_INIT_CONTROL3_PORT_B,
7624 1, &eeprom_data);
7625 else
7626 ret_val = e1000_read_nvm(&adapter->hw,
7627 NVM_INIT_CONTROL3_PORT_A,
7628 1, &eeprom_data);
7629 }
7630
7631 /* fetch WoL from EEPROM */
7632 if (ret_val)
7633 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val);
7634 else if (eeprom_data & eeprom_apme_mask)
7635 adapter->eeprom_wol |= E1000_WUFC_MAG;
7636
7637 /* now that we have the eeprom settings, apply the special cases
7638 * where the eeprom may be wrong or the board simply won't support
7639 * wake on lan on a particular port
7640 */
7641 if (!(adapter->flags & FLAG_HAS_WOL))
7642 adapter->eeprom_wol = 0;
7643
7644 /* initialize the wol settings based on the eeprom settings */
7645 adapter->wol = adapter->eeprom_wol;
7646
7647 /* make sure adapter isn't asleep if manageability is enabled */
7648 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
7649 (hw->mac.ops.check_mng_mode(hw)))
7650 device_wakeup_enable(&pdev->dev);
7651
7652 /* save off EEPROM version number */
7653 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
7654
7655 if (ret_val) {
7656 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val);
7657 adapter->eeprom_vers = 0;
7658 }
7659
7660 /* init PTP hardware clock */
7661 e1000e_ptp_init(adapter);
7662
7663 /* reset the hardware with the new settings */
7664 e1000e_reset(adapter);
7665
7666 /* If the controller has AMT, do not set DRV_LOAD until the interface
7667 * is up. For all other cases, let the f/w know that the h/w is now
7668 * under the control of the driver.
7669 */
7670 if (!(adapter->flags & FLAG_HAS_AMT))
7671 e1000e_get_hw_control(adapter);
7672
7673 if (hw->mac.type >= e1000_pch_cnp)
7674 adapter->flags2 |= FLAG2_ENABLE_S0IX_FLOWS;
7675
7676 strscpy(netdev->name, "eth%d", sizeof(netdev->name));
7677 err = register_netdev(netdev);
7678 if (err)
7679 goto err_register;
7680
7681 /* carrier off reporting is important to ethtool even BEFORE open */
7682 netif_carrier_off(netdev);
7683
7684 e1000_print_device_info(adapter);
7685
7686 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_SMART_PREPARE);
7687
7688 if (pci_dev_run_wake(pdev) && hw->mac.type != e1000_pch_cnp)
7689 pm_runtime_put_noidle(&pdev->dev);
7690
7691 return 0;
7692
7693err_register:
7694 if (!(adapter->flags & FLAG_HAS_AMT))
7695 e1000e_release_hw_control(adapter);
7696err_eeprom:
7697 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
7698 e1000_phy_hw_reset(&adapter->hw);
7699err_hw_init:
7700 kfree(adapter->tx_ring);
7701 kfree(adapter->rx_ring);
7702err_sw_init:
7703 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt))
7704 iounmap(adapter->hw.flash_address);
7705 e1000e_reset_interrupt_capability(adapter);
7706err_flashmap:
7707 iounmap(adapter->hw.hw_addr);
7708err_ioremap:
7709 free_netdev(netdev);
7710err_alloc_etherdev:
7711 pci_disable_pcie_error_reporting(pdev);
7712 pci_release_mem_regions(pdev);
7713err_pci_reg:
7714err_dma:
7715 pci_disable_device(pdev);
7716 return err;
7717}
7718
7719/**
7720 * e1000_remove - Device Removal Routine
7721 * @pdev: PCI device information struct
7722 *
7723 * e1000_remove is called by the PCI subsystem to alert the driver
7724 * that it should release a PCI device. This could be caused by a
7725 * Hot-Plug event, or because the driver is going to be removed from
7726 * memory.
7727 **/
7728static void e1000_remove(struct pci_dev *pdev)
7729{
7730 struct net_device *netdev = pci_get_drvdata(pdev);
7731 struct e1000_adapter *adapter = netdev_priv(netdev);
7732
7733 e1000e_ptp_remove(adapter);
7734
7735 /* The timers may be rescheduled, so explicitly disable them
7736 * from being rescheduled.
7737 */
7738 set_bit(__E1000_DOWN, &adapter->state);
7739 del_timer_sync(&adapter->watchdog_timer);
7740 del_timer_sync(&adapter->phy_info_timer);
7741
7742 cancel_work_sync(&adapter->reset_task);
7743 cancel_work_sync(&adapter->watchdog_task);
7744 cancel_work_sync(&adapter->downshift_task);
7745 cancel_work_sync(&adapter->update_phy_task);
7746 cancel_work_sync(&adapter->print_hang_task);
7747
7748 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
7749 cancel_work_sync(&adapter->tx_hwtstamp_work);
7750 if (adapter->tx_hwtstamp_skb) {
7751 dev_consume_skb_any(adapter->tx_hwtstamp_skb);
7752 adapter->tx_hwtstamp_skb = NULL;
7753 }
7754 }
7755
7756 unregister_netdev(netdev);
7757
7758 if (pci_dev_run_wake(pdev))
7759 pm_runtime_get_noresume(&pdev->dev);
7760
7761 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7762 * would have already happened in close and is redundant.
7763 */
7764 e1000e_release_hw_control(adapter);
7765
7766 e1000e_reset_interrupt_capability(adapter);
7767 kfree(adapter->tx_ring);
7768 kfree(adapter->rx_ring);
7769
7770 iounmap(adapter->hw.hw_addr);
7771 if ((adapter->hw.flash_address) &&
7772 (adapter->hw.mac.type < e1000_pch_spt))
7773 iounmap(adapter->hw.flash_address);
7774 pci_release_mem_regions(pdev);
7775
7776 free_netdev(netdev);
7777
7778 /* AER disable */
7779 pci_disable_pcie_error_reporting(pdev);
7780
7781 pci_disable_device(pdev);
7782}
7783
7784/* PCI Error Recovery (ERS) */
7785static const struct pci_error_handlers e1000_err_handler = {
7786 .error_detected = e1000_io_error_detected,
7787 .slot_reset = e1000_io_slot_reset,
7788 .resume = e1000_io_resume,
7789};
7790
7791static const struct pci_device_id e1000_pci_tbl[] = {
7792 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
7793 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
7794 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
7795 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7796 board_82571 },
7797 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
7798 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
7799 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
7800 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
7801 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
7802
7803 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
7804 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
7805 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
7806 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
7807
7808 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
7809 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
7810 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
7811
7812 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
7813 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
7814 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
7815
7816 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7817 board_80003es2lan },
7818 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7819 board_80003es2lan },
7820 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7821 board_80003es2lan },
7822 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7823 board_80003es2lan },
7824
7825 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
7826 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
7827 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
7828 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
7829 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
7830 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
7831 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
7832 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
7833
7834 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
7835 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
7836 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
7837 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
7838 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
7839 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
7840 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
7841 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
7842 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
7843
7844 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
7845 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
7846 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
7847
7848 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
7849 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
7850 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
7851
7852 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
7853 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
7854 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7855 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7856
7857 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7858 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7859
7860 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7861 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
7862 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7863 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
7864 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt },
7865 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7866 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7867 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
7868 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt },
7869 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt },
7870 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt },
7871 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt },
7872 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt },
7873 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt },
7874 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt },
7875 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt },
7876 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt },
7877 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp },
7878 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp },
7879 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp },
7880 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp },
7881 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp },
7882 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp },
7883 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp },
7884 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp },
7885 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM10), board_pch_cnp },
7886 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V10), board_pch_cnp },
7887 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM11), board_pch_cnp },
7888 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), board_pch_cnp },
7889 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), board_pch_spt },
7890 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), board_pch_spt },
7891 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_tgp },
7892 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_tgp },
7893 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_tgp },
7894 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_tgp },
7895 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_tgp },
7896 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), board_pch_tgp },
7897 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM23), board_pch_adp },
7898 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V23), board_pch_adp },
7899 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), board_pch_adp },
7900 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), board_pch_adp },
7901 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), board_pch_adp },
7902 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), board_pch_adp },
7903 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM22), board_pch_adp },
7904 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V22), board_pch_adp },
7905 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM18), board_pch_mtp },
7906 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V18), board_pch_mtp },
7907 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM19), board_pch_mtp },
7908 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V19), board_pch_mtp },
7909 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM20), board_pch_mtp },
7910 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V20), board_pch_mtp },
7911 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM21), board_pch_mtp },
7912 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V21), board_pch_mtp },
7913 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_LM24), board_pch_mtp },
7914 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_V24), board_pch_mtp },
7915 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM25), board_pch_mtp },
7916 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V25), board_pch_mtp },
7917 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM26), board_pch_mtp },
7918 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V26), board_pch_mtp },
7919 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM27), board_pch_mtp },
7920 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V27), board_pch_mtp },
7921
7922 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
7923};
7924MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7925
7926static const struct dev_pm_ops e1000_pm_ops = {
7927#ifdef CONFIG_PM_SLEEP
7928 .prepare = e1000e_pm_prepare,
7929 .suspend = e1000e_pm_suspend,
7930 .resume = e1000e_pm_resume,
7931 .freeze = e1000e_pm_freeze,
7932 .thaw = e1000e_pm_thaw,
7933 .poweroff = e1000e_pm_suspend,
7934 .restore = e1000e_pm_resume,
7935#endif
7936 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
7937 e1000e_pm_runtime_idle)
7938};
7939
7940/* PCI Device API Driver */
7941static struct pci_driver e1000_driver = {
7942 .name = e1000e_driver_name,
7943 .id_table = e1000_pci_tbl,
7944 .probe = e1000_probe,
7945 .remove = e1000_remove,
7946 .driver = {
7947 .pm = &e1000_pm_ops,
7948 },
7949 .shutdown = e1000_shutdown,
7950 .err_handler = &e1000_err_handler
7951};
7952
7953/**
7954 * e1000_init_module - Driver Registration Routine
7955 *
7956 * e1000_init_module is the first routine called when the driver is
7957 * loaded. All it does is register with the PCI subsystem.
7958 **/
7959static int __init e1000_init_module(void)
7960{
7961 pr_info("Intel(R) PRO/1000 Network Driver\n");
7962 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n");
7963
7964 return pci_register_driver(&e1000_driver);
7965}
7966module_init(e1000_init_module);
7967
7968/**
7969 * e1000_exit_module - Driver Exit Cleanup Routine
7970 *
7971 * e1000_exit_module is called just before the driver is removed
7972 * from memory.
7973 **/
7974static void __exit e1000_exit_module(void)
7975{
7976 pci_unregister_driver(&e1000_driver);
7977}
7978module_exit(e1000_exit_module);
7979
7980MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7981MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7982MODULE_LICENSE("GPL v2");
7983
7984/* netdev.c */