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1/*
2 * Copyright (C) 1995 Linus Torvalds
3 *
4 * Pentium III FXSR, SSE support
5 * Gareth Hughes <gareth@valinux.com>, May 2000
6 */
7
8/*
9 * This file handles the architecture-dependent parts of process handling..
10 */
11
12#include <linux/cpu.h>
13#include <linux/errno.h>
14#include <linux/sched.h>
15#include <linux/sched/task.h>
16#include <linux/sched/task_stack.h>
17#include <linux/fs.h>
18#include <linux/kernel.h>
19#include <linux/mm.h>
20#include <linux/elfcore.h>
21#include <linux/smp.h>
22#include <linux/stddef.h>
23#include <linux/slab.h>
24#include <linux/vmalloc.h>
25#include <linux/user.h>
26#include <linux/interrupt.h>
27#include <linux/delay.h>
28#include <linux/reboot.h>
29#include <linux/mc146818rtc.h>
30#include <linux/export.h>
31#include <linux/kallsyms.h>
32#include <linux/ptrace.h>
33#include <linux/personality.h>
34#include <linux/percpu.h>
35#include <linux/prctl.h>
36#include <linux/ftrace.h>
37#include <linux/uaccess.h>
38#include <linux/io.h>
39#include <linux/kdebug.h>
40#include <linux/syscalls.h>
41
42#include <asm/ldt.h>
43#include <asm/processor.h>
44#include <asm/fpu/sched.h>
45#include <asm/desc.h>
46
47#include <linux/err.h>
48
49#include <asm/tlbflush.h>
50#include <asm/cpu.h>
51#include <asm/debugreg.h>
52#include <asm/switch_to.h>
53#include <asm/vm86.h>
54#include <asm/resctrl.h>
55#include <asm/proto.h>
56
57#include "process.h"
58
59void __show_regs(struct pt_regs *regs, enum show_regs_mode mode,
60 const char *log_lvl)
61{
62 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
63 unsigned long d0, d1, d2, d3, d6, d7;
64 unsigned short gs;
65
66 savesegment(gs, gs);
67
68 show_ip(regs, log_lvl);
69
70 printk("%sEAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
71 log_lvl, regs->ax, regs->bx, regs->cx, regs->dx);
72 printk("%sESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
73 log_lvl, regs->si, regs->di, regs->bp, regs->sp);
74 printk("%sDS: %04x ES: %04x FS: %04x GS: %04x SS: %04x EFLAGS: %08lx\n",
75 log_lvl, (u16)regs->ds, (u16)regs->es, (u16)regs->fs, gs, regs->ss, regs->flags);
76
77 if (mode != SHOW_REGS_ALL)
78 return;
79
80 cr0 = read_cr0();
81 cr2 = read_cr2();
82 cr3 = __read_cr3();
83 cr4 = __read_cr4();
84 printk("%sCR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
85 log_lvl, cr0, cr2, cr3, cr4);
86
87 get_debugreg(d0, 0);
88 get_debugreg(d1, 1);
89 get_debugreg(d2, 2);
90 get_debugreg(d3, 3);
91 get_debugreg(d6, 6);
92 get_debugreg(d7, 7);
93
94 /* Only print out debug registers if they are in their non-default state. */
95 if ((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) &&
96 (d6 == DR6_RESERVED) && (d7 == 0x400))
97 return;
98
99 printk("%sDR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
100 log_lvl, d0, d1, d2, d3);
101 printk("%sDR6: %08lx DR7: %08lx\n",
102 log_lvl, d6, d7);
103}
104
105void release_thread(struct task_struct *dead_task)
106{
107 BUG_ON(dead_task->mm);
108 release_vm86_irqs(dead_task);
109}
110
111void
112start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
113{
114 loadsegment(gs, 0);
115 regs->fs = 0;
116 regs->ds = __USER_DS;
117 regs->es = __USER_DS;
118 regs->ss = __USER_DS;
119 regs->cs = __USER_CS;
120 regs->ip = new_ip;
121 regs->sp = new_sp;
122 regs->flags = X86_EFLAGS_IF;
123}
124EXPORT_SYMBOL_GPL(start_thread);
125
126
127/*
128 * switch_to(x,y) should switch tasks from x to y.
129 *
130 * We fsave/fwait so that an exception goes off at the right time
131 * (as a call from the fsave or fwait in effect) rather than to
132 * the wrong process. Lazy FP saving no longer makes any sense
133 * with modern CPU's, and this simplifies a lot of things (SMP
134 * and UP become the same).
135 *
136 * NOTE! We used to use the x86 hardware context switching. The
137 * reason for not using it any more becomes apparent when you
138 * try to recover gracefully from saved state that is no longer
139 * valid (stale segment register values in particular). With the
140 * hardware task-switch, there is no way to fix up bad state in
141 * a reasonable manner.
142 *
143 * The fact that Intel documents the hardware task-switching to
144 * be slow is a fairly red herring - this code is not noticeably
145 * faster. However, there _is_ some room for improvement here,
146 * so the performance issues may eventually be a valid point.
147 * More important, however, is the fact that this allows us much
148 * more flexibility.
149 *
150 * The return value (in %ax) will be the "prev" task after
151 * the task-switch, and shows up in ret_from_fork in entry.S,
152 * for example.
153 */
154__visible __notrace_funcgraph struct task_struct *
155__switch_to(struct task_struct *prev_p, struct task_struct *next_p)
156{
157 struct thread_struct *prev = &prev_p->thread,
158 *next = &next_p->thread;
159 int cpu = smp_processor_id();
160
161 /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */
162
163 if (!test_tsk_thread_flag(prev_p, TIF_NEED_FPU_LOAD))
164 switch_fpu_prepare(prev_p, cpu);
165
166 /*
167 * Save away %gs. No need to save %fs, as it was saved on the
168 * stack on entry. No need to save %es and %ds, as those are
169 * always kernel segments while inside the kernel. Doing this
170 * before setting the new TLS descriptors avoids the situation
171 * where we temporarily have non-reloadable segments in %fs
172 * and %gs. This could be an issue if the NMI handler ever
173 * used %fs or %gs (it does not today), or if the kernel is
174 * running inside of a hypervisor layer.
175 */
176 savesegment(gs, prev->gs);
177
178 /*
179 * Load the per-thread Thread-Local Storage descriptor.
180 */
181 load_TLS(next, cpu);
182
183 switch_to_extra(prev_p, next_p);
184
185 /*
186 * Leave lazy mode, flushing any hypercalls made here.
187 * This must be done before restoring TLS segments so
188 * the GDT and LDT are properly updated.
189 */
190 arch_end_context_switch(next_p);
191
192 /*
193 * Reload esp0 and pcpu_hot.top_of_stack. This changes
194 * current_thread_info(). Refresh the SYSENTER configuration in
195 * case prev or next is vm86.
196 */
197 update_task_stack(next_p);
198 refresh_sysenter_cs(next);
199 this_cpu_write(pcpu_hot.top_of_stack,
200 (unsigned long)task_stack_page(next_p) +
201 THREAD_SIZE);
202
203 /*
204 * Restore %gs if needed (which is common)
205 */
206 if (prev->gs | next->gs)
207 loadsegment(gs, next->gs);
208
209 raw_cpu_write(pcpu_hot.current_task, next_p);
210
211 switch_fpu_finish(next_p);
212
213 /* Load the Intel cache allocation PQR MSR. */
214 resctrl_sched_in(next_p);
215
216 return prev_p;
217}
218
219SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2)
220{
221 return do_arch_prctl_common(option, arg2);
222}
1/*
2 * Copyright (C) 1995 Linus Torvalds
3 *
4 * Pentium III FXSR, SSE support
5 * Gareth Hughes <gareth@valinux.com>, May 2000
6 */
7
8/*
9 * This file handles the architecture-dependent parts of process handling..
10 */
11
12#include <linux/cpu.h>
13#include <linux/errno.h>
14#include <linux/sched.h>
15#include <linux/sched/task.h>
16#include <linux/sched/task_stack.h>
17#include <linux/fs.h>
18#include <linux/kernel.h>
19#include <linux/mm.h>
20#include <linux/elfcore.h>
21#include <linux/smp.h>
22#include <linux/stddef.h>
23#include <linux/slab.h>
24#include <linux/vmalloc.h>
25#include <linux/user.h>
26#include <linux/interrupt.h>
27#include <linux/delay.h>
28#include <linux/reboot.h>
29#include <linux/mc146818rtc.h>
30#include <linux/export.h>
31#include <linux/kallsyms.h>
32#include <linux/ptrace.h>
33#include <linux/personality.h>
34#include <linux/percpu.h>
35#include <linux/prctl.h>
36#include <linux/ftrace.h>
37#include <linux/uaccess.h>
38#include <linux/io.h>
39#include <linux/kdebug.h>
40#include <linux/syscalls.h>
41
42#include <asm/ldt.h>
43#include <asm/processor.h>
44#include <asm/fpu/internal.h>
45#include <asm/desc.h>
46
47#include <linux/err.h>
48
49#include <asm/tlbflush.h>
50#include <asm/cpu.h>
51#include <asm/debugreg.h>
52#include <asm/switch_to.h>
53#include <asm/vm86.h>
54#include <asm/resctrl.h>
55#include <asm/proto.h>
56
57#include "process.h"
58
59void __show_regs(struct pt_regs *regs, enum show_regs_mode mode,
60 const char *log_lvl)
61{
62 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
63 unsigned long d0, d1, d2, d3, d6, d7;
64 unsigned short gs;
65
66 if (user_mode(regs))
67 gs = get_user_gs(regs);
68 else
69 savesegment(gs, gs);
70
71 show_ip(regs, log_lvl);
72
73 printk("%sEAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
74 log_lvl, regs->ax, regs->bx, regs->cx, regs->dx);
75 printk("%sESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
76 log_lvl, regs->si, regs->di, regs->bp, regs->sp);
77 printk("%sDS: %04x ES: %04x FS: %04x GS: %04x SS: %04x EFLAGS: %08lx\n",
78 log_lvl, (u16)regs->ds, (u16)regs->es, (u16)regs->fs, gs, regs->ss, regs->flags);
79
80 if (mode != SHOW_REGS_ALL)
81 return;
82
83 cr0 = read_cr0();
84 cr2 = read_cr2();
85 cr3 = __read_cr3();
86 cr4 = __read_cr4();
87 printk("%sCR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
88 log_lvl, cr0, cr2, cr3, cr4);
89
90 get_debugreg(d0, 0);
91 get_debugreg(d1, 1);
92 get_debugreg(d2, 2);
93 get_debugreg(d3, 3);
94 get_debugreg(d6, 6);
95 get_debugreg(d7, 7);
96
97 /* Only print out debug registers if they are in their non-default state. */
98 if ((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) &&
99 (d6 == DR6_RESERVED) && (d7 == 0x400))
100 return;
101
102 printk("%sDR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
103 log_lvl, d0, d1, d2, d3);
104 printk("%sDR6: %08lx DR7: %08lx\n",
105 log_lvl, d6, d7);
106}
107
108void release_thread(struct task_struct *dead_task)
109{
110 BUG_ON(dead_task->mm);
111 release_vm86_irqs(dead_task);
112}
113
114void
115start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
116{
117 set_user_gs(regs, 0);
118 regs->fs = 0;
119 regs->ds = __USER_DS;
120 regs->es = __USER_DS;
121 regs->ss = __USER_DS;
122 regs->cs = __USER_CS;
123 regs->ip = new_ip;
124 regs->sp = new_sp;
125 regs->flags = X86_EFLAGS_IF;
126}
127EXPORT_SYMBOL_GPL(start_thread);
128
129
130/*
131 * switch_to(x,y) should switch tasks from x to y.
132 *
133 * We fsave/fwait so that an exception goes off at the right time
134 * (as a call from the fsave or fwait in effect) rather than to
135 * the wrong process. Lazy FP saving no longer makes any sense
136 * with modern CPU's, and this simplifies a lot of things (SMP
137 * and UP become the same).
138 *
139 * NOTE! We used to use the x86 hardware context switching. The
140 * reason for not using it any more becomes apparent when you
141 * try to recover gracefully from saved state that is no longer
142 * valid (stale segment register values in particular). With the
143 * hardware task-switch, there is no way to fix up bad state in
144 * a reasonable manner.
145 *
146 * The fact that Intel documents the hardware task-switching to
147 * be slow is a fairly red herring - this code is not noticeably
148 * faster. However, there _is_ some room for improvement here,
149 * so the performance issues may eventually be a valid point.
150 * More important, however, is the fact that this allows us much
151 * more flexibility.
152 *
153 * The return value (in %ax) will be the "prev" task after
154 * the task-switch, and shows up in ret_from_fork in entry.S,
155 * for example.
156 */
157__visible __notrace_funcgraph struct task_struct *
158__switch_to(struct task_struct *prev_p, struct task_struct *next_p)
159{
160 struct thread_struct *prev = &prev_p->thread,
161 *next = &next_p->thread;
162 struct fpu *prev_fpu = &prev->fpu;
163 struct fpu *next_fpu = &next->fpu;
164 int cpu = smp_processor_id();
165
166 /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */
167
168 if (!test_thread_flag(TIF_NEED_FPU_LOAD))
169 switch_fpu_prepare(prev_fpu, cpu);
170
171 /*
172 * Save away %gs. No need to save %fs, as it was saved on the
173 * stack on entry. No need to save %es and %ds, as those are
174 * always kernel segments while inside the kernel. Doing this
175 * before setting the new TLS descriptors avoids the situation
176 * where we temporarily have non-reloadable segments in %fs
177 * and %gs. This could be an issue if the NMI handler ever
178 * used %fs or %gs (it does not today), or if the kernel is
179 * running inside of a hypervisor layer.
180 */
181 lazy_save_gs(prev->gs);
182
183 /*
184 * Load the per-thread Thread-Local Storage descriptor.
185 */
186 load_TLS(next, cpu);
187
188 switch_to_extra(prev_p, next_p);
189
190 /*
191 * Leave lazy mode, flushing any hypercalls made here.
192 * This must be done before restoring TLS segments so
193 * the GDT and LDT are properly updated.
194 */
195 arch_end_context_switch(next_p);
196
197 /*
198 * Reload esp0 and cpu_current_top_of_stack. This changes
199 * current_thread_info(). Refresh the SYSENTER configuration in
200 * case prev or next is vm86.
201 */
202 update_task_stack(next_p);
203 refresh_sysenter_cs(next);
204 this_cpu_write(cpu_current_top_of_stack,
205 (unsigned long)task_stack_page(next_p) +
206 THREAD_SIZE);
207
208 /*
209 * Restore %gs if needed (which is common)
210 */
211 if (prev->gs | next->gs)
212 lazy_load_gs(next->gs);
213
214 this_cpu_write(current_task, next_p);
215
216 switch_fpu_finish(next_fpu);
217
218 /* Load the Intel cache allocation PQR MSR. */
219 resctrl_sched_in();
220
221 return prev_p;
222}
223
224SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2)
225{
226 return do_arch_prctl_common(current, option, arg2);
227}