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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
5
6#include <linux/module.h>
7#include <linux/types.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/vmalloc.h>
11#include <linux/pagemap.h>
12#include <linux/delay.h>
13#include <linux/netdevice.h>
14#include <linux/interrupt.h>
15#include <linux/tcp.h>
16#include <linux/ipv6.h>
17#include <linux/slab.h>
18#include <net/checksum.h>
19#include <net/ip6_checksum.h>
20#include <linux/ethtool.h>
21#include <linux/if_vlan.h>
22#include <linux/cpu.h>
23#include <linux/smp.h>
24#include <linux/pm_qos.h>
25#include <linux/pm_runtime.h>
26#include <linux/prefetch.h>
27#include <linux/suspend.h>
28
29#include "e1000.h"
30#define CREATE_TRACE_POINTS
31#include "e1000e_trace.h"
32
33char e1000e_driver_name[] = "e1000e";
34
35#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
36static int debug = -1;
37module_param(debug, int, 0);
38MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
39
40static const struct e1000_info *e1000_info_tbl[] = {
41 [board_82571] = &e1000_82571_info,
42 [board_82572] = &e1000_82572_info,
43 [board_82573] = &e1000_82573_info,
44 [board_82574] = &e1000_82574_info,
45 [board_82583] = &e1000_82583_info,
46 [board_80003es2lan] = &e1000_es2_info,
47 [board_ich8lan] = &e1000_ich8_info,
48 [board_ich9lan] = &e1000_ich9_info,
49 [board_ich10lan] = &e1000_ich10_info,
50 [board_pchlan] = &e1000_pch_info,
51 [board_pch2lan] = &e1000_pch2_info,
52 [board_pch_lpt] = &e1000_pch_lpt_info,
53 [board_pch_spt] = &e1000_pch_spt_info,
54 [board_pch_cnp] = &e1000_pch_cnp_info,
55 [board_pch_tgp] = &e1000_pch_tgp_info,
56 [board_pch_adp] = &e1000_pch_adp_info,
57 [board_pch_mtp] = &e1000_pch_mtp_info,
58};
59
60struct e1000_reg_info {
61 u32 ofs;
62 char *name;
63};
64
65static const struct e1000_reg_info e1000_reg_info_tbl[] = {
66 /* General Registers */
67 {E1000_CTRL, "CTRL"},
68 {E1000_STATUS, "STATUS"},
69 {E1000_CTRL_EXT, "CTRL_EXT"},
70
71 /* Interrupt Registers */
72 {E1000_ICR, "ICR"},
73
74 /* Rx Registers */
75 {E1000_RCTL, "RCTL"},
76 {E1000_RDLEN(0), "RDLEN"},
77 {E1000_RDH(0), "RDH"},
78 {E1000_RDT(0), "RDT"},
79 {E1000_RDTR, "RDTR"},
80 {E1000_RXDCTL(0), "RXDCTL"},
81 {E1000_ERT, "ERT"},
82 {E1000_RDBAL(0), "RDBAL"},
83 {E1000_RDBAH(0), "RDBAH"},
84 {E1000_RDFH, "RDFH"},
85 {E1000_RDFT, "RDFT"},
86 {E1000_RDFHS, "RDFHS"},
87 {E1000_RDFTS, "RDFTS"},
88 {E1000_RDFPC, "RDFPC"},
89
90 /* Tx Registers */
91 {E1000_TCTL, "TCTL"},
92 {E1000_TDBAL(0), "TDBAL"},
93 {E1000_TDBAH(0), "TDBAH"},
94 {E1000_TDLEN(0), "TDLEN"},
95 {E1000_TDH(0), "TDH"},
96 {E1000_TDT(0), "TDT"},
97 {E1000_TIDV, "TIDV"},
98 {E1000_TXDCTL(0), "TXDCTL"},
99 {E1000_TADV, "TADV"},
100 {E1000_TARC(0), "TARC"},
101 {E1000_TDFH, "TDFH"},
102 {E1000_TDFT, "TDFT"},
103 {E1000_TDFHS, "TDFHS"},
104 {E1000_TDFTS, "TDFTS"},
105 {E1000_TDFPC, "TDFPC"},
106
107 /* List Terminator */
108 {0, NULL}
109};
110
111/**
112 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
113 * @hw: pointer to the HW structure
114 *
115 * When updating the MAC CSR registers, the Manageability Engine (ME) could
116 * be accessing the registers at the same time. Normally, this is handled in
117 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
118 * accesses later than it should which could result in the register to have
119 * an incorrect value. Workaround this by checking the FWSM register which
120 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
121 * and try again a number of times.
122 **/
123static void __ew32_prepare(struct e1000_hw *hw)
124{
125 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
126
127 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
128 udelay(50);
129}
130
131void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
132{
133 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
134 __ew32_prepare(hw);
135
136 writel(val, hw->hw_addr + reg);
137}
138
139/**
140 * e1000_regdump - register printout routine
141 * @hw: pointer to the HW structure
142 * @reginfo: pointer to the register info table
143 **/
144static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
145{
146 int n = 0;
147 char rname[16];
148 u32 regs[8];
149
150 switch (reginfo->ofs) {
151 case E1000_RXDCTL(0):
152 for (n = 0; n < 2; n++)
153 regs[n] = __er32(hw, E1000_RXDCTL(n));
154 break;
155 case E1000_TXDCTL(0):
156 for (n = 0; n < 2; n++)
157 regs[n] = __er32(hw, E1000_TXDCTL(n));
158 break;
159 case E1000_TARC(0):
160 for (n = 0; n < 2; n++)
161 regs[n] = __er32(hw, E1000_TARC(n));
162 break;
163 default:
164 pr_info("%-15s %08x\n",
165 reginfo->name, __er32(hw, reginfo->ofs));
166 return;
167 }
168
169 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
170 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
171}
172
173static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
174 struct e1000_buffer *bi)
175{
176 int i;
177 struct e1000_ps_page *ps_page;
178
179 for (i = 0; i < adapter->rx_ps_pages; i++) {
180 ps_page = &bi->ps_pages[i];
181
182 if (ps_page->page) {
183 pr_info("packet dump for ps_page %d:\n", i);
184 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
185 16, 1, page_address(ps_page->page),
186 PAGE_SIZE, true);
187 }
188 }
189}
190
191/**
192 * e1000e_dump - Print registers, Tx-ring and Rx-ring
193 * @adapter: board private structure
194 **/
195static void e1000e_dump(struct e1000_adapter *adapter)
196{
197 struct net_device *netdev = adapter->netdev;
198 struct e1000_hw *hw = &adapter->hw;
199 struct e1000_reg_info *reginfo;
200 struct e1000_ring *tx_ring = adapter->tx_ring;
201 struct e1000_tx_desc *tx_desc;
202 struct my_u0 {
203 __le64 a;
204 __le64 b;
205 } *u0;
206 struct e1000_buffer *buffer_info;
207 struct e1000_ring *rx_ring = adapter->rx_ring;
208 union e1000_rx_desc_packet_split *rx_desc_ps;
209 union e1000_rx_desc_extended *rx_desc;
210 struct my_u1 {
211 __le64 a;
212 __le64 b;
213 __le64 c;
214 __le64 d;
215 } *u1;
216 u32 staterr;
217 int i = 0;
218
219 if (!netif_msg_hw(adapter))
220 return;
221
222 /* Print netdevice Info */
223 if (netdev) {
224 dev_info(&adapter->pdev->dev, "Net device Info\n");
225 pr_info("Device Name state trans_start\n");
226 pr_info("%-15s %016lX %016lX\n", netdev->name,
227 netdev->state, dev_trans_start(netdev));
228 }
229
230 /* Print Registers */
231 dev_info(&adapter->pdev->dev, "Register Dump\n");
232 pr_info(" Register Name Value\n");
233 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
234 reginfo->name; reginfo++) {
235 e1000_regdump(hw, reginfo);
236 }
237
238 /* Print Tx Ring Summary */
239 if (!netdev || !netif_running(netdev))
240 return;
241
242 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
243 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
244 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
245 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
246 0, tx_ring->next_to_use, tx_ring->next_to_clean,
247 (unsigned long long)buffer_info->dma,
248 buffer_info->length,
249 buffer_info->next_to_watch,
250 (unsigned long long)buffer_info->time_stamp);
251
252 /* Print Tx Ring */
253 if (!netif_msg_tx_done(adapter))
254 goto rx_ring_summary;
255
256 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
257
258 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
259 *
260 * Legacy Transmit Descriptor
261 * +--------------------------------------------------------------+
262 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
263 * +--------------------------------------------------------------+
264 * 8 | Special | CSS | Status | CMD | CSO | Length |
265 * +--------------------------------------------------------------+
266 * 63 48 47 36 35 32 31 24 23 16 15 0
267 *
268 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
269 * 63 48 47 40 39 32 31 16 15 8 7 0
270 * +----------------------------------------------------------------+
271 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
272 * +----------------------------------------------------------------+
273 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
274 * +----------------------------------------------------------------+
275 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
276 *
277 * Extended Data Descriptor (DTYP=0x1)
278 * +----------------------------------------------------------------+
279 * 0 | Buffer Address [63:0] |
280 * +----------------------------------------------------------------+
281 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
282 * +----------------------------------------------------------------+
283 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
284 */
285 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
286 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
287 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
288 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
289 const char *next_desc;
290 tx_desc = E1000_TX_DESC(*tx_ring, i);
291 buffer_info = &tx_ring->buffer_info[i];
292 u0 = (struct my_u0 *)tx_desc;
293 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
294 next_desc = " NTC/U";
295 else if (i == tx_ring->next_to_use)
296 next_desc = " NTU";
297 else if (i == tx_ring->next_to_clean)
298 next_desc = " NTC";
299 else
300 next_desc = "";
301 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
302 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' :
303 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')),
304 i,
305 (unsigned long long)le64_to_cpu(u0->a),
306 (unsigned long long)le64_to_cpu(u0->b),
307 (unsigned long long)buffer_info->dma,
308 buffer_info->length, buffer_info->next_to_watch,
309 (unsigned long long)buffer_info->time_stamp,
310 buffer_info->skb, next_desc);
311
312 if (netif_msg_pktdata(adapter) && buffer_info->skb)
313 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
314 16, 1, buffer_info->skb->data,
315 buffer_info->skb->len, true);
316 }
317
318 /* Print Rx Ring Summary */
319rx_ring_summary:
320 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
321 pr_info("Queue [NTU] [NTC]\n");
322 pr_info(" %5d %5X %5X\n",
323 0, rx_ring->next_to_use, rx_ring->next_to_clean);
324
325 /* Print Rx Ring */
326 if (!netif_msg_rx_status(adapter))
327 return;
328
329 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
330 switch (adapter->rx_ps_pages) {
331 case 1:
332 case 2:
333 case 3:
334 /* [Extended] Packet Split Receive Descriptor Format
335 *
336 * +-----------------------------------------------------+
337 * 0 | Buffer Address 0 [63:0] |
338 * +-----------------------------------------------------+
339 * 8 | Buffer Address 1 [63:0] |
340 * +-----------------------------------------------------+
341 * 16 | Buffer Address 2 [63:0] |
342 * +-----------------------------------------------------+
343 * 24 | Buffer Address 3 [63:0] |
344 * +-----------------------------------------------------+
345 */
346 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
347 /* [Extended] Receive Descriptor (Write-Back) Format
348 *
349 * 63 48 47 32 31 13 12 8 7 4 3 0
350 * +------------------------------------------------------+
351 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
352 * | Checksum | Ident | | Queue | | Type |
353 * +------------------------------------------------------+
354 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
355 * +------------------------------------------------------+
356 * 63 48 47 32 31 20 19 0
357 */
358 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
359 for (i = 0; i < rx_ring->count; i++) {
360 const char *next_desc;
361 buffer_info = &rx_ring->buffer_info[i];
362 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
363 u1 = (struct my_u1 *)rx_desc_ps;
364 staterr =
365 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
366
367 if (i == rx_ring->next_to_use)
368 next_desc = " NTU";
369 else if (i == rx_ring->next_to_clean)
370 next_desc = " NTC";
371 else
372 next_desc = "";
373
374 if (staterr & E1000_RXD_STAT_DD) {
375 /* Descriptor Done */
376 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
377 "RWB", i,
378 (unsigned long long)le64_to_cpu(u1->a),
379 (unsigned long long)le64_to_cpu(u1->b),
380 (unsigned long long)le64_to_cpu(u1->c),
381 (unsigned long long)le64_to_cpu(u1->d),
382 buffer_info->skb, next_desc);
383 } else {
384 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
385 "R ", i,
386 (unsigned long long)le64_to_cpu(u1->a),
387 (unsigned long long)le64_to_cpu(u1->b),
388 (unsigned long long)le64_to_cpu(u1->c),
389 (unsigned long long)le64_to_cpu(u1->d),
390 (unsigned long long)buffer_info->dma,
391 buffer_info->skb, next_desc);
392
393 if (netif_msg_pktdata(adapter))
394 e1000e_dump_ps_pages(adapter,
395 buffer_info);
396 }
397 }
398 break;
399 default:
400 case 0:
401 /* Extended Receive Descriptor (Read) Format
402 *
403 * +-----------------------------------------------------+
404 * 0 | Buffer Address [63:0] |
405 * +-----------------------------------------------------+
406 * 8 | Reserved |
407 * +-----------------------------------------------------+
408 */
409 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
410 /* Extended Receive Descriptor (Write-Back) Format
411 *
412 * 63 48 47 32 31 24 23 4 3 0
413 * +------------------------------------------------------+
414 * | RSS Hash | | | |
415 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
416 * | Packet | IP | | | Type |
417 * | Checksum | Ident | | | |
418 * +------------------------------------------------------+
419 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
420 * +------------------------------------------------------+
421 * 63 48 47 32 31 20 19 0
422 */
423 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
424
425 for (i = 0; i < rx_ring->count; i++) {
426 const char *next_desc;
427
428 buffer_info = &rx_ring->buffer_info[i];
429 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
430 u1 = (struct my_u1 *)rx_desc;
431 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
432
433 if (i == rx_ring->next_to_use)
434 next_desc = " NTU";
435 else if (i == rx_ring->next_to_clean)
436 next_desc = " NTC";
437 else
438 next_desc = "";
439
440 if (staterr & E1000_RXD_STAT_DD) {
441 /* Descriptor Done */
442 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
443 "RWB", i,
444 (unsigned long long)le64_to_cpu(u1->a),
445 (unsigned long long)le64_to_cpu(u1->b),
446 buffer_info->skb, next_desc);
447 } else {
448 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
449 "R ", i,
450 (unsigned long long)le64_to_cpu(u1->a),
451 (unsigned long long)le64_to_cpu(u1->b),
452 (unsigned long long)buffer_info->dma,
453 buffer_info->skb, next_desc);
454
455 if (netif_msg_pktdata(adapter) &&
456 buffer_info->skb)
457 print_hex_dump(KERN_INFO, "",
458 DUMP_PREFIX_ADDRESS, 16,
459 1,
460 buffer_info->skb->data,
461 adapter->rx_buffer_len,
462 true);
463 }
464 }
465 }
466}
467
468/**
469 * e1000_desc_unused - calculate if we have unused descriptors
470 * @ring: pointer to ring struct to perform calculation on
471 **/
472static int e1000_desc_unused(struct e1000_ring *ring)
473{
474 if (ring->next_to_clean > ring->next_to_use)
475 return ring->next_to_clean - ring->next_to_use - 1;
476
477 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
478}
479
480/**
481 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
482 * @adapter: board private structure
483 * @hwtstamps: time stamp structure to update
484 * @systim: unsigned 64bit system time value.
485 *
486 * Convert the system time value stored in the RX/TXSTMP registers into a
487 * hwtstamp which can be used by the upper level time stamping functions.
488 *
489 * The 'systim_lock' spinlock is used to protect the consistency of the
490 * system time value. This is needed because reading the 64 bit time
491 * value involves reading two 32 bit registers. The first read latches the
492 * value.
493 **/
494static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
495 struct skb_shared_hwtstamps *hwtstamps,
496 u64 systim)
497{
498 u64 ns;
499 unsigned long flags;
500
501 spin_lock_irqsave(&adapter->systim_lock, flags);
502 ns = timecounter_cyc2time(&adapter->tc, systim);
503 spin_unlock_irqrestore(&adapter->systim_lock, flags);
504
505 memset(hwtstamps, 0, sizeof(*hwtstamps));
506 hwtstamps->hwtstamp = ns_to_ktime(ns);
507}
508
509/**
510 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
511 * @adapter: board private structure
512 * @status: descriptor extended error and status field
513 * @skb: particular skb to include time stamp
514 *
515 * If the time stamp is valid, convert it into the timecounter ns value
516 * and store that result into the shhwtstamps structure which is passed
517 * up the network stack.
518 **/
519static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
520 struct sk_buff *skb)
521{
522 struct e1000_hw *hw = &adapter->hw;
523 u64 rxstmp;
524
525 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
526 !(status & E1000_RXDEXT_STATERR_TST) ||
527 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
528 return;
529
530 /* The Rx time stamp registers contain the time stamp. No other
531 * received packet will be time stamped until the Rx time stamp
532 * registers are read. Because only one packet can be time stamped
533 * at a time, the register values must belong to this packet and
534 * therefore none of the other additional attributes need to be
535 * compared.
536 */
537 rxstmp = (u64)er32(RXSTMPL);
538 rxstmp |= (u64)er32(RXSTMPH) << 32;
539 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
540
541 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
542}
543
544/**
545 * e1000_receive_skb - helper function to handle Rx indications
546 * @adapter: board private structure
547 * @netdev: pointer to netdev struct
548 * @staterr: descriptor extended error and status field as written by hardware
549 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
550 * @skb: pointer to sk_buff to be indicated to stack
551 **/
552static void e1000_receive_skb(struct e1000_adapter *adapter,
553 struct net_device *netdev, struct sk_buff *skb,
554 u32 staterr, __le16 vlan)
555{
556 u16 tag = le16_to_cpu(vlan);
557
558 e1000e_rx_hwtstamp(adapter, staterr, skb);
559
560 skb->protocol = eth_type_trans(skb, netdev);
561
562 if (staterr & E1000_RXD_STAT_VP)
563 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
564
565 napi_gro_receive(&adapter->napi, skb);
566}
567
568/**
569 * e1000_rx_checksum - Receive Checksum Offload
570 * @adapter: board private structure
571 * @status_err: receive descriptor status and error fields
572 * @skb: socket buffer with received data
573 **/
574static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
575 struct sk_buff *skb)
576{
577 u16 status = (u16)status_err;
578 u8 errors = (u8)(status_err >> 24);
579
580 skb_checksum_none_assert(skb);
581
582 /* Rx checksum disabled */
583 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
584 return;
585
586 /* Ignore Checksum bit is set */
587 if (status & E1000_RXD_STAT_IXSM)
588 return;
589
590 /* TCP/UDP checksum error bit or IP checksum error bit is set */
591 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
592 /* let the stack verify checksum errors */
593 adapter->hw_csum_err++;
594 return;
595 }
596
597 /* TCP/UDP Checksum has not been calculated */
598 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
599 return;
600
601 /* It must be a TCP or UDP packet with a valid checksum */
602 skb->ip_summed = CHECKSUM_UNNECESSARY;
603 adapter->hw_csum_good++;
604}
605
606static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
607{
608 struct e1000_adapter *adapter = rx_ring->adapter;
609 struct e1000_hw *hw = &adapter->hw;
610
611 __ew32_prepare(hw);
612 writel(i, rx_ring->tail);
613
614 if (unlikely(i != readl(rx_ring->tail))) {
615 u32 rctl = er32(RCTL);
616
617 ew32(RCTL, rctl & ~E1000_RCTL_EN);
618 e_err("ME firmware caused invalid RDT - resetting\n");
619 schedule_work(&adapter->reset_task);
620 }
621}
622
623static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
624{
625 struct e1000_adapter *adapter = tx_ring->adapter;
626 struct e1000_hw *hw = &adapter->hw;
627
628 __ew32_prepare(hw);
629 writel(i, tx_ring->tail);
630
631 if (unlikely(i != readl(tx_ring->tail))) {
632 u32 tctl = er32(TCTL);
633
634 ew32(TCTL, tctl & ~E1000_TCTL_EN);
635 e_err("ME firmware caused invalid TDT - resetting\n");
636 schedule_work(&adapter->reset_task);
637 }
638}
639
640/**
641 * e1000_alloc_rx_buffers - Replace used receive buffers
642 * @rx_ring: Rx descriptor ring
643 * @cleaned_count: number to reallocate
644 * @gfp: flags for allocation
645 **/
646static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
647 int cleaned_count, gfp_t gfp)
648{
649 struct e1000_adapter *adapter = rx_ring->adapter;
650 struct net_device *netdev = adapter->netdev;
651 struct pci_dev *pdev = adapter->pdev;
652 union e1000_rx_desc_extended *rx_desc;
653 struct e1000_buffer *buffer_info;
654 struct sk_buff *skb;
655 unsigned int i;
656 unsigned int bufsz = adapter->rx_buffer_len;
657
658 i = rx_ring->next_to_use;
659 buffer_info = &rx_ring->buffer_info[i];
660
661 while (cleaned_count--) {
662 skb = buffer_info->skb;
663 if (skb) {
664 skb_trim(skb, 0);
665 goto map_skb;
666 }
667
668 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
669 if (!skb) {
670 /* Better luck next round */
671 adapter->alloc_rx_buff_failed++;
672 break;
673 }
674
675 buffer_info->skb = skb;
676map_skb:
677 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
678 adapter->rx_buffer_len,
679 DMA_FROM_DEVICE);
680 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
681 dev_err(&pdev->dev, "Rx DMA map failed\n");
682 adapter->rx_dma_failed++;
683 break;
684 }
685
686 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
687 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
688
689 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
690 /* Force memory writes to complete before letting h/w
691 * know there are new descriptors to fetch. (Only
692 * applicable for weak-ordered memory model archs,
693 * such as IA-64).
694 */
695 wmb();
696 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
697 e1000e_update_rdt_wa(rx_ring, i);
698 else
699 writel(i, rx_ring->tail);
700 }
701 i++;
702 if (i == rx_ring->count)
703 i = 0;
704 buffer_info = &rx_ring->buffer_info[i];
705 }
706
707 rx_ring->next_to_use = i;
708}
709
710/**
711 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
712 * @rx_ring: Rx descriptor ring
713 * @cleaned_count: number to reallocate
714 * @gfp: flags for allocation
715 **/
716static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
717 int cleaned_count, gfp_t gfp)
718{
719 struct e1000_adapter *adapter = rx_ring->adapter;
720 struct net_device *netdev = adapter->netdev;
721 struct pci_dev *pdev = adapter->pdev;
722 union e1000_rx_desc_packet_split *rx_desc;
723 struct e1000_buffer *buffer_info;
724 struct e1000_ps_page *ps_page;
725 struct sk_buff *skb;
726 unsigned int i, j;
727
728 i = rx_ring->next_to_use;
729 buffer_info = &rx_ring->buffer_info[i];
730
731 while (cleaned_count--) {
732 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
733
734 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
735 ps_page = &buffer_info->ps_pages[j];
736 if (j >= adapter->rx_ps_pages) {
737 /* all unused desc entries get hw null ptr */
738 rx_desc->read.buffer_addr[j + 1] =
739 ~cpu_to_le64(0);
740 continue;
741 }
742 if (!ps_page->page) {
743 ps_page->page = alloc_page(gfp);
744 if (!ps_page->page) {
745 adapter->alloc_rx_buff_failed++;
746 goto no_buffers;
747 }
748 ps_page->dma = dma_map_page(&pdev->dev,
749 ps_page->page,
750 0, PAGE_SIZE,
751 DMA_FROM_DEVICE);
752 if (dma_mapping_error(&pdev->dev,
753 ps_page->dma)) {
754 dev_err(&adapter->pdev->dev,
755 "Rx DMA page map failed\n");
756 adapter->rx_dma_failed++;
757 goto no_buffers;
758 }
759 }
760 /* Refresh the desc even if buffer_addrs
761 * didn't change because each write-back
762 * erases this info.
763 */
764 rx_desc->read.buffer_addr[j + 1] =
765 cpu_to_le64(ps_page->dma);
766 }
767
768 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
769 gfp);
770
771 if (!skb) {
772 adapter->alloc_rx_buff_failed++;
773 break;
774 }
775
776 buffer_info->skb = skb;
777 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
778 adapter->rx_ps_bsize0,
779 DMA_FROM_DEVICE);
780 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
781 dev_err(&pdev->dev, "Rx DMA map failed\n");
782 adapter->rx_dma_failed++;
783 /* cleanup skb */
784 dev_kfree_skb_any(skb);
785 buffer_info->skb = NULL;
786 break;
787 }
788
789 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
790
791 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
792 /* Force memory writes to complete before letting h/w
793 * know there are new descriptors to fetch. (Only
794 * applicable for weak-ordered memory model archs,
795 * such as IA-64).
796 */
797 wmb();
798 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
799 e1000e_update_rdt_wa(rx_ring, i << 1);
800 else
801 writel(i << 1, rx_ring->tail);
802 }
803
804 i++;
805 if (i == rx_ring->count)
806 i = 0;
807 buffer_info = &rx_ring->buffer_info[i];
808 }
809
810no_buffers:
811 rx_ring->next_to_use = i;
812}
813
814/**
815 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
816 * @rx_ring: Rx descriptor ring
817 * @cleaned_count: number of buffers to allocate this pass
818 * @gfp: flags for allocation
819 **/
820
821static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
822 int cleaned_count, gfp_t gfp)
823{
824 struct e1000_adapter *adapter = rx_ring->adapter;
825 struct net_device *netdev = adapter->netdev;
826 struct pci_dev *pdev = adapter->pdev;
827 union e1000_rx_desc_extended *rx_desc;
828 struct e1000_buffer *buffer_info;
829 struct sk_buff *skb;
830 unsigned int i;
831 unsigned int bufsz = 256 - 16; /* for skb_reserve */
832
833 i = rx_ring->next_to_use;
834 buffer_info = &rx_ring->buffer_info[i];
835
836 while (cleaned_count--) {
837 skb = buffer_info->skb;
838 if (skb) {
839 skb_trim(skb, 0);
840 goto check_page;
841 }
842
843 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
844 if (unlikely(!skb)) {
845 /* Better luck next round */
846 adapter->alloc_rx_buff_failed++;
847 break;
848 }
849
850 buffer_info->skb = skb;
851check_page:
852 /* allocate a new page if necessary */
853 if (!buffer_info->page) {
854 buffer_info->page = alloc_page(gfp);
855 if (unlikely(!buffer_info->page)) {
856 adapter->alloc_rx_buff_failed++;
857 break;
858 }
859 }
860
861 if (!buffer_info->dma) {
862 buffer_info->dma = dma_map_page(&pdev->dev,
863 buffer_info->page, 0,
864 PAGE_SIZE,
865 DMA_FROM_DEVICE);
866 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
867 adapter->alloc_rx_buff_failed++;
868 break;
869 }
870 }
871
872 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
873 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
874
875 if (unlikely(++i == rx_ring->count))
876 i = 0;
877 buffer_info = &rx_ring->buffer_info[i];
878 }
879
880 if (likely(rx_ring->next_to_use != i)) {
881 rx_ring->next_to_use = i;
882 if (unlikely(i-- == 0))
883 i = (rx_ring->count - 1);
884
885 /* Force memory writes to complete before letting h/w
886 * know there are new descriptors to fetch. (Only
887 * applicable for weak-ordered memory model archs,
888 * such as IA-64).
889 */
890 wmb();
891 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
892 e1000e_update_rdt_wa(rx_ring, i);
893 else
894 writel(i, rx_ring->tail);
895 }
896}
897
898static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
899 struct sk_buff *skb)
900{
901 if (netdev->features & NETIF_F_RXHASH)
902 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3);
903}
904
905/**
906 * e1000_clean_rx_irq - Send received data up the network stack
907 * @rx_ring: Rx descriptor ring
908 * @work_done: output parameter for indicating completed work
909 * @work_to_do: how many packets we can clean
910 *
911 * the return value indicates whether actual cleaning was done, there
912 * is no guarantee that everything was cleaned
913 **/
914static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
915 int work_to_do)
916{
917 struct e1000_adapter *adapter = rx_ring->adapter;
918 struct net_device *netdev = adapter->netdev;
919 struct pci_dev *pdev = adapter->pdev;
920 struct e1000_hw *hw = &adapter->hw;
921 union e1000_rx_desc_extended *rx_desc, *next_rxd;
922 struct e1000_buffer *buffer_info, *next_buffer;
923 u32 length, staterr;
924 unsigned int i;
925 int cleaned_count = 0;
926 bool cleaned = false;
927 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
928
929 i = rx_ring->next_to_clean;
930 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
931 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
932 buffer_info = &rx_ring->buffer_info[i];
933
934 while (staterr & E1000_RXD_STAT_DD) {
935 struct sk_buff *skb;
936
937 if (*work_done >= work_to_do)
938 break;
939 (*work_done)++;
940 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
941
942 skb = buffer_info->skb;
943 buffer_info->skb = NULL;
944
945 prefetch(skb->data - NET_IP_ALIGN);
946
947 i++;
948 if (i == rx_ring->count)
949 i = 0;
950 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
951 prefetch(next_rxd);
952
953 next_buffer = &rx_ring->buffer_info[i];
954
955 cleaned = true;
956 cleaned_count++;
957 dma_unmap_single(&pdev->dev, buffer_info->dma,
958 adapter->rx_buffer_len, DMA_FROM_DEVICE);
959 buffer_info->dma = 0;
960
961 length = le16_to_cpu(rx_desc->wb.upper.length);
962
963 /* !EOP means multiple descriptors were used to store a single
964 * packet, if that's the case we need to toss it. In fact, we
965 * need to toss every packet with the EOP bit clear and the
966 * next frame that _does_ have the EOP bit set, as it is by
967 * definition only a frame fragment
968 */
969 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
970 adapter->flags2 |= FLAG2_IS_DISCARDING;
971
972 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
973 /* All receives must fit into a single buffer */
974 e_dbg("Receive packet consumed multiple buffers\n");
975 /* recycle */
976 buffer_info->skb = skb;
977 if (staterr & E1000_RXD_STAT_EOP)
978 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
979 goto next_desc;
980 }
981
982 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
983 !(netdev->features & NETIF_F_RXALL))) {
984 /* recycle */
985 buffer_info->skb = skb;
986 goto next_desc;
987 }
988
989 /* adjust length to remove Ethernet CRC */
990 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
991 /* If configured to store CRC, don't subtract FCS,
992 * but keep the FCS bytes out of the total_rx_bytes
993 * counter
994 */
995 if (netdev->features & NETIF_F_RXFCS)
996 total_rx_bytes -= 4;
997 else
998 length -= 4;
999 }
1000
1001 total_rx_bytes += length;
1002 total_rx_packets++;
1003
1004 /* code added for copybreak, this should improve
1005 * performance for small packets with large amounts
1006 * of reassembly being done in the stack
1007 */
1008 if (length < copybreak) {
1009 struct sk_buff *new_skb =
1010 napi_alloc_skb(&adapter->napi, length);
1011 if (new_skb) {
1012 skb_copy_to_linear_data_offset(new_skb,
1013 -NET_IP_ALIGN,
1014 (skb->data -
1015 NET_IP_ALIGN),
1016 (length +
1017 NET_IP_ALIGN));
1018 /* save the skb in buffer_info as good */
1019 buffer_info->skb = skb;
1020 skb = new_skb;
1021 }
1022 /* else just continue with the old one */
1023 }
1024 /* end copybreak code */
1025 skb_put(skb, length);
1026
1027 /* Receive Checksum Offload */
1028 e1000_rx_checksum(adapter, staterr, skb);
1029
1030 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1031
1032 e1000_receive_skb(adapter, netdev, skb, staterr,
1033 rx_desc->wb.upper.vlan);
1034
1035next_desc:
1036 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1037
1038 /* return some buffers to hardware, one at a time is too slow */
1039 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1040 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1041 GFP_ATOMIC);
1042 cleaned_count = 0;
1043 }
1044
1045 /* use prefetched values */
1046 rx_desc = next_rxd;
1047 buffer_info = next_buffer;
1048
1049 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1050 }
1051 rx_ring->next_to_clean = i;
1052
1053 cleaned_count = e1000_desc_unused(rx_ring);
1054 if (cleaned_count)
1055 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1056
1057 adapter->total_rx_bytes += total_rx_bytes;
1058 adapter->total_rx_packets += total_rx_packets;
1059 return cleaned;
1060}
1061
1062static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1063 struct e1000_buffer *buffer_info,
1064 bool drop)
1065{
1066 struct e1000_adapter *adapter = tx_ring->adapter;
1067
1068 if (buffer_info->dma) {
1069 if (buffer_info->mapped_as_page)
1070 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1071 buffer_info->length, DMA_TO_DEVICE);
1072 else
1073 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1074 buffer_info->length, DMA_TO_DEVICE);
1075 buffer_info->dma = 0;
1076 }
1077 if (buffer_info->skb) {
1078 if (drop)
1079 dev_kfree_skb_any(buffer_info->skb);
1080 else
1081 dev_consume_skb_any(buffer_info->skb);
1082 buffer_info->skb = NULL;
1083 }
1084 buffer_info->time_stamp = 0;
1085}
1086
1087static void e1000_print_hw_hang(struct work_struct *work)
1088{
1089 struct e1000_adapter *adapter = container_of(work,
1090 struct e1000_adapter,
1091 print_hang_task);
1092 struct net_device *netdev = adapter->netdev;
1093 struct e1000_ring *tx_ring = adapter->tx_ring;
1094 unsigned int i = tx_ring->next_to_clean;
1095 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1096 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
1097 struct e1000_hw *hw = &adapter->hw;
1098 u16 phy_status, phy_1000t_status, phy_ext_status;
1099 u16 pci_status;
1100
1101 if (test_bit(__E1000_DOWN, &adapter->state))
1102 return;
1103
1104 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
1105 /* May be block on write-back, flush and detect again
1106 * flush pending descriptor writebacks to memory
1107 */
1108 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1109 /* execute the writes immediately */
1110 e1e_flush();
1111 /* Due to rare timing issues, write to TIDV again to ensure
1112 * the write is successful
1113 */
1114 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1115 /* execute the writes immediately */
1116 e1e_flush();
1117 adapter->tx_hang_recheck = true;
1118 return;
1119 }
1120 adapter->tx_hang_recheck = false;
1121
1122 if (er32(TDH(0)) == er32(TDT(0))) {
1123 e_dbg("false hang detected, ignoring\n");
1124 return;
1125 }
1126
1127 /* Real hang detected */
1128 netif_stop_queue(netdev);
1129
1130 e1e_rphy(hw, MII_BMSR, &phy_status);
1131 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1132 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
1133
1134 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1135
1136 /* detected Hardware unit hang */
1137 e_err("Detected Hardware Unit Hang:\n"
1138 " TDH <%x>\n"
1139 " TDT <%x>\n"
1140 " next_to_use <%x>\n"
1141 " next_to_clean <%x>\n"
1142 "buffer_info[next_to_clean]:\n"
1143 " time_stamp <%lx>\n"
1144 " next_to_watch <%x>\n"
1145 " jiffies <%lx>\n"
1146 " next_to_watch.status <%x>\n"
1147 "MAC Status <%x>\n"
1148 "PHY Status <%x>\n"
1149 "PHY 1000BASE-T Status <%x>\n"
1150 "PHY Extended Status <%x>\n"
1151 "PCI Status <%x>\n",
1152 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1153 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1154 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1155 phy_status, phy_1000t_status, phy_ext_status, pci_status);
1156
1157 e1000e_dump(adapter);
1158
1159 /* Suggest workaround for known h/w issue */
1160 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1161 e_err("Try turning off Tx pause (flow control) via ethtool\n");
1162}
1163
1164/**
1165 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1166 * @work: pointer to work struct
1167 *
1168 * This work function polls the TSYNCTXCTL valid bit to determine when a
1169 * timestamp has been taken for the current stored skb. The timestamp must
1170 * be for this skb because only one such packet is allowed in the queue.
1171 */
1172static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1173{
1174 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1175 tx_hwtstamp_work);
1176 struct e1000_hw *hw = &adapter->hw;
1177
1178 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1179 struct sk_buff *skb = adapter->tx_hwtstamp_skb;
1180 struct skb_shared_hwtstamps shhwtstamps;
1181 u64 txstmp;
1182
1183 txstmp = er32(TXSTMPL);
1184 txstmp |= (u64)er32(TXSTMPH) << 32;
1185
1186 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1187
1188 /* Clear the global tx_hwtstamp_skb pointer and force writes
1189 * prior to notifying the stack of a Tx timestamp.
1190 */
1191 adapter->tx_hwtstamp_skb = NULL;
1192 wmb(); /* force write prior to skb_tstamp_tx */
1193
1194 skb_tstamp_tx(skb, &shhwtstamps);
1195 dev_consume_skb_any(skb);
1196 } else if (time_after(jiffies, adapter->tx_hwtstamp_start
1197 + adapter->tx_timeout_factor * HZ)) {
1198 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1199 adapter->tx_hwtstamp_skb = NULL;
1200 adapter->tx_hwtstamp_timeouts++;
1201 e_warn("clearing Tx timestamp hang\n");
1202 } else {
1203 /* reschedule to check later */
1204 schedule_work(&adapter->tx_hwtstamp_work);
1205 }
1206}
1207
1208/**
1209 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1210 * @tx_ring: Tx descriptor ring
1211 *
1212 * the return value indicates whether actual cleaning was done, there
1213 * is no guarantee that everything was cleaned
1214 **/
1215static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
1216{
1217 struct e1000_adapter *adapter = tx_ring->adapter;
1218 struct net_device *netdev = adapter->netdev;
1219 struct e1000_hw *hw = &adapter->hw;
1220 struct e1000_tx_desc *tx_desc, *eop_desc;
1221 struct e1000_buffer *buffer_info;
1222 unsigned int i, eop;
1223 unsigned int count = 0;
1224 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
1225 unsigned int bytes_compl = 0, pkts_compl = 0;
1226
1227 i = tx_ring->next_to_clean;
1228 eop = tx_ring->buffer_info[i].next_to_watch;
1229 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1230
1231 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1232 (count < tx_ring->count)) {
1233 bool cleaned = false;
1234
1235 dma_rmb(); /* read buffer_info after eop_desc */
1236 for (; !cleaned; count++) {
1237 tx_desc = E1000_TX_DESC(*tx_ring, i);
1238 buffer_info = &tx_ring->buffer_info[i];
1239 cleaned = (i == eop);
1240
1241 if (cleaned) {
1242 total_tx_packets += buffer_info->segs;
1243 total_tx_bytes += buffer_info->bytecount;
1244 if (buffer_info->skb) {
1245 bytes_compl += buffer_info->skb->len;
1246 pkts_compl++;
1247 }
1248 }
1249
1250 e1000_put_txbuf(tx_ring, buffer_info, false);
1251 tx_desc->upper.data = 0;
1252
1253 i++;
1254 if (i == tx_ring->count)
1255 i = 0;
1256 }
1257
1258 if (i == tx_ring->next_to_use)
1259 break;
1260 eop = tx_ring->buffer_info[i].next_to_watch;
1261 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1262 }
1263
1264 tx_ring->next_to_clean = i;
1265
1266 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1267
1268#define TX_WAKE_THRESHOLD 32
1269 if (count && netif_carrier_ok(netdev) &&
1270 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
1271 /* Make sure that anybody stopping the queue after this
1272 * sees the new next_to_clean.
1273 */
1274 smp_mb();
1275
1276 if (netif_queue_stopped(netdev) &&
1277 !(test_bit(__E1000_DOWN, &adapter->state))) {
1278 netif_wake_queue(netdev);
1279 ++adapter->restart_queue;
1280 }
1281 }
1282
1283 if (adapter->detect_tx_hung) {
1284 /* Detect a transmit hang in hardware, this serializes the
1285 * check with the clearing of time_stamp and movement of i
1286 */
1287 adapter->detect_tx_hung = false;
1288 if (tx_ring->buffer_info[i].time_stamp &&
1289 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
1290 + (adapter->tx_timeout_factor * HZ)) &&
1291 !(er32(STATUS) & E1000_STATUS_TXOFF))
1292 schedule_work(&adapter->print_hang_task);
1293 else
1294 adapter->tx_hang_recheck = false;
1295 }
1296 adapter->total_tx_bytes += total_tx_bytes;
1297 adapter->total_tx_packets += total_tx_packets;
1298 return count < tx_ring->count;
1299}
1300
1301/**
1302 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1303 * @rx_ring: Rx descriptor ring
1304 * @work_done: output parameter for indicating completed work
1305 * @work_to_do: how many packets we can clean
1306 *
1307 * the return value indicates whether actual cleaning was done, there
1308 * is no guarantee that everything was cleaned
1309 **/
1310static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1311 int work_to_do)
1312{
1313 struct e1000_adapter *adapter = rx_ring->adapter;
1314 struct e1000_hw *hw = &adapter->hw;
1315 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1316 struct net_device *netdev = adapter->netdev;
1317 struct pci_dev *pdev = adapter->pdev;
1318 struct e1000_buffer *buffer_info, *next_buffer;
1319 struct e1000_ps_page *ps_page;
1320 struct sk_buff *skb;
1321 unsigned int i, j;
1322 u32 length, staterr;
1323 int cleaned_count = 0;
1324 bool cleaned = false;
1325 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1326
1327 i = rx_ring->next_to_clean;
1328 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1329 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1330 buffer_info = &rx_ring->buffer_info[i];
1331
1332 while (staterr & E1000_RXD_STAT_DD) {
1333 if (*work_done >= work_to_do)
1334 break;
1335 (*work_done)++;
1336 skb = buffer_info->skb;
1337 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1338
1339 /* in the packet split case this is header only */
1340 prefetch(skb->data - NET_IP_ALIGN);
1341
1342 i++;
1343 if (i == rx_ring->count)
1344 i = 0;
1345 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1346 prefetch(next_rxd);
1347
1348 next_buffer = &rx_ring->buffer_info[i];
1349
1350 cleaned = true;
1351 cleaned_count++;
1352 dma_unmap_single(&pdev->dev, buffer_info->dma,
1353 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
1354 buffer_info->dma = 0;
1355
1356 /* see !EOP comment in other Rx routine */
1357 if (!(staterr & E1000_RXD_STAT_EOP))
1358 adapter->flags2 |= FLAG2_IS_DISCARDING;
1359
1360 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
1361 e_dbg("Packet Split buffers didn't pick up the full packet\n");
1362 dev_kfree_skb_irq(skb);
1363 if (staterr & E1000_RXD_STAT_EOP)
1364 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1365 goto next_desc;
1366 }
1367
1368 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1369 !(netdev->features & NETIF_F_RXALL))) {
1370 dev_kfree_skb_irq(skb);
1371 goto next_desc;
1372 }
1373
1374 length = le16_to_cpu(rx_desc->wb.middle.length0);
1375
1376 if (!length) {
1377 e_dbg("Last part of the packet spanning multiple descriptors\n");
1378 dev_kfree_skb_irq(skb);
1379 goto next_desc;
1380 }
1381
1382 /* Good Receive */
1383 skb_put(skb, length);
1384
1385 {
1386 /* this looks ugly, but it seems compiler issues make
1387 * it more efficient than reusing j
1388 */
1389 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
1390
1391 /* page alloc/put takes too long and effects small
1392 * packet throughput, so unsplit small packets and
1393 * save the alloc/put
1394 */
1395 if (l1 && (l1 <= copybreak) &&
1396 ((length + l1) <= adapter->rx_ps_bsize0)) {
1397 ps_page = &buffer_info->ps_pages[0];
1398
1399 dma_sync_single_for_cpu(&pdev->dev,
1400 ps_page->dma,
1401 PAGE_SIZE,
1402 DMA_FROM_DEVICE);
1403 memcpy(skb_tail_pointer(skb),
1404 page_address(ps_page->page), l1);
1405 dma_sync_single_for_device(&pdev->dev,
1406 ps_page->dma,
1407 PAGE_SIZE,
1408 DMA_FROM_DEVICE);
1409
1410 /* remove the CRC */
1411 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1412 if (!(netdev->features & NETIF_F_RXFCS))
1413 l1 -= 4;
1414 }
1415
1416 skb_put(skb, l1);
1417 goto copydone;
1418 } /* if */
1419 }
1420
1421 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1422 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1423 if (!length)
1424 break;
1425
1426 ps_page = &buffer_info->ps_pages[j];
1427 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1428 DMA_FROM_DEVICE);
1429 ps_page->dma = 0;
1430 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1431 ps_page->page = NULL;
1432 skb->len += length;
1433 skb->data_len += length;
1434 skb->truesize += PAGE_SIZE;
1435 }
1436
1437 /* strip the ethernet crc, problem is we're using pages now so
1438 * this whole operation can get a little cpu intensive
1439 */
1440 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1441 if (!(netdev->features & NETIF_F_RXFCS))
1442 pskb_trim(skb, skb->len - 4);
1443 }
1444
1445copydone:
1446 total_rx_bytes += skb->len;
1447 total_rx_packets++;
1448
1449 e1000_rx_checksum(adapter, staterr, skb);
1450
1451 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1452
1453 if (rx_desc->wb.upper.header_status &
1454 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1455 adapter->rx_hdr_split++;
1456
1457 e1000_receive_skb(adapter, netdev, skb, staterr,
1458 rx_desc->wb.middle.vlan);
1459
1460next_desc:
1461 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1462 buffer_info->skb = NULL;
1463
1464 /* return some buffers to hardware, one at a time is too slow */
1465 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1466 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1467 GFP_ATOMIC);
1468 cleaned_count = 0;
1469 }
1470
1471 /* use prefetched values */
1472 rx_desc = next_rxd;
1473 buffer_info = next_buffer;
1474
1475 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1476 }
1477 rx_ring->next_to_clean = i;
1478
1479 cleaned_count = e1000_desc_unused(rx_ring);
1480 if (cleaned_count)
1481 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1482
1483 adapter->total_rx_bytes += total_rx_bytes;
1484 adapter->total_rx_packets += total_rx_packets;
1485 return cleaned;
1486}
1487
1488static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1489 u16 length)
1490{
1491 bi->page = NULL;
1492 skb->len += length;
1493 skb->data_len += length;
1494 skb->truesize += PAGE_SIZE;
1495}
1496
1497/**
1498 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1499 * @rx_ring: Rx descriptor ring
1500 * @work_done: output parameter for indicating completed work
1501 * @work_to_do: how many packets we can clean
1502 *
1503 * the return value indicates whether actual cleaning was done, there
1504 * is no guarantee that everything was cleaned
1505 **/
1506static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1507 int work_to_do)
1508{
1509 struct e1000_adapter *adapter = rx_ring->adapter;
1510 struct net_device *netdev = adapter->netdev;
1511 struct pci_dev *pdev = adapter->pdev;
1512 union e1000_rx_desc_extended *rx_desc, *next_rxd;
1513 struct e1000_buffer *buffer_info, *next_buffer;
1514 u32 length, staterr;
1515 unsigned int i;
1516 int cleaned_count = 0;
1517 bool cleaned = false;
1518 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1519 struct skb_shared_info *shinfo;
1520
1521 i = rx_ring->next_to_clean;
1522 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1524 buffer_info = &rx_ring->buffer_info[i];
1525
1526 while (staterr & E1000_RXD_STAT_DD) {
1527 struct sk_buff *skb;
1528
1529 if (*work_done >= work_to_do)
1530 break;
1531 (*work_done)++;
1532 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1533
1534 skb = buffer_info->skb;
1535 buffer_info->skb = NULL;
1536
1537 ++i;
1538 if (i == rx_ring->count)
1539 i = 0;
1540 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
1541 prefetch(next_rxd);
1542
1543 next_buffer = &rx_ring->buffer_info[i];
1544
1545 cleaned = true;
1546 cleaned_count++;
1547 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1548 DMA_FROM_DEVICE);
1549 buffer_info->dma = 0;
1550
1551 length = le16_to_cpu(rx_desc->wb.upper.length);
1552
1553 /* errors is only valid for DD + EOP descriptors */
1554 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
1555 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1556 !(netdev->features & NETIF_F_RXALL)))) {
1557 /* recycle both page and skb */
1558 buffer_info->skb = skb;
1559 /* an error means any chain goes out the window too */
1560 if (rx_ring->rx_skb_top)
1561 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1562 rx_ring->rx_skb_top = NULL;
1563 goto next_desc;
1564 }
1565#define rxtop (rx_ring->rx_skb_top)
1566 if (!(staterr & E1000_RXD_STAT_EOP)) {
1567 /* this descriptor is only the beginning (or middle) */
1568 if (!rxtop) {
1569 /* this is the beginning of a chain */
1570 rxtop = skb;
1571 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1572 0, length);
1573 } else {
1574 /* this is the middle of a chain */
1575 shinfo = skb_shinfo(rxtop);
1576 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1577 buffer_info->page, 0,
1578 length);
1579 /* re-use the skb, only consumed the page */
1580 buffer_info->skb = skb;
1581 }
1582 e1000_consume_page(buffer_info, rxtop, length);
1583 goto next_desc;
1584 } else {
1585 if (rxtop) {
1586 /* end of the chain */
1587 shinfo = skb_shinfo(rxtop);
1588 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1589 buffer_info->page, 0,
1590 length);
1591 /* re-use the current skb, we only consumed the
1592 * page
1593 */
1594 buffer_info->skb = skb;
1595 skb = rxtop;
1596 rxtop = NULL;
1597 e1000_consume_page(buffer_info, skb, length);
1598 } else {
1599 /* no chain, got EOP, this buf is the packet
1600 * copybreak to save the put_page/alloc_page
1601 */
1602 if (length <= copybreak &&
1603 skb_tailroom(skb) >= length) {
1604 memcpy(skb_tail_pointer(skb),
1605 page_address(buffer_info->page),
1606 length);
1607 /* re-use the page, so don't erase
1608 * buffer_info->page
1609 */
1610 skb_put(skb, length);
1611 } else {
1612 skb_fill_page_desc(skb, 0,
1613 buffer_info->page, 0,
1614 length);
1615 e1000_consume_page(buffer_info, skb,
1616 length);
1617 }
1618 }
1619 }
1620
1621 /* Receive Checksum Offload */
1622 e1000_rx_checksum(adapter, staterr, skb);
1623
1624 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1625
1626 /* probably a little skewed due to removing CRC */
1627 total_rx_bytes += skb->len;
1628 total_rx_packets++;
1629
1630 /* eth type trans needs skb->data to point to something */
1631 if (!pskb_may_pull(skb, ETH_HLEN)) {
1632 e_err("pskb_may_pull failed.\n");
1633 dev_kfree_skb_irq(skb);
1634 goto next_desc;
1635 }
1636
1637 e1000_receive_skb(adapter, netdev, skb, staterr,
1638 rx_desc->wb.upper.vlan);
1639
1640next_desc:
1641 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1642
1643 /* return some buffers to hardware, one at a time is too slow */
1644 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
1645 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1646 GFP_ATOMIC);
1647 cleaned_count = 0;
1648 }
1649
1650 /* use prefetched values */
1651 rx_desc = next_rxd;
1652 buffer_info = next_buffer;
1653
1654 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1655 }
1656 rx_ring->next_to_clean = i;
1657
1658 cleaned_count = e1000_desc_unused(rx_ring);
1659 if (cleaned_count)
1660 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1661
1662 adapter->total_rx_bytes += total_rx_bytes;
1663 adapter->total_rx_packets += total_rx_packets;
1664 return cleaned;
1665}
1666
1667/**
1668 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1669 * @rx_ring: Rx descriptor ring
1670 **/
1671static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
1672{
1673 struct e1000_adapter *adapter = rx_ring->adapter;
1674 struct e1000_buffer *buffer_info;
1675 struct e1000_ps_page *ps_page;
1676 struct pci_dev *pdev = adapter->pdev;
1677 unsigned int i, j;
1678
1679 /* Free all the Rx ring sk_buffs */
1680 for (i = 0; i < rx_ring->count; i++) {
1681 buffer_info = &rx_ring->buffer_info[i];
1682 if (buffer_info->dma) {
1683 if (adapter->clean_rx == e1000_clean_rx_irq)
1684 dma_unmap_single(&pdev->dev, buffer_info->dma,
1685 adapter->rx_buffer_len,
1686 DMA_FROM_DEVICE);
1687 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
1688 dma_unmap_page(&pdev->dev, buffer_info->dma,
1689 PAGE_SIZE, DMA_FROM_DEVICE);
1690 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
1691 dma_unmap_single(&pdev->dev, buffer_info->dma,
1692 adapter->rx_ps_bsize0,
1693 DMA_FROM_DEVICE);
1694 buffer_info->dma = 0;
1695 }
1696
1697 if (buffer_info->page) {
1698 put_page(buffer_info->page);
1699 buffer_info->page = NULL;
1700 }
1701
1702 if (buffer_info->skb) {
1703 dev_kfree_skb(buffer_info->skb);
1704 buffer_info->skb = NULL;
1705 }
1706
1707 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1708 ps_page = &buffer_info->ps_pages[j];
1709 if (!ps_page->page)
1710 break;
1711 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1712 DMA_FROM_DEVICE);
1713 ps_page->dma = 0;
1714 put_page(ps_page->page);
1715 ps_page->page = NULL;
1716 }
1717 }
1718
1719 /* there also may be some cached data from a chained receive */
1720 if (rx_ring->rx_skb_top) {
1721 dev_kfree_skb(rx_ring->rx_skb_top);
1722 rx_ring->rx_skb_top = NULL;
1723 }
1724
1725 /* Zero out the descriptor ring */
1726 memset(rx_ring->desc, 0, rx_ring->size);
1727
1728 rx_ring->next_to_clean = 0;
1729 rx_ring->next_to_use = 0;
1730 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1731}
1732
1733static void e1000e_downshift_workaround(struct work_struct *work)
1734{
1735 struct e1000_adapter *adapter = container_of(work,
1736 struct e1000_adapter,
1737 downshift_task);
1738
1739 if (test_bit(__E1000_DOWN, &adapter->state))
1740 return;
1741
1742 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1743}
1744
1745/**
1746 * e1000_intr_msi - Interrupt Handler
1747 * @irq: interrupt number
1748 * @data: pointer to a network interface device structure
1749 **/
1750static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
1751{
1752 struct net_device *netdev = data;
1753 struct e1000_adapter *adapter = netdev_priv(netdev);
1754 struct e1000_hw *hw = &adapter->hw;
1755 u32 icr = er32(ICR);
1756
1757 /* read ICR disables interrupts using IAM */
1758 if (icr & E1000_ICR_LSC) {
1759 hw->mac.get_link_status = true;
1760 /* ICH8 workaround-- Call gig speed drop workaround on cable
1761 * disconnect (LSC) before accessing any PHY registers
1762 */
1763 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1764 (!(er32(STATUS) & E1000_STATUS_LU)))
1765 schedule_work(&adapter->downshift_task);
1766
1767 /* 80003ES2LAN workaround-- For packet buffer work-around on
1768 * link down event; disable receives here in the ISR and reset
1769 * adapter in watchdog
1770 */
1771 if (netif_carrier_ok(netdev) &&
1772 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1773 /* disable receives */
1774 u32 rctl = er32(RCTL);
1775
1776 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1777 adapter->flags |= FLAG_RESTART_NOW;
1778 }
1779 /* guard against interrupt when we're going down */
1780 if (!test_bit(__E1000_DOWN, &adapter->state))
1781 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1782 }
1783
1784 /* Reset on uncorrectable ECC error */
1785 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1786 u32 pbeccsts = er32(PBECCSTS);
1787
1788 adapter->corr_errors +=
1789 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1790 adapter->uncorr_errors +=
1791 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);
1792
1793 /* Do the reset outside of interrupt context */
1794 schedule_work(&adapter->reset_task);
1795
1796 /* return immediately since reset is imminent */
1797 return IRQ_HANDLED;
1798 }
1799
1800 if (napi_schedule_prep(&adapter->napi)) {
1801 adapter->total_tx_bytes = 0;
1802 adapter->total_tx_packets = 0;
1803 adapter->total_rx_bytes = 0;
1804 adapter->total_rx_packets = 0;
1805 __napi_schedule(&adapter->napi);
1806 }
1807
1808 return IRQ_HANDLED;
1809}
1810
1811/**
1812 * e1000_intr - Interrupt Handler
1813 * @irq: interrupt number
1814 * @data: pointer to a network interface device structure
1815 **/
1816static irqreturn_t e1000_intr(int __always_unused irq, void *data)
1817{
1818 struct net_device *netdev = data;
1819 struct e1000_adapter *adapter = netdev_priv(netdev);
1820 struct e1000_hw *hw = &adapter->hw;
1821 u32 rctl, icr = er32(ICR);
1822
1823 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
1824 return IRQ_NONE; /* Not our interrupt */
1825
1826 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1827 * not set, then the adapter didn't send an interrupt
1828 */
1829 if (!(icr & E1000_ICR_INT_ASSERTED))
1830 return IRQ_NONE;
1831
1832 /* Interrupt Auto-Mask...upon reading ICR,
1833 * interrupts are masked. No need for the
1834 * IMC write
1835 */
1836
1837 if (icr & E1000_ICR_LSC) {
1838 hw->mac.get_link_status = true;
1839 /* ICH8 workaround-- Call gig speed drop workaround on cable
1840 * disconnect (LSC) before accessing any PHY registers
1841 */
1842 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1843 (!(er32(STATUS) & E1000_STATUS_LU)))
1844 schedule_work(&adapter->downshift_task);
1845
1846 /* 80003ES2LAN workaround--
1847 * For packet buffer work-around on link down event;
1848 * disable receives here in the ISR and
1849 * reset adapter in watchdog
1850 */
1851 if (netif_carrier_ok(netdev) &&
1852 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1853 /* disable receives */
1854 rctl = er32(RCTL);
1855 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1856 adapter->flags |= FLAG_RESTART_NOW;
1857 }
1858 /* guard against interrupt when we're going down */
1859 if (!test_bit(__E1000_DOWN, &adapter->state))
1860 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1861 }
1862
1863 /* Reset on uncorrectable ECC error */
1864 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1865 u32 pbeccsts = er32(PBECCSTS);
1866
1867 adapter->corr_errors +=
1868 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1869 adapter->uncorr_errors +=
1870 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);
1871
1872 /* Do the reset outside of interrupt context */
1873 schedule_work(&adapter->reset_task);
1874
1875 /* return immediately since reset is imminent */
1876 return IRQ_HANDLED;
1877 }
1878
1879 if (napi_schedule_prep(&adapter->napi)) {
1880 adapter->total_tx_bytes = 0;
1881 adapter->total_tx_packets = 0;
1882 adapter->total_rx_bytes = 0;
1883 adapter->total_rx_packets = 0;
1884 __napi_schedule(&adapter->napi);
1885 }
1886
1887 return IRQ_HANDLED;
1888}
1889
1890static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
1891{
1892 struct net_device *netdev = data;
1893 struct e1000_adapter *adapter = netdev_priv(netdev);
1894 struct e1000_hw *hw = &adapter->hw;
1895 u32 icr = er32(ICR);
1896
1897 if (icr & adapter->eiac_mask)
1898 ew32(ICS, (icr & adapter->eiac_mask));
1899
1900 if (icr & E1000_ICR_LSC) {
1901 hw->mac.get_link_status = true;
1902 /* guard against interrupt when we're going down */
1903 if (!test_bit(__E1000_DOWN, &adapter->state))
1904 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1905 }
1906
1907 if (!test_bit(__E1000_DOWN, &adapter->state))
1908 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK);
1909
1910 return IRQ_HANDLED;
1911}
1912
1913static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
1914{
1915 struct net_device *netdev = data;
1916 struct e1000_adapter *adapter = netdev_priv(netdev);
1917 struct e1000_hw *hw = &adapter->hw;
1918 struct e1000_ring *tx_ring = adapter->tx_ring;
1919
1920 adapter->total_tx_bytes = 0;
1921 adapter->total_tx_packets = 0;
1922
1923 if (!e1000_clean_tx_irq(tx_ring))
1924 /* Ring was not completely cleaned, so fire another interrupt */
1925 ew32(ICS, tx_ring->ims_val);
1926
1927 if (!test_bit(__E1000_DOWN, &adapter->state))
1928 ew32(IMS, adapter->tx_ring->ims_val);
1929
1930 return IRQ_HANDLED;
1931}
1932
1933static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
1934{
1935 struct net_device *netdev = data;
1936 struct e1000_adapter *adapter = netdev_priv(netdev);
1937 struct e1000_ring *rx_ring = adapter->rx_ring;
1938
1939 /* Write the ITR value calculated at the end of the
1940 * previous interrupt.
1941 */
1942 if (rx_ring->set_itr) {
1943 u32 itr = rx_ring->itr_val ?
1944 1000000000 / (rx_ring->itr_val * 256) : 0;
1945
1946 writel(itr, rx_ring->itr_register);
1947 rx_ring->set_itr = 0;
1948 }
1949
1950 if (napi_schedule_prep(&adapter->napi)) {
1951 adapter->total_rx_bytes = 0;
1952 adapter->total_rx_packets = 0;
1953 __napi_schedule(&adapter->napi);
1954 }
1955 return IRQ_HANDLED;
1956}
1957
1958/**
1959 * e1000_configure_msix - Configure MSI-X hardware
1960 * @adapter: board private structure
1961 *
1962 * e1000_configure_msix sets up the hardware to properly
1963 * generate MSI-X interrupts.
1964 **/
1965static void e1000_configure_msix(struct e1000_adapter *adapter)
1966{
1967 struct e1000_hw *hw = &adapter->hw;
1968 struct e1000_ring *rx_ring = adapter->rx_ring;
1969 struct e1000_ring *tx_ring = adapter->tx_ring;
1970 int vector = 0;
1971 u32 ctrl_ext, ivar = 0;
1972
1973 adapter->eiac_mask = 0;
1974
1975 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1976 if (hw->mac.type == e1000_82574) {
1977 u32 rfctl = er32(RFCTL);
1978
1979 rfctl |= E1000_RFCTL_ACK_DIS;
1980 ew32(RFCTL, rfctl);
1981 }
1982
1983 /* Configure Rx vector */
1984 rx_ring->ims_val = E1000_IMS_RXQ0;
1985 adapter->eiac_mask |= rx_ring->ims_val;
1986 if (rx_ring->itr_val)
1987 writel(1000000000 / (rx_ring->itr_val * 256),
1988 rx_ring->itr_register);
1989 else
1990 writel(1, rx_ring->itr_register);
1991 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1992
1993 /* Configure Tx vector */
1994 tx_ring->ims_val = E1000_IMS_TXQ0;
1995 vector++;
1996 if (tx_ring->itr_val)
1997 writel(1000000000 / (tx_ring->itr_val * 256),
1998 tx_ring->itr_register);
1999 else
2000 writel(1, tx_ring->itr_register);
2001 adapter->eiac_mask |= tx_ring->ims_val;
2002 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
2003
2004 /* set vector for Other Causes, e.g. link changes */
2005 vector++;
2006 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
2007 if (rx_ring->itr_val)
2008 writel(1000000000 / (rx_ring->itr_val * 256),
2009 hw->hw_addr + E1000_EITR_82574(vector));
2010 else
2011 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
2012
2013 /* Cause Tx interrupts on every write back */
2014 ivar |= BIT(31);
2015
2016 ew32(IVAR, ivar);
2017
2018 /* enable MSI-X PBA support */
2019 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME;
2020 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME;
2021 ew32(CTRL_EXT, ctrl_ext);
2022 e1e_flush();
2023}
2024
2025void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2026{
2027 if (adapter->msix_entries) {
2028 pci_disable_msix(adapter->pdev);
2029 kfree(adapter->msix_entries);
2030 adapter->msix_entries = NULL;
2031 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2032 pci_disable_msi(adapter->pdev);
2033 adapter->flags &= ~FLAG_MSI_ENABLED;
2034 }
2035}
2036
2037/**
2038 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2039 * @adapter: board private structure
2040 *
2041 * Attempt to configure interrupts using the best available
2042 * capabilities of the hardware and kernel.
2043 **/
2044void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2045{
2046 int err;
2047 int i;
2048
2049 switch (adapter->int_mode) {
2050 case E1000E_INT_MODE_MSIX:
2051 if (adapter->flags & FLAG_HAS_MSIX) {
2052 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2053 adapter->msix_entries = kcalloc(adapter->num_vectors,
2054 sizeof(struct
2055 msix_entry),
2056 GFP_KERNEL);
2057 if (adapter->msix_entries) {
2058 struct e1000_adapter *a = adapter;
2059
2060 for (i = 0; i < adapter->num_vectors; i++)
2061 adapter->msix_entries[i].entry = i;
2062
2063 err = pci_enable_msix_range(a->pdev,
2064 a->msix_entries,
2065 a->num_vectors,
2066 a->num_vectors);
2067 if (err > 0)
2068 return;
2069 }
2070 /* MSI-X failed, so fall through and try MSI */
2071 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
2072 e1000e_reset_interrupt_capability(adapter);
2073 }
2074 adapter->int_mode = E1000E_INT_MODE_MSI;
2075 fallthrough;
2076 case E1000E_INT_MODE_MSI:
2077 if (!pci_enable_msi(adapter->pdev)) {
2078 adapter->flags |= FLAG_MSI_ENABLED;
2079 } else {
2080 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2081 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
2082 }
2083 fallthrough;
2084 case E1000E_INT_MODE_LEGACY:
2085 /* Don't do anything; this is the system default */
2086 break;
2087 }
2088
2089 /* store the number of vectors being used */
2090 adapter->num_vectors = 1;
2091}
2092
2093/**
2094 * e1000_request_msix - Initialize MSI-X interrupts
2095 * @adapter: board private structure
2096 *
2097 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2098 * kernel.
2099 **/
2100static int e1000_request_msix(struct e1000_adapter *adapter)
2101{
2102 struct net_device *netdev = adapter->netdev;
2103 int err = 0, vector = 0;
2104
2105 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2106 snprintf(adapter->rx_ring->name,
2107 sizeof(adapter->rx_ring->name) - 1,
2108 "%.14s-rx-0", netdev->name);
2109 else
2110 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2111 err = request_irq(adapter->msix_entries[vector].vector,
2112 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
2113 netdev);
2114 if (err)
2115 return err;
2116 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2117 E1000_EITR_82574(vector);
2118 adapter->rx_ring->itr_val = adapter->itr;
2119 vector++;
2120
2121 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2122 snprintf(adapter->tx_ring->name,
2123 sizeof(adapter->tx_ring->name) - 1,
2124 "%.14s-tx-0", netdev->name);
2125 else
2126 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2127 err = request_irq(adapter->msix_entries[vector].vector,
2128 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
2129 netdev);
2130 if (err)
2131 return err;
2132 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2133 E1000_EITR_82574(vector);
2134 adapter->tx_ring->itr_val = adapter->itr;
2135 vector++;
2136
2137 err = request_irq(adapter->msix_entries[vector].vector,
2138 e1000_msix_other, 0, netdev->name, netdev);
2139 if (err)
2140 return err;
2141
2142 e1000_configure_msix(adapter);
2143
2144 return 0;
2145}
2146
2147/**
2148 * e1000_request_irq - initialize interrupts
2149 * @adapter: board private structure
2150 *
2151 * Attempts to configure interrupts using the best available
2152 * capabilities of the hardware and kernel.
2153 **/
2154static int e1000_request_irq(struct e1000_adapter *adapter)
2155{
2156 struct net_device *netdev = adapter->netdev;
2157 int err;
2158
2159 if (adapter->msix_entries) {
2160 err = e1000_request_msix(adapter);
2161 if (!err)
2162 return err;
2163 /* fall back to MSI */
2164 e1000e_reset_interrupt_capability(adapter);
2165 adapter->int_mode = E1000E_INT_MODE_MSI;
2166 e1000e_set_interrupt_capability(adapter);
2167 }
2168 if (adapter->flags & FLAG_MSI_ENABLED) {
2169 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
2170 netdev->name, netdev);
2171 if (!err)
2172 return err;
2173
2174 /* fall back to legacy interrupt */
2175 e1000e_reset_interrupt_capability(adapter);
2176 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2177 }
2178
2179 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
2180 netdev->name, netdev);
2181 if (err)
2182 e_err("Unable to allocate interrupt, Error: %d\n", err);
2183
2184 return err;
2185}
2186
2187static void e1000_free_irq(struct e1000_adapter *adapter)
2188{
2189 struct net_device *netdev = adapter->netdev;
2190
2191 if (adapter->msix_entries) {
2192 int vector = 0;
2193
2194 free_irq(adapter->msix_entries[vector].vector, netdev);
2195 vector++;
2196
2197 free_irq(adapter->msix_entries[vector].vector, netdev);
2198 vector++;
2199
2200 /* Other Causes interrupt vector */
2201 free_irq(adapter->msix_entries[vector].vector, netdev);
2202 return;
2203 }
2204
2205 free_irq(adapter->pdev->irq, netdev);
2206}
2207
2208/**
2209 * e1000_irq_disable - Mask off interrupt generation on the NIC
2210 * @adapter: board private structure
2211 **/
2212static void e1000_irq_disable(struct e1000_adapter *adapter)
2213{
2214 struct e1000_hw *hw = &adapter->hw;
2215
2216 ew32(IMC, ~0);
2217 if (adapter->msix_entries)
2218 ew32(EIAC_82574, 0);
2219 e1e_flush();
2220
2221 if (adapter->msix_entries) {
2222 int i;
2223
2224 for (i = 0; i < adapter->num_vectors; i++)
2225 synchronize_irq(adapter->msix_entries[i].vector);
2226 } else {
2227 synchronize_irq(adapter->pdev->irq);
2228 }
2229}
2230
2231/**
2232 * e1000_irq_enable - Enable default interrupt generation settings
2233 * @adapter: board private structure
2234 **/
2235static void e1000_irq_enable(struct e1000_adapter *adapter)
2236{
2237 struct e1000_hw *hw = &adapter->hw;
2238
2239 if (adapter->msix_entries) {
2240 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2241 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER |
2242 IMS_OTHER_MASK);
2243 } else if (hw->mac.type >= e1000_pch_lpt) {
2244 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
2245 } else {
2246 ew32(IMS, IMS_ENABLE_MASK);
2247 }
2248 e1e_flush();
2249}
2250
2251/**
2252 * e1000e_get_hw_control - get control of the h/w from f/w
2253 * @adapter: address of board private structure
2254 *
2255 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2256 * For ASF and Pass Through versions of f/w this means that
2257 * the driver is loaded. For AMT version (only with 82573)
2258 * of the f/w this means that the network i/f is open.
2259 **/
2260void e1000e_get_hw_control(struct e1000_adapter *adapter)
2261{
2262 struct e1000_hw *hw = &adapter->hw;
2263 u32 ctrl_ext;
2264 u32 swsm;
2265
2266 /* Let firmware know the driver has taken over */
2267 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2268 swsm = er32(SWSM);
2269 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2270 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2271 ctrl_ext = er32(CTRL_EXT);
2272 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2273 }
2274}
2275
2276/**
2277 * e1000e_release_hw_control - release control of the h/w to f/w
2278 * @adapter: address of board private structure
2279 *
2280 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2281 * For ASF and Pass Through versions of f/w this means that the
2282 * driver is no longer loaded. For AMT version (only with 82573) i
2283 * of the f/w this means that the network i/f is closed.
2284 *
2285 **/
2286void e1000e_release_hw_control(struct e1000_adapter *adapter)
2287{
2288 struct e1000_hw *hw = &adapter->hw;
2289 u32 ctrl_ext;
2290 u32 swsm;
2291
2292 /* Let firmware taken over control of h/w */
2293 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2294 swsm = er32(SWSM);
2295 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2296 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2297 ctrl_ext = er32(CTRL_EXT);
2298 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2299 }
2300}
2301
2302/**
2303 * e1000_alloc_ring_dma - allocate memory for a ring structure
2304 * @adapter: board private structure
2305 * @ring: ring struct for which to allocate dma
2306 **/
2307static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2308 struct e1000_ring *ring)
2309{
2310 struct pci_dev *pdev = adapter->pdev;
2311
2312 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2313 GFP_KERNEL);
2314 if (!ring->desc)
2315 return -ENOMEM;
2316
2317 return 0;
2318}
2319
2320/**
2321 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2322 * @tx_ring: Tx descriptor ring
2323 *
2324 * Return 0 on success, negative on failure
2325 **/
2326int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
2327{
2328 struct e1000_adapter *adapter = tx_ring->adapter;
2329 int err = -ENOMEM, size;
2330
2331 size = sizeof(struct e1000_buffer) * tx_ring->count;
2332 tx_ring->buffer_info = vzalloc(size);
2333 if (!tx_ring->buffer_info)
2334 goto err;
2335
2336 /* round up to nearest 4K */
2337 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2338 tx_ring->size = ALIGN(tx_ring->size, 4096);
2339
2340 err = e1000_alloc_ring_dma(adapter, tx_ring);
2341 if (err)
2342 goto err;
2343
2344 tx_ring->next_to_use = 0;
2345 tx_ring->next_to_clean = 0;
2346
2347 return 0;
2348err:
2349 vfree(tx_ring->buffer_info);
2350 e_err("Unable to allocate memory for the transmit descriptor ring\n");
2351 return err;
2352}
2353
2354/**
2355 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2356 * @rx_ring: Rx descriptor ring
2357 *
2358 * Returns 0 on success, negative on failure
2359 **/
2360int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
2361{
2362 struct e1000_adapter *adapter = rx_ring->adapter;
2363 struct e1000_buffer *buffer_info;
2364 int i, size, desc_len, err = -ENOMEM;
2365
2366 size = sizeof(struct e1000_buffer) * rx_ring->count;
2367 rx_ring->buffer_info = vzalloc(size);
2368 if (!rx_ring->buffer_info)
2369 goto err;
2370
2371 for (i = 0; i < rx_ring->count; i++) {
2372 buffer_info = &rx_ring->buffer_info[i];
2373 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2374 sizeof(struct e1000_ps_page),
2375 GFP_KERNEL);
2376 if (!buffer_info->ps_pages)
2377 goto err_pages;
2378 }
2379
2380 desc_len = sizeof(union e1000_rx_desc_packet_split);
2381
2382 /* Round up to nearest 4K */
2383 rx_ring->size = rx_ring->count * desc_len;
2384 rx_ring->size = ALIGN(rx_ring->size, 4096);
2385
2386 err = e1000_alloc_ring_dma(adapter, rx_ring);
2387 if (err)
2388 goto err_pages;
2389
2390 rx_ring->next_to_clean = 0;
2391 rx_ring->next_to_use = 0;
2392 rx_ring->rx_skb_top = NULL;
2393
2394 return 0;
2395
2396err_pages:
2397 for (i = 0; i < rx_ring->count; i++) {
2398 buffer_info = &rx_ring->buffer_info[i];
2399 kfree(buffer_info->ps_pages);
2400 }
2401err:
2402 vfree(rx_ring->buffer_info);
2403 e_err("Unable to allocate memory for the receive descriptor ring\n");
2404 return err;
2405}
2406
2407/**
2408 * e1000_clean_tx_ring - Free Tx Buffers
2409 * @tx_ring: Tx descriptor ring
2410 **/
2411static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
2412{
2413 struct e1000_adapter *adapter = tx_ring->adapter;
2414 struct e1000_buffer *buffer_info;
2415 unsigned long size;
2416 unsigned int i;
2417
2418 for (i = 0; i < tx_ring->count; i++) {
2419 buffer_info = &tx_ring->buffer_info[i];
2420 e1000_put_txbuf(tx_ring, buffer_info, false);
2421 }
2422
2423 netdev_reset_queue(adapter->netdev);
2424 size = sizeof(struct e1000_buffer) * tx_ring->count;
2425 memset(tx_ring->buffer_info, 0, size);
2426
2427 memset(tx_ring->desc, 0, tx_ring->size);
2428
2429 tx_ring->next_to_use = 0;
2430 tx_ring->next_to_clean = 0;
2431}
2432
2433/**
2434 * e1000e_free_tx_resources - Free Tx Resources per Queue
2435 * @tx_ring: Tx descriptor ring
2436 *
2437 * Free all transmit software resources
2438 **/
2439void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
2440{
2441 struct e1000_adapter *adapter = tx_ring->adapter;
2442 struct pci_dev *pdev = adapter->pdev;
2443
2444 e1000_clean_tx_ring(tx_ring);
2445
2446 vfree(tx_ring->buffer_info);
2447 tx_ring->buffer_info = NULL;
2448
2449 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2450 tx_ring->dma);
2451 tx_ring->desc = NULL;
2452}
2453
2454/**
2455 * e1000e_free_rx_resources - Free Rx Resources
2456 * @rx_ring: Rx descriptor ring
2457 *
2458 * Free all receive software resources
2459 **/
2460void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
2461{
2462 struct e1000_adapter *adapter = rx_ring->adapter;
2463 struct pci_dev *pdev = adapter->pdev;
2464 int i;
2465
2466 e1000_clean_rx_ring(rx_ring);
2467
2468 for (i = 0; i < rx_ring->count; i++)
2469 kfree(rx_ring->buffer_info[i].ps_pages);
2470
2471 vfree(rx_ring->buffer_info);
2472 rx_ring->buffer_info = NULL;
2473
2474 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2475 rx_ring->dma);
2476 rx_ring->desc = NULL;
2477}
2478
2479/**
2480 * e1000_update_itr - update the dynamic ITR value based on statistics
2481 * @itr_setting: current adapter->itr
2482 * @packets: the number of packets during this measurement interval
2483 * @bytes: the number of bytes during this measurement interval
2484 *
2485 * Stores a new ITR value based on packets and byte
2486 * counts during the last interrupt. The advantage of per interrupt
2487 * computation is faster updates and more accurate ITR for the current
2488 * traffic pattern. Constants in this function were computed
2489 * based on theoretical maximum wire speed and thresholds were set based
2490 * on testing data as well as attempting to minimize response time
2491 * while increasing bulk throughput. This functionality is controlled
2492 * by the InterruptThrottleRate module parameter.
2493 **/
2494static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
2495{
2496 unsigned int retval = itr_setting;
2497
2498 if (packets == 0)
2499 return itr_setting;
2500
2501 switch (itr_setting) {
2502 case lowest_latency:
2503 /* handle TSO and jumbo frames */
2504 if (bytes / packets > 8000)
2505 retval = bulk_latency;
2506 else if ((packets < 5) && (bytes > 512))
2507 retval = low_latency;
2508 break;
2509 case low_latency: /* 50 usec aka 20000 ints/s */
2510 if (bytes > 10000) {
2511 /* this if handles the TSO accounting */
2512 if (bytes / packets > 8000)
2513 retval = bulk_latency;
2514 else if ((packets < 10) || ((bytes / packets) > 1200))
2515 retval = bulk_latency;
2516 else if ((packets > 35))
2517 retval = lowest_latency;
2518 } else if (bytes / packets > 2000) {
2519 retval = bulk_latency;
2520 } else if (packets <= 2 && bytes < 512) {
2521 retval = lowest_latency;
2522 }
2523 break;
2524 case bulk_latency: /* 250 usec aka 4000 ints/s */
2525 if (bytes > 25000) {
2526 if (packets > 35)
2527 retval = low_latency;
2528 } else if (bytes < 6000) {
2529 retval = low_latency;
2530 }
2531 break;
2532 }
2533
2534 return retval;
2535}
2536
2537static void e1000_set_itr(struct e1000_adapter *adapter)
2538{
2539 u16 current_itr;
2540 u32 new_itr = adapter->itr;
2541
2542 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2543 if (adapter->link_speed != SPEED_1000) {
2544 new_itr = 4000;
2545 goto set_itr_now;
2546 }
2547
2548 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2549 new_itr = 0;
2550 goto set_itr_now;
2551 }
2552
2553 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2554 adapter->total_tx_packets,
2555 adapter->total_tx_bytes);
2556 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2557 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2558 adapter->tx_itr = low_latency;
2559
2560 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2561 adapter->total_rx_packets,
2562 adapter->total_rx_bytes);
2563 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2564 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2565 adapter->rx_itr = low_latency;
2566
2567 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2568
2569 /* counts and packets in update_itr are dependent on these numbers */
2570 switch (current_itr) {
2571 case lowest_latency:
2572 new_itr = 70000;
2573 break;
2574 case low_latency:
2575 new_itr = 20000; /* aka hwitr = ~200 */
2576 break;
2577 case bulk_latency:
2578 new_itr = 4000;
2579 break;
2580 default:
2581 break;
2582 }
2583
2584set_itr_now:
2585 if (new_itr != adapter->itr) {
2586 /* this attempts to bias the interrupt rate towards Bulk
2587 * by adding intermediate steps when interrupt rate is
2588 * increasing
2589 */
2590 new_itr = new_itr > adapter->itr ?
2591 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
2592 adapter->itr = new_itr;
2593 adapter->rx_ring->itr_val = new_itr;
2594 if (adapter->msix_entries)
2595 adapter->rx_ring->set_itr = 1;
2596 else
2597 e1000e_write_itr(adapter, new_itr);
2598 }
2599}
2600
2601/**
2602 * e1000e_write_itr - write the ITR value to the appropriate registers
2603 * @adapter: address of board private structure
2604 * @itr: new ITR value to program
2605 *
2606 * e1000e_write_itr determines if the adapter is in MSI-X mode
2607 * and, if so, writes the EITR registers with the ITR value.
2608 * Otherwise, it writes the ITR value into the ITR register.
2609 **/
2610void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2611{
2612 struct e1000_hw *hw = &adapter->hw;
2613 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2614
2615 if (adapter->msix_entries) {
2616 int vector;
2617
2618 for (vector = 0; vector < adapter->num_vectors; vector++)
2619 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2620 } else {
2621 ew32(ITR, new_itr);
2622 }
2623}
2624
2625/**
2626 * e1000_alloc_queues - Allocate memory for all rings
2627 * @adapter: board private structure to initialize
2628 **/
2629static int e1000_alloc_queues(struct e1000_adapter *adapter)
2630{
2631 int size = sizeof(struct e1000_ring);
2632
2633 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
2634 if (!adapter->tx_ring)
2635 goto err;
2636 adapter->tx_ring->count = adapter->tx_ring_count;
2637 adapter->tx_ring->adapter = adapter;
2638
2639 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
2640 if (!adapter->rx_ring)
2641 goto err;
2642 adapter->rx_ring->count = adapter->rx_ring_count;
2643 adapter->rx_ring->adapter = adapter;
2644
2645 return 0;
2646err:
2647 e_err("Unable to allocate memory for queues\n");
2648 kfree(adapter->rx_ring);
2649 kfree(adapter->tx_ring);
2650 return -ENOMEM;
2651}
2652
2653/**
2654 * e1000e_poll - NAPI Rx polling callback
2655 * @napi: struct associated with this polling callback
2656 * @budget: number of packets driver is allowed to process this poll
2657 **/
2658static int e1000e_poll(struct napi_struct *napi, int budget)
2659{
2660 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2661 napi);
2662 struct e1000_hw *hw = &adapter->hw;
2663 struct net_device *poll_dev = adapter->netdev;
2664 int tx_cleaned = 1, work_done = 0;
2665
2666 adapter = netdev_priv(poll_dev);
2667
2668 if (!adapter->msix_entries ||
2669 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2670 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
2671
2672 adapter->clean_rx(adapter->rx_ring, &work_done, budget);
2673
2674 if (!tx_cleaned || work_done == budget)
2675 return budget;
2676
2677 /* Exit the polling mode, but don't re-enable interrupts if stack might
2678 * poll us due to busy-polling
2679 */
2680 if (likely(napi_complete_done(napi, work_done))) {
2681 if (adapter->itr_setting & 3)
2682 e1000_set_itr(adapter);
2683 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2684 if (adapter->msix_entries)
2685 ew32(IMS, adapter->rx_ring->ims_val);
2686 else
2687 e1000_irq_enable(adapter);
2688 }
2689 }
2690
2691 return work_done;
2692}
2693
2694static int e1000_vlan_rx_add_vid(struct net_device *netdev,
2695 __always_unused __be16 proto, u16 vid)
2696{
2697 struct e1000_adapter *adapter = netdev_priv(netdev);
2698 struct e1000_hw *hw = &adapter->hw;
2699 u32 vfta, index;
2700
2701 /* don't update vlan cookie if already programmed */
2702 if ((adapter->hw.mng_cookie.status &
2703 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2704 (vid == adapter->mng_vlan_id))
2705 return 0;
2706
2707 /* add VID to filter table */
2708 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2709 index = (vid >> 5) & 0x7F;
2710 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2711 vfta |= BIT((vid & 0x1F));
2712 hw->mac.ops.write_vfta(hw, index, vfta);
2713 }
2714
2715 set_bit(vid, adapter->active_vlans);
2716
2717 return 0;
2718}
2719
2720static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
2721 __always_unused __be16 proto, u16 vid)
2722{
2723 struct e1000_adapter *adapter = netdev_priv(netdev);
2724 struct e1000_hw *hw = &adapter->hw;
2725 u32 vfta, index;
2726
2727 if ((adapter->hw.mng_cookie.status &
2728 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2729 (vid == adapter->mng_vlan_id)) {
2730 /* release control to f/w */
2731 e1000e_release_hw_control(adapter);
2732 return 0;
2733 }
2734
2735 /* remove VID from filter table */
2736 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2737 index = (vid >> 5) & 0x7F;
2738 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2739 vfta &= ~BIT((vid & 0x1F));
2740 hw->mac.ops.write_vfta(hw, index, vfta);
2741 }
2742
2743 clear_bit(vid, adapter->active_vlans);
2744
2745 return 0;
2746}
2747
2748/**
2749 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2750 * @adapter: board private structure to initialize
2751 **/
2752static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
2753{
2754 struct net_device *netdev = adapter->netdev;
2755 struct e1000_hw *hw = &adapter->hw;
2756 u32 rctl;
2757
2758 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2759 /* disable VLAN receive filtering */
2760 rctl = er32(RCTL);
2761 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2762 ew32(RCTL, rctl);
2763
2764 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2765 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2766 adapter->mng_vlan_id);
2767 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
2768 }
2769 }
2770}
2771
2772/**
2773 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2774 * @adapter: board private structure to initialize
2775 **/
2776static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2777{
2778 struct e1000_hw *hw = &adapter->hw;
2779 u32 rctl;
2780
2781 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2782 /* enable VLAN receive filtering */
2783 rctl = er32(RCTL);
2784 rctl |= E1000_RCTL_VFE;
2785 rctl &= ~E1000_RCTL_CFIEN;
2786 ew32(RCTL, rctl);
2787 }
2788}
2789
2790/**
2791 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping
2792 * @adapter: board private structure to initialize
2793 **/
2794static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
2795{
2796 struct e1000_hw *hw = &adapter->hw;
2797 u32 ctrl;
2798
2799 /* disable VLAN tag insert/strip */
2800 ctrl = er32(CTRL);
2801 ctrl &= ~E1000_CTRL_VME;
2802 ew32(CTRL, ctrl);
2803}
2804
2805/**
2806 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2807 * @adapter: board private structure to initialize
2808 **/
2809static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2810{
2811 struct e1000_hw *hw = &adapter->hw;
2812 u32 ctrl;
2813
2814 /* enable VLAN tag insert/strip */
2815 ctrl = er32(CTRL);
2816 ctrl |= E1000_CTRL_VME;
2817 ew32(CTRL, ctrl);
2818}
2819
2820static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2821{
2822 struct net_device *netdev = adapter->netdev;
2823 u16 vid = adapter->hw.mng_cookie.vlan_id;
2824 u16 old_vid = adapter->mng_vlan_id;
2825
2826 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2827 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
2828 adapter->mng_vlan_id = vid;
2829 }
2830
2831 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2832 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
2833}
2834
2835static void e1000_restore_vlan(struct e1000_adapter *adapter)
2836{
2837 u16 vid;
2838
2839 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
2840
2841 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2842 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
2843}
2844
2845static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
2846{
2847 struct e1000_hw *hw = &adapter->hw;
2848 u32 manc, manc2h, mdef, i, j;
2849
2850 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2851 return;
2852
2853 manc = er32(MANC);
2854
2855 /* enable receiving management packets to the host. this will probably
2856 * generate destination unreachable messages from the host OS, but
2857 * the packets will be handled on SMBUS
2858 */
2859 manc |= E1000_MANC_EN_MNG2HOST;
2860 manc2h = er32(MANC2H);
2861
2862 switch (hw->mac.type) {
2863 default:
2864 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2865 break;
2866 case e1000_82574:
2867 case e1000_82583:
2868 /* Check if IPMI pass-through decision filter already exists;
2869 * if so, enable it.
2870 */
2871 for (i = 0, j = 0; i < 8; i++) {
2872 mdef = er32(MDEF(i));
2873
2874 /* Ignore filters with anything other than IPMI ports */
2875 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2876 continue;
2877
2878 /* Enable this decision filter in MANC2H */
2879 if (mdef)
2880 manc2h |= BIT(i);
2881
2882 j |= mdef;
2883 }
2884
2885 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2886 break;
2887
2888 /* Create new decision filter in an empty filter */
2889 for (i = 0, j = 0; i < 8; i++)
2890 if (er32(MDEF(i)) == 0) {
2891 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2892 E1000_MDEF_PORT_664));
2893 manc2h |= BIT(1);
2894 j++;
2895 break;
2896 }
2897
2898 if (!j)
2899 e_warn("Unable to create IPMI pass-through filter\n");
2900 break;
2901 }
2902
2903 ew32(MANC2H, manc2h);
2904 ew32(MANC, manc);
2905}
2906
2907/**
2908 * e1000_configure_tx - Configure Transmit Unit after Reset
2909 * @adapter: board private structure
2910 *
2911 * Configure the Tx unit of the MAC after a reset.
2912 **/
2913static void e1000_configure_tx(struct e1000_adapter *adapter)
2914{
2915 struct e1000_hw *hw = &adapter->hw;
2916 struct e1000_ring *tx_ring = adapter->tx_ring;
2917 u64 tdba;
2918 u32 tdlen, tctl, tarc;
2919
2920 /* Setup the HW Tx Head and Tail descriptor pointers */
2921 tdba = tx_ring->dma;
2922 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
2923 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2924 ew32(TDBAH(0), (tdba >> 32));
2925 ew32(TDLEN(0), tdlen);
2926 ew32(TDH(0), 0);
2927 ew32(TDT(0), 0);
2928 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2929 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
2930
2931 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2932 e1000e_update_tdt_wa(tx_ring, 0);
2933
2934 /* Set the Tx Interrupt Delay register */
2935 ew32(TIDV, adapter->tx_int_delay);
2936 /* Tx irq moderation */
2937 ew32(TADV, adapter->tx_abs_int_delay);
2938
2939 if (adapter->flags2 & FLAG2_DMA_BURST) {
2940 u32 txdctl = er32(TXDCTL(0));
2941
2942 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2943 E1000_TXDCTL_WTHRESH);
2944 /* set up some performance related parameters to encourage the
2945 * hardware to use the bus more efficiently in bursts, depends
2946 * on the tx_int_delay to be enabled,
2947 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2948 * hthresh = 1 ==> prefetch when one or more available
2949 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2950 * BEWARE: this seems to work but should be considered first if
2951 * there are Tx hangs or other Tx related bugs
2952 */
2953 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2954 ew32(TXDCTL(0), txdctl);
2955 }
2956 /* erratum work around: set txdctl the same for both queues */
2957 ew32(TXDCTL(1), er32(TXDCTL(0)));
2958
2959 /* Program the Transmit Control Register */
2960 tctl = er32(TCTL);
2961 tctl &= ~E1000_TCTL_CT;
2962 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2963 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2964
2965 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
2966 tarc = er32(TARC(0));
2967 /* set the speed mode bit, we'll clear it if we're not at
2968 * gigabit link later
2969 */
2970#define SPEED_MODE_BIT BIT(21)
2971 tarc |= SPEED_MODE_BIT;
2972 ew32(TARC(0), tarc);
2973 }
2974
2975 /* errata: program both queues to unweighted RR */
2976 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
2977 tarc = er32(TARC(0));
2978 tarc |= 1;
2979 ew32(TARC(0), tarc);
2980 tarc = er32(TARC(1));
2981 tarc |= 1;
2982 ew32(TARC(1), tarc);
2983 }
2984
2985 /* Setup Transmit Descriptor Settings for eop descriptor */
2986 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2987
2988 /* only set IDE if we are delaying interrupts using the timers */
2989 if (adapter->tx_int_delay)
2990 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2991
2992 /* enable Report Status bit */
2993 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2994
2995 ew32(TCTL, tctl);
2996
2997 hw->mac.ops.config_collision_dist(hw);
2998
2999 /* SPT and KBL Si errata workaround to avoid data corruption */
3000 if (hw->mac.type == e1000_pch_spt) {
3001 u32 reg_val;
3002
3003 reg_val = er32(IOSFPC);
3004 reg_val |= E1000_RCTL_RDMTS_HEX;
3005 ew32(IOSFPC, reg_val);
3006
3007 reg_val = er32(TARC(0));
3008 /* SPT and KBL Si errata workaround to avoid Tx hang.
3009 * Dropping the number of outstanding requests from
3010 * 3 to 2 in order to avoid a buffer overrun.
3011 */
3012 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3013 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ;
3014 ew32(TARC(0), reg_val);
3015 }
3016}
3017
3018#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3019 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3020
3021/**
3022 * e1000_setup_rctl - configure the receive control registers
3023 * @adapter: Board private structure
3024 **/
3025static void e1000_setup_rctl(struct e1000_adapter *adapter)
3026{
3027 struct e1000_hw *hw = &adapter->hw;
3028 u32 rctl, rfctl;
3029 u32 pages = 0;
3030
3031 /* Workaround Si errata on PCHx - configure jumbo frame flow.
3032 * If jumbo frames not set, program related MAC/PHY registers
3033 * to h/w defaults
3034 */
3035 if (hw->mac.type >= e1000_pch2lan) {
3036 s32 ret_val;
3037
3038 if (adapter->netdev->mtu > ETH_DATA_LEN)
3039 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
3040 else
3041 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
3042
3043 if (ret_val)
3044 e_dbg("failed to enable|disable jumbo frame workaround mode\n");
3045 }
3046
3047 /* Program MC offset vector base */
3048 rctl = er32(RCTL);
3049 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3050 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3051 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3052 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3053
3054 /* Do not Store bad packets */
3055 rctl &= ~E1000_RCTL_SBP;
3056
3057 /* Enable Long Packet receive */
3058 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3059 rctl &= ~E1000_RCTL_LPE;
3060 else
3061 rctl |= E1000_RCTL_LPE;
3062
3063 /* Some systems expect that the CRC is included in SMBUS traffic. The
3064 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3065 * host memory when this is enabled
3066 */
3067 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3068 rctl |= E1000_RCTL_SECRC;
3069
3070 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3071 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3072 u16 phy_data;
3073
3074 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3075 phy_data &= 0xfff8;
3076 phy_data |= BIT(2);
3077 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3078
3079 e1e_rphy(hw, 22, &phy_data);
3080 phy_data &= 0x0fff;
3081 phy_data |= BIT(14);
3082 e1e_wphy(hw, 0x10, 0x2823);
3083 e1e_wphy(hw, 0x11, 0x0003);
3084 e1e_wphy(hw, 22, phy_data);
3085 }
3086
3087 /* Setup buffer sizes */
3088 rctl &= ~E1000_RCTL_SZ_4096;
3089 rctl |= E1000_RCTL_BSEX;
3090 switch (adapter->rx_buffer_len) {
3091 case 2048:
3092 default:
3093 rctl |= E1000_RCTL_SZ_2048;
3094 rctl &= ~E1000_RCTL_BSEX;
3095 break;
3096 case 4096:
3097 rctl |= E1000_RCTL_SZ_4096;
3098 break;
3099 case 8192:
3100 rctl |= E1000_RCTL_SZ_8192;
3101 break;
3102 case 16384:
3103 rctl |= E1000_RCTL_SZ_16384;
3104 break;
3105 }
3106
3107 /* Enable Extended Status in all Receive Descriptors */
3108 rfctl = er32(RFCTL);
3109 rfctl |= E1000_RFCTL_EXTEN;
3110 ew32(RFCTL, rfctl);
3111
3112 /* 82571 and greater support packet-split where the protocol
3113 * header is placed in skb->data and the packet data is
3114 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3115 * In the case of a non-split, skb->data is linearly filled,
3116 * followed by the page buffers. Therefore, skb->data is
3117 * sized to hold the largest protocol header.
3118 *
3119 * allocations using alloc_page take too long for regular MTU
3120 * so only enable packet split for jumbo frames
3121 *
3122 * Using pages when the page size is greater than 16k wastes
3123 * a lot of memory, since we allocate 3 pages at all times
3124 * per packet.
3125 */
3126 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
3127 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
3128 adapter->rx_ps_pages = pages;
3129 else
3130 adapter->rx_ps_pages = 0;
3131
3132 if (adapter->rx_ps_pages) {
3133 u32 psrctl = 0;
3134
3135 /* Enable Packet split descriptors */
3136 rctl |= E1000_RCTL_DTYP_PS;
3137
3138 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
3139
3140 switch (adapter->rx_ps_pages) {
3141 case 3:
3142 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3143 fallthrough;
3144 case 2:
3145 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3146 fallthrough;
3147 case 1:
3148 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
3149 break;
3150 }
3151
3152 ew32(PSRCTL, psrctl);
3153 }
3154
3155 /* This is useful for sniffing bad packets. */
3156 if (adapter->netdev->features & NETIF_F_RXALL) {
3157 /* UPE and MPE will be handled by normal PROMISC logic
3158 * in e1000e_set_rx_mode
3159 */
3160 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3161 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3162 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3163
3164 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3165 E1000_RCTL_DPF | /* Allow filtered pause */
3166 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3167 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3168 * and that breaks VLANs.
3169 */
3170 }
3171
3172 ew32(RCTL, rctl);
3173 /* just started the receive unit, no need to restart */
3174 adapter->flags &= ~FLAG_RESTART_NOW;
3175}
3176
3177/**
3178 * e1000_configure_rx - Configure Receive Unit after Reset
3179 * @adapter: board private structure
3180 *
3181 * Configure the Rx unit of the MAC after a reset.
3182 **/
3183static void e1000_configure_rx(struct e1000_adapter *adapter)
3184{
3185 struct e1000_hw *hw = &adapter->hw;
3186 struct e1000_ring *rx_ring = adapter->rx_ring;
3187 u64 rdba;
3188 u32 rdlen, rctl, rxcsum, ctrl_ext;
3189
3190 if (adapter->rx_ps_pages) {
3191 /* this is a 32 byte descriptor */
3192 rdlen = rx_ring->count *
3193 sizeof(union e1000_rx_desc_packet_split);
3194 adapter->clean_rx = e1000_clean_rx_irq_ps;
3195 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
3196 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
3197 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3198 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3199 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
3200 } else {
3201 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3202 adapter->clean_rx = e1000_clean_rx_irq;
3203 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3204 }
3205
3206 /* disable receives while setting up the descriptors */
3207 rctl = er32(RCTL);
3208 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3209 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3210 e1e_flush();
3211 usleep_range(10000, 11000);
3212
3213 if (adapter->flags2 & FLAG2_DMA_BURST) {
3214 /* set the writeback threshold (only takes effect if the RDTR
3215 * is set). set GRAN=1 and write back up to 0x4 worth, and
3216 * enable prefetching of 0x20 Rx descriptors
3217 * granularity = 01
3218 * wthresh = 04,
3219 * hthresh = 04,
3220 * pthresh = 0x20
3221 */
3222 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3223 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3224 }
3225
3226 /* set the Receive Delay Timer Register */
3227 ew32(RDTR, adapter->rx_int_delay);
3228
3229 /* irq moderation */
3230 ew32(RADV, adapter->rx_abs_int_delay);
3231 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
3232 e1000e_write_itr(adapter, adapter->itr);
3233
3234 ctrl_ext = er32(CTRL_EXT);
3235 /* Auto-Mask interrupts upon ICR access */
3236 ctrl_ext |= E1000_CTRL_EXT_IAME;
3237 ew32(IAM, 0xffffffff);
3238 ew32(CTRL_EXT, ctrl_ext);
3239 e1e_flush();
3240
3241 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3242 * the Base and Length of the Rx Descriptor Ring
3243 */
3244 rdba = rx_ring->dma;
3245 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3246 ew32(RDBAH(0), (rdba >> 32));
3247 ew32(RDLEN(0), rdlen);
3248 ew32(RDH(0), 0);
3249 ew32(RDT(0), 0);
3250 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3251 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
3252
3253 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
3254 e1000e_update_rdt_wa(rx_ring, 0);
3255
3256 /* Enable Receive Checksum Offload for TCP and UDP */
3257 rxcsum = er32(RXCSUM);
3258 if (adapter->netdev->features & NETIF_F_RXCSUM)
3259 rxcsum |= E1000_RXCSUM_TUOFL;
3260 else
3261 rxcsum &= ~E1000_RXCSUM_TUOFL;
3262 ew32(RXCSUM, rxcsum);
3263
3264 /* With jumbo frames, excessive C-state transition latencies result
3265 * in dropped transactions.
3266 */
3267 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3268 u32 lat =
3269 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3270 adapter->max_frame_size) * 8 / 1000;
3271
3272 if (adapter->flags & FLAG_IS_ICH) {
3273 u32 rxdctl = er32(RXDCTL(0));
3274
3275 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8));
3276 }
3277
3278 dev_info(&adapter->pdev->dev,
3279 "Some CPU C-states have been disabled in order to enable jumbo frames\n");
3280 cpu_latency_qos_update_request(&adapter->pm_qos_req, lat);
3281 } else {
3282 cpu_latency_qos_update_request(&adapter->pm_qos_req,
3283 PM_QOS_DEFAULT_VALUE);
3284 }
3285
3286 /* Enable Receives */
3287 ew32(RCTL, rctl);
3288}
3289
3290/**
3291 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3292 * @netdev: network interface device structure
3293 *
3294 * Writes multicast address list to the MTA hash table.
3295 * Returns: -ENOMEM on failure
3296 * 0 on no addresses written
3297 * X on writing X addresses to MTA
3298 */
3299static int e1000e_write_mc_addr_list(struct net_device *netdev)
3300{
3301 struct e1000_adapter *adapter = netdev_priv(netdev);
3302 struct e1000_hw *hw = &adapter->hw;
3303 struct netdev_hw_addr *ha;
3304 u8 *mta_list;
3305 int i;
3306
3307 if (netdev_mc_empty(netdev)) {
3308 /* nothing to program, so clear mc list */
3309 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3310 return 0;
3311 }
3312
3313 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC);
3314 if (!mta_list)
3315 return -ENOMEM;
3316
3317 /* update_mc_addr_list expects a packed array of only addresses. */
3318 i = 0;
3319 netdev_for_each_mc_addr(ha, netdev)
3320 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3321
3322 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3323 kfree(mta_list);
3324
3325 return netdev_mc_count(netdev);
3326}
3327
3328/**
3329 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3330 * @netdev: network interface device structure
3331 *
3332 * Writes unicast address list to the RAR table.
3333 * Returns: -ENOMEM on failure/insufficient address space
3334 * 0 on no addresses written
3335 * X on writing X addresses to the RAR table
3336 **/
3337static int e1000e_write_uc_addr_list(struct net_device *netdev)
3338{
3339 struct e1000_adapter *adapter = netdev_priv(netdev);
3340 struct e1000_hw *hw = &adapter->hw;
3341 unsigned int rar_entries;
3342 int count = 0;
3343
3344 rar_entries = hw->mac.ops.rar_get_count(hw);
3345
3346 /* save a rar entry for our hardware address */
3347 rar_entries--;
3348
3349 /* save a rar entry for the LAA workaround */
3350 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3351 rar_entries--;
3352
3353 /* return ENOMEM indicating insufficient memory for addresses */
3354 if (netdev_uc_count(netdev) > rar_entries)
3355 return -ENOMEM;
3356
3357 if (!netdev_uc_empty(netdev) && rar_entries) {
3358 struct netdev_hw_addr *ha;
3359
3360 /* write the addresses in reverse order to avoid write
3361 * combining
3362 */
3363 netdev_for_each_uc_addr(ha, netdev) {
3364 int ret_val;
3365
3366 if (!rar_entries)
3367 break;
3368 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
3369 if (ret_val < 0)
3370 return -ENOMEM;
3371 count++;
3372 }
3373 }
3374
3375 /* zero out the remaining RAR entries not used above */
3376 for (; rar_entries > 0; rar_entries--) {
3377 ew32(RAH(rar_entries), 0);
3378 ew32(RAL(rar_entries), 0);
3379 }
3380 e1e_flush();
3381
3382 return count;
3383}
3384
3385/**
3386 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3387 * @netdev: network interface device structure
3388 *
3389 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3390 * address list or the network interface flags are updated. This routine is
3391 * responsible for configuring the hardware for proper unicast, multicast,
3392 * promiscuous mode, and all-multi behavior.
3393 **/
3394static void e1000e_set_rx_mode(struct net_device *netdev)
3395{
3396 struct e1000_adapter *adapter = netdev_priv(netdev);
3397 struct e1000_hw *hw = &adapter->hw;
3398 u32 rctl;
3399
3400 if (pm_runtime_suspended(netdev->dev.parent))
3401 return;
3402
3403 /* Check for Promiscuous and All Multicast modes */
3404 rctl = er32(RCTL);
3405
3406 /* clear the affected bits */
3407 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3408
3409 if (netdev->flags & IFF_PROMISC) {
3410 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3411 /* Do not hardware filter VLANs in promisc mode */
3412 e1000e_vlan_filter_disable(adapter);
3413 } else {
3414 int count;
3415
3416 if (netdev->flags & IFF_ALLMULTI) {
3417 rctl |= E1000_RCTL_MPE;
3418 } else {
3419 /* Write addresses to the MTA, if the attempt fails
3420 * then we should just turn on promiscuous mode so
3421 * that we can at least receive multicast traffic
3422 */
3423 count = e1000e_write_mc_addr_list(netdev);
3424 if (count < 0)
3425 rctl |= E1000_RCTL_MPE;
3426 }
3427 e1000e_vlan_filter_enable(adapter);
3428 /* Write addresses to available RAR registers, if there is not
3429 * sufficient space to store all the addresses then enable
3430 * unicast promiscuous mode
3431 */
3432 count = e1000e_write_uc_addr_list(netdev);
3433 if (count < 0)
3434 rctl |= E1000_RCTL_UPE;
3435 }
3436
3437 ew32(RCTL, rctl);
3438
3439 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3440 e1000e_vlan_strip_enable(adapter);
3441 else
3442 e1000e_vlan_strip_disable(adapter);
3443}
3444
3445static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3446{
3447 struct e1000_hw *hw = &adapter->hw;
3448 u32 mrqc, rxcsum;
3449 u32 rss_key[10];
3450 int i;
3451
3452 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3453 for (i = 0; i < 10; i++)
3454 ew32(RSSRK(i), rss_key[i]);
3455
3456 /* Direct all traffic to queue 0 */
3457 for (i = 0; i < 32; i++)
3458 ew32(RETA(i), 0);
3459
3460 /* Disable raw packet checksumming so that RSS hash is placed in
3461 * descriptor on writeback.
3462 */
3463 rxcsum = er32(RXCSUM);
3464 rxcsum |= E1000_RXCSUM_PCSD;
3465
3466 ew32(RXCSUM, rxcsum);
3467
3468 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3469 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3470 E1000_MRQC_RSS_FIELD_IPV6 |
3471 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3472 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3473
3474 ew32(MRQC, mrqc);
3475}
3476
3477/**
3478 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3479 * @adapter: board private structure
3480 * @timinca: pointer to returned time increment attributes
3481 *
3482 * Get attributes for incrementing the System Time Register SYSTIML/H at
3483 * the default base frequency, and set the cyclecounter shift value.
3484 **/
3485s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
3486{
3487 struct e1000_hw *hw = &adapter->hw;
3488 u32 incvalue, incperiod, shift;
3489
3490 /* Make sure clock is enabled on I217/I218/I219 before checking
3491 * the frequency
3492 */
3493 if ((hw->mac.type >= e1000_pch_lpt) &&
3494 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3495 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3496 u32 fextnvm7 = er32(FEXTNVM7);
3497
3498 if (!(fextnvm7 & BIT(0))) {
3499 ew32(FEXTNVM7, fextnvm7 | BIT(0));
3500 e1e_flush();
3501 }
3502 }
3503
3504 switch (hw->mac.type) {
3505 case e1000_pch2lan:
3506 /* Stable 96MHz frequency */
3507 incperiod = INCPERIOD_96MHZ;
3508 incvalue = INCVALUE_96MHZ;
3509 shift = INCVALUE_SHIFT_96MHZ;
3510 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3511 break;
3512 case e1000_pch_lpt:
3513 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3514 /* Stable 96MHz frequency */
3515 incperiod = INCPERIOD_96MHZ;
3516 incvalue = INCVALUE_96MHZ;
3517 shift = INCVALUE_SHIFT_96MHZ;
3518 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3519 } else {
3520 /* Stable 25MHz frequency */
3521 incperiod = INCPERIOD_25MHZ;
3522 incvalue = INCVALUE_25MHZ;
3523 shift = INCVALUE_SHIFT_25MHZ;
3524 adapter->cc.shift = shift;
3525 }
3526 break;
3527 case e1000_pch_spt:
3528 /* Stable 24MHz frequency */
3529 incperiod = INCPERIOD_24MHZ;
3530 incvalue = INCVALUE_24MHZ;
3531 shift = INCVALUE_SHIFT_24MHZ;
3532 adapter->cc.shift = shift;
3533 break;
3534 case e1000_pch_cnp:
3535 case e1000_pch_tgp:
3536 case e1000_pch_adp:
3537 case e1000_pch_mtp:
3538 case e1000_pch_lnp:
3539 case e1000_pch_ptp:
3540 case e1000_pch_nvp:
3541 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3542 /* Stable 24MHz frequency */
3543 incperiod = INCPERIOD_24MHZ;
3544 incvalue = INCVALUE_24MHZ;
3545 shift = INCVALUE_SHIFT_24MHZ;
3546 adapter->cc.shift = shift;
3547 } else {
3548 /* Stable 38400KHz frequency */
3549 incperiod = INCPERIOD_38400KHZ;
3550 incvalue = INCVALUE_38400KHZ;
3551 shift = INCVALUE_SHIFT_38400KHZ;
3552 adapter->cc.shift = shift;
3553 }
3554 break;
3555 case e1000_82574:
3556 case e1000_82583:
3557 /* Stable 25MHz frequency */
3558 incperiod = INCPERIOD_25MHZ;
3559 incvalue = INCVALUE_25MHZ;
3560 shift = INCVALUE_SHIFT_25MHZ;
3561 adapter->cc.shift = shift;
3562 break;
3563 default:
3564 return -EINVAL;
3565 }
3566
3567 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3568 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3569
3570 return 0;
3571}
3572
3573/**
3574 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3575 * @adapter: board private structure
3576 * @config: timestamp configuration
3577 *
3578 * Outgoing time stamping can be enabled and disabled. Play nice and
3579 * disable it when requested, although it shouldn't cause any overhead
3580 * when no packet needs it. At most one packet in the queue may be
3581 * marked for time stamping, otherwise it would be impossible to tell
3582 * for sure to which packet the hardware time stamp belongs.
3583 *
3584 * Incoming time stamping has to be configured via the hardware filters.
3585 * Not all combinations are supported, in particular event type has to be
3586 * specified. Matching the kind of event packet is not supported, with the
3587 * exception of "all V2 events regardless of level 2 or 4".
3588 **/
3589static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3590 struct hwtstamp_config *config)
3591{
3592 struct e1000_hw *hw = &adapter->hw;
3593 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3594 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
3595 u32 rxmtrl = 0;
3596 u16 rxudp = 0;
3597 bool is_l4 = false;
3598 bool is_l2 = false;
3599 u32 regval;
3600
3601 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3602 return -EINVAL;
3603
3604 switch (config->tx_type) {
3605 case HWTSTAMP_TX_OFF:
3606 tsync_tx_ctl = 0;
3607 break;
3608 case HWTSTAMP_TX_ON:
3609 break;
3610 default:
3611 return -ERANGE;
3612 }
3613
3614 switch (config->rx_filter) {
3615 case HWTSTAMP_FILTER_NONE:
3616 tsync_rx_ctl = 0;
3617 break;
3618 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3619 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3620 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3621 is_l4 = true;
3622 break;
3623 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3624 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3625 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3626 is_l4 = true;
3627 break;
3628 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3629 /* Also time stamps V2 L2 Path Delay Request/Response */
3630 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3631 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3632 is_l2 = true;
3633 break;
3634 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3635 /* Also time stamps V2 L2 Path Delay Request/Response. */
3636 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3637 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3638 is_l2 = true;
3639 break;
3640 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3641 /* Hardware cannot filter just V2 L4 Sync messages */
3642 fallthrough;
3643 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3644 /* Also time stamps V2 Path Delay Request/Response. */
3645 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3646 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3647 is_l2 = true;
3648 is_l4 = true;
3649 break;
3650 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3651 /* Hardware cannot filter just V2 L4 Delay Request messages */
3652 fallthrough;
3653 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3654 /* Also time stamps V2 Path Delay Request/Response. */
3655 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3656 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3657 is_l2 = true;
3658 is_l4 = true;
3659 break;
3660 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3661 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3662 /* Hardware cannot filter just V2 L4 or L2 Event messages */
3663 fallthrough;
3664 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3665 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3666 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3667 is_l2 = true;
3668 is_l4 = true;
3669 break;
3670 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3671 /* For V1, the hardware can only filter Sync messages or
3672 * Delay Request messages but not both so fall-through to
3673 * time stamp all packets.
3674 */
3675 fallthrough;
3676 case HWTSTAMP_FILTER_NTP_ALL:
3677 case HWTSTAMP_FILTER_ALL:
3678 is_l2 = true;
3679 is_l4 = true;
3680 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3681 config->rx_filter = HWTSTAMP_FILTER_ALL;
3682 break;
3683 default:
3684 return -ERANGE;
3685 }
3686
3687 adapter->hwtstamp_config = *config;
3688
3689 /* enable/disable Tx h/w time stamping */
3690 regval = er32(TSYNCTXCTL);
3691 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3692 regval |= tsync_tx_ctl;
3693 ew32(TSYNCTXCTL, regval);
3694 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3695 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3696 e_err("Timesync Tx Control register not set as expected\n");
3697 return -EAGAIN;
3698 }
3699
3700 /* enable/disable Rx h/w time stamping */
3701 regval = er32(TSYNCRXCTL);
3702 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3703 regval |= tsync_rx_ctl;
3704 ew32(TSYNCRXCTL, regval);
3705 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3706 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3707 (regval & (E1000_TSYNCRXCTL_ENABLED |
3708 E1000_TSYNCRXCTL_TYPE_MASK))) {
3709 e_err("Timesync Rx Control register not set as expected\n");
3710 return -EAGAIN;
3711 }
3712
3713 /* L2: define ethertype filter for time stamped packets */
3714 if (is_l2)
3715 rxmtrl |= ETH_P_1588;
3716
3717 /* define which PTP packets get time stamped */
3718 ew32(RXMTRL, rxmtrl);
3719
3720 /* Filter by destination port */
3721 if (is_l4) {
3722 rxudp = PTP_EV_PORT;
3723 cpu_to_be16s(&rxudp);
3724 }
3725 ew32(RXUDP, rxudp);
3726
3727 e1e_flush();
3728
3729 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3730 er32(RXSTMPH);
3731 er32(TXSTMPH);
3732
3733 return 0;
3734}
3735
3736/**
3737 * e1000_configure - configure the hardware for Rx and Tx
3738 * @adapter: private board structure
3739 **/
3740static void e1000_configure(struct e1000_adapter *adapter)
3741{
3742 struct e1000_ring *rx_ring = adapter->rx_ring;
3743
3744 e1000e_set_rx_mode(adapter->netdev);
3745
3746 e1000_restore_vlan(adapter);
3747 e1000_init_manageability_pt(adapter);
3748
3749 e1000_configure_tx(adapter);
3750
3751 if (adapter->netdev->features & NETIF_F_RXHASH)
3752 e1000e_setup_rss_hash(adapter);
3753 e1000_setup_rctl(adapter);
3754 e1000_configure_rx(adapter);
3755 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
3756}
3757
3758/**
3759 * e1000e_power_up_phy - restore link in case the phy was powered down
3760 * @adapter: address of board private structure
3761 *
3762 * The phy may be powered down to save power and turn off link when the
3763 * driver is unloaded and wake on lan is not enabled (among others)
3764 * *** this routine MUST be followed by a call to e1000e_reset ***
3765 **/
3766void e1000e_power_up_phy(struct e1000_adapter *adapter)
3767{
3768 if (adapter->hw.phy.ops.power_up)
3769 adapter->hw.phy.ops.power_up(&adapter->hw);
3770
3771 adapter->hw.mac.ops.setup_link(&adapter->hw);
3772}
3773
3774/**
3775 * e1000_power_down_phy - Power down the PHY
3776 * @adapter: board private structure
3777 *
3778 * Power down the PHY so no link is implied when interface is down.
3779 * The PHY cannot be powered down if management or WoL is active.
3780 */
3781static void e1000_power_down_phy(struct e1000_adapter *adapter)
3782{
3783 if (adapter->hw.phy.ops.power_down)
3784 adapter->hw.phy.ops.power_down(&adapter->hw);
3785}
3786
3787/**
3788 * e1000_flush_tx_ring - remove all descriptors from the tx_ring
3789 * @adapter: board private structure
3790 *
3791 * We want to clear all pending descriptors from the TX ring.
3792 * zeroing happens when the HW reads the regs. We assign the ring itself as
3793 * the data of the next descriptor. We don't care about the data we are about
3794 * to reset the HW.
3795 */
3796static void e1000_flush_tx_ring(struct e1000_adapter *adapter)
3797{
3798 struct e1000_hw *hw = &adapter->hw;
3799 struct e1000_ring *tx_ring = adapter->tx_ring;
3800 struct e1000_tx_desc *tx_desc = NULL;
3801 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
3802 u16 size = 512;
3803
3804 tctl = er32(TCTL);
3805 ew32(TCTL, tctl | E1000_TCTL_EN);
3806 tdt = er32(TDT(0));
3807 BUG_ON(tdt != tx_ring->next_to_use);
3808 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use);
3809 tx_desc->buffer_addr = cpu_to_le64(tx_ring->dma);
3810
3811 tx_desc->lower.data = cpu_to_le32(txd_lower | size);
3812 tx_desc->upper.data = 0;
3813 /* flush descriptors to memory before notifying the HW */
3814 wmb();
3815 tx_ring->next_to_use++;
3816 if (tx_ring->next_to_use == tx_ring->count)
3817 tx_ring->next_to_use = 0;
3818 ew32(TDT(0), tx_ring->next_to_use);
3819 usleep_range(200, 250);
3820}
3821
3822/**
3823 * e1000_flush_rx_ring - remove all descriptors from the rx_ring
3824 * @adapter: board private structure
3825 *
3826 * Mark all descriptors in the RX ring as consumed and disable the rx ring
3827 */
3828static void e1000_flush_rx_ring(struct e1000_adapter *adapter)
3829{
3830 u32 rctl, rxdctl;
3831 struct e1000_hw *hw = &adapter->hw;
3832
3833 rctl = er32(RCTL);
3834 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3835 e1e_flush();
3836 usleep_range(100, 150);
3837
3838 rxdctl = er32(RXDCTL(0));
3839 /* zero the lower 14 bits (prefetch and host thresholds) */
3840 rxdctl &= 0xffffc000;
3841
3842 /* update thresholds: prefetch threshold to 31, host threshold to 1
3843 * and make sure the granularity is "descriptors" and not "cache lines"
3844 */
3845 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC);
3846
3847 ew32(RXDCTL(0), rxdctl);
3848 /* momentarily enable the RX ring for the changes to take effect */
3849 ew32(RCTL, rctl | E1000_RCTL_EN);
3850 e1e_flush();
3851 usleep_range(100, 150);
3852 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3853}
3854
3855/**
3856 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings
3857 * @adapter: board private structure
3858 *
3859 * In i219, the descriptor rings must be emptied before resetting the HW
3860 * or before changing the device state to D3 during runtime (runtime PM).
3861 *
3862 * Failure to do this will cause the HW to enter a unit hang state which can
3863 * only be released by PCI reset on the device
3864 *
3865 */
3866
3867static void e1000_flush_desc_rings(struct e1000_adapter *adapter)
3868{
3869 u16 hang_state;
3870 u32 fext_nvm11, tdlen;
3871 struct e1000_hw *hw = &adapter->hw;
3872
3873 /* First, disable MULR fix in FEXTNVM11 */
3874 fext_nvm11 = er32(FEXTNVM11);
3875 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
3876 ew32(FEXTNVM11, fext_nvm11);
3877 /* do nothing if we're not in faulty state, or if the queue is empty */
3878 tdlen = er32(TDLEN(0));
3879 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3880 &hang_state);
3881 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
3882 return;
3883 e1000_flush_tx_ring(adapter);
3884 /* recheck, maybe the fault is caused by the rx ring */
3885 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3886 &hang_state);
3887 if (hang_state & FLUSH_DESC_REQUIRED)
3888 e1000_flush_rx_ring(adapter);
3889}
3890
3891/**
3892 * e1000e_systim_reset - reset the timesync registers after a hardware reset
3893 * @adapter: board private structure
3894 *
3895 * When the MAC is reset, all hardware bits for timesync will be reset to the
3896 * default values. This function will restore the settings last in place.
3897 * Since the clock SYSTIME registers are reset, we will simply restore the
3898 * cyclecounter to the kernel real clock time.
3899 **/
3900static void e1000e_systim_reset(struct e1000_adapter *adapter)
3901{
3902 struct ptp_clock_info *info = &adapter->ptp_clock_info;
3903 struct e1000_hw *hw = &adapter->hw;
3904 unsigned long flags;
3905 u32 timinca;
3906 s32 ret_val;
3907
3908 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3909 return;
3910
3911 if (info->adjfine) {
3912 /* restore the previous ptp frequency delta */
3913 ret_val = info->adjfine(info, adapter->ptp_delta);
3914 } else {
3915 /* set the default base frequency if no adjustment possible */
3916 ret_val = e1000e_get_base_timinca(adapter, &timinca);
3917 if (!ret_val)
3918 ew32(TIMINCA, timinca);
3919 }
3920
3921 if (ret_val) {
3922 dev_warn(&adapter->pdev->dev,
3923 "Failed to restore TIMINCA clock rate delta: %d\n",
3924 ret_val);
3925 return;
3926 }
3927
3928 /* reset the systim ns time counter */
3929 spin_lock_irqsave(&adapter->systim_lock, flags);
3930 timecounter_init(&adapter->tc, &adapter->cc,
3931 ktime_to_ns(ktime_get_real()));
3932 spin_unlock_irqrestore(&adapter->systim_lock, flags);
3933
3934 /* restore the previous hwtstamp configuration settings */
3935 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config);
3936}
3937
3938/**
3939 * e1000e_reset - bring the hardware into a known good state
3940 * @adapter: board private structure
3941 *
3942 * This function boots the hardware and enables some settings that
3943 * require a configuration cycle of the hardware - those cannot be
3944 * set/changed during runtime. After reset the device needs to be
3945 * properly configured for Rx, Tx etc.
3946 */
3947void e1000e_reset(struct e1000_adapter *adapter)
3948{
3949 struct e1000_mac_info *mac = &adapter->hw.mac;
3950 struct e1000_fc_info *fc = &adapter->hw.fc;
3951 struct e1000_hw *hw = &adapter->hw;
3952 u32 tx_space, min_tx_space, min_rx_space;
3953 u32 pba = adapter->pba;
3954 u16 hwm;
3955
3956 /* reset Packet Buffer Allocation to default */
3957 ew32(PBA, pba);
3958
3959 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) {
3960 /* To maintain wire speed transmits, the Tx FIFO should be
3961 * large enough to accommodate two full transmit packets,
3962 * rounded up to the next 1KB and expressed in KB. Likewise,
3963 * the Rx FIFO should be large enough to accommodate at least
3964 * one full receive packet and is similarly rounded up and
3965 * expressed in KB.
3966 */
3967 pba = er32(PBA);
3968 /* upper 16 bits has Tx packet buffer allocation size in KB */
3969 tx_space = pba >> 16;
3970 /* lower 16 bits has Rx packet buffer allocation size in KB */
3971 pba &= 0xffff;
3972 /* the Tx fifo also stores 16 bytes of information about the Tx
3973 * but don't include ethernet FCS because hardware appends it
3974 */
3975 min_tx_space = (adapter->max_frame_size +
3976 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
3977 min_tx_space = ALIGN(min_tx_space, 1024);
3978 min_tx_space >>= 10;
3979 /* software strips receive CRC, so leave room for it */
3980 min_rx_space = adapter->max_frame_size;
3981 min_rx_space = ALIGN(min_rx_space, 1024);
3982 min_rx_space >>= 10;
3983
3984 /* If current Tx allocation is less than the min Tx FIFO size,
3985 * and the min Tx FIFO size is less than the current Rx FIFO
3986 * allocation, take space away from current Rx allocation
3987 */
3988 if ((tx_space < min_tx_space) &&
3989 ((min_tx_space - tx_space) < pba)) {
3990 pba -= min_tx_space - tx_space;
3991
3992 /* if short on Rx space, Rx wins and must trump Tx
3993 * adjustment
3994 */
3995 if (pba < min_rx_space)
3996 pba = min_rx_space;
3997 }
3998
3999 ew32(PBA, pba);
4000 }
4001
4002 /* flow control settings
4003 *
4004 * The high water mark must be low enough to fit one full frame
4005 * (or the size used for early receive) above it in the Rx FIFO.
4006 * Set it to the lower of:
4007 * - 90% of the Rx FIFO size, and
4008 * - the full Rx FIFO size minus one full frame
4009 */
4010 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
4011 fc->pause_time = 0xFFFF;
4012 else
4013 fc->pause_time = E1000_FC_PAUSE_TIME;
4014 fc->send_xon = true;
4015 fc->current_mode = fc->requested_mode;
4016
4017 switch (hw->mac.type) {
4018 case e1000_ich9lan:
4019 case e1000_ich10lan:
4020 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4021 pba = 14;
4022 ew32(PBA, pba);
4023 fc->high_water = 0x2800;
4024 fc->low_water = fc->high_water - 8;
4025 break;
4026 }
4027 fallthrough;
4028 default:
4029 hwm = min(((pba << 10) * 9 / 10),
4030 ((pba << 10) - adapter->max_frame_size));
4031
4032 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
4033 fc->low_water = fc->high_water - 8;
4034 break;
4035 case e1000_pchlan:
4036 /* Workaround PCH LOM adapter hangs with certain network
4037 * loads. If hangs persist, try disabling Tx flow control.
4038 */
4039 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4040 fc->high_water = 0x3500;
4041 fc->low_water = 0x1500;
4042 } else {
4043 fc->high_water = 0x5000;
4044 fc->low_water = 0x3000;
4045 }
4046 fc->refresh_time = 0x1000;
4047 break;
4048 case e1000_pch2lan:
4049 case e1000_pch_lpt:
4050 case e1000_pch_spt:
4051 case e1000_pch_cnp:
4052 case e1000_pch_tgp:
4053 case e1000_pch_adp:
4054 case e1000_pch_mtp:
4055 case e1000_pch_lnp:
4056 case e1000_pch_ptp:
4057 case e1000_pch_nvp:
4058 fc->refresh_time = 0xFFFF;
4059 fc->pause_time = 0xFFFF;
4060
4061 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
4062 fc->high_water = 0x05C20;
4063 fc->low_water = 0x05048;
4064 break;
4065 }
4066
4067 pba = 14;
4068 ew32(PBA, pba);
4069 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
4070 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
4071 break;
4072 }
4073
4074 /* Alignment of Tx data is on an arbitrary byte boundary with the
4075 * maximum size per Tx descriptor limited only to the transmit
4076 * allocation of the packet buffer minus 96 bytes with an upper
4077 * limit of 24KB due to receive synchronization limitations.
4078 */
4079 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
4080 24 << 10);
4081
4082 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
4083 * fit in receive buffer.
4084 */
4085 if (adapter->itr_setting & 0x3) {
4086 if ((adapter->max_frame_size * 2) > (pba << 10)) {
4087 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
4088 dev_info(&adapter->pdev->dev,
4089 "Interrupt Throttle Rate off\n");
4090 adapter->flags2 |= FLAG2_DISABLE_AIM;
4091 e1000e_write_itr(adapter, 0);
4092 }
4093 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
4094 dev_info(&adapter->pdev->dev,
4095 "Interrupt Throttle Rate on\n");
4096 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
4097 adapter->itr = 20000;
4098 e1000e_write_itr(adapter, adapter->itr);
4099 }
4100 }
4101
4102 if (hw->mac.type >= e1000_pch_spt)
4103 e1000_flush_desc_rings(adapter);
4104 /* Allow time for pending master requests to run */
4105 mac->ops.reset_hw(hw);
4106
4107 /* For parts with AMT enabled, let the firmware know
4108 * that the network interface is in control
4109 */
4110 if (adapter->flags & FLAG_HAS_AMT)
4111 e1000e_get_hw_control(adapter);
4112
4113 ew32(WUC, 0);
4114
4115 if (mac->ops.init_hw(hw))
4116 e_err("Hardware Error\n");
4117
4118 e1000_update_mng_vlan(adapter);
4119
4120 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
4121 ew32(VET, ETH_P_8021Q);
4122
4123 e1000e_reset_adaptive(hw);
4124
4125 /* restore systim and hwtstamp settings */
4126 e1000e_systim_reset(adapter);
4127
4128 /* Set EEE advertisement as appropriate */
4129 if (adapter->flags2 & FLAG2_HAS_EEE) {
4130 s32 ret_val;
4131 u16 adv_addr;
4132
4133 switch (hw->phy.type) {
4134 case e1000_phy_82579:
4135 adv_addr = I82579_EEE_ADVERTISEMENT;
4136 break;
4137 case e1000_phy_i217:
4138 adv_addr = I217_EEE_ADVERTISEMENT;
4139 break;
4140 default:
4141 dev_err(&adapter->pdev->dev,
4142 "Invalid PHY type setting EEE advertisement\n");
4143 return;
4144 }
4145
4146 ret_val = hw->phy.ops.acquire(hw);
4147 if (ret_val) {
4148 dev_err(&adapter->pdev->dev,
4149 "EEE advertisement - unable to acquire PHY\n");
4150 return;
4151 }
4152
4153 e1000_write_emi_reg_locked(hw, adv_addr,
4154 hw->dev_spec.ich8lan.eee_disable ?
4155 0 : adapter->eee_advert);
4156
4157 hw->phy.ops.release(hw);
4158 }
4159
4160 if (!netif_running(adapter->netdev) &&
4161 !test_bit(__E1000_TESTING, &adapter->state))
4162 e1000_power_down_phy(adapter);
4163
4164 e1000_get_phy_info(hw);
4165
4166 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
4167 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
4168 u16 phy_data = 0;
4169 /* speed up time to link by disabling smart power down, ignore
4170 * the return value of this function because there is nothing
4171 * different we would do if it failed
4172 */
4173 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
4174 phy_data &= ~IGP02E1000_PM_SPD;
4175 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
4176 }
4177 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) {
4178 u32 reg;
4179
4180 /* Fextnvm7 @ 0xe4[2] = 1 */
4181 reg = er32(FEXTNVM7);
4182 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE;
4183 ew32(FEXTNVM7, reg);
4184 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */
4185 reg = er32(FEXTNVM9);
4186 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS |
4187 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4188 ew32(FEXTNVM9, reg);
4189 }
4190
4191}
4192
4193/**
4194 * e1000e_trigger_lsc - trigger an LSC interrupt
4195 * @adapter: board private structure
4196 *
4197 * Fire a link status change interrupt to start the watchdog.
4198 **/
4199static void e1000e_trigger_lsc(struct e1000_adapter *adapter)
4200{
4201 struct e1000_hw *hw = &adapter->hw;
4202
4203 if (adapter->msix_entries)
4204 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER);
4205 else
4206 ew32(ICS, E1000_ICS_LSC);
4207}
4208
4209void e1000e_up(struct e1000_adapter *adapter)
4210{
4211 /* hardware has been reset, we need to reload some things */
4212 e1000_configure(adapter);
4213
4214 clear_bit(__E1000_DOWN, &adapter->state);
4215
4216 if (adapter->msix_entries)
4217 e1000_configure_msix(adapter);
4218 e1000_irq_enable(adapter);
4219
4220 /* Tx queue started by watchdog timer when link is up */
4221
4222 e1000e_trigger_lsc(adapter);
4223}
4224
4225static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
4226{
4227 struct e1000_hw *hw = &adapter->hw;
4228
4229 if (!(adapter->flags2 & FLAG2_DMA_BURST))
4230 return;
4231
4232 /* flush pending descriptor writebacks to memory */
4233 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4234 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4235
4236 /* execute the writes immediately */
4237 e1e_flush();
4238
4239 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
4240 * write is successful
4241 */
4242 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4243 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4244
4245 /* execute the writes immediately */
4246 e1e_flush();
4247}
4248
4249static void e1000e_update_stats(struct e1000_adapter *adapter);
4250
4251/**
4252 * e1000e_down - quiesce the device and optionally reset the hardware
4253 * @adapter: board private structure
4254 * @reset: boolean flag to reset the hardware or not
4255 */
4256void e1000e_down(struct e1000_adapter *adapter, bool reset)
4257{
4258 struct net_device *netdev = adapter->netdev;
4259 struct e1000_hw *hw = &adapter->hw;
4260 u32 tctl, rctl;
4261
4262 /* signal that we're down so the interrupt handler does not
4263 * reschedule our watchdog timer
4264 */
4265 set_bit(__E1000_DOWN, &adapter->state);
4266
4267 netif_carrier_off(netdev);
4268
4269 /* disable receives in the hardware */
4270 rctl = er32(RCTL);
4271 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4272 ew32(RCTL, rctl & ~E1000_RCTL_EN);
4273 /* flush and sleep below */
4274
4275 netif_stop_queue(netdev);
4276
4277 /* disable transmits in the hardware */
4278 tctl = er32(TCTL);
4279 tctl &= ~E1000_TCTL_EN;
4280 ew32(TCTL, tctl);
4281
4282 /* flush both disables and wait for them to finish */
4283 e1e_flush();
4284 usleep_range(10000, 11000);
4285
4286 e1000_irq_disable(adapter);
4287
4288 napi_synchronize(&adapter->napi);
4289
4290 del_timer_sync(&adapter->watchdog_timer);
4291 del_timer_sync(&adapter->phy_info_timer);
4292
4293 spin_lock(&adapter->stats64_lock);
4294 e1000e_update_stats(adapter);
4295 spin_unlock(&adapter->stats64_lock);
4296
4297 e1000e_flush_descriptors(adapter);
4298
4299 adapter->link_speed = 0;
4300 adapter->link_duplex = 0;
4301
4302 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4303 if ((hw->mac.type >= e1000_pch2lan) &&
4304 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4305 e1000_lv_jumbo_workaround_ich8lan(hw, false))
4306 e_dbg("failed to disable jumbo frame workaround mode\n");
4307
4308 if (!pci_channel_offline(adapter->pdev)) {
4309 if (reset)
4310 e1000e_reset(adapter);
4311 else if (hw->mac.type >= e1000_pch_spt)
4312 e1000_flush_desc_rings(adapter);
4313 }
4314 e1000_clean_tx_ring(adapter->tx_ring);
4315 e1000_clean_rx_ring(adapter->rx_ring);
4316}
4317
4318void e1000e_reinit_locked(struct e1000_adapter *adapter)
4319{
4320 might_sleep();
4321 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
4322 usleep_range(1000, 1100);
4323 e1000e_down(adapter, true);
4324 e1000e_up(adapter);
4325 clear_bit(__E1000_RESETTING, &adapter->state);
4326}
4327
4328/**
4329 * e1000e_sanitize_systim - sanitize raw cycle counter reads
4330 * @hw: pointer to the HW structure
4331 * @systim: PHC time value read, sanitized and returned
4332 * @sts: structure to hold system time before and after reading SYSTIML,
4333 * may be NULL
4334 *
4335 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L:
4336 * check to see that the time is incrementing at a reasonable
4337 * rate and is a multiple of incvalue.
4338 **/
4339static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim,
4340 struct ptp_system_timestamp *sts)
4341{
4342 u64 time_delta, rem, temp;
4343 u64 systim_next;
4344 u32 incvalue;
4345 int i;
4346
4347 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK;
4348 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) {
4349 /* latch SYSTIMH on read of SYSTIML */
4350 ptp_read_system_prets(sts);
4351 systim_next = (u64)er32(SYSTIML);
4352 ptp_read_system_postts(sts);
4353 systim_next |= (u64)er32(SYSTIMH) << 32;
4354
4355 time_delta = systim_next - systim;
4356 temp = time_delta;
4357 /* VMWare users have seen incvalue of zero, don't div / 0 */
4358 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0);
4359
4360 systim = systim_next;
4361
4362 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0))
4363 break;
4364 }
4365
4366 return systim;
4367}
4368
4369/**
4370 * e1000e_read_systim - read SYSTIM register
4371 * @adapter: board private structure
4372 * @sts: structure which will contain system time before and after reading
4373 * SYSTIML, may be NULL
4374 **/
4375u64 e1000e_read_systim(struct e1000_adapter *adapter,
4376 struct ptp_system_timestamp *sts)
4377{
4378 struct e1000_hw *hw = &adapter->hw;
4379 u32 systimel, systimel_2, systimeh;
4380 u64 systim;
4381 /* SYSTIMH latching upon SYSTIML read does not work well.
4382 * This means that if SYSTIML overflows after we read it but before
4383 * we read SYSTIMH, the value of SYSTIMH has been incremented and we
4384 * will experience a huge non linear increment in the systime value
4385 * to fix that we test for overflow and if true, we re-read systime.
4386 */
4387 ptp_read_system_prets(sts);
4388 systimel = er32(SYSTIML);
4389 ptp_read_system_postts(sts);
4390 systimeh = er32(SYSTIMH);
4391 /* Is systimel is so large that overflow is possible? */
4392 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) {
4393 ptp_read_system_prets(sts);
4394 systimel_2 = er32(SYSTIML);
4395 ptp_read_system_postts(sts);
4396 if (systimel > systimel_2) {
4397 /* There was an overflow, read again SYSTIMH, and use
4398 * systimel_2
4399 */
4400 systimeh = er32(SYSTIMH);
4401 systimel = systimel_2;
4402 }
4403 }
4404 systim = (u64)systimel;
4405 systim |= (u64)systimeh << 32;
4406
4407 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW)
4408 systim = e1000e_sanitize_systim(hw, systim, sts);
4409
4410 return systim;
4411}
4412
4413/**
4414 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4415 * @cc: cyclecounter structure
4416 **/
4417static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc)
4418{
4419 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4420 cc);
4421
4422 return e1000e_read_systim(adapter, NULL);
4423}
4424
4425/**
4426 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4427 * @adapter: board private structure to initialize
4428 *
4429 * e1000_sw_init initializes the Adapter private data structure.
4430 * Fields are initialized based on PCI device information and
4431 * OS network device settings (MTU size).
4432 **/
4433static int e1000_sw_init(struct e1000_adapter *adapter)
4434{
4435 struct net_device *netdev = adapter->netdev;
4436
4437 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
4438 adapter->rx_ps_bsize0 = 128;
4439 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4440 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4441 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4442 adapter->rx_ring_count = E1000_DEFAULT_RXD;
4443
4444 spin_lock_init(&adapter->stats64_lock);
4445
4446 e1000e_set_interrupt_capability(adapter);
4447
4448 if (e1000_alloc_queues(adapter))
4449 return -ENOMEM;
4450
4451 /* Setup hardware time stamping cyclecounter */
4452 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4453 adapter->cc.read = e1000e_cyclecounter_read;
4454 adapter->cc.mask = CYCLECOUNTER_MASK(64);
4455 adapter->cc.mult = 1;
4456 /* cc.shift set in e1000e_get_base_tininca() */
4457
4458 spin_lock_init(&adapter->systim_lock);
4459 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4460 }
4461
4462 /* Explicitly disable IRQ since the NIC can be in any state. */
4463 e1000_irq_disable(adapter);
4464
4465 set_bit(__E1000_DOWN, &adapter->state);
4466 return 0;
4467}
4468
4469/**
4470 * e1000_intr_msi_test - Interrupt Handler
4471 * @irq: interrupt number
4472 * @data: pointer to a network interface device structure
4473 **/
4474static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
4475{
4476 struct net_device *netdev = data;
4477 struct e1000_adapter *adapter = netdev_priv(netdev);
4478 struct e1000_hw *hw = &adapter->hw;
4479 u32 icr = er32(ICR);
4480
4481 e_dbg("icr is %08X\n", icr);
4482 if (icr & E1000_ICR_RXSEQ) {
4483 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
4484 /* Force memory writes to complete before acknowledging the
4485 * interrupt is handled.
4486 */
4487 wmb();
4488 }
4489
4490 return IRQ_HANDLED;
4491}
4492
4493/**
4494 * e1000_test_msi_interrupt - Returns 0 for successful test
4495 * @adapter: board private struct
4496 *
4497 * code flow taken from tg3.c
4498 **/
4499static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4500{
4501 struct net_device *netdev = adapter->netdev;
4502 struct e1000_hw *hw = &adapter->hw;
4503 int err;
4504
4505 /* poll_enable hasn't been called yet, so don't need disable */
4506 /* clear any pending events */
4507 er32(ICR);
4508
4509 /* free the real vector and request a test handler */
4510 e1000_free_irq(adapter);
4511 e1000e_reset_interrupt_capability(adapter);
4512
4513 /* Assume that the test fails, if it succeeds then the test
4514 * MSI irq handler will unset this flag
4515 */
4516 adapter->flags |= FLAG_MSI_TEST_FAILED;
4517
4518 err = pci_enable_msi(adapter->pdev);
4519 if (err)
4520 goto msi_test_failed;
4521
4522 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
4523 netdev->name, netdev);
4524 if (err) {
4525 pci_disable_msi(adapter->pdev);
4526 goto msi_test_failed;
4527 }
4528
4529 /* Force memory writes to complete before enabling and firing an
4530 * interrupt.
4531 */
4532 wmb();
4533
4534 e1000_irq_enable(adapter);
4535
4536 /* fire an unusual interrupt on the test handler */
4537 ew32(ICS, E1000_ICS_RXSEQ);
4538 e1e_flush();
4539 msleep(100);
4540
4541 e1000_irq_disable(adapter);
4542
4543 rmb(); /* read flags after interrupt has been fired */
4544
4545 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4546 adapter->int_mode = E1000E_INT_MODE_LEGACY;
4547 e_info("MSI interrupt test failed, using legacy interrupt.\n");
4548 } else {
4549 e_dbg("MSI interrupt test succeeded!\n");
4550 }
4551
4552 free_irq(adapter->pdev->irq, netdev);
4553 pci_disable_msi(adapter->pdev);
4554
4555msi_test_failed:
4556 e1000e_set_interrupt_capability(adapter);
4557 return e1000_request_irq(adapter);
4558}
4559
4560/**
4561 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4562 * @adapter: board private struct
4563 *
4564 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4565 **/
4566static int e1000_test_msi(struct e1000_adapter *adapter)
4567{
4568 int err;
4569 u16 pci_cmd;
4570
4571 if (!(adapter->flags & FLAG_MSI_ENABLED))
4572 return 0;
4573
4574 /* disable SERR in case the MSI write causes a master abort */
4575 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4576 if (pci_cmd & PCI_COMMAND_SERR)
4577 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4578 pci_cmd & ~PCI_COMMAND_SERR);
4579
4580 err = e1000_test_msi_interrupt(adapter);
4581
4582 /* re-enable SERR */
4583 if (pci_cmd & PCI_COMMAND_SERR) {
4584 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4585 pci_cmd |= PCI_COMMAND_SERR;
4586 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4587 }
4588
4589 return err;
4590}
4591
4592/**
4593 * e1000e_open - Called when a network interface is made active
4594 * @netdev: network interface device structure
4595 *
4596 * Returns 0 on success, negative value on failure
4597 *
4598 * The open entry point is called when a network interface is made
4599 * active by the system (IFF_UP). At this point all resources needed
4600 * for transmit and receive operations are allocated, the interrupt
4601 * handler is registered with the OS, the watchdog timer is started,
4602 * and the stack is notified that the interface is ready.
4603 **/
4604int e1000e_open(struct net_device *netdev)
4605{
4606 struct e1000_adapter *adapter = netdev_priv(netdev);
4607 struct e1000_hw *hw = &adapter->hw;
4608 struct pci_dev *pdev = adapter->pdev;
4609 int err;
4610 int irq;
4611
4612 /* disallow open during test */
4613 if (test_bit(__E1000_TESTING, &adapter->state))
4614 return -EBUSY;
4615
4616 pm_runtime_get_sync(&pdev->dev);
4617
4618 netif_carrier_off(netdev);
4619 netif_stop_queue(netdev);
4620
4621 /* allocate transmit descriptors */
4622 err = e1000e_setup_tx_resources(adapter->tx_ring);
4623 if (err)
4624 goto err_setup_tx;
4625
4626 /* allocate receive descriptors */
4627 err = e1000e_setup_rx_resources(adapter->rx_ring);
4628 if (err)
4629 goto err_setup_rx;
4630
4631 /* If AMT is enabled, let the firmware know that the network
4632 * interface is now open and reset the part to a known state.
4633 */
4634 if (adapter->flags & FLAG_HAS_AMT) {
4635 e1000e_get_hw_control(adapter);
4636 e1000e_reset(adapter);
4637 }
4638
4639 e1000e_power_up_phy(adapter);
4640
4641 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4642 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4643 e1000_update_mng_vlan(adapter);
4644
4645 /* DMA latency requirement to workaround jumbo issue */
4646 cpu_latency_qos_add_request(&adapter->pm_qos_req, PM_QOS_DEFAULT_VALUE);
4647
4648 /* before we allocate an interrupt, we must be ready to handle it.
4649 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4650 * as soon as we call pci_request_irq, so we have to setup our
4651 * clean_rx handler before we do so.
4652 */
4653 e1000_configure(adapter);
4654
4655 err = e1000_request_irq(adapter);
4656 if (err)
4657 goto err_req_irq;
4658
4659 /* Work around PCIe errata with MSI interrupts causing some chipsets to
4660 * ignore e1000e MSI messages, which means we need to test our MSI
4661 * interrupt now
4662 */
4663 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
4664 err = e1000_test_msi(adapter);
4665 if (err) {
4666 e_err("Interrupt allocation failed\n");
4667 goto err_req_irq;
4668 }
4669 }
4670
4671 /* From here on the code is the same as e1000e_up() */
4672 clear_bit(__E1000_DOWN, &adapter->state);
4673
4674 if (adapter->int_mode == E1000E_INT_MODE_MSIX)
4675 irq = adapter->msix_entries[0].vector;
4676 else
4677 irq = adapter->pdev->irq;
4678
4679 netif_napi_set_irq(&adapter->napi, irq);
4680 napi_enable(&adapter->napi);
4681 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_RX, &adapter->napi);
4682 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_TX, &adapter->napi);
4683
4684 e1000_irq_enable(adapter);
4685
4686 adapter->tx_hang_recheck = false;
4687
4688 hw->mac.get_link_status = true;
4689 pm_runtime_put(&pdev->dev);
4690
4691 e1000e_trigger_lsc(adapter);
4692
4693 return 0;
4694
4695err_req_irq:
4696 cpu_latency_qos_remove_request(&adapter->pm_qos_req);
4697 e1000e_release_hw_control(adapter);
4698 e1000_power_down_phy(adapter);
4699 e1000e_free_rx_resources(adapter->rx_ring);
4700err_setup_rx:
4701 e1000e_free_tx_resources(adapter->tx_ring);
4702err_setup_tx:
4703 e1000e_reset(adapter);
4704 pm_runtime_put_sync(&pdev->dev);
4705
4706 return err;
4707}
4708
4709/**
4710 * e1000e_close - Disables a network interface
4711 * @netdev: network interface device structure
4712 *
4713 * Returns 0, this is not allowed to fail
4714 *
4715 * The close entry point is called when an interface is de-activated
4716 * by the OS. The hardware is still under the drivers control, but
4717 * needs to be disabled. A global MAC reset is issued to stop the
4718 * hardware, and all transmit and receive resources are freed.
4719 **/
4720int e1000e_close(struct net_device *netdev)
4721{
4722 struct e1000_adapter *adapter = netdev_priv(netdev);
4723 struct pci_dev *pdev = adapter->pdev;
4724 int count = E1000_CHECK_RESET_COUNT;
4725
4726 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4727 usleep_range(10000, 11000);
4728
4729 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
4730
4731 pm_runtime_get_sync(&pdev->dev);
4732
4733 if (netif_device_present(netdev)) {
4734 e1000e_down(adapter, true);
4735 e1000_free_irq(adapter);
4736
4737 /* Link status message must follow this format */
4738 netdev_info(netdev, "NIC Link is Down\n");
4739 }
4740
4741 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_RX, NULL);
4742 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_TX, NULL);
4743 napi_disable(&adapter->napi);
4744
4745 e1000e_free_tx_resources(adapter->tx_ring);
4746 e1000e_free_rx_resources(adapter->rx_ring);
4747
4748 /* kill manageability vlan ID if supported, but not if a vlan with
4749 * the same ID is registered on the host OS (let 8021q kill it)
4750 */
4751 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
4752 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4753 adapter->mng_vlan_id);
4754
4755 /* If AMT is enabled, let the firmware know that the network
4756 * interface is now closed
4757 */
4758 if ((adapter->flags & FLAG_HAS_AMT) &&
4759 !test_bit(__E1000_TESTING, &adapter->state))
4760 e1000e_release_hw_control(adapter);
4761
4762 cpu_latency_qos_remove_request(&adapter->pm_qos_req);
4763
4764 pm_runtime_put_sync(&pdev->dev);
4765
4766 return 0;
4767}
4768
4769/**
4770 * e1000_set_mac - Change the Ethernet Address of the NIC
4771 * @netdev: network interface device structure
4772 * @p: pointer to an address structure
4773 *
4774 * Returns 0 on success, negative on failure
4775 **/
4776static int e1000_set_mac(struct net_device *netdev, void *p)
4777{
4778 struct e1000_adapter *adapter = netdev_priv(netdev);
4779 struct e1000_hw *hw = &adapter->hw;
4780 struct sockaddr *addr = p;
4781
4782 if (!is_valid_ether_addr(addr->sa_data))
4783 return -EADDRNOTAVAIL;
4784
4785 eth_hw_addr_set(netdev, addr->sa_data);
4786 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4787
4788 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4789
4790 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4791 /* activate the work around */
4792 e1000e_set_laa_state_82571(&adapter->hw, 1);
4793
4794 /* Hold a copy of the LAA in RAR[14] This is done so that
4795 * between the time RAR[0] gets clobbered and the time it
4796 * gets fixed (in e1000_watchdog), the actual LAA is in one
4797 * of the RARs and no incoming packets directed to this port
4798 * are dropped. Eventually the LAA will be in RAR[0] and
4799 * RAR[14]
4800 */
4801 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4802 adapter->hw.mac.rar_entry_count - 1);
4803 }
4804
4805 return 0;
4806}
4807
4808/**
4809 * e1000e_update_phy_task - work thread to update phy
4810 * @work: pointer to our work struct
4811 *
4812 * this worker thread exists because we must acquire a
4813 * semaphore to read the phy, which we could msleep while
4814 * waiting for it, and we can't msleep in a timer.
4815 **/
4816static void e1000e_update_phy_task(struct work_struct *work)
4817{
4818 struct e1000_adapter *adapter = container_of(work,
4819 struct e1000_adapter,
4820 update_phy_task);
4821 struct e1000_hw *hw = &adapter->hw;
4822
4823 if (test_bit(__E1000_DOWN, &adapter->state))
4824 return;
4825
4826 e1000_get_phy_info(hw);
4827
4828 /* Enable EEE on 82579 after link up */
4829 if (hw->phy.type >= e1000_phy_82579)
4830 e1000_set_eee_pchlan(hw);
4831}
4832
4833/**
4834 * e1000_update_phy_info - timre call-back to update PHY info
4835 * @t: pointer to timer_list containing private info adapter
4836 *
4837 * Need to wait a few seconds after link up to get diagnostic information from
4838 * the phy
4839 **/
4840static void e1000_update_phy_info(struct timer_list *t)
4841{
4842 struct e1000_adapter *adapter = from_timer(adapter, t, phy_info_timer);
4843
4844 if (test_bit(__E1000_DOWN, &adapter->state))
4845 return;
4846
4847 schedule_work(&adapter->update_phy_task);
4848}
4849
4850/**
4851 * e1000e_update_phy_stats - Update the PHY statistics counters
4852 * @adapter: board private structure
4853 *
4854 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4855 **/
4856static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4857{
4858 struct e1000_hw *hw = &adapter->hw;
4859 s32 ret_val;
4860 u16 phy_data;
4861
4862 ret_val = hw->phy.ops.acquire(hw);
4863 if (ret_val)
4864 return;
4865
4866 /* A page set is expensive so check if already on desired page.
4867 * If not, set to the page with the PHY status registers.
4868 */
4869 hw->phy.addr = 1;
4870 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4871 &phy_data);
4872 if (ret_val)
4873 goto release;
4874 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4875 ret_val = hw->phy.ops.set_page(hw,
4876 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4877 if (ret_val)
4878 goto release;
4879 }
4880
4881 /* Single Collision Count */
4882 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4883 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4884 if (!ret_val)
4885 adapter->stats.scc += phy_data;
4886
4887 /* Excessive Collision Count */
4888 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4889 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4890 if (!ret_val)
4891 adapter->stats.ecol += phy_data;
4892
4893 /* Multiple Collision Count */
4894 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4895 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4896 if (!ret_val)
4897 adapter->stats.mcc += phy_data;
4898
4899 /* Late Collision Count */
4900 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4901 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4902 if (!ret_val)
4903 adapter->stats.latecol += phy_data;
4904
4905 /* Collision Count - also used for adaptive IFS */
4906 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4907 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4908 if (!ret_val)
4909 hw->mac.collision_delta = phy_data;
4910
4911 /* Defer Count */
4912 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4913 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4914 if (!ret_val)
4915 adapter->stats.dc += phy_data;
4916
4917 /* Transmit with no CRS */
4918 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4919 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4920 if (!ret_val)
4921 adapter->stats.tncrs += phy_data;
4922
4923release:
4924 hw->phy.ops.release(hw);
4925}
4926
4927/**
4928 * e1000e_update_stats - Update the board statistics counters
4929 * @adapter: board private structure
4930 **/
4931static void e1000e_update_stats(struct e1000_adapter *adapter)
4932{
4933 struct net_device *netdev = adapter->netdev;
4934 struct e1000_hw *hw = &adapter->hw;
4935 struct pci_dev *pdev = adapter->pdev;
4936
4937 /* Prevent stats update while adapter is being reset, or if the pci
4938 * connection is down.
4939 */
4940 if (adapter->link_speed == 0)
4941 return;
4942 if (pci_channel_offline(pdev))
4943 return;
4944
4945 adapter->stats.crcerrs += er32(CRCERRS);
4946 adapter->stats.gprc += er32(GPRC);
4947 adapter->stats.gorc += er32(GORCL);
4948 er32(GORCH); /* Clear gorc */
4949 adapter->stats.bprc += er32(BPRC);
4950 adapter->stats.mprc += er32(MPRC);
4951 adapter->stats.roc += er32(ROC);
4952
4953 adapter->stats.mpc += er32(MPC);
4954
4955 /* Half-duplex statistics */
4956 if (adapter->link_duplex == HALF_DUPLEX) {
4957 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4958 e1000e_update_phy_stats(adapter);
4959 } else {
4960 adapter->stats.scc += er32(SCC);
4961 adapter->stats.ecol += er32(ECOL);
4962 adapter->stats.mcc += er32(MCC);
4963 adapter->stats.latecol += er32(LATECOL);
4964 adapter->stats.dc += er32(DC);
4965
4966 hw->mac.collision_delta = er32(COLC);
4967
4968 if ((hw->mac.type != e1000_82574) &&
4969 (hw->mac.type != e1000_82583))
4970 adapter->stats.tncrs += er32(TNCRS);
4971 }
4972 adapter->stats.colc += hw->mac.collision_delta;
4973 }
4974
4975 adapter->stats.xonrxc += er32(XONRXC);
4976 adapter->stats.xontxc += er32(XONTXC);
4977 adapter->stats.xoffrxc += er32(XOFFRXC);
4978 adapter->stats.xofftxc += er32(XOFFTXC);
4979 adapter->stats.gptc += er32(GPTC);
4980 adapter->stats.gotc += er32(GOTCL);
4981 er32(GOTCH); /* Clear gotc */
4982 adapter->stats.rnbc += er32(RNBC);
4983 adapter->stats.ruc += er32(RUC);
4984
4985 adapter->stats.mptc += er32(MPTC);
4986 adapter->stats.bptc += er32(BPTC);
4987
4988 /* used for adaptive IFS */
4989
4990 hw->mac.tx_packet_delta = er32(TPT);
4991 adapter->stats.tpt += hw->mac.tx_packet_delta;
4992
4993 adapter->stats.algnerrc += er32(ALGNERRC);
4994 adapter->stats.rxerrc += er32(RXERRC);
4995 adapter->stats.cexterr += er32(CEXTERR);
4996 adapter->stats.tsctc += er32(TSCTC);
4997 adapter->stats.tsctfc += er32(TSCTFC);
4998
4999 /* Fill out the OS statistics structure */
5000 netdev->stats.multicast = adapter->stats.mprc;
5001 netdev->stats.collisions = adapter->stats.colc;
5002
5003 /* Rx Errors */
5004
5005 /* RLEC on some newer hardware can be incorrect so build
5006 * our own version based on RUC and ROC
5007 */
5008 netdev->stats.rx_errors = adapter->stats.rxerrc +
5009 adapter->stats.crcerrs + adapter->stats.algnerrc +
5010 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5011 netdev->stats.rx_length_errors = adapter->stats.ruc +
5012 adapter->stats.roc;
5013 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5014 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
5015 netdev->stats.rx_missed_errors = adapter->stats.mpc;
5016
5017 /* Tx Errors */
5018 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
5019 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
5020 netdev->stats.tx_window_errors = adapter->stats.latecol;
5021 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
5022
5023 /* Tx Dropped needs to be maintained elsewhere */
5024
5025 /* Management Stats */
5026 adapter->stats.mgptc += er32(MGTPTC);
5027 adapter->stats.mgprc += er32(MGTPRC);
5028 adapter->stats.mgpdc += er32(MGTPDC);
5029
5030 /* Correctable ECC Errors */
5031 if (hw->mac.type >= e1000_pch_lpt) {
5032 u32 pbeccsts = er32(PBECCSTS);
5033
5034 adapter->corr_errors +=
5035 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
5036 adapter->uncorr_errors +=
5037 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);
5038 }
5039}
5040
5041/**
5042 * e1000_phy_read_status - Update the PHY register status snapshot
5043 * @adapter: board private structure
5044 **/
5045static void e1000_phy_read_status(struct e1000_adapter *adapter)
5046{
5047 struct e1000_hw *hw = &adapter->hw;
5048 struct e1000_phy_regs *phy = &adapter->phy_regs;
5049
5050 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
5051 (er32(STATUS) & E1000_STATUS_LU) &&
5052 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
5053 int ret_val;
5054
5055 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
5056 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
5057 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
5058 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
5059 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
5060 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
5061 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
5062 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
5063 if (ret_val)
5064 e_warn("Error reading PHY register\n");
5065 } else {
5066 /* Do not read PHY registers if link is not up
5067 * Set values to typical power-on defaults
5068 */
5069 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
5070 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
5071 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
5072 BMSR_ERCAP);
5073 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
5074 ADVERTISE_ALL | ADVERTISE_CSMA);
5075 phy->lpa = 0;
5076 phy->expansion = EXPANSION_ENABLENPAGE;
5077 phy->ctrl1000 = ADVERTISE_1000FULL;
5078 phy->stat1000 = 0;
5079 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
5080 }
5081}
5082
5083static void e1000_print_link_info(struct e1000_adapter *adapter)
5084{
5085 struct e1000_hw *hw = &adapter->hw;
5086 u32 ctrl = er32(CTRL);
5087
5088 /* Link status message must follow this format for user tools */
5089 netdev_info(adapter->netdev,
5090 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5091 adapter->link_speed,
5092 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
5093 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
5094 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
5095 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
5096}
5097
5098static bool e1000e_has_link(struct e1000_adapter *adapter)
5099{
5100 struct e1000_hw *hw = &adapter->hw;
5101 bool link_active = false;
5102 s32 ret_val = 0;
5103
5104 /* get_link_status is set on LSC (link status) interrupt or
5105 * Rx sequence error interrupt. get_link_status will stay
5106 * true until the check_for_link establishes link
5107 * for copper adapters ONLY
5108 */
5109 switch (hw->phy.media_type) {
5110 case e1000_media_type_copper:
5111 if (hw->mac.get_link_status) {
5112 ret_val = hw->mac.ops.check_for_link(hw);
5113 link_active = !hw->mac.get_link_status;
5114 } else {
5115 link_active = true;
5116 }
5117 break;
5118 case e1000_media_type_fiber:
5119 ret_val = hw->mac.ops.check_for_link(hw);
5120 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
5121 break;
5122 case e1000_media_type_internal_serdes:
5123 ret_val = hw->mac.ops.check_for_link(hw);
5124 link_active = hw->mac.serdes_has_link;
5125 break;
5126 default:
5127 case e1000_media_type_unknown:
5128 break;
5129 }
5130
5131 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
5132 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
5133 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
5134 e_info("Gigabit has been disabled, downgrading speed\n");
5135 }
5136
5137 return link_active;
5138}
5139
5140static void e1000e_enable_receives(struct e1000_adapter *adapter)
5141{
5142 /* make sure the receive unit is started */
5143 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5144 (adapter->flags & FLAG_RESTART_NOW)) {
5145 struct e1000_hw *hw = &adapter->hw;
5146 u32 rctl = er32(RCTL);
5147
5148 ew32(RCTL, rctl | E1000_RCTL_EN);
5149 adapter->flags &= ~FLAG_RESTART_NOW;
5150 }
5151}
5152
5153static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
5154{
5155 struct e1000_hw *hw = &adapter->hw;
5156
5157 /* With 82574 controllers, PHY needs to be checked periodically
5158 * for hung state and reset, if two calls return true
5159 */
5160 if (e1000_check_phy_82574(hw))
5161 adapter->phy_hang_count++;
5162 else
5163 adapter->phy_hang_count = 0;
5164
5165 if (adapter->phy_hang_count > 1) {
5166 adapter->phy_hang_count = 0;
5167 e_dbg("PHY appears hung - resetting\n");
5168 schedule_work(&adapter->reset_task);
5169 }
5170}
5171
5172/**
5173 * e1000_watchdog - Timer Call-back
5174 * @t: pointer to timer_list containing private info adapter
5175 **/
5176static void e1000_watchdog(struct timer_list *t)
5177{
5178 struct e1000_adapter *adapter = from_timer(adapter, t, watchdog_timer);
5179
5180 /* Do the rest outside of interrupt context */
5181 schedule_work(&adapter->watchdog_task);
5182
5183 /* TODO: make this use queue_delayed_work() */
5184}
5185
5186static void e1000_watchdog_task(struct work_struct *work)
5187{
5188 struct e1000_adapter *adapter = container_of(work,
5189 struct e1000_adapter,
5190 watchdog_task);
5191 struct net_device *netdev = adapter->netdev;
5192 struct e1000_mac_info *mac = &adapter->hw.mac;
5193 struct e1000_phy_info *phy = &adapter->hw.phy;
5194 struct e1000_ring *tx_ring = adapter->tx_ring;
5195 u32 dmoff_exit_timeout = 100, tries = 0;
5196 struct e1000_hw *hw = &adapter->hw;
5197 u32 link, tctl, pcim_state;
5198
5199 if (test_bit(__E1000_DOWN, &adapter->state))
5200 return;
5201
5202 link = e1000e_has_link(adapter);
5203 if ((netif_carrier_ok(netdev)) && link) {
5204 /* Cancel scheduled suspend requests. */
5205 pm_runtime_resume(netdev->dev.parent);
5206
5207 e1000e_enable_receives(adapter);
5208 goto link_up;
5209 }
5210
5211 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
5212 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
5213 e1000_update_mng_vlan(adapter);
5214
5215 if (link) {
5216 if (!netif_carrier_ok(netdev)) {
5217 bool txb2b = true;
5218
5219 /* Cancel scheduled suspend requests. */
5220 pm_runtime_resume(netdev->dev.parent);
5221
5222 /* Checking if MAC is in DMoff state*/
5223 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
5224 pcim_state = er32(STATUS);
5225 while (pcim_state & E1000_STATUS_PCIM_STATE) {
5226 if (tries++ == dmoff_exit_timeout) {
5227 e_dbg("Error in exiting dmoff\n");
5228 break;
5229 }
5230 usleep_range(10000, 20000);
5231 pcim_state = er32(STATUS);
5232
5233 /* Checking if MAC exited DMoff state */
5234 if (!(pcim_state & E1000_STATUS_PCIM_STATE))
5235 e1000_phy_hw_reset(&adapter->hw);
5236 }
5237 }
5238
5239 /* update snapshot of PHY registers on LSC */
5240 e1000_phy_read_status(adapter);
5241 mac->ops.get_link_up_info(&adapter->hw,
5242 &adapter->link_speed,
5243 &adapter->link_duplex);
5244 e1000_print_link_info(adapter);
5245
5246 /* check if SmartSpeed worked */
5247 e1000e_check_downshift(hw);
5248 if (phy->speed_downgraded)
5249 netdev_warn(netdev,
5250 "Link Speed was downgraded by SmartSpeed\n");
5251
5252 /* On supported PHYs, check for duplex mismatch only
5253 * if link has autonegotiated at 10/100 half
5254 */
5255 if ((hw->phy.type == e1000_phy_igp_3 ||
5256 hw->phy.type == e1000_phy_bm) &&
5257 hw->mac.autoneg &&
5258 (adapter->link_speed == SPEED_10 ||
5259 adapter->link_speed == SPEED_100) &&
5260 (adapter->link_duplex == HALF_DUPLEX)) {
5261 u16 autoneg_exp;
5262
5263 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
5264
5265 if (!(autoneg_exp & EXPANSION_NWAY))
5266 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
5267 }
5268
5269 /* adjust timeout factor according to speed/duplex */
5270 adapter->tx_timeout_factor = 1;
5271 switch (adapter->link_speed) {
5272 case SPEED_10:
5273 txb2b = false;
5274 adapter->tx_timeout_factor = 16;
5275 break;
5276 case SPEED_100:
5277 txb2b = false;
5278 adapter->tx_timeout_factor = 10;
5279 break;
5280 }
5281
5282 /* workaround: re-program speed mode bit after
5283 * link-up event
5284 */
5285 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
5286 !txb2b) {
5287 u32 tarc0;
5288
5289 tarc0 = er32(TARC(0));
5290 tarc0 &= ~SPEED_MODE_BIT;
5291 ew32(TARC(0), tarc0);
5292 }
5293
5294 /* enable transmits in the hardware, need to do this
5295 * after setting TARC(0)
5296 */
5297 tctl = er32(TCTL);
5298 tctl |= E1000_TCTL_EN;
5299 ew32(TCTL, tctl);
5300
5301 /* Perform any post-link-up configuration before
5302 * reporting link up.
5303 */
5304 if (phy->ops.cfg_on_link_up)
5305 phy->ops.cfg_on_link_up(hw);
5306
5307 netif_wake_queue(netdev);
5308 netif_carrier_on(netdev);
5309
5310 if (!test_bit(__E1000_DOWN, &adapter->state))
5311 mod_timer(&adapter->phy_info_timer,
5312 round_jiffies(jiffies + 2 * HZ));
5313 }
5314 } else {
5315 if (netif_carrier_ok(netdev)) {
5316 adapter->link_speed = 0;
5317 adapter->link_duplex = 0;
5318 /* Link status message must follow this format */
5319 netdev_info(netdev, "NIC Link is Down\n");
5320 netif_carrier_off(netdev);
5321 netif_stop_queue(netdev);
5322 if (!test_bit(__E1000_DOWN, &adapter->state))
5323 mod_timer(&adapter->phy_info_timer,
5324 round_jiffies(jiffies + 2 * HZ));
5325
5326 /* 8000ES2LAN requires a Rx packet buffer work-around
5327 * on link down event; reset the controller to flush
5328 * the Rx packet buffer.
5329 */
5330 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
5331 adapter->flags |= FLAG_RESTART_NOW;
5332 else
5333 pm_schedule_suspend(netdev->dev.parent,
5334 LINK_TIMEOUT);
5335 }
5336 }
5337
5338link_up:
5339 spin_lock(&adapter->stats64_lock);
5340 e1000e_update_stats(adapter);
5341
5342 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
5343 adapter->tpt_old = adapter->stats.tpt;
5344 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
5345 adapter->colc_old = adapter->stats.colc;
5346
5347 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
5348 adapter->gorc_old = adapter->stats.gorc;
5349 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
5350 adapter->gotc_old = adapter->stats.gotc;
5351 spin_unlock(&adapter->stats64_lock);
5352
5353 /* If the link is lost the controller stops DMA, but
5354 * if there is queued Tx work it cannot be done. So
5355 * reset the controller to flush the Tx packet buffers.
5356 */
5357 if (!netif_carrier_ok(netdev) &&
5358 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
5359 adapter->flags |= FLAG_RESTART_NOW;
5360
5361 /* If reset is necessary, do it outside of interrupt context. */
5362 if (adapter->flags & FLAG_RESTART_NOW) {
5363 schedule_work(&adapter->reset_task);
5364 /* return immediately since reset is imminent */
5365 return;
5366 }
5367
5368 e1000e_update_adaptive(&adapter->hw);
5369
5370 /* Simple mode for Interrupt Throttle Rate (ITR) */
5371 if (adapter->itr_setting == 4) {
5372 /* Symmetric Tx/Rx gets a reduced ITR=2000;
5373 * Total asymmetrical Tx or Rx gets ITR=8000;
5374 * everyone else is between 2000-8000.
5375 */
5376 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5377 u32 dif = (adapter->gotc > adapter->gorc ?
5378 adapter->gotc - adapter->gorc :
5379 adapter->gorc - adapter->gotc) / 10000;
5380 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5381
5382 e1000e_write_itr(adapter, itr);
5383 }
5384
5385 /* Cause software interrupt to ensure Rx ring is cleaned */
5386 if (adapter->msix_entries)
5387 ew32(ICS, adapter->rx_ring->ims_val);
5388 else
5389 ew32(ICS, E1000_ICS_RXDMT0);
5390
5391 /* flush pending descriptors to memory before detecting Tx hang */
5392 e1000e_flush_descriptors(adapter);
5393
5394 /* Force detection of hung controller every watchdog period */
5395 adapter->detect_tx_hung = true;
5396
5397 /* With 82571 controllers, LAA may be overwritten due to controller
5398 * reset from the other port. Set the appropriate LAA in RAR[0]
5399 */
5400 if (e1000e_get_laa_state_82571(hw))
5401 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
5402
5403 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5404 e1000e_check_82574_phy_workaround(adapter);
5405
5406 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5407 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5408 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5409 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5410 er32(RXSTMPH);
5411 adapter->rx_hwtstamp_cleared++;
5412 } else {
5413 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5414 }
5415 }
5416
5417 /* Reset the timer */
5418 if (!test_bit(__E1000_DOWN, &adapter->state))
5419 mod_timer(&adapter->watchdog_timer,
5420 round_jiffies(jiffies + 2 * HZ));
5421}
5422
5423#define E1000_TX_FLAGS_CSUM 0x00000001
5424#define E1000_TX_FLAGS_VLAN 0x00000002
5425#define E1000_TX_FLAGS_TSO 0x00000004
5426#define E1000_TX_FLAGS_IPV4 0x00000008
5427#define E1000_TX_FLAGS_NO_FCS 0x00000010
5428#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5429#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5430#define E1000_TX_FLAGS_VLAN_SHIFT 16
5431
5432static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb,
5433 __be16 protocol)
5434{
5435 struct e1000_context_desc *context_desc;
5436 struct e1000_buffer *buffer_info;
5437 unsigned int i;
5438 u32 cmd_length = 0;
5439 u16 ipcse = 0, mss;
5440 u8 ipcss, ipcso, tucss, tucso, hdr_len;
5441 int err;
5442
5443 if (!skb_is_gso(skb))
5444 return 0;
5445
5446 err = skb_cow_head(skb, 0);
5447 if (err < 0)
5448 return err;
5449
5450 hdr_len = skb_tcp_all_headers(skb);
5451 mss = skb_shinfo(skb)->gso_size;
5452 if (protocol == htons(ETH_P_IP)) {
5453 struct iphdr *iph = ip_hdr(skb);
5454 iph->tot_len = 0;
5455 iph->check = 0;
5456 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
5457 0, IPPROTO_TCP, 0);
5458 cmd_length = E1000_TXD_CMD_IP;
5459 ipcse = skb_transport_offset(skb) - 1;
5460 } else if (skb_is_gso_v6(skb)) {
5461 tcp_v6_gso_csum_prep(skb);
5462 ipcse = 0;
5463 }
5464 ipcss = skb_network_offset(skb);
5465 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5466 tucss = skb_transport_offset(skb);
5467 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
5468
5469 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
5470 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
5471
5472 i = tx_ring->next_to_use;
5473 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5474 buffer_info = &tx_ring->buffer_info[i];
5475
5476 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5477 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5478 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
5479 context_desc->upper_setup.tcp_fields.tucss = tucss;
5480 context_desc->upper_setup.tcp_fields.tucso = tucso;
5481 context_desc->upper_setup.tcp_fields.tucse = 0;
5482 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
5483 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5484 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5485
5486 buffer_info->time_stamp = jiffies;
5487 buffer_info->next_to_watch = i;
5488
5489 i++;
5490 if (i == tx_ring->count)
5491 i = 0;
5492 tx_ring->next_to_use = i;
5493
5494 return 1;
5495}
5496
5497static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb,
5498 __be16 protocol)
5499{
5500 struct e1000_adapter *adapter = tx_ring->adapter;
5501 struct e1000_context_desc *context_desc;
5502 struct e1000_buffer *buffer_info;
5503 unsigned int i;
5504 u8 css;
5505 u32 cmd_len = E1000_TXD_CMD_DEXT;
5506
5507 if (skb->ip_summed != CHECKSUM_PARTIAL)
5508 return false;
5509
5510 switch (protocol) {
5511 case cpu_to_be16(ETH_P_IP):
5512 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5513 cmd_len |= E1000_TXD_CMD_TCP;
5514 break;
5515 case cpu_to_be16(ETH_P_IPV6):
5516 /* XXX not handling all IPV6 headers */
5517 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5518 cmd_len |= E1000_TXD_CMD_TCP;
5519 break;
5520 default:
5521 if (unlikely(net_ratelimit()))
5522 e_warn("checksum_partial proto=%x!\n",
5523 be16_to_cpu(protocol));
5524 break;
5525 }
5526
5527 css = skb_checksum_start_offset(skb);
5528
5529 i = tx_ring->next_to_use;
5530 buffer_info = &tx_ring->buffer_info[i];
5531 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5532
5533 context_desc->lower_setup.ip_config = 0;
5534 context_desc->upper_setup.tcp_fields.tucss = css;
5535 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
5536 context_desc->upper_setup.tcp_fields.tucse = 0;
5537 context_desc->tcp_seg_setup.data = 0;
5538 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5539
5540 buffer_info->time_stamp = jiffies;
5541 buffer_info->next_to_watch = i;
5542
5543 i++;
5544 if (i == tx_ring->count)
5545 i = 0;
5546 tx_ring->next_to_use = i;
5547
5548 return true;
5549}
5550
5551static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5552 unsigned int first, unsigned int max_per_txd,
5553 unsigned int nr_frags)
5554{
5555 struct e1000_adapter *adapter = tx_ring->adapter;
5556 struct pci_dev *pdev = adapter->pdev;
5557 struct e1000_buffer *buffer_info;
5558 unsigned int len = skb_headlen(skb);
5559 unsigned int offset = 0, size, count = 0, i;
5560 unsigned int f, bytecount, segs;
5561
5562 i = tx_ring->next_to_use;
5563
5564 while (len) {
5565 buffer_info = &tx_ring->buffer_info[i];
5566 size = min(len, max_per_txd);
5567
5568 buffer_info->length = size;
5569 buffer_info->time_stamp = jiffies;
5570 buffer_info->next_to_watch = i;
5571 buffer_info->dma = dma_map_single(&pdev->dev,
5572 skb->data + offset,
5573 size, DMA_TO_DEVICE);
5574 buffer_info->mapped_as_page = false;
5575 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5576 goto dma_error;
5577
5578 len -= size;
5579 offset += size;
5580 count++;
5581
5582 if (len) {
5583 i++;
5584 if (i == tx_ring->count)
5585 i = 0;
5586 }
5587 }
5588
5589 for (f = 0; f < nr_frags; f++) {
5590 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
5591
5592 len = skb_frag_size(frag);
5593 offset = 0;
5594
5595 while (len) {
5596 i++;
5597 if (i == tx_ring->count)
5598 i = 0;
5599
5600 buffer_info = &tx_ring->buffer_info[i];
5601 size = min(len, max_per_txd);
5602
5603 buffer_info->length = size;
5604 buffer_info->time_stamp = jiffies;
5605 buffer_info->next_to_watch = i;
5606 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
5607 offset, size,
5608 DMA_TO_DEVICE);
5609 buffer_info->mapped_as_page = true;
5610 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5611 goto dma_error;
5612
5613 len -= size;
5614 offset += size;
5615 count++;
5616 }
5617 }
5618
5619 segs = skb_shinfo(skb)->gso_segs ? : 1;
5620 /* multiply data chunks by size of headers */
5621 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5622
5623 tx_ring->buffer_info[i].skb = skb;
5624 tx_ring->buffer_info[i].segs = segs;
5625 tx_ring->buffer_info[i].bytecount = bytecount;
5626 tx_ring->buffer_info[first].next_to_watch = i;
5627
5628 return count;
5629
5630dma_error:
5631 dev_err(&pdev->dev, "Tx DMA map failed\n");
5632 buffer_info->dma = 0;
5633 if (count)
5634 count--;
5635
5636 while (count--) {
5637 if (i == 0)
5638 i += tx_ring->count;
5639 i--;
5640 buffer_info = &tx_ring->buffer_info[i];
5641 e1000_put_txbuf(tx_ring, buffer_info, true);
5642 }
5643
5644 return 0;
5645}
5646
5647static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
5648{
5649 struct e1000_adapter *adapter = tx_ring->adapter;
5650 struct e1000_tx_desc *tx_desc = NULL;
5651 struct e1000_buffer *buffer_info;
5652 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5653 unsigned int i;
5654
5655 if (tx_flags & E1000_TX_FLAGS_TSO) {
5656 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
5657 E1000_TXD_CMD_TSE;
5658 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5659
5660 if (tx_flags & E1000_TX_FLAGS_IPV4)
5661 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5662 }
5663
5664 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5665 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5666 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5667 }
5668
5669 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5670 txd_lower |= E1000_TXD_CMD_VLE;
5671 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5672 }
5673
5674 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5675 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5676
5677 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5678 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5679 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5680 }
5681
5682 i = tx_ring->next_to_use;
5683
5684 do {
5685 buffer_info = &tx_ring->buffer_info[i];
5686 tx_desc = E1000_TX_DESC(*tx_ring, i);
5687 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
5688 tx_desc->lower.data = cpu_to_le32(txd_lower |
5689 buffer_info->length);
5690 tx_desc->upper.data = cpu_to_le32(txd_upper);
5691
5692 i++;
5693 if (i == tx_ring->count)
5694 i = 0;
5695 } while (--count > 0);
5696
5697 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5698
5699 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5700 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5701 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5702
5703 /* Force memory writes to complete before letting h/w
5704 * know there are new descriptors to fetch. (Only
5705 * applicable for weak-ordered memory model archs,
5706 * such as IA-64).
5707 */
5708 wmb();
5709
5710 tx_ring->next_to_use = i;
5711}
5712
5713#define MINIMUM_DHCP_PACKET_SIZE 282
5714static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5715 struct sk_buff *skb)
5716{
5717 struct e1000_hw *hw = &adapter->hw;
5718 u16 length, offset;
5719
5720 if (skb_vlan_tag_present(skb) &&
5721 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5722 (adapter->hw.mng_cookie.status &
5723 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5724 return 0;
5725
5726 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5727 return 0;
5728
5729 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
5730 return 0;
5731
5732 {
5733 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
5734 struct udphdr *udp;
5735
5736 if (ip->protocol != IPPROTO_UDP)
5737 return 0;
5738
5739 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5740 if (ntohs(udp->dest) != 67)
5741 return 0;
5742
5743 offset = (u8 *)udp + 8 - skb->data;
5744 length = skb->len - offset;
5745 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5746 }
5747
5748 return 0;
5749}
5750
5751static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5752{
5753 struct e1000_adapter *adapter = tx_ring->adapter;
5754
5755 netif_stop_queue(adapter->netdev);
5756 /* Herbert's original patch had:
5757 * smp_mb__after_netif_stop_queue();
5758 * but since that doesn't exist yet, just open code it.
5759 */
5760 smp_mb();
5761
5762 /* We need to check again in a case another CPU has just
5763 * made room available.
5764 */
5765 if (e1000_desc_unused(tx_ring) < size)
5766 return -EBUSY;
5767
5768 /* A reprieve! */
5769 netif_start_queue(adapter->netdev);
5770 ++adapter->restart_queue;
5771 return 0;
5772}
5773
5774static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5775{
5776 BUG_ON(size > tx_ring->count);
5777
5778 if (e1000_desc_unused(tx_ring) >= size)
5779 return 0;
5780 return __e1000_maybe_stop_tx(tx_ring, size);
5781}
5782
5783static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5784 struct net_device *netdev)
5785{
5786 struct e1000_adapter *adapter = netdev_priv(netdev);
5787 struct e1000_ring *tx_ring = adapter->tx_ring;
5788 unsigned int first;
5789 unsigned int tx_flags = 0;
5790 unsigned int len = skb_headlen(skb);
5791 unsigned int nr_frags;
5792 unsigned int mss;
5793 int count = 0;
5794 int tso;
5795 unsigned int f;
5796 __be16 protocol = vlan_get_protocol(skb);
5797
5798 if (test_bit(__E1000_DOWN, &adapter->state)) {
5799 dev_kfree_skb_any(skb);
5800 return NETDEV_TX_OK;
5801 }
5802
5803 if (skb->len <= 0) {
5804 dev_kfree_skb_any(skb);
5805 return NETDEV_TX_OK;
5806 }
5807
5808 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5809 * pad skb in order to meet this minimum size requirement
5810 */
5811 if (skb_put_padto(skb, 17))
5812 return NETDEV_TX_OK;
5813
5814 mss = skb_shinfo(skb)->gso_size;
5815 if (mss) {
5816 u8 hdr_len;
5817
5818 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5819 * points to just header, pull a few bytes of payload from
5820 * frags into skb->data
5821 */
5822 hdr_len = skb_tcp_all_headers(skb);
5823 /* we do this workaround for ES2LAN, but it is un-necessary,
5824 * avoiding it could save a lot of cycles
5825 */
5826 if (skb->data_len && (hdr_len == len)) {
5827 unsigned int pull_size;
5828
5829 pull_size = min_t(unsigned int, 4, skb->data_len);
5830 if (!__pskb_pull_tail(skb, pull_size)) {
5831 e_err("__pskb_pull_tail failed.\n");
5832 dev_kfree_skb_any(skb);
5833 return NETDEV_TX_OK;
5834 }
5835 len = skb_headlen(skb);
5836 }
5837 }
5838
5839 /* reserve a descriptor for the offload context */
5840 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5841 count++;
5842 count++;
5843
5844 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
5845
5846 nr_frags = skb_shinfo(skb)->nr_frags;
5847 for (f = 0; f < nr_frags; f++)
5848 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5849 adapter->tx_fifo_limit);
5850
5851 if (adapter->hw.mac.tx_pkt_filtering)
5852 e1000_transfer_dhcp_info(adapter, skb);
5853
5854 /* need: count + 2 desc gap to keep tail from touching
5855 * head, otherwise try next time
5856 */
5857 if (e1000_maybe_stop_tx(tx_ring, count + 2))
5858 return NETDEV_TX_BUSY;
5859
5860 if (skb_vlan_tag_present(skb)) {
5861 tx_flags |= E1000_TX_FLAGS_VLAN;
5862 tx_flags |= (skb_vlan_tag_get(skb) <<
5863 E1000_TX_FLAGS_VLAN_SHIFT);
5864 }
5865
5866 first = tx_ring->next_to_use;
5867
5868 tso = e1000_tso(tx_ring, skb, protocol);
5869 if (tso < 0) {
5870 dev_kfree_skb_any(skb);
5871 return NETDEV_TX_OK;
5872 }
5873
5874 if (tso)
5875 tx_flags |= E1000_TX_FLAGS_TSO;
5876 else if (e1000_tx_csum(tx_ring, skb, protocol))
5877 tx_flags |= E1000_TX_FLAGS_CSUM;
5878
5879 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5880 * 82571 hardware supports TSO capabilities for IPv6 as well...
5881 * no longer assume, we must.
5882 */
5883 if (protocol == htons(ETH_P_IP))
5884 tx_flags |= E1000_TX_FLAGS_IPV4;
5885
5886 if (unlikely(skb->no_fcs))
5887 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5888
5889 /* if count is 0 then mapping error has occurred */
5890 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5891 nr_frags);
5892 if (count) {
5893 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5894 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) {
5895 if (!adapter->tx_hwtstamp_skb) {
5896 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5897 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5898 adapter->tx_hwtstamp_skb = skb_get(skb);
5899 adapter->tx_hwtstamp_start = jiffies;
5900 schedule_work(&adapter->tx_hwtstamp_work);
5901 } else {
5902 adapter->tx_hwtstamp_skipped++;
5903 }
5904 }
5905
5906 skb_tx_timestamp(skb);
5907
5908 netdev_sent_queue(netdev, skb->len);
5909 e1000_tx_queue(tx_ring, tx_flags, count);
5910 /* Make sure there is space in the ring for the next send. */
5911 e1000_maybe_stop_tx(tx_ring,
5912 ((MAX_SKB_FRAGS + 1) *
5913 DIV_ROUND_UP(PAGE_SIZE,
5914 adapter->tx_fifo_limit) + 4));
5915
5916 if (!netdev_xmit_more() ||
5917 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) {
5918 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
5919 e1000e_update_tdt_wa(tx_ring,
5920 tx_ring->next_to_use);
5921 else
5922 writel(tx_ring->next_to_use, tx_ring->tail);
5923 }
5924 } else {
5925 dev_kfree_skb_any(skb);
5926 tx_ring->buffer_info[first].time_stamp = 0;
5927 tx_ring->next_to_use = first;
5928 }
5929
5930 return NETDEV_TX_OK;
5931}
5932
5933/**
5934 * e1000_tx_timeout - Respond to a Tx Hang
5935 * @netdev: network interface device structure
5936 * @txqueue: index of the hung queue (unused)
5937 **/
5938static void e1000_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
5939{
5940 struct e1000_adapter *adapter = netdev_priv(netdev);
5941
5942 /* Do the reset outside of interrupt context */
5943 adapter->tx_timeout_count++;
5944 schedule_work(&adapter->reset_task);
5945}
5946
5947static void e1000_reset_task(struct work_struct *work)
5948{
5949 struct e1000_adapter *adapter;
5950 adapter = container_of(work, struct e1000_adapter, reset_task);
5951
5952 rtnl_lock();
5953 /* don't run the task if already down */
5954 if (test_bit(__E1000_DOWN, &adapter->state)) {
5955 rtnl_unlock();
5956 return;
5957 }
5958
5959 if (!(adapter->flags & FLAG_RESTART_NOW)) {
5960 e1000e_dump(adapter);
5961 e_err("Reset adapter unexpectedly\n");
5962 }
5963 e1000e_reinit_locked(adapter);
5964 rtnl_unlock();
5965}
5966
5967/**
5968 * e1000e_get_stats64 - Get System Network Statistics
5969 * @netdev: network interface device structure
5970 * @stats: rtnl_link_stats64 pointer
5971 *
5972 * Returns the address of the device statistics structure.
5973 **/
5974void e1000e_get_stats64(struct net_device *netdev,
5975 struct rtnl_link_stats64 *stats)
5976{
5977 struct e1000_adapter *adapter = netdev_priv(netdev);
5978
5979 spin_lock(&adapter->stats64_lock);
5980 e1000e_update_stats(adapter);
5981 /* Fill out the OS statistics structure */
5982 stats->rx_bytes = adapter->stats.gorc;
5983 stats->rx_packets = adapter->stats.gprc;
5984 stats->tx_bytes = adapter->stats.gotc;
5985 stats->tx_packets = adapter->stats.gptc;
5986 stats->multicast = adapter->stats.mprc;
5987 stats->collisions = adapter->stats.colc;
5988
5989 /* Rx Errors */
5990
5991 /* RLEC on some newer hardware can be incorrect so build
5992 * our own version based on RUC and ROC
5993 */
5994 stats->rx_errors = adapter->stats.rxerrc +
5995 adapter->stats.crcerrs + adapter->stats.algnerrc +
5996 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5997 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
5998 stats->rx_crc_errors = adapter->stats.crcerrs;
5999 stats->rx_frame_errors = adapter->stats.algnerrc;
6000 stats->rx_missed_errors = adapter->stats.mpc;
6001
6002 /* Tx Errors */
6003 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
6004 stats->tx_aborted_errors = adapter->stats.ecol;
6005 stats->tx_window_errors = adapter->stats.latecol;
6006 stats->tx_carrier_errors = adapter->stats.tncrs;
6007
6008 /* Tx Dropped needs to be maintained elsewhere */
6009
6010 spin_unlock(&adapter->stats64_lock);
6011}
6012
6013/**
6014 * e1000_change_mtu - Change the Maximum Transfer Unit
6015 * @netdev: network interface device structure
6016 * @new_mtu: new value for maximum frame size
6017 *
6018 * Returns 0 on success, negative on failure
6019 **/
6020static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
6021{
6022 struct e1000_adapter *adapter = netdev_priv(netdev);
6023 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6024
6025 /* Jumbo frame support */
6026 if ((new_mtu > ETH_DATA_LEN) &&
6027 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
6028 e_err("Jumbo Frames not supported.\n");
6029 return -EINVAL;
6030 }
6031
6032 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6033 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
6034 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
6035 (new_mtu > ETH_DATA_LEN)) {
6036 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
6037 return -EINVAL;
6038 }
6039
6040 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
6041 usleep_range(1000, 1100);
6042 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
6043 adapter->max_frame_size = max_frame;
6044 netdev_dbg(netdev, "changing MTU from %d to %d\n",
6045 netdev->mtu, new_mtu);
6046 WRITE_ONCE(netdev->mtu, new_mtu);
6047
6048 pm_runtime_get_sync(netdev->dev.parent);
6049
6050 if (netif_running(netdev))
6051 e1000e_down(adapter, true);
6052
6053 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
6054 * means we reserve 2 more, this pushes us to allocate from the next
6055 * larger slab size.
6056 * i.e. RXBUFFER_2048 --> size-4096 slab
6057 * However with the new *_jumbo_rx* routines, jumbo receives will use
6058 * fragmented skbs
6059 */
6060
6061 if (max_frame <= 2048)
6062 adapter->rx_buffer_len = 2048;
6063 else
6064 adapter->rx_buffer_len = 4096;
6065
6066 /* adjust allocation if LPE protects us, and we aren't using SBP */
6067 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN))
6068 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
6069
6070 if (netif_running(netdev))
6071 e1000e_up(adapter);
6072 else
6073 e1000e_reset(adapter);
6074
6075 pm_runtime_put_sync(netdev->dev.parent);
6076
6077 clear_bit(__E1000_RESETTING, &adapter->state);
6078
6079 return 0;
6080}
6081
6082static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
6083 int cmd)
6084{
6085 struct e1000_adapter *adapter = netdev_priv(netdev);
6086 struct mii_ioctl_data *data = if_mii(ifr);
6087
6088 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6089 return -EOPNOTSUPP;
6090
6091 switch (cmd) {
6092 case SIOCGMIIPHY:
6093 data->phy_id = adapter->hw.phy.addr;
6094 break;
6095 case SIOCGMIIREG:
6096 e1000_phy_read_status(adapter);
6097
6098 switch (data->reg_num & 0x1F) {
6099 case MII_BMCR:
6100 data->val_out = adapter->phy_regs.bmcr;
6101 break;
6102 case MII_BMSR:
6103 data->val_out = adapter->phy_regs.bmsr;
6104 break;
6105 case MII_PHYSID1:
6106 data->val_out = (adapter->hw.phy.id >> 16);
6107 break;
6108 case MII_PHYSID2:
6109 data->val_out = (adapter->hw.phy.id & 0xFFFF);
6110 break;
6111 case MII_ADVERTISE:
6112 data->val_out = adapter->phy_regs.advertise;
6113 break;
6114 case MII_LPA:
6115 data->val_out = adapter->phy_regs.lpa;
6116 break;
6117 case MII_EXPANSION:
6118 data->val_out = adapter->phy_regs.expansion;
6119 break;
6120 case MII_CTRL1000:
6121 data->val_out = adapter->phy_regs.ctrl1000;
6122 break;
6123 case MII_STAT1000:
6124 data->val_out = adapter->phy_regs.stat1000;
6125 break;
6126 case MII_ESTATUS:
6127 data->val_out = adapter->phy_regs.estatus;
6128 break;
6129 default:
6130 return -EIO;
6131 }
6132 break;
6133 case SIOCSMIIREG:
6134 default:
6135 return -EOPNOTSUPP;
6136 }
6137 return 0;
6138}
6139
6140/**
6141 * e1000e_hwtstamp_set - control hardware time stamping
6142 * @netdev: network interface device structure
6143 * @ifr: interface request
6144 *
6145 * Outgoing time stamping can be enabled and disabled. Play nice and
6146 * disable it when requested, although it shouldn't cause any overhead
6147 * when no packet needs it. At most one packet in the queue may be
6148 * marked for time stamping, otherwise it would be impossible to tell
6149 * for sure to which packet the hardware time stamp belongs.
6150 *
6151 * Incoming time stamping has to be configured via the hardware filters.
6152 * Not all combinations are supported, in particular event type has to be
6153 * specified. Matching the kind of event packet is not supported, with the
6154 * exception of "all V2 events regardless of level 2 or 4".
6155 **/
6156static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
6157{
6158 struct e1000_adapter *adapter = netdev_priv(netdev);
6159 struct hwtstamp_config config;
6160 int ret_val;
6161
6162 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
6163 return -EFAULT;
6164
6165 ret_val = e1000e_config_hwtstamp(adapter, &config);
6166 if (ret_val)
6167 return ret_val;
6168
6169 switch (config.rx_filter) {
6170 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6171 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6172 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6173 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6174 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6175 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6176 /* With V2 type filters which specify a Sync or Delay Request,
6177 * Path Delay Request/Response messages are also time stamped
6178 * by hardware so notify the caller the requested packets plus
6179 * some others are time stamped.
6180 */
6181 config.rx_filter = HWTSTAMP_FILTER_SOME;
6182 break;
6183 default:
6184 break;
6185 }
6186
6187 return copy_to_user(ifr->ifr_data, &config,
6188 sizeof(config)) ? -EFAULT : 0;
6189}
6190
6191static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
6192{
6193 struct e1000_adapter *adapter = netdev_priv(netdev);
6194
6195 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config,
6196 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0;
6197}
6198
6199static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6200{
6201 switch (cmd) {
6202 case SIOCGMIIPHY:
6203 case SIOCGMIIREG:
6204 case SIOCSMIIREG:
6205 return e1000_mii_ioctl(netdev, ifr, cmd);
6206 case SIOCSHWTSTAMP:
6207 return e1000e_hwtstamp_set(netdev, ifr);
6208 case SIOCGHWTSTAMP:
6209 return e1000e_hwtstamp_get(netdev, ifr);
6210 default:
6211 return -EOPNOTSUPP;
6212 }
6213}
6214
6215static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
6216{
6217 struct e1000_hw *hw = &adapter->hw;
6218 u32 i, mac_reg, wuc;
6219 u16 phy_reg, wuc_enable;
6220 int retval;
6221
6222 /* copy MAC RARs to PHY RARs */
6223 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
6224
6225 retval = hw->phy.ops.acquire(hw);
6226 if (retval) {
6227 e_err("Could not acquire PHY\n");
6228 return retval;
6229 }
6230
6231 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
6232 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6233 if (retval)
6234 goto release;
6235
6236 /* copy MAC MTA to PHY MTA - only needed for pchlan */
6237 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
6238 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
6239 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
6240 (u16)(mac_reg & 0xFFFF));
6241 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
6242 (u16)((mac_reg >> 16) & 0xFFFF));
6243 }
6244
6245 /* configure PHY Rx Control register */
6246 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
6247 mac_reg = er32(RCTL);
6248 if (mac_reg & E1000_RCTL_UPE)
6249 phy_reg |= BM_RCTL_UPE;
6250 if (mac_reg & E1000_RCTL_MPE)
6251 phy_reg |= BM_RCTL_MPE;
6252 phy_reg &= ~(BM_RCTL_MO_MASK);
6253 if (mac_reg & E1000_RCTL_MO_3)
6254 phy_reg |= (FIELD_GET(E1000_RCTL_MO_3, mac_reg)
6255 << BM_RCTL_MO_SHIFT);
6256 if (mac_reg & E1000_RCTL_BAM)
6257 phy_reg |= BM_RCTL_BAM;
6258 if (mac_reg & E1000_RCTL_PMCF)
6259 phy_reg |= BM_RCTL_PMCF;
6260 mac_reg = er32(CTRL);
6261 if (mac_reg & E1000_CTRL_RFCE)
6262 phy_reg |= BM_RCTL_RFCE;
6263 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
6264
6265 wuc = E1000_WUC_PME_EN;
6266 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
6267 wuc |= E1000_WUC_APME;
6268
6269 /* enable PHY wakeup in MAC register */
6270 ew32(WUFC, wufc);
6271 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
6272 E1000_WUC_PME_STATUS | wuc));
6273
6274 /* configure and enable PHY wakeup in PHY registers */
6275 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
6276 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
6277
6278 /* activate PHY wakeup */
6279 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
6280 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6281 if (retval)
6282 e_err("Could not set PHY Host Wakeup bit\n");
6283release:
6284 hw->phy.ops.release(hw);
6285
6286 return retval;
6287}
6288
6289static void e1000e_flush_lpic(struct pci_dev *pdev)
6290{
6291 struct net_device *netdev = pci_get_drvdata(pdev);
6292 struct e1000_adapter *adapter = netdev_priv(netdev);
6293 struct e1000_hw *hw = &adapter->hw;
6294 u32 ret_val;
6295
6296 pm_runtime_get_sync(netdev->dev.parent);
6297
6298 ret_val = hw->phy.ops.acquire(hw);
6299 if (ret_val)
6300 goto fl_out;
6301
6302 pr_info("EEE TX LPI TIMER: %08X\n",
6303 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT);
6304
6305 hw->phy.ops.release(hw);
6306
6307fl_out:
6308 pm_runtime_put_sync(netdev->dev.parent);
6309}
6310
6311/* S0ix implementation */
6312static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter)
6313{
6314 struct e1000_hw *hw = &adapter->hw;
6315 u32 mac_data;
6316 u16 phy_data;
6317
6318 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID &&
6319 hw->mac.type >= e1000_pch_adp) {
6320 /* Request ME configure the device for S0ix */
6321 mac_data = er32(H2ME);
6322 mac_data |= E1000_H2ME_START_DPG;
6323 mac_data &= ~E1000_H2ME_EXIT_DPG;
6324 trace_e1000e_trace_mac_register(mac_data);
6325 ew32(H2ME, mac_data);
6326 } else {
6327 /* Request driver configure the device to S0ix */
6328 /* Disable the periodic inband message,
6329 * don't request PCIe clock in K1 page770_17[10:9] = 10b
6330 */
6331 e1e_rphy(hw, HV_PM_CTRL, &phy_data);
6332 phy_data &= ~HV_PM_CTRL_K1_CLK_REQ;
6333 phy_data |= BIT(10);
6334 e1e_wphy(hw, HV_PM_CTRL, phy_data);
6335
6336 /* Make sure we don't exit K1 every time a new packet arrives
6337 * 772_29[5] = 1 CS_Mode_Stay_In_K1
6338 */
6339 e1e_rphy(hw, I217_CGFREG, &phy_data);
6340 phy_data |= BIT(5);
6341 e1e_wphy(hw, I217_CGFREG, phy_data);
6342
6343 /* Change the MAC/PHY interface to SMBus
6344 * Force the SMBus in PHY page769_23[0] = 1
6345 * Force the SMBus in MAC CTRL_EXT[11] = 1
6346 */
6347 e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
6348 phy_data |= CV_SMB_CTRL_FORCE_SMBUS;
6349 e1e_wphy(hw, CV_SMB_CTRL, phy_data);
6350 mac_data = er32(CTRL_EXT);
6351 mac_data |= E1000_CTRL_EXT_FORCE_SMBUS;
6352 ew32(CTRL_EXT, mac_data);
6353
6354 /* DFT control: PHY bit: page769_20[0] = 1
6355 * page769_20[7] - PHY PLL stop
6356 * page769_20[8] - PHY go to the electrical idle
6357 * page769_20[9] - PHY serdes disable
6358 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1
6359 */
6360 e1e_rphy(hw, I82579_DFT_CTRL, &phy_data);
6361 phy_data |= BIT(0);
6362 phy_data |= BIT(7);
6363 phy_data |= BIT(8);
6364 phy_data |= BIT(9);
6365 e1e_wphy(hw, I82579_DFT_CTRL, phy_data);
6366
6367 mac_data = er32(EXTCNF_CTRL);
6368 mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
6369 ew32(EXTCNF_CTRL, mac_data);
6370
6371 /* Disable disconnected cable conditioning for Power Gating */
6372 mac_data = er32(DPGFR);
6373 mac_data |= BIT(2);
6374 ew32(DPGFR, mac_data);
6375
6376 /* Enable the Dynamic Clock Gating in the DMA and MAC */
6377 mac_data = er32(CTRL_EXT);
6378 mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN;
6379 ew32(CTRL_EXT, mac_data);
6380 }
6381
6382 /* Enable the Dynamic Power Gating in the MAC */
6383 mac_data = er32(FEXTNVM7);
6384 mac_data |= BIT(22);
6385 ew32(FEXTNVM7, mac_data);
6386
6387 /* Don't wake from dynamic Power Gating with clock request */
6388 mac_data = er32(FEXTNVM12);
6389 mac_data |= BIT(12);
6390 ew32(FEXTNVM12, mac_data);
6391
6392 /* Ungate PGCB clock */
6393 mac_data = er32(FEXTNVM9);
6394 mac_data &= ~BIT(28);
6395 ew32(FEXTNVM9, mac_data);
6396
6397 /* Enable K1 off to enable mPHY Power Gating */
6398 mac_data = er32(FEXTNVM6);
6399 mac_data |= BIT(31);
6400 ew32(FEXTNVM6, mac_data);
6401
6402 /* Enable mPHY power gating for any link and speed */
6403 mac_data = er32(FEXTNVM8);
6404 mac_data |= BIT(9);
6405 ew32(FEXTNVM8, mac_data);
6406
6407 /* No MAC DPG gating SLP_S0 in modern standby
6408 * Switch the logic of the lanphypc to use PMC counter
6409 */
6410 mac_data = er32(FEXTNVM5);
6411 mac_data |= BIT(7);
6412 ew32(FEXTNVM5, mac_data);
6413
6414 /* Disable the time synchronization clock */
6415 mac_data = er32(FEXTNVM7);
6416 mac_data |= BIT(31);
6417 mac_data &= ~BIT(0);
6418 ew32(FEXTNVM7, mac_data);
6419
6420 /* Dynamic Power Gating Enable */
6421 mac_data = er32(CTRL_EXT);
6422 mac_data |= BIT(3);
6423 ew32(CTRL_EXT, mac_data);
6424
6425 /* Check MAC Tx/Rx packet buffer pointers.
6426 * Reset MAC Tx/Rx packet buffer pointers to suppress any
6427 * pending traffic indication that would prevent power gating.
6428 */
6429 mac_data = er32(TDFH);
6430 if (mac_data)
6431 ew32(TDFH, 0);
6432 mac_data = er32(TDFT);
6433 if (mac_data)
6434 ew32(TDFT, 0);
6435 mac_data = er32(TDFHS);
6436 if (mac_data)
6437 ew32(TDFHS, 0);
6438 mac_data = er32(TDFTS);
6439 if (mac_data)
6440 ew32(TDFTS, 0);
6441 mac_data = er32(TDFPC);
6442 if (mac_data)
6443 ew32(TDFPC, 0);
6444 mac_data = er32(RDFH);
6445 if (mac_data)
6446 ew32(RDFH, 0);
6447 mac_data = er32(RDFT);
6448 if (mac_data)
6449 ew32(RDFT, 0);
6450 mac_data = er32(RDFHS);
6451 if (mac_data)
6452 ew32(RDFHS, 0);
6453 mac_data = er32(RDFTS);
6454 if (mac_data)
6455 ew32(RDFTS, 0);
6456 mac_data = er32(RDFPC);
6457 if (mac_data)
6458 ew32(RDFPC, 0);
6459}
6460
6461static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter)
6462{
6463 struct e1000_hw *hw = &adapter->hw;
6464 bool firmware_bug = false;
6465 u32 mac_data;
6466 u16 phy_data;
6467 u32 i = 0;
6468
6469 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID &&
6470 hw->mac.type >= e1000_pch_adp) {
6471 /* Keep the GPT clock enabled for CSME */
6472 mac_data = er32(FEXTNVM);
6473 mac_data |= BIT(3);
6474 ew32(FEXTNVM, mac_data);
6475 /* Request ME unconfigure the device from S0ix */
6476 mac_data = er32(H2ME);
6477 mac_data &= ~E1000_H2ME_START_DPG;
6478 mac_data |= E1000_H2ME_EXIT_DPG;
6479 trace_e1000e_trace_mac_register(mac_data);
6480 ew32(H2ME, mac_data);
6481
6482 /* Poll up to 2.5 seconds for ME to unconfigure DPG.
6483 * If this takes more than 1 second, show a warning indicating a
6484 * firmware bug
6485 */
6486 while (!(er32(EXFWSM) & E1000_EXFWSM_DPG_EXIT_DONE)) {
6487 if (i > 100 && !firmware_bug)
6488 firmware_bug = true;
6489
6490 if (i++ == 250) {
6491 e_dbg("Timeout (firmware bug): %d msec\n",
6492 i * 10);
6493 break;
6494 }
6495
6496 usleep_range(10000, 11000);
6497 }
6498 if (firmware_bug)
6499 e_warn("DPG_EXIT_DONE took %d msec. This is a firmware bug\n",
6500 i * 10);
6501 else
6502 e_dbg("DPG_EXIT_DONE cleared after %d msec\n", i * 10);
6503 } else {
6504 /* Request driver unconfigure the device from S0ix */
6505
6506 /* Cancel disable disconnected cable conditioning
6507 * for Power Gating
6508 */
6509 mac_data = er32(DPGFR);
6510 mac_data &= ~BIT(2);
6511 ew32(DPGFR, mac_data);
6512
6513 /* Disable the Dynamic Clock Gating in the DMA and MAC */
6514 mac_data = er32(CTRL_EXT);
6515 mac_data &= 0xFFF7FFFF;
6516 ew32(CTRL_EXT, mac_data);
6517
6518 /* Enable the periodic inband message,
6519 * Request PCIe clock in K1 page770_17[10:9] =01b
6520 */
6521 e1e_rphy(hw, HV_PM_CTRL, &phy_data);
6522 phy_data &= 0xFBFF;
6523 phy_data |= HV_PM_CTRL_K1_CLK_REQ;
6524 e1e_wphy(hw, HV_PM_CTRL, phy_data);
6525
6526 /* Return back configuration
6527 * 772_29[5] = 0 CS_Mode_Stay_In_K1
6528 */
6529 e1e_rphy(hw, I217_CGFREG, &phy_data);
6530 phy_data &= 0xFFDF;
6531 e1e_wphy(hw, I217_CGFREG, phy_data);
6532
6533 /* Change the MAC/PHY interface to Kumeran
6534 * Unforce the SMBus in PHY page769_23[0] = 0
6535 * Unforce the SMBus in MAC CTRL_EXT[11] = 0
6536 */
6537 e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
6538 phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS;
6539 e1e_wphy(hw, CV_SMB_CTRL, phy_data);
6540 mac_data = er32(CTRL_EXT);
6541 mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS;
6542 ew32(CTRL_EXT, mac_data);
6543 }
6544
6545 /* Disable Dynamic Power Gating */
6546 mac_data = er32(CTRL_EXT);
6547 mac_data &= 0xFFFFFFF7;
6548 ew32(CTRL_EXT, mac_data);
6549
6550 /* Enable the time synchronization clock */
6551 mac_data = er32(FEXTNVM7);
6552 mac_data &= ~BIT(31);
6553 mac_data |= BIT(0);
6554 ew32(FEXTNVM7, mac_data);
6555
6556 /* Disable the Dynamic Power Gating in the MAC */
6557 mac_data = er32(FEXTNVM7);
6558 mac_data &= 0xFFBFFFFF;
6559 ew32(FEXTNVM7, mac_data);
6560
6561 /* Disable mPHY power gating for any link and speed */
6562 mac_data = er32(FEXTNVM8);
6563 mac_data &= ~BIT(9);
6564 ew32(FEXTNVM8, mac_data);
6565
6566 /* Disable K1 off */
6567 mac_data = er32(FEXTNVM6);
6568 mac_data &= ~BIT(31);
6569 ew32(FEXTNVM6, mac_data);
6570
6571 /* Disable Ungate PGCB clock */
6572 mac_data = er32(FEXTNVM9);
6573 mac_data |= BIT(28);
6574 ew32(FEXTNVM9, mac_data);
6575
6576 /* Cancel not waking from dynamic
6577 * Power Gating with clock request
6578 */
6579 mac_data = er32(FEXTNVM12);
6580 mac_data &= ~BIT(12);
6581 ew32(FEXTNVM12, mac_data);
6582
6583 /* Revert the lanphypc logic to use the internal Gbe counter
6584 * and not the PMC counter
6585 */
6586 mac_data = er32(FEXTNVM5);
6587 mac_data &= 0xFFFFFF7F;
6588 ew32(FEXTNVM5, mac_data);
6589}
6590
6591static int e1000e_pm_freeze(struct device *dev)
6592{
6593 struct net_device *netdev = dev_get_drvdata(dev);
6594 struct e1000_adapter *adapter = netdev_priv(netdev);
6595 bool present;
6596
6597 rtnl_lock();
6598
6599 present = netif_device_present(netdev);
6600 netif_device_detach(netdev);
6601
6602 if (present && netif_running(netdev)) {
6603 int count = E1000_CHECK_RESET_COUNT;
6604
6605 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6606 usleep_range(10000, 11000);
6607
6608 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6609
6610 /* Quiesce the device without resetting the hardware */
6611 e1000e_down(adapter, false);
6612 e1000_free_irq(adapter);
6613 }
6614 rtnl_unlock();
6615
6616 e1000e_reset_interrupt_capability(adapter);
6617
6618 /* Allow time for pending master requests to run */
6619 e1000e_disable_pcie_master(&adapter->hw);
6620
6621 return 0;
6622}
6623
6624static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
6625{
6626 struct net_device *netdev = pci_get_drvdata(pdev);
6627 struct e1000_adapter *adapter = netdev_priv(netdev);
6628 struct e1000_hw *hw = &adapter->hw;
6629 u32 ctrl, ctrl_ext, rctl, status, wufc;
6630 int retval = 0;
6631
6632 /* Runtime suspend should only enable wakeup for link changes */
6633 if (runtime)
6634 wufc = E1000_WUFC_LNKC;
6635 else if (device_may_wakeup(&pdev->dev))
6636 wufc = adapter->wol;
6637 else
6638 wufc = 0;
6639
6640 status = er32(STATUS);
6641 if (status & E1000_STATUS_LU)
6642 wufc &= ~E1000_WUFC_LNKC;
6643
6644 if (wufc) {
6645 e1000_setup_rctl(adapter);
6646 e1000e_set_rx_mode(netdev);
6647
6648 /* turn on all-multi mode if wake on multicast is enabled */
6649 if (wufc & E1000_WUFC_MC) {
6650 rctl = er32(RCTL);
6651 rctl |= E1000_RCTL_MPE;
6652 ew32(RCTL, rctl);
6653 }
6654
6655 ctrl = er32(CTRL);
6656 ctrl |= E1000_CTRL_ADVD3WUC;
6657 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
6658 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
6659 ew32(CTRL, ctrl);
6660
6661 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
6662 adapter->hw.phy.media_type ==
6663 e1000_media_type_internal_serdes) {
6664 /* keep the laser running in D3 */
6665 ctrl_ext = er32(CTRL_EXT);
6666 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
6667 ew32(CTRL_EXT, ctrl_ext);
6668 }
6669
6670 if (!runtime)
6671 e1000e_power_up_phy(adapter);
6672
6673 if (adapter->flags & FLAG_IS_ICH)
6674 e1000_suspend_workarounds_ich8lan(&adapter->hw);
6675
6676 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6677 /* enable wakeup by the PHY */
6678 retval = e1000_init_phy_wakeup(adapter, wufc);
6679 if (retval) {
6680 e_err("Failed to enable wakeup\n");
6681 goto skip_phy_configurations;
6682 }
6683 } else {
6684 /* enable wakeup by the MAC */
6685 ew32(WUFC, wufc);
6686 ew32(WUC, E1000_WUC_PME_EN);
6687 }
6688 } else {
6689 ew32(WUC, 0);
6690 ew32(WUFC, 0);
6691
6692 e1000_power_down_phy(adapter);
6693 }
6694
6695 if (adapter->hw.phy.type == e1000_phy_igp_3) {
6696 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
6697 } else if (hw->mac.type >= e1000_pch_lpt) {
6698 if (wufc && !(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) {
6699 /* ULP does not support wake from unicast, multicast
6700 * or broadcast.
6701 */
6702 retval = e1000_enable_ulp_lpt_lp(hw, !runtime);
6703 if (retval) {
6704 e_err("Failed to enable ULP\n");
6705 goto skip_phy_configurations;
6706 }
6707 }
6708 }
6709
6710 /* Ensure that the appropriate bits are set in LPI_CTRL
6711 * for EEE in Sx
6712 */
6713 if ((hw->phy.type >= e1000_phy_i217) &&
6714 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) {
6715 u16 lpi_ctrl = 0;
6716
6717 retval = hw->phy.ops.acquire(hw);
6718 if (!retval) {
6719 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL,
6720 &lpi_ctrl);
6721 if (!retval) {
6722 if (adapter->eee_advert &
6723 hw->dev_spec.ich8lan.eee_lp_ability &
6724 I82579_EEE_100_SUPPORTED)
6725 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
6726 if (adapter->eee_advert &
6727 hw->dev_spec.ich8lan.eee_lp_ability &
6728 I82579_EEE_1000_SUPPORTED)
6729 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
6730
6731 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL,
6732 lpi_ctrl);
6733 }
6734 }
6735 hw->phy.ops.release(hw);
6736 }
6737
6738skip_phy_configurations:
6739 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6740 * would have already happened in close and is redundant.
6741 */
6742 e1000e_release_hw_control(adapter);
6743
6744 pci_clear_master(pdev);
6745
6746 /* The pci-e switch on some quad port adapters will report a
6747 * correctable error when the MAC transitions from D0 to D3. To
6748 * prevent this we need to mask off the correctable errors on the
6749 * downstream port of the pci-e switch.
6750 *
6751 * We don't have the associated upstream bridge while assigning
6752 * the PCI device into guest. For example, the KVM on power is
6753 * one of the cases.
6754 */
6755 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6756 struct pci_dev *us_dev = pdev->bus->self;
6757 u16 devctl;
6758
6759 if (!us_dev)
6760 return 0;
6761
6762 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6763 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6764 (devctl & ~PCI_EXP_DEVCTL_CERE));
6765
6766 pci_save_state(pdev);
6767 pci_prepare_to_sleep(pdev);
6768
6769 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
6770 }
6771
6772 return 0;
6773}
6774
6775/**
6776 * __e1000e_disable_aspm - Disable ASPM states
6777 * @pdev: pointer to PCI device struct
6778 * @state: bit-mask of ASPM states to disable
6779 * @locked: indication if this context holds pci_bus_sem locked.
6780 *
6781 * Some devices *must* have certain ASPM states disabled per hardware errata.
6782 **/
6783static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked)
6784{
6785 struct pci_dev *parent = pdev->bus->self;
6786 u16 aspm_dis_mask = 0;
6787 u16 pdev_aspmc, parent_aspmc;
6788
6789 switch (state) {
6790 case PCIE_LINK_STATE_L0S:
6791 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6792 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6793 fallthrough; /* can't have L1 without L0s */
6794 case PCIE_LINK_STATE_L1:
6795 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6796 break;
6797 default:
6798 return;
6799 }
6800
6801 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6802 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6803
6804 if (parent) {
6805 pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6806 &parent_aspmc);
6807 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6808 }
6809
6810 /* Nothing to do if the ASPM states to be disabled already are */
6811 if (!(pdev_aspmc & aspm_dis_mask) &&
6812 (!parent || !(parent_aspmc & aspm_dis_mask)))
6813 return;
6814
6815 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6816 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6817 "L0s" : "",
6818 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6819 "L1" : "");
6820
6821#ifdef CONFIG_PCIEASPM
6822 if (locked)
6823 pci_disable_link_state_locked(pdev, state);
6824 else
6825 pci_disable_link_state(pdev, state);
6826
6827 /* Double-check ASPM control. If not disabled by the above, the
6828 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6829 * not enabled); override by writing PCI config space directly.
6830 */
6831 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6832 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6833
6834 if (!(aspm_dis_mask & pdev_aspmc))
6835 return;
6836#endif
6837
6838 /* Both device and parent should have the same ASPM setting.
6839 * Disable ASPM in downstream component first and then upstream.
6840 */
6841 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6842
6843 if (parent)
6844 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6845 aspm_dis_mask);
6846}
6847
6848/**
6849 * e1000e_disable_aspm - Disable ASPM states.
6850 * @pdev: pointer to PCI device struct
6851 * @state: bit-mask of ASPM states to disable
6852 *
6853 * This function acquires the pci_bus_sem!
6854 * Some devices *must* have certain ASPM states disabled per hardware errata.
6855 **/
6856static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6857{
6858 __e1000e_disable_aspm(pdev, state, 0);
6859}
6860
6861/**
6862 * e1000e_disable_aspm_locked - Disable ASPM states.
6863 * @pdev: pointer to PCI device struct
6864 * @state: bit-mask of ASPM states to disable
6865 *
6866 * This function must be called with pci_bus_sem acquired!
6867 * Some devices *must* have certain ASPM states disabled per hardware errata.
6868 **/
6869static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state)
6870{
6871 __e1000e_disable_aspm(pdev, state, 1);
6872}
6873
6874static int e1000e_pm_thaw(struct device *dev)
6875{
6876 struct net_device *netdev = dev_get_drvdata(dev);
6877 struct e1000_adapter *adapter = netdev_priv(netdev);
6878 int rc = 0;
6879
6880 e1000e_set_interrupt_capability(adapter);
6881
6882 rtnl_lock();
6883 if (netif_running(netdev)) {
6884 rc = e1000_request_irq(adapter);
6885 if (rc)
6886 goto err_irq;
6887
6888 e1000e_up(adapter);
6889 }
6890
6891 netif_device_attach(netdev);
6892err_irq:
6893 rtnl_unlock();
6894
6895 return rc;
6896}
6897
6898static int __e1000_resume(struct pci_dev *pdev)
6899{
6900 struct net_device *netdev = pci_get_drvdata(pdev);
6901 struct e1000_adapter *adapter = netdev_priv(netdev);
6902 struct e1000_hw *hw = &adapter->hw;
6903 u16 aspm_disable_flag = 0;
6904
6905 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6906 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6907 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6908 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6909 if (aspm_disable_flag)
6910 e1000e_disable_aspm(pdev, aspm_disable_flag);
6911
6912 pci_set_master(pdev);
6913
6914 if (hw->mac.type >= e1000_pch2lan)
6915 e1000_resume_workarounds_pchlan(&adapter->hw);
6916
6917 e1000e_power_up_phy(adapter);
6918
6919 /* report the system wakeup cause from S3/S4 */
6920 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6921 u16 phy_data;
6922
6923 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6924 if (phy_data) {
6925 e_info("PHY Wakeup cause - %s\n",
6926 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6927 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6928 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6929 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6930 phy_data & E1000_WUS_LNKC ?
6931 "Link Status Change" : "other");
6932 }
6933 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6934 } else {
6935 u32 wus = er32(WUS);
6936
6937 if (wus) {
6938 e_info("MAC Wakeup cause - %s\n",
6939 wus & E1000_WUS_EX ? "Unicast Packet" :
6940 wus & E1000_WUS_MC ? "Multicast Packet" :
6941 wus & E1000_WUS_BC ? "Broadcast Packet" :
6942 wus & E1000_WUS_MAG ? "Magic Packet" :
6943 wus & E1000_WUS_LNKC ? "Link Status Change" :
6944 "other");
6945 }
6946 ew32(WUS, ~0);
6947 }
6948
6949 e1000e_reset(adapter);
6950
6951 e1000_init_manageability_pt(adapter);
6952
6953 /* If the controller has AMT, do not set DRV_LOAD until the interface
6954 * is up. For all other cases, let the f/w know that the h/w is now
6955 * under the control of the driver.
6956 */
6957 if (!(adapter->flags & FLAG_HAS_AMT))
6958 e1000e_get_hw_control(adapter);
6959
6960 return 0;
6961}
6962
6963static int e1000e_pm_prepare(struct device *dev)
6964{
6965 return pm_runtime_suspended(dev) &&
6966 pm_suspend_via_firmware();
6967}
6968
6969static int e1000e_pm_suspend(struct device *dev)
6970{
6971 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6972 struct e1000_adapter *adapter = netdev_priv(netdev);
6973 struct pci_dev *pdev = to_pci_dev(dev);
6974 int rc;
6975
6976 e1000e_flush_lpic(pdev);
6977
6978 e1000e_pm_freeze(dev);
6979
6980 rc = __e1000_shutdown(pdev, false);
6981 if (!rc) {
6982 /* Introduce S0ix implementation */
6983 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
6984 e1000e_s0ix_entry_flow(adapter);
6985 }
6986
6987 return 0;
6988}
6989
6990static int e1000e_pm_resume(struct device *dev)
6991{
6992 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6993 struct e1000_adapter *adapter = netdev_priv(netdev);
6994 struct pci_dev *pdev = to_pci_dev(dev);
6995 int rc;
6996
6997 /* Introduce S0ix implementation */
6998 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
6999 e1000e_s0ix_exit_flow(adapter);
7000
7001 rc = __e1000_resume(pdev);
7002 if (rc)
7003 return rc;
7004
7005 return e1000e_pm_thaw(dev);
7006}
7007
7008static __maybe_unused int e1000e_pm_runtime_idle(struct device *dev)
7009{
7010 struct net_device *netdev = dev_get_drvdata(dev);
7011 struct e1000_adapter *adapter = netdev_priv(netdev);
7012 u16 eee_lp;
7013
7014 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability;
7015
7016 if (!e1000e_has_link(adapter)) {
7017 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp;
7018 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);
7019 }
7020
7021 return -EBUSY;
7022}
7023
7024static int e1000e_pm_runtime_resume(struct device *dev)
7025{
7026 struct pci_dev *pdev = to_pci_dev(dev);
7027 struct net_device *netdev = pci_get_drvdata(pdev);
7028 struct e1000_adapter *adapter = netdev_priv(netdev);
7029 int rc;
7030
7031 pdev->pme_poll = true;
7032
7033 rc = __e1000_resume(pdev);
7034 if (rc)
7035 return rc;
7036
7037 if (netdev->flags & IFF_UP)
7038 e1000e_up(adapter);
7039
7040 return rc;
7041}
7042
7043static int e1000e_pm_runtime_suspend(struct device *dev)
7044{
7045 struct pci_dev *pdev = to_pci_dev(dev);
7046 struct net_device *netdev = pci_get_drvdata(pdev);
7047 struct e1000_adapter *adapter = netdev_priv(netdev);
7048
7049 if (netdev->flags & IFF_UP) {
7050 int count = E1000_CHECK_RESET_COUNT;
7051
7052 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
7053 usleep_range(10000, 11000);
7054
7055 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
7056
7057 /* Down the device without resetting the hardware */
7058 e1000e_down(adapter, false);
7059 }
7060
7061 if (__e1000_shutdown(pdev, true)) {
7062 e1000e_pm_runtime_resume(dev);
7063 return -EBUSY;
7064 }
7065
7066 return 0;
7067}
7068
7069static void e1000_shutdown(struct pci_dev *pdev)
7070{
7071 e1000e_flush_lpic(pdev);
7072
7073 e1000e_pm_freeze(&pdev->dev);
7074
7075 __e1000_shutdown(pdev, false);
7076}
7077
7078#ifdef CONFIG_NET_POLL_CONTROLLER
7079
7080static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
7081{
7082 struct net_device *netdev = data;
7083 struct e1000_adapter *adapter = netdev_priv(netdev);
7084
7085 if (adapter->msix_entries) {
7086 int vector, msix_irq;
7087
7088 vector = 0;
7089 msix_irq = adapter->msix_entries[vector].vector;
7090 if (disable_hardirq(msix_irq))
7091 e1000_intr_msix_rx(msix_irq, netdev);
7092 enable_irq(msix_irq);
7093
7094 vector++;
7095 msix_irq = adapter->msix_entries[vector].vector;
7096 if (disable_hardirq(msix_irq))
7097 e1000_intr_msix_tx(msix_irq, netdev);
7098 enable_irq(msix_irq);
7099
7100 vector++;
7101 msix_irq = adapter->msix_entries[vector].vector;
7102 if (disable_hardirq(msix_irq))
7103 e1000_msix_other(msix_irq, netdev);
7104 enable_irq(msix_irq);
7105 }
7106
7107 return IRQ_HANDLED;
7108}
7109
7110/**
7111 * e1000_netpoll
7112 * @netdev: network interface device structure
7113 *
7114 * Polling 'interrupt' - used by things like netconsole to send skbs
7115 * without having to re-enable interrupts. It's not called while
7116 * the interrupt routine is executing.
7117 */
7118static void e1000_netpoll(struct net_device *netdev)
7119{
7120 struct e1000_adapter *adapter = netdev_priv(netdev);
7121
7122 switch (adapter->int_mode) {
7123 case E1000E_INT_MODE_MSIX:
7124 e1000_intr_msix(adapter->pdev->irq, netdev);
7125 break;
7126 case E1000E_INT_MODE_MSI:
7127 if (disable_hardirq(adapter->pdev->irq))
7128 e1000_intr_msi(adapter->pdev->irq, netdev);
7129 enable_irq(adapter->pdev->irq);
7130 break;
7131 default: /* E1000E_INT_MODE_LEGACY */
7132 if (disable_hardirq(adapter->pdev->irq))
7133 e1000_intr(adapter->pdev->irq, netdev);
7134 enable_irq(adapter->pdev->irq);
7135 break;
7136 }
7137}
7138#endif
7139
7140/**
7141 * e1000_io_error_detected - called when PCI error is detected
7142 * @pdev: Pointer to PCI device
7143 * @state: The current pci connection state
7144 *
7145 * This function is called after a PCI bus error affecting
7146 * this device has been detected.
7147 */
7148static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
7149 pci_channel_state_t state)
7150{
7151 e1000e_pm_freeze(&pdev->dev);
7152
7153 if (state == pci_channel_io_perm_failure)
7154 return PCI_ERS_RESULT_DISCONNECT;
7155
7156 pci_disable_device(pdev);
7157
7158 /* Request a slot reset. */
7159 return PCI_ERS_RESULT_NEED_RESET;
7160}
7161
7162/**
7163 * e1000_io_slot_reset - called after the pci bus has been reset.
7164 * @pdev: Pointer to PCI device
7165 *
7166 * Restart the card from scratch, as if from a cold-boot. Implementation
7167 * resembles the first-half of the e1000e_pm_resume routine.
7168 */
7169static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
7170{
7171 struct net_device *netdev = pci_get_drvdata(pdev);
7172 struct e1000_adapter *adapter = netdev_priv(netdev);
7173 struct e1000_hw *hw = &adapter->hw;
7174 u16 aspm_disable_flag = 0;
7175 int err;
7176 pci_ers_result_t result;
7177
7178 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
7179 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7180 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
7181 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7182 if (aspm_disable_flag)
7183 e1000e_disable_aspm_locked(pdev, aspm_disable_flag);
7184
7185 err = pci_enable_device_mem(pdev);
7186 if (err) {
7187 dev_err(&pdev->dev,
7188 "Cannot re-enable PCI device after reset.\n");
7189 result = PCI_ERS_RESULT_DISCONNECT;
7190 } else {
7191 pdev->state_saved = true;
7192 pci_restore_state(pdev);
7193 pci_set_master(pdev);
7194
7195 pci_enable_wake(pdev, PCI_D3hot, 0);
7196 pci_enable_wake(pdev, PCI_D3cold, 0);
7197
7198 e1000e_reset(adapter);
7199 ew32(WUS, ~0);
7200 result = PCI_ERS_RESULT_RECOVERED;
7201 }
7202
7203 return result;
7204}
7205
7206/**
7207 * e1000_io_resume - called when traffic can start flowing again.
7208 * @pdev: Pointer to PCI device
7209 *
7210 * This callback is called when the error recovery driver tells us that
7211 * its OK to resume normal operation. Implementation resembles the
7212 * second-half of the e1000e_pm_resume routine.
7213 */
7214static void e1000_io_resume(struct pci_dev *pdev)
7215{
7216 struct net_device *netdev = pci_get_drvdata(pdev);
7217 struct e1000_adapter *adapter = netdev_priv(netdev);
7218
7219 e1000_init_manageability_pt(adapter);
7220
7221 e1000e_pm_thaw(&pdev->dev);
7222
7223 /* If the controller has AMT, do not set DRV_LOAD until the interface
7224 * is up. For all other cases, let the f/w know that the h/w is now
7225 * under the control of the driver.
7226 */
7227 if (!(adapter->flags & FLAG_HAS_AMT))
7228 e1000e_get_hw_control(adapter);
7229}
7230
7231static void e1000_print_device_info(struct e1000_adapter *adapter)
7232{
7233 struct e1000_hw *hw = &adapter->hw;
7234 struct net_device *netdev = adapter->netdev;
7235 u32 ret_val;
7236 u8 pba_str[E1000_PBANUM_LENGTH];
7237
7238 /* print bus type/speed/width info */
7239 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
7240 /* bus width */
7241 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
7242 "Width x1"),
7243 /* MAC address */
7244 netdev->dev_addr);
7245 e_info("Intel(R) PRO/%s Network Connection\n",
7246 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
7247 ret_val = e1000_read_pba_string_generic(hw, pba_str,
7248 E1000_PBANUM_LENGTH);
7249 if (ret_val)
7250 strscpy((char *)pba_str, "Unknown", sizeof(pba_str));
7251 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
7252 hw->mac.type, hw->phy.type, pba_str);
7253}
7254
7255static void e1000_eeprom_checks(struct e1000_adapter *adapter)
7256{
7257 struct e1000_hw *hw = &adapter->hw;
7258 int ret_val;
7259 u16 buf = 0;
7260
7261 if (hw->mac.type != e1000_82573)
7262 return;
7263
7264 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
7265 le16_to_cpus(&buf);
7266 if (!ret_val && (!(buf & BIT(0)))) {
7267 /* Deep Smart Power Down (DSPD) */
7268 dev_warn(&adapter->pdev->dev,
7269 "Warning: detected DSPD enabled in EEPROM\n");
7270 }
7271}
7272
7273static netdev_features_t e1000_fix_features(struct net_device *netdev,
7274 netdev_features_t features)
7275{
7276 struct e1000_adapter *adapter = netdev_priv(netdev);
7277 struct e1000_hw *hw = &adapter->hw;
7278
7279 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
7280 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN))
7281 features &= ~NETIF_F_RXFCS;
7282
7283 /* Since there is no support for separate Rx/Tx vlan accel
7284 * enable/disable make sure Tx flag is always in same state as Rx.
7285 */
7286 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7287 features |= NETIF_F_HW_VLAN_CTAG_TX;
7288 else
7289 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
7290
7291 return features;
7292}
7293
7294static int e1000_set_features(struct net_device *netdev,
7295 netdev_features_t features)
7296{
7297 struct e1000_adapter *adapter = netdev_priv(netdev);
7298 netdev_features_t changed = features ^ netdev->features;
7299
7300 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
7301 adapter->flags |= FLAG_TSO_FORCE;
7302
7303 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
7304 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
7305 NETIF_F_RXALL)))
7306 return 0;
7307
7308 if (changed & NETIF_F_RXFCS) {
7309 if (features & NETIF_F_RXFCS) {
7310 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7311 } else {
7312 /* We need to take it back to defaults, which might mean
7313 * stripping is still disabled at the adapter level.
7314 */
7315 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
7316 adapter->flags2 |= FLAG2_CRC_STRIPPING;
7317 else
7318 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7319 }
7320 }
7321
7322 netdev->features = features;
7323
7324 if (netif_running(netdev))
7325 e1000e_reinit_locked(adapter);
7326 else
7327 e1000e_reset(adapter);
7328
7329 return 1;
7330}
7331
7332static const struct net_device_ops e1000e_netdev_ops = {
7333 .ndo_open = e1000e_open,
7334 .ndo_stop = e1000e_close,
7335 .ndo_start_xmit = e1000_xmit_frame,
7336 .ndo_get_stats64 = e1000e_get_stats64,
7337 .ndo_set_rx_mode = e1000e_set_rx_mode,
7338 .ndo_set_mac_address = e1000_set_mac,
7339 .ndo_change_mtu = e1000_change_mtu,
7340 .ndo_eth_ioctl = e1000_ioctl,
7341 .ndo_tx_timeout = e1000_tx_timeout,
7342 .ndo_validate_addr = eth_validate_addr,
7343
7344 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
7345 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
7346#ifdef CONFIG_NET_POLL_CONTROLLER
7347 .ndo_poll_controller = e1000_netpoll,
7348#endif
7349 .ndo_set_features = e1000_set_features,
7350 .ndo_fix_features = e1000_fix_features,
7351 .ndo_features_check = passthru_features_check,
7352};
7353
7354/**
7355 * e1000_probe - Device Initialization Routine
7356 * @pdev: PCI device information struct
7357 * @ent: entry in e1000_pci_tbl
7358 *
7359 * Returns 0 on success, negative on failure
7360 *
7361 * e1000_probe initializes an adapter identified by a pci_dev structure.
7362 * The OS initialization, configuring of the adapter private structure,
7363 * and a hardware reset occur.
7364 **/
7365static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7366{
7367 struct net_device *netdev;
7368 struct e1000_adapter *adapter;
7369 struct e1000_hw *hw;
7370 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
7371 resource_size_t mmio_start, mmio_len;
7372 resource_size_t flash_start, flash_len;
7373 static int cards_found;
7374 u16 aspm_disable_flag = 0;
7375 u16 eeprom_data = 0;
7376 u16 eeprom_apme_mask = E1000_EEPROM_APME;
7377 int bars, i, err;
7378 s32 ret_val = 0;
7379
7380 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
7381 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7382 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
7383 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7384 if (aspm_disable_flag)
7385 e1000e_disable_aspm(pdev, aspm_disable_flag);
7386
7387 err = pci_enable_device_mem(pdev);
7388 if (err)
7389 return err;
7390
7391 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7392 if (err) {
7393 dev_err(&pdev->dev,
7394 "No usable DMA configuration, aborting\n");
7395 goto err_dma;
7396 }
7397
7398 bars = pci_select_bars(pdev, IORESOURCE_MEM);
7399 err = pci_request_selected_regions_exclusive(pdev, bars,
7400 e1000e_driver_name);
7401 if (err)
7402 goto err_pci_reg;
7403
7404 pci_set_master(pdev);
7405 /* PCI config space info */
7406 err = pci_save_state(pdev);
7407 if (err)
7408 goto err_alloc_etherdev;
7409
7410 err = -ENOMEM;
7411 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
7412 if (!netdev)
7413 goto err_alloc_etherdev;
7414
7415 SET_NETDEV_DEV(netdev, &pdev->dev);
7416
7417 netdev->irq = pdev->irq;
7418
7419 pci_set_drvdata(pdev, netdev);
7420 adapter = netdev_priv(netdev);
7421 hw = &adapter->hw;
7422 adapter->netdev = netdev;
7423 adapter->pdev = pdev;
7424 adapter->ei = ei;
7425 adapter->pba = ei->pba;
7426 adapter->flags = ei->flags;
7427 adapter->flags2 = ei->flags2;
7428 adapter->hw.adapter = adapter;
7429 adapter->hw.mac.type = ei->mac;
7430 adapter->max_hw_frame_size = ei->max_hw_frame_size;
7431 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7432
7433 mmio_start = pci_resource_start(pdev, 0);
7434 mmio_len = pci_resource_len(pdev, 0);
7435
7436 err = -EIO;
7437 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
7438 if (!adapter->hw.hw_addr)
7439 goto err_ioremap;
7440
7441 if ((adapter->flags & FLAG_HAS_FLASH) &&
7442 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) &&
7443 (hw->mac.type < e1000_pch_spt)) {
7444 flash_start = pci_resource_start(pdev, 1);
7445 flash_len = pci_resource_len(pdev, 1);
7446 adapter->hw.flash_address = ioremap(flash_start, flash_len);
7447 if (!adapter->hw.flash_address)
7448 goto err_flashmap;
7449 }
7450
7451 /* Set default EEE advertisement */
7452 if (adapter->flags2 & FLAG2_HAS_EEE)
7453 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
7454
7455 /* construct the net_device struct */
7456 netdev->netdev_ops = &e1000e_netdev_ops;
7457 e1000e_set_ethtool_ops(netdev);
7458 netdev->watchdog_timeo = 5 * HZ;
7459 netif_napi_add(netdev, &adapter->napi, e1000e_poll);
7460 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
7461
7462 netdev->mem_start = mmio_start;
7463 netdev->mem_end = mmio_start + mmio_len;
7464
7465 adapter->bd_number = cards_found++;
7466
7467 e1000e_check_options(adapter);
7468
7469 /* setup adapter struct */
7470 err = e1000_sw_init(adapter);
7471 if (err)
7472 goto err_sw_init;
7473
7474 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
7475 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
7476 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
7477
7478 err = ei->get_variants(adapter);
7479 if (err)
7480 goto err_hw_init;
7481
7482 if ((adapter->flags & FLAG_IS_ICH) &&
7483 (adapter->flags & FLAG_READ_ONLY_NVM) &&
7484 (hw->mac.type < e1000_pch_spt))
7485 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
7486
7487 hw->mac.ops.get_bus_info(&adapter->hw);
7488
7489 adapter->hw.phy.autoneg_wait_to_complete = 0;
7490
7491 /* Copper options */
7492 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
7493 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7494 adapter->hw.phy.disable_polarity_correction = 0;
7495 adapter->hw.phy.ms_type = e1000_ms_hw_default;
7496 }
7497
7498 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
7499 dev_info(&pdev->dev,
7500 "PHY reset is blocked due to SOL/IDER session.\n");
7501
7502 /* Set initial default active device features */
7503 netdev->features = (NETIF_F_SG |
7504 NETIF_F_HW_VLAN_CTAG_RX |
7505 NETIF_F_HW_VLAN_CTAG_TX |
7506 NETIF_F_TSO |
7507 NETIF_F_TSO6 |
7508 NETIF_F_RXHASH |
7509 NETIF_F_RXCSUM |
7510 NETIF_F_HW_CSUM);
7511
7512 /* disable TSO for pcie and 10/100 speeds to avoid
7513 * some hardware issues and for i219 to fix transfer
7514 * speed being capped at 60%
7515 */
7516 if (!(adapter->flags & FLAG_TSO_FORCE)) {
7517 switch (adapter->link_speed) {
7518 case SPEED_10:
7519 case SPEED_100:
7520 e_info("10/100 speed: disabling TSO\n");
7521 netdev->features &= ~NETIF_F_TSO;
7522 netdev->features &= ~NETIF_F_TSO6;
7523 break;
7524 case SPEED_1000:
7525 netdev->features |= NETIF_F_TSO;
7526 netdev->features |= NETIF_F_TSO6;
7527 break;
7528 default:
7529 /* oops */
7530 break;
7531 }
7532 if (hw->mac.type == e1000_pch_spt) {
7533 netdev->features &= ~NETIF_F_TSO;
7534 netdev->features &= ~NETIF_F_TSO6;
7535 }
7536 }
7537
7538 /* Set user-changeable features (subset of all device features) */
7539 netdev->hw_features = netdev->features;
7540 netdev->hw_features |= NETIF_F_RXFCS;
7541 netdev->priv_flags |= IFF_SUPP_NOFCS;
7542 netdev->hw_features |= NETIF_F_RXALL;
7543
7544 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
7545 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
7546
7547 netdev->vlan_features |= (NETIF_F_SG |
7548 NETIF_F_TSO |
7549 NETIF_F_TSO6 |
7550 NETIF_F_HW_CSUM);
7551
7552 netdev->priv_flags |= IFF_UNICAST_FLT;
7553
7554 netdev->features |= NETIF_F_HIGHDMA;
7555 netdev->vlan_features |= NETIF_F_HIGHDMA;
7556
7557 /* MTU range: 68 - max_hw_frame_size */
7558 netdev->min_mtu = ETH_MIN_MTU;
7559 netdev->max_mtu = adapter->max_hw_frame_size -
7560 (VLAN_ETH_HLEN + ETH_FCS_LEN);
7561
7562 if (e1000e_enable_mng_pass_thru(&adapter->hw))
7563 adapter->flags |= FLAG_MNG_PT_ENABLED;
7564
7565 /* before reading the NVM, reset the controller to
7566 * put the device in a known good starting state
7567 */
7568 adapter->hw.mac.ops.reset_hw(&adapter->hw);
7569
7570 /* systems with ASPM and others may see the checksum fail on the first
7571 * attempt. Let's give it a few tries
7572 */
7573 for (i = 0;; i++) {
7574 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
7575 break;
7576 if (i == 2) {
7577 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
7578 err = -EIO;
7579 goto err_eeprom;
7580 }
7581 }
7582
7583 e1000_eeprom_checks(adapter);
7584
7585 /* copy the MAC address */
7586 if (e1000e_read_mac_addr(&adapter->hw))
7587 dev_err(&pdev->dev,
7588 "NVM Read Error while reading MAC address\n");
7589
7590 eth_hw_addr_set(netdev, adapter->hw.mac.addr);
7591
7592 if (!is_valid_ether_addr(netdev->dev_addr)) {
7593 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
7594 netdev->dev_addr);
7595 err = -EIO;
7596 goto err_eeprom;
7597 }
7598
7599 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0);
7600 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0);
7601
7602 INIT_WORK(&adapter->reset_task, e1000_reset_task);
7603 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
7604 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
7605 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
7606 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
7607
7608 /* Initialize link parameters. User can change them with ethtool */
7609 adapter->hw.mac.autoneg = 1;
7610 adapter->fc_autoneg = true;
7611 adapter->hw.fc.requested_mode = e1000_fc_default;
7612 adapter->hw.fc.current_mode = e1000_fc_default;
7613 adapter->hw.phy.autoneg_advertised = 0x2f;
7614
7615 /* Initial Wake on LAN setting - If APM wake is enabled in
7616 * the EEPROM, enable the ACPI Magic Packet filter
7617 */
7618 if (adapter->flags & FLAG_APME_IN_WUC) {
7619 /* APME bit in EEPROM is mapped to WUC.APME */
7620 eeprom_data = er32(WUC);
7621 eeprom_apme_mask = E1000_WUC_APME;
7622 if ((hw->mac.type > e1000_ich10lan) &&
7623 (eeprom_data & E1000_WUC_PHY_WAKE))
7624 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
7625 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
7626 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
7627 (adapter->hw.bus.func == 1))
7628 ret_val = e1000_read_nvm(&adapter->hw,
7629 NVM_INIT_CONTROL3_PORT_B,
7630 1, &eeprom_data);
7631 else
7632 ret_val = e1000_read_nvm(&adapter->hw,
7633 NVM_INIT_CONTROL3_PORT_A,
7634 1, &eeprom_data);
7635 }
7636
7637 /* fetch WoL from EEPROM */
7638 if (ret_val)
7639 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val);
7640 else if (eeprom_data & eeprom_apme_mask)
7641 adapter->eeprom_wol |= E1000_WUFC_MAG;
7642
7643 /* now that we have the eeprom settings, apply the special cases
7644 * where the eeprom may be wrong or the board simply won't support
7645 * wake on lan on a particular port
7646 */
7647 if (!(adapter->flags & FLAG_HAS_WOL))
7648 adapter->eeprom_wol = 0;
7649
7650 /* initialize the wol settings based on the eeprom settings */
7651 adapter->wol = adapter->eeprom_wol;
7652
7653 /* make sure adapter isn't asleep if manageability is enabled */
7654 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
7655 (hw->mac.ops.check_mng_mode(hw)))
7656 device_wakeup_enable(&pdev->dev);
7657
7658 /* save off EEPROM version number */
7659 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
7660
7661 if (ret_val) {
7662 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val);
7663 adapter->eeprom_vers = 0;
7664 }
7665
7666 /* init PTP hardware clock */
7667 e1000e_ptp_init(adapter);
7668
7669 /* reset the hardware with the new settings */
7670 e1000e_reset(adapter);
7671
7672 /* If the controller has AMT, do not set DRV_LOAD until the interface
7673 * is up. For all other cases, let the f/w know that the h/w is now
7674 * under the control of the driver.
7675 */
7676 if (!(adapter->flags & FLAG_HAS_AMT))
7677 e1000e_get_hw_control(adapter);
7678
7679 if (hw->mac.type >= e1000_pch_cnp)
7680 adapter->flags2 |= FLAG2_ENABLE_S0IX_FLOWS;
7681
7682 strscpy(netdev->name, "eth%d", sizeof(netdev->name));
7683 err = register_netdev(netdev);
7684 if (err)
7685 goto err_register;
7686
7687 /* carrier off reporting is important to ethtool even BEFORE open */
7688 netif_carrier_off(netdev);
7689
7690 e1000_print_device_info(adapter);
7691
7692 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_SMART_PREPARE);
7693
7694 if (pci_dev_run_wake(pdev))
7695 pm_runtime_put_noidle(&pdev->dev);
7696
7697 return 0;
7698
7699err_register:
7700 if (!(adapter->flags & FLAG_HAS_AMT))
7701 e1000e_release_hw_control(adapter);
7702err_eeprom:
7703 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
7704 e1000_phy_hw_reset(&adapter->hw);
7705err_hw_init:
7706 kfree(adapter->tx_ring);
7707 kfree(adapter->rx_ring);
7708err_sw_init:
7709 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt))
7710 iounmap(adapter->hw.flash_address);
7711 e1000e_reset_interrupt_capability(adapter);
7712err_flashmap:
7713 iounmap(adapter->hw.hw_addr);
7714err_ioremap:
7715 free_netdev(netdev);
7716err_alloc_etherdev:
7717 pci_release_mem_regions(pdev);
7718err_pci_reg:
7719err_dma:
7720 pci_disable_device(pdev);
7721 return err;
7722}
7723
7724/**
7725 * e1000_remove - Device Removal Routine
7726 * @pdev: PCI device information struct
7727 *
7728 * e1000_remove is called by the PCI subsystem to alert the driver
7729 * that it should release a PCI device. This could be caused by a
7730 * Hot-Plug event, or because the driver is going to be removed from
7731 * memory.
7732 **/
7733static void e1000_remove(struct pci_dev *pdev)
7734{
7735 struct net_device *netdev = pci_get_drvdata(pdev);
7736 struct e1000_adapter *adapter = netdev_priv(netdev);
7737
7738 e1000e_ptp_remove(adapter);
7739
7740 /* The timers may be rescheduled, so explicitly disable them
7741 * from being rescheduled.
7742 */
7743 set_bit(__E1000_DOWN, &adapter->state);
7744 del_timer_sync(&adapter->watchdog_timer);
7745 del_timer_sync(&adapter->phy_info_timer);
7746
7747 cancel_work_sync(&adapter->reset_task);
7748 cancel_work_sync(&adapter->watchdog_task);
7749 cancel_work_sync(&adapter->downshift_task);
7750 cancel_work_sync(&adapter->update_phy_task);
7751 cancel_work_sync(&adapter->print_hang_task);
7752
7753 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
7754 cancel_work_sync(&adapter->tx_hwtstamp_work);
7755 if (adapter->tx_hwtstamp_skb) {
7756 dev_consume_skb_any(adapter->tx_hwtstamp_skb);
7757 adapter->tx_hwtstamp_skb = NULL;
7758 }
7759 }
7760
7761 unregister_netdev(netdev);
7762
7763 if (pci_dev_run_wake(pdev))
7764 pm_runtime_get_noresume(&pdev->dev);
7765
7766 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7767 * would have already happened in close and is redundant.
7768 */
7769 e1000e_release_hw_control(adapter);
7770
7771 e1000e_reset_interrupt_capability(adapter);
7772 kfree(adapter->tx_ring);
7773 kfree(adapter->rx_ring);
7774
7775 iounmap(adapter->hw.hw_addr);
7776 if ((adapter->hw.flash_address) &&
7777 (adapter->hw.mac.type < e1000_pch_spt))
7778 iounmap(adapter->hw.flash_address);
7779 pci_release_mem_regions(pdev);
7780
7781 free_netdev(netdev);
7782
7783 pci_disable_device(pdev);
7784}
7785
7786/* PCI Error Recovery (ERS) */
7787static const struct pci_error_handlers e1000_err_handler = {
7788 .error_detected = e1000_io_error_detected,
7789 .slot_reset = e1000_io_slot_reset,
7790 .resume = e1000_io_resume,
7791};
7792
7793static const struct pci_device_id e1000_pci_tbl[] = {
7794 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
7795 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
7796 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
7797 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7798 board_82571 },
7799 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
7800 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
7801 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
7802 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
7803 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
7804
7805 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
7806 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
7807 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
7808 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
7809
7810 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
7811 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
7812 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
7813
7814 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
7815 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
7816 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
7817
7818 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7819 board_80003es2lan },
7820 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7821 board_80003es2lan },
7822 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7823 board_80003es2lan },
7824 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7825 board_80003es2lan },
7826
7827 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
7828 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
7829 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
7830 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
7831 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
7832 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
7833 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
7834 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
7835
7836 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
7837 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
7838 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
7839 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
7840 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
7841 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
7842 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
7843 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
7844 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
7845
7846 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
7847 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
7848 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
7849
7850 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
7851 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
7852 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
7853
7854 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
7855 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
7856 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7857 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7858
7859 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7860 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7861
7862 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7863 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
7864 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7865 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
7866 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt },
7867 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7868 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7869 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
7870 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt },
7871 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt },
7872 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt },
7873 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt },
7874 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt },
7875 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt },
7876 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt },
7877 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt },
7878 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt },
7879 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp },
7880 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp },
7881 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp },
7882 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp },
7883 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp },
7884 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp },
7885 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp },
7886 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp },
7887 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM10), board_pch_cnp },
7888 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V10), board_pch_cnp },
7889 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM11), board_pch_cnp },
7890 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), board_pch_cnp },
7891 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), board_pch_spt },
7892 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), board_pch_spt },
7893 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_tgp },
7894 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_tgp },
7895 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_tgp },
7896 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_tgp },
7897 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_tgp },
7898 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), board_pch_tgp },
7899 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM23), board_pch_adp },
7900 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V23), board_pch_adp },
7901 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), board_pch_adp },
7902 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), board_pch_adp },
7903 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), board_pch_adp },
7904 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), board_pch_adp },
7905 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM22), board_pch_adp },
7906 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V22), board_pch_adp },
7907 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM19), board_pch_adp },
7908 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V19), board_pch_adp },
7909 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM18), board_pch_mtp },
7910 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V18), board_pch_mtp },
7911 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM20), board_pch_mtp },
7912 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V20), board_pch_mtp },
7913 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM21), board_pch_mtp },
7914 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V21), board_pch_mtp },
7915 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_LM24), board_pch_mtp },
7916 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_V24), board_pch_mtp },
7917 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM25), board_pch_mtp },
7918 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V25), board_pch_mtp },
7919 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM26), board_pch_mtp },
7920 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V26), board_pch_mtp },
7921 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM27), board_pch_mtp },
7922 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V27), board_pch_mtp },
7923 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_LM29), board_pch_mtp },
7924 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_V29), board_pch_mtp },
7925
7926 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
7927};
7928MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7929
7930static const struct dev_pm_ops e1000e_pm_ops = {
7931 .prepare = e1000e_pm_prepare,
7932 .suspend = e1000e_pm_suspend,
7933 .resume = e1000e_pm_resume,
7934 .freeze = e1000e_pm_freeze,
7935 .thaw = e1000e_pm_thaw,
7936 .poweroff = e1000e_pm_suspend,
7937 .restore = e1000e_pm_resume,
7938 RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
7939 e1000e_pm_runtime_idle)
7940};
7941
7942/* PCI Device API Driver */
7943static struct pci_driver e1000_driver = {
7944 .name = e1000e_driver_name,
7945 .id_table = e1000_pci_tbl,
7946 .probe = e1000_probe,
7947 .remove = e1000_remove,
7948 .driver.pm = pm_ptr(&e1000e_pm_ops),
7949 .shutdown = e1000_shutdown,
7950 .err_handler = &e1000_err_handler
7951};
7952
7953/**
7954 * e1000_init_module - Driver Registration Routine
7955 *
7956 * e1000_init_module is the first routine called when the driver is
7957 * loaded. All it does is register with the PCI subsystem.
7958 **/
7959static int __init e1000_init_module(void)
7960{
7961 pr_info("Intel(R) PRO/1000 Network Driver\n");
7962 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n");
7963
7964 return pci_register_driver(&e1000_driver);
7965}
7966module_init(e1000_init_module);
7967
7968/**
7969 * e1000_exit_module - Driver Exit Cleanup Routine
7970 *
7971 * e1000_exit_module is called just before the driver is removed
7972 * from memory.
7973 **/
7974static void __exit e1000_exit_module(void)
7975{
7976 pci_unregister_driver(&e1000_driver);
7977}
7978module_exit(e1000_exit_module);
7979
7980MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7981MODULE_LICENSE("GPL v2");
7982
7983/* netdev.c */
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
5
6#include <linux/module.h>
7#include <linux/types.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/vmalloc.h>
11#include <linux/pagemap.h>
12#include <linux/delay.h>
13#include <linux/netdevice.h>
14#include <linux/interrupt.h>
15#include <linux/tcp.h>
16#include <linux/ipv6.h>
17#include <linux/slab.h>
18#include <net/checksum.h>
19#include <net/ip6_checksum.h>
20#include <linux/ethtool.h>
21#include <linux/if_vlan.h>
22#include <linux/cpu.h>
23#include <linux/smp.h>
24#include <linux/pm_qos.h>
25#include <linux/pm_runtime.h>
26#include <linux/aer.h>
27#include <linux/prefetch.h>
28
29#include "e1000.h"
30
31#define DRV_EXTRAVERSION "-k"
32
33#define DRV_VERSION "3.2.6" DRV_EXTRAVERSION
34char e1000e_driver_name[] = "e1000e";
35const char e1000e_driver_version[] = DRV_VERSION;
36
37#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
38static int debug = -1;
39module_param(debug, int, 0);
40MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
41
42static const struct e1000_info *e1000_info_tbl[] = {
43 [board_82571] = &e1000_82571_info,
44 [board_82572] = &e1000_82572_info,
45 [board_82573] = &e1000_82573_info,
46 [board_82574] = &e1000_82574_info,
47 [board_82583] = &e1000_82583_info,
48 [board_80003es2lan] = &e1000_es2_info,
49 [board_ich8lan] = &e1000_ich8_info,
50 [board_ich9lan] = &e1000_ich9_info,
51 [board_ich10lan] = &e1000_ich10_info,
52 [board_pchlan] = &e1000_pch_info,
53 [board_pch2lan] = &e1000_pch2_info,
54 [board_pch_lpt] = &e1000_pch_lpt_info,
55 [board_pch_spt] = &e1000_pch_spt_info,
56 [board_pch_cnp] = &e1000_pch_cnp_info,
57};
58
59struct e1000_reg_info {
60 u32 ofs;
61 char *name;
62};
63
64static const struct e1000_reg_info e1000_reg_info_tbl[] = {
65 /* General Registers */
66 {E1000_CTRL, "CTRL"},
67 {E1000_STATUS, "STATUS"},
68 {E1000_CTRL_EXT, "CTRL_EXT"},
69
70 /* Interrupt Registers */
71 {E1000_ICR, "ICR"},
72
73 /* Rx Registers */
74 {E1000_RCTL, "RCTL"},
75 {E1000_RDLEN(0), "RDLEN"},
76 {E1000_RDH(0), "RDH"},
77 {E1000_RDT(0), "RDT"},
78 {E1000_RDTR, "RDTR"},
79 {E1000_RXDCTL(0), "RXDCTL"},
80 {E1000_ERT, "ERT"},
81 {E1000_RDBAL(0), "RDBAL"},
82 {E1000_RDBAH(0), "RDBAH"},
83 {E1000_RDFH, "RDFH"},
84 {E1000_RDFT, "RDFT"},
85 {E1000_RDFHS, "RDFHS"},
86 {E1000_RDFTS, "RDFTS"},
87 {E1000_RDFPC, "RDFPC"},
88
89 /* Tx Registers */
90 {E1000_TCTL, "TCTL"},
91 {E1000_TDBAL(0), "TDBAL"},
92 {E1000_TDBAH(0), "TDBAH"},
93 {E1000_TDLEN(0), "TDLEN"},
94 {E1000_TDH(0), "TDH"},
95 {E1000_TDT(0), "TDT"},
96 {E1000_TIDV, "TIDV"},
97 {E1000_TXDCTL(0), "TXDCTL"},
98 {E1000_TADV, "TADV"},
99 {E1000_TARC(0), "TARC"},
100 {E1000_TDFH, "TDFH"},
101 {E1000_TDFT, "TDFT"},
102 {E1000_TDFHS, "TDFHS"},
103 {E1000_TDFTS, "TDFTS"},
104 {E1000_TDFPC, "TDFPC"},
105
106 /* List Terminator */
107 {0, NULL}
108};
109
110/**
111 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
112 * @hw: pointer to the HW structure
113 *
114 * When updating the MAC CSR registers, the Manageability Engine (ME) could
115 * be accessing the registers at the same time. Normally, this is handled in
116 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
117 * accesses later than it should which could result in the register to have
118 * an incorrect value. Workaround this by checking the FWSM register which
119 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
120 * and try again a number of times.
121 **/
122s32 __ew32_prepare(struct e1000_hw *hw)
123{
124 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
125
126 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
127 udelay(50);
128
129 return i;
130}
131
132void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
133{
134 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
135 __ew32_prepare(hw);
136
137 writel(val, hw->hw_addr + reg);
138}
139
140/**
141 * e1000_regdump - register printout routine
142 * @hw: pointer to the HW structure
143 * @reginfo: pointer to the register info table
144 **/
145static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
146{
147 int n = 0;
148 char rname[16];
149 u32 regs[8];
150
151 switch (reginfo->ofs) {
152 case E1000_RXDCTL(0):
153 for (n = 0; n < 2; n++)
154 regs[n] = __er32(hw, E1000_RXDCTL(n));
155 break;
156 case E1000_TXDCTL(0):
157 for (n = 0; n < 2; n++)
158 regs[n] = __er32(hw, E1000_TXDCTL(n));
159 break;
160 case E1000_TARC(0):
161 for (n = 0; n < 2; n++)
162 regs[n] = __er32(hw, E1000_TARC(n));
163 break;
164 default:
165 pr_info("%-15s %08x\n",
166 reginfo->name, __er32(hw, reginfo->ofs));
167 return;
168 }
169
170 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
171 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
172}
173
174static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
175 struct e1000_buffer *bi)
176{
177 int i;
178 struct e1000_ps_page *ps_page;
179
180 for (i = 0; i < adapter->rx_ps_pages; i++) {
181 ps_page = &bi->ps_pages[i];
182
183 if (ps_page->page) {
184 pr_info("packet dump for ps_page %d:\n", i);
185 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
186 16, 1, page_address(ps_page->page),
187 PAGE_SIZE, true);
188 }
189 }
190}
191
192/**
193 * e1000e_dump - Print registers, Tx-ring and Rx-ring
194 * @adapter: board private structure
195 **/
196static void e1000e_dump(struct e1000_adapter *adapter)
197{
198 struct net_device *netdev = adapter->netdev;
199 struct e1000_hw *hw = &adapter->hw;
200 struct e1000_reg_info *reginfo;
201 struct e1000_ring *tx_ring = adapter->tx_ring;
202 struct e1000_tx_desc *tx_desc;
203 struct my_u0 {
204 __le64 a;
205 __le64 b;
206 } *u0;
207 struct e1000_buffer *buffer_info;
208 struct e1000_ring *rx_ring = adapter->rx_ring;
209 union e1000_rx_desc_packet_split *rx_desc_ps;
210 union e1000_rx_desc_extended *rx_desc;
211 struct my_u1 {
212 __le64 a;
213 __le64 b;
214 __le64 c;
215 __le64 d;
216 } *u1;
217 u32 staterr;
218 int i = 0;
219
220 if (!netif_msg_hw(adapter))
221 return;
222
223 /* Print netdevice Info */
224 if (netdev) {
225 dev_info(&adapter->pdev->dev, "Net device Info\n");
226 pr_info("Device Name state trans_start\n");
227 pr_info("%-15s %016lX %016lX\n", netdev->name,
228 netdev->state, dev_trans_start(netdev));
229 }
230
231 /* Print Registers */
232 dev_info(&adapter->pdev->dev, "Register Dump\n");
233 pr_info(" Register Name Value\n");
234 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
235 reginfo->name; reginfo++) {
236 e1000_regdump(hw, reginfo);
237 }
238
239 /* Print Tx Ring Summary */
240 if (!netdev || !netif_running(netdev))
241 return;
242
243 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
244 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
245 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
246 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
247 0, tx_ring->next_to_use, tx_ring->next_to_clean,
248 (unsigned long long)buffer_info->dma,
249 buffer_info->length,
250 buffer_info->next_to_watch,
251 (unsigned long long)buffer_info->time_stamp);
252
253 /* Print Tx Ring */
254 if (!netif_msg_tx_done(adapter))
255 goto rx_ring_summary;
256
257 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
258
259 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
260 *
261 * Legacy Transmit Descriptor
262 * +--------------------------------------------------------------+
263 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
264 * +--------------------------------------------------------------+
265 * 8 | Special | CSS | Status | CMD | CSO | Length |
266 * +--------------------------------------------------------------+
267 * 63 48 47 36 35 32 31 24 23 16 15 0
268 *
269 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
270 * 63 48 47 40 39 32 31 16 15 8 7 0
271 * +----------------------------------------------------------------+
272 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
273 * +----------------------------------------------------------------+
274 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
275 * +----------------------------------------------------------------+
276 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
277 *
278 * Extended Data Descriptor (DTYP=0x1)
279 * +----------------------------------------------------------------+
280 * 0 | Buffer Address [63:0] |
281 * +----------------------------------------------------------------+
282 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
283 * +----------------------------------------------------------------+
284 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
285 */
286 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
287 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
288 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
289 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
290 const char *next_desc;
291 tx_desc = E1000_TX_DESC(*tx_ring, i);
292 buffer_info = &tx_ring->buffer_info[i];
293 u0 = (struct my_u0 *)tx_desc;
294 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
295 next_desc = " NTC/U";
296 else if (i == tx_ring->next_to_use)
297 next_desc = " NTU";
298 else if (i == tx_ring->next_to_clean)
299 next_desc = " NTC";
300 else
301 next_desc = "";
302 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
303 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' :
304 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')),
305 i,
306 (unsigned long long)le64_to_cpu(u0->a),
307 (unsigned long long)le64_to_cpu(u0->b),
308 (unsigned long long)buffer_info->dma,
309 buffer_info->length, buffer_info->next_to_watch,
310 (unsigned long long)buffer_info->time_stamp,
311 buffer_info->skb, next_desc);
312
313 if (netif_msg_pktdata(adapter) && buffer_info->skb)
314 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
315 16, 1, buffer_info->skb->data,
316 buffer_info->skb->len, true);
317 }
318
319 /* Print Rx Ring Summary */
320rx_ring_summary:
321 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
322 pr_info("Queue [NTU] [NTC]\n");
323 pr_info(" %5d %5X %5X\n",
324 0, rx_ring->next_to_use, rx_ring->next_to_clean);
325
326 /* Print Rx Ring */
327 if (!netif_msg_rx_status(adapter))
328 return;
329
330 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
331 switch (adapter->rx_ps_pages) {
332 case 1:
333 case 2:
334 case 3:
335 /* [Extended] Packet Split Receive Descriptor Format
336 *
337 * +-----------------------------------------------------+
338 * 0 | Buffer Address 0 [63:0] |
339 * +-----------------------------------------------------+
340 * 8 | Buffer Address 1 [63:0] |
341 * +-----------------------------------------------------+
342 * 16 | Buffer Address 2 [63:0] |
343 * +-----------------------------------------------------+
344 * 24 | Buffer Address 3 [63:0] |
345 * +-----------------------------------------------------+
346 */
347 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
348 /* [Extended] Receive Descriptor (Write-Back) Format
349 *
350 * 63 48 47 32 31 13 12 8 7 4 3 0
351 * +------------------------------------------------------+
352 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
353 * | Checksum | Ident | | Queue | | Type |
354 * +------------------------------------------------------+
355 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
356 * +------------------------------------------------------+
357 * 63 48 47 32 31 20 19 0
358 */
359 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
360 for (i = 0; i < rx_ring->count; i++) {
361 const char *next_desc;
362 buffer_info = &rx_ring->buffer_info[i];
363 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
364 u1 = (struct my_u1 *)rx_desc_ps;
365 staterr =
366 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
367
368 if (i == rx_ring->next_to_use)
369 next_desc = " NTU";
370 else if (i == rx_ring->next_to_clean)
371 next_desc = " NTC";
372 else
373 next_desc = "";
374
375 if (staterr & E1000_RXD_STAT_DD) {
376 /* Descriptor Done */
377 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
378 "RWB", i,
379 (unsigned long long)le64_to_cpu(u1->a),
380 (unsigned long long)le64_to_cpu(u1->b),
381 (unsigned long long)le64_to_cpu(u1->c),
382 (unsigned long long)le64_to_cpu(u1->d),
383 buffer_info->skb, next_desc);
384 } else {
385 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
386 "R ", i,
387 (unsigned long long)le64_to_cpu(u1->a),
388 (unsigned long long)le64_to_cpu(u1->b),
389 (unsigned long long)le64_to_cpu(u1->c),
390 (unsigned long long)le64_to_cpu(u1->d),
391 (unsigned long long)buffer_info->dma,
392 buffer_info->skb, next_desc);
393
394 if (netif_msg_pktdata(adapter))
395 e1000e_dump_ps_pages(adapter,
396 buffer_info);
397 }
398 }
399 break;
400 default:
401 case 0:
402 /* Extended Receive Descriptor (Read) Format
403 *
404 * +-----------------------------------------------------+
405 * 0 | Buffer Address [63:0] |
406 * +-----------------------------------------------------+
407 * 8 | Reserved |
408 * +-----------------------------------------------------+
409 */
410 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
411 /* Extended Receive Descriptor (Write-Back) Format
412 *
413 * 63 48 47 32 31 24 23 4 3 0
414 * +------------------------------------------------------+
415 * | RSS Hash | | | |
416 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
417 * | Packet | IP | | | Type |
418 * | Checksum | Ident | | | |
419 * +------------------------------------------------------+
420 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
421 * +------------------------------------------------------+
422 * 63 48 47 32 31 20 19 0
423 */
424 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
425
426 for (i = 0; i < rx_ring->count; i++) {
427 const char *next_desc;
428
429 buffer_info = &rx_ring->buffer_info[i];
430 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
431 u1 = (struct my_u1 *)rx_desc;
432 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
433
434 if (i == rx_ring->next_to_use)
435 next_desc = " NTU";
436 else if (i == rx_ring->next_to_clean)
437 next_desc = " NTC";
438 else
439 next_desc = "";
440
441 if (staterr & E1000_RXD_STAT_DD) {
442 /* Descriptor Done */
443 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
444 "RWB", i,
445 (unsigned long long)le64_to_cpu(u1->a),
446 (unsigned long long)le64_to_cpu(u1->b),
447 buffer_info->skb, next_desc);
448 } else {
449 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
450 "R ", i,
451 (unsigned long long)le64_to_cpu(u1->a),
452 (unsigned long long)le64_to_cpu(u1->b),
453 (unsigned long long)buffer_info->dma,
454 buffer_info->skb, next_desc);
455
456 if (netif_msg_pktdata(adapter) &&
457 buffer_info->skb)
458 print_hex_dump(KERN_INFO, "",
459 DUMP_PREFIX_ADDRESS, 16,
460 1,
461 buffer_info->skb->data,
462 adapter->rx_buffer_len,
463 true);
464 }
465 }
466 }
467}
468
469/**
470 * e1000_desc_unused - calculate if we have unused descriptors
471 **/
472static int e1000_desc_unused(struct e1000_ring *ring)
473{
474 if (ring->next_to_clean > ring->next_to_use)
475 return ring->next_to_clean - ring->next_to_use - 1;
476
477 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
478}
479
480/**
481 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
482 * @adapter: board private structure
483 * @hwtstamps: time stamp structure to update
484 * @systim: unsigned 64bit system time value.
485 *
486 * Convert the system time value stored in the RX/TXSTMP registers into a
487 * hwtstamp which can be used by the upper level time stamping functions.
488 *
489 * The 'systim_lock' spinlock is used to protect the consistency of the
490 * system time value. This is needed because reading the 64 bit time
491 * value involves reading two 32 bit registers. The first read latches the
492 * value.
493 **/
494static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
495 struct skb_shared_hwtstamps *hwtstamps,
496 u64 systim)
497{
498 u64 ns;
499 unsigned long flags;
500
501 spin_lock_irqsave(&adapter->systim_lock, flags);
502 ns = timecounter_cyc2time(&adapter->tc, systim);
503 spin_unlock_irqrestore(&adapter->systim_lock, flags);
504
505 memset(hwtstamps, 0, sizeof(*hwtstamps));
506 hwtstamps->hwtstamp = ns_to_ktime(ns);
507}
508
509/**
510 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
511 * @adapter: board private structure
512 * @status: descriptor extended error and status field
513 * @skb: particular skb to include time stamp
514 *
515 * If the time stamp is valid, convert it into the timecounter ns value
516 * and store that result into the shhwtstamps structure which is passed
517 * up the network stack.
518 **/
519static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
520 struct sk_buff *skb)
521{
522 struct e1000_hw *hw = &adapter->hw;
523 u64 rxstmp;
524
525 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
526 !(status & E1000_RXDEXT_STATERR_TST) ||
527 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
528 return;
529
530 /* The Rx time stamp registers contain the time stamp. No other
531 * received packet will be time stamped until the Rx time stamp
532 * registers are read. Because only one packet can be time stamped
533 * at a time, the register values must belong to this packet and
534 * therefore none of the other additional attributes need to be
535 * compared.
536 */
537 rxstmp = (u64)er32(RXSTMPL);
538 rxstmp |= (u64)er32(RXSTMPH) << 32;
539 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
540
541 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
542}
543
544/**
545 * e1000_receive_skb - helper function to handle Rx indications
546 * @adapter: board private structure
547 * @staterr: descriptor extended error and status field as written by hardware
548 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
549 * @skb: pointer to sk_buff to be indicated to stack
550 **/
551static void e1000_receive_skb(struct e1000_adapter *adapter,
552 struct net_device *netdev, struct sk_buff *skb,
553 u32 staterr, __le16 vlan)
554{
555 u16 tag = le16_to_cpu(vlan);
556
557 e1000e_rx_hwtstamp(adapter, staterr, skb);
558
559 skb->protocol = eth_type_trans(skb, netdev);
560
561 if (staterr & E1000_RXD_STAT_VP)
562 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
563
564 napi_gro_receive(&adapter->napi, skb);
565}
566
567/**
568 * e1000_rx_checksum - Receive Checksum Offload
569 * @adapter: board private structure
570 * @status_err: receive descriptor status and error fields
571 * @csum: receive descriptor csum field
572 * @sk_buff: socket buffer with received data
573 **/
574static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
575 struct sk_buff *skb)
576{
577 u16 status = (u16)status_err;
578 u8 errors = (u8)(status_err >> 24);
579
580 skb_checksum_none_assert(skb);
581
582 /* Rx checksum disabled */
583 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
584 return;
585
586 /* Ignore Checksum bit is set */
587 if (status & E1000_RXD_STAT_IXSM)
588 return;
589
590 /* TCP/UDP checksum error bit or IP checksum error bit is set */
591 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
592 /* let the stack verify checksum errors */
593 adapter->hw_csum_err++;
594 return;
595 }
596
597 /* TCP/UDP Checksum has not been calculated */
598 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
599 return;
600
601 /* It must be a TCP or UDP packet with a valid checksum */
602 skb->ip_summed = CHECKSUM_UNNECESSARY;
603 adapter->hw_csum_good++;
604}
605
606static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
607{
608 struct e1000_adapter *adapter = rx_ring->adapter;
609 struct e1000_hw *hw = &adapter->hw;
610 s32 ret_val = __ew32_prepare(hw);
611
612 writel(i, rx_ring->tail);
613
614 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
615 u32 rctl = er32(RCTL);
616
617 ew32(RCTL, rctl & ~E1000_RCTL_EN);
618 e_err("ME firmware caused invalid RDT - resetting\n");
619 schedule_work(&adapter->reset_task);
620 }
621}
622
623static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
624{
625 struct e1000_adapter *adapter = tx_ring->adapter;
626 struct e1000_hw *hw = &adapter->hw;
627 s32 ret_val = __ew32_prepare(hw);
628
629 writel(i, tx_ring->tail);
630
631 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
632 u32 tctl = er32(TCTL);
633
634 ew32(TCTL, tctl & ~E1000_TCTL_EN);
635 e_err("ME firmware caused invalid TDT - resetting\n");
636 schedule_work(&adapter->reset_task);
637 }
638}
639
640/**
641 * e1000_alloc_rx_buffers - Replace used receive buffers
642 * @rx_ring: Rx descriptor ring
643 **/
644static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
645 int cleaned_count, gfp_t gfp)
646{
647 struct e1000_adapter *adapter = rx_ring->adapter;
648 struct net_device *netdev = adapter->netdev;
649 struct pci_dev *pdev = adapter->pdev;
650 union e1000_rx_desc_extended *rx_desc;
651 struct e1000_buffer *buffer_info;
652 struct sk_buff *skb;
653 unsigned int i;
654 unsigned int bufsz = adapter->rx_buffer_len;
655
656 i = rx_ring->next_to_use;
657 buffer_info = &rx_ring->buffer_info[i];
658
659 while (cleaned_count--) {
660 skb = buffer_info->skb;
661 if (skb) {
662 skb_trim(skb, 0);
663 goto map_skb;
664 }
665
666 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
667 if (!skb) {
668 /* Better luck next round */
669 adapter->alloc_rx_buff_failed++;
670 break;
671 }
672
673 buffer_info->skb = skb;
674map_skb:
675 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
676 adapter->rx_buffer_len,
677 DMA_FROM_DEVICE);
678 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
679 dev_err(&pdev->dev, "Rx DMA map failed\n");
680 adapter->rx_dma_failed++;
681 break;
682 }
683
684 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
685 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
686
687 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
688 /* Force memory writes to complete before letting h/w
689 * know there are new descriptors to fetch. (Only
690 * applicable for weak-ordered memory model archs,
691 * such as IA-64).
692 */
693 wmb();
694 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
695 e1000e_update_rdt_wa(rx_ring, i);
696 else
697 writel(i, rx_ring->tail);
698 }
699 i++;
700 if (i == rx_ring->count)
701 i = 0;
702 buffer_info = &rx_ring->buffer_info[i];
703 }
704
705 rx_ring->next_to_use = i;
706}
707
708/**
709 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
710 * @rx_ring: Rx descriptor ring
711 **/
712static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
713 int cleaned_count, gfp_t gfp)
714{
715 struct e1000_adapter *adapter = rx_ring->adapter;
716 struct net_device *netdev = adapter->netdev;
717 struct pci_dev *pdev = adapter->pdev;
718 union e1000_rx_desc_packet_split *rx_desc;
719 struct e1000_buffer *buffer_info;
720 struct e1000_ps_page *ps_page;
721 struct sk_buff *skb;
722 unsigned int i, j;
723
724 i = rx_ring->next_to_use;
725 buffer_info = &rx_ring->buffer_info[i];
726
727 while (cleaned_count--) {
728 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
729
730 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
731 ps_page = &buffer_info->ps_pages[j];
732 if (j >= adapter->rx_ps_pages) {
733 /* all unused desc entries get hw null ptr */
734 rx_desc->read.buffer_addr[j + 1] =
735 ~cpu_to_le64(0);
736 continue;
737 }
738 if (!ps_page->page) {
739 ps_page->page = alloc_page(gfp);
740 if (!ps_page->page) {
741 adapter->alloc_rx_buff_failed++;
742 goto no_buffers;
743 }
744 ps_page->dma = dma_map_page(&pdev->dev,
745 ps_page->page,
746 0, PAGE_SIZE,
747 DMA_FROM_DEVICE);
748 if (dma_mapping_error(&pdev->dev,
749 ps_page->dma)) {
750 dev_err(&adapter->pdev->dev,
751 "Rx DMA page map failed\n");
752 adapter->rx_dma_failed++;
753 goto no_buffers;
754 }
755 }
756 /* Refresh the desc even if buffer_addrs
757 * didn't change because each write-back
758 * erases this info.
759 */
760 rx_desc->read.buffer_addr[j + 1] =
761 cpu_to_le64(ps_page->dma);
762 }
763
764 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
765 gfp);
766
767 if (!skb) {
768 adapter->alloc_rx_buff_failed++;
769 break;
770 }
771
772 buffer_info->skb = skb;
773 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
774 adapter->rx_ps_bsize0,
775 DMA_FROM_DEVICE);
776 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
777 dev_err(&pdev->dev, "Rx DMA map failed\n");
778 adapter->rx_dma_failed++;
779 /* cleanup skb */
780 dev_kfree_skb_any(skb);
781 buffer_info->skb = NULL;
782 break;
783 }
784
785 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
786
787 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
788 /* Force memory writes to complete before letting h/w
789 * know there are new descriptors to fetch. (Only
790 * applicable for weak-ordered memory model archs,
791 * such as IA-64).
792 */
793 wmb();
794 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
795 e1000e_update_rdt_wa(rx_ring, i << 1);
796 else
797 writel(i << 1, rx_ring->tail);
798 }
799
800 i++;
801 if (i == rx_ring->count)
802 i = 0;
803 buffer_info = &rx_ring->buffer_info[i];
804 }
805
806no_buffers:
807 rx_ring->next_to_use = i;
808}
809
810/**
811 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
812 * @rx_ring: Rx descriptor ring
813 * @cleaned_count: number of buffers to allocate this pass
814 **/
815
816static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
817 int cleaned_count, gfp_t gfp)
818{
819 struct e1000_adapter *adapter = rx_ring->adapter;
820 struct net_device *netdev = adapter->netdev;
821 struct pci_dev *pdev = adapter->pdev;
822 union e1000_rx_desc_extended *rx_desc;
823 struct e1000_buffer *buffer_info;
824 struct sk_buff *skb;
825 unsigned int i;
826 unsigned int bufsz = 256 - 16; /* for skb_reserve */
827
828 i = rx_ring->next_to_use;
829 buffer_info = &rx_ring->buffer_info[i];
830
831 while (cleaned_count--) {
832 skb = buffer_info->skb;
833 if (skb) {
834 skb_trim(skb, 0);
835 goto check_page;
836 }
837
838 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
839 if (unlikely(!skb)) {
840 /* Better luck next round */
841 adapter->alloc_rx_buff_failed++;
842 break;
843 }
844
845 buffer_info->skb = skb;
846check_page:
847 /* allocate a new page if necessary */
848 if (!buffer_info->page) {
849 buffer_info->page = alloc_page(gfp);
850 if (unlikely(!buffer_info->page)) {
851 adapter->alloc_rx_buff_failed++;
852 break;
853 }
854 }
855
856 if (!buffer_info->dma) {
857 buffer_info->dma = dma_map_page(&pdev->dev,
858 buffer_info->page, 0,
859 PAGE_SIZE,
860 DMA_FROM_DEVICE);
861 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
862 adapter->alloc_rx_buff_failed++;
863 break;
864 }
865 }
866
867 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
868 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
869
870 if (unlikely(++i == rx_ring->count))
871 i = 0;
872 buffer_info = &rx_ring->buffer_info[i];
873 }
874
875 if (likely(rx_ring->next_to_use != i)) {
876 rx_ring->next_to_use = i;
877 if (unlikely(i-- == 0))
878 i = (rx_ring->count - 1);
879
880 /* Force memory writes to complete before letting h/w
881 * know there are new descriptors to fetch. (Only
882 * applicable for weak-ordered memory model archs,
883 * such as IA-64).
884 */
885 wmb();
886 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
887 e1000e_update_rdt_wa(rx_ring, i);
888 else
889 writel(i, rx_ring->tail);
890 }
891}
892
893static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
894 struct sk_buff *skb)
895{
896 if (netdev->features & NETIF_F_RXHASH)
897 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3);
898}
899
900/**
901 * e1000_clean_rx_irq - Send received data up the network stack
902 * @rx_ring: Rx descriptor ring
903 *
904 * the return value indicates whether actual cleaning was done, there
905 * is no guarantee that everything was cleaned
906 **/
907static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
908 int work_to_do)
909{
910 struct e1000_adapter *adapter = rx_ring->adapter;
911 struct net_device *netdev = adapter->netdev;
912 struct pci_dev *pdev = adapter->pdev;
913 struct e1000_hw *hw = &adapter->hw;
914 union e1000_rx_desc_extended *rx_desc, *next_rxd;
915 struct e1000_buffer *buffer_info, *next_buffer;
916 u32 length, staterr;
917 unsigned int i;
918 int cleaned_count = 0;
919 bool cleaned = false;
920 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
921
922 i = rx_ring->next_to_clean;
923 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
924 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
925 buffer_info = &rx_ring->buffer_info[i];
926
927 while (staterr & E1000_RXD_STAT_DD) {
928 struct sk_buff *skb;
929
930 if (*work_done >= work_to_do)
931 break;
932 (*work_done)++;
933 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
934
935 skb = buffer_info->skb;
936 buffer_info->skb = NULL;
937
938 prefetch(skb->data - NET_IP_ALIGN);
939
940 i++;
941 if (i == rx_ring->count)
942 i = 0;
943 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
944 prefetch(next_rxd);
945
946 next_buffer = &rx_ring->buffer_info[i];
947
948 cleaned = true;
949 cleaned_count++;
950 dma_unmap_single(&pdev->dev, buffer_info->dma,
951 adapter->rx_buffer_len, DMA_FROM_DEVICE);
952 buffer_info->dma = 0;
953
954 length = le16_to_cpu(rx_desc->wb.upper.length);
955
956 /* !EOP means multiple descriptors were used to store a single
957 * packet, if that's the case we need to toss it. In fact, we
958 * need to toss every packet with the EOP bit clear and the
959 * next frame that _does_ have the EOP bit set, as it is by
960 * definition only a frame fragment
961 */
962 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
963 adapter->flags2 |= FLAG2_IS_DISCARDING;
964
965 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
966 /* All receives must fit into a single buffer */
967 e_dbg("Receive packet consumed multiple buffers\n");
968 /* recycle */
969 buffer_info->skb = skb;
970 if (staterr & E1000_RXD_STAT_EOP)
971 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
972 goto next_desc;
973 }
974
975 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
976 !(netdev->features & NETIF_F_RXALL))) {
977 /* recycle */
978 buffer_info->skb = skb;
979 goto next_desc;
980 }
981
982 /* adjust length to remove Ethernet CRC */
983 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
984 /* If configured to store CRC, don't subtract FCS,
985 * but keep the FCS bytes out of the total_rx_bytes
986 * counter
987 */
988 if (netdev->features & NETIF_F_RXFCS)
989 total_rx_bytes -= 4;
990 else
991 length -= 4;
992 }
993
994 total_rx_bytes += length;
995 total_rx_packets++;
996
997 /* code added for copybreak, this should improve
998 * performance for small packets with large amounts
999 * of reassembly being done in the stack
1000 */
1001 if (length < copybreak) {
1002 struct sk_buff *new_skb =
1003 napi_alloc_skb(&adapter->napi, length);
1004 if (new_skb) {
1005 skb_copy_to_linear_data_offset(new_skb,
1006 -NET_IP_ALIGN,
1007 (skb->data -
1008 NET_IP_ALIGN),
1009 (length +
1010 NET_IP_ALIGN));
1011 /* save the skb in buffer_info as good */
1012 buffer_info->skb = skb;
1013 skb = new_skb;
1014 }
1015 /* else just continue with the old one */
1016 }
1017 /* end copybreak code */
1018 skb_put(skb, length);
1019
1020 /* Receive Checksum Offload */
1021 e1000_rx_checksum(adapter, staterr, skb);
1022
1023 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1024
1025 e1000_receive_skb(adapter, netdev, skb, staterr,
1026 rx_desc->wb.upper.vlan);
1027
1028next_desc:
1029 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1030
1031 /* return some buffers to hardware, one at a time is too slow */
1032 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1033 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1034 GFP_ATOMIC);
1035 cleaned_count = 0;
1036 }
1037
1038 /* use prefetched values */
1039 rx_desc = next_rxd;
1040 buffer_info = next_buffer;
1041
1042 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1043 }
1044 rx_ring->next_to_clean = i;
1045
1046 cleaned_count = e1000_desc_unused(rx_ring);
1047 if (cleaned_count)
1048 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1049
1050 adapter->total_rx_bytes += total_rx_bytes;
1051 adapter->total_rx_packets += total_rx_packets;
1052 return cleaned;
1053}
1054
1055static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1056 struct e1000_buffer *buffer_info,
1057 bool drop)
1058{
1059 struct e1000_adapter *adapter = tx_ring->adapter;
1060
1061 if (buffer_info->dma) {
1062 if (buffer_info->mapped_as_page)
1063 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1064 buffer_info->length, DMA_TO_DEVICE);
1065 else
1066 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1067 buffer_info->length, DMA_TO_DEVICE);
1068 buffer_info->dma = 0;
1069 }
1070 if (buffer_info->skb) {
1071 if (drop)
1072 dev_kfree_skb_any(buffer_info->skb);
1073 else
1074 dev_consume_skb_any(buffer_info->skb);
1075 buffer_info->skb = NULL;
1076 }
1077 buffer_info->time_stamp = 0;
1078}
1079
1080static void e1000_print_hw_hang(struct work_struct *work)
1081{
1082 struct e1000_adapter *adapter = container_of(work,
1083 struct e1000_adapter,
1084 print_hang_task);
1085 struct net_device *netdev = adapter->netdev;
1086 struct e1000_ring *tx_ring = adapter->tx_ring;
1087 unsigned int i = tx_ring->next_to_clean;
1088 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1089 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
1090 struct e1000_hw *hw = &adapter->hw;
1091 u16 phy_status, phy_1000t_status, phy_ext_status;
1092 u16 pci_status;
1093
1094 if (test_bit(__E1000_DOWN, &adapter->state))
1095 return;
1096
1097 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
1098 /* May be block on write-back, flush and detect again
1099 * flush pending descriptor writebacks to memory
1100 */
1101 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1102 /* execute the writes immediately */
1103 e1e_flush();
1104 /* Due to rare timing issues, write to TIDV again to ensure
1105 * the write is successful
1106 */
1107 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1108 /* execute the writes immediately */
1109 e1e_flush();
1110 adapter->tx_hang_recheck = true;
1111 return;
1112 }
1113 adapter->tx_hang_recheck = false;
1114
1115 if (er32(TDH(0)) == er32(TDT(0))) {
1116 e_dbg("false hang detected, ignoring\n");
1117 return;
1118 }
1119
1120 /* Real hang detected */
1121 netif_stop_queue(netdev);
1122
1123 e1e_rphy(hw, MII_BMSR, &phy_status);
1124 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1125 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
1126
1127 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1128
1129 /* detected Hardware unit hang */
1130 e_err("Detected Hardware Unit Hang:\n"
1131 " TDH <%x>\n"
1132 " TDT <%x>\n"
1133 " next_to_use <%x>\n"
1134 " next_to_clean <%x>\n"
1135 "buffer_info[next_to_clean]:\n"
1136 " time_stamp <%lx>\n"
1137 " next_to_watch <%x>\n"
1138 " jiffies <%lx>\n"
1139 " next_to_watch.status <%x>\n"
1140 "MAC Status <%x>\n"
1141 "PHY Status <%x>\n"
1142 "PHY 1000BASE-T Status <%x>\n"
1143 "PHY Extended Status <%x>\n"
1144 "PCI Status <%x>\n",
1145 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1146 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1147 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1148 phy_status, phy_1000t_status, phy_ext_status, pci_status);
1149
1150 e1000e_dump(adapter);
1151
1152 /* Suggest workaround for known h/w issue */
1153 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1154 e_err("Try turning off Tx pause (flow control) via ethtool\n");
1155}
1156
1157/**
1158 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1159 * @work: pointer to work struct
1160 *
1161 * This work function polls the TSYNCTXCTL valid bit to determine when a
1162 * timestamp has been taken for the current stored skb. The timestamp must
1163 * be for this skb because only one such packet is allowed in the queue.
1164 */
1165static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1166{
1167 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1168 tx_hwtstamp_work);
1169 struct e1000_hw *hw = &adapter->hw;
1170
1171 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1172 struct sk_buff *skb = adapter->tx_hwtstamp_skb;
1173 struct skb_shared_hwtstamps shhwtstamps;
1174 u64 txstmp;
1175
1176 txstmp = er32(TXSTMPL);
1177 txstmp |= (u64)er32(TXSTMPH) << 32;
1178
1179 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1180
1181 /* Clear the global tx_hwtstamp_skb pointer and force writes
1182 * prior to notifying the stack of a Tx timestamp.
1183 */
1184 adapter->tx_hwtstamp_skb = NULL;
1185 wmb(); /* force write prior to skb_tstamp_tx */
1186
1187 skb_tstamp_tx(skb, &shhwtstamps);
1188 dev_consume_skb_any(skb);
1189 } else if (time_after(jiffies, adapter->tx_hwtstamp_start
1190 + adapter->tx_timeout_factor * HZ)) {
1191 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1192 adapter->tx_hwtstamp_skb = NULL;
1193 adapter->tx_hwtstamp_timeouts++;
1194 e_warn("clearing Tx timestamp hang\n");
1195 } else {
1196 /* reschedule to check later */
1197 schedule_work(&adapter->tx_hwtstamp_work);
1198 }
1199}
1200
1201/**
1202 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1203 * @tx_ring: Tx descriptor ring
1204 *
1205 * the return value indicates whether actual cleaning was done, there
1206 * is no guarantee that everything was cleaned
1207 **/
1208static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
1209{
1210 struct e1000_adapter *adapter = tx_ring->adapter;
1211 struct net_device *netdev = adapter->netdev;
1212 struct e1000_hw *hw = &adapter->hw;
1213 struct e1000_tx_desc *tx_desc, *eop_desc;
1214 struct e1000_buffer *buffer_info;
1215 unsigned int i, eop;
1216 unsigned int count = 0;
1217 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
1218 unsigned int bytes_compl = 0, pkts_compl = 0;
1219
1220 i = tx_ring->next_to_clean;
1221 eop = tx_ring->buffer_info[i].next_to_watch;
1222 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1223
1224 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1225 (count < tx_ring->count)) {
1226 bool cleaned = false;
1227
1228 dma_rmb(); /* read buffer_info after eop_desc */
1229 for (; !cleaned; count++) {
1230 tx_desc = E1000_TX_DESC(*tx_ring, i);
1231 buffer_info = &tx_ring->buffer_info[i];
1232 cleaned = (i == eop);
1233
1234 if (cleaned) {
1235 total_tx_packets += buffer_info->segs;
1236 total_tx_bytes += buffer_info->bytecount;
1237 if (buffer_info->skb) {
1238 bytes_compl += buffer_info->skb->len;
1239 pkts_compl++;
1240 }
1241 }
1242
1243 e1000_put_txbuf(tx_ring, buffer_info, false);
1244 tx_desc->upper.data = 0;
1245
1246 i++;
1247 if (i == tx_ring->count)
1248 i = 0;
1249 }
1250
1251 if (i == tx_ring->next_to_use)
1252 break;
1253 eop = tx_ring->buffer_info[i].next_to_watch;
1254 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1255 }
1256
1257 tx_ring->next_to_clean = i;
1258
1259 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1260
1261#define TX_WAKE_THRESHOLD 32
1262 if (count && netif_carrier_ok(netdev) &&
1263 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
1264 /* Make sure that anybody stopping the queue after this
1265 * sees the new next_to_clean.
1266 */
1267 smp_mb();
1268
1269 if (netif_queue_stopped(netdev) &&
1270 !(test_bit(__E1000_DOWN, &adapter->state))) {
1271 netif_wake_queue(netdev);
1272 ++adapter->restart_queue;
1273 }
1274 }
1275
1276 if (adapter->detect_tx_hung) {
1277 /* Detect a transmit hang in hardware, this serializes the
1278 * check with the clearing of time_stamp and movement of i
1279 */
1280 adapter->detect_tx_hung = false;
1281 if (tx_ring->buffer_info[i].time_stamp &&
1282 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
1283 + (adapter->tx_timeout_factor * HZ)) &&
1284 !(er32(STATUS) & E1000_STATUS_TXOFF))
1285 schedule_work(&adapter->print_hang_task);
1286 else
1287 adapter->tx_hang_recheck = false;
1288 }
1289 adapter->total_tx_bytes += total_tx_bytes;
1290 adapter->total_tx_packets += total_tx_packets;
1291 return count < tx_ring->count;
1292}
1293
1294/**
1295 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1296 * @rx_ring: Rx descriptor ring
1297 *
1298 * the return value indicates whether actual cleaning was done, there
1299 * is no guarantee that everything was cleaned
1300 **/
1301static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1302 int work_to_do)
1303{
1304 struct e1000_adapter *adapter = rx_ring->adapter;
1305 struct e1000_hw *hw = &adapter->hw;
1306 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1307 struct net_device *netdev = adapter->netdev;
1308 struct pci_dev *pdev = adapter->pdev;
1309 struct e1000_buffer *buffer_info, *next_buffer;
1310 struct e1000_ps_page *ps_page;
1311 struct sk_buff *skb;
1312 unsigned int i, j;
1313 u32 length, staterr;
1314 int cleaned_count = 0;
1315 bool cleaned = false;
1316 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1317
1318 i = rx_ring->next_to_clean;
1319 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1320 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1321 buffer_info = &rx_ring->buffer_info[i];
1322
1323 while (staterr & E1000_RXD_STAT_DD) {
1324 if (*work_done >= work_to_do)
1325 break;
1326 (*work_done)++;
1327 skb = buffer_info->skb;
1328 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1329
1330 /* in the packet split case this is header only */
1331 prefetch(skb->data - NET_IP_ALIGN);
1332
1333 i++;
1334 if (i == rx_ring->count)
1335 i = 0;
1336 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1337 prefetch(next_rxd);
1338
1339 next_buffer = &rx_ring->buffer_info[i];
1340
1341 cleaned = true;
1342 cleaned_count++;
1343 dma_unmap_single(&pdev->dev, buffer_info->dma,
1344 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
1345 buffer_info->dma = 0;
1346
1347 /* see !EOP comment in other Rx routine */
1348 if (!(staterr & E1000_RXD_STAT_EOP))
1349 adapter->flags2 |= FLAG2_IS_DISCARDING;
1350
1351 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
1352 e_dbg("Packet Split buffers didn't pick up the full packet\n");
1353 dev_kfree_skb_irq(skb);
1354 if (staterr & E1000_RXD_STAT_EOP)
1355 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1356 goto next_desc;
1357 }
1358
1359 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1360 !(netdev->features & NETIF_F_RXALL))) {
1361 dev_kfree_skb_irq(skb);
1362 goto next_desc;
1363 }
1364
1365 length = le16_to_cpu(rx_desc->wb.middle.length0);
1366
1367 if (!length) {
1368 e_dbg("Last part of the packet spanning multiple descriptors\n");
1369 dev_kfree_skb_irq(skb);
1370 goto next_desc;
1371 }
1372
1373 /* Good Receive */
1374 skb_put(skb, length);
1375
1376 {
1377 /* this looks ugly, but it seems compiler issues make
1378 * it more efficient than reusing j
1379 */
1380 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
1381
1382 /* page alloc/put takes too long and effects small
1383 * packet throughput, so unsplit small packets and
1384 * save the alloc/put only valid in softirq (napi)
1385 * context to call kmap_*
1386 */
1387 if (l1 && (l1 <= copybreak) &&
1388 ((length + l1) <= adapter->rx_ps_bsize0)) {
1389 u8 *vaddr;
1390
1391 ps_page = &buffer_info->ps_pages[0];
1392
1393 /* there is no documentation about how to call
1394 * kmap_atomic, so we can't hold the mapping
1395 * very long
1396 */
1397 dma_sync_single_for_cpu(&pdev->dev,
1398 ps_page->dma,
1399 PAGE_SIZE,
1400 DMA_FROM_DEVICE);
1401 vaddr = kmap_atomic(ps_page->page);
1402 memcpy(skb_tail_pointer(skb), vaddr, l1);
1403 kunmap_atomic(vaddr);
1404 dma_sync_single_for_device(&pdev->dev,
1405 ps_page->dma,
1406 PAGE_SIZE,
1407 DMA_FROM_DEVICE);
1408
1409 /* remove the CRC */
1410 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1411 if (!(netdev->features & NETIF_F_RXFCS))
1412 l1 -= 4;
1413 }
1414
1415 skb_put(skb, l1);
1416 goto copydone;
1417 } /* if */
1418 }
1419
1420 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1421 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1422 if (!length)
1423 break;
1424
1425 ps_page = &buffer_info->ps_pages[j];
1426 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1427 DMA_FROM_DEVICE);
1428 ps_page->dma = 0;
1429 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1430 ps_page->page = NULL;
1431 skb->len += length;
1432 skb->data_len += length;
1433 skb->truesize += PAGE_SIZE;
1434 }
1435
1436 /* strip the ethernet crc, problem is we're using pages now so
1437 * this whole operation can get a little cpu intensive
1438 */
1439 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1440 if (!(netdev->features & NETIF_F_RXFCS))
1441 pskb_trim(skb, skb->len - 4);
1442 }
1443
1444copydone:
1445 total_rx_bytes += skb->len;
1446 total_rx_packets++;
1447
1448 e1000_rx_checksum(adapter, staterr, skb);
1449
1450 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1451
1452 if (rx_desc->wb.upper.header_status &
1453 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1454 adapter->rx_hdr_split++;
1455
1456 e1000_receive_skb(adapter, netdev, skb, staterr,
1457 rx_desc->wb.middle.vlan);
1458
1459next_desc:
1460 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1461 buffer_info->skb = NULL;
1462
1463 /* return some buffers to hardware, one at a time is too slow */
1464 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1465 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1466 GFP_ATOMIC);
1467 cleaned_count = 0;
1468 }
1469
1470 /* use prefetched values */
1471 rx_desc = next_rxd;
1472 buffer_info = next_buffer;
1473
1474 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1475 }
1476 rx_ring->next_to_clean = i;
1477
1478 cleaned_count = e1000_desc_unused(rx_ring);
1479 if (cleaned_count)
1480 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1481
1482 adapter->total_rx_bytes += total_rx_bytes;
1483 adapter->total_rx_packets += total_rx_packets;
1484 return cleaned;
1485}
1486
1487/**
1488 * e1000_consume_page - helper function
1489 **/
1490static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1491 u16 length)
1492{
1493 bi->page = NULL;
1494 skb->len += length;
1495 skb->data_len += length;
1496 skb->truesize += PAGE_SIZE;
1497}
1498
1499/**
1500 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1501 * @adapter: board private structure
1502 *
1503 * the return value indicates whether actual cleaning was done, there
1504 * is no guarantee that everything was cleaned
1505 **/
1506static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1507 int work_to_do)
1508{
1509 struct e1000_adapter *adapter = rx_ring->adapter;
1510 struct net_device *netdev = adapter->netdev;
1511 struct pci_dev *pdev = adapter->pdev;
1512 union e1000_rx_desc_extended *rx_desc, *next_rxd;
1513 struct e1000_buffer *buffer_info, *next_buffer;
1514 u32 length, staterr;
1515 unsigned int i;
1516 int cleaned_count = 0;
1517 bool cleaned = false;
1518 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1519 struct skb_shared_info *shinfo;
1520
1521 i = rx_ring->next_to_clean;
1522 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1524 buffer_info = &rx_ring->buffer_info[i];
1525
1526 while (staterr & E1000_RXD_STAT_DD) {
1527 struct sk_buff *skb;
1528
1529 if (*work_done >= work_to_do)
1530 break;
1531 (*work_done)++;
1532 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1533
1534 skb = buffer_info->skb;
1535 buffer_info->skb = NULL;
1536
1537 ++i;
1538 if (i == rx_ring->count)
1539 i = 0;
1540 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
1541 prefetch(next_rxd);
1542
1543 next_buffer = &rx_ring->buffer_info[i];
1544
1545 cleaned = true;
1546 cleaned_count++;
1547 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1548 DMA_FROM_DEVICE);
1549 buffer_info->dma = 0;
1550
1551 length = le16_to_cpu(rx_desc->wb.upper.length);
1552
1553 /* errors is only valid for DD + EOP descriptors */
1554 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
1555 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1556 !(netdev->features & NETIF_F_RXALL)))) {
1557 /* recycle both page and skb */
1558 buffer_info->skb = skb;
1559 /* an error means any chain goes out the window too */
1560 if (rx_ring->rx_skb_top)
1561 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1562 rx_ring->rx_skb_top = NULL;
1563 goto next_desc;
1564 }
1565#define rxtop (rx_ring->rx_skb_top)
1566 if (!(staterr & E1000_RXD_STAT_EOP)) {
1567 /* this descriptor is only the beginning (or middle) */
1568 if (!rxtop) {
1569 /* this is the beginning of a chain */
1570 rxtop = skb;
1571 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1572 0, length);
1573 } else {
1574 /* this is the middle of a chain */
1575 shinfo = skb_shinfo(rxtop);
1576 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1577 buffer_info->page, 0,
1578 length);
1579 /* re-use the skb, only consumed the page */
1580 buffer_info->skb = skb;
1581 }
1582 e1000_consume_page(buffer_info, rxtop, length);
1583 goto next_desc;
1584 } else {
1585 if (rxtop) {
1586 /* end of the chain */
1587 shinfo = skb_shinfo(rxtop);
1588 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1589 buffer_info->page, 0,
1590 length);
1591 /* re-use the current skb, we only consumed the
1592 * page
1593 */
1594 buffer_info->skb = skb;
1595 skb = rxtop;
1596 rxtop = NULL;
1597 e1000_consume_page(buffer_info, skb, length);
1598 } else {
1599 /* no chain, got EOP, this buf is the packet
1600 * copybreak to save the put_page/alloc_page
1601 */
1602 if (length <= copybreak &&
1603 skb_tailroom(skb) >= length) {
1604 u8 *vaddr;
1605 vaddr = kmap_atomic(buffer_info->page);
1606 memcpy(skb_tail_pointer(skb), vaddr,
1607 length);
1608 kunmap_atomic(vaddr);
1609 /* re-use the page, so don't erase
1610 * buffer_info->page
1611 */
1612 skb_put(skb, length);
1613 } else {
1614 skb_fill_page_desc(skb, 0,
1615 buffer_info->page, 0,
1616 length);
1617 e1000_consume_page(buffer_info, skb,
1618 length);
1619 }
1620 }
1621 }
1622
1623 /* Receive Checksum Offload */
1624 e1000_rx_checksum(adapter, staterr, skb);
1625
1626 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1627
1628 /* probably a little skewed due to removing CRC */
1629 total_rx_bytes += skb->len;
1630 total_rx_packets++;
1631
1632 /* eth type trans needs skb->data to point to something */
1633 if (!pskb_may_pull(skb, ETH_HLEN)) {
1634 e_err("pskb_may_pull failed.\n");
1635 dev_kfree_skb_irq(skb);
1636 goto next_desc;
1637 }
1638
1639 e1000_receive_skb(adapter, netdev, skb, staterr,
1640 rx_desc->wb.upper.vlan);
1641
1642next_desc:
1643 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1644
1645 /* return some buffers to hardware, one at a time is too slow */
1646 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
1647 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1648 GFP_ATOMIC);
1649 cleaned_count = 0;
1650 }
1651
1652 /* use prefetched values */
1653 rx_desc = next_rxd;
1654 buffer_info = next_buffer;
1655
1656 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1657 }
1658 rx_ring->next_to_clean = i;
1659
1660 cleaned_count = e1000_desc_unused(rx_ring);
1661 if (cleaned_count)
1662 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1663
1664 adapter->total_rx_bytes += total_rx_bytes;
1665 adapter->total_rx_packets += total_rx_packets;
1666 return cleaned;
1667}
1668
1669/**
1670 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1671 * @rx_ring: Rx descriptor ring
1672 **/
1673static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
1674{
1675 struct e1000_adapter *adapter = rx_ring->adapter;
1676 struct e1000_buffer *buffer_info;
1677 struct e1000_ps_page *ps_page;
1678 struct pci_dev *pdev = adapter->pdev;
1679 unsigned int i, j;
1680
1681 /* Free all the Rx ring sk_buffs */
1682 for (i = 0; i < rx_ring->count; i++) {
1683 buffer_info = &rx_ring->buffer_info[i];
1684 if (buffer_info->dma) {
1685 if (adapter->clean_rx == e1000_clean_rx_irq)
1686 dma_unmap_single(&pdev->dev, buffer_info->dma,
1687 adapter->rx_buffer_len,
1688 DMA_FROM_DEVICE);
1689 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
1690 dma_unmap_page(&pdev->dev, buffer_info->dma,
1691 PAGE_SIZE, DMA_FROM_DEVICE);
1692 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
1693 dma_unmap_single(&pdev->dev, buffer_info->dma,
1694 adapter->rx_ps_bsize0,
1695 DMA_FROM_DEVICE);
1696 buffer_info->dma = 0;
1697 }
1698
1699 if (buffer_info->page) {
1700 put_page(buffer_info->page);
1701 buffer_info->page = NULL;
1702 }
1703
1704 if (buffer_info->skb) {
1705 dev_kfree_skb(buffer_info->skb);
1706 buffer_info->skb = NULL;
1707 }
1708
1709 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1710 ps_page = &buffer_info->ps_pages[j];
1711 if (!ps_page->page)
1712 break;
1713 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1714 DMA_FROM_DEVICE);
1715 ps_page->dma = 0;
1716 put_page(ps_page->page);
1717 ps_page->page = NULL;
1718 }
1719 }
1720
1721 /* there also may be some cached data from a chained receive */
1722 if (rx_ring->rx_skb_top) {
1723 dev_kfree_skb(rx_ring->rx_skb_top);
1724 rx_ring->rx_skb_top = NULL;
1725 }
1726
1727 /* Zero out the descriptor ring */
1728 memset(rx_ring->desc, 0, rx_ring->size);
1729
1730 rx_ring->next_to_clean = 0;
1731 rx_ring->next_to_use = 0;
1732 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1733}
1734
1735static void e1000e_downshift_workaround(struct work_struct *work)
1736{
1737 struct e1000_adapter *adapter = container_of(work,
1738 struct e1000_adapter,
1739 downshift_task);
1740
1741 if (test_bit(__E1000_DOWN, &adapter->state))
1742 return;
1743
1744 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1745}
1746
1747/**
1748 * e1000_intr_msi - Interrupt Handler
1749 * @irq: interrupt number
1750 * @data: pointer to a network interface device structure
1751 **/
1752static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
1753{
1754 struct net_device *netdev = data;
1755 struct e1000_adapter *adapter = netdev_priv(netdev);
1756 struct e1000_hw *hw = &adapter->hw;
1757 u32 icr = er32(ICR);
1758
1759 /* read ICR disables interrupts using IAM */
1760 if (icr & E1000_ICR_LSC) {
1761 hw->mac.get_link_status = true;
1762 /* ICH8 workaround-- Call gig speed drop workaround on cable
1763 * disconnect (LSC) before accessing any PHY registers
1764 */
1765 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1766 (!(er32(STATUS) & E1000_STATUS_LU)))
1767 schedule_work(&adapter->downshift_task);
1768
1769 /* 80003ES2LAN workaround-- For packet buffer work-around on
1770 * link down event; disable receives here in the ISR and reset
1771 * adapter in watchdog
1772 */
1773 if (netif_carrier_ok(netdev) &&
1774 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1775 /* disable receives */
1776 u32 rctl = er32(RCTL);
1777
1778 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1779 adapter->flags |= FLAG_RESTART_NOW;
1780 }
1781 /* guard against interrupt when we're going down */
1782 if (!test_bit(__E1000_DOWN, &adapter->state))
1783 mod_delayed_work(adapter->e1000_workqueue,
1784 &adapter->watchdog_task, HZ);
1785 }
1786
1787 /* Reset on uncorrectable ECC error */
1788 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1789 u32 pbeccsts = er32(PBECCSTS);
1790
1791 adapter->corr_errors +=
1792 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1793 adapter->uncorr_errors +=
1794 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1795 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1796
1797 /* Do the reset outside of interrupt context */
1798 schedule_work(&adapter->reset_task);
1799
1800 /* return immediately since reset is imminent */
1801 return IRQ_HANDLED;
1802 }
1803
1804 if (napi_schedule_prep(&adapter->napi)) {
1805 adapter->total_tx_bytes = 0;
1806 adapter->total_tx_packets = 0;
1807 adapter->total_rx_bytes = 0;
1808 adapter->total_rx_packets = 0;
1809 __napi_schedule(&adapter->napi);
1810 }
1811
1812 return IRQ_HANDLED;
1813}
1814
1815/**
1816 * e1000_intr - Interrupt Handler
1817 * @irq: interrupt number
1818 * @data: pointer to a network interface device structure
1819 **/
1820static irqreturn_t e1000_intr(int __always_unused irq, void *data)
1821{
1822 struct net_device *netdev = data;
1823 struct e1000_adapter *adapter = netdev_priv(netdev);
1824 struct e1000_hw *hw = &adapter->hw;
1825 u32 rctl, icr = er32(ICR);
1826
1827 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
1828 return IRQ_NONE; /* Not our interrupt */
1829
1830 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1831 * not set, then the adapter didn't send an interrupt
1832 */
1833 if (!(icr & E1000_ICR_INT_ASSERTED))
1834 return IRQ_NONE;
1835
1836 /* Interrupt Auto-Mask...upon reading ICR,
1837 * interrupts are masked. No need for the
1838 * IMC write
1839 */
1840
1841 if (icr & E1000_ICR_LSC) {
1842 hw->mac.get_link_status = true;
1843 /* ICH8 workaround-- Call gig speed drop workaround on cable
1844 * disconnect (LSC) before accessing any PHY registers
1845 */
1846 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1847 (!(er32(STATUS) & E1000_STATUS_LU)))
1848 schedule_work(&adapter->downshift_task);
1849
1850 /* 80003ES2LAN workaround--
1851 * For packet buffer work-around on link down event;
1852 * disable receives here in the ISR and
1853 * reset adapter in watchdog
1854 */
1855 if (netif_carrier_ok(netdev) &&
1856 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1857 /* disable receives */
1858 rctl = er32(RCTL);
1859 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1860 adapter->flags |= FLAG_RESTART_NOW;
1861 }
1862 /* guard against interrupt when we're going down */
1863 if (!test_bit(__E1000_DOWN, &adapter->state))
1864 mod_delayed_work(adapter->e1000_workqueue,
1865 &adapter->watchdog_task, HZ);
1866 }
1867
1868 /* Reset on uncorrectable ECC error */
1869 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1870 u32 pbeccsts = er32(PBECCSTS);
1871
1872 adapter->corr_errors +=
1873 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1874 adapter->uncorr_errors +=
1875 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1876 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1877
1878 /* Do the reset outside of interrupt context */
1879 schedule_work(&adapter->reset_task);
1880
1881 /* return immediately since reset is imminent */
1882 return IRQ_HANDLED;
1883 }
1884
1885 if (napi_schedule_prep(&adapter->napi)) {
1886 adapter->total_tx_bytes = 0;
1887 adapter->total_tx_packets = 0;
1888 adapter->total_rx_bytes = 0;
1889 adapter->total_rx_packets = 0;
1890 __napi_schedule(&adapter->napi);
1891 }
1892
1893 return IRQ_HANDLED;
1894}
1895
1896static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
1897{
1898 struct net_device *netdev = data;
1899 struct e1000_adapter *adapter = netdev_priv(netdev);
1900 struct e1000_hw *hw = &adapter->hw;
1901 u32 icr = er32(ICR);
1902
1903 if (icr & adapter->eiac_mask)
1904 ew32(ICS, (icr & adapter->eiac_mask));
1905
1906 if (icr & E1000_ICR_LSC) {
1907 hw->mac.get_link_status = true;
1908 /* guard against interrupt when we're going down */
1909 if (!test_bit(__E1000_DOWN, &adapter->state))
1910 mod_delayed_work(adapter->e1000_workqueue,
1911 &adapter->watchdog_task, HZ);
1912 }
1913
1914 if (!test_bit(__E1000_DOWN, &adapter->state))
1915 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK);
1916
1917 return IRQ_HANDLED;
1918}
1919
1920static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
1921{
1922 struct net_device *netdev = data;
1923 struct e1000_adapter *adapter = netdev_priv(netdev);
1924 struct e1000_hw *hw = &adapter->hw;
1925 struct e1000_ring *tx_ring = adapter->tx_ring;
1926
1927 adapter->total_tx_bytes = 0;
1928 adapter->total_tx_packets = 0;
1929
1930 if (!e1000_clean_tx_irq(tx_ring))
1931 /* Ring was not completely cleaned, so fire another interrupt */
1932 ew32(ICS, tx_ring->ims_val);
1933
1934 if (!test_bit(__E1000_DOWN, &adapter->state))
1935 ew32(IMS, adapter->tx_ring->ims_val);
1936
1937 return IRQ_HANDLED;
1938}
1939
1940static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
1941{
1942 struct net_device *netdev = data;
1943 struct e1000_adapter *adapter = netdev_priv(netdev);
1944 struct e1000_ring *rx_ring = adapter->rx_ring;
1945
1946 /* Write the ITR value calculated at the end of the
1947 * previous interrupt.
1948 */
1949 if (rx_ring->set_itr) {
1950 u32 itr = rx_ring->itr_val ?
1951 1000000000 / (rx_ring->itr_val * 256) : 0;
1952
1953 writel(itr, rx_ring->itr_register);
1954 rx_ring->set_itr = 0;
1955 }
1956
1957 if (napi_schedule_prep(&adapter->napi)) {
1958 adapter->total_rx_bytes = 0;
1959 adapter->total_rx_packets = 0;
1960 __napi_schedule(&adapter->napi);
1961 }
1962 return IRQ_HANDLED;
1963}
1964
1965/**
1966 * e1000_configure_msix - Configure MSI-X hardware
1967 *
1968 * e1000_configure_msix sets up the hardware to properly
1969 * generate MSI-X interrupts.
1970 **/
1971static void e1000_configure_msix(struct e1000_adapter *adapter)
1972{
1973 struct e1000_hw *hw = &adapter->hw;
1974 struct e1000_ring *rx_ring = adapter->rx_ring;
1975 struct e1000_ring *tx_ring = adapter->tx_ring;
1976 int vector = 0;
1977 u32 ctrl_ext, ivar = 0;
1978
1979 adapter->eiac_mask = 0;
1980
1981 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1982 if (hw->mac.type == e1000_82574) {
1983 u32 rfctl = er32(RFCTL);
1984
1985 rfctl |= E1000_RFCTL_ACK_DIS;
1986 ew32(RFCTL, rfctl);
1987 }
1988
1989 /* Configure Rx vector */
1990 rx_ring->ims_val = E1000_IMS_RXQ0;
1991 adapter->eiac_mask |= rx_ring->ims_val;
1992 if (rx_ring->itr_val)
1993 writel(1000000000 / (rx_ring->itr_val * 256),
1994 rx_ring->itr_register);
1995 else
1996 writel(1, rx_ring->itr_register);
1997 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1998
1999 /* Configure Tx vector */
2000 tx_ring->ims_val = E1000_IMS_TXQ0;
2001 vector++;
2002 if (tx_ring->itr_val)
2003 writel(1000000000 / (tx_ring->itr_val * 256),
2004 tx_ring->itr_register);
2005 else
2006 writel(1, tx_ring->itr_register);
2007 adapter->eiac_mask |= tx_ring->ims_val;
2008 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
2009
2010 /* set vector for Other Causes, e.g. link changes */
2011 vector++;
2012 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
2013 if (rx_ring->itr_val)
2014 writel(1000000000 / (rx_ring->itr_val * 256),
2015 hw->hw_addr + E1000_EITR_82574(vector));
2016 else
2017 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
2018
2019 /* Cause Tx interrupts on every write back */
2020 ivar |= BIT(31);
2021
2022 ew32(IVAR, ivar);
2023
2024 /* enable MSI-X PBA support */
2025 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME;
2026 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME;
2027 ew32(CTRL_EXT, ctrl_ext);
2028 e1e_flush();
2029}
2030
2031void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2032{
2033 if (adapter->msix_entries) {
2034 pci_disable_msix(adapter->pdev);
2035 kfree(adapter->msix_entries);
2036 adapter->msix_entries = NULL;
2037 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2038 pci_disable_msi(adapter->pdev);
2039 adapter->flags &= ~FLAG_MSI_ENABLED;
2040 }
2041}
2042
2043/**
2044 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2045 *
2046 * Attempt to configure interrupts using the best available
2047 * capabilities of the hardware and kernel.
2048 **/
2049void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2050{
2051 int err;
2052 int i;
2053
2054 switch (adapter->int_mode) {
2055 case E1000E_INT_MODE_MSIX:
2056 if (adapter->flags & FLAG_HAS_MSIX) {
2057 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2058 adapter->msix_entries = kcalloc(adapter->num_vectors,
2059 sizeof(struct
2060 msix_entry),
2061 GFP_KERNEL);
2062 if (adapter->msix_entries) {
2063 struct e1000_adapter *a = adapter;
2064
2065 for (i = 0; i < adapter->num_vectors; i++)
2066 adapter->msix_entries[i].entry = i;
2067
2068 err = pci_enable_msix_range(a->pdev,
2069 a->msix_entries,
2070 a->num_vectors,
2071 a->num_vectors);
2072 if (err > 0)
2073 return;
2074 }
2075 /* MSI-X failed, so fall through and try MSI */
2076 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
2077 e1000e_reset_interrupt_capability(adapter);
2078 }
2079 adapter->int_mode = E1000E_INT_MODE_MSI;
2080 /* Fall through */
2081 case E1000E_INT_MODE_MSI:
2082 if (!pci_enable_msi(adapter->pdev)) {
2083 adapter->flags |= FLAG_MSI_ENABLED;
2084 } else {
2085 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2086 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
2087 }
2088 /* Fall through */
2089 case E1000E_INT_MODE_LEGACY:
2090 /* Don't do anything; this is the system default */
2091 break;
2092 }
2093
2094 /* store the number of vectors being used */
2095 adapter->num_vectors = 1;
2096}
2097
2098/**
2099 * e1000_request_msix - Initialize MSI-X interrupts
2100 *
2101 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2102 * kernel.
2103 **/
2104static int e1000_request_msix(struct e1000_adapter *adapter)
2105{
2106 struct net_device *netdev = adapter->netdev;
2107 int err = 0, vector = 0;
2108
2109 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2110 snprintf(adapter->rx_ring->name,
2111 sizeof(adapter->rx_ring->name) - 1,
2112 "%.14s-rx-0", netdev->name);
2113 else
2114 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2115 err = request_irq(adapter->msix_entries[vector].vector,
2116 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
2117 netdev);
2118 if (err)
2119 return err;
2120 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2121 E1000_EITR_82574(vector);
2122 adapter->rx_ring->itr_val = adapter->itr;
2123 vector++;
2124
2125 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2126 snprintf(adapter->tx_ring->name,
2127 sizeof(adapter->tx_ring->name) - 1,
2128 "%.14s-tx-0", netdev->name);
2129 else
2130 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2131 err = request_irq(adapter->msix_entries[vector].vector,
2132 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
2133 netdev);
2134 if (err)
2135 return err;
2136 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2137 E1000_EITR_82574(vector);
2138 adapter->tx_ring->itr_val = adapter->itr;
2139 vector++;
2140
2141 err = request_irq(adapter->msix_entries[vector].vector,
2142 e1000_msix_other, 0, netdev->name, netdev);
2143 if (err)
2144 return err;
2145
2146 e1000_configure_msix(adapter);
2147
2148 return 0;
2149}
2150
2151/**
2152 * e1000_request_irq - initialize interrupts
2153 *
2154 * Attempts to configure interrupts using the best available
2155 * capabilities of the hardware and kernel.
2156 **/
2157static int e1000_request_irq(struct e1000_adapter *adapter)
2158{
2159 struct net_device *netdev = adapter->netdev;
2160 int err;
2161
2162 if (adapter->msix_entries) {
2163 err = e1000_request_msix(adapter);
2164 if (!err)
2165 return err;
2166 /* fall back to MSI */
2167 e1000e_reset_interrupt_capability(adapter);
2168 adapter->int_mode = E1000E_INT_MODE_MSI;
2169 e1000e_set_interrupt_capability(adapter);
2170 }
2171 if (adapter->flags & FLAG_MSI_ENABLED) {
2172 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
2173 netdev->name, netdev);
2174 if (!err)
2175 return err;
2176
2177 /* fall back to legacy interrupt */
2178 e1000e_reset_interrupt_capability(adapter);
2179 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2180 }
2181
2182 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
2183 netdev->name, netdev);
2184 if (err)
2185 e_err("Unable to allocate interrupt, Error: %d\n", err);
2186
2187 return err;
2188}
2189
2190static void e1000_free_irq(struct e1000_adapter *adapter)
2191{
2192 struct net_device *netdev = adapter->netdev;
2193
2194 if (adapter->msix_entries) {
2195 int vector = 0;
2196
2197 free_irq(adapter->msix_entries[vector].vector, netdev);
2198 vector++;
2199
2200 free_irq(adapter->msix_entries[vector].vector, netdev);
2201 vector++;
2202
2203 /* Other Causes interrupt vector */
2204 free_irq(adapter->msix_entries[vector].vector, netdev);
2205 return;
2206 }
2207
2208 free_irq(adapter->pdev->irq, netdev);
2209}
2210
2211/**
2212 * e1000_irq_disable - Mask off interrupt generation on the NIC
2213 **/
2214static void e1000_irq_disable(struct e1000_adapter *adapter)
2215{
2216 struct e1000_hw *hw = &adapter->hw;
2217
2218 ew32(IMC, ~0);
2219 if (adapter->msix_entries)
2220 ew32(EIAC_82574, 0);
2221 e1e_flush();
2222
2223 if (adapter->msix_entries) {
2224 int i;
2225
2226 for (i = 0; i < adapter->num_vectors; i++)
2227 synchronize_irq(adapter->msix_entries[i].vector);
2228 } else {
2229 synchronize_irq(adapter->pdev->irq);
2230 }
2231}
2232
2233/**
2234 * e1000_irq_enable - Enable default interrupt generation settings
2235 **/
2236static void e1000_irq_enable(struct e1000_adapter *adapter)
2237{
2238 struct e1000_hw *hw = &adapter->hw;
2239
2240 if (adapter->msix_entries) {
2241 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2242 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER |
2243 IMS_OTHER_MASK);
2244 } else if (hw->mac.type >= e1000_pch_lpt) {
2245 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
2246 } else {
2247 ew32(IMS, IMS_ENABLE_MASK);
2248 }
2249 e1e_flush();
2250}
2251
2252/**
2253 * e1000e_get_hw_control - get control of the h/w from f/w
2254 * @adapter: address of board private structure
2255 *
2256 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2257 * For ASF and Pass Through versions of f/w this means that
2258 * the driver is loaded. For AMT version (only with 82573)
2259 * of the f/w this means that the network i/f is open.
2260 **/
2261void e1000e_get_hw_control(struct e1000_adapter *adapter)
2262{
2263 struct e1000_hw *hw = &adapter->hw;
2264 u32 ctrl_ext;
2265 u32 swsm;
2266
2267 /* Let firmware know the driver has taken over */
2268 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2269 swsm = er32(SWSM);
2270 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2271 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2272 ctrl_ext = er32(CTRL_EXT);
2273 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2274 }
2275}
2276
2277/**
2278 * e1000e_release_hw_control - release control of the h/w to f/w
2279 * @adapter: address of board private structure
2280 *
2281 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2282 * For ASF and Pass Through versions of f/w this means that the
2283 * driver is no longer loaded. For AMT version (only with 82573) i
2284 * of the f/w this means that the network i/f is closed.
2285 *
2286 **/
2287void e1000e_release_hw_control(struct e1000_adapter *adapter)
2288{
2289 struct e1000_hw *hw = &adapter->hw;
2290 u32 ctrl_ext;
2291 u32 swsm;
2292
2293 /* Let firmware taken over control of h/w */
2294 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2295 swsm = er32(SWSM);
2296 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2297 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2298 ctrl_ext = er32(CTRL_EXT);
2299 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2300 }
2301}
2302
2303/**
2304 * e1000_alloc_ring_dma - allocate memory for a ring structure
2305 **/
2306static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2307 struct e1000_ring *ring)
2308{
2309 struct pci_dev *pdev = adapter->pdev;
2310
2311 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2312 GFP_KERNEL);
2313 if (!ring->desc)
2314 return -ENOMEM;
2315
2316 return 0;
2317}
2318
2319/**
2320 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2321 * @tx_ring: Tx descriptor ring
2322 *
2323 * Return 0 on success, negative on failure
2324 **/
2325int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
2326{
2327 struct e1000_adapter *adapter = tx_ring->adapter;
2328 int err = -ENOMEM, size;
2329
2330 size = sizeof(struct e1000_buffer) * tx_ring->count;
2331 tx_ring->buffer_info = vzalloc(size);
2332 if (!tx_ring->buffer_info)
2333 goto err;
2334
2335 /* round up to nearest 4K */
2336 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2337 tx_ring->size = ALIGN(tx_ring->size, 4096);
2338
2339 err = e1000_alloc_ring_dma(adapter, tx_ring);
2340 if (err)
2341 goto err;
2342
2343 tx_ring->next_to_use = 0;
2344 tx_ring->next_to_clean = 0;
2345
2346 return 0;
2347err:
2348 vfree(tx_ring->buffer_info);
2349 e_err("Unable to allocate memory for the transmit descriptor ring\n");
2350 return err;
2351}
2352
2353/**
2354 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2355 * @rx_ring: Rx descriptor ring
2356 *
2357 * Returns 0 on success, negative on failure
2358 **/
2359int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
2360{
2361 struct e1000_adapter *adapter = rx_ring->adapter;
2362 struct e1000_buffer *buffer_info;
2363 int i, size, desc_len, err = -ENOMEM;
2364
2365 size = sizeof(struct e1000_buffer) * rx_ring->count;
2366 rx_ring->buffer_info = vzalloc(size);
2367 if (!rx_ring->buffer_info)
2368 goto err;
2369
2370 for (i = 0; i < rx_ring->count; i++) {
2371 buffer_info = &rx_ring->buffer_info[i];
2372 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2373 sizeof(struct e1000_ps_page),
2374 GFP_KERNEL);
2375 if (!buffer_info->ps_pages)
2376 goto err_pages;
2377 }
2378
2379 desc_len = sizeof(union e1000_rx_desc_packet_split);
2380
2381 /* Round up to nearest 4K */
2382 rx_ring->size = rx_ring->count * desc_len;
2383 rx_ring->size = ALIGN(rx_ring->size, 4096);
2384
2385 err = e1000_alloc_ring_dma(adapter, rx_ring);
2386 if (err)
2387 goto err_pages;
2388
2389 rx_ring->next_to_clean = 0;
2390 rx_ring->next_to_use = 0;
2391 rx_ring->rx_skb_top = NULL;
2392
2393 return 0;
2394
2395err_pages:
2396 for (i = 0; i < rx_ring->count; i++) {
2397 buffer_info = &rx_ring->buffer_info[i];
2398 kfree(buffer_info->ps_pages);
2399 }
2400err:
2401 vfree(rx_ring->buffer_info);
2402 e_err("Unable to allocate memory for the receive descriptor ring\n");
2403 return err;
2404}
2405
2406/**
2407 * e1000_clean_tx_ring - Free Tx Buffers
2408 * @tx_ring: Tx descriptor ring
2409 **/
2410static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
2411{
2412 struct e1000_adapter *adapter = tx_ring->adapter;
2413 struct e1000_buffer *buffer_info;
2414 unsigned long size;
2415 unsigned int i;
2416
2417 for (i = 0; i < tx_ring->count; i++) {
2418 buffer_info = &tx_ring->buffer_info[i];
2419 e1000_put_txbuf(tx_ring, buffer_info, false);
2420 }
2421
2422 netdev_reset_queue(adapter->netdev);
2423 size = sizeof(struct e1000_buffer) * tx_ring->count;
2424 memset(tx_ring->buffer_info, 0, size);
2425
2426 memset(tx_ring->desc, 0, tx_ring->size);
2427
2428 tx_ring->next_to_use = 0;
2429 tx_ring->next_to_clean = 0;
2430}
2431
2432/**
2433 * e1000e_free_tx_resources - Free Tx Resources per Queue
2434 * @tx_ring: Tx descriptor ring
2435 *
2436 * Free all transmit software resources
2437 **/
2438void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
2439{
2440 struct e1000_adapter *adapter = tx_ring->adapter;
2441 struct pci_dev *pdev = adapter->pdev;
2442
2443 e1000_clean_tx_ring(tx_ring);
2444
2445 vfree(tx_ring->buffer_info);
2446 tx_ring->buffer_info = NULL;
2447
2448 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2449 tx_ring->dma);
2450 tx_ring->desc = NULL;
2451}
2452
2453/**
2454 * e1000e_free_rx_resources - Free Rx Resources
2455 * @rx_ring: Rx descriptor ring
2456 *
2457 * Free all receive software resources
2458 **/
2459void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
2460{
2461 struct e1000_adapter *adapter = rx_ring->adapter;
2462 struct pci_dev *pdev = adapter->pdev;
2463 int i;
2464
2465 e1000_clean_rx_ring(rx_ring);
2466
2467 for (i = 0; i < rx_ring->count; i++)
2468 kfree(rx_ring->buffer_info[i].ps_pages);
2469
2470 vfree(rx_ring->buffer_info);
2471 rx_ring->buffer_info = NULL;
2472
2473 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2474 rx_ring->dma);
2475 rx_ring->desc = NULL;
2476}
2477
2478/**
2479 * e1000_update_itr - update the dynamic ITR value based on statistics
2480 * @adapter: pointer to adapter
2481 * @itr_setting: current adapter->itr
2482 * @packets: the number of packets during this measurement interval
2483 * @bytes: the number of bytes during this measurement interval
2484 *
2485 * Stores a new ITR value based on packets and byte
2486 * counts during the last interrupt. The advantage of per interrupt
2487 * computation is faster updates and more accurate ITR for the current
2488 * traffic pattern. Constants in this function were computed
2489 * based on theoretical maximum wire speed and thresholds were set based
2490 * on testing data as well as attempting to minimize response time
2491 * while increasing bulk throughput. This functionality is controlled
2492 * by the InterruptThrottleRate module parameter.
2493 **/
2494static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
2495{
2496 unsigned int retval = itr_setting;
2497
2498 if (packets == 0)
2499 return itr_setting;
2500
2501 switch (itr_setting) {
2502 case lowest_latency:
2503 /* handle TSO and jumbo frames */
2504 if (bytes / packets > 8000)
2505 retval = bulk_latency;
2506 else if ((packets < 5) && (bytes > 512))
2507 retval = low_latency;
2508 break;
2509 case low_latency: /* 50 usec aka 20000 ints/s */
2510 if (bytes > 10000) {
2511 /* this if handles the TSO accounting */
2512 if (bytes / packets > 8000)
2513 retval = bulk_latency;
2514 else if ((packets < 10) || ((bytes / packets) > 1200))
2515 retval = bulk_latency;
2516 else if ((packets > 35))
2517 retval = lowest_latency;
2518 } else if (bytes / packets > 2000) {
2519 retval = bulk_latency;
2520 } else if (packets <= 2 && bytes < 512) {
2521 retval = lowest_latency;
2522 }
2523 break;
2524 case bulk_latency: /* 250 usec aka 4000 ints/s */
2525 if (bytes > 25000) {
2526 if (packets > 35)
2527 retval = low_latency;
2528 } else if (bytes < 6000) {
2529 retval = low_latency;
2530 }
2531 break;
2532 }
2533
2534 return retval;
2535}
2536
2537static void e1000_set_itr(struct e1000_adapter *adapter)
2538{
2539 u16 current_itr;
2540 u32 new_itr = adapter->itr;
2541
2542 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2543 if (adapter->link_speed != SPEED_1000) {
2544 current_itr = 0;
2545 new_itr = 4000;
2546 goto set_itr_now;
2547 }
2548
2549 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2550 new_itr = 0;
2551 goto set_itr_now;
2552 }
2553
2554 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2555 adapter->total_tx_packets,
2556 adapter->total_tx_bytes);
2557 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2558 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2559 adapter->tx_itr = low_latency;
2560
2561 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2562 adapter->total_rx_packets,
2563 adapter->total_rx_bytes);
2564 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2565 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2566 adapter->rx_itr = low_latency;
2567
2568 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2569
2570 /* counts and packets in update_itr are dependent on these numbers */
2571 switch (current_itr) {
2572 case lowest_latency:
2573 new_itr = 70000;
2574 break;
2575 case low_latency:
2576 new_itr = 20000; /* aka hwitr = ~200 */
2577 break;
2578 case bulk_latency:
2579 new_itr = 4000;
2580 break;
2581 default:
2582 break;
2583 }
2584
2585set_itr_now:
2586 if (new_itr != adapter->itr) {
2587 /* this attempts to bias the interrupt rate towards Bulk
2588 * by adding intermediate steps when interrupt rate is
2589 * increasing
2590 */
2591 new_itr = new_itr > adapter->itr ?
2592 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
2593 adapter->itr = new_itr;
2594 adapter->rx_ring->itr_val = new_itr;
2595 if (adapter->msix_entries)
2596 adapter->rx_ring->set_itr = 1;
2597 else
2598 e1000e_write_itr(adapter, new_itr);
2599 }
2600}
2601
2602/**
2603 * e1000e_write_itr - write the ITR value to the appropriate registers
2604 * @adapter: address of board private structure
2605 * @itr: new ITR value to program
2606 *
2607 * e1000e_write_itr determines if the adapter is in MSI-X mode
2608 * and, if so, writes the EITR registers with the ITR value.
2609 * Otherwise, it writes the ITR value into the ITR register.
2610 **/
2611void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2612{
2613 struct e1000_hw *hw = &adapter->hw;
2614 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2615
2616 if (adapter->msix_entries) {
2617 int vector;
2618
2619 for (vector = 0; vector < adapter->num_vectors; vector++)
2620 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2621 } else {
2622 ew32(ITR, new_itr);
2623 }
2624}
2625
2626/**
2627 * e1000_alloc_queues - Allocate memory for all rings
2628 * @adapter: board private structure to initialize
2629 **/
2630static int e1000_alloc_queues(struct e1000_adapter *adapter)
2631{
2632 int size = sizeof(struct e1000_ring);
2633
2634 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
2635 if (!adapter->tx_ring)
2636 goto err;
2637 adapter->tx_ring->count = adapter->tx_ring_count;
2638 adapter->tx_ring->adapter = adapter;
2639
2640 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
2641 if (!adapter->rx_ring)
2642 goto err;
2643 adapter->rx_ring->count = adapter->rx_ring_count;
2644 adapter->rx_ring->adapter = adapter;
2645
2646 return 0;
2647err:
2648 e_err("Unable to allocate memory for queues\n");
2649 kfree(adapter->rx_ring);
2650 kfree(adapter->tx_ring);
2651 return -ENOMEM;
2652}
2653
2654/**
2655 * e1000e_poll - NAPI Rx polling callback
2656 * @napi: struct associated with this polling callback
2657 * @budget: number of packets driver is allowed to process this poll
2658 **/
2659static int e1000e_poll(struct napi_struct *napi, int budget)
2660{
2661 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2662 napi);
2663 struct e1000_hw *hw = &adapter->hw;
2664 struct net_device *poll_dev = adapter->netdev;
2665 int tx_cleaned = 1, work_done = 0;
2666
2667 adapter = netdev_priv(poll_dev);
2668
2669 if (!adapter->msix_entries ||
2670 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2671 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
2672
2673 adapter->clean_rx(adapter->rx_ring, &work_done, budget);
2674
2675 if (!tx_cleaned || work_done == budget)
2676 return budget;
2677
2678 /* Exit the polling mode, but don't re-enable interrupts if stack might
2679 * poll us due to busy-polling
2680 */
2681 if (likely(napi_complete_done(napi, work_done))) {
2682 if (adapter->itr_setting & 3)
2683 e1000_set_itr(adapter);
2684 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2685 if (adapter->msix_entries)
2686 ew32(IMS, adapter->rx_ring->ims_val);
2687 else
2688 e1000_irq_enable(adapter);
2689 }
2690 }
2691
2692 return work_done;
2693}
2694
2695static int e1000_vlan_rx_add_vid(struct net_device *netdev,
2696 __always_unused __be16 proto, u16 vid)
2697{
2698 struct e1000_adapter *adapter = netdev_priv(netdev);
2699 struct e1000_hw *hw = &adapter->hw;
2700 u32 vfta, index;
2701
2702 /* don't update vlan cookie if already programmed */
2703 if ((adapter->hw.mng_cookie.status &
2704 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2705 (vid == adapter->mng_vlan_id))
2706 return 0;
2707
2708 /* add VID to filter table */
2709 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2710 index = (vid >> 5) & 0x7F;
2711 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2712 vfta |= BIT((vid & 0x1F));
2713 hw->mac.ops.write_vfta(hw, index, vfta);
2714 }
2715
2716 set_bit(vid, adapter->active_vlans);
2717
2718 return 0;
2719}
2720
2721static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
2722 __always_unused __be16 proto, u16 vid)
2723{
2724 struct e1000_adapter *adapter = netdev_priv(netdev);
2725 struct e1000_hw *hw = &adapter->hw;
2726 u32 vfta, index;
2727
2728 if ((adapter->hw.mng_cookie.status &
2729 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2730 (vid == adapter->mng_vlan_id)) {
2731 /* release control to f/w */
2732 e1000e_release_hw_control(adapter);
2733 return 0;
2734 }
2735
2736 /* remove VID from filter table */
2737 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2738 index = (vid >> 5) & 0x7F;
2739 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2740 vfta &= ~BIT((vid & 0x1F));
2741 hw->mac.ops.write_vfta(hw, index, vfta);
2742 }
2743
2744 clear_bit(vid, adapter->active_vlans);
2745
2746 return 0;
2747}
2748
2749/**
2750 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2751 * @adapter: board private structure to initialize
2752 **/
2753static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
2754{
2755 struct net_device *netdev = adapter->netdev;
2756 struct e1000_hw *hw = &adapter->hw;
2757 u32 rctl;
2758
2759 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2760 /* disable VLAN receive filtering */
2761 rctl = er32(RCTL);
2762 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2763 ew32(RCTL, rctl);
2764
2765 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2766 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2767 adapter->mng_vlan_id);
2768 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
2769 }
2770 }
2771}
2772
2773/**
2774 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2775 * @adapter: board private structure to initialize
2776 **/
2777static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2778{
2779 struct e1000_hw *hw = &adapter->hw;
2780 u32 rctl;
2781
2782 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2783 /* enable VLAN receive filtering */
2784 rctl = er32(RCTL);
2785 rctl |= E1000_RCTL_VFE;
2786 rctl &= ~E1000_RCTL_CFIEN;
2787 ew32(RCTL, rctl);
2788 }
2789}
2790
2791/**
2792 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping
2793 * @adapter: board private structure to initialize
2794 **/
2795static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
2796{
2797 struct e1000_hw *hw = &adapter->hw;
2798 u32 ctrl;
2799
2800 /* disable VLAN tag insert/strip */
2801 ctrl = er32(CTRL);
2802 ctrl &= ~E1000_CTRL_VME;
2803 ew32(CTRL, ctrl);
2804}
2805
2806/**
2807 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2808 * @adapter: board private structure to initialize
2809 **/
2810static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2811{
2812 struct e1000_hw *hw = &adapter->hw;
2813 u32 ctrl;
2814
2815 /* enable VLAN tag insert/strip */
2816 ctrl = er32(CTRL);
2817 ctrl |= E1000_CTRL_VME;
2818 ew32(CTRL, ctrl);
2819}
2820
2821static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2822{
2823 struct net_device *netdev = adapter->netdev;
2824 u16 vid = adapter->hw.mng_cookie.vlan_id;
2825 u16 old_vid = adapter->mng_vlan_id;
2826
2827 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2828 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
2829 adapter->mng_vlan_id = vid;
2830 }
2831
2832 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2833 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
2834}
2835
2836static void e1000_restore_vlan(struct e1000_adapter *adapter)
2837{
2838 u16 vid;
2839
2840 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
2841
2842 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2843 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
2844}
2845
2846static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
2847{
2848 struct e1000_hw *hw = &adapter->hw;
2849 u32 manc, manc2h, mdef, i, j;
2850
2851 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2852 return;
2853
2854 manc = er32(MANC);
2855
2856 /* enable receiving management packets to the host. this will probably
2857 * generate destination unreachable messages from the host OS, but
2858 * the packets will be handled on SMBUS
2859 */
2860 manc |= E1000_MANC_EN_MNG2HOST;
2861 manc2h = er32(MANC2H);
2862
2863 switch (hw->mac.type) {
2864 default:
2865 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2866 break;
2867 case e1000_82574:
2868 case e1000_82583:
2869 /* Check if IPMI pass-through decision filter already exists;
2870 * if so, enable it.
2871 */
2872 for (i = 0, j = 0; i < 8; i++) {
2873 mdef = er32(MDEF(i));
2874
2875 /* Ignore filters with anything other than IPMI ports */
2876 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2877 continue;
2878
2879 /* Enable this decision filter in MANC2H */
2880 if (mdef)
2881 manc2h |= BIT(i);
2882
2883 j |= mdef;
2884 }
2885
2886 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2887 break;
2888
2889 /* Create new decision filter in an empty filter */
2890 for (i = 0, j = 0; i < 8; i++)
2891 if (er32(MDEF(i)) == 0) {
2892 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2893 E1000_MDEF_PORT_664));
2894 manc2h |= BIT(1);
2895 j++;
2896 break;
2897 }
2898
2899 if (!j)
2900 e_warn("Unable to create IPMI pass-through filter\n");
2901 break;
2902 }
2903
2904 ew32(MANC2H, manc2h);
2905 ew32(MANC, manc);
2906}
2907
2908/**
2909 * e1000_configure_tx - Configure Transmit Unit after Reset
2910 * @adapter: board private structure
2911 *
2912 * Configure the Tx unit of the MAC after a reset.
2913 **/
2914static void e1000_configure_tx(struct e1000_adapter *adapter)
2915{
2916 struct e1000_hw *hw = &adapter->hw;
2917 struct e1000_ring *tx_ring = adapter->tx_ring;
2918 u64 tdba;
2919 u32 tdlen, tctl, tarc;
2920
2921 /* Setup the HW Tx Head and Tail descriptor pointers */
2922 tdba = tx_ring->dma;
2923 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
2924 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2925 ew32(TDBAH(0), (tdba >> 32));
2926 ew32(TDLEN(0), tdlen);
2927 ew32(TDH(0), 0);
2928 ew32(TDT(0), 0);
2929 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2930 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
2931
2932 writel(0, tx_ring->head);
2933 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2934 e1000e_update_tdt_wa(tx_ring, 0);
2935 else
2936 writel(0, tx_ring->tail);
2937
2938 /* Set the Tx Interrupt Delay register */
2939 ew32(TIDV, adapter->tx_int_delay);
2940 /* Tx irq moderation */
2941 ew32(TADV, adapter->tx_abs_int_delay);
2942
2943 if (adapter->flags2 & FLAG2_DMA_BURST) {
2944 u32 txdctl = er32(TXDCTL(0));
2945
2946 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2947 E1000_TXDCTL_WTHRESH);
2948 /* set up some performance related parameters to encourage the
2949 * hardware to use the bus more efficiently in bursts, depends
2950 * on the tx_int_delay to be enabled,
2951 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2952 * hthresh = 1 ==> prefetch when one or more available
2953 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2954 * BEWARE: this seems to work but should be considered first if
2955 * there are Tx hangs or other Tx related bugs
2956 */
2957 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2958 ew32(TXDCTL(0), txdctl);
2959 }
2960 /* erratum work around: set txdctl the same for both queues */
2961 ew32(TXDCTL(1), er32(TXDCTL(0)));
2962
2963 /* Program the Transmit Control Register */
2964 tctl = er32(TCTL);
2965 tctl &= ~E1000_TCTL_CT;
2966 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2967 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2968
2969 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
2970 tarc = er32(TARC(0));
2971 /* set the speed mode bit, we'll clear it if we're not at
2972 * gigabit link later
2973 */
2974#define SPEED_MODE_BIT BIT(21)
2975 tarc |= SPEED_MODE_BIT;
2976 ew32(TARC(0), tarc);
2977 }
2978
2979 /* errata: program both queues to unweighted RR */
2980 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
2981 tarc = er32(TARC(0));
2982 tarc |= 1;
2983 ew32(TARC(0), tarc);
2984 tarc = er32(TARC(1));
2985 tarc |= 1;
2986 ew32(TARC(1), tarc);
2987 }
2988
2989 /* Setup Transmit Descriptor Settings for eop descriptor */
2990 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2991
2992 /* only set IDE if we are delaying interrupts using the timers */
2993 if (adapter->tx_int_delay)
2994 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2995
2996 /* enable Report Status bit */
2997 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2998
2999 ew32(TCTL, tctl);
3000
3001 hw->mac.ops.config_collision_dist(hw);
3002
3003 /* SPT and KBL Si errata workaround to avoid data corruption */
3004 if (hw->mac.type == e1000_pch_spt) {
3005 u32 reg_val;
3006
3007 reg_val = er32(IOSFPC);
3008 reg_val |= E1000_RCTL_RDMTS_HEX;
3009 ew32(IOSFPC, reg_val);
3010
3011 reg_val = er32(TARC(0));
3012 /* SPT and KBL Si errata workaround to avoid Tx hang.
3013 * Dropping the number of outstanding requests from
3014 * 3 to 2 in order to avoid a buffer overrun.
3015 */
3016 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3017 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ;
3018 ew32(TARC(0), reg_val);
3019 }
3020}
3021
3022/**
3023 * e1000_setup_rctl - configure the receive control registers
3024 * @adapter: Board private structure
3025 **/
3026#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3027 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3028static void e1000_setup_rctl(struct e1000_adapter *adapter)
3029{
3030 struct e1000_hw *hw = &adapter->hw;
3031 u32 rctl, rfctl;
3032 u32 pages = 0;
3033
3034 /* Workaround Si errata on PCHx - configure jumbo frame flow.
3035 * If jumbo frames not set, program related MAC/PHY registers
3036 * to h/w defaults
3037 */
3038 if (hw->mac.type >= e1000_pch2lan) {
3039 s32 ret_val;
3040
3041 if (adapter->netdev->mtu > ETH_DATA_LEN)
3042 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
3043 else
3044 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
3045
3046 if (ret_val)
3047 e_dbg("failed to enable|disable jumbo frame workaround mode\n");
3048 }
3049
3050 /* Program MC offset vector base */
3051 rctl = er32(RCTL);
3052 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3053 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3054 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3055 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3056
3057 /* Do not Store bad packets */
3058 rctl &= ~E1000_RCTL_SBP;
3059
3060 /* Enable Long Packet receive */
3061 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3062 rctl &= ~E1000_RCTL_LPE;
3063 else
3064 rctl |= E1000_RCTL_LPE;
3065
3066 /* Some systems expect that the CRC is included in SMBUS traffic. The
3067 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3068 * host memory when this is enabled
3069 */
3070 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3071 rctl |= E1000_RCTL_SECRC;
3072
3073 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3074 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3075 u16 phy_data;
3076
3077 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3078 phy_data &= 0xfff8;
3079 phy_data |= BIT(2);
3080 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3081
3082 e1e_rphy(hw, 22, &phy_data);
3083 phy_data &= 0x0fff;
3084 phy_data |= BIT(14);
3085 e1e_wphy(hw, 0x10, 0x2823);
3086 e1e_wphy(hw, 0x11, 0x0003);
3087 e1e_wphy(hw, 22, phy_data);
3088 }
3089
3090 /* Setup buffer sizes */
3091 rctl &= ~E1000_RCTL_SZ_4096;
3092 rctl |= E1000_RCTL_BSEX;
3093 switch (adapter->rx_buffer_len) {
3094 case 2048:
3095 default:
3096 rctl |= E1000_RCTL_SZ_2048;
3097 rctl &= ~E1000_RCTL_BSEX;
3098 break;
3099 case 4096:
3100 rctl |= E1000_RCTL_SZ_4096;
3101 break;
3102 case 8192:
3103 rctl |= E1000_RCTL_SZ_8192;
3104 break;
3105 case 16384:
3106 rctl |= E1000_RCTL_SZ_16384;
3107 break;
3108 }
3109
3110 /* Enable Extended Status in all Receive Descriptors */
3111 rfctl = er32(RFCTL);
3112 rfctl |= E1000_RFCTL_EXTEN;
3113 ew32(RFCTL, rfctl);
3114
3115 /* 82571 and greater support packet-split where the protocol
3116 * header is placed in skb->data and the packet data is
3117 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3118 * In the case of a non-split, skb->data is linearly filled,
3119 * followed by the page buffers. Therefore, skb->data is
3120 * sized to hold the largest protocol header.
3121 *
3122 * allocations using alloc_page take too long for regular MTU
3123 * so only enable packet split for jumbo frames
3124 *
3125 * Using pages when the page size is greater than 16k wastes
3126 * a lot of memory, since we allocate 3 pages at all times
3127 * per packet.
3128 */
3129 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
3130 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
3131 adapter->rx_ps_pages = pages;
3132 else
3133 adapter->rx_ps_pages = 0;
3134
3135 if (adapter->rx_ps_pages) {
3136 u32 psrctl = 0;
3137
3138 /* Enable Packet split descriptors */
3139 rctl |= E1000_RCTL_DTYP_PS;
3140
3141 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
3142
3143 switch (adapter->rx_ps_pages) {
3144 case 3:
3145 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3146 /* fall-through */
3147 case 2:
3148 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3149 /* fall-through */
3150 case 1:
3151 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
3152 break;
3153 }
3154
3155 ew32(PSRCTL, psrctl);
3156 }
3157
3158 /* This is useful for sniffing bad packets. */
3159 if (adapter->netdev->features & NETIF_F_RXALL) {
3160 /* UPE and MPE will be handled by normal PROMISC logic
3161 * in e1000e_set_rx_mode
3162 */
3163 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3164 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3165 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3166
3167 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3168 E1000_RCTL_DPF | /* Allow filtered pause */
3169 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3170 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3171 * and that breaks VLANs.
3172 */
3173 }
3174
3175 ew32(RCTL, rctl);
3176 /* just started the receive unit, no need to restart */
3177 adapter->flags &= ~FLAG_RESTART_NOW;
3178}
3179
3180/**
3181 * e1000_configure_rx - Configure Receive Unit after Reset
3182 * @adapter: board private structure
3183 *
3184 * Configure the Rx unit of the MAC after a reset.
3185 **/
3186static void e1000_configure_rx(struct e1000_adapter *adapter)
3187{
3188 struct e1000_hw *hw = &adapter->hw;
3189 struct e1000_ring *rx_ring = adapter->rx_ring;
3190 u64 rdba;
3191 u32 rdlen, rctl, rxcsum, ctrl_ext;
3192
3193 if (adapter->rx_ps_pages) {
3194 /* this is a 32 byte descriptor */
3195 rdlen = rx_ring->count *
3196 sizeof(union e1000_rx_desc_packet_split);
3197 adapter->clean_rx = e1000_clean_rx_irq_ps;
3198 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
3199 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
3200 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3201 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3202 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
3203 } else {
3204 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3205 adapter->clean_rx = e1000_clean_rx_irq;
3206 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3207 }
3208
3209 /* disable receives while setting up the descriptors */
3210 rctl = er32(RCTL);
3211 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3212 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3213 e1e_flush();
3214 usleep_range(10000, 11000);
3215
3216 if (adapter->flags2 & FLAG2_DMA_BURST) {
3217 /* set the writeback threshold (only takes effect if the RDTR
3218 * is set). set GRAN=1 and write back up to 0x4 worth, and
3219 * enable prefetching of 0x20 Rx descriptors
3220 * granularity = 01
3221 * wthresh = 04,
3222 * hthresh = 04,
3223 * pthresh = 0x20
3224 */
3225 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3226 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3227 }
3228
3229 /* set the Receive Delay Timer Register */
3230 ew32(RDTR, adapter->rx_int_delay);
3231
3232 /* irq moderation */
3233 ew32(RADV, adapter->rx_abs_int_delay);
3234 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
3235 e1000e_write_itr(adapter, adapter->itr);
3236
3237 ctrl_ext = er32(CTRL_EXT);
3238 /* Auto-Mask interrupts upon ICR access */
3239 ctrl_ext |= E1000_CTRL_EXT_IAME;
3240 ew32(IAM, 0xffffffff);
3241 ew32(CTRL_EXT, ctrl_ext);
3242 e1e_flush();
3243
3244 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3245 * the Base and Length of the Rx Descriptor Ring
3246 */
3247 rdba = rx_ring->dma;
3248 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3249 ew32(RDBAH(0), (rdba >> 32));
3250 ew32(RDLEN(0), rdlen);
3251 ew32(RDH(0), 0);
3252 ew32(RDT(0), 0);
3253 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3254 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
3255
3256 writel(0, rx_ring->head);
3257 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
3258 e1000e_update_rdt_wa(rx_ring, 0);
3259 else
3260 writel(0, rx_ring->tail);
3261
3262 /* Enable Receive Checksum Offload for TCP and UDP */
3263 rxcsum = er32(RXCSUM);
3264 if (adapter->netdev->features & NETIF_F_RXCSUM)
3265 rxcsum |= E1000_RXCSUM_TUOFL;
3266 else
3267 rxcsum &= ~E1000_RXCSUM_TUOFL;
3268 ew32(RXCSUM, rxcsum);
3269
3270 /* With jumbo frames, excessive C-state transition latencies result
3271 * in dropped transactions.
3272 */
3273 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3274 u32 lat =
3275 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3276 adapter->max_frame_size) * 8 / 1000;
3277
3278 if (adapter->flags & FLAG_IS_ICH) {
3279 u32 rxdctl = er32(RXDCTL(0));
3280
3281 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8));
3282 }
3283
3284 dev_info(&adapter->pdev->dev,
3285 "Some CPU C-states have been disabled in order to enable jumbo frames\n");
3286 pm_qos_update_request(&adapter->pm_qos_req, lat);
3287 } else {
3288 pm_qos_update_request(&adapter->pm_qos_req,
3289 PM_QOS_DEFAULT_VALUE);
3290 }
3291
3292 /* Enable Receives */
3293 ew32(RCTL, rctl);
3294}
3295
3296/**
3297 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3298 * @netdev: network interface device structure
3299 *
3300 * Writes multicast address list to the MTA hash table.
3301 * Returns: -ENOMEM on failure
3302 * 0 on no addresses written
3303 * X on writing X addresses to MTA
3304 */
3305static int e1000e_write_mc_addr_list(struct net_device *netdev)
3306{
3307 struct e1000_adapter *adapter = netdev_priv(netdev);
3308 struct e1000_hw *hw = &adapter->hw;
3309 struct netdev_hw_addr *ha;
3310 u8 *mta_list;
3311 int i;
3312
3313 if (netdev_mc_empty(netdev)) {
3314 /* nothing to program, so clear mc list */
3315 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3316 return 0;
3317 }
3318
3319 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC);
3320 if (!mta_list)
3321 return -ENOMEM;
3322
3323 /* update_mc_addr_list expects a packed array of only addresses. */
3324 i = 0;
3325 netdev_for_each_mc_addr(ha, netdev)
3326 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3327
3328 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3329 kfree(mta_list);
3330
3331 return netdev_mc_count(netdev);
3332}
3333
3334/**
3335 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3336 * @netdev: network interface device structure
3337 *
3338 * Writes unicast address list to the RAR table.
3339 * Returns: -ENOMEM on failure/insufficient address space
3340 * 0 on no addresses written
3341 * X on writing X addresses to the RAR table
3342 **/
3343static int e1000e_write_uc_addr_list(struct net_device *netdev)
3344{
3345 struct e1000_adapter *adapter = netdev_priv(netdev);
3346 struct e1000_hw *hw = &adapter->hw;
3347 unsigned int rar_entries;
3348 int count = 0;
3349
3350 rar_entries = hw->mac.ops.rar_get_count(hw);
3351
3352 /* save a rar entry for our hardware address */
3353 rar_entries--;
3354
3355 /* save a rar entry for the LAA workaround */
3356 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3357 rar_entries--;
3358
3359 /* return ENOMEM indicating insufficient memory for addresses */
3360 if (netdev_uc_count(netdev) > rar_entries)
3361 return -ENOMEM;
3362
3363 if (!netdev_uc_empty(netdev) && rar_entries) {
3364 struct netdev_hw_addr *ha;
3365
3366 /* write the addresses in reverse order to avoid write
3367 * combining
3368 */
3369 netdev_for_each_uc_addr(ha, netdev) {
3370 int ret_val;
3371
3372 if (!rar_entries)
3373 break;
3374 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
3375 if (ret_val < 0)
3376 return -ENOMEM;
3377 count++;
3378 }
3379 }
3380
3381 /* zero out the remaining RAR entries not used above */
3382 for (; rar_entries > 0; rar_entries--) {
3383 ew32(RAH(rar_entries), 0);
3384 ew32(RAL(rar_entries), 0);
3385 }
3386 e1e_flush();
3387
3388 return count;
3389}
3390
3391/**
3392 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3393 * @netdev: network interface device structure
3394 *
3395 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3396 * address list or the network interface flags are updated. This routine is
3397 * responsible for configuring the hardware for proper unicast, multicast,
3398 * promiscuous mode, and all-multi behavior.
3399 **/
3400static void e1000e_set_rx_mode(struct net_device *netdev)
3401{
3402 struct e1000_adapter *adapter = netdev_priv(netdev);
3403 struct e1000_hw *hw = &adapter->hw;
3404 u32 rctl;
3405
3406 if (pm_runtime_suspended(netdev->dev.parent))
3407 return;
3408
3409 /* Check for Promiscuous and All Multicast modes */
3410 rctl = er32(RCTL);
3411
3412 /* clear the affected bits */
3413 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3414
3415 if (netdev->flags & IFF_PROMISC) {
3416 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3417 /* Do not hardware filter VLANs in promisc mode */
3418 e1000e_vlan_filter_disable(adapter);
3419 } else {
3420 int count;
3421
3422 if (netdev->flags & IFF_ALLMULTI) {
3423 rctl |= E1000_RCTL_MPE;
3424 } else {
3425 /* Write addresses to the MTA, if the attempt fails
3426 * then we should just turn on promiscuous mode so
3427 * that we can at least receive multicast traffic
3428 */
3429 count = e1000e_write_mc_addr_list(netdev);
3430 if (count < 0)
3431 rctl |= E1000_RCTL_MPE;
3432 }
3433 e1000e_vlan_filter_enable(adapter);
3434 /* Write addresses to available RAR registers, if there is not
3435 * sufficient space to store all the addresses then enable
3436 * unicast promiscuous mode
3437 */
3438 count = e1000e_write_uc_addr_list(netdev);
3439 if (count < 0)
3440 rctl |= E1000_RCTL_UPE;
3441 }
3442
3443 ew32(RCTL, rctl);
3444
3445 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3446 e1000e_vlan_strip_enable(adapter);
3447 else
3448 e1000e_vlan_strip_disable(adapter);
3449}
3450
3451static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3452{
3453 struct e1000_hw *hw = &adapter->hw;
3454 u32 mrqc, rxcsum;
3455 u32 rss_key[10];
3456 int i;
3457
3458 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3459 for (i = 0; i < 10; i++)
3460 ew32(RSSRK(i), rss_key[i]);
3461
3462 /* Direct all traffic to queue 0 */
3463 for (i = 0; i < 32; i++)
3464 ew32(RETA(i), 0);
3465
3466 /* Disable raw packet checksumming so that RSS hash is placed in
3467 * descriptor on writeback.
3468 */
3469 rxcsum = er32(RXCSUM);
3470 rxcsum |= E1000_RXCSUM_PCSD;
3471
3472 ew32(RXCSUM, rxcsum);
3473
3474 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3475 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3476 E1000_MRQC_RSS_FIELD_IPV6 |
3477 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3478 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3479
3480 ew32(MRQC, mrqc);
3481}
3482
3483/**
3484 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3485 * @adapter: board private structure
3486 * @timinca: pointer to returned time increment attributes
3487 *
3488 * Get attributes for incrementing the System Time Register SYSTIML/H at
3489 * the default base frequency, and set the cyclecounter shift value.
3490 **/
3491s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
3492{
3493 struct e1000_hw *hw = &adapter->hw;
3494 u32 incvalue, incperiod, shift;
3495
3496 /* Make sure clock is enabled on I217/I218/I219 before checking
3497 * the frequency
3498 */
3499 if ((hw->mac.type >= e1000_pch_lpt) &&
3500 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3501 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3502 u32 fextnvm7 = er32(FEXTNVM7);
3503
3504 if (!(fextnvm7 & BIT(0))) {
3505 ew32(FEXTNVM7, fextnvm7 | BIT(0));
3506 e1e_flush();
3507 }
3508 }
3509
3510 switch (hw->mac.type) {
3511 case e1000_pch2lan:
3512 /* Stable 96MHz frequency */
3513 incperiod = INCPERIOD_96MHZ;
3514 incvalue = INCVALUE_96MHZ;
3515 shift = INCVALUE_SHIFT_96MHZ;
3516 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3517 break;
3518 case e1000_pch_lpt:
3519 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3520 /* Stable 96MHz frequency */
3521 incperiod = INCPERIOD_96MHZ;
3522 incvalue = INCVALUE_96MHZ;
3523 shift = INCVALUE_SHIFT_96MHZ;
3524 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3525 } else {
3526 /* Stable 25MHz frequency */
3527 incperiod = INCPERIOD_25MHZ;
3528 incvalue = INCVALUE_25MHZ;
3529 shift = INCVALUE_SHIFT_25MHZ;
3530 adapter->cc.shift = shift;
3531 }
3532 break;
3533 case e1000_pch_spt:
3534 /* Stable 24MHz frequency */
3535 incperiod = INCPERIOD_24MHZ;
3536 incvalue = INCVALUE_24MHZ;
3537 shift = INCVALUE_SHIFT_24MHZ;
3538 adapter->cc.shift = shift;
3539 break;
3540 case e1000_pch_cnp:
3541 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3542 /* Stable 24MHz frequency */
3543 incperiod = INCPERIOD_24MHZ;
3544 incvalue = INCVALUE_24MHZ;
3545 shift = INCVALUE_SHIFT_24MHZ;
3546 adapter->cc.shift = shift;
3547 } else {
3548 /* Stable 38400KHz frequency */
3549 incperiod = INCPERIOD_38400KHZ;
3550 incvalue = INCVALUE_38400KHZ;
3551 shift = INCVALUE_SHIFT_38400KHZ;
3552 adapter->cc.shift = shift;
3553 }
3554 break;
3555 case e1000_82574:
3556 case e1000_82583:
3557 /* Stable 25MHz frequency */
3558 incperiod = INCPERIOD_25MHZ;
3559 incvalue = INCVALUE_25MHZ;
3560 shift = INCVALUE_SHIFT_25MHZ;
3561 adapter->cc.shift = shift;
3562 break;
3563 default:
3564 return -EINVAL;
3565 }
3566
3567 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3568 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3569
3570 return 0;
3571}
3572
3573/**
3574 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3575 * @adapter: board private structure
3576 *
3577 * Outgoing time stamping can be enabled and disabled. Play nice and
3578 * disable it when requested, although it shouldn't cause any overhead
3579 * when no packet needs it. At most one packet in the queue may be
3580 * marked for time stamping, otherwise it would be impossible to tell
3581 * for sure to which packet the hardware time stamp belongs.
3582 *
3583 * Incoming time stamping has to be configured via the hardware filters.
3584 * Not all combinations are supported, in particular event type has to be
3585 * specified. Matching the kind of event packet is not supported, with the
3586 * exception of "all V2 events regardless of level 2 or 4".
3587 **/
3588static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3589 struct hwtstamp_config *config)
3590{
3591 struct e1000_hw *hw = &adapter->hw;
3592 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3593 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
3594 u32 rxmtrl = 0;
3595 u16 rxudp = 0;
3596 bool is_l4 = false;
3597 bool is_l2 = false;
3598 u32 regval;
3599
3600 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3601 return -EINVAL;
3602
3603 /* flags reserved for future extensions - must be zero */
3604 if (config->flags)
3605 return -EINVAL;
3606
3607 switch (config->tx_type) {
3608 case HWTSTAMP_TX_OFF:
3609 tsync_tx_ctl = 0;
3610 break;
3611 case HWTSTAMP_TX_ON:
3612 break;
3613 default:
3614 return -ERANGE;
3615 }
3616
3617 switch (config->rx_filter) {
3618 case HWTSTAMP_FILTER_NONE:
3619 tsync_rx_ctl = 0;
3620 break;
3621 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3622 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3623 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3624 is_l4 = true;
3625 break;
3626 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3627 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3628 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3629 is_l4 = true;
3630 break;
3631 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3632 /* Also time stamps V2 L2 Path Delay Request/Response */
3633 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3634 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3635 is_l2 = true;
3636 break;
3637 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3638 /* Also time stamps V2 L2 Path Delay Request/Response. */
3639 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3640 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3641 is_l2 = true;
3642 break;
3643 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3644 /* Hardware cannot filter just V2 L4 Sync messages;
3645 * fall-through to V2 (both L2 and L4) Sync.
3646 */
3647 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3648 /* Also time stamps V2 Path Delay Request/Response. */
3649 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3650 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3651 is_l2 = true;
3652 is_l4 = true;
3653 break;
3654 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3655 /* Hardware cannot filter just V2 L4 Delay Request messages;
3656 * fall-through to V2 (both L2 and L4) Delay Request.
3657 */
3658 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3659 /* Also time stamps V2 Path Delay Request/Response. */
3660 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3661 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3662 is_l2 = true;
3663 is_l4 = true;
3664 break;
3665 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3666 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3667 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3668 * fall-through to all V2 (both L2 and L4) Events.
3669 */
3670 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3671 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3672 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3673 is_l2 = true;
3674 is_l4 = true;
3675 break;
3676 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3677 /* For V1, the hardware can only filter Sync messages or
3678 * Delay Request messages but not both so fall-through to
3679 * time stamp all packets.
3680 */
3681 case HWTSTAMP_FILTER_NTP_ALL:
3682 case HWTSTAMP_FILTER_ALL:
3683 is_l2 = true;
3684 is_l4 = true;
3685 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3686 config->rx_filter = HWTSTAMP_FILTER_ALL;
3687 break;
3688 default:
3689 return -ERANGE;
3690 }
3691
3692 adapter->hwtstamp_config = *config;
3693
3694 /* enable/disable Tx h/w time stamping */
3695 regval = er32(TSYNCTXCTL);
3696 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3697 regval |= tsync_tx_ctl;
3698 ew32(TSYNCTXCTL, regval);
3699 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3700 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3701 e_err("Timesync Tx Control register not set as expected\n");
3702 return -EAGAIN;
3703 }
3704
3705 /* enable/disable Rx h/w time stamping */
3706 regval = er32(TSYNCRXCTL);
3707 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3708 regval |= tsync_rx_ctl;
3709 ew32(TSYNCRXCTL, regval);
3710 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3711 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3712 (regval & (E1000_TSYNCRXCTL_ENABLED |
3713 E1000_TSYNCRXCTL_TYPE_MASK))) {
3714 e_err("Timesync Rx Control register not set as expected\n");
3715 return -EAGAIN;
3716 }
3717
3718 /* L2: define ethertype filter for time stamped packets */
3719 if (is_l2)
3720 rxmtrl |= ETH_P_1588;
3721
3722 /* define which PTP packets get time stamped */
3723 ew32(RXMTRL, rxmtrl);
3724
3725 /* Filter by destination port */
3726 if (is_l4) {
3727 rxudp = PTP_EV_PORT;
3728 cpu_to_be16s(&rxudp);
3729 }
3730 ew32(RXUDP, rxudp);
3731
3732 e1e_flush();
3733
3734 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3735 er32(RXSTMPH);
3736 er32(TXSTMPH);
3737
3738 return 0;
3739}
3740
3741/**
3742 * e1000_configure - configure the hardware for Rx and Tx
3743 * @adapter: private board structure
3744 **/
3745static void e1000_configure(struct e1000_adapter *adapter)
3746{
3747 struct e1000_ring *rx_ring = adapter->rx_ring;
3748
3749 e1000e_set_rx_mode(adapter->netdev);
3750
3751 e1000_restore_vlan(adapter);
3752 e1000_init_manageability_pt(adapter);
3753
3754 e1000_configure_tx(adapter);
3755
3756 if (adapter->netdev->features & NETIF_F_RXHASH)
3757 e1000e_setup_rss_hash(adapter);
3758 e1000_setup_rctl(adapter);
3759 e1000_configure_rx(adapter);
3760 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
3761}
3762
3763/**
3764 * e1000e_power_up_phy - restore link in case the phy was powered down
3765 * @adapter: address of board private structure
3766 *
3767 * The phy may be powered down to save power and turn off link when the
3768 * driver is unloaded and wake on lan is not enabled (among others)
3769 * *** this routine MUST be followed by a call to e1000e_reset ***
3770 **/
3771void e1000e_power_up_phy(struct e1000_adapter *adapter)
3772{
3773 if (adapter->hw.phy.ops.power_up)
3774 adapter->hw.phy.ops.power_up(&adapter->hw);
3775
3776 adapter->hw.mac.ops.setup_link(&adapter->hw);
3777}
3778
3779/**
3780 * e1000_power_down_phy - Power down the PHY
3781 *
3782 * Power down the PHY so no link is implied when interface is down.
3783 * The PHY cannot be powered down if management or WoL is active.
3784 */
3785static void e1000_power_down_phy(struct e1000_adapter *adapter)
3786{
3787 if (adapter->hw.phy.ops.power_down)
3788 adapter->hw.phy.ops.power_down(&adapter->hw);
3789}
3790
3791/**
3792 * e1000_flush_tx_ring - remove all descriptors from the tx_ring
3793 *
3794 * We want to clear all pending descriptors from the TX ring.
3795 * zeroing happens when the HW reads the regs. We assign the ring itself as
3796 * the data of the next descriptor. We don't care about the data we are about
3797 * to reset the HW.
3798 */
3799static void e1000_flush_tx_ring(struct e1000_adapter *adapter)
3800{
3801 struct e1000_hw *hw = &adapter->hw;
3802 struct e1000_ring *tx_ring = adapter->tx_ring;
3803 struct e1000_tx_desc *tx_desc = NULL;
3804 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
3805 u16 size = 512;
3806
3807 tctl = er32(TCTL);
3808 ew32(TCTL, tctl | E1000_TCTL_EN);
3809 tdt = er32(TDT(0));
3810 BUG_ON(tdt != tx_ring->next_to_use);
3811 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use);
3812 tx_desc->buffer_addr = tx_ring->dma;
3813
3814 tx_desc->lower.data = cpu_to_le32(txd_lower | size);
3815 tx_desc->upper.data = 0;
3816 /* flush descriptors to memory before notifying the HW */
3817 wmb();
3818 tx_ring->next_to_use++;
3819 if (tx_ring->next_to_use == tx_ring->count)
3820 tx_ring->next_to_use = 0;
3821 ew32(TDT(0), tx_ring->next_to_use);
3822 usleep_range(200, 250);
3823}
3824
3825/**
3826 * e1000_flush_rx_ring - remove all descriptors from the rx_ring
3827 *
3828 * Mark all descriptors in the RX ring as consumed and disable the rx ring
3829 */
3830static void e1000_flush_rx_ring(struct e1000_adapter *adapter)
3831{
3832 u32 rctl, rxdctl;
3833 struct e1000_hw *hw = &adapter->hw;
3834
3835 rctl = er32(RCTL);
3836 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3837 e1e_flush();
3838 usleep_range(100, 150);
3839
3840 rxdctl = er32(RXDCTL(0));
3841 /* zero the lower 14 bits (prefetch and host thresholds) */
3842 rxdctl &= 0xffffc000;
3843
3844 /* update thresholds: prefetch threshold to 31, host threshold to 1
3845 * and make sure the granularity is "descriptors" and not "cache lines"
3846 */
3847 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC);
3848
3849 ew32(RXDCTL(0), rxdctl);
3850 /* momentarily enable the RX ring for the changes to take effect */
3851 ew32(RCTL, rctl | E1000_RCTL_EN);
3852 e1e_flush();
3853 usleep_range(100, 150);
3854 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3855}
3856
3857/**
3858 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings
3859 *
3860 * In i219, the descriptor rings must be emptied before resetting the HW
3861 * or before changing the device state to D3 during runtime (runtime PM).
3862 *
3863 * Failure to do this will cause the HW to enter a unit hang state which can
3864 * only be released by PCI reset on the device
3865 *
3866 */
3867
3868static void e1000_flush_desc_rings(struct e1000_adapter *adapter)
3869{
3870 u16 hang_state;
3871 u32 fext_nvm11, tdlen;
3872 struct e1000_hw *hw = &adapter->hw;
3873
3874 /* First, disable MULR fix in FEXTNVM11 */
3875 fext_nvm11 = er32(FEXTNVM11);
3876 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
3877 ew32(FEXTNVM11, fext_nvm11);
3878 /* do nothing if we're not in faulty state, or if the queue is empty */
3879 tdlen = er32(TDLEN(0));
3880 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3881 &hang_state);
3882 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
3883 return;
3884 e1000_flush_tx_ring(adapter);
3885 /* recheck, maybe the fault is caused by the rx ring */
3886 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3887 &hang_state);
3888 if (hang_state & FLUSH_DESC_REQUIRED)
3889 e1000_flush_rx_ring(adapter);
3890}
3891
3892/**
3893 * e1000e_systim_reset - reset the timesync registers after a hardware reset
3894 * @adapter: board private structure
3895 *
3896 * When the MAC is reset, all hardware bits for timesync will be reset to the
3897 * default values. This function will restore the settings last in place.
3898 * Since the clock SYSTIME registers are reset, we will simply restore the
3899 * cyclecounter to the kernel real clock time.
3900 **/
3901static void e1000e_systim_reset(struct e1000_adapter *adapter)
3902{
3903 struct ptp_clock_info *info = &adapter->ptp_clock_info;
3904 struct e1000_hw *hw = &adapter->hw;
3905 unsigned long flags;
3906 u32 timinca;
3907 s32 ret_val;
3908
3909 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3910 return;
3911
3912 if (info->adjfreq) {
3913 /* restore the previous ptp frequency delta */
3914 ret_val = info->adjfreq(info, adapter->ptp_delta);
3915 } else {
3916 /* set the default base frequency if no adjustment possible */
3917 ret_val = e1000e_get_base_timinca(adapter, &timinca);
3918 if (!ret_val)
3919 ew32(TIMINCA, timinca);
3920 }
3921
3922 if (ret_val) {
3923 dev_warn(&adapter->pdev->dev,
3924 "Failed to restore TIMINCA clock rate delta: %d\n",
3925 ret_val);
3926 return;
3927 }
3928
3929 /* reset the systim ns time counter */
3930 spin_lock_irqsave(&adapter->systim_lock, flags);
3931 timecounter_init(&adapter->tc, &adapter->cc,
3932 ktime_to_ns(ktime_get_real()));
3933 spin_unlock_irqrestore(&adapter->systim_lock, flags);
3934
3935 /* restore the previous hwtstamp configuration settings */
3936 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config);
3937}
3938
3939/**
3940 * e1000e_reset - bring the hardware into a known good state
3941 *
3942 * This function boots the hardware and enables some settings that
3943 * require a configuration cycle of the hardware - those cannot be
3944 * set/changed during runtime. After reset the device needs to be
3945 * properly configured for Rx, Tx etc.
3946 */
3947void e1000e_reset(struct e1000_adapter *adapter)
3948{
3949 struct e1000_mac_info *mac = &adapter->hw.mac;
3950 struct e1000_fc_info *fc = &adapter->hw.fc;
3951 struct e1000_hw *hw = &adapter->hw;
3952 u32 tx_space, min_tx_space, min_rx_space;
3953 u32 pba = adapter->pba;
3954 u16 hwm;
3955
3956 /* reset Packet Buffer Allocation to default */
3957 ew32(PBA, pba);
3958
3959 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) {
3960 /* To maintain wire speed transmits, the Tx FIFO should be
3961 * large enough to accommodate two full transmit packets,
3962 * rounded up to the next 1KB and expressed in KB. Likewise,
3963 * the Rx FIFO should be large enough to accommodate at least
3964 * one full receive packet and is similarly rounded up and
3965 * expressed in KB.
3966 */
3967 pba = er32(PBA);
3968 /* upper 16 bits has Tx packet buffer allocation size in KB */
3969 tx_space = pba >> 16;
3970 /* lower 16 bits has Rx packet buffer allocation size in KB */
3971 pba &= 0xffff;
3972 /* the Tx fifo also stores 16 bytes of information about the Tx
3973 * but don't include ethernet FCS because hardware appends it
3974 */
3975 min_tx_space = (adapter->max_frame_size +
3976 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
3977 min_tx_space = ALIGN(min_tx_space, 1024);
3978 min_tx_space >>= 10;
3979 /* software strips receive CRC, so leave room for it */
3980 min_rx_space = adapter->max_frame_size;
3981 min_rx_space = ALIGN(min_rx_space, 1024);
3982 min_rx_space >>= 10;
3983
3984 /* If current Tx allocation is less than the min Tx FIFO size,
3985 * and the min Tx FIFO size is less than the current Rx FIFO
3986 * allocation, take space away from current Rx allocation
3987 */
3988 if ((tx_space < min_tx_space) &&
3989 ((min_tx_space - tx_space) < pba)) {
3990 pba -= min_tx_space - tx_space;
3991
3992 /* if short on Rx space, Rx wins and must trump Tx
3993 * adjustment
3994 */
3995 if (pba < min_rx_space)
3996 pba = min_rx_space;
3997 }
3998
3999 ew32(PBA, pba);
4000 }
4001
4002 /* flow control settings
4003 *
4004 * The high water mark must be low enough to fit one full frame
4005 * (or the size used for early receive) above it in the Rx FIFO.
4006 * Set it to the lower of:
4007 * - 90% of the Rx FIFO size, and
4008 * - the full Rx FIFO size minus one full frame
4009 */
4010 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
4011 fc->pause_time = 0xFFFF;
4012 else
4013 fc->pause_time = E1000_FC_PAUSE_TIME;
4014 fc->send_xon = true;
4015 fc->current_mode = fc->requested_mode;
4016
4017 switch (hw->mac.type) {
4018 case e1000_ich9lan:
4019 case e1000_ich10lan:
4020 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4021 pba = 14;
4022 ew32(PBA, pba);
4023 fc->high_water = 0x2800;
4024 fc->low_water = fc->high_water - 8;
4025 break;
4026 }
4027 /* fall-through */
4028 default:
4029 hwm = min(((pba << 10) * 9 / 10),
4030 ((pba << 10) - adapter->max_frame_size));
4031
4032 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
4033 fc->low_water = fc->high_water - 8;
4034 break;
4035 case e1000_pchlan:
4036 /* Workaround PCH LOM adapter hangs with certain network
4037 * loads. If hangs persist, try disabling Tx flow control.
4038 */
4039 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4040 fc->high_water = 0x3500;
4041 fc->low_water = 0x1500;
4042 } else {
4043 fc->high_water = 0x5000;
4044 fc->low_water = 0x3000;
4045 }
4046 fc->refresh_time = 0x1000;
4047 break;
4048 case e1000_pch2lan:
4049 case e1000_pch_lpt:
4050 case e1000_pch_spt:
4051 case e1000_pch_cnp:
4052 fc->refresh_time = 0xFFFF;
4053 fc->pause_time = 0xFFFF;
4054
4055 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
4056 fc->high_water = 0x05C20;
4057 fc->low_water = 0x05048;
4058 break;
4059 }
4060
4061 pba = 14;
4062 ew32(PBA, pba);
4063 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
4064 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
4065 break;
4066 }
4067
4068 /* Alignment of Tx data is on an arbitrary byte boundary with the
4069 * maximum size per Tx descriptor limited only to the transmit
4070 * allocation of the packet buffer minus 96 bytes with an upper
4071 * limit of 24KB due to receive synchronization limitations.
4072 */
4073 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
4074 24 << 10);
4075
4076 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
4077 * fit in receive buffer.
4078 */
4079 if (adapter->itr_setting & 0x3) {
4080 if ((adapter->max_frame_size * 2) > (pba << 10)) {
4081 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
4082 dev_info(&adapter->pdev->dev,
4083 "Interrupt Throttle Rate off\n");
4084 adapter->flags2 |= FLAG2_DISABLE_AIM;
4085 e1000e_write_itr(adapter, 0);
4086 }
4087 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
4088 dev_info(&adapter->pdev->dev,
4089 "Interrupt Throttle Rate on\n");
4090 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
4091 adapter->itr = 20000;
4092 e1000e_write_itr(adapter, adapter->itr);
4093 }
4094 }
4095
4096 if (hw->mac.type >= e1000_pch_spt)
4097 e1000_flush_desc_rings(adapter);
4098 /* Allow time for pending master requests to run */
4099 mac->ops.reset_hw(hw);
4100
4101 /* For parts with AMT enabled, let the firmware know
4102 * that the network interface is in control
4103 */
4104 if (adapter->flags & FLAG_HAS_AMT)
4105 e1000e_get_hw_control(adapter);
4106
4107 ew32(WUC, 0);
4108
4109 if (mac->ops.init_hw(hw))
4110 e_err("Hardware Error\n");
4111
4112 e1000_update_mng_vlan(adapter);
4113
4114 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
4115 ew32(VET, ETH_P_8021Q);
4116
4117 e1000e_reset_adaptive(hw);
4118
4119 /* restore systim and hwtstamp settings */
4120 e1000e_systim_reset(adapter);
4121
4122 /* Set EEE advertisement as appropriate */
4123 if (adapter->flags2 & FLAG2_HAS_EEE) {
4124 s32 ret_val;
4125 u16 adv_addr;
4126
4127 switch (hw->phy.type) {
4128 case e1000_phy_82579:
4129 adv_addr = I82579_EEE_ADVERTISEMENT;
4130 break;
4131 case e1000_phy_i217:
4132 adv_addr = I217_EEE_ADVERTISEMENT;
4133 break;
4134 default:
4135 dev_err(&adapter->pdev->dev,
4136 "Invalid PHY type setting EEE advertisement\n");
4137 return;
4138 }
4139
4140 ret_val = hw->phy.ops.acquire(hw);
4141 if (ret_val) {
4142 dev_err(&adapter->pdev->dev,
4143 "EEE advertisement - unable to acquire PHY\n");
4144 return;
4145 }
4146
4147 e1000_write_emi_reg_locked(hw, adv_addr,
4148 hw->dev_spec.ich8lan.eee_disable ?
4149 0 : adapter->eee_advert);
4150
4151 hw->phy.ops.release(hw);
4152 }
4153
4154 if (!netif_running(adapter->netdev) &&
4155 !test_bit(__E1000_TESTING, &adapter->state))
4156 e1000_power_down_phy(adapter);
4157
4158 e1000_get_phy_info(hw);
4159
4160 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
4161 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
4162 u16 phy_data = 0;
4163 /* speed up time to link by disabling smart power down, ignore
4164 * the return value of this function because there is nothing
4165 * different we would do if it failed
4166 */
4167 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
4168 phy_data &= ~IGP02E1000_PM_SPD;
4169 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
4170 }
4171 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) {
4172 u32 reg;
4173
4174 /* Fextnvm7 @ 0xe4[2] = 1 */
4175 reg = er32(FEXTNVM7);
4176 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE;
4177 ew32(FEXTNVM7, reg);
4178 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */
4179 reg = er32(FEXTNVM9);
4180 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS |
4181 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4182 ew32(FEXTNVM9, reg);
4183 }
4184
4185}
4186
4187/**
4188 * e1000e_trigger_lsc - trigger an LSC interrupt
4189 * @adapter:
4190 *
4191 * Fire a link status change interrupt to start the watchdog.
4192 **/
4193static void e1000e_trigger_lsc(struct e1000_adapter *adapter)
4194{
4195 struct e1000_hw *hw = &adapter->hw;
4196
4197 if (adapter->msix_entries)
4198 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER);
4199 else
4200 ew32(ICS, E1000_ICS_LSC);
4201}
4202
4203void e1000e_up(struct e1000_adapter *adapter)
4204{
4205 /* hardware has been reset, we need to reload some things */
4206 e1000_configure(adapter);
4207
4208 clear_bit(__E1000_DOWN, &adapter->state);
4209
4210 if (adapter->msix_entries)
4211 e1000_configure_msix(adapter);
4212 e1000_irq_enable(adapter);
4213
4214 /* Tx queue started by watchdog timer when link is up */
4215
4216 e1000e_trigger_lsc(adapter);
4217}
4218
4219static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
4220{
4221 struct e1000_hw *hw = &adapter->hw;
4222
4223 if (!(adapter->flags2 & FLAG2_DMA_BURST))
4224 return;
4225
4226 /* flush pending descriptor writebacks to memory */
4227 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4228 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4229
4230 /* execute the writes immediately */
4231 e1e_flush();
4232
4233 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
4234 * write is successful
4235 */
4236 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4237 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4238
4239 /* execute the writes immediately */
4240 e1e_flush();
4241}
4242
4243static void e1000e_update_stats(struct e1000_adapter *adapter);
4244
4245/**
4246 * e1000e_down - quiesce the device and optionally reset the hardware
4247 * @adapter: board private structure
4248 * @reset: boolean flag to reset the hardware or not
4249 */
4250void e1000e_down(struct e1000_adapter *adapter, bool reset)
4251{
4252 struct net_device *netdev = adapter->netdev;
4253 struct e1000_hw *hw = &adapter->hw;
4254 u32 tctl, rctl;
4255
4256 /* signal that we're down so the interrupt handler does not
4257 * reschedule our watchdog timer
4258 */
4259 set_bit(__E1000_DOWN, &adapter->state);
4260
4261 netif_carrier_off(netdev);
4262
4263 /* disable receives in the hardware */
4264 rctl = er32(RCTL);
4265 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4266 ew32(RCTL, rctl & ~E1000_RCTL_EN);
4267 /* flush and sleep below */
4268
4269 netif_stop_queue(netdev);
4270
4271 /* disable transmits in the hardware */
4272 tctl = er32(TCTL);
4273 tctl &= ~E1000_TCTL_EN;
4274 ew32(TCTL, tctl);
4275
4276 /* flush both disables and wait for them to finish */
4277 e1e_flush();
4278 usleep_range(10000, 11000);
4279
4280 e1000_irq_disable(adapter);
4281
4282 napi_synchronize(&adapter->napi);
4283
4284 del_timer_sync(&adapter->phy_info_timer);
4285
4286 spin_lock(&adapter->stats64_lock);
4287 e1000e_update_stats(adapter);
4288 spin_unlock(&adapter->stats64_lock);
4289
4290 e1000e_flush_descriptors(adapter);
4291
4292 adapter->link_speed = 0;
4293 adapter->link_duplex = 0;
4294
4295 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4296 if ((hw->mac.type >= e1000_pch2lan) &&
4297 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4298 e1000_lv_jumbo_workaround_ich8lan(hw, false))
4299 e_dbg("failed to disable jumbo frame workaround mode\n");
4300
4301 if (!pci_channel_offline(adapter->pdev)) {
4302 if (reset)
4303 e1000e_reset(adapter);
4304 else if (hw->mac.type >= e1000_pch_spt)
4305 e1000_flush_desc_rings(adapter);
4306 }
4307 e1000_clean_tx_ring(adapter->tx_ring);
4308 e1000_clean_rx_ring(adapter->rx_ring);
4309}
4310
4311void e1000e_reinit_locked(struct e1000_adapter *adapter)
4312{
4313 might_sleep();
4314 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
4315 usleep_range(1000, 1100);
4316 e1000e_down(adapter, true);
4317 e1000e_up(adapter);
4318 clear_bit(__E1000_RESETTING, &adapter->state);
4319}
4320
4321/**
4322 * e1000e_sanitize_systim - sanitize raw cycle counter reads
4323 * @hw: pointer to the HW structure
4324 * @systim: PHC time value read, sanitized and returned
4325 * @sts: structure to hold system time before and after reading SYSTIML,
4326 * may be NULL
4327 *
4328 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L:
4329 * check to see that the time is incrementing at a reasonable
4330 * rate and is a multiple of incvalue.
4331 **/
4332static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim,
4333 struct ptp_system_timestamp *sts)
4334{
4335 u64 time_delta, rem, temp;
4336 u64 systim_next;
4337 u32 incvalue;
4338 int i;
4339
4340 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK;
4341 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) {
4342 /* latch SYSTIMH on read of SYSTIML */
4343 ptp_read_system_prets(sts);
4344 systim_next = (u64)er32(SYSTIML);
4345 ptp_read_system_postts(sts);
4346 systim_next |= (u64)er32(SYSTIMH) << 32;
4347
4348 time_delta = systim_next - systim;
4349 temp = time_delta;
4350 /* VMWare users have seen incvalue of zero, don't div / 0 */
4351 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0);
4352
4353 systim = systim_next;
4354
4355 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0))
4356 break;
4357 }
4358
4359 return systim;
4360}
4361
4362/**
4363 * e1000e_read_systim - read SYSTIM register
4364 * @adapter: board private structure
4365 * @sts: structure which will contain system time before and after reading
4366 * SYSTIML, may be NULL
4367 **/
4368u64 e1000e_read_systim(struct e1000_adapter *adapter,
4369 struct ptp_system_timestamp *sts)
4370{
4371 struct e1000_hw *hw = &adapter->hw;
4372 u32 systimel, systimel_2, systimeh;
4373 u64 systim;
4374 /* SYSTIMH latching upon SYSTIML read does not work well.
4375 * This means that if SYSTIML overflows after we read it but before
4376 * we read SYSTIMH, the value of SYSTIMH has been incremented and we
4377 * will experience a huge non linear increment in the systime value
4378 * to fix that we test for overflow and if true, we re-read systime.
4379 */
4380 ptp_read_system_prets(sts);
4381 systimel = er32(SYSTIML);
4382 ptp_read_system_postts(sts);
4383 systimeh = er32(SYSTIMH);
4384 /* Is systimel is so large that overflow is possible? */
4385 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) {
4386 ptp_read_system_prets(sts);
4387 systimel_2 = er32(SYSTIML);
4388 ptp_read_system_postts(sts);
4389 if (systimel > systimel_2) {
4390 /* There was an overflow, read again SYSTIMH, and use
4391 * systimel_2
4392 */
4393 systimeh = er32(SYSTIMH);
4394 systimel = systimel_2;
4395 }
4396 }
4397 systim = (u64)systimel;
4398 systim |= (u64)systimeh << 32;
4399
4400 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW)
4401 systim = e1000e_sanitize_systim(hw, systim, sts);
4402
4403 return systim;
4404}
4405
4406/**
4407 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4408 * @cc: cyclecounter structure
4409 **/
4410static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc)
4411{
4412 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4413 cc);
4414
4415 return e1000e_read_systim(adapter, NULL);
4416}
4417
4418/**
4419 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4420 * @adapter: board private structure to initialize
4421 *
4422 * e1000_sw_init initializes the Adapter private data structure.
4423 * Fields are initialized based on PCI device information and
4424 * OS network device settings (MTU size).
4425 **/
4426static int e1000_sw_init(struct e1000_adapter *adapter)
4427{
4428 struct net_device *netdev = adapter->netdev;
4429
4430 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
4431 adapter->rx_ps_bsize0 = 128;
4432 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4433 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4434 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4435 adapter->rx_ring_count = E1000_DEFAULT_RXD;
4436
4437 spin_lock_init(&adapter->stats64_lock);
4438
4439 e1000e_set_interrupt_capability(adapter);
4440
4441 if (e1000_alloc_queues(adapter))
4442 return -ENOMEM;
4443
4444 /* Setup hardware time stamping cyclecounter */
4445 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4446 adapter->cc.read = e1000e_cyclecounter_read;
4447 adapter->cc.mask = CYCLECOUNTER_MASK(64);
4448 adapter->cc.mult = 1;
4449 /* cc.shift set in e1000e_get_base_tininca() */
4450
4451 spin_lock_init(&adapter->systim_lock);
4452 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4453 }
4454
4455 /* Explicitly disable IRQ since the NIC can be in any state. */
4456 e1000_irq_disable(adapter);
4457
4458 set_bit(__E1000_DOWN, &adapter->state);
4459 return 0;
4460}
4461
4462/**
4463 * e1000_intr_msi_test - Interrupt Handler
4464 * @irq: interrupt number
4465 * @data: pointer to a network interface device structure
4466 **/
4467static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
4468{
4469 struct net_device *netdev = data;
4470 struct e1000_adapter *adapter = netdev_priv(netdev);
4471 struct e1000_hw *hw = &adapter->hw;
4472 u32 icr = er32(ICR);
4473
4474 e_dbg("icr is %08X\n", icr);
4475 if (icr & E1000_ICR_RXSEQ) {
4476 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
4477 /* Force memory writes to complete before acknowledging the
4478 * interrupt is handled.
4479 */
4480 wmb();
4481 }
4482
4483 return IRQ_HANDLED;
4484}
4485
4486/**
4487 * e1000_test_msi_interrupt - Returns 0 for successful test
4488 * @adapter: board private struct
4489 *
4490 * code flow taken from tg3.c
4491 **/
4492static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4493{
4494 struct net_device *netdev = adapter->netdev;
4495 struct e1000_hw *hw = &adapter->hw;
4496 int err;
4497
4498 /* poll_enable hasn't been called yet, so don't need disable */
4499 /* clear any pending events */
4500 er32(ICR);
4501
4502 /* free the real vector and request a test handler */
4503 e1000_free_irq(adapter);
4504 e1000e_reset_interrupt_capability(adapter);
4505
4506 /* Assume that the test fails, if it succeeds then the test
4507 * MSI irq handler will unset this flag
4508 */
4509 adapter->flags |= FLAG_MSI_TEST_FAILED;
4510
4511 err = pci_enable_msi(adapter->pdev);
4512 if (err)
4513 goto msi_test_failed;
4514
4515 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
4516 netdev->name, netdev);
4517 if (err) {
4518 pci_disable_msi(adapter->pdev);
4519 goto msi_test_failed;
4520 }
4521
4522 /* Force memory writes to complete before enabling and firing an
4523 * interrupt.
4524 */
4525 wmb();
4526
4527 e1000_irq_enable(adapter);
4528
4529 /* fire an unusual interrupt on the test handler */
4530 ew32(ICS, E1000_ICS_RXSEQ);
4531 e1e_flush();
4532 msleep(100);
4533
4534 e1000_irq_disable(adapter);
4535
4536 rmb(); /* read flags after interrupt has been fired */
4537
4538 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4539 adapter->int_mode = E1000E_INT_MODE_LEGACY;
4540 e_info("MSI interrupt test failed, using legacy interrupt.\n");
4541 } else {
4542 e_dbg("MSI interrupt test succeeded!\n");
4543 }
4544
4545 free_irq(adapter->pdev->irq, netdev);
4546 pci_disable_msi(adapter->pdev);
4547
4548msi_test_failed:
4549 e1000e_set_interrupt_capability(adapter);
4550 return e1000_request_irq(adapter);
4551}
4552
4553/**
4554 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4555 * @adapter: board private struct
4556 *
4557 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4558 **/
4559static int e1000_test_msi(struct e1000_adapter *adapter)
4560{
4561 int err;
4562 u16 pci_cmd;
4563
4564 if (!(adapter->flags & FLAG_MSI_ENABLED))
4565 return 0;
4566
4567 /* disable SERR in case the MSI write causes a master abort */
4568 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4569 if (pci_cmd & PCI_COMMAND_SERR)
4570 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4571 pci_cmd & ~PCI_COMMAND_SERR);
4572
4573 err = e1000_test_msi_interrupt(adapter);
4574
4575 /* re-enable SERR */
4576 if (pci_cmd & PCI_COMMAND_SERR) {
4577 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4578 pci_cmd |= PCI_COMMAND_SERR;
4579 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4580 }
4581
4582 return err;
4583}
4584
4585/**
4586 * e1000e_open - Called when a network interface is made active
4587 * @netdev: network interface device structure
4588 *
4589 * Returns 0 on success, negative value on failure
4590 *
4591 * The open entry point is called when a network interface is made
4592 * active by the system (IFF_UP). At this point all resources needed
4593 * for transmit and receive operations are allocated, the interrupt
4594 * handler is registered with the OS, the watchdog timer is started,
4595 * and the stack is notified that the interface is ready.
4596 **/
4597int e1000e_open(struct net_device *netdev)
4598{
4599 struct e1000_adapter *adapter = netdev_priv(netdev);
4600 struct e1000_hw *hw = &adapter->hw;
4601 struct pci_dev *pdev = adapter->pdev;
4602 int err;
4603
4604 /* disallow open during test */
4605 if (test_bit(__E1000_TESTING, &adapter->state))
4606 return -EBUSY;
4607
4608 pm_runtime_get_sync(&pdev->dev);
4609
4610 netif_carrier_off(netdev);
4611 netif_stop_queue(netdev);
4612
4613 /* allocate transmit descriptors */
4614 err = e1000e_setup_tx_resources(adapter->tx_ring);
4615 if (err)
4616 goto err_setup_tx;
4617
4618 /* allocate receive descriptors */
4619 err = e1000e_setup_rx_resources(adapter->rx_ring);
4620 if (err)
4621 goto err_setup_rx;
4622
4623 /* If AMT is enabled, let the firmware know that the network
4624 * interface is now open and reset the part to a known state.
4625 */
4626 if (adapter->flags & FLAG_HAS_AMT) {
4627 e1000e_get_hw_control(adapter);
4628 e1000e_reset(adapter);
4629 }
4630
4631 e1000e_power_up_phy(adapter);
4632
4633 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4634 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4635 e1000_update_mng_vlan(adapter);
4636
4637 /* DMA latency requirement to workaround jumbo issue */
4638 pm_qos_add_request(&adapter->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
4639 PM_QOS_DEFAULT_VALUE);
4640
4641 /* before we allocate an interrupt, we must be ready to handle it.
4642 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4643 * as soon as we call pci_request_irq, so we have to setup our
4644 * clean_rx handler before we do so.
4645 */
4646 e1000_configure(adapter);
4647
4648 err = e1000_request_irq(adapter);
4649 if (err)
4650 goto err_req_irq;
4651
4652 /* Work around PCIe errata with MSI interrupts causing some chipsets to
4653 * ignore e1000e MSI messages, which means we need to test our MSI
4654 * interrupt now
4655 */
4656 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
4657 err = e1000_test_msi(adapter);
4658 if (err) {
4659 e_err("Interrupt allocation failed\n");
4660 goto err_req_irq;
4661 }
4662 }
4663
4664 /* From here on the code is the same as e1000e_up() */
4665 clear_bit(__E1000_DOWN, &adapter->state);
4666
4667 napi_enable(&adapter->napi);
4668
4669 e1000_irq_enable(adapter);
4670
4671 adapter->tx_hang_recheck = false;
4672
4673 hw->mac.get_link_status = true;
4674 pm_runtime_put(&pdev->dev);
4675
4676 e1000e_trigger_lsc(adapter);
4677
4678 return 0;
4679
4680err_req_irq:
4681 pm_qos_remove_request(&adapter->pm_qos_req);
4682 e1000e_release_hw_control(adapter);
4683 e1000_power_down_phy(adapter);
4684 e1000e_free_rx_resources(adapter->rx_ring);
4685err_setup_rx:
4686 e1000e_free_tx_resources(adapter->tx_ring);
4687err_setup_tx:
4688 e1000e_reset(adapter);
4689 pm_runtime_put_sync(&pdev->dev);
4690
4691 return err;
4692}
4693
4694/**
4695 * e1000e_close - Disables a network interface
4696 * @netdev: network interface device structure
4697 *
4698 * Returns 0, this is not allowed to fail
4699 *
4700 * The close entry point is called when an interface is de-activated
4701 * by the OS. The hardware is still under the drivers control, but
4702 * needs to be disabled. A global MAC reset is issued to stop the
4703 * hardware, and all transmit and receive resources are freed.
4704 **/
4705int e1000e_close(struct net_device *netdev)
4706{
4707 struct e1000_adapter *adapter = netdev_priv(netdev);
4708 struct pci_dev *pdev = adapter->pdev;
4709 int count = E1000_CHECK_RESET_COUNT;
4710
4711 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4712 usleep_range(10000, 11000);
4713
4714 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
4715
4716 pm_runtime_get_sync(&pdev->dev);
4717
4718 if (!test_bit(__E1000_DOWN, &adapter->state)) {
4719 e1000e_down(adapter, true);
4720 e1000_free_irq(adapter);
4721
4722 /* Link status message must follow this format */
4723 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
4724 }
4725
4726 napi_disable(&adapter->napi);
4727
4728 e1000e_free_tx_resources(adapter->tx_ring);
4729 e1000e_free_rx_resources(adapter->rx_ring);
4730
4731 /* kill manageability vlan ID if supported, but not if a vlan with
4732 * the same ID is registered on the host OS (let 8021q kill it)
4733 */
4734 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
4735 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4736 adapter->mng_vlan_id);
4737
4738 /* If AMT is enabled, let the firmware know that the network
4739 * interface is now closed
4740 */
4741 if ((adapter->flags & FLAG_HAS_AMT) &&
4742 !test_bit(__E1000_TESTING, &adapter->state))
4743 e1000e_release_hw_control(adapter);
4744
4745 pm_qos_remove_request(&adapter->pm_qos_req);
4746
4747 pm_runtime_put_sync(&pdev->dev);
4748
4749 return 0;
4750}
4751
4752/**
4753 * e1000_set_mac - Change the Ethernet Address of the NIC
4754 * @netdev: network interface device structure
4755 * @p: pointer to an address structure
4756 *
4757 * Returns 0 on success, negative on failure
4758 **/
4759static int e1000_set_mac(struct net_device *netdev, void *p)
4760{
4761 struct e1000_adapter *adapter = netdev_priv(netdev);
4762 struct e1000_hw *hw = &adapter->hw;
4763 struct sockaddr *addr = p;
4764
4765 if (!is_valid_ether_addr(addr->sa_data))
4766 return -EADDRNOTAVAIL;
4767
4768 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4769 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4770
4771 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4772
4773 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4774 /* activate the work around */
4775 e1000e_set_laa_state_82571(&adapter->hw, 1);
4776
4777 /* Hold a copy of the LAA in RAR[14] This is done so that
4778 * between the time RAR[0] gets clobbered and the time it
4779 * gets fixed (in e1000_watchdog), the actual LAA is in one
4780 * of the RARs and no incoming packets directed to this port
4781 * are dropped. Eventually the LAA will be in RAR[0] and
4782 * RAR[14]
4783 */
4784 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4785 adapter->hw.mac.rar_entry_count - 1);
4786 }
4787
4788 return 0;
4789}
4790
4791/**
4792 * e1000e_update_phy_task - work thread to update phy
4793 * @work: pointer to our work struct
4794 *
4795 * this worker thread exists because we must acquire a
4796 * semaphore to read the phy, which we could msleep while
4797 * waiting for it, and we can't msleep in a timer.
4798 **/
4799static void e1000e_update_phy_task(struct work_struct *work)
4800{
4801 struct e1000_adapter *adapter = container_of(work,
4802 struct e1000_adapter,
4803 update_phy_task);
4804 struct e1000_hw *hw = &adapter->hw;
4805
4806 if (test_bit(__E1000_DOWN, &adapter->state))
4807 return;
4808
4809 e1000_get_phy_info(hw);
4810
4811 /* Enable EEE on 82579 after link up */
4812 if (hw->phy.type >= e1000_phy_82579)
4813 e1000_set_eee_pchlan(hw);
4814}
4815
4816/**
4817 * e1000_update_phy_info - timre call-back to update PHY info
4818 * @data: pointer to adapter cast into an unsigned long
4819 *
4820 * Need to wait a few seconds after link up to get diagnostic information from
4821 * the phy
4822 **/
4823static void e1000_update_phy_info(struct timer_list *t)
4824{
4825 struct e1000_adapter *adapter = from_timer(adapter, t, phy_info_timer);
4826
4827 if (test_bit(__E1000_DOWN, &adapter->state))
4828 return;
4829
4830 schedule_work(&adapter->update_phy_task);
4831}
4832
4833/**
4834 * e1000e_update_phy_stats - Update the PHY statistics counters
4835 * @adapter: board private structure
4836 *
4837 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4838 **/
4839static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4840{
4841 struct e1000_hw *hw = &adapter->hw;
4842 s32 ret_val;
4843 u16 phy_data;
4844
4845 ret_val = hw->phy.ops.acquire(hw);
4846 if (ret_val)
4847 return;
4848
4849 /* A page set is expensive so check if already on desired page.
4850 * If not, set to the page with the PHY status registers.
4851 */
4852 hw->phy.addr = 1;
4853 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4854 &phy_data);
4855 if (ret_val)
4856 goto release;
4857 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4858 ret_val = hw->phy.ops.set_page(hw,
4859 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4860 if (ret_val)
4861 goto release;
4862 }
4863
4864 /* Single Collision Count */
4865 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4866 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4867 if (!ret_val)
4868 adapter->stats.scc += phy_data;
4869
4870 /* Excessive Collision Count */
4871 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4872 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4873 if (!ret_val)
4874 adapter->stats.ecol += phy_data;
4875
4876 /* Multiple Collision Count */
4877 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4878 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4879 if (!ret_val)
4880 adapter->stats.mcc += phy_data;
4881
4882 /* Late Collision Count */
4883 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4884 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4885 if (!ret_val)
4886 adapter->stats.latecol += phy_data;
4887
4888 /* Collision Count - also used for adaptive IFS */
4889 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4890 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4891 if (!ret_val)
4892 hw->mac.collision_delta = phy_data;
4893
4894 /* Defer Count */
4895 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4896 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4897 if (!ret_val)
4898 adapter->stats.dc += phy_data;
4899
4900 /* Transmit with no CRS */
4901 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4902 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4903 if (!ret_val)
4904 adapter->stats.tncrs += phy_data;
4905
4906release:
4907 hw->phy.ops.release(hw);
4908}
4909
4910/**
4911 * e1000e_update_stats - Update the board statistics counters
4912 * @adapter: board private structure
4913 **/
4914static void e1000e_update_stats(struct e1000_adapter *adapter)
4915{
4916 struct net_device *netdev = adapter->netdev;
4917 struct e1000_hw *hw = &adapter->hw;
4918 struct pci_dev *pdev = adapter->pdev;
4919
4920 /* Prevent stats update while adapter is being reset, or if the pci
4921 * connection is down.
4922 */
4923 if (adapter->link_speed == 0)
4924 return;
4925 if (pci_channel_offline(pdev))
4926 return;
4927
4928 adapter->stats.crcerrs += er32(CRCERRS);
4929 adapter->stats.gprc += er32(GPRC);
4930 adapter->stats.gorc += er32(GORCL);
4931 er32(GORCH); /* Clear gorc */
4932 adapter->stats.bprc += er32(BPRC);
4933 adapter->stats.mprc += er32(MPRC);
4934 adapter->stats.roc += er32(ROC);
4935
4936 adapter->stats.mpc += er32(MPC);
4937
4938 /* Half-duplex statistics */
4939 if (adapter->link_duplex == HALF_DUPLEX) {
4940 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4941 e1000e_update_phy_stats(adapter);
4942 } else {
4943 adapter->stats.scc += er32(SCC);
4944 adapter->stats.ecol += er32(ECOL);
4945 adapter->stats.mcc += er32(MCC);
4946 adapter->stats.latecol += er32(LATECOL);
4947 adapter->stats.dc += er32(DC);
4948
4949 hw->mac.collision_delta = er32(COLC);
4950
4951 if ((hw->mac.type != e1000_82574) &&
4952 (hw->mac.type != e1000_82583))
4953 adapter->stats.tncrs += er32(TNCRS);
4954 }
4955 adapter->stats.colc += hw->mac.collision_delta;
4956 }
4957
4958 adapter->stats.xonrxc += er32(XONRXC);
4959 adapter->stats.xontxc += er32(XONTXC);
4960 adapter->stats.xoffrxc += er32(XOFFRXC);
4961 adapter->stats.xofftxc += er32(XOFFTXC);
4962 adapter->stats.gptc += er32(GPTC);
4963 adapter->stats.gotc += er32(GOTCL);
4964 er32(GOTCH); /* Clear gotc */
4965 adapter->stats.rnbc += er32(RNBC);
4966 adapter->stats.ruc += er32(RUC);
4967
4968 adapter->stats.mptc += er32(MPTC);
4969 adapter->stats.bptc += er32(BPTC);
4970
4971 /* used for adaptive IFS */
4972
4973 hw->mac.tx_packet_delta = er32(TPT);
4974 adapter->stats.tpt += hw->mac.tx_packet_delta;
4975
4976 adapter->stats.algnerrc += er32(ALGNERRC);
4977 adapter->stats.rxerrc += er32(RXERRC);
4978 adapter->stats.cexterr += er32(CEXTERR);
4979 adapter->stats.tsctc += er32(TSCTC);
4980 adapter->stats.tsctfc += er32(TSCTFC);
4981
4982 /* Fill out the OS statistics structure */
4983 netdev->stats.multicast = adapter->stats.mprc;
4984 netdev->stats.collisions = adapter->stats.colc;
4985
4986 /* Rx Errors */
4987
4988 /* RLEC on some newer hardware can be incorrect so build
4989 * our own version based on RUC and ROC
4990 */
4991 netdev->stats.rx_errors = adapter->stats.rxerrc +
4992 adapter->stats.crcerrs + adapter->stats.algnerrc +
4993 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
4994 netdev->stats.rx_length_errors = adapter->stats.ruc +
4995 adapter->stats.roc;
4996 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4997 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4998 netdev->stats.rx_missed_errors = adapter->stats.mpc;
4999
5000 /* Tx Errors */
5001 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
5002 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
5003 netdev->stats.tx_window_errors = adapter->stats.latecol;
5004 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
5005
5006 /* Tx Dropped needs to be maintained elsewhere */
5007
5008 /* Management Stats */
5009 adapter->stats.mgptc += er32(MGTPTC);
5010 adapter->stats.mgprc += er32(MGTPRC);
5011 adapter->stats.mgpdc += er32(MGTPDC);
5012
5013 /* Correctable ECC Errors */
5014 if (hw->mac.type >= e1000_pch_lpt) {
5015 u32 pbeccsts = er32(PBECCSTS);
5016
5017 adapter->corr_errors +=
5018 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
5019 adapter->uncorr_errors +=
5020 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
5021 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
5022 }
5023}
5024
5025/**
5026 * e1000_phy_read_status - Update the PHY register status snapshot
5027 * @adapter: board private structure
5028 **/
5029static void e1000_phy_read_status(struct e1000_adapter *adapter)
5030{
5031 struct e1000_hw *hw = &adapter->hw;
5032 struct e1000_phy_regs *phy = &adapter->phy_regs;
5033
5034 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
5035 (er32(STATUS) & E1000_STATUS_LU) &&
5036 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
5037 int ret_val;
5038
5039 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
5040 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
5041 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
5042 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
5043 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
5044 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
5045 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
5046 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
5047 if (ret_val)
5048 e_warn("Error reading PHY register\n");
5049 } else {
5050 /* Do not read PHY registers if link is not up
5051 * Set values to typical power-on defaults
5052 */
5053 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
5054 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
5055 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
5056 BMSR_ERCAP);
5057 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
5058 ADVERTISE_ALL | ADVERTISE_CSMA);
5059 phy->lpa = 0;
5060 phy->expansion = EXPANSION_ENABLENPAGE;
5061 phy->ctrl1000 = ADVERTISE_1000FULL;
5062 phy->stat1000 = 0;
5063 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
5064 }
5065}
5066
5067static void e1000_print_link_info(struct e1000_adapter *adapter)
5068{
5069 struct e1000_hw *hw = &adapter->hw;
5070 u32 ctrl = er32(CTRL);
5071
5072 /* Link status message must follow this format for user tools */
5073 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5074 adapter->netdev->name, adapter->link_speed,
5075 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
5076 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
5077 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
5078 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
5079}
5080
5081static bool e1000e_has_link(struct e1000_adapter *adapter)
5082{
5083 struct e1000_hw *hw = &adapter->hw;
5084 bool link_active = false;
5085 s32 ret_val = 0;
5086
5087 /* get_link_status is set on LSC (link status) interrupt or
5088 * Rx sequence error interrupt. get_link_status will stay
5089 * true until the check_for_link establishes link
5090 * for copper adapters ONLY
5091 */
5092 switch (hw->phy.media_type) {
5093 case e1000_media_type_copper:
5094 if (hw->mac.get_link_status) {
5095 ret_val = hw->mac.ops.check_for_link(hw);
5096 link_active = !hw->mac.get_link_status;
5097 } else {
5098 link_active = true;
5099 }
5100 break;
5101 case e1000_media_type_fiber:
5102 ret_val = hw->mac.ops.check_for_link(hw);
5103 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
5104 break;
5105 case e1000_media_type_internal_serdes:
5106 ret_val = hw->mac.ops.check_for_link(hw);
5107 link_active = hw->mac.serdes_has_link;
5108 break;
5109 default:
5110 case e1000_media_type_unknown:
5111 break;
5112 }
5113
5114 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
5115 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
5116 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
5117 e_info("Gigabit has been disabled, downgrading speed\n");
5118 }
5119
5120 return link_active;
5121}
5122
5123static void e1000e_enable_receives(struct e1000_adapter *adapter)
5124{
5125 /* make sure the receive unit is started */
5126 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5127 (adapter->flags & FLAG_RESTART_NOW)) {
5128 struct e1000_hw *hw = &adapter->hw;
5129 u32 rctl = er32(RCTL);
5130
5131 ew32(RCTL, rctl | E1000_RCTL_EN);
5132 adapter->flags &= ~FLAG_RESTART_NOW;
5133 }
5134}
5135
5136static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
5137{
5138 struct e1000_hw *hw = &adapter->hw;
5139
5140 /* With 82574 controllers, PHY needs to be checked periodically
5141 * for hung state and reset, if two calls return true
5142 */
5143 if (e1000_check_phy_82574(hw))
5144 adapter->phy_hang_count++;
5145 else
5146 adapter->phy_hang_count = 0;
5147
5148 if (adapter->phy_hang_count > 1) {
5149 adapter->phy_hang_count = 0;
5150 e_dbg("PHY appears hung - resetting\n");
5151 schedule_work(&adapter->reset_task);
5152 }
5153}
5154
5155static void e1000_watchdog_task(struct work_struct *work)
5156{
5157 struct e1000_adapter *adapter = container_of(work,
5158 struct e1000_adapter,
5159 watchdog_task.work);
5160 struct net_device *netdev = adapter->netdev;
5161 struct e1000_mac_info *mac = &adapter->hw.mac;
5162 struct e1000_phy_info *phy = &adapter->hw.phy;
5163 struct e1000_ring *tx_ring = adapter->tx_ring;
5164 u32 dmoff_exit_timeout = 100, tries = 0;
5165 struct e1000_hw *hw = &adapter->hw;
5166 u32 link, tctl, pcim_state;
5167
5168 if (test_bit(__E1000_DOWN, &adapter->state))
5169 return;
5170
5171 link = e1000e_has_link(adapter);
5172 if ((netif_carrier_ok(netdev)) && link) {
5173 /* Cancel scheduled suspend requests. */
5174 pm_runtime_resume(netdev->dev.parent);
5175
5176 e1000e_enable_receives(adapter);
5177 goto link_up;
5178 }
5179
5180 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
5181 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
5182 e1000_update_mng_vlan(adapter);
5183
5184 if (link) {
5185 if (!netif_carrier_ok(netdev)) {
5186 bool txb2b = true;
5187
5188 /* Cancel scheduled suspend requests. */
5189 pm_runtime_resume(netdev->dev.parent);
5190
5191 /* Checking if MAC is in DMoff state*/
5192 pcim_state = er32(STATUS);
5193 while (pcim_state & E1000_STATUS_PCIM_STATE) {
5194 if (tries++ == dmoff_exit_timeout) {
5195 e_dbg("Error in exiting dmoff\n");
5196 break;
5197 }
5198 usleep_range(10000, 20000);
5199 pcim_state = er32(STATUS);
5200
5201 /* Checking if MAC exited DMoff state */
5202 if (!(pcim_state & E1000_STATUS_PCIM_STATE))
5203 e1000_phy_hw_reset(&adapter->hw);
5204 }
5205
5206 /* update snapshot of PHY registers on LSC */
5207 e1000_phy_read_status(adapter);
5208 mac->ops.get_link_up_info(&adapter->hw,
5209 &adapter->link_speed,
5210 &adapter->link_duplex);
5211 e1000_print_link_info(adapter);
5212
5213 /* check if SmartSpeed worked */
5214 e1000e_check_downshift(hw);
5215 if (phy->speed_downgraded)
5216 netdev_warn(netdev,
5217 "Link Speed was downgraded by SmartSpeed\n");
5218
5219 /* On supported PHYs, check for duplex mismatch only
5220 * if link has autonegotiated at 10/100 half
5221 */
5222 if ((hw->phy.type == e1000_phy_igp_3 ||
5223 hw->phy.type == e1000_phy_bm) &&
5224 hw->mac.autoneg &&
5225 (adapter->link_speed == SPEED_10 ||
5226 adapter->link_speed == SPEED_100) &&
5227 (adapter->link_duplex == HALF_DUPLEX)) {
5228 u16 autoneg_exp;
5229
5230 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
5231
5232 if (!(autoneg_exp & EXPANSION_NWAY))
5233 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
5234 }
5235
5236 /* adjust timeout factor according to speed/duplex */
5237 adapter->tx_timeout_factor = 1;
5238 switch (adapter->link_speed) {
5239 case SPEED_10:
5240 txb2b = false;
5241 adapter->tx_timeout_factor = 16;
5242 break;
5243 case SPEED_100:
5244 txb2b = false;
5245 adapter->tx_timeout_factor = 10;
5246 break;
5247 }
5248
5249 /* workaround: re-program speed mode bit after
5250 * link-up event
5251 */
5252 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
5253 !txb2b) {
5254 u32 tarc0;
5255
5256 tarc0 = er32(TARC(0));
5257 tarc0 &= ~SPEED_MODE_BIT;
5258 ew32(TARC(0), tarc0);
5259 }
5260
5261 /* disable TSO for pcie and 10/100 speeds, to avoid
5262 * some hardware issues
5263 */
5264 if (!(adapter->flags & FLAG_TSO_FORCE)) {
5265 switch (adapter->link_speed) {
5266 case SPEED_10:
5267 case SPEED_100:
5268 e_info("10/100 speed: disabling TSO\n");
5269 netdev->features &= ~NETIF_F_TSO;
5270 netdev->features &= ~NETIF_F_TSO6;
5271 break;
5272 case SPEED_1000:
5273 netdev->features |= NETIF_F_TSO;
5274 netdev->features |= NETIF_F_TSO6;
5275 break;
5276 default:
5277 /* oops */
5278 break;
5279 }
5280 }
5281
5282 /* enable transmits in the hardware, need to do this
5283 * after setting TARC(0)
5284 */
5285 tctl = er32(TCTL);
5286 tctl |= E1000_TCTL_EN;
5287 ew32(TCTL, tctl);
5288
5289 /* Perform any post-link-up configuration before
5290 * reporting link up.
5291 */
5292 if (phy->ops.cfg_on_link_up)
5293 phy->ops.cfg_on_link_up(hw);
5294
5295 netif_wake_queue(netdev);
5296 netif_carrier_on(netdev);
5297
5298 if (!test_bit(__E1000_DOWN, &adapter->state))
5299 mod_timer(&adapter->phy_info_timer,
5300 round_jiffies(jiffies + 2 * HZ));
5301 }
5302 } else {
5303 if (netif_carrier_ok(netdev)) {
5304 adapter->link_speed = 0;
5305 adapter->link_duplex = 0;
5306 /* Link status message must follow this format */
5307 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
5308 netif_carrier_off(netdev);
5309 netif_stop_queue(netdev);
5310 if (!test_bit(__E1000_DOWN, &adapter->state))
5311 mod_timer(&adapter->phy_info_timer,
5312 round_jiffies(jiffies + 2 * HZ));
5313
5314 /* 8000ES2LAN requires a Rx packet buffer work-around
5315 * on link down event; reset the controller to flush
5316 * the Rx packet buffer.
5317 */
5318 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
5319 adapter->flags |= FLAG_RESTART_NOW;
5320 else
5321 pm_schedule_suspend(netdev->dev.parent,
5322 LINK_TIMEOUT);
5323 }
5324 }
5325
5326link_up:
5327 spin_lock(&adapter->stats64_lock);
5328 e1000e_update_stats(adapter);
5329
5330 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
5331 adapter->tpt_old = adapter->stats.tpt;
5332 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
5333 adapter->colc_old = adapter->stats.colc;
5334
5335 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
5336 adapter->gorc_old = adapter->stats.gorc;
5337 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
5338 adapter->gotc_old = adapter->stats.gotc;
5339 spin_unlock(&adapter->stats64_lock);
5340
5341 /* If the link is lost the controller stops DMA, but
5342 * if there is queued Tx work it cannot be done. So
5343 * reset the controller to flush the Tx packet buffers.
5344 */
5345 if (!netif_carrier_ok(netdev) &&
5346 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
5347 adapter->flags |= FLAG_RESTART_NOW;
5348
5349 /* If reset is necessary, do it outside of interrupt context. */
5350 if (adapter->flags & FLAG_RESTART_NOW) {
5351 schedule_work(&adapter->reset_task);
5352 /* return immediately since reset is imminent */
5353 return;
5354 }
5355
5356 e1000e_update_adaptive(&adapter->hw);
5357
5358 /* Simple mode for Interrupt Throttle Rate (ITR) */
5359 if (adapter->itr_setting == 4) {
5360 /* Symmetric Tx/Rx gets a reduced ITR=2000;
5361 * Total asymmetrical Tx or Rx gets ITR=8000;
5362 * everyone else is between 2000-8000.
5363 */
5364 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5365 u32 dif = (adapter->gotc > adapter->gorc ?
5366 adapter->gotc - adapter->gorc :
5367 adapter->gorc - adapter->gotc) / 10000;
5368 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5369
5370 e1000e_write_itr(adapter, itr);
5371 }
5372
5373 /* Cause software interrupt to ensure Rx ring is cleaned */
5374 if (adapter->msix_entries)
5375 ew32(ICS, adapter->rx_ring->ims_val);
5376 else
5377 ew32(ICS, E1000_ICS_RXDMT0);
5378
5379 /* flush pending descriptors to memory before detecting Tx hang */
5380 e1000e_flush_descriptors(adapter);
5381
5382 /* Force detection of hung controller every watchdog period */
5383 adapter->detect_tx_hung = true;
5384
5385 /* With 82571 controllers, LAA may be overwritten due to controller
5386 * reset from the other port. Set the appropriate LAA in RAR[0]
5387 */
5388 if (e1000e_get_laa_state_82571(hw))
5389 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
5390
5391 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5392 e1000e_check_82574_phy_workaround(adapter);
5393
5394 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5395 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5396 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5397 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5398 er32(RXSTMPH);
5399 adapter->rx_hwtstamp_cleared++;
5400 } else {
5401 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5402 }
5403 }
5404
5405 /* Reset the timer */
5406 if (!test_bit(__E1000_DOWN, &adapter->state))
5407 queue_delayed_work(adapter->e1000_workqueue,
5408 &adapter->watchdog_task,
5409 round_jiffies(2 * HZ));
5410}
5411
5412#define E1000_TX_FLAGS_CSUM 0x00000001
5413#define E1000_TX_FLAGS_VLAN 0x00000002
5414#define E1000_TX_FLAGS_TSO 0x00000004
5415#define E1000_TX_FLAGS_IPV4 0x00000008
5416#define E1000_TX_FLAGS_NO_FCS 0x00000010
5417#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5418#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5419#define E1000_TX_FLAGS_VLAN_SHIFT 16
5420
5421static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb,
5422 __be16 protocol)
5423{
5424 struct e1000_context_desc *context_desc;
5425 struct e1000_buffer *buffer_info;
5426 unsigned int i;
5427 u32 cmd_length = 0;
5428 u16 ipcse = 0, mss;
5429 u8 ipcss, ipcso, tucss, tucso, hdr_len;
5430 int err;
5431
5432 if (!skb_is_gso(skb))
5433 return 0;
5434
5435 err = skb_cow_head(skb, 0);
5436 if (err < 0)
5437 return err;
5438
5439 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5440 mss = skb_shinfo(skb)->gso_size;
5441 if (protocol == htons(ETH_P_IP)) {
5442 struct iphdr *iph = ip_hdr(skb);
5443 iph->tot_len = 0;
5444 iph->check = 0;
5445 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
5446 0, IPPROTO_TCP, 0);
5447 cmd_length = E1000_TXD_CMD_IP;
5448 ipcse = skb_transport_offset(skb) - 1;
5449 } else if (skb_is_gso_v6(skb)) {
5450 ipv6_hdr(skb)->payload_len = 0;
5451 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5452 &ipv6_hdr(skb)->daddr,
5453 0, IPPROTO_TCP, 0);
5454 ipcse = 0;
5455 }
5456 ipcss = skb_network_offset(skb);
5457 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5458 tucss = skb_transport_offset(skb);
5459 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
5460
5461 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
5462 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
5463
5464 i = tx_ring->next_to_use;
5465 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5466 buffer_info = &tx_ring->buffer_info[i];
5467
5468 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5469 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5470 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
5471 context_desc->upper_setup.tcp_fields.tucss = tucss;
5472 context_desc->upper_setup.tcp_fields.tucso = tucso;
5473 context_desc->upper_setup.tcp_fields.tucse = 0;
5474 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
5475 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5476 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5477
5478 buffer_info->time_stamp = jiffies;
5479 buffer_info->next_to_watch = i;
5480
5481 i++;
5482 if (i == tx_ring->count)
5483 i = 0;
5484 tx_ring->next_to_use = i;
5485
5486 return 1;
5487}
5488
5489static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb,
5490 __be16 protocol)
5491{
5492 struct e1000_adapter *adapter = tx_ring->adapter;
5493 struct e1000_context_desc *context_desc;
5494 struct e1000_buffer *buffer_info;
5495 unsigned int i;
5496 u8 css;
5497 u32 cmd_len = E1000_TXD_CMD_DEXT;
5498
5499 if (skb->ip_summed != CHECKSUM_PARTIAL)
5500 return false;
5501
5502 switch (protocol) {
5503 case cpu_to_be16(ETH_P_IP):
5504 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5505 cmd_len |= E1000_TXD_CMD_TCP;
5506 break;
5507 case cpu_to_be16(ETH_P_IPV6):
5508 /* XXX not handling all IPV6 headers */
5509 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5510 cmd_len |= E1000_TXD_CMD_TCP;
5511 break;
5512 default:
5513 if (unlikely(net_ratelimit()))
5514 e_warn("checksum_partial proto=%x!\n",
5515 be16_to_cpu(protocol));
5516 break;
5517 }
5518
5519 css = skb_checksum_start_offset(skb);
5520
5521 i = tx_ring->next_to_use;
5522 buffer_info = &tx_ring->buffer_info[i];
5523 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5524
5525 context_desc->lower_setup.ip_config = 0;
5526 context_desc->upper_setup.tcp_fields.tucss = css;
5527 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
5528 context_desc->upper_setup.tcp_fields.tucse = 0;
5529 context_desc->tcp_seg_setup.data = 0;
5530 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5531
5532 buffer_info->time_stamp = jiffies;
5533 buffer_info->next_to_watch = i;
5534
5535 i++;
5536 if (i == tx_ring->count)
5537 i = 0;
5538 tx_ring->next_to_use = i;
5539
5540 return true;
5541}
5542
5543static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5544 unsigned int first, unsigned int max_per_txd,
5545 unsigned int nr_frags)
5546{
5547 struct e1000_adapter *adapter = tx_ring->adapter;
5548 struct pci_dev *pdev = adapter->pdev;
5549 struct e1000_buffer *buffer_info;
5550 unsigned int len = skb_headlen(skb);
5551 unsigned int offset = 0, size, count = 0, i;
5552 unsigned int f, bytecount, segs;
5553
5554 i = tx_ring->next_to_use;
5555
5556 while (len) {
5557 buffer_info = &tx_ring->buffer_info[i];
5558 size = min(len, max_per_txd);
5559
5560 buffer_info->length = size;
5561 buffer_info->time_stamp = jiffies;
5562 buffer_info->next_to_watch = i;
5563 buffer_info->dma = dma_map_single(&pdev->dev,
5564 skb->data + offset,
5565 size, DMA_TO_DEVICE);
5566 buffer_info->mapped_as_page = false;
5567 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5568 goto dma_error;
5569
5570 len -= size;
5571 offset += size;
5572 count++;
5573
5574 if (len) {
5575 i++;
5576 if (i == tx_ring->count)
5577 i = 0;
5578 }
5579 }
5580
5581 for (f = 0; f < nr_frags; f++) {
5582 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
5583
5584 len = skb_frag_size(frag);
5585 offset = 0;
5586
5587 while (len) {
5588 i++;
5589 if (i == tx_ring->count)
5590 i = 0;
5591
5592 buffer_info = &tx_ring->buffer_info[i];
5593 size = min(len, max_per_txd);
5594
5595 buffer_info->length = size;
5596 buffer_info->time_stamp = jiffies;
5597 buffer_info->next_to_watch = i;
5598 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
5599 offset, size,
5600 DMA_TO_DEVICE);
5601 buffer_info->mapped_as_page = true;
5602 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5603 goto dma_error;
5604
5605 len -= size;
5606 offset += size;
5607 count++;
5608 }
5609 }
5610
5611 segs = skb_shinfo(skb)->gso_segs ? : 1;
5612 /* multiply data chunks by size of headers */
5613 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5614
5615 tx_ring->buffer_info[i].skb = skb;
5616 tx_ring->buffer_info[i].segs = segs;
5617 tx_ring->buffer_info[i].bytecount = bytecount;
5618 tx_ring->buffer_info[first].next_to_watch = i;
5619
5620 return count;
5621
5622dma_error:
5623 dev_err(&pdev->dev, "Tx DMA map failed\n");
5624 buffer_info->dma = 0;
5625 if (count)
5626 count--;
5627
5628 while (count--) {
5629 if (i == 0)
5630 i += tx_ring->count;
5631 i--;
5632 buffer_info = &tx_ring->buffer_info[i];
5633 e1000_put_txbuf(tx_ring, buffer_info, true);
5634 }
5635
5636 return 0;
5637}
5638
5639static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
5640{
5641 struct e1000_adapter *adapter = tx_ring->adapter;
5642 struct e1000_tx_desc *tx_desc = NULL;
5643 struct e1000_buffer *buffer_info;
5644 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5645 unsigned int i;
5646
5647 if (tx_flags & E1000_TX_FLAGS_TSO) {
5648 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
5649 E1000_TXD_CMD_TSE;
5650 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5651
5652 if (tx_flags & E1000_TX_FLAGS_IPV4)
5653 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5654 }
5655
5656 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5657 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5658 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5659 }
5660
5661 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5662 txd_lower |= E1000_TXD_CMD_VLE;
5663 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5664 }
5665
5666 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5667 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5668
5669 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5670 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5671 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5672 }
5673
5674 i = tx_ring->next_to_use;
5675
5676 do {
5677 buffer_info = &tx_ring->buffer_info[i];
5678 tx_desc = E1000_TX_DESC(*tx_ring, i);
5679 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
5680 tx_desc->lower.data = cpu_to_le32(txd_lower |
5681 buffer_info->length);
5682 tx_desc->upper.data = cpu_to_le32(txd_upper);
5683
5684 i++;
5685 if (i == tx_ring->count)
5686 i = 0;
5687 } while (--count > 0);
5688
5689 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5690
5691 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5692 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5693 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5694
5695 /* Force memory writes to complete before letting h/w
5696 * know there are new descriptors to fetch. (Only
5697 * applicable for weak-ordered memory model archs,
5698 * such as IA-64).
5699 */
5700 wmb();
5701
5702 tx_ring->next_to_use = i;
5703}
5704
5705#define MINIMUM_DHCP_PACKET_SIZE 282
5706static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5707 struct sk_buff *skb)
5708{
5709 struct e1000_hw *hw = &adapter->hw;
5710 u16 length, offset;
5711
5712 if (skb_vlan_tag_present(skb) &&
5713 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5714 (adapter->hw.mng_cookie.status &
5715 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5716 return 0;
5717
5718 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5719 return 0;
5720
5721 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
5722 return 0;
5723
5724 {
5725 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
5726 struct udphdr *udp;
5727
5728 if (ip->protocol != IPPROTO_UDP)
5729 return 0;
5730
5731 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5732 if (ntohs(udp->dest) != 67)
5733 return 0;
5734
5735 offset = (u8 *)udp + 8 - skb->data;
5736 length = skb->len - offset;
5737 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5738 }
5739
5740 return 0;
5741}
5742
5743static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5744{
5745 struct e1000_adapter *adapter = tx_ring->adapter;
5746
5747 netif_stop_queue(adapter->netdev);
5748 /* Herbert's original patch had:
5749 * smp_mb__after_netif_stop_queue();
5750 * but since that doesn't exist yet, just open code it.
5751 */
5752 smp_mb();
5753
5754 /* We need to check again in a case another CPU has just
5755 * made room available.
5756 */
5757 if (e1000_desc_unused(tx_ring) < size)
5758 return -EBUSY;
5759
5760 /* A reprieve! */
5761 netif_start_queue(adapter->netdev);
5762 ++adapter->restart_queue;
5763 return 0;
5764}
5765
5766static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5767{
5768 BUG_ON(size > tx_ring->count);
5769
5770 if (e1000_desc_unused(tx_ring) >= size)
5771 return 0;
5772 return __e1000_maybe_stop_tx(tx_ring, size);
5773}
5774
5775static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5776 struct net_device *netdev)
5777{
5778 struct e1000_adapter *adapter = netdev_priv(netdev);
5779 struct e1000_ring *tx_ring = adapter->tx_ring;
5780 unsigned int first;
5781 unsigned int tx_flags = 0;
5782 unsigned int len = skb_headlen(skb);
5783 unsigned int nr_frags;
5784 unsigned int mss;
5785 int count = 0;
5786 int tso;
5787 unsigned int f;
5788 __be16 protocol = vlan_get_protocol(skb);
5789
5790 if (test_bit(__E1000_DOWN, &adapter->state)) {
5791 dev_kfree_skb_any(skb);
5792 return NETDEV_TX_OK;
5793 }
5794
5795 if (skb->len <= 0) {
5796 dev_kfree_skb_any(skb);
5797 return NETDEV_TX_OK;
5798 }
5799
5800 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5801 * pad skb in order to meet this minimum size requirement
5802 */
5803 if (skb_put_padto(skb, 17))
5804 return NETDEV_TX_OK;
5805
5806 mss = skb_shinfo(skb)->gso_size;
5807 if (mss) {
5808 u8 hdr_len;
5809
5810 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5811 * points to just header, pull a few bytes of payload from
5812 * frags into skb->data
5813 */
5814 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5815 /* we do this workaround for ES2LAN, but it is un-necessary,
5816 * avoiding it could save a lot of cycles
5817 */
5818 if (skb->data_len && (hdr_len == len)) {
5819 unsigned int pull_size;
5820
5821 pull_size = min_t(unsigned int, 4, skb->data_len);
5822 if (!__pskb_pull_tail(skb, pull_size)) {
5823 e_err("__pskb_pull_tail failed.\n");
5824 dev_kfree_skb_any(skb);
5825 return NETDEV_TX_OK;
5826 }
5827 len = skb_headlen(skb);
5828 }
5829 }
5830
5831 /* reserve a descriptor for the offload context */
5832 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5833 count++;
5834 count++;
5835
5836 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
5837
5838 nr_frags = skb_shinfo(skb)->nr_frags;
5839 for (f = 0; f < nr_frags; f++)
5840 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5841 adapter->tx_fifo_limit);
5842
5843 if (adapter->hw.mac.tx_pkt_filtering)
5844 e1000_transfer_dhcp_info(adapter, skb);
5845
5846 /* need: count + 2 desc gap to keep tail from touching
5847 * head, otherwise try next time
5848 */
5849 if (e1000_maybe_stop_tx(tx_ring, count + 2))
5850 return NETDEV_TX_BUSY;
5851
5852 if (skb_vlan_tag_present(skb)) {
5853 tx_flags |= E1000_TX_FLAGS_VLAN;
5854 tx_flags |= (skb_vlan_tag_get(skb) <<
5855 E1000_TX_FLAGS_VLAN_SHIFT);
5856 }
5857
5858 first = tx_ring->next_to_use;
5859
5860 tso = e1000_tso(tx_ring, skb, protocol);
5861 if (tso < 0) {
5862 dev_kfree_skb_any(skb);
5863 return NETDEV_TX_OK;
5864 }
5865
5866 if (tso)
5867 tx_flags |= E1000_TX_FLAGS_TSO;
5868 else if (e1000_tx_csum(tx_ring, skb, protocol))
5869 tx_flags |= E1000_TX_FLAGS_CSUM;
5870
5871 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5872 * 82571 hardware supports TSO capabilities for IPv6 as well...
5873 * no longer assume, we must.
5874 */
5875 if (protocol == htons(ETH_P_IP))
5876 tx_flags |= E1000_TX_FLAGS_IPV4;
5877
5878 if (unlikely(skb->no_fcs))
5879 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5880
5881 /* if count is 0 then mapping error has occurred */
5882 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5883 nr_frags);
5884 if (count) {
5885 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5886 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) {
5887 if (!adapter->tx_hwtstamp_skb) {
5888 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5889 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5890 adapter->tx_hwtstamp_skb = skb_get(skb);
5891 adapter->tx_hwtstamp_start = jiffies;
5892 schedule_work(&adapter->tx_hwtstamp_work);
5893 } else {
5894 adapter->tx_hwtstamp_skipped++;
5895 }
5896 }
5897
5898 skb_tx_timestamp(skb);
5899
5900 netdev_sent_queue(netdev, skb->len);
5901 e1000_tx_queue(tx_ring, tx_flags, count);
5902 /* Make sure there is space in the ring for the next send. */
5903 e1000_maybe_stop_tx(tx_ring,
5904 (MAX_SKB_FRAGS *
5905 DIV_ROUND_UP(PAGE_SIZE,
5906 adapter->tx_fifo_limit) + 2));
5907
5908 if (!netdev_xmit_more() ||
5909 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) {
5910 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
5911 e1000e_update_tdt_wa(tx_ring,
5912 tx_ring->next_to_use);
5913 else
5914 writel(tx_ring->next_to_use, tx_ring->tail);
5915 }
5916 } else {
5917 dev_kfree_skb_any(skb);
5918 tx_ring->buffer_info[first].time_stamp = 0;
5919 tx_ring->next_to_use = first;
5920 }
5921
5922 return NETDEV_TX_OK;
5923}
5924
5925/**
5926 * e1000_tx_timeout - Respond to a Tx Hang
5927 * @netdev: network interface device structure
5928 **/
5929static void e1000_tx_timeout(struct net_device *netdev)
5930{
5931 struct e1000_adapter *adapter = netdev_priv(netdev);
5932
5933 /* Do the reset outside of interrupt context */
5934 adapter->tx_timeout_count++;
5935 schedule_work(&adapter->reset_task);
5936}
5937
5938static void e1000_reset_task(struct work_struct *work)
5939{
5940 struct e1000_adapter *adapter;
5941 adapter = container_of(work, struct e1000_adapter, reset_task);
5942
5943 /* don't run the task if already down */
5944 if (test_bit(__E1000_DOWN, &adapter->state))
5945 return;
5946
5947 if (!(adapter->flags & FLAG_RESTART_NOW)) {
5948 e1000e_dump(adapter);
5949 e_err("Reset adapter unexpectedly\n");
5950 }
5951 e1000e_reinit_locked(adapter);
5952}
5953
5954/**
5955 * e1000_get_stats64 - Get System Network Statistics
5956 * @netdev: network interface device structure
5957 * @stats: rtnl_link_stats64 pointer
5958 *
5959 * Returns the address of the device statistics structure.
5960 **/
5961void e1000e_get_stats64(struct net_device *netdev,
5962 struct rtnl_link_stats64 *stats)
5963{
5964 struct e1000_adapter *adapter = netdev_priv(netdev);
5965
5966 spin_lock(&adapter->stats64_lock);
5967 e1000e_update_stats(adapter);
5968 /* Fill out the OS statistics structure */
5969 stats->rx_bytes = adapter->stats.gorc;
5970 stats->rx_packets = adapter->stats.gprc;
5971 stats->tx_bytes = adapter->stats.gotc;
5972 stats->tx_packets = adapter->stats.gptc;
5973 stats->multicast = adapter->stats.mprc;
5974 stats->collisions = adapter->stats.colc;
5975
5976 /* Rx Errors */
5977
5978 /* RLEC on some newer hardware can be incorrect so build
5979 * our own version based on RUC and ROC
5980 */
5981 stats->rx_errors = adapter->stats.rxerrc +
5982 adapter->stats.crcerrs + adapter->stats.algnerrc +
5983 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5984 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
5985 stats->rx_crc_errors = adapter->stats.crcerrs;
5986 stats->rx_frame_errors = adapter->stats.algnerrc;
5987 stats->rx_missed_errors = adapter->stats.mpc;
5988
5989 /* Tx Errors */
5990 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
5991 stats->tx_aborted_errors = adapter->stats.ecol;
5992 stats->tx_window_errors = adapter->stats.latecol;
5993 stats->tx_carrier_errors = adapter->stats.tncrs;
5994
5995 /* Tx Dropped needs to be maintained elsewhere */
5996
5997 spin_unlock(&adapter->stats64_lock);
5998}
5999
6000/**
6001 * e1000_change_mtu - Change the Maximum Transfer Unit
6002 * @netdev: network interface device structure
6003 * @new_mtu: new value for maximum frame size
6004 *
6005 * Returns 0 on success, negative on failure
6006 **/
6007static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
6008{
6009 struct e1000_adapter *adapter = netdev_priv(netdev);
6010 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6011
6012 /* Jumbo frame support */
6013 if ((new_mtu > ETH_DATA_LEN) &&
6014 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
6015 e_err("Jumbo Frames not supported.\n");
6016 return -EINVAL;
6017 }
6018
6019 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6020 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
6021 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
6022 (new_mtu > ETH_DATA_LEN)) {
6023 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
6024 return -EINVAL;
6025 }
6026
6027 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
6028 usleep_range(1000, 1100);
6029 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
6030 adapter->max_frame_size = max_frame;
6031 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
6032 netdev->mtu = new_mtu;
6033
6034 pm_runtime_get_sync(netdev->dev.parent);
6035
6036 if (netif_running(netdev))
6037 e1000e_down(adapter, true);
6038
6039 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
6040 * means we reserve 2 more, this pushes us to allocate from the next
6041 * larger slab size.
6042 * i.e. RXBUFFER_2048 --> size-4096 slab
6043 * However with the new *_jumbo_rx* routines, jumbo receives will use
6044 * fragmented skbs
6045 */
6046
6047 if (max_frame <= 2048)
6048 adapter->rx_buffer_len = 2048;
6049 else
6050 adapter->rx_buffer_len = 4096;
6051
6052 /* adjust allocation if LPE protects us, and we aren't using SBP */
6053 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN))
6054 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
6055
6056 if (netif_running(netdev))
6057 e1000e_up(adapter);
6058 else
6059 e1000e_reset(adapter);
6060
6061 pm_runtime_put_sync(netdev->dev.parent);
6062
6063 clear_bit(__E1000_RESETTING, &adapter->state);
6064
6065 return 0;
6066}
6067
6068static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
6069 int cmd)
6070{
6071 struct e1000_adapter *adapter = netdev_priv(netdev);
6072 struct mii_ioctl_data *data = if_mii(ifr);
6073
6074 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6075 return -EOPNOTSUPP;
6076
6077 switch (cmd) {
6078 case SIOCGMIIPHY:
6079 data->phy_id = adapter->hw.phy.addr;
6080 break;
6081 case SIOCGMIIREG:
6082 e1000_phy_read_status(adapter);
6083
6084 switch (data->reg_num & 0x1F) {
6085 case MII_BMCR:
6086 data->val_out = adapter->phy_regs.bmcr;
6087 break;
6088 case MII_BMSR:
6089 data->val_out = adapter->phy_regs.bmsr;
6090 break;
6091 case MII_PHYSID1:
6092 data->val_out = (adapter->hw.phy.id >> 16);
6093 break;
6094 case MII_PHYSID2:
6095 data->val_out = (adapter->hw.phy.id & 0xFFFF);
6096 break;
6097 case MII_ADVERTISE:
6098 data->val_out = adapter->phy_regs.advertise;
6099 break;
6100 case MII_LPA:
6101 data->val_out = adapter->phy_regs.lpa;
6102 break;
6103 case MII_EXPANSION:
6104 data->val_out = adapter->phy_regs.expansion;
6105 break;
6106 case MII_CTRL1000:
6107 data->val_out = adapter->phy_regs.ctrl1000;
6108 break;
6109 case MII_STAT1000:
6110 data->val_out = adapter->phy_regs.stat1000;
6111 break;
6112 case MII_ESTATUS:
6113 data->val_out = adapter->phy_regs.estatus;
6114 break;
6115 default:
6116 return -EIO;
6117 }
6118 break;
6119 case SIOCSMIIREG:
6120 default:
6121 return -EOPNOTSUPP;
6122 }
6123 return 0;
6124}
6125
6126/**
6127 * e1000e_hwtstamp_ioctl - control hardware time stamping
6128 * @netdev: network interface device structure
6129 * @ifreq: interface request
6130 *
6131 * Outgoing time stamping can be enabled and disabled. Play nice and
6132 * disable it when requested, although it shouldn't cause any overhead
6133 * when no packet needs it. At most one packet in the queue may be
6134 * marked for time stamping, otherwise it would be impossible to tell
6135 * for sure to which packet the hardware time stamp belongs.
6136 *
6137 * Incoming time stamping has to be configured via the hardware filters.
6138 * Not all combinations are supported, in particular event type has to be
6139 * specified. Matching the kind of event packet is not supported, with the
6140 * exception of "all V2 events regardless of level 2 or 4".
6141 **/
6142static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
6143{
6144 struct e1000_adapter *adapter = netdev_priv(netdev);
6145 struct hwtstamp_config config;
6146 int ret_val;
6147
6148 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
6149 return -EFAULT;
6150
6151 ret_val = e1000e_config_hwtstamp(adapter, &config);
6152 if (ret_val)
6153 return ret_val;
6154
6155 switch (config.rx_filter) {
6156 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6157 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6158 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6159 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6160 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6161 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6162 /* With V2 type filters which specify a Sync or Delay Request,
6163 * Path Delay Request/Response messages are also time stamped
6164 * by hardware so notify the caller the requested packets plus
6165 * some others are time stamped.
6166 */
6167 config.rx_filter = HWTSTAMP_FILTER_SOME;
6168 break;
6169 default:
6170 break;
6171 }
6172
6173 return copy_to_user(ifr->ifr_data, &config,
6174 sizeof(config)) ? -EFAULT : 0;
6175}
6176
6177static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
6178{
6179 struct e1000_adapter *adapter = netdev_priv(netdev);
6180
6181 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config,
6182 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0;
6183}
6184
6185static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6186{
6187 switch (cmd) {
6188 case SIOCGMIIPHY:
6189 case SIOCGMIIREG:
6190 case SIOCSMIIREG:
6191 return e1000_mii_ioctl(netdev, ifr, cmd);
6192 case SIOCSHWTSTAMP:
6193 return e1000e_hwtstamp_set(netdev, ifr);
6194 case SIOCGHWTSTAMP:
6195 return e1000e_hwtstamp_get(netdev, ifr);
6196 default:
6197 return -EOPNOTSUPP;
6198 }
6199}
6200
6201static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
6202{
6203 struct e1000_hw *hw = &adapter->hw;
6204 u32 i, mac_reg, wuc;
6205 u16 phy_reg, wuc_enable;
6206 int retval;
6207
6208 /* copy MAC RARs to PHY RARs */
6209 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
6210
6211 retval = hw->phy.ops.acquire(hw);
6212 if (retval) {
6213 e_err("Could not acquire PHY\n");
6214 return retval;
6215 }
6216
6217 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
6218 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6219 if (retval)
6220 goto release;
6221
6222 /* copy MAC MTA to PHY MTA - only needed for pchlan */
6223 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
6224 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
6225 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
6226 (u16)(mac_reg & 0xFFFF));
6227 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
6228 (u16)((mac_reg >> 16) & 0xFFFF));
6229 }
6230
6231 /* configure PHY Rx Control register */
6232 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
6233 mac_reg = er32(RCTL);
6234 if (mac_reg & E1000_RCTL_UPE)
6235 phy_reg |= BM_RCTL_UPE;
6236 if (mac_reg & E1000_RCTL_MPE)
6237 phy_reg |= BM_RCTL_MPE;
6238 phy_reg &= ~(BM_RCTL_MO_MASK);
6239 if (mac_reg & E1000_RCTL_MO_3)
6240 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
6241 << BM_RCTL_MO_SHIFT);
6242 if (mac_reg & E1000_RCTL_BAM)
6243 phy_reg |= BM_RCTL_BAM;
6244 if (mac_reg & E1000_RCTL_PMCF)
6245 phy_reg |= BM_RCTL_PMCF;
6246 mac_reg = er32(CTRL);
6247 if (mac_reg & E1000_CTRL_RFCE)
6248 phy_reg |= BM_RCTL_RFCE;
6249 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
6250
6251 wuc = E1000_WUC_PME_EN;
6252 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
6253 wuc |= E1000_WUC_APME;
6254
6255 /* enable PHY wakeup in MAC register */
6256 ew32(WUFC, wufc);
6257 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
6258 E1000_WUC_PME_STATUS | wuc));
6259
6260 /* configure and enable PHY wakeup in PHY registers */
6261 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
6262 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
6263
6264 /* activate PHY wakeup */
6265 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
6266 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6267 if (retval)
6268 e_err("Could not set PHY Host Wakeup bit\n");
6269release:
6270 hw->phy.ops.release(hw);
6271
6272 return retval;
6273}
6274
6275static void e1000e_flush_lpic(struct pci_dev *pdev)
6276{
6277 struct net_device *netdev = pci_get_drvdata(pdev);
6278 struct e1000_adapter *adapter = netdev_priv(netdev);
6279 struct e1000_hw *hw = &adapter->hw;
6280 u32 ret_val;
6281
6282 pm_runtime_get_sync(netdev->dev.parent);
6283
6284 ret_val = hw->phy.ops.acquire(hw);
6285 if (ret_val)
6286 goto fl_out;
6287
6288 pr_info("EEE TX LPI TIMER: %08X\n",
6289 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT);
6290
6291 hw->phy.ops.release(hw);
6292
6293fl_out:
6294 pm_runtime_put_sync(netdev->dev.parent);
6295}
6296
6297static int e1000e_pm_freeze(struct device *dev)
6298{
6299 struct net_device *netdev = dev_get_drvdata(dev);
6300 struct e1000_adapter *adapter = netdev_priv(netdev);
6301
6302 netif_device_detach(netdev);
6303
6304 if (netif_running(netdev)) {
6305 int count = E1000_CHECK_RESET_COUNT;
6306
6307 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6308 usleep_range(10000, 11000);
6309
6310 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6311
6312 /* Quiesce the device without resetting the hardware */
6313 e1000e_down(adapter, false);
6314 e1000_free_irq(adapter);
6315 }
6316 e1000e_reset_interrupt_capability(adapter);
6317
6318 /* Allow time for pending master requests to run */
6319 e1000e_disable_pcie_master(&adapter->hw);
6320
6321 return 0;
6322}
6323
6324static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
6325{
6326 struct net_device *netdev = pci_get_drvdata(pdev);
6327 struct e1000_adapter *adapter = netdev_priv(netdev);
6328 struct e1000_hw *hw = &adapter->hw;
6329 u32 ctrl, ctrl_ext, rctl, status;
6330 /* Runtime suspend should only enable wakeup for link changes */
6331 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
6332 int retval = 0;
6333
6334 status = er32(STATUS);
6335 if (status & E1000_STATUS_LU)
6336 wufc &= ~E1000_WUFC_LNKC;
6337
6338 if (wufc) {
6339 e1000_setup_rctl(adapter);
6340 e1000e_set_rx_mode(netdev);
6341
6342 /* turn on all-multi mode if wake on multicast is enabled */
6343 if (wufc & E1000_WUFC_MC) {
6344 rctl = er32(RCTL);
6345 rctl |= E1000_RCTL_MPE;
6346 ew32(RCTL, rctl);
6347 }
6348
6349 ctrl = er32(CTRL);
6350 ctrl |= E1000_CTRL_ADVD3WUC;
6351 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
6352 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
6353 ew32(CTRL, ctrl);
6354
6355 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
6356 adapter->hw.phy.media_type ==
6357 e1000_media_type_internal_serdes) {
6358 /* keep the laser running in D3 */
6359 ctrl_ext = er32(CTRL_EXT);
6360 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
6361 ew32(CTRL_EXT, ctrl_ext);
6362 }
6363
6364 if (!runtime)
6365 e1000e_power_up_phy(adapter);
6366
6367 if (adapter->flags & FLAG_IS_ICH)
6368 e1000_suspend_workarounds_ich8lan(&adapter->hw);
6369
6370 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6371 /* enable wakeup by the PHY */
6372 retval = e1000_init_phy_wakeup(adapter, wufc);
6373 if (retval)
6374 return retval;
6375 } else {
6376 /* enable wakeup by the MAC */
6377 ew32(WUFC, wufc);
6378 ew32(WUC, E1000_WUC_PME_EN);
6379 }
6380 } else {
6381 ew32(WUC, 0);
6382 ew32(WUFC, 0);
6383
6384 e1000_power_down_phy(adapter);
6385 }
6386
6387 if (adapter->hw.phy.type == e1000_phy_igp_3) {
6388 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
6389 } else if (hw->mac.type >= e1000_pch_lpt) {
6390 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC)))
6391 /* ULP does not support wake from unicast, multicast
6392 * or broadcast.
6393 */
6394 retval = e1000_enable_ulp_lpt_lp(hw, !runtime);
6395
6396 if (retval)
6397 return retval;
6398 }
6399
6400 /* Ensure that the appropriate bits are set in LPI_CTRL
6401 * for EEE in Sx
6402 */
6403 if ((hw->phy.type >= e1000_phy_i217) &&
6404 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) {
6405 u16 lpi_ctrl = 0;
6406
6407 retval = hw->phy.ops.acquire(hw);
6408 if (!retval) {
6409 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL,
6410 &lpi_ctrl);
6411 if (!retval) {
6412 if (adapter->eee_advert &
6413 hw->dev_spec.ich8lan.eee_lp_ability &
6414 I82579_EEE_100_SUPPORTED)
6415 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
6416 if (adapter->eee_advert &
6417 hw->dev_spec.ich8lan.eee_lp_ability &
6418 I82579_EEE_1000_SUPPORTED)
6419 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
6420
6421 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL,
6422 lpi_ctrl);
6423 }
6424 }
6425 hw->phy.ops.release(hw);
6426 }
6427
6428 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6429 * would have already happened in close and is redundant.
6430 */
6431 e1000e_release_hw_control(adapter);
6432
6433 pci_clear_master(pdev);
6434
6435 /* The pci-e switch on some quad port adapters will report a
6436 * correctable error when the MAC transitions from D0 to D3. To
6437 * prevent this we need to mask off the correctable errors on the
6438 * downstream port of the pci-e switch.
6439 *
6440 * We don't have the associated upstream bridge while assigning
6441 * the PCI device into guest. For example, the KVM on power is
6442 * one of the cases.
6443 */
6444 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6445 struct pci_dev *us_dev = pdev->bus->self;
6446 u16 devctl;
6447
6448 if (!us_dev)
6449 return 0;
6450
6451 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6452 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6453 (devctl & ~PCI_EXP_DEVCTL_CERE));
6454
6455 pci_save_state(pdev);
6456 pci_prepare_to_sleep(pdev);
6457
6458 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
6459 }
6460
6461 return 0;
6462}
6463
6464/**
6465 * __e1000e_disable_aspm - Disable ASPM states
6466 * @pdev: pointer to PCI device struct
6467 * @state: bit-mask of ASPM states to disable
6468 * @locked: indication if this context holds pci_bus_sem locked.
6469 *
6470 * Some devices *must* have certain ASPM states disabled per hardware errata.
6471 **/
6472static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked)
6473{
6474 struct pci_dev *parent = pdev->bus->self;
6475 u16 aspm_dis_mask = 0;
6476 u16 pdev_aspmc, parent_aspmc;
6477
6478 switch (state) {
6479 case PCIE_LINK_STATE_L0S:
6480 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6481 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6482 /* fall-through - can't have L1 without L0s */
6483 case PCIE_LINK_STATE_L1:
6484 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6485 break;
6486 default:
6487 return;
6488 }
6489
6490 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6491 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6492
6493 if (parent) {
6494 pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6495 &parent_aspmc);
6496 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6497 }
6498
6499 /* Nothing to do if the ASPM states to be disabled already are */
6500 if (!(pdev_aspmc & aspm_dis_mask) &&
6501 (!parent || !(parent_aspmc & aspm_dis_mask)))
6502 return;
6503
6504 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6505 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6506 "L0s" : "",
6507 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6508 "L1" : "");
6509
6510#ifdef CONFIG_PCIEASPM
6511 if (locked)
6512 pci_disable_link_state_locked(pdev, state);
6513 else
6514 pci_disable_link_state(pdev, state);
6515
6516 /* Double-check ASPM control. If not disabled by the above, the
6517 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6518 * not enabled); override by writing PCI config space directly.
6519 */
6520 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6521 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6522
6523 if (!(aspm_dis_mask & pdev_aspmc))
6524 return;
6525#endif
6526
6527 /* Both device and parent should have the same ASPM setting.
6528 * Disable ASPM in downstream component first and then upstream.
6529 */
6530 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6531
6532 if (parent)
6533 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6534 aspm_dis_mask);
6535}
6536
6537/**
6538 * e1000e_disable_aspm - Disable ASPM states.
6539 * @pdev: pointer to PCI device struct
6540 * @state: bit-mask of ASPM states to disable
6541 *
6542 * This function acquires the pci_bus_sem!
6543 * Some devices *must* have certain ASPM states disabled per hardware errata.
6544 **/
6545static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6546{
6547 __e1000e_disable_aspm(pdev, state, 0);
6548}
6549
6550/**
6551 * e1000e_disable_aspm_locked Disable ASPM states.
6552 * @pdev: pointer to PCI device struct
6553 * @state: bit-mask of ASPM states to disable
6554 *
6555 * This function must be called with pci_bus_sem acquired!
6556 * Some devices *must* have certain ASPM states disabled per hardware errata.
6557 **/
6558static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state)
6559{
6560 __e1000e_disable_aspm(pdev, state, 1);
6561}
6562
6563#ifdef CONFIG_PM
6564static int __e1000_resume(struct pci_dev *pdev)
6565{
6566 struct net_device *netdev = pci_get_drvdata(pdev);
6567 struct e1000_adapter *adapter = netdev_priv(netdev);
6568 struct e1000_hw *hw = &adapter->hw;
6569 u16 aspm_disable_flag = 0;
6570
6571 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6572 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6573 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6574 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6575 if (aspm_disable_flag)
6576 e1000e_disable_aspm(pdev, aspm_disable_flag);
6577
6578 pci_set_master(pdev);
6579
6580 if (hw->mac.type >= e1000_pch2lan)
6581 e1000_resume_workarounds_pchlan(&adapter->hw);
6582
6583 e1000e_power_up_phy(adapter);
6584
6585 /* report the system wakeup cause from S3/S4 */
6586 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6587 u16 phy_data;
6588
6589 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6590 if (phy_data) {
6591 e_info("PHY Wakeup cause - %s\n",
6592 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6593 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6594 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6595 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6596 phy_data & E1000_WUS_LNKC ?
6597 "Link Status Change" : "other");
6598 }
6599 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6600 } else {
6601 u32 wus = er32(WUS);
6602
6603 if (wus) {
6604 e_info("MAC Wakeup cause - %s\n",
6605 wus & E1000_WUS_EX ? "Unicast Packet" :
6606 wus & E1000_WUS_MC ? "Multicast Packet" :
6607 wus & E1000_WUS_BC ? "Broadcast Packet" :
6608 wus & E1000_WUS_MAG ? "Magic Packet" :
6609 wus & E1000_WUS_LNKC ? "Link Status Change" :
6610 "other");
6611 }
6612 ew32(WUS, ~0);
6613 }
6614
6615 e1000e_reset(adapter);
6616
6617 e1000_init_manageability_pt(adapter);
6618
6619 /* If the controller has AMT, do not set DRV_LOAD until the interface
6620 * is up. For all other cases, let the f/w know that the h/w is now
6621 * under the control of the driver.
6622 */
6623 if (!(adapter->flags & FLAG_HAS_AMT))
6624 e1000e_get_hw_control(adapter);
6625
6626 return 0;
6627}
6628
6629#ifdef CONFIG_PM_SLEEP
6630static int e1000e_pm_thaw(struct device *dev)
6631{
6632 struct net_device *netdev = dev_get_drvdata(dev);
6633 struct e1000_adapter *adapter = netdev_priv(netdev);
6634
6635 e1000e_set_interrupt_capability(adapter);
6636 if (netif_running(netdev)) {
6637 u32 err = e1000_request_irq(adapter);
6638
6639 if (err)
6640 return err;
6641
6642 e1000e_up(adapter);
6643 }
6644
6645 netif_device_attach(netdev);
6646
6647 return 0;
6648}
6649
6650static int e1000e_pm_suspend(struct device *dev)
6651{
6652 struct pci_dev *pdev = to_pci_dev(dev);
6653 int rc;
6654
6655 e1000e_flush_lpic(pdev);
6656
6657 e1000e_pm_freeze(dev);
6658
6659 rc = __e1000_shutdown(pdev, false);
6660 if (rc)
6661 e1000e_pm_thaw(dev);
6662
6663 return rc;
6664}
6665
6666static int e1000e_pm_resume(struct device *dev)
6667{
6668 struct pci_dev *pdev = to_pci_dev(dev);
6669 int rc;
6670
6671 rc = __e1000_resume(pdev);
6672 if (rc)
6673 return rc;
6674
6675 return e1000e_pm_thaw(dev);
6676}
6677#endif /* CONFIG_PM_SLEEP */
6678
6679static int e1000e_pm_runtime_idle(struct device *dev)
6680{
6681 struct net_device *netdev = dev_get_drvdata(dev);
6682 struct e1000_adapter *adapter = netdev_priv(netdev);
6683 u16 eee_lp;
6684
6685 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability;
6686
6687 if (!e1000e_has_link(adapter)) {
6688 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp;
6689 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);
6690 }
6691
6692 return -EBUSY;
6693}
6694
6695static int e1000e_pm_runtime_resume(struct device *dev)
6696{
6697 struct pci_dev *pdev = to_pci_dev(dev);
6698 struct net_device *netdev = pci_get_drvdata(pdev);
6699 struct e1000_adapter *adapter = netdev_priv(netdev);
6700 int rc;
6701
6702 rc = __e1000_resume(pdev);
6703 if (rc)
6704 return rc;
6705
6706 if (netdev->flags & IFF_UP)
6707 e1000e_up(adapter);
6708
6709 return rc;
6710}
6711
6712static int e1000e_pm_runtime_suspend(struct device *dev)
6713{
6714 struct pci_dev *pdev = to_pci_dev(dev);
6715 struct net_device *netdev = pci_get_drvdata(pdev);
6716 struct e1000_adapter *adapter = netdev_priv(netdev);
6717
6718 if (netdev->flags & IFF_UP) {
6719 int count = E1000_CHECK_RESET_COUNT;
6720
6721 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6722 usleep_range(10000, 11000);
6723
6724 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6725
6726 /* Down the device without resetting the hardware */
6727 e1000e_down(adapter, false);
6728 }
6729
6730 if (__e1000_shutdown(pdev, true)) {
6731 e1000e_pm_runtime_resume(dev);
6732 return -EBUSY;
6733 }
6734
6735 return 0;
6736}
6737#endif /* CONFIG_PM */
6738
6739static void e1000_shutdown(struct pci_dev *pdev)
6740{
6741 e1000e_flush_lpic(pdev);
6742
6743 e1000e_pm_freeze(&pdev->dev);
6744
6745 __e1000_shutdown(pdev, false);
6746}
6747
6748#ifdef CONFIG_NET_POLL_CONTROLLER
6749
6750static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
6751{
6752 struct net_device *netdev = data;
6753 struct e1000_adapter *adapter = netdev_priv(netdev);
6754
6755 if (adapter->msix_entries) {
6756 int vector, msix_irq;
6757
6758 vector = 0;
6759 msix_irq = adapter->msix_entries[vector].vector;
6760 if (disable_hardirq(msix_irq))
6761 e1000_intr_msix_rx(msix_irq, netdev);
6762 enable_irq(msix_irq);
6763
6764 vector++;
6765 msix_irq = adapter->msix_entries[vector].vector;
6766 if (disable_hardirq(msix_irq))
6767 e1000_intr_msix_tx(msix_irq, netdev);
6768 enable_irq(msix_irq);
6769
6770 vector++;
6771 msix_irq = adapter->msix_entries[vector].vector;
6772 if (disable_hardirq(msix_irq))
6773 e1000_msix_other(msix_irq, netdev);
6774 enable_irq(msix_irq);
6775 }
6776
6777 return IRQ_HANDLED;
6778}
6779
6780/**
6781 * e1000_netpoll
6782 * @netdev: network interface device structure
6783 *
6784 * Polling 'interrupt' - used by things like netconsole to send skbs
6785 * without having to re-enable interrupts. It's not called while
6786 * the interrupt routine is executing.
6787 */
6788static void e1000_netpoll(struct net_device *netdev)
6789{
6790 struct e1000_adapter *adapter = netdev_priv(netdev);
6791
6792 switch (adapter->int_mode) {
6793 case E1000E_INT_MODE_MSIX:
6794 e1000_intr_msix(adapter->pdev->irq, netdev);
6795 break;
6796 case E1000E_INT_MODE_MSI:
6797 if (disable_hardirq(adapter->pdev->irq))
6798 e1000_intr_msi(adapter->pdev->irq, netdev);
6799 enable_irq(adapter->pdev->irq);
6800 break;
6801 default: /* E1000E_INT_MODE_LEGACY */
6802 if (disable_hardirq(adapter->pdev->irq))
6803 e1000_intr(adapter->pdev->irq, netdev);
6804 enable_irq(adapter->pdev->irq);
6805 break;
6806 }
6807}
6808#endif
6809
6810/**
6811 * e1000_io_error_detected - called when PCI error is detected
6812 * @pdev: Pointer to PCI device
6813 * @state: The current pci connection state
6814 *
6815 * This function is called after a PCI bus error affecting
6816 * this device has been detected.
6817 */
6818static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
6819 pci_channel_state_t state)
6820{
6821 struct net_device *netdev = pci_get_drvdata(pdev);
6822 struct e1000_adapter *adapter = netdev_priv(netdev);
6823
6824 netif_device_detach(netdev);
6825
6826 if (state == pci_channel_io_perm_failure)
6827 return PCI_ERS_RESULT_DISCONNECT;
6828
6829 if (netif_running(netdev))
6830 e1000e_down(adapter, true);
6831 pci_disable_device(pdev);
6832
6833 /* Request a slot slot reset. */
6834 return PCI_ERS_RESULT_NEED_RESET;
6835}
6836
6837/**
6838 * e1000_io_slot_reset - called after the pci bus has been reset.
6839 * @pdev: Pointer to PCI device
6840 *
6841 * Restart the card from scratch, as if from a cold-boot. Implementation
6842 * resembles the first-half of the e1000e_pm_resume routine.
6843 */
6844static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
6845{
6846 struct net_device *netdev = pci_get_drvdata(pdev);
6847 struct e1000_adapter *adapter = netdev_priv(netdev);
6848 struct e1000_hw *hw = &adapter->hw;
6849 u16 aspm_disable_flag = 0;
6850 int err;
6851 pci_ers_result_t result;
6852
6853 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6854 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6855 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6856 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6857 if (aspm_disable_flag)
6858 e1000e_disable_aspm_locked(pdev, aspm_disable_flag);
6859
6860 err = pci_enable_device_mem(pdev);
6861 if (err) {
6862 dev_err(&pdev->dev,
6863 "Cannot re-enable PCI device after reset.\n");
6864 result = PCI_ERS_RESULT_DISCONNECT;
6865 } else {
6866 pdev->state_saved = true;
6867 pci_restore_state(pdev);
6868 pci_set_master(pdev);
6869
6870 pci_enable_wake(pdev, PCI_D3hot, 0);
6871 pci_enable_wake(pdev, PCI_D3cold, 0);
6872
6873 e1000e_reset(adapter);
6874 ew32(WUS, ~0);
6875 result = PCI_ERS_RESULT_RECOVERED;
6876 }
6877
6878 return result;
6879}
6880
6881/**
6882 * e1000_io_resume - called when traffic can start flowing again.
6883 * @pdev: Pointer to PCI device
6884 *
6885 * This callback is called when the error recovery driver tells us that
6886 * its OK to resume normal operation. Implementation resembles the
6887 * second-half of the e1000e_pm_resume routine.
6888 */
6889static void e1000_io_resume(struct pci_dev *pdev)
6890{
6891 struct net_device *netdev = pci_get_drvdata(pdev);
6892 struct e1000_adapter *adapter = netdev_priv(netdev);
6893
6894 e1000_init_manageability_pt(adapter);
6895
6896 if (netif_running(netdev))
6897 e1000e_up(adapter);
6898
6899 netif_device_attach(netdev);
6900
6901 /* If the controller has AMT, do not set DRV_LOAD until the interface
6902 * is up. For all other cases, let the f/w know that the h/w is now
6903 * under the control of the driver.
6904 */
6905 if (!(adapter->flags & FLAG_HAS_AMT))
6906 e1000e_get_hw_control(adapter);
6907}
6908
6909static void e1000_print_device_info(struct e1000_adapter *adapter)
6910{
6911 struct e1000_hw *hw = &adapter->hw;
6912 struct net_device *netdev = adapter->netdev;
6913 u32 ret_val;
6914 u8 pba_str[E1000_PBANUM_LENGTH];
6915
6916 /* print bus type/speed/width info */
6917 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
6918 /* bus width */
6919 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
6920 "Width x1"),
6921 /* MAC address */
6922 netdev->dev_addr);
6923 e_info("Intel(R) PRO/%s Network Connection\n",
6924 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
6925 ret_val = e1000_read_pba_string_generic(hw, pba_str,
6926 E1000_PBANUM_LENGTH);
6927 if (ret_val)
6928 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
6929 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
6930 hw->mac.type, hw->phy.type, pba_str);
6931}
6932
6933static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6934{
6935 struct e1000_hw *hw = &adapter->hw;
6936 int ret_val;
6937 u16 buf = 0;
6938
6939 if (hw->mac.type != e1000_82573)
6940 return;
6941
6942 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
6943 le16_to_cpus(&buf);
6944 if (!ret_val && (!(buf & BIT(0)))) {
6945 /* Deep Smart Power Down (DSPD) */
6946 dev_warn(&adapter->pdev->dev,
6947 "Warning: detected DSPD enabled in EEPROM\n");
6948 }
6949}
6950
6951static netdev_features_t e1000_fix_features(struct net_device *netdev,
6952 netdev_features_t features)
6953{
6954 struct e1000_adapter *adapter = netdev_priv(netdev);
6955 struct e1000_hw *hw = &adapter->hw;
6956
6957 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6958 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN))
6959 features &= ~NETIF_F_RXFCS;
6960
6961 /* Since there is no support for separate Rx/Tx vlan accel
6962 * enable/disable make sure Tx flag is always in same state as Rx.
6963 */
6964 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6965 features |= NETIF_F_HW_VLAN_CTAG_TX;
6966 else
6967 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
6968
6969 return features;
6970}
6971
6972static int e1000_set_features(struct net_device *netdev,
6973 netdev_features_t features)
6974{
6975 struct e1000_adapter *adapter = netdev_priv(netdev);
6976 netdev_features_t changed = features ^ netdev->features;
6977
6978 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6979 adapter->flags |= FLAG_TSO_FORCE;
6980
6981 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
6982 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6983 NETIF_F_RXALL)))
6984 return 0;
6985
6986 if (changed & NETIF_F_RXFCS) {
6987 if (features & NETIF_F_RXFCS) {
6988 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6989 } else {
6990 /* We need to take it back to defaults, which might mean
6991 * stripping is still disabled at the adapter level.
6992 */
6993 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6994 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6995 else
6996 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6997 }
6998 }
6999
7000 netdev->features = features;
7001
7002 if (netif_running(netdev))
7003 e1000e_reinit_locked(adapter);
7004 else
7005 e1000e_reset(adapter);
7006
7007 return 1;
7008}
7009
7010static const struct net_device_ops e1000e_netdev_ops = {
7011 .ndo_open = e1000e_open,
7012 .ndo_stop = e1000e_close,
7013 .ndo_start_xmit = e1000_xmit_frame,
7014 .ndo_get_stats64 = e1000e_get_stats64,
7015 .ndo_set_rx_mode = e1000e_set_rx_mode,
7016 .ndo_set_mac_address = e1000_set_mac,
7017 .ndo_change_mtu = e1000_change_mtu,
7018 .ndo_do_ioctl = e1000_ioctl,
7019 .ndo_tx_timeout = e1000_tx_timeout,
7020 .ndo_validate_addr = eth_validate_addr,
7021
7022 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
7023 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
7024#ifdef CONFIG_NET_POLL_CONTROLLER
7025 .ndo_poll_controller = e1000_netpoll,
7026#endif
7027 .ndo_set_features = e1000_set_features,
7028 .ndo_fix_features = e1000_fix_features,
7029 .ndo_features_check = passthru_features_check,
7030};
7031
7032/**
7033 * e1000_probe - Device Initialization Routine
7034 * @pdev: PCI device information struct
7035 * @ent: entry in e1000_pci_tbl
7036 *
7037 * Returns 0 on success, negative on failure
7038 *
7039 * e1000_probe initializes an adapter identified by a pci_dev structure.
7040 * The OS initialization, configuring of the adapter private structure,
7041 * and a hardware reset occur.
7042 **/
7043static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7044{
7045 struct net_device *netdev;
7046 struct e1000_adapter *adapter;
7047 struct e1000_hw *hw;
7048 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
7049 resource_size_t mmio_start, mmio_len;
7050 resource_size_t flash_start, flash_len;
7051 static int cards_found;
7052 u16 aspm_disable_flag = 0;
7053 int bars, i, err, pci_using_dac;
7054 u16 eeprom_data = 0;
7055 u16 eeprom_apme_mask = E1000_EEPROM_APME;
7056 s32 ret_val = 0;
7057
7058 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
7059 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7060 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
7061 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7062 if (aspm_disable_flag)
7063 e1000e_disable_aspm(pdev, aspm_disable_flag);
7064
7065 err = pci_enable_device_mem(pdev);
7066 if (err)
7067 return err;
7068
7069 pci_using_dac = 0;
7070 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7071 if (!err) {
7072 pci_using_dac = 1;
7073 } else {
7074 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
7075 if (err) {
7076 dev_err(&pdev->dev,
7077 "No usable DMA configuration, aborting\n");
7078 goto err_dma;
7079 }
7080 }
7081
7082 bars = pci_select_bars(pdev, IORESOURCE_MEM);
7083 err = pci_request_selected_regions_exclusive(pdev, bars,
7084 e1000e_driver_name);
7085 if (err)
7086 goto err_pci_reg;
7087
7088 /* AER (Advanced Error Reporting) hooks */
7089 pci_enable_pcie_error_reporting(pdev);
7090
7091 pci_set_master(pdev);
7092 /* PCI config space info */
7093 err = pci_save_state(pdev);
7094 if (err)
7095 goto err_alloc_etherdev;
7096
7097 err = -ENOMEM;
7098 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
7099 if (!netdev)
7100 goto err_alloc_etherdev;
7101
7102 SET_NETDEV_DEV(netdev, &pdev->dev);
7103
7104 netdev->irq = pdev->irq;
7105
7106 pci_set_drvdata(pdev, netdev);
7107 adapter = netdev_priv(netdev);
7108 hw = &adapter->hw;
7109 adapter->netdev = netdev;
7110 adapter->pdev = pdev;
7111 adapter->ei = ei;
7112 adapter->pba = ei->pba;
7113 adapter->flags = ei->flags;
7114 adapter->flags2 = ei->flags2;
7115 adapter->hw.adapter = adapter;
7116 adapter->hw.mac.type = ei->mac;
7117 adapter->max_hw_frame_size = ei->max_hw_frame_size;
7118 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7119
7120 mmio_start = pci_resource_start(pdev, 0);
7121 mmio_len = pci_resource_len(pdev, 0);
7122
7123 err = -EIO;
7124 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
7125 if (!adapter->hw.hw_addr)
7126 goto err_ioremap;
7127
7128 if ((adapter->flags & FLAG_HAS_FLASH) &&
7129 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) &&
7130 (hw->mac.type < e1000_pch_spt)) {
7131 flash_start = pci_resource_start(pdev, 1);
7132 flash_len = pci_resource_len(pdev, 1);
7133 adapter->hw.flash_address = ioremap(flash_start, flash_len);
7134 if (!adapter->hw.flash_address)
7135 goto err_flashmap;
7136 }
7137
7138 /* Set default EEE advertisement */
7139 if (adapter->flags2 & FLAG2_HAS_EEE)
7140 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
7141
7142 /* construct the net_device struct */
7143 netdev->netdev_ops = &e1000e_netdev_ops;
7144 e1000e_set_ethtool_ops(netdev);
7145 netdev->watchdog_timeo = 5 * HZ;
7146 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
7147 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
7148
7149 netdev->mem_start = mmio_start;
7150 netdev->mem_end = mmio_start + mmio_len;
7151
7152 adapter->bd_number = cards_found++;
7153
7154 e1000e_check_options(adapter);
7155
7156 /* setup adapter struct */
7157 err = e1000_sw_init(adapter);
7158 if (err)
7159 goto err_sw_init;
7160
7161 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
7162 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
7163 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
7164
7165 err = ei->get_variants(adapter);
7166 if (err)
7167 goto err_hw_init;
7168
7169 if ((adapter->flags & FLAG_IS_ICH) &&
7170 (adapter->flags & FLAG_READ_ONLY_NVM) &&
7171 (hw->mac.type < e1000_pch_spt))
7172 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
7173
7174 hw->mac.ops.get_bus_info(&adapter->hw);
7175
7176 adapter->hw.phy.autoneg_wait_to_complete = 0;
7177
7178 /* Copper options */
7179 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
7180 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7181 adapter->hw.phy.disable_polarity_correction = 0;
7182 adapter->hw.phy.ms_type = e1000_ms_hw_default;
7183 }
7184
7185 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
7186 dev_info(&pdev->dev,
7187 "PHY reset is blocked due to SOL/IDER session.\n");
7188
7189 /* Set initial default active device features */
7190 netdev->features = (NETIF_F_SG |
7191 NETIF_F_HW_VLAN_CTAG_RX |
7192 NETIF_F_HW_VLAN_CTAG_TX |
7193 NETIF_F_TSO |
7194 NETIF_F_TSO6 |
7195 NETIF_F_RXHASH |
7196 NETIF_F_RXCSUM |
7197 NETIF_F_HW_CSUM);
7198
7199 /* Set user-changeable features (subset of all device features) */
7200 netdev->hw_features = netdev->features;
7201 netdev->hw_features |= NETIF_F_RXFCS;
7202 netdev->priv_flags |= IFF_SUPP_NOFCS;
7203 netdev->hw_features |= NETIF_F_RXALL;
7204
7205 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
7206 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
7207
7208 netdev->vlan_features |= (NETIF_F_SG |
7209 NETIF_F_TSO |
7210 NETIF_F_TSO6 |
7211 NETIF_F_HW_CSUM);
7212
7213 netdev->priv_flags |= IFF_UNICAST_FLT;
7214
7215 if (pci_using_dac) {
7216 netdev->features |= NETIF_F_HIGHDMA;
7217 netdev->vlan_features |= NETIF_F_HIGHDMA;
7218 }
7219
7220 /* MTU range: 68 - max_hw_frame_size */
7221 netdev->min_mtu = ETH_MIN_MTU;
7222 netdev->max_mtu = adapter->max_hw_frame_size -
7223 (VLAN_ETH_HLEN + ETH_FCS_LEN);
7224
7225 if (e1000e_enable_mng_pass_thru(&adapter->hw))
7226 adapter->flags |= FLAG_MNG_PT_ENABLED;
7227
7228 /* before reading the NVM, reset the controller to
7229 * put the device in a known good starting state
7230 */
7231 adapter->hw.mac.ops.reset_hw(&adapter->hw);
7232
7233 /* systems with ASPM and others may see the checksum fail on the first
7234 * attempt. Let's give it a few tries
7235 */
7236 for (i = 0;; i++) {
7237 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
7238 break;
7239 if (i == 2) {
7240 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
7241 err = -EIO;
7242 goto err_eeprom;
7243 }
7244 }
7245
7246 e1000_eeprom_checks(adapter);
7247
7248 /* copy the MAC address */
7249 if (e1000e_read_mac_addr(&adapter->hw))
7250 dev_err(&pdev->dev,
7251 "NVM Read Error while reading MAC address\n");
7252
7253 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
7254
7255 if (!is_valid_ether_addr(netdev->dev_addr)) {
7256 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
7257 netdev->dev_addr);
7258 err = -EIO;
7259 goto err_eeprom;
7260 }
7261
7262 adapter->e1000_workqueue = alloc_workqueue("%s", WQ_MEM_RECLAIM, 0,
7263 e1000e_driver_name);
7264
7265 if (!adapter->e1000_workqueue) {
7266 err = -ENOMEM;
7267 goto err_workqueue;
7268 }
7269
7270 INIT_DELAYED_WORK(&adapter->watchdog_task, e1000_watchdog_task);
7271 queue_delayed_work(adapter->e1000_workqueue, &adapter->watchdog_task,
7272 0);
7273
7274 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0);
7275
7276 INIT_WORK(&adapter->reset_task, e1000_reset_task);
7277 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
7278 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
7279 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
7280
7281 /* Initialize link parameters. User can change them with ethtool */
7282 adapter->hw.mac.autoneg = 1;
7283 adapter->fc_autoneg = true;
7284 adapter->hw.fc.requested_mode = e1000_fc_default;
7285 adapter->hw.fc.current_mode = e1000_fc_default;
7286 adapter->hw.phy.autoneg_advertised = 0x2f;
7287
7288 /* Initial Wake on LAN setting - If APM wake is enabled in
7289 * the EEPROM, enable the ACPI Magic Packet filter
7290 */
7291 if (adapter->flags & FLAG_APME_IN_WUC) {
7292 /* APME bit in EEPROM is mapped to WUC.APME */
7293 eeprom_data = er32(WUC);
7294 eeprom_apme_mask = E1000_WUC_APME;
7295 if ((hw->mac.type > e1000_ich10lan) &&
7296 (eeprom_data & E1000_WUC_PHY_WAKE))
7297 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
7298 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
7299 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
7300 (adapter->hw.bus.func == 1))
7301 ret_val = e1000_read_nvm(&adapter->hw,
7302 NVM_INIT_CONTROL3_PORT_B,
7303 1, &eeprom_data);
7304 else
7305 ret_val = e1000_read_nvm(&adapter->hw,
7306 NVM_INIT_CONTROL3_PORT_A,
7307 1, &eeprom_data);
7308 }
7309
7310 /* fetch WoL from EEPROM */
7311 if (ret_val)
7312 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val);
7313 else if (eeprom_data & eeprom_apme_mask)
7314 adapter->eeprom_wol |= E1000_WUFC_MAG;
7315
7316 /* now that we have the eeprom settings, apply the special cases
7317 * where the eeprom may be wrong or the board simply won't support
7318 * wake on lan on a particular port
7319 */
7320 if (!(adapter->flags & FLAG_HAS_WOL))
7321 adapter->eeprom_wol = 0;
7322
7323 /* initialize the wol settings based on the eeprom settings */
7324 adapter->wol = adapter->eeprom_wol;
7325
7326 /* make sure adapter isn't asleep if manageability is enabled */
7327 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
7328 (hw->mac.ops.check_mng_mode(hw)))
7329 device_wakeup_enable(&pdev->dev);
7330
7331 /* save off EEPROM version number */
7332 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
7333
7334 if (ret_val) {
7335 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val);
7336 adapter->eeprom_vers = 0;
7337 }
7338
7339 /* init PTP hardware clock */
7340 e1000e_ptp_init(adapter);
7341
7342 /* reset the hardware with the new settings */
7343 e1000e_reset(adapter);
7344
7345 /* If the controller has AMT, do not set DRV_LOAD until the interface
7346 * is up. For all other cases, let the f/w know that the h/w is now
7347 * under the control of the driver.
7348 */
7349 if (!(adapter->flags & FLAG_HAS_AMT))
7350 e1000e_get_hw_control(adapter);
7351
7352 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
7353 err = register_netdev(netdev);
7354 if (err)
7355 goto err_register;
7356
7357 /* carrier off reporting is important to ethtool even BEFORE open */
7358 netif_carrier_off(netdev);
7359
7360 e1000_print_device_info(adapter);
7361
7362 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
7363
7364 if (pci_dev_run_wake(pdev) && hw->mac.type < e1000_pch_cnp)
7365 pm_runtime_put_noidle(&pdev->dev);
7366
7367 return 0;
7368
7369err_register:
7370 flush_workqueue(adapter->e1000_workqueue);
7371 destroy_workqueue(adapter->e1000_workqueue);
7372err_workqueue:
7373 if (!(adapter->flags & FLAG_HAS_AMT))
7374 e1000e_release_hw_control(adapter);
7375err_eeprom:
7376 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
7377 e1000_phy_hw_reset(&adapter->hw);
7378err_hw_init:
7379 kfree(adapter->tx_ring);
7380 kfree(adapter->rx_ring);
7381err_sw_init:
7382 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt))
7383 iounmap(adapter->hw.flash_address);
7384 e1000e_reset_interrupt_capability(adapter);
7385err_flashmap:
7386 iounmap(adapter->hw.hw_addr);
7387err_ioremap:
7388 free_netdev(netdev);
7389err_alloc_etherdev:
7390 pci_release_mem_regions(pdev);
7391err_pci_reg:
7392err_dma:
7393 pci_disable_device(pdev);
7394 return err;
7395}
7396
7397/**
7398 * e1000_remove - Device Removal Routine
7399 * @pdev: PCI device information struct
7400 *
7401 * e1000_remove is called by the PCI subsystem to alert the driver
7402 * that it should release a PCI device. The could be caused by a
7403 * Hot-Plug event, or because the driver is going to be removed from
7404 * memory.
7405 **/
7406static void e1000_remove(struct pci_dev *pdev)
7407{
7408 struct net_device *netdev = pci_get_drvdata(pdev);
7409 struct e1000_adapter *adapter = netdev_priv(netdev);
7410 bool down = test_bit(__E1000_DOWN, &adapter->state);
7411
7412 e1000e_ptp_remove(adapter);
7413
7414 /* The timers may be rescheduled, so explicitly disable them
7415 * from being rescheduled.
7416 */
7417 if (!down)
7418 set_bit(__E1000_DOWN, &adapter->state);
7419 del_timer_sync(&adapter->phy_info_timer);
7420
7421 cancel_work_sync(&adapter->reset_task);
7422 cancel_work_sync(&adapter->downshift_task);
7423 cancel_work_sync(&adapter->update_phy_task);
7424 cancel_work_sync(&adapter->print_hang_task);
7425
7426 cancel_delayed_work(&adapter->watchdog_task);
7427 flush_workqueue(adapter->e1000_workqueue);
7428 destroy_workqueue(adapter->e1000_workqueue);
7429
7430 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
7431 cancel_work_sync(&adapter->tx_hwtstamp_work);
7432 if (adapter->tx_hwtstamp_skb) {
7433 dev_consume_skb_any(adapter->tx_hwtstamp_skb);
7434 adapter->tx_hwtstamp_skb = NULL;
7435 }
7436 }
7437
7438 /* Don't lie to e1000_close() down the road. */
7439 if (!down)
7440 clear_bit(__E1000_DOWN, &adapter->state);
7441 unregister_netdev(netdev);
7442
7443 if (pci_dev_run_wake(pdev))
7444 pm_runtime_get_noresume(&pdev->dev);
7445
7446 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7447 * would have already happened in close and is redundant.
7448 */
7449 e1000e_release_hw_control(adapter);
7450
7451 e1000e_reset_interrupt_capability(adapter);
7452 kfree(adapter->tx_ring);
7453 kfree(adapter->rx_ring);
7454
7455 iounmap(adapter->hw.hw_addr);
7456 if ((adapter->hw.flash_address) &&
7457 (adapter->hw.mac.type < e1000_pch_spt))
7458 iounmap(adapter->hw.flash_address);
7459 pci_release_mem_regions(pdev);
7460
7461 free_netdev(netdev);
7462
7463 /* AER disable */
7464 pci_disable_pcie_error_reporting(pdev);
7465
7466 pci_disable_device(pdev);
7467}
7468
7469/* PCI Error Recovery (ERS) */
7470static const struct pci_error_handlers e1000_err_handler = {
7471 .error_detected = e1000_io_error_detected,
7472 .slot_reset = e1000_io_slot_reset,
7473 .resume = e1000_io_resume,
7474};
7475
7476static const struct pci_device_id e1000_pci_tbl[] = {
7477 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
7478 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
7479 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
7480 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7481 board_82571 },
7482 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
7483 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
7484 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
7485 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
7486 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
7487
7488 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
7489 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
7490 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
7491 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
7492
7493 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
7494 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
7495 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
7496
7497 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
7498 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
7499 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
7500
7501 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7502 board_80003es2lan },
7503 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7504 board_80003es2lan },
7505 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7506 board_80003es2lan },
7507 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7508 board_80003es2lan },
7509
7510 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
7511 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
7512 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
7513 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
7514 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
7515 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
7516 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
7517 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
7518
7519 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
7520 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
7521 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
7522 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
7523 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
7524 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
7525 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
7526 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
7527 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
7528
7529 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
7530 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
7531 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
7532
7533 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
7534 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
7535 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
7536
7537 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
7538 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
7539 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7540 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7541
7542 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7543 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7544
7545 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7546 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
7547 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7548 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
7549 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt },
7550 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7551 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7552 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
7553 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt },
7554 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt },
7555 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt },
7556 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt },
7557 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt },
7558 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt },
7559 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt },
7560 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt },
7561 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt },
7562 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp },
7563 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp },
7564 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp },
7565 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp },
7566 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp },
7567 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp },
7568 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp },
7569 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp },
7570
7571 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
7572};
7573MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7574
7575static const struct dev_pm_ops e1000_pm_ops = {
7576#ifdef CONFIG_PM_SLEEP
7577 .suspend = e1000e_pm_suspend,
7578 .resume = e1000e_pm_resume,
7579 .freeze = e1000e_pm_freeze,
7580 .thaw = e1000e_pm_thaw,
7581 .poweroff = e1000e_pm_suspend,
7582 .restore = e1000e_pm_resume,
7583#endif
7584 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
7585 e1000e_pm_runtime_idle)
7586};
7587
7588/* PCI Device API Driver */
7589static struct pci_driver e1000_driver = {
7590 .name = e1000e_driver_name,
7591 .id_table = e1000_pci_tbl,
7592 .probe = e1000_probe,
7593 .remove = e1000_remove,
7594 .driver = {
7595 .pm = &e1000_pm_ops,
7596 },
7597 .shutdown = e1000_shutdown,
7598 .err_handler = &e1000_err_handler
7599};
7600
7601/**
7602 * e1000_init_module - Driver Registration Routine
7603 *
7604 * e1000_init_module is the first routine called when the driver is
7605 * loaded. All it does is register with the PCI subsystem.
7606 **/
7607static int __init e1000_init_module(void)
7608{
7609 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
7610 e1000e_driver_version);
7611 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n");
7612
7613 return pci_register_driver(&e1000_driver);
7614}
7615module_init(e1000_init_module);
7616
7617/**
7618 * e1000_exit_module - Driver Exit Cleanup Routine
7619 *
7620 * e1000_exit_module is called just before the driver is removed
7621 * from memory.
7622 **/
7623static void __exit e1000_exit_module(void)
7624{
7625 pci_unregister_driver(&e1000_driver);
7626}
7627module_exit(e1000_exit_module);
7628
7629MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7630MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7631MODULE_LICENSE("GPL v2");
7632MODULE_VERSION(DRV_VERSION);
7633
7634/* netdev.c */