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1// SPDX-License-Identifier: GPL-2.0+
2/* Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> */
3
4#include <linux/module.h>
5#include <linux/device.h>
6#include <linux/pci.h>
7#include <linux/ptp_classify.h>
8
9#include "igb.h"
10
11#define INCVALUE_MASK 0x7fffffff
12#define ISGN 0x80000000
13
14/* The 82580 timesync updates the system timer every 8ns by 8ns,
15 * and this update value cannot be reprogrammed.
16 *
17 * Neither the 82576 nor the 82580 offer registers wide enough to hold
18 * nanoseconds time values for very long. For the 82580, SYSTIM always
19 * counts nanoseconds, but the upper 24 bits are not available. The
20 * frequency is adjusted by changing the 32 bit fractional nanoseconds
21 * register, TIMINCA.
22 *
23 * For the 82576, the SYSTIM register time unit is affect by the
24 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
25 * field are needed to provide the nominal 16 nanosecond period,
26 * leaving 19 bits for fractional nanoseconds.
27 *
28 * We scale the NIC clock cycle by a large factor so that relatively
29 * small clock corrections can be added or subtracted at each clock
30 * tick. The drawbacks of a large factor are a) that the clock
31 * register overflows more quickly (not such a big deal) and b) that
32 * the increment per tick has to fit into 24 bits. As a result we
33 * need to use a shift of 19 so we can fit a value of 16 into the
34 * TIMINCA register.
35 *
36 *
37 * SYSTIMH SYSTIML
38 * +--------------+ +---+---+------+
39 * 82576 | 32 | | 8 | 5 | 19 |
40 * +--------------+ +---+---+------+
41 * \________ 45 bits _______/ fract
42 *
43 * +----------+---+ +--------------+
44 * 82580 | 24 | 8 | | 32 |
45 * +----------+---+ +--------------+
46 * reserved \______ 40 bits _____/
47 *
48 *
49 * The 45 bit 82576 SYSTIM overflows every
50 * 2^45 * 10^-9 / 3600 = 9.77 hours.
51 *
52 * The 40 bit 82580 SYSTIM overflows every
53 * 2^40 * 10^-9 / 60 = 18.3 minutes.
54 *
55 * SYSTIM is converted to real time using a timecounter. As
56 * timecounter_cyc2time() allows old timestamps, the timecounter needs
57 * to be updated at least once per half of the SYSTIM interval.
58 * Scheduling of delayed work is not very accurate, and also the NIC
59 * clock can be adjusted to run up to 6% faster and the system clock
60 * up to 10% slower, so we aim for 6 minutes to be sure the actual
61 * interval in the NIC time is shorter than 9.16 minutes.
62 */
63
64#define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 6)
65#define IGB_PTP_TX_TIMEOUT (HZ * 15)
66#define INCPERIOD_82576 BIT(E1000_TIMINCA_16NS_SHIFT)
67#define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0)
68#define INCVALUE_82576 (16u << IGB_82576_TSYNC_SHIFT)
69#define IGB_NBITS_82580 40
70#define IGB_82580_BASE_PERIOD 0x800000000
71
72static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
73static void igb_ptp_sdp_init(struct igb_adapter *adapter);
74
75/* SYSTIM read access for the 82576 */
76static u64 igb_ptp_read_82576(const struct cyclecounter *cc)
77{
78 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
79 struct e1000_hw *hw = &igb->hw;
80 u64 val;
81 u32 lo, hi;
82
83 lo = rd32(E1000_SYSTIML);
84 hi = rd32(E1000_SYSTIMH);
85
86 val = ((u64) hi) << 32;
87 val |= lo;
88
89 return val;
90}
91
92/* SYSTIM read access for the 82580 */
93static u64 igb_ptp_read_82580(const struct cyclecounter *cc)
94{
95 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
96 struct e1000_hw *hw = &igb->hw;
97 u32 lo, hi;
98 u64 val;
99
100 /* The timestamp latches on lowest register read. For the 82580
101 * the lowest register is SYSTIMR instead of SYSTIML. However we only
102 * need to provide nanosecond resolution, so we just ignore it.
103 */
104 rd32(E1000_SYSTIMR);
105 lo = rd32(E1000_SYSTIML);
106 hi = rd32(E1000_SYSTIMH);
107
108 val = ((u64) hi) << 32;
109 val |= lo;
110
111 return val;
112}
113
114/* SYSTIM read access for I210/I211 */
115static void igb_ptp_read_i210(struct igb_adapter *adapter,
116 struct timespec64 *ts)
117{
118 struct e1000_hw *hw = &adapter->hw;
119 u32 sec, nsec;
120
121 /* The timestamp latches on lowest register read. For I210/I211, the
122 * lowest register is SYSTIMR. Since we only need to provide nanosecond
123 * resolution, we can ignore it.
124 */
125 rd32(E1000_SYSTIMR);
126 nsec = rd32(E1000_SYSTIML);
127 sec = rd32(E1000_SYSTIMH);
128
129 ts->tv_sec = sec;
130 ts->tv_nsec = nsec;
131}
132
133static void igb_ptp_write_i210(struct igb_adapter *adapter,
134 const struct timespec64 *ts)
135{
136 struct e1000_hw *hw = &adapter->hw;
137
138 /* Writing the SYSTIMR register is not necessary as it only provides
139 * sub-nanosecond resolution.
140 */
141 wr32(E1000_SYSTIML, ts->tv_nsec);
142 wr32(E1000_SYSTIMH, (u32)ts->tv_sec);
143}
144
145/**
146 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
147 * @adapter: board private structure
148 * @hwtstamps: timestamp structure to update
149 * @systim: unsigned 64bit system time value.
150 *
151 * We need to convert the system time value stored in the RX/TXSTMP registers
152 * into a hwtstamp which can be used by the upper level timestamping functions.
153 *
154 * The 'tmreg_lock' spinlock is used to protect the consistency of the
155 * system time value. This is needed because reading the 64 bit time
156 * value involves reading two (or three) 32 bit registers. The first
157 * read latches the value. Ditto for writing.
158 *
159 * In addition, here have extended the system time with an overflow
160 * counter in software.
161 **/
162static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,
163 struct skb_shared_hwtstamps *hwtstamps,
164 u64 systim)
165{
166 unsigned long flags;
167 u64 ns;
168
169 memset(hwtstamps, 0, sizeof(*hwtstamps));
170
171 switch (adapter->hw.mac.type) {
172 case e1000_82576:
173 case e1000_82580:
174 case e1000_i354:
175 case e1000_i350:
176 spin_lock_irqsave(&adapter->tmreg_lock, flags);
177 ns = timecounter_cyc2time(&adapter->tc, systim);
178 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
179
180 hwtstamps->hwtstamp = ns_to_ktime(ns);
181 break;
182 case e1000_i210:
183 case e1000_i211:
184 /* Upper 32 bits contain s, lower 32 bits contain ns. */
185 hwtstamps->hwtstamp = ktime_set(systim >> 32,
186 systim & 0xFFFFFFFF);
187 break;
188 default:
189 break;
190 }
191}
192
193/* PTP clock operations */
194static int igb_ptp_adjfine_82576(struct ptp_clock_info *ptp, long scaled_ppm)
195{
196 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
197 ptp_caps);
198 struct e1000_hw *hw = &igb->hw;
199 u64 incvalue;
200
201 incvalue = adjust_by_scaled_ppm(INCVALUE_82576, scaled_ppm);
202
203 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
204
205 return 0;
206}
207
208static int igb_ptp_adjfine_82580(struct ptp_clock_info *ptp, long scaled_ppm)
209{
210 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
211 ptp_caps);
212 struct e1000_hw *hw = &igb->hw;
213 bool neg_adj;
214 u64 rate;
215 u32 inca;
216
217 neg_adj = diff_by_scaled_ppm(IGB_82580_BASE_PERIOD, scaled_ppm, &rate);
218
219 inca = rate & INCVALUE_MASK;
220 if (neg_adj)
221 inca |= ISGN;
222
223 wr32(E1000_TIMINCA, inca);
224
225 return 0;
226}
227
228static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta)
229{
230 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
231 ptp_caps);
232 unsigned long flags;
233
234 spin_lock_irqsave(&igb->tmreg_lock, flags);
235 timecounter_adjtime(&igb->tc, delta);
236 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
237
238 return 0;
239}
240
241static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta)
242{
243 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
244 ptp_caps);
245 unsigned long flags;
246 struct timespec64 now, then = ns_to_timespec64(delta);
247
248 spin_lock_irqsave(&igb->tmreg_lock, flags);
249
250 igb_ptp_read_i210(igb, &now);
251 now = timespec64_add(now, then);
252 igb_ptp_write_i210(igb, (const struct timespec64 *)&now);
253
254 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
255
256 return 0;
257}
258
259static int igb_ptp_gettimex_82576(struct ptp_clock_info *ptp,
260 struct timespec64 *ts,
261 struct ptp_system_timestamp *sts)
262{
263 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
264 ptp_caps);
265 struct e1000_hw *hw = &igb->hw;
266 unsigned long flags;
267 u32 lo, hi;
268 u64 ns;
269
270 spin_lock_irqsave(&igb->tmreg_lock, flags);
271
272 ptp_read_system_prets(sts);
273 lo = rd32(E1000_SYSTIML);
274 ptp_read_system_postts(sts);
275 hi = rd32(E1000_SYSTIMH);
276
277 ns = timecounter_cyc2time(&igb->tc, ((u64)hi << 32) | lo);
278
279 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
280
281 *ts = ns_to_timespec64(ns);
282
283 return 0;
284}
285
286static int igb_ptp_gettimex_82580(struct ptp_clock_info *ptp,
287 struct timespec64 *ts,
288 struct ptp_system_timestamp *sts)
289{
290 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
291 ptp_caps);
292 struct e1000_hw *hw = &igb->hw;
293 unsigned long flags;
294 u32 lo, hi;
295 u64 ns;
296
297 spin_lock_irqsave(&igb->tmreg_lock, flags);
298
299 ptp_read_system_prets(sts);
300 rd32(E1000_SYSTIMR);
301 ptp_read_system_postts(sts);
302 lo = rd32(E1000_SYSTIML);
303 hi = rd32(E1000_SYSTIMH);
304
305 ns = timecounter_cyc2time(&igb->tc, ((u64)hi << 32) | lo);
306
307 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
308
309 *ts = ns_to_timespec64(ns);
310
311 return 0;
312}
313
314static int igb_ptp_gettimex_i210(struct ptp_clock_info *ptp,
315 struct timespec64 *ts,
316 struct ptp_system_timestamp *sts)
317{
318 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
319 ptp_caps);
320 struct e1000_hw *hw = &igb->hw;
321 unsigned long flags;
322
323 spin_lock_irqsave(&igb->tmreg_lock, flags);
324
325 ptp_read_system_prets(sts);
326 rd32(E1000_SYSTIMR);
327 ptp_read_system_postts(sts);
328 ts->tv_nsec = rd32(E1000_SYSTIML);
329 ts->tv_sec = rd32(E1000_SYSTIMH);
330
331 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
332
333 return 0;
334}
335
336static int igb_ptp_settime_82576(struct ptp_clock_info *ptp,
337 const struct timespec64 *ts)
338{
339 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
340 ptp_caps);
341 unsigned long flags;
342 u64 ns;
343
344 ns = timespec64_to_ns(ts);
345
346 spin_lock_irqsave(&igb->tmreg_lock, flags);
347
348 timecounter_init(&igb->tc, &igb->cc, ns);
349
350 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
351
352 return 0;
353}
354
355static int igb_ptp_settime_i210(struct ptp_clock_info *ptp,
356 const struct timespec64 *ts)
357{
358 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
359 ptp_caps);
360 unsigned long flags;
361
362 spin_lock_irqsave(&igb->tmreg_lock, flags);
363
364 igb_ptp_write_i210(igb, ts);
365
366 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
367
368 return 0;
369}
370
371static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
372{
373 u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
374 static const u32 mask[IGB_N_SDP] = {
375 E1000_CTRL_SDP0_DIR,
376 E1000_CTRL_SDP1_DIR,
377 E1000_CTRL_EXT_SDP2_DIR,
378 E1000_CTRL_EXT_SDP3_DIR,
379 };
380
381 if (input)
382 *ptr &= ~mask[pin];
383 else
384 *ptr |= mask[pin];
385}
386
387static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin)
388{
389 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
390 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
391 };
392 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
393 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
394 };
395 static const u32 ts_sdp_en[IGB_N_SDP] = {
396 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
397 };
398 struct e1000_hw *hw = &igb->hw;
399 u32 ctrl, ctrl_ext, tssdp = 0;
400
401 ctrl = rd32(E1000_CTRL);
402 ctrl_ext = rd32(E1000_CTRL_EXT);
403 tssdp = rd32(E1000_TSSDP);
404
405 igb_pin_direction(pin, 1, &ctrl, &ctrl_ext);
406
407 /* Make sure this pin is not enabled as an output. */
408 tssdp &= ~ts_sdp_en[pin];
409
410 if (chan == 1) {
411 tssdp &= ~AUX1_SEL_SDP3;
412 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN;
413 } else {
414 tssdp &= ~AUX0_SEL_SDP3;
415 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN;
416 }
417
418 wr32(E1000_TSSDP, tssdp);
419 wr32(E1000_CTRL, ctrl);
420 wr32(E1000_CTRL_EXT, ctrl_ext);
421}
422
423static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq)
424{
425 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
426 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
427 };
428 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
429 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
430 };
431 static const u32 ts_sdp_en[IGB_N_SDP] = {
432 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
433 };
434 static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = {
435 TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0,
436 TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0,
437 };
438 static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = {
439 TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1,
440 TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1,
441 };
442 static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = {
443 TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0,
444 TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0,
445 };
446 static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = {
447 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
448 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
449 };
450 static const u32 ts_sdp_sel_clr[IGB_N_SDP] = {
451 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
452 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
453 };
454 struct e1000_hw *hw = &igb->hw;
455 u32 ctrl, ctrl_ext, tssdp = 0;
456
457 ctrl = rd32(E1000_CTRL);
458 ctrl_ext = rd32(E1000_CTRL_EXT);
459 tssdp = rd32(E1000_TSSDP);
460
461 igb_pin_direction(pin, 0, &ctrl, &ctrl_ext);
462
463 /* Make sure this pin is not enabled as an input. */
464 if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin])
465 tssdp &= ~AUX0_TS_SDP_EN;
466
467 if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin])
468 tssdp &= ~AUX1_TS_SDP_EN;
469
470 tssdp &= ~ts_sdp_sel_clr[pin];
471 if (freq) {
472 if (chan == 1)
473 tssdp |= ts_sdp_sel_fc1[pin];
474 else
475 tssdp |= ts_sdp_sel_fc0[pin];
476 } else {
477 if (chan == 1)
478 tssdp |= ts_sdp_sel_tt1[pin];
479 else
480 tssdp |= ts_sdp_sel_tt0[pin];
481 }
482 tssdp |= ts_sdp_en[pin];
483
484 wr32(E1000_TSSDP, tssdp);
485 wr32(E1000_CTRL, ctrl);
486 wr32(E1000_CTRL_EXT, ctrl_ext);
487}
488
489static int igb_ptp_feature_enable_82580(struct ptp_clock_info *ptp,
490 struct ptp_clock_request *rq, int on)
491{
492 struct igb_adapter *igb =
493 container_of(ptp, struct igb_adapter, ptp_caps);
494 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, systiml,
495 systimh, level_mask, level, rem;
496 struct e1000_hw *hw = &igb->hw;
497 struct timespec64 ts, start;
498 unsigned long flags;
499 u64 systim, now;
500 int pin = -1;
501 s64 ns;
502
503 switch (rq->type) {
504 case PTP_CLK_REQ_EXTTS:
505 /* Reject requests with unsupported flags */
506 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
507 PTP_RISING_EDGE |
508 PTP_FALLING_EDGE |
509 PTP_STRICT_FLAGS))
510 return -EOPNOTSUPP;
511
512 if (on) {
513 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS,
514 rq->extts.index);
515 if (pin < 0)
516 return -EBUSY;
517 }
518 if (rq->extts.index == 1) {
519 tsauxc_mask = TSAUXC_EN_TS1;
520 tsim_mask = TSINTR_AUTT1;
521 } else {
522 tsauxc_mask = TSAUXC_EN_TS0;
523 tsim_mask = TSINTR_AUTT0;
524 }
525 spin_lock_irqsave(&igb->tmreg_lock, flags);
526 tsauxc = rd32(E1000_TSAUXC);
527 tsim = rd32(E1000_TSIM);
528 if (on) {
529 igb_pin_extts(igb, rq->extts.index, pin);
530 tsauxc |= tsauxc_mask;
531 tsim |= tsim_mask;
532 } else {
533 tsauxc &= ~tsauxc_mask;
534 tsim &= ~tsim_mask;
535 }
536 wr32(E1000_TSAUXC, tsauxc);
537 wr32(E1000_TSIM, tsim);
538 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
539 return 0;
540
541 case PTP_CLK_REQ_PEROUT:
542 /* Reject requests with unsupported flags */
543 if (rq->perout.flags)
544 return -EOPNOTSUPP;
545
546 if (on) {
547 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT,
548 rq->perout.index);
549 if (pin < 0)
550 return -EBUSY;
551 }
552 ts.tv_sec = rq->perout.period.sec;
553 ts.tv_nsec = rq->perout.period.nsec;
554 ns = timespec64_to_ns(&ts);
555 ns = ns >> 1;
556 if (on && ns < 8LL)
557 return -EINVAL;
558 ts = ns_to_timespec64(ns);
559 if (rq->perout.index == 1) {
560 tsauxc_mask = TSAUXC_EN_TT1;
561 tsim_mask = TSINTR_TT1;
562 trgttiml = E1000_TRGTTIML1;
563 trgttimh = E1000_TRGTTIMH1;
564 } else {
565 tsauxc_mask = TSAUXC_EN_TT0;
566 tsim_mask = TSINTR_TT0;
567 trgttiml = E1000_TRGTTIML0;
568 trgttimh = E1000_TRGTTIMH0;
569 }
570 spin_lock_irqsave(&igb->tmreg_lock, flags);
571 tsauxc = rd32(E1000_TSAUXC);
572 tsim = rd32(E1000_TSIM);
573 if (rq->perout.index == 1) {
574 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1);
575 tsim &= ~TSINTR_TT1;
576 } else {
577 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0);
578 tsim &= ~TSINTR_TT0;
579 }
580 if (on) {
581 int i = rq->perout.index;
582
583 /* read systim registers in sequence */
584 rd32(E1000_SYSTIMR);
585 systiml = rd32(E1000_SYSTIML);
586 systimh = rd32(E1000_SYSTIMH);
587 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml);
588 now = timecounter_cyc2time(&igb->tc, systim);
589
590 if (pin < 2) {
591 level_mask = (i == 1) ? 0x80000 : 0x40000;
592 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0;
593 } else {
594 level_mask = (i == 1) ? 0x80 : 0x40;
595 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0;
596 }
597
598 div_u64_rem(now, ns, &rem);
599 systim = systim + (ns - rem);
600
601 /* synchronize pin level with rising/falling edges */
602 div_u64_rem(now, ns << 1, &rem);
603 if (rem < ns) {
604 /* first half of period */
605 if (level == 0) {
606 /* output is already low, skip this period */
607 systim += ns;
608 }
609 } else {
610 /* second half of period */
611 if (level == 1) {
612 /* output is already high, skip this period */
613 systim += ns;
614 }
615 }
616
617 start = ns_to_timespec64(systim + (ns - rem));
618 igb_pin_perout(igb, i, pin, 0);
619 igb->perout[i].start.tv_sec = start.tv_sec;
620 igb->perout[i].start.tv_nsec = start.tv_nsec;
621 igb->perout[i].period.tv_sec = ts.tv_sec;
622 igb->perout[i].period.tv_nsec = ts.tv_nsec;
623
624 wr32(trgttiml, (u32)systim);
625 wr32(trgttimh, ((u32)(systim >> 32)) & 0xFF);
626 tsauxc |= tsauxc_mask;
627 tsim |= tsim_mask;
628 }
629 wr32(E1000_TSAUXC, tsauxc);
630 wr32(E1000_TSIM, tsim);
631 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
632 return 0;
633
634 case PTP_CLK_REQ_PPS:
635 return -EOPNOTSUPP;
636 }
637
638 return -EOPNOTSUPP;
639}
640
641static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp,
642 struct ptp_clock_request *rq, int on)
643{
644 struct igb_adapter *igb =
645 container_of(ptp, struct igb_adapter, ptp_caps);
646 struct e1000_hw *hw = &igb->hw;
647 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
648 unsigned long flags;
649 struct timespec64 ts;
650 int use_freq = 0, pin = -1;
651 s64 ns;
652
653 switch (rq->type) {
654 case PTP_CLK_REQ_EXTTS:
655 /* Reject requests with unsupported flags */
656 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
657 PTP_RISING_EDGE |
658 PTP_FALLING_EDGE |
659 PTP_STRICT_FLAGS))
660 return -EOPNOTSUPP;
661
662 /* Reject requests failing to enable both edges. */
663 if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
664 (rq->extts.flags & PTP_ENABLE_FEATURE) &&
665 (rq->extts.flags & PTP_EXTTS_EDGES) != PTP_EXTTS_EDGES)
666 return -EOPNOTSUPP;
667
668 if (on) {
669 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS,
670 rq->extts.index);
671 if (pin < 0)
672 return -EBUSY;
673 }
674 if (rq->extts.index == 1) {
675 tsauxc_mask = TSAUXC_EN_TS1;
676 tsim_mask = TSINTR_AUTT1;
677 } else {
678 tsauxc_mask = TSAUXC_EN_TS0;
679 tsim_mask = TSINTR_AUTT0;
680 }
681 spin_lock_irqsave(&igb->tmreg_lock, flags);
682 tsauxc = rd32(E1000_TSAUXC);
683 tsim = rd32(E1000_TSIM);
684 if (on) {
685 igb_pin_extts(igb, rq->extts.index, pin);
686 tsauxc |= tsauxc_mask;
687 tsim |= tsim_mask;
688 } else {
689 tsauxc &= ~tsauxc_mask;
690 tsim &= ~tsim_mask;
691 }
692 wr32(E1000_TSAUXC, tsauxc);
693 wr32(E1000_TSIM, tsim);
694 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
695 return 0;
696
697 case PTP_CLK_REQ_PEROUT:
698 /* Reject requests with unsupported flags */
699 if (rq->perout.flags)
700 return -EOPNOTSUPP;
701
702 if (on) {
703 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT,
704 rq->perout.index);
705 if (pin < 0)
706 return -EBUSY;
707 }
708 ts.tv_sec = rq->perout.period.sec;
709 ts.tv_nsec = rq->perout.period.nsec;
710 ns = timespec64_to_ns(&ts);
711 ns = ns >> 1;
712 if (on && ((ns <= 70000000LL) || (ns == 125000000LL) ||
713 (ns == 250000000LL) || (ns == 500000000LL))) {
714 if (ns < 8LL)
715 return -EINVAL;
716 use_freq = 1;
717 }
718 ts = ns_to_timespec64(ns);
719 if (rq->perout.index == 1) {
720 if (use_freq) {
721 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1;
722 tsim_mask = 0;
723 } else {
724 tsauxc_mask = TSAUXC_EN_TT1;
725 tsim_mask = TSINTR_TT1;
726 }
727 trgttiml = E1000_TRGTTIML1;
728 trgttimh = E1000_TRGTTIMH1;
729 freqout = E1000_FREQOUT1;
730 } else {
731 if (use_freq) {
732 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0;
733 tsim_mask = 0;
734 } else {
735 tsauxc_mask = TSAUXC_EN_TT0;
736 tsim_mask = TSINTR_TT0;
737 }
738 trgttiml = E1000_TRGTTIML0;
739 trgttimh = E1000_TRGTTIMH0;
740 freqout = E1000_FREQOUT0;
741 }
742 spin_lock_irqsave(&igb->tmreg_lock, flags);
743 tsauxc = rd32(E1000_TSAUXC);
744 tsim = rd32(E1000_TSIM);
745 if (rq->perout.index == 1) {
746 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1);
747 tsim &= ~TSINTR_TT1;
748 } else {
749 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0);
750 tsim &= ~TSINTR_TT0;
751 }
752 if (on) {
753 int i = rq->perout.index;
754 igb_pin_perout(igb, i, pin, use_freq);
755 igb->perout[i].start.tv_sec = rq->perout.start.sec;
756 igb->perout[i].start.tv_nsec = rq->perout.start.nsec;
757 igb->perout[i].period.tv_sec = ts.tv_sec;
758 igb->perout[i].period.tv_nsec = ts.tv_nsec;
759 wr32(trgttimh, rq->perout.start.sec);
760 wr32(trgttiml, rq->perout.start.nsec);
761 if (use_freq)
762 wr32(freqout, ns);
763 tsauxc |= tsauxc_mask;
764 tsim |= tsim_mask;
765 }
766 wr32(E1000_TSAUXC, tsauxc);
767 wr32(E1000_TSIM, tsim);
768 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
769 return 0;
770
771 case PTP_CLK_REQ_PPS:
772 spin_lock_irqsave(&igb->tmreg_lock, flags);
773 tsim = rd32(E1000_TSIM);
774 if (on)
775 tsim |= TSINTR_SYS_WRAP;
776 else
777 tsim &= ~TSINTR_SYS_WRAP;
778 igb->pps_sys_wrap_on = !!on;
779 wr32(E1000_TSIM, tsim);
780 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
781 return 0;
782 }
783
784 return -EOPNOTSUPP;
785}
786
787static int igb_ptp_feature_enable(struct ptp_clock_info *ptp,
788 struct ptp_clock_request *rq, int on)
789{
790 return -EOPNOTSUPP;
791}
792
793static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
794 enum ptp_pin_function func, unsigned int chan)
795{
796 switch (func) {
797 case PTP_PF_NONE:
798 case PTP_PF_EXTTS:
799 case PTP_PF_PEROUT:
800 break;
801 case PTP_PF_PHYSYNC:
802 return -1;
803 }
804 return 0;
805}
806
807/**
808 * igb_ptp_tx_work
809 * @work: pointer to work struct
810 *
811 * This work function polls the TSYNCTXCTL valid bit to determine when a
812 * timestamp has been taken for the current stored skb.
813 **/
814static void igb_ptp_tx_work(struct work_struct *work)
815{
816 struct igb_adapter *adapter = container_of(work, struct igb_adapter,
817 ptp_tx_work);
818 struct e1000_hw *hw = &adapter->hw;
819 u32 tsynctxctl;
820
821 if (!adapter->ptp_tx_skb)
822 return;
823
824 if (time_is_before_jiffies(adapter->ptp_tx_start +
825 IGB_PTP_TX_TIMEOUT)) {
826 dev_kfree_skb_any(adapter->ptp_tx_skb);
827 adapter->ptp_tx_skb = NULL;
828 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
829 adapter->tx_hwtstamp_timeouts++;
830 /* Clear the tx valid bit in TSYNCTXCTL register to enable
831 * interrupt
832 */
833 rd32(E1000_TXSTMPH);
834 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
835 return;
836 }
837
838 tsynctxctl = rd32(E1000_TSYNCTXCTL);
839 if (tsynctxctl & E1000_TSYNCTXCTL_VALID)
840 igb_ptp_tx_hwtstamp(adapter);
841 else
842 /* reschedule to check later */
843 schedule_work(&adapter->ptp_tx_work);
844}
845
846static void igb_ptp_overflow_check(struct work_struct *work)
847{
848 struct igb_adapter *igb =
849 container_of(work, struct igb_adapter, ptp_overflow_work.work);
850 struct timespec64 ts;
851 u64 ns;
852
853 /* Update the timecounter */
854 ns = timecounter_read(&igb->tc);
855
856 ts = ns_to_timespec64(ns);
857 pr_debug("igb overflow check at %lld.%09lu\n",
858 (long long) ts.tv_sec, ts.tv_nsec);
859
860 schedule_delayed_work(&igb->ptp_overflow_work,
861 IGB_SYSTIM_OVERFLOW_PERIOD);
862}
863
864/**
865 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched
866 * @adapter: private network adapter structure
867 *
868 * This watchdog task is scheduled to detect error case where hardware has
869 * dropped an Rx packet that was timestamped when the ring is full. The
870 * particular error is rare but leaves the device in a state unable to timestamp
871 * any future packets.
872 **/
873void igb_ptp_rx_hang(struct igb_adapter *adapter)
874{
875 struct e1000_hw *hw = &adapter->hw;
876 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL);
877 unsigned long rx_event;
878
879 /* Other hardware uses per-packet timestamps */
880 if (hw->mac.type != e1000_82576)
881 return;
882
883 /* If we don't have a valid timestamp in the registers, just update the
884 * timeout counter and exit
885 */
886 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) {
887 adapter->last_rx_ptp_check = jiffies;
888 return;
889 }
890
891 /* Determine the most recent watchdog or rx_timestamp event */
892 rx_event = adapter->last_rx_ptp_check;
893 if (time_after(adapter->last_rx_timestamp, rx_event))
894 rx_event = adapter->last_rx_timestamp;
895
896 /* Only need to read the high RXSTMP register to clear the lock */
897 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
898 rd32(E1000_RXSTMPH);
899 adapter->last_rx_ptp_check = jiffies;
900 adapter->rx_hwtstamp_cleared++;
901 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n");
902 }
903}
904
905/**
906 * igb_ptp_tx_hang - detect error case where Tx timestamp never finishes
907 * @adapter: private network adapter structure
908 */
909void igb_ptp_tx_hang(struct igb_adapter *adapter)
910{
911 struct e1000_hw *hw = &adapter->hw;
912 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
913 IGB_PTP_TX_TIMEOUT);
914
915 if (!adapter->ptp_tx_skb)
916 return;
917
918 if (!test_bit(__IGB_PTP_TX_IN_PROGRESS, &adapter->state))
919 return;
920
921 /* If we haven't received a timestamp within the timeout, it is
922 * reasonable to assume that it will never occur, so we can unlock the
923 * timestamp bit when this occurs.
924 */
925 if (timeout) {
926 cancel_work_sync(&adapter->ptp_tx_work);
927 dev_kfree_skb_any(adapter->ptp_tx_skb);
928 adapter->ptp_tx_skb = NULL;
929 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
930 adapter->tx_hwtstamp_timeouts++;
931 /* Clear the tx valid bit in TSYNCTXCTL register to enable
932 * interrupt
933 */
934 rd32(E1000_TXSTMPH);
935 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
936 }
937}
938
939/**
940 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
941 * @adapter: Board private structure.
942 *
943 * If we were asked to do hardware stamping and such a time stamp is
944 * available, then it must have been for this skb here because we only
945 * allow only one such packet into the queue.
946 **/
947static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)
948{
949 struct sk_buff *skb = adapter->ptp_tx_skb;
950 struct e1000_hw *hw = &adapter->hw;
951 struct skb_shared_hwtstamps shhwtstamps;
952 u64 regval;
953 int adjust = 0;
954
955 regval = rd32(E1000_TXSTMPL);
956 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
957
958 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
959 /* adjust timestamp for the TX latency based on link speed */
960 if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
961 switch (adapter->link_speed) {
962 case SPEED_10:
963 adjust = IGB_I210_TX_LATENCY_10;
964 break;
965 case SPEED_100:
966 adjust = IGB_I210_TX_LATENCY_100;
967 break;
968 case SPEED_1000:
969 adjust = IGB_I210_TX_LATENCY_1000;
970 break;
971 }
972 }
973
974 shhwtstamps.hwtstamp =
975 ktime_add_ns(shhwtstamps.hwtstamp, adjust);
976
977 /* Clear the lock early before calling skb_tstamp_tx so that
978 * applications are not woken up before the lock bit is clear. We use
979 * a copy of the skb pointer to ensure other threads can't change it
980 * while we're notifying the stack.
981 */
982 adapter->ptp_tx_skb = NULL;
983 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
984
985 /* Notify the stack and free the skb after we've unlocked */
986 skb_tstamp_tx(skb, &shhwtstamps);
987 dev_kfree_skb_any(skb);
988}
989
990/**
991 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
992 * @q_vector: Pointer to interrupt specific structure
993 * @va: Pointer to address containing Rx buffer
994 * @timestamp: Pointer where timestamp will be stored
995 *
996 * This function is meant to retrieve a timestamp from the first buffer of an
997 * incoming frame. The value is stored in little endian format starting on
998 * byte 8
999 *
1000 * Returns: The timestamp header length or 0 if not available
1001 **/
1002int igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va,
1003 ktime_t *timestamp)
1004{
1005 struct igb_adapter *adapter = q_vector->adapter;
1006 struct e1000_hw *hw = &adapter->hw;
1007 struct skb_shared_hwtstamps ts;
1008 __le64 *regval = (__le64 *)va;
1009 int adjust = 0;
1010
1011 if (!(adapter->ptp_flags & IGB_PTP_ENABLED))
1012 return 0;
1013
1014 /* The timestamp is recorded in little endian format.
1015 * DWORD: 0 1 2 3
1016 * Field: Reserved Reserved SYSTIML SYSTIMH
1017 */
1018
1019 /* check reserved dwords are zero, be/le doesn't matter for zero */
1020 if (regval[0])
1021 return 0;
1022
1023 igb_ptp_systim_to_hwtstamp(adapter, &ts, le64_to_cpu(regval[1]));
1024
1025 /* adjust timestamp for the RX latency based on link speed */
1026 if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1027 switch (adapter->link_speed) {
1028 case SPEED_10:
1029 adjust = IGB_I210_RX_LATENCY_10;
1030 break;
1031 case SPEED_100:
1032 adjust = IGB_I210_RX_LATENCY_100;
1033 break;
1034 case SPEED_1000:
1035 adjust = IGB_I210_RX_LATENCY_1000;
1036 break;
1037 }
1038 }
1039
1040 *timestamp = ktime_sub_ns(ts.hwtstamp, adjust);
1041
1042 return IGB_TS_HDR_LEN;
1043}
1044
1045/**
1046 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
1047 * @q_vector: Pointer to interrupt specific structure
1048 * @skb: Buffer containing timestamp and packet
1049 *
1050 * This function is meant to retrieve a timestamp from the internal registers
1051 * of the adapter and store it in the skb.
1052 **/
1053void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb)
1054{
1055 struct igb_adapter *adapter = q_vector->adapter;
1056 struct e1000_hw *hw = &adapter->hw;
1057 int adjust = 0;
1058 u64 regval;
1059
1060 if (!(adapter->ptp_flags & IGB_PTP_ENABLED))
1061 return;
1062
1063 /* If this bit is set, then the RX registers contain the time stamp. No
1064 * other packet will be time stamped until we read these registers, so
1065 * read the registers to make them available again. Because only one
1066 * packet can be time stamped at a time, we know that the register
1067 * values must belong to this one here and therefore we don't need to
1068 * compare any of the additional attributes stored for it.
1069 *
1070 * If nothing went wrong, then it should have a shared tx_flags that we
1071 * can turn into a skb_shared_hwtstamps.
1072 */
1073 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
1074 return;
1075
1076 regval = rd32(E1000_RXSTMPL);
1077 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
1078
1079 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
1080
1081 /* adjust timestamp for the RX latency based on link speed */
1082 if (adapter->hw.mac.type == e1000_i210) {
1083 switch (adapter->link_speed) {
1084 case SPEED_10:
1085 adjust = IGB_I210_RX_LATENCY_10;
1086 break;
1087 case SPEED_100:
1088 adjust = IGB_I210_RX_LATENCY_100;
1089 break;
1090 case SPEED_1000:
1091 adjust = IGB_I210_RX_LATENCY_1000;
1092 break;
1093 }
1094 }
1095 skb_hwtstamps(skb)->hwtstamp =
1096 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust);
1097
1098 /* Update the last_rx_timestamp timer in order to enable watchdog check
1099 * for error case of latched timestamp on a dropped packet.
1100 */
1101 adapter->last_rx_timestamp = jiffies;
1102}
1103
1104/**
1105 * igb_ptp_get_ts_config - get hardware time stamping config
1106 * @netdev: netdev struct
1107 * @ifr: interface struct
1108 *
1109 * Get the hwtstamp_config settings to return to the user. Rather than attempt
1110 * to deconstruct the settings from the registers, just return a shadow copy
1111 * of the last known settings.
1112 **/
1113int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
1114{
1115 struct igb_adapter *adapter = netdev_priv(netdev);
1116 struct hwtstamp_config *config = &adapter->tstamp_config;
1117
1118 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
1119 -EFAULT : 0;
1120}
1121
1122/**
1123 * igb_ptp_set_timestamp_mode - setup hardware for timestamping
1124 * @adapter: networking device structure
1125 * @config: hwtstamp configuration
1126 *
1127 * Outgoing time stamping can be enabled and disabled. Play nice and
1128 * disable it when requested, although it shouldn't case any overhead
1129 * when no packet needs it. At most one packet in the queue may be
1130 * marked for time stamping, otherwise it would be impossible to tell
1131 * for sure to which packet the hardware time stamp belongs.
1132 *
1133 * Incoming time stamping has to be configured via the hardware
1134 * filters. Not all combinations are supported, in particular event
1135 * type has to be specified. Matching the kind of event packet is
1136 * not supported, with the exception of "all V2 events regardless of
1137 * level 2 or 4".
1138 */
1139static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter,
1140 struct hwtstamp_config *config)
1141{
1142 struct e1000_hw *hw = &adapter->hw;
1143 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
1144 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
1145 u32 tsync_rx_cfg = 0;
1146 bool is_l4 = false;
1147 bool is_l2 = false;
1148 u32 regval;
1149
1150 switch (config->tx_type) {
1151 case HWTSTAMP_TX_OFF:
1152 tsync_tx_ctl = 0;
1153 break;
1154 case HWTSTAMP_TX_ON:
1155 break;
1156 default:
1157 return -ERANGE;
1158 }
1159
1160 switch (config->rx_filter) {
1161 case HWTSTAMP_FILTER_NONE:
1162 tsync_rx_ctl = 0;
1163 break;
1164 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1165 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
1166 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
1167 is_l4 = true;
1168 break;
1169 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1170 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
1171 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
1172 is_l4 = true;
1173 break;
1174 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1175 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1176 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1177 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1178 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1179 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1180 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1181 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1182 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1183 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
1184 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1185 is_l2 = true;
1186 is_l4 = true;
1187 break;
1188 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1189 case HWTSTAMP_FILTER_NTP_ALL:
1190 case HWTSTAMP_FILTER_ALL:
1191 /* 82576 cannot timestamp all packets, which it needs to do to
1192 * support both V1 Sync and Delay_Req messages
1193 */
1194 if (hw->mac.type != e1000_82576) {
1195 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
1196 config->rx_filter = HWTSTAMP_FILTER_ALL;
1197 break;
1198 }
1199 fallthrough;
1200 default:
1201 config->rx_filter = HWTSTAMP_FILTER_NONE;
1202 return -ERANGE;
1203 }
1204
1205 if (hw->mac.type == e1000_82575) {
1206 if (tsync_rx_ctl | tsync_tx_ctl)
1207 return -EINVAL;
1208 return 0;
1209 }
1210
1211 /* Per-packet timestamping only works if all packets are
1212 * timestamped, so enable timestamping in all packets as
1213 * long as one Rx filter was configured.
1214 */
1215 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
1216 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
1217 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
1218 config->rx_filter = HWTSTAMP_FILTER_ALL;
1219 is_l2 = true;
1220 is_l4 = true;
1221
1222 if ((hw->mac.type == e1000_i210) ||
1223 (hw->mac.type == e1000_i211)) {
1224 regval = rd32(E1000_RXPBS);
1225 regval |= E1000_RXPBS_CFG_TS_EN;
1226 wr32(E1000_RXPBS, regval);
1227 }
1228 }
1229
1230 /* enable/disable TX */
1231 regval = rd32(E1000_TSYNCTXCTL);
1232 regval &= ~E1000_TSYNCTXCTL_ENABLED;
1233 regval |= tsync_tx_ctl;
1234 wr32(E1000_TSYNCTXCTL, regval);
1235
1236 /* enable/disable RX */
1237 regval = rd32(E1000_TSYNCRXCTL);
1238 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
1239 regval |= tsync_rx_ctl;
1240 wr32(E1000_TSYNCRXCTL, regval);
1241
1242 /* define which PTP packets are time stamped */
1243 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
1244
1245 /* define ethertype filter for timestamped packets */
1246 if (is_l2)
1247 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588),
1248 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
1249 E1000_ETQF_1588 | /* enable timestamping */
1250 ETH_P_1588)); /* 1588 eth protocol type */
1251 else
1252 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 0);
1253
1254 /* L4 Queue Filter[3]: filter by destination port and protocol */
1255 if (is_l4) {
1256 u32 ftqf = (IPPROTO_UDP /* UDP */
1257 | E1000_FTQF_VF_BP /* VF not compared */
1258 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
1259 | E1000_FTQF_MASK); /* mask all inputs */
1260 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
1261
1262 wr32(E1000_IMIR(3), (__force unsigned int)htons(PTP_EV_PORT));
1263 wr32(E1000_IMIREXT(3),
1264 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
1265 if (hw->mac.type == e1000_82576) {
1266 /* enable source port check */
1267 wr32(E1000_SPQF(3), (__force unsigned int)htons(PTP_EV_PORT));
1268 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
1269 }
1270 wr32(E1000_FTQF(3), ftqf);
1271 } else {
1272 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
1273 }
1274 wrfl();
1275
1276 /* clear TX/RX time stamp registers, just to be sure */
1277 regval = rd32(E1000_TXSTMPL);
1278 regval = rd32(E1000_TXSTMPH);
1279 regval = rd32(E1000_RXSTMPL);
1280 regval = rd32(E1000_RXSTMPH);
1281
1282 return 0;
1283}
1284
1285/**
1286 * igb_ptp_set_ts_config - set hardware time stamping config
1287 * @netdev: netdev struct
1288 * @ifr: interface struct
1289 *
1290 **/
1291int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
1292{
1293 struct igb_adapter *adapter = netdev_priv(netdev);
1294 struct hwtstamp_config config;
1295 int err;
1296
1297 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1298 return -EFAULT;
1299
1300 err = igb_ptp_set_timestamp_mode(adapter, &config);
1301 if (err)
1302 return err;
1303
1304 /* save these settings for future reference */
1305 memcpy(&adapter->tstamp_config, &config,
1306 sizeof(adapter->tstamp_config));
1307
1308 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1309 -EFAULT : 0;
1310}
1311
1312/**
1313 * igb_ptp_init - Initialize PTP functionality
1314 * @adapter: Board private structure
1315 *
1316 * This function is called at device probe to initialize the PTP
1317 * functionality.
1318 */
1319void igb_ptp_init(struct igb_adapter *adapter)
1320{
1321 struct e1000_hw *hw = &adapter->hw;
1322 struct net_device *netdev = adapter->netdev;
1323
1324 switch (hw->mac.type) {
1325 case e1000_82576:
1326 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1327 adapter->ptp_caps.owner = THIS_MODULE;
1328 adapter->ptp_caps.max_adj = 999999881;
1329 adapter->ptp_caps.n_ext_ts = 0;
1330 adapter->ptp_caps.pps = 0;
1331 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82576;
1332 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1333 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_82576;
1334 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1335 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1336 adapter->cc.read = igb_ptp_read_82576;
1337 adapter->cc.mask = CYCLECOUNTER_MASK(64);
1338 adapter->cc.mult = 1;
1339 adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
1340 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK;
1341 break;
1342 case e1000_82580:
1343 case e1000_i354:
1344 case e1000_i350:
1345 igb_ptp_sdp_init(adapter);
1346 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1347 adapter->ptp_caps.owner = THIS_MODULE;
1348 adapter->ptp_caps.max_adj = 62499999;
1349 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS;
1350 adapter->ptp_caps.n_per_out = IGB_N_PEROUT;
1351 adapter->ptp_caps.n_pins = IGB_N_SDP;
1352 adapter->ptp_caps.pps = 0;
1353 adapter->ptp_caps.pin_config = adapter->sdp_config;
1354 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580;
1355 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1356 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_82580;
1357 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1358 adapter->ptp_caps.enable = igb_ptp_feature_enable_82580;
1359 adapter->ptp_caps.verify = igb_ptp_verify_pin;
1360 adapter->cc.read = igb_ptp_read_82580;
1361 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580);
1362 adapter->cc.mult = 1;
1363 adapter->cc.shift = 0;
1364 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK;
1365 break;
1366 case e1000_i210:
1367 case e1000_i211:
1368 igb_ptp_sdp_init(adapter);
1369 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1370 adapter->ptp_caps.owner = THIS_MODULE;
1371 adapter->ptp_caps.max_adj = 62499999;
1372 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS;
1373 adapter->ptp_caps.n_per_out = IGB_N_PEROUT;
1374 adapter->ptp_caps.n_pins = IGB_N_SDP;
1375 adapter->ptp_caps.pps = 1;
1376 adapter->ptp_caps.pin_config = adapter->sdp_config;
1377 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580;
1378 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;
1379 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_i210;
1380 adapter->ptp_caps.settime64 = igb_ptp_settime_i210;
1381 adapter->ptp_caps.enable = igb_ptp_feature_enable_i210;
1382 adapter->ptp_caps.verify = igb_ptp_verify_pin;
1383 break;
1384 default:
1385 adapter->ptp_clock = NULL;
1386 return;
1387 }
1388
1389 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1390 &adapter->pdev->dev);
1391 if (IS_ERR(adapter->ptp_clock)) {
1392 adapter->ptp_clock = NULL;
1393 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
1394 } else if (adapter->ptp_clock) {
1395 dev_info(&adapter->pdev->dev, "added PHC on %s\n",
1396 adapter->netdev->name);
1397 adapter->ptp_flags |= IGB_PTP_ENABLED;
1398
1399 spin_lock_init(&adapter->tmreg_lock);
1400 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);
1401
1402 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1403 INIT_DELAYED_WORK(&adapter->ptp_overflow_work,
1404 igb_ptp_overflow_check);
1405
1406 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1407 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1408
1409 igb_ptp_reset(adapter);
1410 }
1411}
1412
1413/**
1414 * igb_ptp_sdp_init - utility function which inits the SDP config structs
1415 * @adapter: Board private structure.
1416 **/
1417void igb_ptp_sdp_init(struct igb_adapter *adapter)
1418{
1419 int i;
1420
1421 for (i = 0; i < IGB_N_SDP; i++) {
1422 struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
1423
1424 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
1425 ppd->index = i;
1426 ppd->func = PTP_PF_NONE;
1427 }
1428}
1429
1430/**
1431 * igb_ptp_suspend - Disable PTP work items and prepare for suspend
1432 * @adapter: Board private structure
1433 *
1434 * This function stops the overflow check work and PTP Tx timestamp work, and
1435 * will prepare the device for OS suspend.
1436 */
1437void igb_ptp_suspend(struct igb_adapter *adapter)
1438{
1439 if (!(adapter->ptp_flags & IGB_PTP_ENABLED))
1440 return;
1441
1442 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1443 cancel_delayed_work_sync(&adapter->ptp_overflow_work);
1444
1445 cancel_work_sync(&adapter->ptp_tx_work);
1446 if (adapter->ptp_tx_skb) {
1447 dev_kfree_skb_any(adapter->ptp_tx_skb);
1448 adapter->ptp_tx_skb = NULL;
1449 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
1450 }
1451}
1452
1453/**
1454 * igb_ptp_stop - Disable PTP device and stop the overflow check.
1455 * @adapter: Board private structure.
1456 *
1457 * This function stops the PTP support and cancels the delayed work.
1458 **/
1459void igb_ptp_stop(struct igb_adapter *adapter)
1460{
1461 igb_ptp_suspend(adapter);
1462
1463 if (adapter->ptp_clock) {
1464 ptp_clock_unregister(adapter->ptp_clock);
1465 dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
1466 adapter->netdev->name);
1467 adapter->ptp_flags &= ~IGB_PTP_ENABLED;
1468 }
1469}
1470
1471/**
1472 * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
1473 * @adapter: Board private structure.
1474 *
1475 * This function handles the reset work required to re-enable the PTP device.
1476 **/
1477void igb_ptp_reset(struct igb_adapter *adapter)
1478{
1479 struct e1000_hw *hw = &adapter->hw;
1480 unsigned long flags;
1481
1482 /* reset the tstamp_config */
1483 igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1484
1485 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1486
1487 switch (adapter->hw.mac.type) {
1488 case e1000_82576:
1489 /* Dial the nominal frequency. */
1490 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1491 break;
1492 case e1000_82580:
1493 case e1000_i354:
1494 case e1000_i350:
1495 case e1000_i210:
1496 case e1000_i211:
1497 wr32(E1000_TSAUXC, 0x0);
1498 wr32(E1000_TSSDP, 0x0);
1499 wr32(E1000_TSIM,
1500 TSYNC_INTERRUPTS |
1501 (adapter->pps_sys_wrap_on ? TSINTR_SYS_WRAP : 0));
1502 wr32(E1000_IMS, E1000_IMS_TS);
1503 break;
1504 default:
1505 /* No work to do. */
1506 goto out;
1507 }
1508
1509 /* Re-initialize the timer. */
1510 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1511 struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1512
1513 igb_ptp_write_i210(adapter, &ts);
1514 } else {
1515 timecounter_init(&adapter->tc, &adapter->cc,
1516 ktime_to_ns(ktime_get_real()));
1517 }
1518out:
1519 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1520
1521 wrfl();
1522
1523 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1524 schedule_delayed_work(&adapter->ptp_overflow_work,
1525 IGB_SYSTIM_OVERFLOW_PERIOD);
1526}
1// SPDX-License-Identifier: GPL-2.0+
2/* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
3 *
4 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <linux/module.h>
20#include <linux/device.h>
21#include <linux/pci.h>
22#include <linux/ptp_classify.h>
23
24#include "igb.h"
25
26#define INCVALUE_MASK 0x7fffffff
27#define ISGN 0x80000000
28
29/* The 82580 timesync updates the system timer every 8ns by 8ns,
30 * and this update value cannot be reprogrammed.
31 *
32 * Neither the 82576 nor the 82580 offer registers wide enough to hold
33 * nanoseconds time values for very long. For the 82580, SYSTIM always
34 * counts nanoseconds, but the upper 24 bits are not available. The
35 * frequency is adjusted by changing the 32 bit fractional nanoseconds
36 * register, TIMINCA.
37 *
38 * For the 82576, the SYSTIM register time unit is affect by the
39 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
40 * field are needed to provide the nominal 16 nanosecond period,
41 * leaving 19 bits for fractional nanoseconds.
42 *
43 * We scale the NIC clock cycle by a large factor so that relatively
44 * small clock corrections can be added or subtracted at each clock
45 * tick. The drawbacks of a large factor are a) that the clock
46 * register overflows more quickly (not such a big deal) and b) that
47 * the increment per tick has to fit into 24 bits. As a result we
48 * need to use a shift of 19 so we can fit a value of 16 into the
49 * TIMINCA register.
50 *
51 *
52 * SYSTIMH SYSTIML
53 * +--------------+ +---+---+------+
54 * 82576 | 32 | | 8 | 5 | 19 |
55 * +--------------+ +---+---+------+
56 * \________ 45 bits _______/ fract
57 *
58 * +----------+---+ +--------------+
59 * 82580 | 24 | 8 | | 32 |
60 * +----------+---+ +--------------+
61 * reserved \______ 40 bits _____/
62 *
63 *
64 * The 45 bit 82576 SYSTIM overflows every
65 * 2^45 * 10^-9 / 3600 = 9.77 hours.
66 *
67 * The 40 bit 82580 SYSTIM overflows every
68 * 2^40 * 10^-9 / 60 = 18.3 minutes.
69 */
70
71#define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9)
72#define IGB_PTP_TX_TIMEOUT (HZ * 15)
73#define INCPERIOD_82576 BIT(E1000_TIMINCA_16NS_SHIFT)
74#define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0)
75#define INCVALUE_82576 (16u << IGB_82576_TSYNC_SHIFT)
76#define IGB_NBITS_82580 40
77
78static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
79
80/* SYSTIM read access for the 82576 */
81static u64 igb_ptp_read_82576(const struct cyclecounter *cc)
82{
83 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
84 struct e1000_hw *hw = &igb->hw;
85 u64 val;
86 u32 lo, hi;
87
88 lo = rd32(E1000_SYSTIML);
89 hi = rd32(E1000_SYSTIMH);
90
91 val = ((u64) hi) << 32;
92 val |= lo;
93
94 return val;
95}
96
97/* SYSTIM read access for the 82580 */
98static u64 igb_ptp_read_82580(const struct cyclecounter *cc)
99{
100 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
101 struct e1000_hw *hw = &igb->hw;
102 u32 lo, hi;
103 u64 val;
104
105 /* The timestamp latches on lowest register read. For the 82580
106 * the lowest register is SYSTIMR instead of SYSTIML. However we only
107 * need to provide nanosecond resolution, so we just ignore it.
108 */
109 rd32(E1000_SYSTIMR);
110 lo = rd32(E1000_SYSTIML);
111 hi = rd32(E1000_SYSTIMH);
112
113 val = ((u64) hi) << 32;
114 val |= lo;
115
116 return val;
117}
118
119/* SYSTIM read access for I210/I211 */
120static void igb_ptp_read_i210(struct igb_adapter *adapter,
121 struct timespec64 *ts)
122{
123 struct e1000_hw *hw = &adapter->hw;
124 u32 sec, nsec;
125
126 /* The timestamp latches on lowest register read. For I210/I211, the
127 * lowest register is SYSTIMR. Since we only need to provide nanosecond
128 * resolution, we can ignore it.
129 */
130 rd32(E1000_SYSTIMR);
131 nsec = rd32(E1000_SYSTIML);
132 sec = rd32(E1000_SYSTIMH);
133
134 ts->tv_sec = sec;
135 ts->tv_nsec = nsec;
136}
137
138static void igb_ptp_write_i210(struct igb_adapter *adapter,
139 const struct timespec64 *ts)
140{
141 struct e1000_hw *hw = &adapter->hw;
142
143 /* Writing the SYSTIMR register is not necessary as it only provides
144 * sub-nanosecond resolution.
145 */
146 wr32(E1000_SYSTIML, ts->tv_nsec);
147 wr32(E1000_SYSTIMH, (u32)ts->tv_sec);
148}
149
150/**
151 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
152 * @adapter: board private structure
153 * @hwtstamps: timestamp structure to update
154 * @systim: unsigned 64bit system time value.
155 *
156 * We need to convert the system time value stored in the RX/TXSTMP registers
157 * into a hwtstamp which can be used by the upper level timestamping functions.
158 *
159 * The 'tmreg_lock' spinlock is used to protect the consistency of the
160 * system time value. This is needed because reading the 64 bit time
161 * value involves reading two (or three) 32 bit registers. The first
162 * read latches the value. Ditto for writing.
163 *
164 * In addition, here have extended the system time with an overflow
165 * counter in software.
166 **/
167static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,
168 struct skb_shared_hwtstamps *hwtstamps,
169 u64 systim)
170{
171 unsigned long flags;
172 u64 ns;
173
174 switch (adapter->hw.mac.type) {
175 case e1000_82576:
176 case e1000_82580:
177 case e1000_i354:
178 case e1000_i350:
179 spin_lock_irqsave(&adapter->tmreg_lock, flags);
180
181 ns = timecounter_cyc2time(&adapter->tc, systim);
182
183 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
184
185 memset(hwtstamps, 0, sizeof(*hwtstamps));
186 hwtstamps->hwtstamp = ns_to_ktime(ns);
187 break;
188 case e1000_i210:
189 case e1000_i211:
190 memset(hwtstamps, 0, sizeof(*hwtstamps));
191 /* Upper 32 bits contain s, lower 32 bits contain ns. */
192 hwtstamps->hwtstamp = ktime_set(systim >> 32,
193 systim & 0xFFFFFFFF);
194 break;
195 default:
196 break;
197 }
198}
199
200/* PTP clock operations */
201static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb)
202{
203 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
204 ptp_caps);
205 struct e1000_hw *hw = &igb->hw;
206 int neg_adj = 0;
207 u64 rate;
208 u32 incvalue;
209
210 if (ppb < 0) {
211 neg_adj = 1;
212 ppb = -ppb;
213 }
214 rate = ppb;
215 rate <<= 14;
216 rate = div_u64(rate, 1953125);
217
218 incvalue = 16 << IGB_82576_TSYNC_SHIFT;
219
220 if (neg_adj)
221 incvalue -= rate;
222 else
223 incvalue += rate;
224
225 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
226
227 return 0;
228}
229
230static int igb_ptp_adjfine_82580(struct ptp_clock_info *ptp, long scaled_ppm)
231{
232 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
233 ptp_caps);
234 struct e1000_hw *hw = &igb->hw;
235 int neg_adj = 0;
236 u64 rate;
237 u32 inca;
238
239 if (scaled_ppm < 0) {
240 neg_adj = 1;
241 scaled_ppm = -scaled_ppm;
242 }
243 rate = scaled_ppm;
244 rate <<= 13;
245 rate = div_u64(rate, 15625);
246
247 inca = rate & INCVALUE_MASK;
248 if (neg_adj)
249 inca |= ISGN;
250
251 wr32(E1000_TIMINCA, inca);
252
253 return 0;
254}
255
256static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta)
257{
258 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
259 ptp_caps);
260 unsigned long flags;
261
262 spin_lock_irqsave(&igb->tmreg_lock, flags);
263 timecounter_adjtime(&igb->tc, delta);
264 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
265
266 return 0;
267}
268
269static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta)
270{
271 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
272 ptp_caps);
273 unsigned long flags;
274 struct timespec64 now, then = ns_to_timespec64(delta);
275
276 spin_lock_irqsave(&igb->tmreg_lock, flags);
277
278 igb_ptp_read_i210(igb, &now);
279 now = timespec64_add(now, then);
280 igb_ptp_write_i210(igb, (const struct timespec64 *)&now);
281
282 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
283
284 return 0;
285}
286
287static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp,
288 struct timespec64 *ts)
289{
290 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
291 ptp_caps);
292 unsigned long flags;
293 u64 ns;
294
295 spin_lock_irqsave(&igb->tmreg_lock, flags);
296
297 ns = timecounter_read(&igb->tc);
298
299 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
300
301 *ts = ns_to_timespec64(ns);
302
303 return 0;
304}
305
306static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp,
307 struct timespec64 *ts)
308{
309 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
310 ptp_caps);
311 unsigned long flags;
312
313 spin_lock_irqsave(&igb->tmreg_lock, flags);
314
315 igb_ptp_read_i210(igb, ts);
316
317 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
318
319 return 0;
320}
321
322static int igb_ptp_settime_82576(struct ptp_clock_info *ptp,
323 const struct timespec64 *ts)
324{
325 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
326 ptp_caps);
327 unsigned long flags;
328 u64 ns;
329
330 ns = timespec64_to_ns(ts);
331
332 spin_lock_irqsave(&igb->tmreg_lock, flags);
333
334 timecounter_init(&igb->tc, &igb->cc, ns);
335
336 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
337
338 return 0;
339}
340
341static int igb_ptp_settime_i210(struct ptp_clock_info *ptp,
342 const struct timespec64 *ts)
343{
344 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
345 ptp_caps);
346 unsigned long flags;
347
348 spin_lock_irqsave(&igb->tmreg_lock, flags);
349
350 igb_ptp_write_i210(igb, ts);
351
352 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
353
354 return 0;
355}
356
357static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
358{
359 u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
360 static const u32 mask[IGB_N_SDP] = {
361 E1000_CTRL_SDP0_DIR,
362 E1000_CTRL_SDP1_DIR,
363 E1000_CTRL_EXT_SDP2_DIR,
364 E1000_CTRL_EXT_SDP3_DIR,
365 };
366
367 if (input)
368 *ptr &= ~mask[pin];
369 else
370 *ptr |= mask[pin];
371}
372
373static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin)
374{
375 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
376 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
377 };
378 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
379 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
380 };
381 static const u32 ts_sdp_en[IGB_N_SDP] = {
382 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
383 };
384 struct e1000_hw *hw = &igb->hw;
385 u32 ctrl, ctrl_ext, tssdp = 0;
386
387 ctrl = rd32(E1000_CTRL);
388 ctrl_ext = rd32(E1000_CTRL_EXT);
389 tssdp = rd32(E1000_TSSDP);
390
391 igb_pin_direction(pin, 1, &ctrl, &ctrl_ext);
392
393 /* Make sure this pin is not enabled as an output. */
394 tssdp &= ~ts_sdp_en[pin];
395
396 if (chan == 1) {
397 tssdp &= ~AUX1_SEL_SDP3;
398 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN;
399 } else {
400 tssdp &= ~AUX0_SEL_SDP3;
401 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN;
402 }
403
404 wr32(E1000_TSSDP, tssdp);
405 wr32(E1000_CTRL, ctrl);
406 wr32(E1000_CTRL_EXT, ctrl_ext);
407}
408
409static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq)
410{
411 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
412 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
413 };
414 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
415 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
416 };
417 static const u32 ts_sdp_en[IGB_N_SDP] = {
418 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
419 };
420 static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = {
421 TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0,
422 TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0,
423 };
424 static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = {
425 TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1,
426 TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1,
427 };
428 static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = {
429 TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0,
430 TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0,
431 };
432 static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = {
433 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
434 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
435 };
436 static const u32 ts_sdp_sel_clr[IGB_N_SDP] = {
437 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
438 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
439 };
440 struct e1000_hw *hw = &igb->hw;
441 u32 ctrl, ctrl_ext, tssdp = 0;
442
443 ctrl = rd32(E1000_CTRL);
444 ctrl_ext = rd32(E1000_CTRL_EXT);
445 tssdp = rd32(E1000_TSSDP);
446
447 igb_pin_direction(pin, 0, &ctrl, &ctrl_ext);
448
449 /* Make sure this pin is not enabled as an input. */
450 if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin])
451 tssdp &= ~AUX0_TS_SDP_EN;
452
453 if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin])
454 tssdp &= ~AUX1_TS_SDP_EN;
455
456 tssdp &= ~ts_sdp_sel_clr[pin];
457 if (freq) {
458 if (chan == 1)
459 tssdp |= ts_sdp_sel_fc1[pin];
460 else
461 tssdp |= ts_sdp_sel_fc0[pin];
462 } else {
463 if (chan == 1)
464 tssdp |= ts_sdp_sel_tt1[pin];
465 else
466 tssdp |= ts_sdp_sel_tt0[pin];
467 }
468 tssdp |= ts_sdp_en[pin];
469
470 wr32(E1000_TSSDP, tssdp);
471 wr32(E1000_CTRL, ctrl);
472 wr32(E1000_CTRL_EXT, ctrl_ext);
473}
474
475static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp,
476 struct ptp_clock_request *rq, int on)
477{
478 struct igb_adapter *igb =
479 container_of(ptp, struct igb_adapter, ptp_caps);
480 struct e1000_hw *hw = &igb->hw;
481 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
482 unsigned long flags;
483 struct timespec64 ts;
484 int use_freq = 0, pin = -1;
485 s64 ns;
486
487 switch (rq->type) {
488 case PTP_CLK_REQ_EXTTS:
489 if (on) {
490 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS,
491 rq->extts.index);
492 if (pin < 0)
493 return -EBUSY;
494 }
495 if (rq->extts.index == 1) {
496 tsauxc_mask = TSAUXC_EN_TS1;
497 tsim_mask = TSINTR_AUTT1;
498 } else {
499 tsauxc_mask = TSAUXC_EN_TS0;
500 tsim_mask = TSINTR_AUTT0;
501 }
502 spin_lock_irqsave(&igb->tmreg_lock, flags);
503 tsauxc = rd32(E1000_TSAUXC);
504 tsim = rd32(E1000_TSIM);
505 if (on) {
506 igb_pin_extts(igb, rq->extts.index, pin);
507 tsauxc |= tsauxc_mask;
508 tsim |= tsim_mask;
509 } else {
510 tsauxc &= ~tsauxc_mask;
511 tsim &= ~tsim_mask;
512 }
513 wr32(E1000_TSAUXC, tsauxc);
514 wr32(E1000_TSIM, tsim);
515 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
516 return 0;
517
518 case PTP_CLK_REQ_PEROUT:
519 if (on) {
520 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT,
521 rq->perout.index);
522 if (pin < 0)
523 return -EBUSY;
524 }
525 ts.tv_sec = rq->perout.period.sec;
526 ts.tv_nsec = rq->perout.period.nsec;
527 ns = timespec64_to_ns(&ts);
528 ns = ns >> 1;
529 if (on && ((ns <= 70000000LL) || (ns == 125000000LL) ||
530 (ns == 250000000LL) || (ns == 500000000LL))) {
531 if (ns < 8LL)
532 return -EINVAL;
533 use_freq = 1;
534 }
535 ts = ns_to_timespec64(ns);
536 if (rq->perout.index == 1) {
537 if (use_freq) {
538 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1;
539 tsim_mask = 0;
540 } else {
541 tsauxc_mask = TSAUXC_EN_TT1;
542 tsim_mask = TSINTR_TT1;
543 }
544 trgttiml = E1000_TRGTTIML1;
545 trgttimh = E1000_TRGTTIMH1;
546 freqout = E1000_FREQOUT1;
547 } else {
548 if (use_freq) {
549 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0;
550 tsim_mask = 0;
551 } else {
552 tsauxc_mask = TSAUXC_EN_TT0;
553 tsim_mask = TSINTR_TT0;
554 }
555 trgttiml = E1000_TRGTTIML0;
556 trgttimh = E1000_TRGTTIMH0;
557 freqout = E1000_FREQOUT0;
558 }
559 spin_lock_irqsave(&igb->tmreg_lock, flags);
560 tsauxc = rd32(E1000_TSAUXC);
561 tsim = rd32(E1000_TSIM);
562 if (rq->perout.index == 1) {
563 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1);
564 tsim &= ~TSINTR_TT1;
565 } else {
566 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0);
567 tsim &= ~TSINTR_TT0;
568 }
569 if (on) {
570 int i = rq->perout.index;
571 igb_pin_perout(igb, i, pin, use_freq);
572 igb->perout[i].start.tv_sec = rq->perout.start.sec;
573 igb->perout[i].start.tv_nsec = rq->perout.start.nsec;
574 igb->perout[i].period.tv_sec = ts.tv_sec;
575 igb->perout[i].period.tv_nsec = ts.tv_nsec;
576 wr32(trgttimh, rq->perout.start.sec);
577 wr32(trgttiml, rq->perout.start.nsec);
578 if (use_freq)
579 wr32(freqout, ns);
580 tsauxc |= tsauxc_mask;
581 tsim |= tsim_mask;
582 }
583 wr32(E1000_TSAUXC, tsauxc);
584 wr32(E1000_TSIM, tsim);
585 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
586 return 0;
587
588 case PTP_CLK_REQ_PPS:
589 spin_lock_irqsave(&igb->tmreg_lock, flags);
590 tsim = rd32(E1000_TSIM);
591 if (on)
592 tsim |= TSINTR_SYS_WRAP;
593 else
594 tsim &= ~TSINTR_SYS_WRAP;
595 igb->pps_sys_wrap_on = !!on;
596 wr32(E1000_TSIM, tsim);
597 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
598 return 0;
599 }
600
601 return -EOPNOTSUPP;
602}
603
604static int igb_ptp_feature_enable(struct ptp_clock_info *ptp,
605 struct ptp_clock_request *rq, int on)
606{
607 return -EOPNOTSUPP;
608}
609
610static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
611 enum ptp_pin_function func, unsigned int chan)
612{
613 switch (func) {
614 case PTP_PF_NONE:
615 case PTP_PF_EXTTS:
616 case PTP_PF_PEROUT:
617 break;
618 case PTP_PF_PHYSYNC:
619 return -1;
620 }
621 return 0;
622}
623
624/**
625 * igb_ptp_tx_work
626 * @work: pointer to work struct
627 *
628 * This work function polls the TSYNCTXCTL valid bit to determine when a
629 * timestamp has been taken for the current stored skb.
630 **/
631static void igb_ptp_tx_work(struct work_struct *work)
632{
633 struct igb_adapter *adapter = container_of(work, struct igb_adapter,
634 ptp_tx_work);
635 struct e1000_hw *hw = &adapter->hw;
636 u32 tsynctxctl;
637
638 if (!adapter->ptp_tx_skb)
639 return;
640
641 if (time_is_before_jiffies(adapter->ptp_tx_start +
642 IGB_PTP_TX_TIMEOUT)) {
643 dev_kfree_skb_any(adapter->ptp_tx_skb);
644 adapter->ptp_tx_skb = NULL;
645 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
646 adapter->tx_hwtstamp_timeouts++;
647 /* Clear the tx valid bit in TSYNCTXCTL register to enable
648 * interrupt
649 */
650 rd32(E1000_TXSTMPH);
651 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
652 return;
653 }
654
655 tsynctxctl = rd32(E1000_TSYNCTXCTL);
656 if (tsynctxctl & E1000_TSYNCTXCTL_VALID)
657 igb_ptp_tx_hwtstamp(adapter);
658 else
659 /* reschedule to check later */
660 schedule_work(&adapter->ptp_tx_work);
661}
662
663static void igb_ptp_overflow_check(struct work_struct *work)
664{
665 struct igb_adapter *igb =
666 container_of(work, struct igb_adapter, ptp_overflow_work.work);
667 struct timespec64 ts;
668
669 igb->ptp_caps.gettime64(&igb->ptp_caps, &ts);
670
671 pr_debug("igb overflow check at %lld.%09lu\n",
672 (long long) ts.tv_sec, ts.tv_nsec);
673
674 schedule_delayed_work(&igb->ptp_overflow_work,
675 IGB_SYSTIM_OVERFLOW_PERIOD);
676}
677
678/**
679 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched
680 * @adapter: private network adapter structure
681 *
682 * This watchdog task is scheduled to detect error case where hardware has
683 * dropped an Rx packet that was timestamped when the ring is full. The
684 * particular error is rare but leaves the device in a state unable to timestamp
685 * any future packets.
686 **/
687void igb_ptp_rx_hang(struct igb_adapter *adapter)
688{
689 struct e1000_hw *hw = &adapter->hw;
690 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL);
691 unsigned long rx_event;
692
693 /* Other hardware uses per-packet timestamps */
694 if (hw->mac.type != e1000_82576)
695 return;
696
697 /* If we don't have a valid timestamp in the registers, just update the
698 * timeout counter and exit
699 */
700 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) {
701 adapter->last_rx_ptp_check = jiffies;
702 return;
703 }
704
705 /* Determine the most recent watchdog or rx_timestamp event */
706 rx_event = adapter->last_rx_ptp_check;
707 if (time_after(adapter->last_rx_timestamp, rx_event))
708 rx_event = adapter->last_rx_timestamp;
709
710 /* Only need to read the high RXSTMP register to clear the lock */
711 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
712 rd32(E1000_RXSTMPH);
713 adapter->last_rx_ptp_check = jiffies;
714 adapter->rx_hwtstamp_cleared++;
715 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n");
716 }
717}
718
719/**
720 * igb_ptp_tx_hang - detect error case where Tx timestamp never finishes
721 * @adapter: private network adapter structure
722 */
723void igb_ptp_tx_hang(struct igb_adapter *adapter)
724{
725 struct e1000_hw *hw = &adapter->hw;
726 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
727 IGB_PTP_TX_TIMEOUT);
728
729 if (!adapter->ptp_tx_skb)
730 return;
731
732 if (!test_bit(__IGB_PTP_TX_IN_PROGRESS, &adapter->state))
733 return;
734
735 /* If we haven't received a timestamp within the timeout, it is
736 * reasonable to assume that it will never occur, so we can unlock the
737 * timestamp bit when this occurs.
738 */
739 if (timeout) {
740 cancel_work_sync(&adapter->ptp_tx_work);
741 dev_kfree_skb_any(adapter->ptp_tx_skb);
742 adapter->ptp_tx_skb = NULL;
743 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
744 adapter->tx_hwtstamp_timeouts++;
745 /* Clear the tx valid bit in TSYNCTXCTL register to enable
746 * interrupt
747 */
748 rd32(E1000_TXSTMPH);
749 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
750 }
751}
752
753/**
754 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
755 * @adapter: Board private structure.
756 *
757 * If we were asked to do hardware stamping and such a time stamp is
758 * available, then it must have been for this skb here because we only
759 * allow only one such packet into the queue.
760 **/
761static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)
762{
763 struct sk_buff *skb = adapter->ptp_tx_skb;
764 struct e1000_hw *hw = &adapter->hw;
765 struct skb_shared_hwtstamps shhwtstamps;
766 u64 regval;
767 int adjust = 0;
768
769 regval = rd32(E1000_TXSTMPL);
770 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
771
772 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
773 /* adjust timestamp for the TX latency based on link speed */
774 if (adapter->hw.mac.type == e1000_i210) {
775 switch (adapter->link_speed) {
776 case SPEED_10:
777 adjust = IGB_I210_TX_LATENCY_10;
778 break;
779 case SPEED_100:
780 adjust = IGB_I210_TX_LATENCY_100;
781 break;
782 case SPEED_1000:
783 adjust = IGB_I210_TX_LATENCY_1000;
784 break;
785 }
786 }
787
788 shhwtstamps.hwtstamp =
789 ktime_add_ns(shhwtstamps.hwtstamp, adjust);
790
791 /* Clear the lock early before calling skb_tstamp_tx so that
792 * applications are not woken up before the lock bit is clear. We use
793 * a copy of the skb pointer to ensure other threads can't change it
794 * while we're notifying the stack.
795 */
796 adapter->ptp_tx_skb = NULL;
797 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
798
799 /* Notify the stack and free the skb after we've unlocked */
800 skb_tstamp_tx(skb, &shhwtstamps);
801 dev_kfree_skb_any(skb);
802}
803
804/**
805 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
806 * @q_vector: Pointer to interrupt specific structure
807 * @va: Pointer to address containing Rx buffer
808 * @skb: Buffer containing timestamp and packet
809 *
810 * This function is meant to retrieve a timestamp from the first buffer of an
811 * incoming frame. The value is stored in little endian format starting on
812 * byte 8.
813 **/
814void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va,
815 struct sk_buff *skb)
816{
817 __le64 *regval = (__le64 *)va;
818 struct igb_adapter *adapter = q_vector->adapter;
819 int adjust = 0;
820
821 /* The timestamp is recorded in little endian format.
822 * DWORD: 0 1 2 3
823 * Field: Reserved Reserved SYSTIML SYSTIMH
824 */
825 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb),
826 le64_to_cpu(regval[1]));
827
828 /* adjust timestamp for the RX latency based on link speed */
829 if (adapter->hw.mac.type == e1000_i210) {
830 switch (adapter->link_speed) {
831 case SPEED_10:
832 adjust = IGB_I210_RX_LATENCY_10;
833 break;
834 case SPEED_100:
835 adjust = IGB_I210_RX_LATENCY_100;
836 break;
837 case SPEED_1000:
838 adjust = IGB_I210_RX_LATENCY_1000;
839 break;
840 }
841 }
842 skb_hwtstamps(skb)->hwtstamp =
843 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust);
844}
845
846/**
847 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
848 * @q_vector: Pointer to interrupt specific structure
849 * @skb: Buffer containing timestamp and packet
850 *
851 * This function is meant to retrieve a timestamp from the internal registers
852 * of the adapter and store it in the skb.
853 **/
854void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
855 struct sk_buff *skb)
856{
857 struct igb_adapter *adapter = q_vector->adapter;
858 struct e1000_hw *hw = &adapter->hw;
859 u64 regval;
860 int adjust = 0;
861
862 /* If this bit is set, then the RX registers contain the time stamp. No
863 * other packet will be time stamped until we read these registers, so
864 * read the registers to make them available again. Because only one
865 * packet can be time stamped at a time, we know that the register
866 * values must belong to this one here and therefore we don't need to
867 * compare any of the additional attributes stored for it.
868 *
869 * If nothing went wrong, then it should have a shared tx_flags that we
870 * can turn into a skb_shared_hwtstamps.
871 */
872 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
873 return;
874
875 regval = rd32(E1000_RXSTMPL);
876 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
877
878 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
879
880 /* adjust timestamp for the RX latency based on link speed */
881 if (adapter->hw.mac.type == e1000_i210) {
882 switch (adapter->link_speed) {
883 case SPEED_10:
884 adjust = IGB_I210_RX_LATENCY_10;
885 break;
886 case SPEED_100:
887 adjust = IGB_I210_RX_LATENCY_100;
888 break;
889 case SPEED_1000:
890 adjust = IGB_I210_RX_LATENCY_1000;
891 break;
892 }
893 }
894 skb_hwtstamps(skb)->hwtstamp =
895 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust);
896
897 /* Update the last_rx_timestamp timer in order to enable watchdog check
898 * for error case of latched timestamp on a dropped packet.
899 */
900 adapter->last_rx_timestamp = jiffies;
901}
902
903/**
904 * igb_ptp_get_ts_config - get hardware time stamping config
905 * @netdev:
906 * @ifreq:
907 *
908 * Get the hwtstamp_config settings to return to the user. Rather than attempt
909 * to deconstruct the settings from the registers, just return a shadow copy
910 * of the last known settings.
911 **/
912int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
913{
914 struct igb_adapter *adapter = netdev_priv(netdev);
915 struct hwtstamp_config *config = &adapter->tstamp_config;
916
917 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
918 -EFAULT : 0;
919}
920
921/**
922 * igb_ptp_set_timestamp_mode - setup hardware for timestamping
923 * @adapter: networking device structure
924 * @config: hwtstamp configuration
925 *
926 * Outgoing time stamping can be enabled and disabled. Play nice and
927 * disable it when requested, although it shouldn't case any overhead
928 * when no packet needs it. At most one packet in the queue may be
929 * marked for time stamping, otherwise it would be impossible to tell
930 * for sure to which packet the hardware time stamp belongs.
931 *
932 * Incoming time stamping has to be configured via the hardware
933 * filters. Not all combinations are supported, in particular event
934 * type has to be specified. Matching the kind of event packet is
935 * not supported, with the exception of "all V2 events regardless of
936 * level 2 or 4".
937 */
938static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter,
939 struct hwtstamp_config *config)
940{
941 struct e1000_hw *hw = &adapter->hw;
942 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
943 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
944 u32 tsync_rx_cfg = 0;
945 bool is_l4 = false;
946 bool is_l2 = false;
947 u32 regval;
948
949 /* reserved for future extensions */
950 if (config->flags)
951 return -EINVAL;
952
953 switch (config->tx_type) {
954 case HWTSTAMP_TX_OFF:
955 tsync_tx_ctl = 0;
956 case HWTSTAMP_TX_ON:
957 break;
958 default:
959 return -ERANGE;
960 }
961
962 switch (config->rx_filter) {
963 case HWTSTAMP_FILTER_NONE:
964 tsync_rx_ctl = 0;
965 break;
966 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
967 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
968 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
969 is_l4 = true;
970 break;
971 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
972 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
973 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
974 is_l4 = true;
975 break;
976 case HWTSTAMP_FILTER_PTP_V2_EVENT:
977 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
978 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
979 case HWTSTAMP_FILTER_PTP_V2_SYNC:
980 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
981 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
982 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
983 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
984 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
985 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
986 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
987 is_l2 = true;
988 is_l4 = true;
989 break;
990 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
991 case HWTSTAMP_FILTER_NTP_ALL:
992 case HWTSTAMP_FILTER_ALL:
993 /* 82576 cannot timestamp all packets, which it needs to do to
994 * support both V1 Sync and Delay_Req messages
995 */
996 if (hw->mac.type != e1000_82576) {
997 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
998 config->rx_filter = HWTSTAMP_FILTER_ALL;
999 break;
1000 }
1001 /* fall through */
1002 default:
1003 config->rx_filter = HWTSTAMP_FILTER_NONE;
1004 return -ERANGE;
1005 }
1006
1007 if (hw->mac.type == e1000_82575) {
1008 if (tsync_rx_ctl | tsync_tx_ctl)
1009 return -EINVAL;
1010 return 0;
1011 }
1012
1013 /* Per-packet timestamping only works if all packets are
1014 * timestamped, so enable timestamping in all packets as
1015 * long as one Rx filter was configured.
1016 */
1017 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
1018 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
1019 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
1020 config->rx_filter = HWTSTAMP_FILTER_ALL;
1021 is_l2 = true;
1022 is_l4 = true;
1023
1024 if ((hw->mac.type == e1000_i210) ||
1025 (hw->mac.type == e1000_i211)) {
1026 regval = rd32(E1000_RXPBS);
1027 regval |= E1000_RXPBS_CFG_TS_EN;
1028 wr32(E1000_RXPBS, regval);
1029 }
1030 }
1031
1032 /* enable/disable TX */
1033 regval = rd32(E1000_TSYNCTXCTL);
1034 regval &= ~E1000_TSYNCTXCTL_ENABLED;
1035 regval |= tsync_tx_ctl;
1036 wr32(E1000_TSYNCTXCTL, regval);
1037
1038 /* enable/disable RX */
1039 regval = rd32(E1000_TSYNCRXCTL);
1040 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
1041 regval |= tsync_rx_ctl;
1042 wr32(E1000_TSYNCRXCTL, regval);
1043
1044 /* define which PTP packets are time stamped */
1045 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
1046
1047 /* define ethertype filter for timestamped packets */
1048 if (is_l2)
1049 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588),
1050 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
1051 E1000_ETQF_1588 | /* enable timestamping */
1052 ETH_P_1588)); /* 1588 eth protocol type */
1053 else
1054 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 0);
1055
1056 /* L4 Queue Filter[3]: filter by destination port and protocol */
1057 if (is_l4) {
1058 u32 ftqf = (IPPROTO_UDP /* UDP */
1059 | E1000_FTQF_VF_BP /* VF not compared */
1060 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
1061 | E1000_FTQF_MASK); /* mask all inputs */
1062 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
1063
1064 wr32(E1000_IMIR(3), htons(PTP_EV_PORT));
1065 wr32(E1000_IMIREXT(3),
1066 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
1067 if (hw->mac.type == e1000_82576) {
1068 /* enable source port check */
1069 wr32(E1000_SPQF(3), htons(PTP_EV_PORT));
1070 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
1071 }
1072 wr32(E1000_FTQF(3), ftqf);
1073 } else {
1074 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
1075 }
1076 wrfl();
1077
1078 /* clear TX/RX time stamp registers, just to be sure */
1079 regval = rd32(E1000_TXSTMPL);
1080 regval = rd32(E1000_TXSTMPH);
1081 regval = rd32(E1000_RXSTMPL);
1082 regval = rd32(E1000_RXSTMPH);
1083
1084 return 0;
1085}
1086
1087/**
1088 * igb_ptp_set_ts_config - set hardware time stamping config
1089 * @netdev:
1090 * @ifreq:
1091 *
1092 **/
1093int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
1094{
1095 struct igb_adapter *adapter = netdev_priv(netdev);
1096 struct hwtstamp_config config;
1097 int err;
1098
1099 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1100 return -EFAULT;
1101
1102 err = igb_ptp_set_timestamp_mode(adapter, &config);
1103 if (err)
1104 return err;
1105
1106 /* save these settings for future reference */
1107 memcpy(&adapter->tstamp_config, &config,
1108 sizeof(adapter->tstamp_config));
1109
1110 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1111 -EFAULT : 0;
1112}
1113
1114/**
1115 * igb_ptp_init - Initialize PTP functionality
1116 * @adapter: Board private structure
1117 *
1118 * This function is called at device probe to initialize the PTP
1119 * functionality.
1120 */
1121void igb_ptp_init(struct igb_adapter *adapter)
1122{
1123 struct e1000_hw *hw = &adapter->hw;
1124 struct net_device *netdev = adapter->netdev;
1125 int i;
1126
1127 switch (hw->mac.type) {
1128 case e1000_82576:
1129 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1130 adapter->ptp_caps.owner = THIS_MODULE;
1131 adapter->ptp_caps.max_adj = 999999881;
1132 adapter->ptp_caps.n_ext_ts = 0;
1133 adapter->ptp_caps.pps = 0;
1134 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576;
1135 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1136 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1137 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1138 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1139 adapter->cc.read = igb_ptp_read_82576;
1140 adapter->cc.mask = CYCLECOUNTER_MASK(64);
1141 adapter->cc.mult = 1;
1142 adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
1143 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK;
1144 break;
1145 case e1000_82580:
1146 case e1000_i354:
1147 case e1000_i350:
1148 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1149 adapter->ptp_caps.owner = THIS_MODULE;
1150 adapter->ptp_caps.max_adj = 62499999;
1151 adapter->ptp_caps.n_ext_ts = 0;
1152 adapter->ptp_caps.pps = 0;
1153 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580;
1154 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1155 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1156 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1157 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1158 adapter->cc.read = igb_ptp_read_82580;
1159 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580);
1160 adapter->cc.mult = 1;
1161 adapter->cc.shift = 0;
1162 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK;
1163 break;
1164 case e1000_i210:
1165 case e1000_i211:
1166 for (i = 0; i < IGB_N_SDP; i++) {
1167 struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
1168
1169 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
1170 ppd->index = i;
1171 ppd->func = PTP_PF_NONE;
1172 }
1173 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1174 adapter->ptp_caps.owner = THIS_MODULE;
1175 adapter->ptp_caps.max_adj = 62499999;
1176 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS;
1177 adapter->ptp_caps.n_per_out = IGB_N_PEROUT;
1178 adapter->ptp_caps.n_pins = IGB_N_SDP;
1179 adapter->ptp_caps.pps = 1;
1180 adapter->ptp_caps.pin_config = adapter->sdp_config;
1181 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580;
1182 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;
1183 adapter->ptp_caps.gettime64 = igb_ptp_gettime_i210;
1184 adapter->ptp_caps.settime64 = igb_ptp_settime_i210;
1185 adapter->ptp_caps.enable = igb_ptp_feature_enable_i210;
1186 adapter->ptp_caps.verify = igb_ptp_verify_pin;
1187 break;
1188 default:
1189 adapter->ptp_clock = NULL;
1190 return;
1191 }
1192
1193 spin_lock_init(&adapter->tmreg_lock);
1194 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);
1195
1196 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1197 INIT_DELAYED_WORK(&adapter->ptp_overflow_work,
1198 igb_ptp_overflow_check);
1199
1200 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1201 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1202
1203 igb_ptp_reset(adapter);
1204
1205 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1206 &adapter->pdev->dev);
1207 if (IS_ERR(adapter->ptp_clock)) {
1208 adapter->ptp_clock = NULL;
1209 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
1210 } else if (adapter->ptp_clock) {
1211 dev_info(&adapter->pdev->dev, "added PHC on %s\n",
1212 adapter->netdev->name);
1213 adapter->ptp_flags |= IGB_PTP_ENABLED;
1214 }
1215}
1216
1217/**
1218 * igb_ptp_suspend - Disable PTP work items and prepare for suspend
1219 * @adapter: Board private structure
1220 *
1221 * This function stops the overflow check work and PTP Tx timestamp work, and
1222 * will prepare the device for OS suspend.
1223 */
1224void igb_ptp_suspend(struct igb_adapter *adapter)
1225{
1226 if (!(adapter->ptp_flags & IGB_PTP_ENABLED))
1227 return;
1228
1229 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1230 cancel_delayed_work_sync(&adapter->ptp_overflow_work);
1231
1232 cancel_work_sync(&adapter->ptp_tx_work);
1233 if (adapter->ptp_tx_skb) {
1234 dev_kfree_skb_any(adapter->ptp_tx_skb);
1235 adapter->ptp_tx_skb = NULL;
1236 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
1237 }
1238}
1239
1240/**
1241 * igb_ptp_stop - Disable PTP device and stop the overflow check.
1242 * @adapter: Board private structure.
1243 *
1244 * This function stops the PTP support and cancels the delayed work.
1245 **/
1246void igb_ptp_stop(struct igb_adapter *adapter)
1247{
1248 igb_ptp_suspend(adapter);
1249
1250 if (adapter->ptp_clock) {
1251 ptp_clock_unregister(adapter->ptp_clock);
1252 dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
1253 adapter->netdev->name);
1254 adapter->ptp_flags &= ~IGB_PTP_ENABLED;
1255 }
1256}
1257
1258/**
1259 * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
1260 * @adapter: Board private structure.
1261 *
1262 * This function handles the reset work required to re-enable the PTP device.
1263 **/
1264void igb_ptp_reset(struct igb_adapter *adapter)
1265{
1266 struct e1000_hw *hw = &adapter->hw;
1267 unsigned long flags;
1268
1269 /* reset the tstamp_config */
1270 igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1271
1272 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1273
1274 switch (adapter->hw.mac.type) {
1275 case e1000_82576:
1276 /* Dial the nominal frequency. */
1277 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1278 break;
1279 case e1000_82580:
1280 case e1000_i354:
1281 case e1000_i350:
1282 case e1000_i210:
1283 case e1000_i211:
1284 wr32(E1000_TSAUXC, 0x0);
1285 wr32(E1000_TSSDP, 0x0);
1286 wr32(E1000_TSIM,
1287 TSYNC_INTERRUPTS |
1288 (adapter->pps_sys_wrap_on ? TSINTR_SYS_WRAP : 0));
1289 wr32(E1000_IMS, E1000_IMS_TS);
1290 break;
1291 default:
1292 /* No work to do. */
1293 goto out;
1294 }
1295
1296 /* Re-initialize the timer. */
1297 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1298 struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1299
1300 igb_ptp_write_i210(adapter, &ts);
1301 } else {
1302 timecounter_init(&adapter->tc, &adapter->cc,
1303 ktime_to_ns(ktime_get_real()));
1304 }
1305out:
1306 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1307
1308 wrfl();
1309
1310 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1311 schedule_delayed_work(&adapter->ptp_overflow_work,
1312 IGB_SYSTIM_OVERFLOW_PERIOD);
1313}