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1/*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30#include <linux/dma-mapping.h>
31#include <drm/ttm/ttm_tt.h>
32
33#include "nouveau_drv.h"
34#include "nouveau_chan.h"
35#include "nouveau_fence.h"
36
37#include "nouveau_bo.h"
38#include "nouveau_ttm.h"
39#include "nouveau_gem.h"
40#include "nouveau_mem.h"
41#include "nouveau_vmm.h"
42
43#include <nvif/class.h>
44#include <nvif/if500b.h>
45#include <nvif/if900b.h>
46
47static int nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
48 struct ttm_resource *reg);
49static void nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm);
50
51/*
52 * NV10-NV40 tiling helpers
53 */
54
55static void
56nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
57 u32 addr, u32 size, u32 pitch, u32 flags)
58{
59 struct nouveau_drm *drm = nouveau_drm(dev);
60 int i = reg - drm->tile.reg;
61 struct nvkm_fb *fb = nvxx_fb(drm);
62 struct nvkm_fb_tile *tile = &fb->tile.region[i];
63
64 nouveau_fence_unref(®->fence);
65
66 if (tile->pitch)
67 nvkm_fb_tile_fini(fb, i, tile);
68
69 if (pitch)
70 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
71
72 nvkm_fb_tile_prog(fb, i, tile);
73}
74
75static struct nouveau_drm_tile *
76nv10_bo_get_tile_region(struct drm_device *dev, int i)
77{
78 struct nouveau_drm *drm = nouveau_drm(dev);
79 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
80
81 spin_lock(&drm->tile.lock);
82
83 if (!tile->used &&
84 (!tile->fence || nouveau_fence_done(tile->fence)))
85 tile->used = true;
86 else
87 tile = NULL;
88
89 spin_unlock(&drm->tile.lock);
90 return tile;
91}
92
93static void
94nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
95 struct dma_fence *fence)
96{
97 struct nouveau_drm *drm = nouveau_drm(dev);
98
99 if (tile) {
100 spin_lock(&drm->tile.lock);
101 tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
102 tile->used = false;
103 spin_unlock(&drm->tile.lock);
104 }
105}
106
107static struct nouveau_drm_tile *
108nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
109 u32 size, u32 pitch, u32 zeta)
110{
111 struct nouveau_drm *drm = nouveau_drm(dev);
112 struct nvkm_fb *fb = nvxx_fb(drm);
113 struct nouveau_drm_tile *tile, *found = NULL;
114 int i;
115
116 for (i = 0; i < fb->tile.regions; i++) {
117 tile = nv10_bo_get_tile_region(dev, i);
118
119 if (pitch && !found) {
120 found = tile;
121 continue;
122
123 } else if (tile && fb->tile.region[i].pitch) {
124 /* Kill an unused tile region. */
125 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
126 }
127
128 nv10_bo_put_tile_region(dev, tile, NULL);
129 }
130
131 if (found)
132 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
133 return found;
134}
135
136static void
137nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
138{
139 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
140 struct drm_device *dev = drm->dev;
141 struct nouveau_bo *nvbo = nouveau_bo(bo);
142
143 WARN_ON(nvbo->bo.pin_count > 0);
144 nouveau_bo_del_io_reserve_lru(bo);
145 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
146
147 /*
148 * If nouveau_bo_new() allocated this buffer, the GEM object was never
149 * initialized, so don't attempt to release it.
150 */
151 if (bo->base.dev) {
152 /* Gem objects not being shared with other VMs get their
153 * dma_resv from a root GEM object.
154 */
155 if (nvbo->no_share)
156 drm_gem_object_put(nvbo->r_obj);
157
158 drm_gem_object_release(&bo->base);
159 } else {
160 dma_resv_fini(&bo->base._resv);
161 }
162
163 kfree(nvbo);
164}
165
166static inline u64
167roundup_64(u64 x, u32 y)
168{
169 x += y - 1;
170 do_div(x, y);
171 return x * y;
172}
173
174static void
175nouveau_bo_fixup_align(struct nouveau_bo *nvbo, int *align, u64 *size)
176{
177 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
178 struct nvif_device *device = &drm->client.device;
179
180 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
181 if (nvbo->mode) {
182 if (device->info.chipset >= 0x40) {
183 *align = 65536;
184 *size = roundup_64(*size, 64 * nvbo->mode);
185
186 } else if (device->info.chipset >= 0x30) {
187 *align = 32768;
188 *size = roundup_64(*size, 64 * nvbo->mode);
189
190 } else if (device->info.chipset >= 0x20) {
191 *align = 16384;
192 *size = roundup_64(*size, 64 * nvbo->mode);
193
194 } else if (device->info.chipset >= 0x10) {
195 *align = 16384;
196 *size = roundup_64(*size, 32 * nvbo->mode);
197 }
198 }
199 } else {
200 *size = roundup_64(*size, (1 << nvbo->page));
201 *align = max((1 << nvbo->page), *align);
202 }
203
204 *size = roundup_64(*size, PAGE_SIZE);
205}
206
207struct nouveau_bo *
208nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain,
209 u32 tile_mode, u32 tile_flags, bool internal)
210{
211 struct nouveau_drm *drm = cli->drm;
212 struct nouveau_bo *nvbo;
213 struct nvif_mmu *mmu = &cli->mmu;
214 struct nvif_vmm *vmm = &nouveau_cli_vmm(cli)->vmm;
215 int i, pi = -1;
216
217 if (!*size) {
218 NV_WARN(drm, "skipped size %016llx\n", *size);
219 return ERR_PTR(-EINVAL);
220 }
221
222 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
223 if (!nvbo)
224 return ERR_PTR(-ENOMEM);
225
226 INIT_LIST_HEAD(&nvbo->head);
227 INIT_LIST_HEAD(&nvbo->entry);
228 INIT_LIST_HEAD(&nvbo->vma_list);
229 nvbo->bo.bdev = &drm->ttm.bdev;
230
231 /* This is confusing, and doesn't actually mean we want an uncached
232 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
233 * into in nouveau_gem_new().
234 */
235 if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) {
236 /* Determine if we can get a cache-coherent map, forcing
237 * uncached mapping if we can't.
238 */
239 if (!nouveau_drm_use_coherent_gpu_mapping(drm))
240 nvbo->force_coherent = true;
241 }
242
243 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
244
245 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
246 nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
247 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
248 kfree(nvbo);
249 return ERR_PTR(-EINVAL);
250 }
251
252 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind;
253 } else if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
254 nvbo->kind = (tile_flags & 0x00007f00) >> 8;
255 nvbo->comp = (tile_flags & 0x00030000) >> 16;
256 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
257 kfree(nvbo);
258 return ERR_PTR(-EINVAL);
259 }
260 } else {
261 nvbo->zeta = (tile_flags & 0x00000007);
262 }
263 nvbo->mode = tile_mode;
264
265 if (!nouveau_cli_uvmm(cli) || internal) {
266 /* Determine the desirable target GPU page size for the buffer. */
267 for (i = 0; i < vmm->page_nr; i++) {
268 /* Because we cannot currently allow VMM maps to fail
269 * during buffer migration, we need to determine page
270 * size for the buffer up-front, and pre-allocate its
271 * page tables.
272 *
273 * Skip page sizes that can't support needed domains.
274 */
275 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE &&
276 (domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
277 continue;
278 if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
279 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
280 continue;
281
282 /* Select this page size if it's the first that supports
283 * the potential memory domains, or when it's compatible
284 * with the requested compression settings.
285 */
286 if (pi < 0 || !nvbo->comp || vmm->page[i].comp)
287 pi = i;
288
289 /* Stop once the buffer is larger than the current page size. */
290 if (*size >= 1ULL << vmm->page[i].shift)
291 break;
292 }
293
294 if (WARN_ON(pi < 0)) {
295 kfree(nvbo);
296 return ERR_PTR(-EINVAL);
297 }
298
299 /* Disable compression if suitable settings couldn't be found. */
300 if (nvbo->comp && !vmm->page[pi].comp) {
301 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100)
302 nvbo->kind = mmu->kind[nvbo->kind];
303 nvbo->comp = 0;
304 }
305 nvbo->page = vmm->page[pi].shift;
306 } else {
307 /* Determine the desirable target GPU page size for the buffer. */
308 for (i = 0; i < vmm->page_nr; i++) {
309 /* Because we cannot currently allow VMM maps to fail
310 * during buffer migration, we need to determine page
311 * size for the buffer up-front, and pre-allocate its
312 * page tables.
313 *
314 * Skip page sizes that can't support needed domains.
315 */
316 if ((domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
317 continue;
318 if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
319 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
320 continue;
321
322 /* pick the last one as it will be smallest. */
323 pi = i;
324
325 /* Stop once the buffer is larger than the current page size. */
326 if (*size >= 1ULL << vmm->page[i].shift)
327 break;
328 }
329 if (WARN_ON(pi < 0)) {
330 kfree(nvbo);
331 return ERR_PTR(-EINVAL);
332 }
333 nvbo->page = vmm->page[pi].shift;
334 }
335
336 nouveau_bo_fixup_align(nvbo, align, size);
337
338 return nvbo;
339}
340
341int
342nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 domain,
343 struct sg_table *sg, struct dma_resv *robj)
344{
345 int type = sg ? ttm_bo_type_sg : ttm_bo_type_device;
346 int ret;
347 struct ttm_operation_ctx ctx = {
348 .interruptible = false,
349 .no_wait_gpu = false,
350 .resv = robj,
351 };
352
353 nouveau_bo_placement_set(nvbo, domain, 0);
354 INIT_LIST_HEAD(&nvbo->io_reserve_lru);
355
356 ret = ttm_bo_init_reserved(nvbo->bo.bdev, &nvbo->bo, type,
357 &nvbo->placement, align >> PAGE_SHIFT, &ctx,
358 sg, robj, nouveau_bo_del_ttm);
359 if (ret) {
360 /* ttm will call nouveau_bo_del_ttm if it fails.. */
361 return ret;
362 }
363
364 if (!robj)
365 ttm_bo_unreserve(&nvbo->bo);
366
367 return 0;
368}
369
370int
371nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
372 uint32_t domain, uint32_t tile_mode, uint32_t tile_flags,
373 struct sg_table *sg, struct dma_resv *robj,
374 struct nouveau_bo **pnvbo)
375{
376 struct nouveau_bo *nvbo;
377 int ret;
378
379 nvbo = nouveau_bo_alloc(cli, &size, &align, domain, tile_mode,
380 tile_flags, true);
381 if (IS_ERR(nvbo))
382 return PTR_ERR(nvbo);
383
384 nvbo->bo.base.size = size;
385 dma_resv_init(&nvbo->bo.base._resv);
386 drm_vma_node_reset(&nvbo->bo.base.vma_node);
387
388 /* This must be called before ttm_bo_init_reserved(). Subsequent
389 * bo_move() callbacks might already iterate the GEMs GPUVA list.
390 */
391 drm_gem_gpuva_init(&nvbo->bo.base);
392
393 ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj);
394 if (ret)
395 return ret;
396
397 *pnvbo = nvbo;
398 return 0;
399}
400
401static void
402set_placement_range(struct nouveau_bo *nvbo, uint32_t domain)
403{
404 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
405 u64 vram_size = drm->client.device.info.ram_size;
406 unsigned i, fpfn, lpfn;
407
408 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
409 nvbo->mode && (domain & NOUVEAU_GEM_DOMAIN_VRAM) &&
410 nvbo->bo.base.size < vram_size / 4) {
411 /*
412 * Make sure that the color and depth buffers are handled
413 * by independent memory controller units. Up to a 9x
414 * speed up when alpha-blending and depth-test are enabled
415 * at the same time.
416 */
417 if (nvbo->zeta) {
418 fpfn = (vram_size / 2) >> PAGE_SHIFT;
419 lpfn = ~0;
420 } else {
421 fpfn = 0;
422 lpfn = (vram_size / 2) >> PAGE_SHIFT;
423 }
424 for (i = 0; i < nvbo->placement.num_placement; ++i) {
425 nvbo->placements[i].fpfn = fpfn;
426 nvbo->placements[i].lpfn = lpfn;
427 }
428 }
429}
430
431void
432nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t domain,
433 uint32_t busy)
434{
435 unsigned int *n = &nvbo->placement.num_placement;
436 struct ttm_place *pl = nvbo->placements;
437
438 domain |= busy;
439
440 *n = 0;
441 if (domain & NOUVEAU_GEM_DOMAIN_VRAM) {
442 pl[*n].mem_type = TTM_PL_VRAM;
443 pl[*n].flags = busy & NOUVEAU_GEM_DOMAIN_VRAM ?
444 TTM_PL_FLAG_FALLBACK : 0;
445 (*n)++;
446 }
447 if (domain & NOUVEAU_GEM_DOMAIN_GART) {
448 pl[*n].mem_type = TTM_PL_TT;
449 pl[*n].flags = busy & NOUVEAU_GEM_DOMAIN_GART ?
450 TTM_PL_FLAG_FALLBACK : 0;
451 (*n)++;
452 }
453 if (domain & NOUVEAU_GEM_DOMAIN_CPU) {
454 pl[*n].mem_type = TTM_PL_SYSTEM;
455 pl[*n].flags = busy & NOUVEAU_GEM_DOMAIN_CPU ?
456 TTM_PL_FLAG_FALLBACK : 0;
457 (*n)++;
458 }
459
460 nvbo->placement.placement = nvbo->placements;
461 set_placement_range(nvbo, domain);
462}
463
464int nouveau_bo_pin_locked(struct nouveau_bo *nvbo, uint32_t domain, bool contig)
465{
466 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
467 struct ttm_buffer_object *bo = &nvbo->bo;
468 bool force = false, evict = false;
469 int ret = 0;
470
471 dma_resv_assert_held(bo->base.resv);
472
473 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
474 domain == NOUVEAU_GEM_DOMAIN_VRAM && contig) {
475 if (!nvbo->contig) {
476 nvbo->contig = true;
477 force = true;
478 evict = true;
479 }
480 }
481
482 if (nvbo->bo.pin_count) {
483 bool error = evict;
484
485 switch (bo->resource->mem_type) {
486 case TTM_PL_VRAM:
487 error |= !(domain & NOUVEAU_GEM_DOMAIN_VRAM);
488 break;
489 case TTM_PL_TT:
490 error |= !(domain & NOUVEAU_GEM_DOMAIN_GART);
491 break;
492 default:
493 break;
494 }
495
496 if (error) {
497 NV_ERROR(drm, "bo %p pinned elsewhere: "
498 "0x%08x vs 0x%08x\n", bo,
499 bo->resource->mem_type, domain);
500 ret = -EBUSY;
501 }
502 ttm_bo_pin(&nvbo->bo);
503 goto out;
504 }
505
506 if (evict) {
507 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
508 ret = nouveau_bo_validate(nvbo, false, false);
509 if (ret)
510 goto out;
511 }
512
513 nouveau_bo_placement_set(nvbo, domain, 0);
514 ret = nouveau_bo_validate(nvbo, false, false);
515 if (ret)
516 goto out;
517
518 ttm_bo_pin(&nvbo->bo);
519
520 switch (bo->resource->mem_type) {
521 case TTM_PL_VRAM:
522 drm->gem.vram_available -= bo->base.size;
523 break;
524 case TTM_PL_TT:
525 drm->gem.gart_available -= bo->base.size;
526 break;
527 default:
528 break;
529 }
530
531out:
532 if (force && ret)
533 nvbo->contig = false;
534 return ret;
535}
536
537void nouveau_bo_unpin_locked(struct nouveau_bo *nvbo)
538{
539 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
540 struct ttm_buffer_object *bo = &nvbo->bo;
541
542 dma_resv_assert_held(bo->base.resv);
543
544 ttm_bo_unpin(&nvbo->bo);
545 if (!nvbo->bo.pin_count) {
546 switch (bo->resource->mem_type) {
547 case TTM_PL_VRAM:
548 drm->gem.vram_available += bo->base.size;
549 break;
550 case TTM_PL_TT:
551 drm->gem.gart_available += bo->base.size;
552 break;
553 default:
554 break;
555 }
556 }
557}
558
559int nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, bool contig)
560{
561 struct ttm_buffer_object *bo = &nvbo->bo;
562 int ret;
563
564 ret = ttm_bo_reserve(bo, false, false, NULL);
565 if (ret)
566 return ret;
567 ret = nouveau_bo_pin_locked(nvbo, domain, contig);
568 ttm_bo_unreserve(bo);
569
570 return ret;
571}
572
573int nouveau_bo_unpin(struct nouveau_bo *nvbo)
574{
575 struct ttm_buffer_object *bo = &nvbo->bo;
576 int ret;
577
578 ret = ttm_bo_reserve(bo, false, false, NULL);
579 if (ret)
580 return ret;
581 nouveau_bo_unpin_locked(nvbo);
582 ttm_bo_unreserve(bo);
583
584 return 0;
585}
586
587int
588nouveau_bo_map(struct nouveau_bo *nvbo)
589{
590 int ret;
591
592 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
593 if (ret)
594 return ret;
595
596 ret = ttm_bo_kmap(&nvbo->bo, 0, PFN_UP(nvbo->bo.base.size), &nvbo->kmap);
597
598 ttm_bo_unreserve(&nvbo->bo);
599 return ret;
600}
601
602void
603nouveau_bo_unmap(struct nouveau_bo *nvbo)
604{
605 if (!nvbo)
606 return;
607
608 ttm_bo_kunmap(&nvbo->kmap);
609}
610
611void
612nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
613{
614 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
615 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
616 int i, j;
617
618 if (!ttm_dma || !ttm_dma->dma_address)
619 return;
620 if (!ttm_dma->pages) {
621 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma);
622 return;
623 }
624
625 /* Don't waste time looping if the object is coherent */
626 if (nvbo->force_coherent)
627 return;
628
629 i = 0;
630 while (i < ttm_dma->num_pages) {
631 struct page *p = ttm_dma->pages[i];
632 size_t num_pages = 1;
633
634 for (j = i + 1; j < ttm_dma->num_pages; ++j) {
635 if (++p != ttm_dma->pages[j])
636 break;
637
638 ++num_pages;
639 }
640 dma_sync_single_for_device(drm->dev->dev,
641 ttm_dma->dma_address[i],
642 num_pages * PAGE_SIZE, DMA_TO_DEVICE);
643 i += num_pages;
644 }
645}
646
647void
648nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
649{
650 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
651 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
652 int i, j;
653
654 if (!ttm_dma || !ttm_dma->dma_address)
655 return;
656 if (!ttm_dma->pages) {
657 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma);
658 return;
659 }
660
661 /* Don't waste time looping if the object is coherent */
662 if (nvbo->force_coherent)
663 return;
664
665 i = 0;
666 while (i < ttm_dma->num_pages) {
667 struct page *p = ttm_dma->pages[i];
668 size_t num_pages = 1;
669
670 for (j = i + 1; j < ttm_dma->num_pages; ++j) {
671 if (++p != ttm_dma->pages[j])
672 break;
673
674 ++num_pages;
675 }
676
677 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
678 num_pages * PAGE_SIZE, DMA_FROM_DEVICE);
679 i += num_pages;
680 }
681}
682
683void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo)
684{
685 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
686 struct nouveau_bo *nvbo = nouveau_bo(bo);
687
688 mutex_lock(&drm->ttm.io_reserve_mutex);
689 list_move_tail(&nvbo->io_reserve_lru, &drm->ttm.io_reserve_lru);
690 mutex_unlock(&drm->ttm.io_reserve_mutex);
691}
692
693void nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object *bo)
694{
695 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
696 struct nouveau_bo *nvbo = nouveau_bo(bo);
697
698 mutex_lock(&drm->ttm.io_reserve_mutex);
699 list_del_init(&nvbo->io_reserve_lru);
700 mutex_unlock(&drm->ttm.io_reserve_mutex);
701}
702
703int
704nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
705 bool no_wait_gpu)
706{
707 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
708 int ret;
709
710 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
711 if (ret)
712 return ret;
713
714 nouveau_bo_sync_for_device(nvbo);
715
716 return 0;
717}
718
719void
720nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
721{
722 bool is_iomem;
723 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
724
725 mem += index;
726
727 if (is_iomem)
728 iowrite16_native(val, (void __force __iomem *)mem);
729 else
730 *mem = val;
731}
732
733u32
734nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
735{
736 bool is_iomem;
737 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
738
739 mem += index;
740
741 if (is_iomem)
742 return ioread32_native((void __force __iomem *)mem);
743 else
744 return *mem;
745}
746
747void
748nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
749{
750 bool is_iomem;
751 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
752
753 mem += index;
754
755 if (is_iomem)
756 iowrite32_native(val, (void __force __iomem *)mem);
757 else
758 *mem = val;
759}
760
761static struct ttm_tt *
762nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags)
763{
764#if IS_ENABLED(CONFIG_AGP)
765 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
766
767 if (drm->agp.bridge) {
768 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags);
769 }
770#endif
771
772 return nouveau_sgdma_create_ttm(bo, page_flags);
773}
774
775static int
776nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
777 struct ttm_resource *reg)
778{
779#if IS_ENABLED(CONFIG_AGP)
780 struct nouveau_drm *drm = nouveau_bdev(bdev);
781#endif
782 if (!reg)
783 return -EINVAL;
784#if IS_ENABLED(CONFIG_AGP)
785 if (drm->agp.bridge)
786 return ttm_agp_bind(ttm, reg);
787#endif
788 return nouveau_sgdma_bind(bdev, ttm, reg);
789}
790
791static void
792nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm)
793{
794#if IS_ENABLED(CONFIG_AGP)
795 struct nouveau_drm *drm = nouveau_bdev(bdev);
796
797 if (drm->agp.bridge) {
798 ttm_agp_unbind(ttm);
799 return;
800 }
801#endif
802 nouveau_sgdma_unbind(bdev, ttm);
803}
804
805static void
806nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
807{
808 struct nouveau_bo *nvbo = nouveau_bo(bo);
809
810 switch (bo->resource->mem_type) {
811 case TTM_PL_VRAM:
812 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART,
813 NOUVEAU_GEM_DOMAIN_CPU);
814 break;
815 default:
816 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_CPU, 0);
817 break;
818 }
819
820 *pl = nvbo->placement;
821}
822
823static int
824nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
825 struct ttm_resource *reg)
826{
827 struct nouveau_mem *old_mem = nouveau_mem(bo->resource);
828 struct nouveau_mem *new_mem = nouveau_mem(reg);
829 struct nvif_vmm *vmm = &drm->client.vmm.vmm;
830 int ret;
831
832 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0,
833 old_mem->mem.size, &old_mem->vma[0]);
834 if (ret)
835 return ret;
836
837 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0,
838 new_mem->mem.size, &old_mem->vma[1]);
839 if (ret)
840 goto done;
841
842 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
843 if (ret)
844 goto done;
845
846 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
847done:
848 if (ret) {
849 nvif_vmm_put(vmm, &old_mem->vma[1]);
850 nvif_vmm_put(vmm, &old_mem->vma[0]);
851 }
852 return 0;
853}
854
855static int
856nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict,
857 struct ttm_operation_ctx *ctx,
858 struct ttm_resource *new_reg)
859{
860 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
861 struct nouveau_channel *chan = drm->ttm.chan;
862 struct nouveau_cli *cli = chan->cli;
863 struct nouveau_fence *fence;
864 int ret;
865
866 /* create temporary vmas for the transfer and attach them to the
867 * old nvkm_mem node, these will get cleaned up after ttm has
868 * destroyed the ttm_resource
869 */
870 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
871 ret = nouveau_bo_move_prep(drm, bo, new_reg);
872 if (ret)
873 return ret;
874 }
875
876 if (drm_drv_uses_atomic_modeset(drm->dev))
877 mutex_lock(&cli->mutex);
878 else
879 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
880
881 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, ctx->interruptible);
882 if (ret)
883 goto out_unlock;
884
885 ret = drm->ttm.move(chan, bo, bo->resource, new_reg);
886 if (ret)
887 goto out_unlock;
888
889 ret = nouveau_fence_new(&fence, chan);
890 if (ret)
891 goto out_unlock;
892
893 /* TODO: figure out a better solution here
894 *
895 * wait on the fence here explicitly as going through
896 * ttm_bo_move_accel_cleanup somehow doesn't seem to do it.
897 *
898 * Without this the operation can timeout and we'll fallback to a
899 * software copy, which might take several minutes to finish.
900 */
901 nouveau_fence_wait(fence, false, false);
902 ret = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, false,
903 new_reg);
904 nouveau_fence_unref(&fence);
905
906out_unlock:
907 mutex_unlock(&cli->mutex);
908 return ret;
909}
910
911void
912nouveau_bo_move_init(struct nouveau_drm *drm)
913{
914 static const struct _method_table {
915 const char *name;
916 int engine;
917 s32 oclass;
918 int (*exec)(struct nouveau_channel *,
919 struct ttm_buffer_object *,
920 struct ttm_resource *, struct ttm_resource *);
921 int (*init)(struct nouveau_channel *, u32 handle);
922 } _methods[] = {
923 { "COPY", 4, 0xc7b5, nve0_bo_move_copy, nve0_bo_move_init },
924 { "GRCE", 0, 0xc7b5, nve0_bo_move_copy, nvc0_bo_move_init },
925 { "COPY", 4, 0xc6b5, nve0_bo_move_copy, nve0_bo_move_init },
926 { "GRCE", 0, 0xc6b5, nve0_bo_move_copy, nvc0_bo_move_init },
927 { "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init },
928 { "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init },
929 { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init },
930 { "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init },
931 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
932 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
933 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
934 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
935 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
936 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
937 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
938 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
939 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
940 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
941 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
942 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
943 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
944 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
945 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
946 {},
947 };
948 const struct _method_table *mthd = _methods;
949 const char *name = "CPU";
950 int ret;
951
952 do {
953 struct nouveau_channel *chan;
954
955 if (mthd->engine)
956 chan = drm->cechan;
957 else
958 chan = drm->channel;
959 if (chan == NULL)
960 continue;
961
962 ret = nvif_object_ctor(&chan->user, "ttmBoMove",
963 mthd->oclass | (mthd->engine << 16),
964 mthd->oclass, NULL, 0,
965 &drm->ttm.copy);
966 if (ret == 0) {
967 ret = mthd->init(chan, drm->ttm.copy.handle);
968 if (ret) {
969 nvif_object_dtor(&drm->ttm.copy);
970 continue;
971 }
972
973 drm->ttm.move = mthd->exec;
974 drm->ttm.chan = chan;
975 name = mthd->name;
976 break;
977 }
978 } while ((++mthd)->exec);
979
980 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
981}
982
983static void nouveau_bo_move_ntfy(struct ttm_buffer_object *bo,
984 struct ttm_resource *new_reg)
985{
986 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
987 struct nouveau_bo *nvbo = nouveau_bo(bo);
988 struct nouveau_vma *vma;
989 long ret;
990
991 /* ttm can now (stupidly) pass the driver bos it didn't create... */
992 if (bo->destroy != nouveau_bo_del_ttm)
993 return;
994
995 nouveau_bo_del_io_reserve_lru(bo);
996
997 if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
998 mem->mem.page == nvbo->page) {
999 list_for_each_entry(vma, &nvbo->vma_list, head) {
1000 nouveau_vma_map(vma, mem);
1001 }
1002 nouveau_uvmm_bo_map_all(nvbo, mem);
1003 } else {
1004 list_for_each_entry(vma, &nvbo->vma_list, head) {
1005 ret = dma_resv_wait_timeout(bo->base.resv,
1006 DMA_RESV_USAGE_BOOKKEEP,
1007 false, 15 * HZ);
1008 WARN_ON(ret <= 0);
1009 nouveau_vma_unmap(vma);
1010 }
1011 nouveau_uvmm_bo_unmap_all(nvbo);
1012 }
1013
1014 if (new_reg)
1015 nvbo->offset = (new_reg->start << PAGE_SHIFT);
1016
1017}
1018
1019static int
1020nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg,
1021 struct nouveau_drm_tile **new_tile)
1022{
1023 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1024 struct drm_device *dev = drm->dev;
1025 struct nouveau_bo *nvbo = nouveau_bo(bo);
1026 u64 offset = new_reg->start << PAGE_SHIFT;
1027
1028 *new_tile = NULL;
1029 if (new_reg->mem_type != TTM_PL_VRAM)
1030 return 0;
1031
1032 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
1033 *new_tile = nv10_bo_set_tiling(dev, offset, bo->base.size,
1034 nvbo->mode, nvbo->zeta);
1035 }
1036
1037 return 0;
1038}
1039
1040static void
1041nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1042 struct nouveau_drm_tile *new_tile,
1043 struct nouveau_drm_tile **old_tile)
1044{
1045 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1046 struct drm_device *dev = drm->dev;
1047 struct dma_fence *fence;
1048 int ret;
1049
1050 ret = dma_resv_get_singleton(bo->base.resv, DMA_RESV_USAGE_WRITE,
1051 &fence);
1052 if (ret)
1053 dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_WRITE,
1054 false, MAX_SCHEDULE_TIMEOUT);
1055
1056 nv10_bo_put_tile_region(dev, *old_tile, fence);
1057 *old_tile = new_tile;
1058}
1059
1060static int
1061nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
1062 struct ttm_operation_ctx *ctx,
1063 struct ttm_resource *new_reg,
1064 struct ttm_place *hop)
1065{
1066 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1067 struct nouveau_bo *nvbo = nouveau_bo(bo);
1068 struct drm_gem_object *obj = &bo->base;
1069 struct ttm_resource *old_reg = bo->resource;
1070 struct nouveau_drm_tile *new_tile = NULL;
1071 int ret = 0;
1072
1073 if (new_reg->mem_type == TTM_PL_TT) {
1074 ret = nouveau_ttm_tt_bind(bo->bdev, bo->ttm, new_reg);
1075 if (ret)
1076 return ret;
1077 }
1078
1079 drm_gpuvm_bo_gem_evict(obj, evict);
1080 nouveau_bo_move_ntfy(bo, new_reg);
1081 ret = ttm_bo_wait_ctx(bo, ctx);
1082 if (ret)
1083 goto out_ntfy;
1084
1085 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1086 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
1087 if (ret)
1088 goto out_ntfy;
1089 }
1090
1091 /* Fake bo copy. */
1092 if (!old_reg || (old_reg->mem_type == TTM_PL_SYSTEM &&
1093 !bo->ttm)) {
1094 ttm_bo_move_null(bo, new_reg);
1095 goto out;
1096 }
1097
1098 if (old_reg->mem_type == TTM_PL_SYSTEM &&
1099 new_reg->mem_type == TTM_PL_TT) {
1100 ttm_bo_move_null(bo, new_reg);
1101 goto out;
1102 }
1103
1104 if (old_reg->mem_type == TTM_PL_TT &&
1105 new_reg->mem_type == TTM_PL_SYSTEM) {
1106 nouveau_ttm_tt_unbind(bo->bdev, bo->ttm);
1107 ttm_resource_free(bo, &bo->resource);
1108 ttm_bo_assign_mem(bo, new_reg);
1109 goto out;
1110 }
1111
1112 /* Hardware assisted copy. */
1113 if (drm->ttm.move) {
1114 if ((old_reg->mem_type == TTM_PL_SYSTEM &&
1115 new_reg->mem_type == TTM_PL_VRAM) ||
1116 (old_reg->mem_type == TTM_PL_VRAM &&
1117 new_reg->mem_type == TTM_PL_SYSTEM)) {
1118 hop->fpfn = 0;
1119 hop->lpfn = 0;
1120 hop->mem_type = TTM_PL_TT;
1121 hop->flags = 0;
1122 return -EMULTIHOP;
1123 }
1124 ret = nouveau_bo_move_m2mf(bo, evict, ctx,
1125 new_reg);
1126 } else
1127 ret = -ENODEV;
1128
1129 if (ret) {
1130 /* Fallback to software copy. */
1131 ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
1132 }
1133
1134out:
1135 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1136 if (ret)
1137 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1138 else
1139 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1140 }
1141out_ntfy:
1142 if (ret) {
1143 nouveau_bo_move_ntfy(bo, bo->resource);
1144 drm_gpuvm_bo_gem_evict(obj, !evict);
1145 }
1146 return ret;
1147}
1148
1149static void
1150nouveau_ttm_io_mem_free_locked(struct nouveau_drm *drm,
1151 struct ttm_resource *reg)
1152{
1153 struct nouveau_mem *mem = nouveau_mem(reg);
1154
1155 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1156 switch (reg->mem_type) {
1157 case TTM_PL_TT:
1158 if (mem->kind)
1159 nvif_object_unmap_handle(&mem->mem.object);
1160 break;
1161 case TTM_PL_VRAM:
1162 nvif_object_unmap_handle(&mem->mem.object);
1163 break;
1164 default:
1165 break;
1166 }
1167 }
1168}
1169
1170static int
1171nouveau_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *reg)
1172{
1173 struct nouveau_drm *drm = nouveau_bdev(bdev);
1174 struct nvkm_device *device = nvxx_device(drm);
1175 struct nouveau_mem *mem = nouveau_mem(reg);
1176 struct nvif_mmu *mmu = &drm->client.mmu;
1177 int ret;
1178
1179 mutex_lock(&drm->ttm.io_reserve_mutex);
1180retry:
1181 switch (reg->mem_type) {
1182 case TTM_PL_SYSTEM:
1183 /* System memory */
1184 ret = 0;
1185 goto out;
1186 case TTM_PL_TT:
1187#if IS_ENABLED(CONFIG_AGP)
1188 if (drm->agp.bridge) {
1189 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1190 drm->agp.base;
1191 reg->bus.is_iomem = !drm->agp.cma;
1192 reg->bus.caching = ttm_write_combined;
1193 }
1194#endif
1195 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 ||
1196 !mem->kind) {
1197 /* untiled */
1198 ret = 0;
1199 break;
1200 }
1201 fallthrough; /* tiled memory */
1202 case TTM_PL_VRAM:
1203 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1204 device->func->resource_addr(device, 1);
1205 reg->bus.is_iomem = true;
1206
1207 /* Some BARs do not support being ioremapped WC */
1208 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
1209 mmu->type[drm->ttm.type_vram].type & NVIF_MEM_UNCACHED)
1210 reg->bus.caching = ttm_uncached;
1211 else
1212 reg->bus.caching = ttm_write_combined;
1213
1214 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1215 union {
1216 struct nv50_mem_map_v0 nv50;
1217 struct gf100_mem_map_v0 gf100;
1218 } args;
1219 u64 handle, length;
1220 u32 argc = 0;
1221
1222 switch (mem->mem.object.oclass) {
1223 case NVIF_CLASS_MEM_NV50:
1224 args.nv50.version = 0;
1225 args.nv50.ro = 0;
1226 args.nv50.kind = mem->kind;
1227 args.nv50.comp = mem->comp;
1228 argc = sizeof(args.nv50);
1229 break;
1230 case NVIF_CLASS_MEM_GF100:
1231 args.gf100.version = 0;
1232 args.gf100.ro = 0;
1233 args.gf100.kind = mem->kind;
1234 argc = sizeof(args.gf100);
1235 break;
1236 default:
1237 WARN_ON(1);
1238 break;
1239 }
1240
1241 ret = nvif_object_map_handle(&mem->mem.object,
1242 &args, argc,
1243 &handle, &length);
1244 if (ret != 1) {
1245 if (WARN_ON(ret == 0))
1246 ret = -EINVAL;
1247 goto out;
1248 }
1249
1250 reg->bus.offset = handle;
1251 }
1252 ret = 0;
1253 break;
1254 default:
1255 ret = -EINVAL;
1256 }
1257
1258out:
1259 if (ret == -ENOSPC) {
1260 struct nouveau_bo *nvbo;
1261
1262 nvbo = list_first_entry_or_null(&drm->ttm.io_reserve_lru,
1263 typeof(*nvbo),
1264 io_reserve_lru);
1265 if (nvbo) {
1266 list_del_init(&nvbo->io_reserve_lru);
1267 drm_vma_node_unmap(&nvbo->bo.base.vma_node,
1268 bdev->dev_mapping);
1269 nouveau_ttm_io_mem_free_locked(drm, nvbo->bo.resource);
1270 nvbo->bo.resource->bus.offset = 0;
1271 nvbo->bo.resource->bus.addr = NULL;
1272 goto retry;
1273 }
1274
1275 }
1276 mutex_unlock(&drm->ttm.io_reserve_mutex);
1277 return ret;
1278}
1279
1280static void
1281nouveau_ttm_io_mem_free(struct ttm_device *bdev, struct ttm_resource *reg)
1282{
1283 struct nouveau_drm *drm = nouveau_bdev(bdev);
1284
1285 mutex_lock(&drm->ttm.io_reserve_mutex);
1286 nouveau_ttm_io_mem_free_locked(drm, reg);
1287 mutex_unlock(&drm->ttm.io_reserve_mutex);
1288}
1289
1290vm_fault_t nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1291{
1292 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1293 struct nouveau_bo *nvbo = nouveau_bo(bo);
1294 struct nvkm_device *device = nvxx_device(drm);
1295 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1296 int i, ret;
1297
1298 /* as long as the bo isn't in vram, and isn't tiled, we've got
1299 * nothing to do here.
1300 */
1301 if (bo->resource->mem_type != TTM_PL_VRAM) {
1302 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1303 !nvbo->kind)
1304 return 0;
1305
1306 if (bo->resource->mem_type != TTM_PL_SYSTEM)
1307 return 0;
1308
1309 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
1310
1311 } else {
1312 /* make sure bo is in mappable vram */
1313 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1314 bo->resource->start + PFN_UP(bo->resource->size) < mappable)
1315 return 0;
1316
1317 for (i = 0; i < nvbo->placement.num_placement; ++i) {
1318 nvbo->placements[i].fpfn = 0;
1319 nvbo->placements[i].lpfn = mappable;
1320 }
1321
1322 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0);
1323 }
1324
1325 ret = nouveau_bo_validate(nvbo, false, false);
1326 if (unlikely(ret == -EBUSY || ret == -ERESTARTSYS))
1327 return VM_FAULT_NOPAGE;
1328 else if (unlikely(ret))
1329 return VM_FAULT_SIGBUS;
1330
1331 ttm_bo_move_to_lru_tail_unlocked(bo);
1332 return 0;
1333}
1334
1335static int
1336nouveau_ttm_tt_populate(struct ttm_device *bdev,
1337 struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
1338{
1339 struct ttm_tt *ttm_dma = (void *)ttm;
1340 struct nouveau_drm *drm;
1341 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
1342
1343 if (ttm_tt_is_populated(ttm))
1344 return 0;
1345
1346 if (slave && ttm->sg) {
1347 drm_prime_sg_to_dma_addr_array(ttm->sg, ttm_dma->dma_address,
1348 ttm->num_pages);
1349 return 0;
1350 }
1351
1352 drm = nouveau_bdev(bdev);
1353
1354 return ttm_pool_alloc(&drm->ttm.bdev.pool, ttm, ctx);
1355}
1356
1357static void
1358nouveau_ttm_tt_unpopulate(struct ttm_device *bdev,
1359 struct ttm_tt *ttm)
1360{
1361 struct nouveau_drm *drm;
1362 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
1363
1364 if (slave)
1365 return;
1366
1367 nouveau_ttm_tt_unbind(bdev, ttm);
1368
1369 drm = nouveau_bdev(bdev);
1370
1371 return ttm_pool_free(&drm->ttm.bdev.pool, ttm);
1372}
1373
1374static void
1375nouveau_ttm_tt_destroy(struct ttm_device *bdev,
1376 struct ttm_tt *ttm)
1377{
1378#if IS_ENABLED(CONFIG_AGP)
1379 struct nouveau_drm *drm = nouveau_bdev(bdev);
1380 if (drm->agp.bridge) {
1381 ttm_agp_destroy(ttm);
1382 return;
1383 }
1384#endif
1385 nouveau_sgdma_destroy(bdev, ttm);
1386}
1387
1388void
1389nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1390{
1391 struct dma_resv *resv = nvbo->bo.base.resv;
1392
1393 if (!fence)
1394 return;
1395
1396 dma_resv_add_fence(resv, &fence->base, exclusive ?
1397 DMA_RESV_USAGE_WRITE : DMA_RESV_USAGE_READ);
1398}
1399
1400static void
1401nouveau_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1402{
1403 nouveau_bo_move_ntfy(bo, NULL);
1404}
1405
1406struct ttm_device_funcs nouveau_bo_driver = {
1407 .ttm_tt_create = &nouveau_ttm_tt_create,
1408 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1409 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1410 .ttm_tt_destroy = &nouveau_ttm_tt_destroy,
1411 .eviction_valuable = ttm_bo_eviction_valuable,
1412 .evict_flags = nouveau_bo_evict_flags,
1413 .delete_mem_notify = nouveau_bo_delete_mem_notify,
1414 .move = nouveau_bo_move,
1415 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1416 .io_mem_free = &nouveau_ttm_io_mem_free,
1417};
1/*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30#include "drmP.h"
31#include "ttm/ttm_page_alloc.h"
32
33#include "nouveau_drm.h"
34#include "nouveau_drv.h"
35#include "nouveau_dma.h"
36#include "nouveau_mm.h"
37#include "nouveau_vm.h"
38#include "nouveau_fence.h"
39#include "nouveau_ramht.h"
40
41#include <linux/log2.h>
42#include <linux/slab.h>
43
44static void
45nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
46{
47 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
48 struct drm_device *dev = dev_priv->dev;
49 struct nouveau_bo *nvbo = nouveau_bo(bo);
50
51 if (unlikely(nvbo->gem))
52 DRM_ERROR("bo %p still attached to GEM object\n", bo);
53
54 nv10_mem_put_tile_region(dev, nvbo->tile, NULL);
55 kfree(nvbo);
56}
57
58static void
59nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
60 int *align, int *size)
61{
62 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
63
64 if (dev_priv->card_type < NV_50) {
65 if (nvbo->tile_mode) {
66 if (dev_priv->chipset >= 0x40) {
67 *align = 65536;
68 *size = roundup(*size, 64 * nvbo->tile_mode);
69
70 } else if (dev_priv->chipset >= 0x30) {
71 *align = 32768;
72 *size = roundup(*size, 64 * nvbo->tile_mode);
73
74 } else if (dev_priv->chipset >= 0x20) {
75 *align = 16384;
76 *size = roundup(*size, 64 * nvbo->tile_mode);
77
78 } else if (dev_priv->chipset >= 0x10) {
79 *align = 16384;
80 *size = roundup(*size, 32 * nvbo->tile_mode);
81 }
82 }
83 } else {
84 *size = roundup(*size, (1 << nvbo->page_shift));
85 *align = max((1 << nvbo->page_shift), *align);
86 }
87
88 *size = roundup(*size, PAGE_SIZE);
89}
90
91int
92nouveau_bo_new(struct drm_device *dev, int size, int align,
93 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
94 struct sg_table *sg,
95 struct nouveau_bo **pnvbo)
96{
97 struct drm_nouveau_private *dev_priv = dev->dev_private;
98 struct nouveau_bo *nvbo;
99 size_t acc_size;
100 int ret;
101 int type = ttm_bo_type_device;
102
103 if (sg)
104 type = ttm_bo_type_sg;
105
106 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
107 if (!nvbo)
108 return -ENOMEM;
109 INIT_LIST_HEAD(&nvbo->head);
110 INIT_LIST_HEAD(&nvbo->entry);
111 INIT_LIST_HEAD(&nvbo->vma_list);
112 nvbo->tile_mode = tile_mode;
113 nvbo->tile_flags = tile_flags;
114 nvbo->bo.bdev = &dev_priv->ttm.bdev;
115
116 nvbo->page_shift = 12;
117 if (dev_priv->bar1_vm) {
118 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
119 nvbo->page_shift = dev_priv->bar1_vm->lpg_shift;
120 }
121
122 nouveau_bo_fixup_align(nvbo, flags, &align, &size);
123 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
124 nouveau_bo_placement_set(nvbo, flags, 0);
125
126 acc_size = ttm_bo_dma_acc_size(&dev_priv->ttm.bdev, size,
127 sizeof(struct nouveau_bo));
128
129 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
130 type, &nvbo->placement,
131 align >> PAGE_SHIFT, 0, false, NULL, acc_size, sg,
132 nouveau_bo_del_ttm);
133 if (ret) {
134 /* ttm will call nouveau_bo_del_ttm if it fails.. */
135 return ret;
136 }
137
138 *pnvbo = nvbo;
139 return 0;
140}
141
142static void
143set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
144{
145 *n = 0;
146
147 if (type & TTM_PL_FLAG_VRAM)
148 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
149 if (type & TTM_PL_FLAG_TT)
150 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
151 if (type & TTM_PL_FLAG_SYSTEM)
152 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
153}
154
155static void
156set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
157{
158 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
159 int vram_pages = dev_priv->vram_size >> PAGE_SHIFT;
160
161 if (dev_priv->card_type == NV_10 &&
162 nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
163 nvbo->bo.mem.num_pages < vram_pages / 4) {
164 /*
165 * Make sure that the color and depth buffers are handled
166 * by independent memory controller units. Up to a 9x
167 * speed up when alpha-blending and depth-test are enabled
168 * at the same time.
169 */
170 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
171 nvbo->placement.fpfn = vram_pages / 2;
172 nvbo->placement.lpfn = ~0;
173 } else {
174 nvbo->placement.fpfn = 0;
175 nvbo->placement.lpfn = vram_pages / 2;
176 }
177 }
178}
179
180void
181nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
182{
183 struct ttm_placement *pl = &nvbo->placement;
184 uint32_t flags = TTM_PL_MASK_CACHING |
185 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
186
187 pl->placement = nvbo->placements;
188 set_placement_list(nvbo->placements, &pl->num_placement,
189 type, flags);
190
191 pl->busy_placement = nvbo->busy_placements;
192 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
193 type | busy, flags);
194
195 set_placement_range(nvbo, type);
196}
197
198int
199nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
200{
201 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
202 struct ttm_buffer_object *bo = &nvbo->bo;
203 int ret;
204
205 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
206 NV_ERROR(nouveau_bdev(bo->bdev)->dev,
207 "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
208 1 << bo->mem.mem_type, memtype);
209 return -EINVAL;
210 }
211
212 if (nvbo->pin_refcnt++)
213 return 0;
214
215 ret = ttm_bo_reserve(bo, false, false, false, 0);
216 if (ret)
217 goto out;
218
219 nouveau_bo_placement_set(nvbo, memtype, 0);
220
221 ret = nouveau_bo_validate(nvbo, false, false, false);
222 if (ret == 0) {
223 switch (bo->mem.mem_type) {
224 case TTM_PL_VRAM:
225 dev_priv->fb_aper_free -= bo->mem.size;
226 break;
227 case TTM_PL_TT:
228 dev_priv->gart_info.aper_free -= bo->mem.size;
229 break;
230 default:
231 break;
232 }
233 }
234 ttm_bo_unreserve(bo);
235out:
236 if (unlikely(ret))
237 nvbo->pin_refcnt--;
238 return ret;
239}
240
241int
242nouveau_bo_unpin(struct nouveau_bo *nvbo)
243{
244 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
245 struct ttm_buffer_object *bo = &nvbo->bo;
246 int ret;
247
248 if (--nvbo->pin_refcnt)
249 return 0;
250
251 ret = ttm_bo_reserve(bo, false, false, false, 0);
252 if (ret)
253 return ret;
254
255 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
256
257 ret = nouveau_bo_validate(nvbo, false, false, false);
258 if (ret == 0) {
259 switch (bo->mem.mem_type) {
260 case TTM_PL_VRAM:
261 dev_priv->fb_aper_free += bo->mem.size;
262 break;
263 case TTM_PL_TT:
264 dev_priv->gart_info.aper_free += bo->mem.size;
265 break;
266 default:
267 break;
268 }
269 }
270
271 ttm_bo_unreserve(bo);
272 return ret;
273}
274
275int
276nouveau_bo_map(struct nouveau_bo *nvbo)
277{
278 int ret;
279
280 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
281 if (ret)
282 return ret;
283
284 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
285 ttm_bo_unreserve(&nvbo->bo);
286 return ret;
287}
288
289void
290nouveau_bo_unmap(struct nouveau_bo *nvbo)
291{
292 if (nvbo)
293 ttm_bo_kunmap(&nvbo->kmap);
294}
295
296int
297nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
298 bool no_wait_reserve, bool no_wait_gpu)
299{
300 int ret;
301
302 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, interruptible,
303 no_wait_reserve, no_wait_gpu);
304 if (ret)
305 return ret;
306
307 return 0;
308}
309
310u16
311nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
312{
313 bool is_iomem;
314 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
315 mem = &mem[index];
316 if (is_iomem)
317 return ioread16_native((void __force __iomem *)mem);
318 else
319 return *mem;
320}
321
322void
323nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
324{
325 bool is_iomem;
326 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
327 mem = &mem[index];
328 if (is_iomem)
329 iowrite16_native(val, (void __force __iomem *)mem);
330 else
331 *mem = val;
332}
333
334u32
335nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
336{
337 bool is_iomem;
338 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
339 mem = &mem[index];
340 if (is_iomem)
341 return ioread32_native((void __force __iomem *)mem);
342 else
343 return *mem;
344}
345
346void
347nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
348{
349 bool is_iomem;
350 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
351 mem = &mem[index];
352 if (is_iomem)
353 iowrite32_native(val, (void __force __iomem *)mem);
354 else
355 *mem = val;
356}
357
358static struct ttm_tt *
359nouveau_ttm_tt_create(struct ttm_bo_device *bdev,
360 unsigned long size, uint32_t page_flags,
361 struct page *dummy_read_page)
362{
363 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
364 struct drm_device *dev = dev_priv->dev;
365
366 switch (dev_priv->gart_info.type) {
367#if __OS_HAS_AGP
368 case NOUVEAU_GART_AGP:
369 return ttm_agp_tt_create(bdev, dev->agp->bridge,
370 size, page_flags, dummy_read_page);
371#endif
372 case NOUVEAU_GART_PDMA:
373 case NOUVEAU_GART_HW:
374 return nouveau_sgdma_create_ttm(bdev, size, page_flags,
375 dummy_read_page);
376 default:
377 NV_ERROR(dev, "Unknown GART type %d\n",
378 dev_priv->gart_info.type);
379 break;
380 }
381
382 return NULL;
383}
384
385static int
386nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
387{
388 /* We'll do this from user space. */
389 return 0;
390}
391
392static int
393nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
394 struct ttm_mem_type_manager *man)
395{
396 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
397 struct drm_device *dev = dev_priv->dev;
398
399 switch (type) {
400 case TTM_PL_SYSTEM:
401 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
402 man->available_caching = TTM_PL_MASK_CACHING;
403 man->default_caching = TTM_PL_FLAG_CACHED;
404 break;
405 case TTM_PL_VRAM:
406 if (dev_priv->card_type >= NV_50) {
407 man->func = &nouveau_vram_manager;
408 man->io_reserve_fastpath = false;
409 man->use_io_reserve_lru = true;
410 } else {
411 man->func = &ttm_bo_manager_func;
412 }
413 man->flags = TTM_MEMTYPE_FLAG_FIXED |
414 TTM_MEMTYPE_FLAG_MAPPABLE;
415 man->available_caching = TTM_PL_FLAG_UNCACHED |
416 TTM_PL_FLAG_WC;
417 man->default_caching = TTM_PL_FLAG_WC;
418 break;
419 case TTM_PL_TT:
420 if (dev_priv->card_type >= NV_50)
421 man->func = &nouveau_gart_manager;
422 else
423 man->func = &ttm_bo_manager_func;
424 switch (dev_priv->gart_info.type) {
425 case NOUVEAU_GART_AGP:
426 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
427 man->available_caching = TTM_PL_FLAG_UNCACHED |
428 TTM_PL_FLAG_WC;
429 man->default_caching = TTM_PL_FLAG_WC;
430 break;
431 case NOUVEAU_GART_PDMA:
432 case NOUVEAU_GART_HW:
433 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
434 TTM_MEMTYPE_FLAG_CMA;
435 man->available_caching = TTM_PL_MASK_CACHING;
436 man->default_caching = TTM_PL_FLAG_CACHED;
437 break;
438 default:
439 NV_ERROR(dev, "Unknown GART type: %d\n",
440 dev_priv->gart_info.type);
441 return -EINVAL;
442 }
443 break;
444 default:
445 NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
446 return -EINVAL;
447 }
448 return 0;
449}
450
451static void
452nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
453{
454 struct nouveau_bo *nvbo = nouveau_bo(bo);
455
456 switch (bo->mem.mem_type) {
457 case TTM_PL_VRAM:
458 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
459 TTM_PL_FLAG_SYSTEM);
460 break;
461 default:
462 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
463 break;
464 }
465
466 *pl = nvbo->placement;
467}
468
469
470/* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
471 * TTM_PL_{VRAM,TT} directly.
472 */
473
474static int
475nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
476 struct nouveau_bo *nvbo, bool evict,
477 bool no_wait_reserve, bool no_wait_gpu,
478 struct ttm_mem_reg *new_mem)
479{
480 struct nouveau_fence *fence = NULL;
481 int ret;
482
483 ret = nouveau_fence_new(chan, &fence);
484 if (ret)
485 return ret;
486
487 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, evict,
488 no_wait_reserve, no_wait_gpu, new_mem);
489 nouveau_fence_unref(&fence);
490 return ret;
491}
492
493static int
494nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
495 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
496{
497 struct nouveau_mem *node = old_mem->mm_node;
498 int ret = RING_SPACE(chan, 10);
499 if (ret == 0) {
500 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
501 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
502 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
503 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
504 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
505 OUT_RING (chan, PAGE_SIZE);
506 OUT_RING (chan, PAGE_SIZE);
507 OUT_RING (chan, PAGE_SIZE);
508 OUT_RING (chan, new_mem->num_pages);
509 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
510 }
511 return ret;
512}
513
514static int
515nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
516{
517 int ret = RING_SPACE(chan, 2);
518 if (ret == 0) {
519 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
520 OUT_RING (chan, handle);
521 }
522 return ret;
523}
524
525static int
526nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
527 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
528{
529 struct nouveau_mem *node = old_mem->mm_node;
530 u64 src_offset = node->vma[0].offset;
531 u64 dst_offset = node->vma[1].offset;
532 u32 page_count = new_mem->num_pages;
533 int ret;
534
535 page_count = new_mem->num_pages;
536 while (page_count) {
537 int line_count = (page_count > 8191) ? 8191 : page_count;
538
539 ret = RING_SPACE(chan, 11);
540 if (ret)
541 return ret;
542
543 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
544 OUT_RING (chan, upper_32_bits(src_offset));
545 OUT_RING (chan, lower_32_bits(src_offset));
546 OUT_RING (chan, upper_32_bits(dst_offset));
547 OUT_RING (chan, lower_32_bits(dst_offset));
548 OUT_RING (chan, PAGE_SIZE);
549 OUT_RING (chan, PAGE_SIZE);
550 OUT_RING (chan, PAGE_SIZE);
551 OUT_RING (chan, line_count);
552 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
553 OUT_RING (chan, 0x00000110);
554
555 page_count -= line_count;
556 src_offset += (PAGE_SIZE * line_count);
557 dst_offset += (PAGE_SIZE * line_count);
558 }
559
560 return 0;
561}
562
563static int
564nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
565 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
566{
567 struct nouveau_mem *node = old_mem->mm_node;
568 u64 src_offset = node->vma[0].offset;
569 u64 dst_offset = node->vma[1].offset;
570 u32 page_count = new_mem->num_pages;
571 int ret;
572
573 page_count = new_mem->num_pages;
574 while (page_count) {
575 int line_count = (page_count > 2047) ? 2047 : page_count;
576
577 ret = RING_SPACE(chan, 12);
578 if (ret)
579 return ret;
580
581 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
582 OUT_RING (chan, upper_32_bits(dst_offset));
583 OUT_RING (chan, lower_32_bits(dst_offset));
584 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
585 OUT_RING (chan, upper_32_bits(src_offset));
586 OUT_RING (chan, lower_32_bits(src_offset));
587 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
588 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
589 OUT_RING (chan, PAGE_SIZE); /* line_length */
590 OUT_RING (chan, line_count);
591 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
592 OUT_RING (chan, 0x00100110);
593
594 page_count -= line_count;
595 src_offset += (PAGE_SIZE * line_count);
596 dst_offset += (PAGE_SIZE * line_count);
597 }
598
599 return 0;
600}
601
602static int
603nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
604 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
605{
606 struct nouveau_mem *node = old_mem->mm_node;
607 u64 src_offset = node->vma[0].offset;
608 u64 dst_offset = node->vma[1].offset;
609 u32 page_count = new_mem->num_pages;
610 int ret;
611
612 page_count = new_mem->num_pages;
613 while (page_count) {
614 int line_count = (page_count > 8191) ? 8191 : page_count;
615
616 ret = RING_SPACE(chan, 11);
617 if (ret)
618 return ret;
619
620 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
621 OUT_RING (chan, upper_32_bits(src_offset));
622 OUT_RING (chan, lower_32_bits(src_offset));
623 OUT_RING (chan, upper_32_bits(dst_offset));
624 OUT_RING (chan, lower_32_bits(dst_offset));
625 OUT_RING (chan, PAGE_SIZE);
626 OUT_RING (chan, PAGE_SIZE);
627 OUT_RING (chan, PAGE_SIZE);
628 OUT_RING (chan, line_count);
629 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
630 OUT_RING (chan, 0x00000110);
631
632 page_count -= line_count;
633 src_offset += (PAGE_SIZE * line_count);
634 dst_offset += (PAGE_SIZE * line_count);
635 }
636
637 return 0;
638}
639
640static int
641nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
642 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
643{
644 struct nouveau_mem *node = old_mem->mm_node;
645 int ret = RING_SPACE(chan, 7);
646 if (ret == 0) {
647 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
648 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
649 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
650 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
651 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
652 OUT_RING (chan, 0x00000000 /* COPY */);
653 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
654 }
655 return ret;
656}
657
658static int
659nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
660 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
661{
662 struct nouveau_mem *node = old_mem->mm_node;
663 int ret = RING_SPACE(chan, 7);
664 if (ret == 0) {
665 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
666 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
667 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
668 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
669 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
670 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
671 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
672 }
673 return ret;
674}
675
676static int
677nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
678{
679 int ret = nouveau_notifier_alloc(chan, NvNotify0, 32, 0xfe0, 0x1000,
680 &chan->m2mf_ntfy);
681 if (ret == 0) {
682 ret = RING_SPACE(chan, 6);
683 if (ret == 0) {
684 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
685 OUT_RING (chan, handle);
686 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
687 OUT_RING (chan, NvNotify0);
688 OUT_RING (chan, NvDmaFB);
689 OUT_RING (chan, NvDmaFB);
690 } else {
691 nouveau_ramht_remove(chan, NvNotify0);
692 }
693 }
694
695 return ret;
696}
697
698static int
699nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
700 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
701{
702 struct nouveau_mem *node = old_mem->mm_node;
703 struct nouveau_bo *nvbo = nouveau_bo(bo);
704 u64 length = (new_mem->num_pages << PAGE_SHIFT);
705 u64 src_offset = node->vma[0].offset;
706 u64 dst_offset = node->vma[1].offset;
707 int ret;
708
709 while (length) {
710 u32 amount, stride, height;
711
712 amount = min(length, (u64)(4 * 1024 * 1024));
713 stride = 16 * 4;
714 height = amount / stride;
715
716 if (new_mem->mem_type == TTM_PL_VRAM &&
717 nouveau_bo_tile_layout(nvbo)) {
718 ret = RING_SPACE(chan, 8);
719 if (ret)
720 return ret;
721
722 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
723 OUT_RING (chan, 0);
724 OUT_RING (chan, 0);
725 OUT_RING (chan, stride);
726 OUT_RING (chan, height);
727 OUT_RING (chan, 1);
728 OUT_RING (chan, 0);
729 OUT_RING (chan, 0);
730 } else {
731 ret = RING_SPACE(chan, 2);
732 if (ret)
733 return ret;
734
735 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
736 OUT_RING (chan, 1);
737 }
738 if (old_mem->mem_type == TTM_PL_VRAM &&
739 nouveau_bo_tile_layout(nvbo)) {
740 ret = RING_SPACE(chan, 8);
741 if (ret)
742 return ret;
743
744 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
745 OUT_RING (chan, 0);
746 OUT_RING (chan, 0);
747 OUT_RING (chan, stride);
748 OUT_RING (chan, height);
749 OUT_RING (chan, 1);
750 OUT_RING (chan, 0);
751 OUT_RING (chan, 0);
752 } else {
753 ret = RING_SPACE(chan, 2);
754 if (ret)
755 return ret;
756
757 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
758 OUT_RING (chan, 1);
759 }
760
761 ret = RING_SPACE(chan, 14);
762 if (ret)
763 return ret;
764
765 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
766 OUT_RING (chan, upper_32_bits(src_offset));
767 OUT_RING (chan, upper_32_bits(dst_offset));
768 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
769 OUT_RING (chan, lower_32_bits(src_offset));
770 OUT_RING (chan, lower_32_bits(dst_offset));
771 OUT_RING (chan, stride);
772 OUT_RING (chan, stride);
773 OUT_RING (chan, stride);
774 OUT_RING (chan, height);
775 OUT_RING (chan, 0x00000101);
776 OUT_RING (chan, 0x00000000);
777 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
778 OUT_RING (chan, 0);
779
780 length -= amount;
781 src_offset += amount;
782 dst_offset += amount;
783 }
784
785 return 0;
786}
787
788static int
789nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
790{
791 int ret = nouveau_notifier_alloc(chan, NvNotify0, 32, 0xfe0, 0x1000,
792 &chan->m2mf_ntfy);
793 if (ret == 0) {
794 ret = RING_SPACE(chan, 4);
795 if (ret == 0) {
796 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
797 OUT_RING (chan, handle);
798 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
799 OUT_RING (chan, NvNotify0);
800 }
801 }
802
803 return ret;
804}
805
806static inline uint32_t
807nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
808 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
809{
810 if (mem->mem_type == TTM_PL_TT)
811 return chan->gart_handle;
812 return chan->vram_handle;
813}
814
815static int
816nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
817 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
818{
819 u32 src_offset = old_mem->start << PAGE_SHIFT;
820 u32 dst_offset = new_mem->start << PAGE_SHIFT;
821 u32 page_count = new_mem->num_pages;
822 int ret;
823
824 ret = RING_SPACE(chan, 3);
825 if (ret)
826 return ret;
827
828 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
829 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
830 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
831
832 page_count = new_mem->num_pages;
833 while (page_count) {
834 int line_count = (page_count > 2047) ? 2047 : page_count;
835
836 ret = RING_SPACE(chan, 11);
837 if (ret)
838 return ret;
839
840 BEGIN_NV04(chan, NvSubCopy,
841 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
842 OUT_RING (chan, src_offset);
843 OUT_RING (chan, dst_offset);
844 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
845 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
846 OUT_RING (chan, PAGE_SIZE); /* line_length */
847 OUT_RING (chan, line_count);
848 OUT_RING (chan, 0x00000101);
849 OUT_RING (chan, 0x00000000);
850 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
851 OUT_RING (chan, 0);
852
853 page_count -= line_count;
854 src_offset += (PAGE_SIZE * line_count);
855 dst_offset += (PAGE_SIZE * line_count);
856 }
857
858 return 0;
859}
860
861static int
862nouveau_vma_getmap(struct nouveau_channel *chan, struct nouveau_bo *nvbo,
863 struct ttm_mem_reg *mem, struct nouveau_vma *vma)
864{
865 struct nouveau_mem *node = mem->mm_node;
866 int ret;
867
868 ret = nouveau_vm_get(chan->vm, mem->num_pages << PAGE_SHIFT,
869 node->page_shift, NV_MEM_ACCESS_RO, vma);
870 if (ret)
871 return ret;
872
873 if (mem->mem_type == TTM_PL_VRAM)
874 nouveau_vm_map(vma, node);
875 else
876 nouveau_vm_map_sg(vma, 0, mem->num_pages << PAGE_SHIFT, node);
877
878 return 0;
879}
880
881static int
882nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
883 bool no_wait_reserve, bool no_wait_gpu,
884 struct ttm_mem_reg *new_mem)
885{
886 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
887 struct nouveau_channel *chan = chan = dev_priv->channel;
888 struct nouveau_bo *nvbo = nouveau_bo(bo);
889 struct ttm_mem_reg *old_mem = &bo->mem;
890 int ret;
891
892 mutex_lock_nested(&chan->mutex, NOUVEAU_KCHANNEL_MUTEX);
893
894 /* create temporary vmas for the transfer and attach them to the
895 * old nouveau_mem node, these will get cleaned up after ttm has
896 * destroyed the ttm_mem_reg
897 */
898 if (dev_priv->card_type >= NV_50) {
899 struct nouveau_mem *node = old_mem->mm_node;
900
901 ret = nouveau_vma_getmap(chan, nvbo, old_mem, &node->vma[0]);
902 if (ret)
903 goto out;
904
905 ret = nouveau_vma_getmap(chan, nvbo, new_mem, &node->vma[1]);
906 if (ret)
907 goto out;
908 }
909
910 ret = dev_priv->ttm.move(chan, bo, &bo->mem, new_mem);
911 if (ret == 0) {
912 ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict,
913 no_wait_reserve,
914 no_wait_gpu, new_mem);
915 }
916
917out:
918 mutex_unlock(&chan->mutex);
919 return ret;
920}
921
922void
923nouveau_bo_move_init(struct nouveau_channel *chan)
924{
925 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
926 static const struct {
927 const char *name;
928 int engine;
929 u32 oclass;
930 int (*exec)(struct nouveau_channel *,
931 struct ttm_buffer_object *,
932 struct ttm_mem_reg *, struct ttm_mem_reg *);
933 int (*init)(struct nouveau_channel *, u32 handle);
934 } _methods[] = {
935 { "COPY", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
936 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
937 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
938 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
939 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
940 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
941 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
942 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
943 {},
944 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
945 }, *mthd = _methods;
946 const char *name = "CPU";
947 int ret;
948
949 do {
950 u32 handle = (mthd->engine << 16) | mthd->oclass;
951 ret = nouveau_gpuobj_gr_new(chan, handle, mthd->oclass);
952 if (ret == 0) {
953 ret = mthd->init(chan, handle);
954 if (ret == 0) {
955 dev_priv->ttm.move = mthd->exec;
956 name = mthd->name;
957 break;
958 }
959 }
960 } while ((++mthd)->exec);
961
962 NV_INFO(chan->dev, "MM: using %s for buffer copies\n", name);
963}
964
965static int
966nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
967 bool no_wait_reserve, bool no_wait_gpu,
968 struct ttm_mem_reg *new_mem)
969{
970 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
971 struct ttm_placement placement;
972 struct ttm_mem_reg tmp_mem;
973 int ret;
974
975 placement.fpfn = placement.lpfn = 0;
976 placement.num_placement = placement.num_busy_placement = 1;
977 placement.placement = placement.busy_placement = &placement_memtype;
978
979 tmp_mem = *new_mem;
980 tmp_mem.mm_node = NULL;
981 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
982 if (ret)
983 return ret;
984
985 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
986 if (ret)
987 goto out;
988
989 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
990 if (ret)
991 goto out;
992
993 ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem);
994out:
995 ttm_bo_mem_put(bo, &tmp_mem);
996 return ret;
997}
998
999static int
1000nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
1001 bool no_wait_reserve, bool no_wait_gpu,
1002 struct ttm_mem_reg *new_mem)
1003{
1004 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
1005 struct ttm_placement placement;
1006 struct ttm_mem_reg tmp_mem;
1007 int ret;
1008
1009 placement.fpfn = placement.lpfn = 0;
1010 placement.num_placement = placement.num_busy_placement = 1;
1011 placement.placement = placement.busy_placement = &placement_memtype;
1012
1013 tmp_mem = *new_mem;
1014 tmp_mem.mm_node = NULL;
1015 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
1016 if (ret)
1017 return ret;
1018
1019 ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem);
1020 if (ret)
1021 goto out;
1022
1023 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, new_mem);
1024 if (ret)
1025 goto out;
1026
1027out:
1028 ttm_bo_mem_put(bo, &tmp_mem);
1029 return ret;
1030}
1031
1032static void
1033nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
1034{
1035 struct nouveau_bo *nvbo = nouveau_bo(bo);
1036 struct nouveau_vma *vma;
1037
1038 /* ttm can now (stupidly) pass the driver bos it didn't create... */
1039 if (bo->destroy != nouveau_bo_del_ttm)
1040 return;
1041
1042 list_for_each_entry(vma, &nvbo->vma_list, head) {
1043 if (new_mem && new_mem->mem_type == TTM_PL_VRAM) {
1044 nouveau_vm_map(vma, new_mem->mm_node);
1045 } else
1046 if (new_mem && new_mem->mem_type == TTM_PL_TT &&
1047 nvbo->page_shift == vma->vm->spg_shift) {
1048 if (((struct nouveau_mem *)new_mem->mm_node)->sg)
1049 nouveau_vm_map_sg_table(vma, 0, new_mem->
1050 num_pages << PAGE_SHIFT,
1051 new_mem->mm_node);
1052 else
1053 nouveau_vm_map_sg(vma, 0, new_mem->
1054 num_pages << PAGE_SHIFT,
1055 new_mem->mm_node);
1056 } else {
1057 nouveau_vm_unmap(vma);
1058 }
1059 }
1060}
1061
1062static int
1063nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
1064 struct nouveau_tile_reg **new_tile)
1065{
1066 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
1067 struct drm_device *dev = dev_priv->dev;
1068 struct nouveau_bo *nvbo = nouveau_bo(bo);
1069 u64 offset = new_mem->start << PAGE_SHIFT;
1070
1071 *new_tile = NULL;
1072 if (new_mem->mem_type != TTM_PL_VRAM)
1073 return 0;
1074
1075 if (dev_priv->card_type >= NV_10) {
1076 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
1077 nvbo->tile_mode,
1078 nvbo->tile_flags);
1079 }
1080
1081 return 0;
1082}
1083
1084static void
1085nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1086 struct nouveau_tile_reg *new_tile,
1087 struct nouveau_tile_reg **old_tile)
1088{
1089 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
1090 struct drm_device *dev = dev_priv->dev;
1091
1092 nv10_mem_put_tile_region(dev, *old_tile, bo->sync_obj);
1093 *old_tile = new_tile;
1094}
1095
1096static int
1097nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
1098 bool no_wait_reserve, bool no_wait_gpu,
1099 struct ttm_mem_reg *new_mem)
1100{
1101 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
1102 struct nouveau_bo *nvbo = nouveau_bo(bo);
1103 struct ttm_mem_reg *old_mem = &bo->mem;
1104 struct nouveau_tile_reg *new_tile = NULL;
1105 int ret = 0;
1106
1107 if (dev_priv->card_type < NV_50) {
1108 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
1109 if (ret)
1110 return ret;
1111 }
1112
1113 /* Fake bo copy. */
1114 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1115 BUG_ON(bo->mem.mm_node != NULL);
1116 bo->mem = *new_mem;
1117 new_mem->mm_node = NULL;
1118 goto out;
1119 }
1120
1121 /* CPU copy if we have no accelerated method available */
1122 if (!dev_priv->ttm.move) {
1123 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
1124 goto out;
1125 }
1126
1127 /* Hardware assisted copy. */
1128 if (new_mem->mem_type == TTM_PL_SYSTEM)
1129 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
1130 else if (old_mem->mem_type == TTM_PL_SYSTEM)
1131 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
1132 else
1133 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
1134
1135 if (!ret)
1136 goto out;
1137
1138 /* Fallback to software copy. */
1139 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
1140
1141out:
1142 if (dev_priv->card_type < NV_50) {
1143 if (ret)
1144 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1145 else
1146 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1147 }
1148
1149 return ret;
1150}
1151
1152static int
1153nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1154{
1155 return 0;
1156}
1157
1158static int
1159nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1160{
1161 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
1162 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
1163 struct drm_device *dev = dev_priv->dev;
1164 int ret;
1165
1166 mem->bus.addr = NULL;
1167 mem->bus.offset = 0;
1168 mem->bus.size = mem->num_pages << PAGE_SHIFT;
1169 mem->bus.base = 0;
1170 mem->bus.is_iomem = false;
1171 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
1172 return -EINVAL;
1173 switch (mem->mem_type) {
1174 case TTM_PL_SYSTEM:
1175 /* System memory */
1176 return 0;
1177 case TTM_PL_TT:
1178#if __OS_HAS_AGP
1179 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
1180 mem->bus.offset = mem->start << PAGE_SHIFT;
1181 mem->bus.base = dev_priv->gart_info.aper_base;
1182 mem->bus.is_iomem = true;
1183 }
1184#endif
1185 break;
1186 case TTM_PL_VRAM:
1187 {
1188 struct nouveau_mem *node = mem->mm_node;
1189 u8 page_shift;
1190
1191 if (!dev_priv->bar1_vm) {
1192 mem->bus.offset = mem->start << PAGE_SHIFT;
1193 mem->bus.base = pci_resource_start(dev->pdev, 1);
1194 mem->bus.is_iomem = true;
1195 break;
1196 }
1197
1198 if (dev_priv->card_type >= NV_C0)
1199 page_shift = node->page_shift;
1200 else
1201 page_shift = 12;
1202
1203 ret = nouveau_vm_get(dev_priv->bar1_vm, mem->bus.size,
1204 page_shift, NV_MEM_ACCESS_RW,
1205 &node->bar_vma);
1206 if (ret)
1207 return ret;
1208
1209 nouveau_vm_map(&node->bar_vma, node);
1210 if (ret) {
1211 nouveau_vm_put(&node->bar_vma);
1212 return ret;
1213 }
1214
1215 mem->bus.offset = node->bar_vma.offset;
1216 if (dev_priv->card_type == NV_50) /*XXX*/
1217 mem->bus.offset -= 0x0020000000ULL;
1218 mem->bus.base = pci_resource_start(dev->pdev, 1);
1219 mem->bus.is_iomem = true;
1220 }
1221 break;
1222 default:
1223 return -EINVAL;
1224 }
1225 return 0;
1226}
1227
1228static void
1229nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1230{
1231 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
1232 struct nouveau_mem *node = mem->mm_node;
1233
1234 if (!dev_priv->bar1_vm || mem->mem_type != TTM_PL_VRAM)
1235 return;
1236
1237 if (!node->bar_vma.node)
1238 return;
1239
1240 nouveau_vm_unmap(&node->bar_vma);
1241 nouveau_vm_put(&node->bar_vma);
1242}
1243
1244static int
1245nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1246{
1247 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
1248 struct nouveau_bo *nvbo = nouveau_bo(bo);
1249
1250 /* as long as the bo isn't in vram, and isn't tiled, we've got
1251 * nothing to do here.
1252 */
1253 if (bo->mem.mem_type != TTM_PL_VRAM) {
1254 if (dev_priv->card_type < NV_50 ||
1255 !nouveau_bo_tile_layout(nvbo))
1256 return 0;
1257 }
1258
1259 /* make sure bo is in mappable vram */
1260 if (bo->mem.start + bo->mem.num_pages < dev_priv->fb_mappable_pages)
1261 return 0;
1262
1263
1264 nvbo->placement.fpfn = 0;
1265 nvbo->placement.lpfn = dev_priv->fb_mappable_pages;
1266 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
1267 return nouveau_bo_validate(nvbo, false, true, false);
1268}
1269
1270static int
1271nouveau_ttm_tt_populate(struct ttm_tt *ttm)
1272{
1273 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1274 struct drm_nouveau_private *dev_priv;
1275 struct drm_device *dev;
1276 unsigned i;
1277 int r;
1278 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1279
1280 if (ttm->state != tt_unpopulated)
1281 return 0;
1282
1283 if (slave && ttm->sg) {
1284 /* make userspace faulting work */
1285 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1286 ttm_dma->dma_address, ttm->num_pages);
1287 ttm->state = tt_unbound;
1288 return 0;
1289 }
1290
1291 dev_priv = nouveau_bdev(ttm->bdev);
1292 dev = dev_priv->dev;
1293
1294#if __OS_HAS_AGP
1295 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
1296 return ttm_agp_tt_populate(ttm);
1297 }
1298#endif
1299
1300#ifdef CONFIG_SWIOTLB
1301 if (swiotlb_nr_tbl()) {
1302 return ttm_dma_populate((void *)ttm, dev->dev);
1303 }
1304#endif
1305
1306 r = ttm_pool_populate(ttm);
1307 if (r) {
1308 return r;
1309 }
1310
1311 for (i = 0; i < ttm->num_pages; i++) {
1312 ttm_dma->dma_address[i] = pci_map_page(dev->pdev, ttm->pages[i],
1313 0, PAGE_SIZE,
1314 PCI_DMA_BIDIRECTIONAL);
1315 if (pci_dma_mapping_error(dev->pdev, ttm_dma->dma_address[i])) {
1316 while (--i) {
1317 pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
1318 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1319 ttm_dma->dma_address[i] = 0;
1320 }
1321 ttm_pool_unpopulate(ttm);
1322 return -EFAULT;
1323 }
1324 }
1325 return 0;
1326}
1327
1328static void
1329nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1330{
1331 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1332 struct drm_nouveau_private *dev_priv;
1333 struct drm_device *dev;
1334 unsigned i;
1335 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1336
1337 if (slave)
1338 return;
1339
1340 dev_priv = nouveau_bdev(ttm->bdev);
1341 dev = dev_priv->dev;
1342
1343#if __OS_HAS_AGP
1344 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
1345 ttm_agp_tt_unpopulate(ttm);
1346 return;
1347 }
1348#endif
1349
1350#ifdef CONFIG_SWIOTLB
1351 if (swiotlb_nr_tbl()) {
1352 ttm_dma_unpopulate((void *)ttm, dev->dev);
1353 return;
1354 }
1355#endif
1356
1357 for (i = 0; i < ttm->num_pages; i++) {
1358 if (ttm_dma->dma_address[i]) {
1359 pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
1360 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1361 }
1362 }
1363
1364 ttm_pool_unpopulate(ttm);
1365}
1366
1367void
1368nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
1369{
1370 struct nouveau_fence *old_fence = NULL;
1371
1372 if (likely(fence))
1373 nouveau_fence_ref(fence);
1374
1375 spin_lock(&nvbo->bo.bdev->fence_lock);
1376 old_fence = nvbo->bo.sync_obj;
1377 nvbo->bo.sync_obj = fence;
1378 spin_unlock(&nvbo->bo.bdev->fence_lock);
1379
1380 nouveau_fence_unref(&old_fence);
1381}
1382
1383static void
1384nouveau_bo_fence_unref(void **sync_obj)
1385{
1386 nouveau_fence_unref((struct nouveau_fence **)sync_obj);
1387}
1388
1389static void *
1390nouveau_bo_fence_ref(void *sync_obj)
1391{
1392 return nouveau_fence_ref(sync_obj);
1393}
1394
1395static bool
1396nouveau_bo_fence_signalled(void *sync_obj, void *sync_arg)
1397{
1398 return nouveau_fence_done(sync_obj);
1399}
1400
1401static int
1402nouveau_bo_fence_wait(void *sync_obj, void *sync_arg, bool lazy, bool intr)
1403{
1404 return nouveau_fence_wait(sync_obj, lazy, intr);
1405}
1406
1407static int
1408nouveau_bo_fence_flush(void *sync_obj, void *sync_arg)
1409{
1410 return 0;
1411}
1412
1413struct ttm_bo_driver nouveau_bo_driver = {
1414 .ttm_tt_create = &nouveau_ttm_tt_create,
1415 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1416 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1417 .invalidate_caches = nouveau_bo_invalidate_caches,
1418 .init_mem_type = nouveau_bo_init_mem_type,
1419 .evict_flags = nouveau_bo_evict_flags,
1420 .move_notify = nouveau_bo_move_ntfy,
1421 .move = nouveau_bo_move,
1422 .verify_access = nouveau_bo_verify_access,
1423 .sync_obj_signaled = nouveau_bo_fence_signalled,
1424 .sync_obj_wait = nouveau_bo_fence_wait,
1425 .sync_obj_flush = nouveau_bo_fence_flush,
1426 .sync_obj_unref = nouveau_bo_fence_unref,
1427 .sync_obj_ref = nouveau_bo_fence_ref,
1428 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1429 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1430 .io_mem_free = &nouveau_ttm_io_mem_free,
1431};
1432
1433struct nouveau_vma *
1434nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm)
1435{
1436 struct nouveau_vma *vma;
1437 list_for_each_entry(vma, &nvbo->vma_list, head) {
1438 if (vma->vm == vm)
1439 return vma;
1440 }
1441
1442 return NULL;
1443}
1444
1445int
1446nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
1447 struct nouveau_vma *vma)
1448{
1449 const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1450 struct nouveau_mem *node = nvbo->bo.mem.mm_node;
1451 int ret;
1452
1453 ret = nouveau_vm_get(vm, size, nvbo->page_shift,
1454 NV_MEM_ACCESS_RW, vma);
1455 if (ret)
1456 return ret;
1457
1458 if (nvbo->bo.mem.mem_type == TTM_PL_VRAM)
1459 nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
1460 else if (nvbo->bo.mem.mem_type == TTM_PL_TT) {
1461 if (node->sg)
1462 nouveau_vm_map_sg_table(vma, 0, size, node);
1463 else
1464 nouveau_vm_map_sg(vma, 0, size, node);
1465 }
1466
1467 list_add_tail(&vma->head, &nvbo->vma_list);
1468 vma->refcount = 1;
1469 return 0;
1470}
1471
1472void
1473nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
1474{
1475 if (vma->node) {
1476 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM) {
1477 spin_lock(&nvbo->bo.bdev->fence_lock);
1478 ttm_bo_wait(&nvbo->bo, false, false, false);
1479 spin_unlock(&nvbo->bo.bdev->fence_lock);
1480 nouveau_vm_unmap(vma);
1481 }
1482
1483 nouveau_vm_put(vma);
1484 list_del(&vma->head);
1485 }
1486}