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1/*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30#include <linux/dma-mapping.h>
31#include <drm/ttm/ttm_tt.h>
32
33#include "nouveau_drv.h"
34#include "nouveau_chan.h"
35#include "nouveau_fence.h"
36
37#include "nouveau_bo.h"
38#include "nouveau_ttm.h"
39#include "nouveau_gem.h"
40#include "nouveau_mem.h"
41#include "nouveau_vmm.h"
42
43#include <nvif/class.h>
44#include <nvif/if500b.h>
45#include <nvif/if900b.h>
46
47static int nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
48 struct ttm_resource *reg);
49static void nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm);
50
51/*
52 * NV10-NV40 tiling helpers
53 */
54
55static void
56nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
57 u32 addr, u32 size, u32 pitch, u32 flags)
58{
59 struct nouveau_drm *drm = nouveau_drm(dev);
60 int i = reg - drm->tile.reg;
61 struct nvkm_fb *fb = nvxx_fb(drm);
62 struct nvkm_fb_tile *tile = &fb->tile.region[i];
63
64 nouveau_fence_unref(®->fence);
65
66 if (tile->pitch)
67 nvkm_fb_tile_fini(fb, i, tile);
68
69 if (pitch)
70 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
71
72 nvkm_fb_tile_prog(fb, i, tile);
73}
74
75static struct nouveau_drm_tile *
76nv10_bo_get_tile_region(struct drm_device *dev, int i)
77{
78 struct nouveau_drm *drm = nouveau_drm(dev);
79 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
80
81 spin_lock(&drm->tile.lock);
82
83 if (!tile->used &&
84 (!tile->fence || nouveau_fence_done(tile->fence)))
85 tile->used = true;
86 else
87 tile = NULL;
88
89 spin_unlock(&drm->tile.lock);
90 return tile;
91}
92
93static void
94nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
95 struct dma_fence *fence)
96{
97 struct nouveau_drm *drm = nouveau_drm(dev);
98
99 if (tile) {
100 spin_lock(&drm->tile.lock);
101 tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
102 tile->used = false;
103 spin_unlock(&drm->tile.lock);
104 }
105}
106
107static struct nouveau_drm_tile *
108nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
109 u32 size, u32 pitch, u32 zeta)
110{
111 struct nouveau_drm *drm = nouveau_drm(dev);
112 struct nvkm_fb *fb = nvxx_fb(drm);
113 struct nouveau_drm_tile *tile, *found = NULL;
114 int i;
115
116 for (i = 0; i < fb->tile.regions; i++) {
117 tile = nv10_bo_get_tile_region(dev, i);
118
119 if (pitch && !found) {
120 found = tile;
121 continue;
122
123 } else if (tile && fb->tile.region[i].pitch) {
124 /* Kill an unused tile region. */
125 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
126 }
127
128 nv10_bo_put_tile_region(dev, tile, NULL);
129 }
130
131 if (found)
132 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
133 return found;
134}
135
136static void
137nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
138{
139 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
140 struct drm_device *dev = drm->dev;
141 struct nouveau_bo *nvbo = nouveau_bo(bo);
142
143 WARN_ON(nvbo->bo.pin_count > 0);
144 nouveau_bo_del_io_reserve_lru(bo);
145 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
146
147 /*
148 * If nouveau_bo_new() allocated this buffer, the GEM object was never
149 * initialized, so don't attempt to release it.
150 */
151 if (bo->base.dev) {
152 /* Gem objects not being shared with other VMs get their
153 * dma_resv from a root GEM object.
154 */
155 if (nvbo->no_share)
156 drm_gem_object_put(nvbo->r_obj);
157
158 drm_gem_object_release(&bo->base);
159 } else {
160 dma_resv_fini(&bo->base._resv);
161 }
162
163 kfree(nvbo);
164}
165
166static inline u64
167roundup_64(u64 x, u32 y)
168{
169 x += y - 1;
170 do_div(x, y);
171 return x * y;
172}
173
174static void
175nouveau_bo_fixup_align(struct nouveau_bo *nvbo, int *align, u64 *size)
176{
177 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
178 struct nvif_device *device = &drm->client.device;
179
180 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
181 if (nvbo->mode) {
182 if (device->info.chipset >= 0x40) {
183 *align = 65536;
184 *size = roundup_64(*size, 64 * nvbo->mode);
185
186 } else if (device->info.chipset >= 0x30) {
187 *align = 32768;
188 *size = roundup_64(*size, 64 * nvbo->mode);
189
190 } else if (device->info.chipset >= 0x20) {
191 *align = 16384;
192 *size = roundup_64(*size, 64 * nvbo->mode);
193
194 } else if (device->info.chipset >= 0x10) {
195 *align = 16384;
196 *size = roundup_64(*size, 32 * nvbo->mode);
197 }
198 }
199 } else {
200 *size = roundup_64(*size, (1 << nvbo->page));
201 *align = max((1 << nvbo->page), *align);
202 }
203
204 *size = roundup_64(*size, PAGE_SIZE);
205}
206
207struct nouveau_bo *
208nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain,
209 u32 tile_mode, u32 tile_flags, bool internal)
210{
211 struct nouveau_drm *drm = cli->drm;
212 struct nouveau_bo *nvbo;
213 struct nvif_mmu *mmu = &cli->mmu;
214 struct nvif_vmm *vmm = &nouveau_cli_vmm(cli)->vmm;
215 int i, pi = -1;
216
217 if (!*size) {
218 NV_WARN(drm, "skipped size %016llx\n", *size);
219 return ERR_PTR(-EINVAL);
220 }
221
222 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
223 if (!nvbo)
224 return ERR_PTR(-ENOMEM);
225
226 INIT_LIST_HEAD(&nvbo->head);
227 INIT_LIST_HEAD(&nvbo->entry);
228 INIT_LIST_HEAD(&nvbo->vma_list);
229 nvbo->bo.bdev = &drm->ttm.bdev;
230
231 /* This is confusing, and doesn't actually mean we want an uncached
232 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
233 * into in nouveau_gem_new().
234 */
235 if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) {
236 /* Determine if we can get a cache-coherent map, forcing
237 * uncached mapping if we can't.
238 */
239 if (!nouveau_drm_use_coherent_gpu_mapping(drm))
240 nvbo->force_coherent = true;
241 }
242
243 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
244
245 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
246 nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
247 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
248 kfree(nvbo);
249 return ERR_PTR(-EINVAL);
250 }
251
252 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind;
253 } else if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
254 nvbo->kind = (tile_flags & 0x00007f00) >> 8;
255 nvbo->comp = (tile_flags & 0x00030000) >> 16;
256 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
257 kfree(nvbo);
258 return ERR_PTR(-EINVAL);
259 }
260 } else {
261 nvbo->zeta = (tile_flags & 0x00000007);
262 }
263 nvbo->mode = tile_mode;
264
265 if (!nouveau_cli_uvmm(cli) || internal) {
266 /* Determine the desirable target GPU page size for the buffer. */
267 for (i = 0; i < vmm->page_nr; i++) {
268 /* Because we cannot currently allow VMM maps to fail
269 * during buffer migration, we need to determine page
270 * size for the buffer up-front, and pre-allocate its
271 * page tables.
272 *
273 * Skip page sizes that can't support needed domains.
274 */
275 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE &&
276 (domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
277 continue;
278 if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
279 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
280 continue;
281
282 /* Select this page size if it's the first that supports
283 * the potential memory domains, or when it's compatible
284 * with the requested compression settings.
285 */
286 if (pi < 0 || !nvbo->comp || vmm->page[i].comp)
287 pi = i;
288
289 /* Stop once the buffer is larger than the current page size. */
290 if (*size >= 1ULL << vmm->page[i].shift)
291 break;
292 }
293
294 if (WARN_ON(pi < 0)) {
295 kfree(nvbo);
296 return ERR_PTR(-EINVAL);
297 }
298
299 /* Disable compression if suitable settings couldn't be found. */
300 if (nvbo->comp && !vmm->page[pi].comp) {
301 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100)
302 nvbo->kind = mmu->kind[nvbo->kind];
303 nvbo->comp = 0;
304 }
305 nvbo->page = vmm->page[pi].shift;
306 } else {
307 /* Determine the desirable target GPU page size for the buffer. */
308 for (i = 0; i < vmm->page_nr; i++) {
309 /* Because we cannot currently allow VMM maps to fail
310 * during buffer migration, we need to determine page
311 * size for the buffer up-front, and pre-allocate its
312 * page tables.
313 *
314 * Skip page sizes that can't support needed domains.
315 */
316 if ((domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
317 continue;
318 if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
319 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
320 continue;
321
322 /* pick the last one as it will be smallest. */
323 pi = i;
324
325 /* Stop once the buffer is larger than the current page size. */
326 if (*size >= 1ULL << vmm->page[i].shift)
327 break;
328 }
329 if (WARN_ON(pi < 0)) {
330 kfree(nvbo);
331 return ERR_PTR(-EINVAL);
332 }
333 nvbo->page = vmm->page[pi].shift;
334 }
335
336 nouveau_bo_fixup_align(nvbo, align, size);
337
338 return nvbo;
339}
340
341int
342nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 domain,
343 struct sg_table *sg, struct dma_resv *robj)
344{
345 int type = sg ? ttm_bo_type_sg : ttm_bo_type_device;
346 int ret;
347 struct ttm_operation_ctx ctx = {
348 .interruptible = false,
349 .no_wait_gpu = false,
350 .resv = robj,
351 };
352
353 nouveau_bo_placement_set(nvbo, domain, 0);
354 INIT_LIST_HEAD(&nvbo->io_reserve_lru);
355
356 ret = ttm_bo_init_reserved(nvbo->bo.bdev, &nvbo->bo, type,
357 &nvbo->placement, align >> PAGE_SHIFT, &ctx,
358 sg, robj, nouveau_bo_del_ttm);
359 if (ret) {
360 /* ttm will call nouveau_bo_del_ttm if it fails.. */
361 return ret;
362 }
363
364 if (!robj)
365 ttm_bo_unreserve(&nvbo->bo);
366
367 return 0;
368}
369
370int
371nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
372 uint32_t domain, uint32_t tile_mode, uint32_t tile_flags,
373 struct sg_table *sg, struct dma_resv *robj,
374 struct nouveau_bo **pnvbo)
375{
376 struct nouveau_bo *nvbo;
377 int ret;
378
379 nvbo = nouveau_bo_alloc(cli, &size, &align, domain, tile_mode,
380 tile_flags, true);
381 if (IS_ERR(nvbo))
382 return PTR_ERR(nvbo);
383
384 nvbo->bo.base.size = size;
385 dma_resv_init(&nvbo->bo.base._resv);
386 drm_vma_node_reset(&nvbo->bo.base.vma_node);
387
388 /* This must be called before ttm_bo_init_reserved(). Subsequent
389 * bo_move() callbacks might already iterate the GEMs GPUVA list.
390 */
391 drm_gem_gpuva_init(&nvbo->bo.base);
392
393 ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj);
394 if (ret)
395 return ret;
396
397 *pnvbo = nvbo;
398 return 0;
399}
400
401static void
402set_placement_range(struct nouveau_bo *nvbo, uint32_t domain)
403{
404 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
405 u64 vram_size = drm->client.device.info.ram_size;
406 unsigned i, fpfn, lpfn;
407
408 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
409 nvbo->mode && (domain & NOUVEAU_GEM_DOMAIN_VRAM) &&
410 nvbo->bo.base.size < vram_size / 4) {
411 /*
412 * Make sure that the color and depth buffers are handled
413 * by independent memory controller units. Up to a 9x
414 * speed up when alpha-blending and depth-test are enabled
415 * at the same time.
416 */
417 if (nvbo->zeta) {
418 fpfn = (vram_size / 2) >> PAGE_SHIFT;
419 lpfn = ~0;
420 } else {
421 fpfn = 0;
422 lpfn = (vram_size / 2) >> PAGE_SHIFT;
423 }
424 for (i = 0; i < nvbo->placement.num_placement; ++i) {
425 nvbo->placements[i].fpfn = fpfn;
426 nvbo->placements[i].lpfn = lpfn;
427 }
428 }
429}
430
431void
432nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t domain,
433 uint32_t busy)
434{
435 unsigned int *n = &nvbo->placement.num_placement;
436 struct ttm_place *pl = nvbo->placements;
437
438 domain |= busy;
439
440 *n = 0;
441 if (domain & NOUVEAU_GEM_DOMAIN_VRAM) {
442 pl[*n].mem_type = TTM_PL_VRAM;
443 pl[*n].flags = busy & NOUVEAU_GEM_DOMAIN_VRAM ?
444 TTM_PL_FLAG_FALLBACK : 0;
445 (*n)++;
446 }
447 if (domain & NOUVEAU_GEM_DOMAIN_GART) {
448 pl[*n].mem_type = TTM_PL_TT;
449 pl[*n].flags = busy & NOUVEAU_GEM_DOMAIN_GART ?
450 TTM_PL_FLAG_FALLBACK : 0;
451 (*n)++;
452 }
453 if (domain & NOUVEAU_GEM_DOMAIN_CPU) {
454 pl[*n].mem_type = TTM_PL_SYSTEM;
455 pl[*n].flags = busy & NOUVEAU_GEM_DOMAIN_CPU ?
456 TTM_PL_FLAG_FALLBACK : 0;
457 (*n)++;
458 }
459
460 nvbo->placement.placement = nvbo->placements;
461 set_placement_range(nvbo, domain);
462}
463
464int nouveau_bo_pin_locked(struct nouveau_bo *nvbo, uint32_t domain, bool contig)
465{
466 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
467 struct ttm_buffer_object *bo = &nvbo->bo;
468 bool force = false, evict = false;
469 int ret = 0;
470
471 dma_resv_assert_held(bo->base.resv);
472
473 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
474 domain == NOUVEAU_GEM_DOMAIN_VRAM && contig) {
475 if (!nvbo->contig) {
476 nvbo->contig = true;
477 force = true;
478 evict = true;
479 }
480 }
481
482 if (nvbo->bo.pin_count) {
483 bool error = evict;
484
485 switch (bo->resource->mem_type) {
486 case TTM_PL_VRAM:
487 error |= !(domain & NOUVEAU_GEM_DOMAIN_VRAM);
488 break;
489 case TTM_PL_TT:
490 error |= !(domain & NOUVEAU_GEM_DOMAIN_GART);
491 break;
492 default:
493 break;
494 }
495
496 if (error) {
497 NV_ERROR(drm, "bo %p pinned elsewhere: "
498 "0x%08x vs 0x%08x\n", bo,
499 bo->resource->mem_type, domain);
500 ret = -EBUSY;
501 }
502 ttm_bo_pin(&nvbo->bo);
503 goto out;
504 }
505
506 if (evict) {
507 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
508 ret = nouveau_bo_validate(nvbo, false, false);
509 if (ret)
510 goto out;
511 }
512
513 nouveau_bo_placement_set(nvbo, domain, 0);
514 ret = nouveau_bo_validate(nvbo, false, false);
515 if (ret)
516 goto out;
517
518 ttm_bo_pin(&nvbo->bo);
519
520 switch (bo->resource->mem_type) {
521 case TTM_PL_VRAM:
522 drm->gem.vram_available -= bo->base.size;
523 break;
524 case TTM_PL_TT:
525 drm->gem.gart_available -= bo->base.size;
526 break;
527 default:
528 break;
529 }
530
531out:
532 if (force && ret)
533 nvbo->contig = false;
534 return ret;
535}
536
537void nouveau_bo_unpin_locked(struct nouveau_bo *nvbo)
538{
539 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
540 struct ttm_buffer_object *bo = &nvbo->bo;
541
542 dma_resv_assert_held(bo->base.resv);
543
544 ttm_bo_unpin(&nvbo->bo);
545 if (!nvbo->bo.pin_count) {
546 switch (bo->resource->mem_type) {
547 case TTM_PL_VRAM:
548 drm->gem.vram_available += bo->base.size;
549 break;
550 case TTM_PL_TT:
551 drm->gem.gart_available += bo->base.size;
552 break;
553 default:
554 break;
555 }
556 }
557}
558
559int nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, bool contig)
560{
561 struct ttm_buffer_object *bo = &nvbo->bo;
562 int ret;
563
564 ret = ttm_bo_reserve(bo, false, false, NULL);
565 if (ret)
566 return ret;
567 ret = nouveau_bo_pin_locked(nvbo, domain, contig);
568 ttm_bo_unreserve(bo);
569
570 return ret;
571}
572
573int nouveau_bo_unpin(struct nouveau_bo *nvbo)
574{
575 struct ttm_buffer_object *bo = &nvbo->bo;
576 int ret;
577
578 ret = ttm_bo_reserve(bo, false, false, NULL);
579 if (ret)
580 return ret;
581 nouveau_bo_unpin_locked(nvbo);
582 ttm_bo_unreserve(bo);
583
584 return 0;
585}
586
587int
588nouveau_bo_map(struct nouveau_bo *nvbo)
589{
590 int ret;
591
592 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
593 if (ret)
594 return ret;
595
596 ret = ttm_bo_kmap(&nvbo->bo, 0, PFN_UP(nvbo->bo.base.size), &nvbo->kmap);
597
598 ttm_bo_unreserve(&nvbo->bo);
599 return ret;
600}
601
602void
603nouveau_bo_unmap(struct nouveau_bo *nvbo)
604{
605 if (!nvbo)
606 return;
607
608 ttm_bo_kunmap(&nvbo->kmap);
609}
610
611void
612nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
613{
614 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
615 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
616 int i, j;
617
618 if (!ttm_dma || !ttm_dma->dma_address)
619 return;
620 if (!ttm_dma->pages) {
621 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma);
622 return;
623 }
624
625 /* Don't waste time looping if the object is coherent */
626 if (nvbo->force_coherent)
627 return;
628
629 i = 0;
630 while (i < ttm_dma->num_pages) {
631 struct page *p = ttm_dma->pages[i];
632 size_t num_pages = 1;
633
634 for (j = i + 1; j < ttm_dma->num_pages; ++j) {
635 if (++p != ttm_dma->pages[j])
636 break;
637
638 ++num_pages;
639 }
640 dma_sync_single_for_device(drm->dev->dev,
641 ttm_dma->dma_address[i],
642 num_pages * PAGE_SIZE, DMA_TO_DEVICE);
643 i += num_pages;
644 }
645}
646
647void
648nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
649{
650 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
651 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
652 int i, j;
653
654 if (!ttm_dma || !ttm_dma->dma_address)
655 return;
656 if (!ttm_dma->pages) {
657 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma);
658 return;
659 }
660
661 /* Don't waste time looping if the object is coherent */
662 if (nvbo->force_coherent)
663 return;
664
665 i = 0;
666 while (i < ttm_dma->num_pages) {
667 struct page *p = ttm_dma->pages[i];
668 size_t num_pages = 1;
669
670 for (j = i + 1; j < ttm_dma->num_pages; ++j) {
671 if (++p != ttm_dma->pages[j])
672 break;
673
674 ++num_pages;
675 }
676
677 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
678 num_pages * PAGE_SIZE, DMA_FROM_DEVICE);
679 i += num_pages;
680 }
681}
682
683void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo)
684{
685 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
686 struct nouveau_bo *nvbo = nouveau_bo(bo);
687
688 mutex_lock(&drm->ttm.io_reserve_mutex);
689 list_move_tail(&nvbo->io_reserve_lru, &drm->ttm.io_reserve_lru);
690 mutex_unlock(&drm->ttm.io_reserve_mutex);
691}
692
693void nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object *bo)
694{
695 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
696 struct nouveau_bo *nvbo = nouveau_bo(bo);
697
698 mutex_lock(&drm->ttm.io_reserve_mutex);
699 list_del_init(&nvbo->io_reserve_lru);
700 mutex_unlock(&drm->ttm.io_reserve_mutex);
701}
702
703int
704nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
705 bool no_wait_gpu)
706{
707 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
708 int ret;
709
710 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
711 if (ret)
712 return ret;
713
714 nouveau_bo_sync_for_device(nvbo);
715
716 return 0;
717}
718
719void
720nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
721{
722 bool is_iomem;
723 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
724
725 mem += index;
726
727 if (is_iomem)
728 iowrite16_native(val, (void __force __iomem *)mem);
729 else
730 *mem = val;
731}
732
733u32
734nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
735{
736 bool is_iomem;
737 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
738
739 mem += index;
740
741 if (is_iomem)
742 return ioread32_native((void __force __iomem *)mem);
743 else
744 return *mem;
745}
746
747void
748nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
749{
750 bool is_iomem;
751 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
752
753 mem += index;
754
755 if (is_iomem)
756 iowrite32_native(val, (void __force __iomem *)mem);
757 else
758 *mem = val;
759}
760
761static struct ttm_tt *
762nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags)
763{
764#if IS_ENABLED(CONFIG_AGP)
765 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
766
767 if (drm->agp.bridge) {
768 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags);
769 }
770#endif
771
772 return nouveau_sgdma_create_ttm(bo, page_flags);
773}
774
775static int
776nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
777 struct ttm_resource *reg)
778{
779#if IS_ENABLED(CONFIG_AGP)
780 struct nouveau_drm *drm = nouveau_bdev(bdev);
781#endif
782 if (!reg)
783 return -EINVAL;
784#if IS_ENABLED(CONFIG_AGP)
785 if (drm->agp.bridge)
786 return ttm_agp_bind(ttm, reg);
787#endif
788 return nouveau_sgdma_bind(bdev, ttm, reg);
789}
790
791static void
792nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm)
793{
794#if IS_ENABLED(CONFIG_AGP)
795 struct nouveau_drm *drm = nouveau_bdev(bdev);
796
797 if (drm->agp.bridge) {
798 ttm_agp_unbind(ttm);
799 return;
800 }
801#endif
802 nouveau_sgdma_unbind(bdev, ttm);
803}
804
805static void
806nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
807{
808 struct nouveau_bo *nvbo = nouveau_bo(bo);
809
810 switch (bo->resource->mem_type) {
811 case TTM_PL_VRAM:
812 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART,
813 NOUVEAU_GEM_DOMAIN_CPU);
814 break;
815 default:
816 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_CPU, 0);
817 break;
818 }
819
820 *pl = nvbo->placement;
821}
822
823static int
824nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
825 struct ttm_resource *reg)
826{
827 struct nouveau_mem *old_mem = nouveau_mem(bo->resource);
828 struct nouveau_mem *new_mem = nouveau_mem(reg);
829 struct nvif_vmm *vmm = &drm->client.vmm.vmm;
830 int ret;
831
832 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0,
833 old_mem->mem.size, &old_mem->vma[0]);
834 if (ret)
835 return ret;
836
837 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0,
838 new_mem->mem.size, &old_mem->vma[1]);
839 if (ret)
840 goto done;
841
842 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
843 if (ret)
844 goto done;
845
846 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
847done:
848 if (ret) {
849 nvif_vmm_put(vmm, &old_mem->vma[1]);
850 nvif_vmm_put(vmm, &old_mem->vma[0]);
851 }
852 return 0;
853}
854
855static int
856nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict,
857 struct ttm_operation_ctx *ctx,
858 struct ttm_resource *new_reg)
859{
860 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
861 struct nouveau_channel *chan = drm->ttm.chan;
862 struct nouveau_cli *cli = chan->cli;
863 struct nouveau_fence *fence;
864 int ret;
865
866 /* create temporary vmas for the transfer and attach them to the
867 * old nvkm_mem node, these will get cleaned up after ttm has
868 * destroyed the ttm_resource
869 */
870 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
871 ret = nouveau_bo_move_prep(drm, bo, new_reg);
872 if (ret)
873 return ret;
874 }
875
876 if (drm_drv_uses_atomic_modeset(drm->dev))
877 mutex_lock(&cli->mutex);
878 else
879 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
880
881 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, ctx->interruptible);
882 if (ret)
883 goto out_unlock;
884
885 ret = drm->ttm.move(chan, bo, bo->resource, new_reg);
886 if (ret)
887 goto out_unlock;
888
889 ret = nouveau_fence_new(&fence, chan);
890 if (ret)
891 goto out_unlock;
892
893 /* TODO: figure out a better solution here
894 *
895 * wait on the fence here explicitly as going through
896 * ttm_bo_move_accel_cleanup somehow doesn't seem to do it.
897 *
898 * Without this the operation can timeout and we'll fallback to a
899 * software copy, which might take several minutes to finish.
900 */
901 nouveau_fence_wait(fence, false, false);
902 ret = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, false,
903 new_reg);
904 nouveau_fence_unref(&fence);
905
906out_unlock:
907 mutex_unlock(&cli->mutex);
908 return ret;
909}
910
911void
912nouveau_bo_move_init(struct nouveau_drm *drm)
913{
914 static const struct _method_table {
915 const char *name;
916 int engine;
917 s32 oclass;
918 int (*exec)(struct nouveau_channel *,
919 struct ttm_buffer_object *,
920 struct ttm_resource *, struct ttm_resource *);
921 int (*init)(struct nouveau_channel *, u32 handle);
922 } _methods[] = {
923 { "COPY", 4, 0xc7b5, nve0_bo_move_copy, nve0_bo_move_init },
924 { "GRCE", 0, 0xc7b5, nve0_bo_move_copy, nvc0_bo_move_init },
925 { "COPY", 4, 0xc6b5, nve0_bo_move_copy, nve0_bo_move_init },
926 { "GRCE", 0, 0xc6b5, nve0_bo_move_copy, nvc0_bo_move_init },
927 { "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init },
928 { "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init },
929 { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init },
930 { "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init },
931 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
932 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
933 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
934 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
935 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
936 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
937 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
938 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
939 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
940 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
941 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
942 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
943 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
944 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
945 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
946 {},
947 };
948 const struct _method_table *mthd = _methods;
949 const char *name = "CPU";
950 int ret;
951
952 do {
953 struct nouveau_channel *chan;
954
955 if (mthd->engine)
956 chan = drm->cechan;
957 else
958 chan = drm->channel;
959 if (chan == NULL)
960 continue;
961
962 ret = nvif_object_ctor(&chan->user, "ttmBoMove",
963 mthd->oclass | (mthd->engine << 16),
964 mthd->oclass, NULL, 0,
965 &drm->ttm.copy);
966 if (ret == 0) {
967 ret = mthd->init(chan, drm->ttm.copy.handle);
968 if (ret) {
969 nvif_object_dtor(&drm->ttm.copy);
970 continue;
971 }
972
973 drm->ttm.move = mthd->exec;
974 drm->ttm.chan = chan;
975 name = mthd->name;
976 break;
977 }
978 } while ((++mthd)->exec);
979
980 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
981}
982
983static void nouveau_bo_move_ntfy(struct ttm_buffer_object *bo,
984 struct ttm_resource *new_reg)
985{
986 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
987 struct nouveau_bo *nvbo = nouveau_bo(bo);
988 struct nouveau_vma *vma;
989 long ret;
990
991 /* ttm can now (stupidly) pass the driver bos it didn't create... */
992 if (bo->destroy != nouveau_bo_del_ttm)
993 return;
994
995 nouveau_bo_del_io_reserve_lru(bo);
996
997 if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
998 mem->mem.page == nvbo->page) {
999 list_for_each_entry(vma, &nvbo->vma_list, head) {
1000 nouveau_vma_map(vma, mem);
1001 }
1002 nouveau_uvmm_bo_map_all(nvbo, mem);
1003 } else {
1004 list_for_each_entry(vma, &nvbo->vma_list, head) {
1005 ret = dma_resv_wait_timeout(bo->base.resv,
1006 DMA_RESV_USAGE_BOOKKEEP,
1007 false, 15 * HZ);
1008 WARN_ON(ret <= 0);
1009 nouveau_vma_unmap(vma);
1010 }
1011 nouveau_uvmm_bo_unmap_all(nvbo);
1012 }
1013
1014 if (new_reg)
1015 nvbo->offset = (new_reg->start << PAGE_SHIFT);
1016
1017}
1018
1019static int
1020nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg,
1021 struct nouveau_drm_tile **new_tile)
1022{
1023 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1024 struct drm_device *dev = drm->dev;
1025 struct nouveau_bo *nvbo = nouveau_bo(bo);
1026 u64 offset = new_reg->start << PAGE_SHIFT;
1027
1028 *new_tile = NULL;
1029 if (new_reg->mem_type != TTM_PL_VRAM)
1030 return 0;
1031
1032 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
1033 *new_tile = nv10_bo_set_tiling(dev, offset, bo->base.size,
1034 nvbo->mode, nvbo->zeta);
1035 }
1036
1037 return 0;
1038}
1039
1040static void
1041nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1042 struct nouveau_drm_tile *new_tile,
1043 struct nouveau_drm_tile **old_tile)
1044{
1045 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1046 struct drm_device *dev = drm->dev;
1047 struct dma_fence *fence;
1048 int ret;
1049
1050 ret = dma_resv_get_singleton(bo->base.resv, DMA_RESV_USAGE_WRITE,
1051 &fence);
1052 if (ret)
1053 dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_WRITE,
1054 false, MAX_SCHEDULE_TIMEOUT);
1055
1056 nv10_bo_put_tile_region(dev, *old_tile, fence);
1057 *old_tile = new_tile;
1058}
1059
1060static int
1061nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
1062 struct ttm_operation_ctx *ctx,
1063 struct ttm_resource *new_reg,
1064 struct ttm_place *hop)
1065{
1066 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1067 struct nouveau_bo *nvbo = nouveau_bo(bo);
1068 struct drm_gem_object *obj = &bo->base;
1069 struct ttm_resource *old_reg = bo->resource;
1070 struct nouveau_drm_tile *new_tile = NULL;
1071 int ret = 0;
1072
1073 if (new_reg->mem_type == TTM_PL_TT) {
1074 ret = nouveau_ttm_tt_bind(bo->bdev, bo->ttm, new_reg);
1075 if (ret)
1076 return ret;
1077 }
1078
1079 drm_gpuvm_bo_gem_evict(obj, evict);
1080 nouveau_bo_move_ntfy(bo, new_reg);
1081 ret = ttm_bo_wait_ctx(bo, ctx);
1082 if (ret)
1083 goto out_ntfy;
1084
1085 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1086 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
1087 if (ret)
1088 goto out_ntfy;
1089 }
1090
1091 /* Fake bo copy. */
1092 if (!old_reg || (old_reg->mem_type == TTM_PL_SYSTEM &&
1093 !bo->ttm)) {
1094 ttm_bo_move_null(bo, new_reg);
1095 goto out;
1096 }
1097
1098 if (old_reg->mem_type == TTM_PL_SYSTEM &&
1099 new_reg->mem_type == TTM_PL_TT) {
1100 ttm_bo_move_null(bo, new_reg);
1101 goto out;
1102 }
1103
1104 if (old_reg->mem_type == TTM_PL_TT &&
1105 new_reg->mem_type == TTM_PL_SYSTEM) {
1106 nouveau_ttm_tt_unbind(bo->bdev, bo->ttm);
1107 ttm_resource_free(bo, &bo->resource);
1108 ttm_bo_assign_mem(bo, new_reg);
1109 goto out;
1110 }
1111
1112 /* Hardware assisted copy. */
1113 if (drm->ttm.move) {
1114 if ((old_reg->mem_type == TTM_PL_SYSTEM &&
1115 new_reg->mem_type == TTM_PL_VRAM) ||
1116 (old_reg->mem_type == TTM_PL_VRAM &&
1117 new_reg->mem_type == TTM_PL_SYSTEM)) {
1118 hop->fpfn = 0;
1119 hop->lpfn = 0;
1120 hop->mem_type = TTM_PL_TT;
1121 hop->flags = 0;
1122 return -EMULTIHOP;
1123 }
1124 ret = nouveau_bo_move_m2mf(bo, evict, ctx,
1125 new_reg);
1126 } else
1127 ret = -ENODEV;
1128
1129 if (ret) {
1130 /* Fallback to software copy. */
1131 ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
1132 }
1133
1134out:
1135 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1136 if (ret)
1137 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1138 else
1139 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1140 }
1141out_ntfy:
1142 if (ret) {
1143 nouveau_bo_move_ntfy(bo, bo->resource);
1144 drm_gpuvm_bo_gem_evict(obj, !evict);
1145 }
1146 return ret;
1147}
1148
1149static void
1150nouveau_ttm_io_mem_free_locked(struct nouveau_drm *drm,
1151 struct ttm_resource *reg)
1152{
1153 struct nouveau_mem *mem = nouveau_mem(reg);
1154
1155 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1156 switch (reg->mem_type) {
1157 case TTM_PL_TT:
1158 if (mem->kind)
1159 nvif_object_unmap_handle(&mem->mem.object);
1160 break;
1161 case TTM_PL_VRAM:
1162 nvif_object_unmap_handle(&mem->mem.object);
1163 break;
1164 default:
1165 break;
1166 }
1167 }
1168}
1169
1170static int
1171nouveau_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *reg)
1172{
1173 struct nouveau_drm *drm = nouveau_bdev(bdev);
1174 struct nvkm_device *device = nvxx_device(drm);
1175 struct nouveau_mem *mem = nouveau_mem(reg);
1176 struct nvif_mmu *mmu = &drm->client.mmu;
1177 int ret;
1178
1179 mutex_lock(&drm->ttm.io_reserve_mutex);
1180retry:
1181 switch (reg->mem_type) {
1182 case TTM_PL_SYSTEM:
1183 /* System memory */
1184 ret = 0;
1185 goto out;
1186 case TTM_PL_TT:
1187#if IS_ENABLED(CONFIG_AGP)
1188 if (drm->agp.bridge) {
1189 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1190 drm->agp.base;
1191 reg->bus.is_iomem = !drm->agp.cma;
1192 reg->bus.caching = ttm_write_combined;
1193 }
1194#endif
1195 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 ||
1196 !mem->kind) {
1197 /* untiled */
1198 ret = 0;
1199 break;
1200 }
1201 fallthrough; /* tiled memory */
1202 case TTM_PL_VRAM:
1203 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1204 device->func->resource_addr(device, 1);
1205 reg->bus.is_iomem = true;
1206
1207 /* Some BARs do not support being ioremapped WC */
1208 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
1209 mmu->type[drm->ttm.type_vram].type & NVIF_MEM_UNCACHED)
1210 reg->bus.caching = ttm_uncached;
1211 else
1212 reg->bus.caching = ttm_write_combined;
1213
1214 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1215 union {
1216 struct nv50_mem_map_v0 nv50;
1217 struct gf100_mem_map_v0 gf100;
1218 } args;
1219 u64 handle, length;
1220 u32 argc = 0;
1221
1222 switch (mem->mem.object.oclass) {
1223 case NVIF_CLASS_MEM_NV50:
1224 args.nv50.version = 0;
1225 args.nv50.ro = 0;
1226 args.nv50.kind = mem->kind;
1227 args.nv50.comp = mem->comp;
1228 argc = sizeof(args.nv50);
1229 break;
1230 case NVIF_CLASS_MEM_GF100:
1231 args.gf100.version = 0;
1232 args.gf100.ro = 0;
1233 args.gf100.kind = mem->kind;
1234 argc = sizeof(args.gf100);
1235 break;
1236 default:
1237 WARN_ON(1);
1238 break;
1239 }
1240
1241 ret = nvif_object_map_handle(&mem->mem.object,
1242 &args, argc,
1243 &handle, &length);
1244 if (ret != 1) {
1245 if (WARN_ON(ret == 0))
1246 ret = -EINVAL;
1247 goto out;
1248 }
1249
1250 reg->bus.offset = handle;
1251 }
1252 ret = 0;
1253 break;
1254 default:
1255 ret = -EINVAL;
1256 }
1257
1258out:
1259 if (ret == -ENOSPC) {
1260 struct nouveau_bo *nvbo;
1261
1262 nvbo = list_first_entry_or_null(&drm->ttm.io_reserve_lru,
1263 typeof(*nvbo),
1264 io_reserve_lru);
1265 if (nvbo) {
1266 list_del_init(&nvbo->io_reserve_lru);
1267 drm_vma_node_unmap(&nvbo->bo.base.vma_node,
1268 bdev->dev_mapping);
1269 nouveau_ttm_io_mem_free_locked(drm, nvbo->bo.resource);
1270 nvbo->bo.resource->bus.offset = 0;
1271 nvbo->bo.resource->bus.addr = NULL;
1272 goto retry;
1273 }
1274
1275 }
1276 mutex_unlock(&drm->ttm.io_reserve_mutex);
1277 return ret;
1278}
1279
1280static void
1281nouveau_ttm_io_mem_free(struct ttm_device *bdev, struct ttm_resource *reg)
1282{
1283 struct nouveau_drm *drm = nouveau_bdev(bdev);
1284
1285 mutex_lock(&drm->ttm.io_reserve_mutex);
1286 nouveau_ttm_io_mem_free_locked(drm, reg);
1287 mutex_unlock(&drm->ttm.io_reserve_mutex);
1288}
1289
1290vm_fault_t nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1291{
1292 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1293 struct nouveau_bo *nvbo = nouveau_bo(bo);
1294 struct nvkm_device *device = nvxx_device(drm);
1295 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1296 int i, ret;
1297
1298 /* as long as the bo isn't in vram, and isn't tiled, we've got
1299 * nothing to do here.
1300 */
1301 if (bo->resource->mem_type != TTM_PL_VRAM) {
1302 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1303 !nvbo->kind)
1304 return 0;
1305
1306 if (bo->resource->mem_type != TTM_PL_SYSTEM)
1307 return 0;
1308
1309 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
1310
1311 } else {
1312 /* make sure bo is in mappable vram */
1313 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1314 bo->resource->start + PFN_UP(bo->resource->size) < mappable)
1315 return 0;
1316
1317 for (i = 0; i < nvbo->placement.num_placement; ++i) {
1318 nvbo->placements[i].fpfn = 0;
1319 nvbo->placements[i].lpfn = mappable;
1320 }
1321
1322 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0);
1323 }
1324
1325 ret = nouveau_bo_validate(nvbo, false, false);
1326 if (unlikely(ret == -EBUSY || ret == -ERESTARTSYS))
1327 return VM_FAULT_NOPAGE;
1328 else if (unlikely(ret))
1329 return VM_FAULT_SIGBUS;
1330
1331 ttm_bo_move_to_lru_tail_unlocked(bo);
1332 return 0;
1333}
1334
1335static int
1336nouveau_ttm_tt_populate(struct ttm_device *bdev,
1337 struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
1338{
1339 struct ttm_tt *ttm_dma = (void *)ttm;
1340 struct nouveau_drm *drm;
1341 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
1342
1343 if (ttm_tt_is_populated(ttm))
1344 return 0;
1345
1346 if (slave && ttm->sg) {
1347 drm_prime_sg_to_dma_addr_array(ttm->sg, ttm_dma->dma_address,
1348 ttm->num_pages);
1349 return 0;
1350 }
1351
1352 drm = nouveau_bdev(bdev);
1353
1354 return ttm_pool_alloc(&drm->ttm.bdev.pool, ttm, ctx);
1355}
1356
1357static void
1358nouveau_ttm_tt_unpopulate(struct ttm_device *bdev,
1359 struct ttm_tt *ttm)
1360{
1361 struct nouveau_drm *drm;
1362 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
1363
1364 if (slave)
1365 return;
1366
1367 nouveau_ttm_tt_unbind(bdev, ttm);
1368
1369 drm = nouveau_bdev(bdev);
1370
1371 return ttm_pool_free(&drm->ttm.bdev.pool, ttm);
1372}
1373
1374static void
1375nouveau_ttm_tt_destroy(struct ttm_device *bdev,
1376 struct ttm_tt *ttm)
1377{
1378#if IS_ENABLED(CONFIG_AGP)
1379 struct nouveau_drm *drm = nouveau_bdev(bdev);
1380 if (drm->agp.bridge) {
1381 ttm_agp_destroy(ttm);
1382 return;
1383 }
1384#endif
1385 nouveau_sgdma_destroy(bdev, ttm);
1386}
1387
1388void
1389nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1390{
1391 struct dma_resv *resv = nvbo->bo.base.resv;
1392
1393 if (!fence)
1394 return;
1395
1396 dma_resv_add_fence(resv, &fence->base, exclusive ?
1397 DMA_RESV_USAGE_WRITE : DMA_RESV_USAGE_READ);
1398}
1399
1400static void
1401nouveau_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1402{
1403 nouveau_bo_move_ntfy(bo, NULL);
1404}
1405
1406struct ttm_device_funcs nouveau_bo_driver = {
1407 .ttm_tt_create = &nouveau_ttm_tt_create,
1408 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1409 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1410 .ttm_tt_destroy = &nouveau_ttm_tt_destroy,
1411 .eviction_valuable = ttm_bo_eviction_valuable,
1412 .evict_flags = nouveau_bo_evict_flags,
1413 .delete_mem_notify = nouveau_bo_delete_mem_notify,
1414 .move = nouveau_bo_move,
1415 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1416 .io_mem_free = &nouveau_ttm_io_mem_free,
1417};
1/*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30#include <linux/dma-mapping.h>
31#include <linux/swiotlb.h>
32
33#include "nouveau_drv.h"
34#include "nouveau_dma.h"
35#include "nouveau_fence.h"
36
37#include "nouveau_bo.h"
38#include "nouveau_ttm.h"
39#include "nouveau_gem.h"
40
41/*
42 * NV10-NV40 tiling helpers
43 */
44
45static void
46nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
47 u32 addr, u32 size, u32 pitch, u32 flags)
48{
49 struct nouveau_drm *drm = nouveau_drm(dev);
50 int i = reg - drm->tile.reg;
51 struct nvkm_device *device = nvxx_device(&drm->device);
52 struct nvkm_fb *fb = device->fb;
53 struct nvkm_fb_tile *tile = &fb->tile.region[i];
54
55 nouveau_fence_unref(®->fence);
56
57 if (tile->pitch)
58 nvkm_fb_tile_fini(fb, i, tile);
59
60 if (pitch)
61 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
62
63 nvkm_fb_tile_prog(fb, i, tile);
64}
65
66static struct nouveau_drm_tile *
67nv10_bo_get_tile_region(struct drm_device *dev, int i)
68{
69 struct nouveau_drm *drm = nouveau_drm(dev);
70 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
71
72 spin_lock(&drm->tile.lock);
73
74 if (!tile->used &&
75 (!tile->fence || nouveau_fence_done(tile->fence)))
76 tile->used = true;
77 else
78 tile = NULL;
79
80 spin_unlock(&drm->tile.lock);
81 return tile;
82}
83
84static void
85nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
86 struct dma_fence *fence)
87{
88 struct nouveau_drm *drm = nouveau_drm(dev);
89
90 if (tile) {
91 spin_lock(&drm->tile.lock);
92 tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
93 tile->used = false;
94 spin_unlock(&drm->tile.lock);
95 }
96}
97
98static struct nouveau_drm_tile *
99nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
100 u32 size, u32 pitch, u32 flags)
101{
102 struct nouveau_drm *drm = nouveau_drm(dev);
103 struct nvkm_fb *fb = nvxx_fb(&drm->device);
104 struct nouveau_drm_tile *tile, *found = NULL;
105 int i;
106
107 for (i = 0; i < fb->tile.regions; i++) {
108 tile = nv10_bo_get_tile_region(dev, i);
109
110 if (pitch && !found) {
111 found = tile;
112 continue;
113
114 } else if (tile && fb->tile.region[i].pitch) {
115 /* Kill an unused tile region. */
116 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
117 }
118
119 nv10_bo_put_tile_region(dev, tile, NULL);
120 }
121
122 if (found)
123 nv10_bo_update_tile_region(dev, found, addr, size,
124 pitch, flags);
125 return found;
126}
127
128static void
129nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
130{
131 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
132 struct drm_device *dev = drm->dev;
133 struct nouveau_bo *nvbo = nouveau_bo(bo);
134
135 if (unlikely(nvbo->gem.filp))
136 DRM_ERROR("bo %p still attached to GEM object\n", bo);
137 WARN_ON(nvbo->pin_refcnt > 0);
138 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
139 kfree(nvbo);
140}
141
142static void
143nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
144 int *align, int *size)
145{
146 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
147 struct nvif_device *device = &drm->device;
148
149 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
150 if (nvbo->tile_mode) {
151 if (device->info.chipset >= 0x40) {
152 *align = 65536;
153 *size = roundup(*size, 64 * nvbo->tile_mode);
154
155 } else if (device->info.chipset >= 0x30) {
156 *align = 32768;
157 *size = roundup(*size, 64 * nvbo->tile_mode);
158
159 } else if (device->info.chipset >= 0x20) {
160 *align = 16384;
161 *size = roundup(*size, 64 * nvbo->tile_mode);
162
163 } else if (device->info.chipset >= 0x10) {
164 *align = 16384;
165 *size = roundup(*size, 32 * nvbo->tile_mode);
166 }
167 }
168 } else {
169 *size = roundup(*size, (1 << nvbo->page_shift));
170 *align = max((1 << nvbo->page_shift), *align);
171 }
172
173 *size = roundup(*size, PAGE_SIZE);
174}
175
176int
177nouveau_bo_new(struct drm_device *dev, int size, int align,
178 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
179 struct sg_table *sg, struct reservation_object *robj,
180 struct nouveau_bo **pnvbo)
181{
182 struct nouveau_drm *drm = nouveau_drm(dev);
183 struct nouveau_bo *nvbo;
184 size_t acc_size;
185 int ret;
186 int type = ttm_bo_type_device;
187 int lpg_shift = 12;
188 int max_size;
189
190 if (drm->client.vm)
191 lpg_shift = drm->client.vm->mmu->lpg_shift;
192 max_size = INT_MAX & ~((1 << lpg_shift) - 1);
193
194 if (size <= 0 || size > max_size) {
195 NV_WARN(drm, "skipped size %x\n", (u32)size);
196 return -EINVAL;
197 }
198
199 if (sg)
200 type = ttm_bo_type_sg;
201
202 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
203 if (!nvbo)
204 return -ENOMEM;
205 INIT_LIST_HEAD(&nvbo->head);
206 INIT_LIST_HEAD(&nvbo->entry);
207 INIT_LIST_HEAD(&nvbo->vma_list);
208 nvbo->tile_mode = tile_mode;
209 nvbo->tile_flags = tile_flags;
210 nvbo->bo.bdev = &drm->ttm.bdev;
211
212 if (!nvxx_device(&drm->device)->func->cpu_coherent)
213 nvbo->force_coherent = flags & TTM_PL_FLAG_UNCACHED;
214
215 nvbo->page_shift = 12;
216 if (drm->client.vm) {
217 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
218 nvbo->page_shift = drm->client.vm->mmu->lpg_shift;
219 }
220
221 nouveau_bo_fixup_align(nvbo, flags, &align, &size);
222 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
223 nouveau_bo_placement_set(nvbo, flags, 0);
224
225 acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size,
226 sizeof(struct nouveau_bo));
227
228 ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size,
229 type, &nvbo->placement,
230 align >> PAGE_SHIFT, false, NULL, acc_size, sg,
231 robj, nouveau_bo_del_ttm);
232 if (ret) {
233 /* ttm will call nouveau_bo_del_ttm if it fails.. */
234 return ret;
235 }
236
237 *pnvbo = nvbo;
238 return 0;
239}
240
241static void
242set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags)
243{
244 *n = 0;
245
246 if (type & TTM_PL_FLAG_VRAM)
247 pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags;
248 if (type & TTM_PL_FLAG_TT)
249 pl[(*n)++].flags = TTM_PL_FLAG_TT | flags;
250 if (type & TTM_PL_FLAG_SYSTEM)
251 pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags;
252}
253
254static void
255set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
256{
257 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
258 u32 vram_pages = drm->device.info.ram_size >> PAGE_SHIFT;
259 unsigned i, fpfn, lpfn;
260
261 if (drm->device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
262 nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
263 nvbo->bo.mem.num_pages < vram_pages / 4) {
264 /*
265 * Make sure that the color and depth buffers are handled
266 * by independent memory controller units. Up to a 9x
267 * speed up when alpha-blending and depth-test are enabled
268 * at the same time.
269 */
270 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
271 fpfn = vram_pages / 2;
272 lpfn = ~0;
273 } else {
274 fpfn = 0;
275 lpfn = vram_pages / 2;
276 }
277 for (i = 0; i < nvbo->placement.num_placement; ++i) {
278 nvbo->placements[i].fpfn = fpfn;
279 nvbo->placements[i].lpfn = lpfn;
280 }
281 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
282 nvbo->busy_placements[i].fpfn = fpfn;
283 nvbo->busy_placements[i].lpfn = lpfn;
284 }
285 }
286}
287
288void
289nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
290{
291 struct ttm_placement *pl = &nvbo->placement;
292 uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED :
293 TTM_PL_MASK_CACHING) |
294 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
295
296 pl->placement = nvbo->placements;
297 set_placement_list(nvbo->placements, &pl->num_placement,
298 type, flags);
299
300 pl->busy_placement = nvbo->busy_placements;
301 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
302 type | busy, flags);
303
304 set_placement_range(nvbo, type);
305}
306
307int
308nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig)
309{
310 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
311 struct ttm_buffer_object *bo = &nvbo->bo;
312 bool force = false, evict = false;
313 int ret;
314
315 ret = ttm_bo_reserve(bo, false, false, NULL);
316 if (ret)
317 return ret;
318
319 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
320 memtype == TTM_PL_FLAG_VRAM && contig) {
321 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) {
322 if (bo->mem.mem_type == TTM_PL_VRAM) {
323 struct nvkm_mem *mem = bo->mem.mm_node;
324 if (!list_is_singular(&mem->regions))
325 evict = true;
326 }
327 nvbo->tile_flags &= ~NOUVEAU_GEM_TILE_NONCONTIG;
328 force = true;
329 }
330 }
331
332 if (nvbo->pin_refcnt) {
333 if (!(memtype & (1 << bo->mem.mem_type)) || evict) {
334 NV_ERROR(drm, "bo %p pinned elsewhere: "
335 "0x%08x vs 0x%08x\n", bo,
336 1 << bo->mem.mem_type, memtype);
337 ret = -EBUSY;
338 }
339 nvbo->pin_refcnt++;
340 goto out;
341 }
342
343 if (evict) {
344 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0);
345 ret = nouveau_bo_validate(nvbo, false, false);
346 if (ret)
347 goto out;
348 }
349
350 nvbo->pin_refcnt++;
351 nouveau_bo_placement_set(nvbo, memtype, 0);
352
353 /* drop pin_refcnt temporarily, so we don't trip the assertion
354 * in nouveau_bo_move() that makes sure we're not trying to
355 * move a pinned buffer
356 */
357 nvbo->pin_refcnt--;
358 ret = nouveau_bo_validate(nvbo, false, false);
359 if (ret)
360 goto out;
361 nvbo->pin_refcnt++;
362
363 switch (bo->mem.mem_type) {
364 case TTM_PL_VRAM:
365 drm->gem.vram_available -= bo->mem.size;
366 break;
367 case TTM_PL_TT:
368 drm->gem.gart_available -= bo->mem.size;
369 break;
370 default:
371 break;
372 }
373
374out:
375 if (force && ret)
376 nvbo->tile_flags |= NOUVEAU_GEM_TILE_NONCONTIG;
377 ttm_bo_unreserve(bo);
378 return ret;
379}
380
381int
382nouveau_bo_unpin(struct nouveau_bo *nvbo)
383{
384 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
385 struct ttm_buffer_object *bo = &nvbo->bo;
386 int ret, ref;
387
388 ret = ttm_bo_reserve(bo, false, false, NULL);
389 if (ret)
390 return ret;
391
392 ref = --nvbo->pin_refcnt;
393 WARN_ON_ONCE(ref < 0);
394 if (ref)
395 goto out;
396
397 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
398
399 ret = nouveau_bo_validate(nvbo, false, false);
400 if (ret == 0) {
401 switch (bo->mem.mem_type) {
402 case TTM_PL_VRAM:
403 drm->gem.vram_available += bo->mem.size;
404 break;
405 case TTM_PL_TT:
406 drm->gem.gart_available += bo->mem.size;
407 break;
408 default:
409 break;
410 }
411 }
412
413out:
414 ttm_bo_unreserve(bo);
415 return ret;
416}
417
418int
419nouveau_bo_map(struct nouveau_bo *nvbo)
420{
421 int ret;
422
423 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
424 if (ret)
425 return ret;
426
427 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
428
429 ttm_bo_unreserve(&nvbo->bo);
430 return ret;
431}
432
433void
434nouveau_bo_unmap(struct nouveau_bo *nvbo)
435{
436 if (!nvbo)
437 return;
438
439 ttm_bo_kunmap(&nvbo->kmap);
440}
441
442void
443nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
444{
445 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
446 struct nvkm_device *device = nvxx_device(&drm->device);
447 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
448 int i;
449
450 if (!ttm_dma)
451 return;
452
453 /* Don't waste time looping if the object is coherent */
454 if (nvbo->force_coherent)
455 return;
456
457 for (i = 0; i < ttm_dma->ttm.num_pages; i++)
458 dma_sync_single_for_device(device->dev, ttm_dma->dma_address[i],
459 PAGE_SIZE, DMA_TO_DEVICE);
460}
461
462void
463nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
464{
465 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
466 struct nvkm_device *device = nvxx_device(&drm->device);
467 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
468 int i;
469
470 if (!ttm_dma)
471 return;
472
473 /* Don't waste time looping if the object is coherent */
474 if (nvbo->force_coherent)
475 return;
476
477 for (i = 0; i < ttm_dma->ttm.num_pages; i++)
478 dma_sync_single_for_cpu(device->dev, ttm_dma->dma_address[i],
479 PAGE_SIZE, DMA_FROM_DEVICE);
480}
481
482int
483nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
484 bool no_wait_gpu)
485{
486 int ret;
487
488 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement,
489 interruptible, no_wait_gpu);
490 if (ret)
491 return ret;
492
493 nouveau_bo_sync_for_device(nvbo);
494
495 return 0;
496}
497
498void
499nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
500{
501 bool is_iomem;
502 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
503
504 mem += index;
505
506 if (is_iomem)
507 iowrite16_native(val, (void __force __iomem *)mem);
508 else
509 *mem = val;
510}
511
512u32
513nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
514{
515 bool is_iomem;
516 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
517
518 mem += index;
519
520 if (is_iomem)
521 return ioread32_native((void __force __iomem *)mem);
522 else
523 return *mem;
524}
525
526void
527nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
528{
529 bool is_iomem;
530 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
531
532 mem += index;
533
534 if (is_iomem)
535 iowrite32_native(val, (void __force __iomem *)mem);
536 else
537 *mem = val;
538}
539
540static struct ttm_tt *
541nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size,
542 uint32_t page_flags, struct page *dummy_read)
543{
544#if IS_ENABLED(CONFIG_AGP)
545 struct nouveau_drm *drm = nouveau_bdev(bdev);
546
547 if (drm->agp.bridge) {
548 return ttm_agp_tt_create(bdev, drm->agp.bridge, size,
549 page_flags, dummy_read);
550 }
551#endif
552
553 return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read);
554}
555
556static int
557nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
558{
559 /* We'll do this from user space. */
560 return 0;
561}
562
563static int
564nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
565 struct ttm_mem_type_manager *man)
566{
567 struct nouveau_drm *drm = nouveau_bdev(bdev);
568
569 switch (type) {
570 case TTM_PL_SYSTEM:
571 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
572 man->available_caching = TTM_PL_MASK_CACHING;
573 man->default_caching = TTM_PL_FLAG_CACHED;
574 break;
575 case TTM_PL_VRAM:
576 man->flags = TTM_MEMTYPE_FLAG_FIXED |
577 TTM_MEMTYPE_FLAG_MAPPABLE;
578 man->available_caching = TTM_PL_FLAG_UNCACHED |
579 TTM_PL_FLAG_WC;
580 man->default_caching = TTM_PL_FLAG_WC;
581
582 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
583 /* Some BARs do not support being ioremapped WC */
584 if (nvxx_bar(&drm->device)->iomap_uncached) {
585 man->available_caching = TTM_PL_FLAG_UNCACHED;
586 man->default_caching = TTM_PL_FLAG_UNCACHED;
587 }
588
589 man->func = &nouveau_vram_manager;
590 man->io_reserve_fastpath = false;
591 man->use_io_reserve_lru = true;
592 } else {
593 man->func = &ttm_bo_manager_func;
594 }
595 break;
596 case TTM_PL_TT:
597 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA)
598 man->func = &nouveau_gart_manager;
599 else
600 if (!drm->agp.bridge)
601 man->func = &nv04_gart_manager;
602 else
603 man->func = &ttm_bo_manager_func;
604
605 if (drm->agp.bridge) {
606 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
607 man->available_caching = TTM_PL_FLAG_UNCACHED |
608 TTM_PL_FLAG_WC;
609 man->default_caching = TTM_PL_FLAG_WC;
610 } else {
611 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
612 TTM_MEMTYPE_FLAG_CMA;
613 man->available_caching = TTM_PL_MASK_CACHING;
614 man->default_caching = TTM_PL_FLAG_CACHED;
615 }
616
617 break;
618 default:
619 return -EINVAL;
620 }
621 return 0;
622}
623
624static void
625nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
626{
627 struct nouveau_bo *nvbo = nouveau_bo(bo);
628
629 switch (bo->mem.mem_type) {
630 case TTM_PL_VRAM:
631 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
632 TTM_PL_FLAG_SYSTEM);
633 break;
634 default:
635 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
636 break;
637 }
638
639 *pl = nvbo->placement;
640}
641
642
643static int
644nve0_bo_move_init(struct nouveau_channel *chan, u32 handle)
645{
646 int ret = RING_SPACE(chan, 2);
647 if (ret == 0) {
648 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
649 OUT_RING (chan, handle & 0x0000ffff);
650 FIRE_RING (chan);
651 }
652 return ret;
653}
654
655static int
656nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
657 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
658{
659 struct nvkm_mem *node = old_mem->mm_node;
660 int ret = RING_SPACE(chan, 10);
661 if (ret == 0) {
662 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
663 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
664 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
665 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
666 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
667 OUT_RING (chan, PAGE_SIZE);
668 OUT_RING (chan, PAGE_SIZE);
669 OUT_RING (chan, PAGE_SIZE);
670 OUT_RING (chan, new_mem->num_pages);
671 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
672 }
673 return ret;
674}
675
676static int
677nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
678{
679 int ret = RING_SPACE(chan, 2);
680 if (ret == 0) {
681 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
682 OUT_RING (chan, handle);
683 }
684 return ret;
685}
686
687static int
688nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
689 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
690{
691 struct nvkm_mem *node = old_mem->mm_node;
692 u64 src_offset = node->vma[0].offset;
693 u64 dst_offset = node->vma[1].offset;
694 u32 page_count = new_mem->num_pages;
695 int ret;
696
697 page_count = new_mem->num_pages;
698 while (page_count) {
699 int line_count = (page_count > 8191) ? 8191 : page_count;
700
701 ret = RING_SPACE(chan, 11);
702 if (ret)
703 return ret;
704
705 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
706 OUT_RING (chan, upper_32_bits(src_offset));
707 OUT_RING (chan, lower_32_bits(src_offset));
708 OUT_RING (chan, upper_32_bits(dst_offset));
709 OUT_RING (chan, lower_32_bits(dst_offset));
710 OUT_RING (chan, PAGE_SIZE);
711 OUT_RING (chan, PAGE_SIZE);
712 OUT_RING (chan, PAGE_SIZE);
713 OUT_RING (chan, line_count);
714 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
715 OUT_RING (chan, 0x00000110);
716
717 page_count -= line_count;
718 src_offset += (PAGE_SIZE * line_count);
719 dst_offset += (PAGE_SIZE * line_count);
720 }
721
722 return 0;
723}
724
725static int
726nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
727 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
728{
729 struct nvkm_mem *node = old_mem->mm_node;
730 u64 src_offset = node->vma[0].offset;
731 u64 dst_offset = node->vma[1].offset;
732 u32 page_count = new_mem->num_pages;
733 int ret;
734
735 page_count = new_mem->num_pages;
736 while (page_count) {
737 int line_count = (page_count > 2047) ? 2047 : page_count;
738
739 ret = RING_SPACE(chan, 12);
740 if (ret)
741 return ret;
742
743 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
744 OUT_RING (chan, upper_32_bits(dst_offset));
745 OUT_RING (chan, lower_32_bits(dst_offset));
746 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
747 OUT_RING (chan, upper_32_bits(src_offset));
748 OUT_RING (chan, lower_32_bits(src_offset));
749 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
750 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
751 OUT_RING (chan, PAGE_SIZE); /* line_length */
752 OUT_RING (chan, line_count);
753 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
754 OUT_RING (chan, 0x00100110);
755
756 page_count -= line_count;
757 src_offset += (PAGE_SIZE * line_count);
758 dst_offset += (PAGE_SIZE * line_count);
759 }
760
761 return 0;
762}
763
764static int
765nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
766 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
767{
768 struct nvkm_mem *node = old_mem->mm_node;
769 u64 src_offset = node->vma[0].offset;
770 u64 dst_offset = node->vma[1].offset;
771 u32 page_count = new_mem->num_pages;
772 int ret;
773
774 page_count = new_mem->num_pages;
775 while (page_count) {
776 int line_count = (page_count > 8191) ? 8191 : page_count;
777
778 ret = RING_SPACE(chan, 11);
779 if (ret)
780 return ret;
781
782 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
783 OUT_RING (chan, upper_32_bits(src_offset));
784 OUT_RING (chan, lower_32_bits(src_offset));
785 OUT_RING (chan, upper_32_bits(dst_offset));
786 OUT_RING (chan, lower_32_bits(dst_offset));
787 OUT_RING (chan, PAGE_SIZE);
788 OUT_RING (chan, PAGE_SIZE);
789 OUT_RING (chan, PAGE_SIZE);
790 OUT_RING (chan, line_count);
791 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
792 OUT_RING (chan, 0x00000110);
793
794 page_count -= line_count;
795 src_offset += (PAGE_SIZE * line_count);
796 dst_offset += (PAGE_SIZE * line_count);
797 }
798
799 return 0;
800}
801
802static int
803nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
804 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
805{
806 struct nvkm_mem *node = old_mem->mm_node;
807 int ret = RING_SPACE(chan, 7);
808 if (ret == 0) {
809 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
810 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
811 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
812 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
813 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
814 OUT_RING (chan, 0x00000000 /* COPY */);
815 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
816 }
817 return ret;
818}
819
820static int
821nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
822 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
823{
824 struct nvkm_mem *node = old_mem->mm_node;
825 int ret = RING_SPACE(chan, 7);
826 if (ret == 0) {
827 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
828 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
829 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
830 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
831 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
832 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
833 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
834 }
835 return ret;
836}
837
838static int
839nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
840{
841 int ret = RING_SPACE(chan, 6);
842 if (ret == 0) {
843 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
844 OUT_RING (chan, handle);
845 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
846 OUT_RING (chan, chan->drm->ntfy.handle);
847 OUT_RING (chan, chan->vram.handle);
848 OUT_RING (chan, chan->vram.handle);
849 }
850
851 return ret;
852}
853
854static int
855nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
856 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
857{
858 struct nvkm_mem *node = old_mem->mm_node;
859 u64 length = (new_mem->num_pages << PAGE_SHIFT);
860 u64 src_offset = node->vma[0].offset;
861 u64 dst_offset = node->vma[1].offset;
862 int src_tiled = !!node->memtype;
863 int dst_tiled = !!((struct nvkm_mem *)new_mem->mm_node)->memtype;
864 int ret;
865
866 while (length) {
867 u32 amount, stride, height;
868
869 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled));
870 if (ret)
871 return ret;
872
873 amount = min(length, (u64)(4 * 1024 * 1024));
874 stride = 16 * 4;
875 height = amount / stride;
876
877 if (src_tiled) {
878 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
879 OUT_RING (chan, 0);
880 OUT_RING (chan, 0);
881 OUT_RING (chan, stride);
882 OUT_RING (chan, height);
883 OUT_RING (chan, 1);
884 OUT_RING (chan, 0);
885 OUT_RING (chan, 0);
886 } else {
887 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
888 OUT_RING (chan, 1);
889 }
890 if (dst_tiled) {
891 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
892 OUT_RING (chan, 0);
893 OUT_RING (chan, 0);
894 OUT_RING (chan, stride);
895 OUT_RING (chan, height);
896 OUT_RING (chan, 1);
897 OUT_RING (chan, 0);
898 OUT_RING (chan, 0);
899 } else {
900 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
901 OUT_RING (chan, 1);
902 }
903
904 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
905 OUT_RING (chan, upper_32_bits(src_offset));
906 OUT_RING (chan, upper_32_bits(dst_offset));
907 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
908 OUT_RING (chan, lower_32_bits(src_offset));
909 OUT_RING (chan, lower_32_bits(dst_offset));
910 OUT_RING (chan, stride);
911 OUT_RING (chan, stride);
912 OUT_RING (chan, stride);
913 OUT_RING (chan, height);
914 OUT_RING (chan, 0x00000101);
915 OUT_RING (chan, 0x00000000);
916 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
917 OUT_RING (chan, 0);
918
919 length -= amount;
920 src_offset += amount;
921 dst_offset += amount;
922 }
923
924 return 0;
925}
926
927static int
928nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
929{
930 int ret = RING_SPACE(chan, 4);
931 if (ret == 0) {
932 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
933 OUT_RING (chan, handle);
934 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
935 OUT_RING (chan, chan->drm->ntfy.handle);
936 }
937
938 return ret;
939}
940
941static inline uint32_t
942nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
943 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
944{
945 if (mem->mem_type == TTM_PL_TT)
946 return NvDmaTT;
947 return chan->vram.handle;
948}
949
950static int
951nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
952 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
953{
954 u32 src_offset = old_mem->start << PAGE_SHIFT;
955 u32 dst_offset = new_mem->start << PAGE_SHIFT;
956 u32 page_count = new_mem->num_pages;
957 int ret;
958
959 ret = RING_SPACE(chan, 3);
960 if (ret)
961 return ret;
962
963 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
964 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
965 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
966
967 page_count = new_mem->num_pages;
968 while (page_count) {
969 int line_count = (page_count > 2047) ? 2047 : page_count;
970
971 ret = RING_SPACE(chan, 11);
972 if (ret)
973 return ret;
974
975 BEGIN_NV04(chan, NvSubCopy,
976 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
977 OUT_RING (chan, src_offset);
978 OUT_RING (chan, dst_offset);
979 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
980 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
981 OUT_RING (chan, PAGE_SIZE); /* line_length */
982 OUT_RING (chan, line_count);
983 OUT_RING (chan, 0x00000101);
984 OUT_RING (chan, 0x00000000);
985 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
986 OUT_RING (chan, 0);
987
988 page_count -= line_count;
989 src_offset += (PAGE_SIZE * line_count);
990 dst_offset += (PAGE_SIZE * line_count);
991 }
992
993 return 0;
994}
995
996static int
997nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
998 struct ttm_mem_reg *mem)
999{
1000 struct nvkm_mem *old_node = bo->mem.mm_node;
1001 struct nvkm_mem *new_node = mem->mm_node;
1002 u64 size = (u64)mem->num_pages << PAGE_SHIFT;
1003 int ret;
1004
1005 ret = nvkm_vm_get(drm->client.vm, size, old_node->page_shift,
1006 NV_MEM_ACCESS_RW, &old_node->vma[0]);
1007 if (ret)
1008 return ret;
1009
1010 ret = nvkm_vm_get(drm->client.vm, size, new_node->page_shift,
1011 NV_MEM_ACCESS_RW, &old_node->vma[1]);
1012 if (ret) {
1013 nvkm_vm_put(&old_node->vma[0]);
1014 return ret;
1015 }
1016
1017 nvkm_vm_map(&old_node->vma[0], old_node);
1018 nvkm_vm_map(&old_node->vma[1], new_node);
1019 return 0;
1020}
1021
1022static int
1023nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
1024 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1025{
1026 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1027 struct nouveau_channel *chan = drm->ttm.chan;
1028 struct nouveau_cli *cli = (void *)chan->user.client;
1029 struct nouveau_fence *fence;
1030 int ret;
1031
1032 /* create temporary vmas for the transfer and attach them to the
1033 * old nvkm_mem node, these will get cleaned up after ttm has
1034 * destroyed the ttm_mem_reg
1035 */
1036 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
1037 ret = nouveau_bo_move_prep(drm, bo, new_mem);
1038 if (ret)
1039 return ret;
1040 }
1041
1042 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
1043 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr);
1044 if (ret == 0) {
1045 ret = drm->ttm.move(chan, bo, &bo->mem, new_mem);
1046 if (ret == 0) {
1047 ret = nouveau_fence_new(chan, false, &fence);
1048 if (ret == 0) {
1049 ret = ttm_bo_move_accel_cleanup(bo,
1050 &fence->base,
1051 evict,
1052 new_mem);
1053 nouveau_fence_unref(&fence);
1054 }
1055 }
1056 }
1057 mutex_unlock(&cli->mutex);
1058 return ret;
1059}
1060
1061void
1062nouveau_bo_move_init(struct nouveau_drm *drm)
1063{
1064 static const struct {
1065 const char *name;
1066 int engine;
1067 s32 oclass;
1068 int (*exec)(struct nouveau_channel *,
1069 struct ttm_buffer_object *,
1070 struct ttm_mem_reg *, struct ttm_mem_reg *);
1071 int (*init)(struct nouveau_channel *, u32 handle);
1072 } _methods[] = {
1073 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
1074 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
1075 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
1076 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1077 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
1078 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1079 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
1080 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1081 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
1082 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
1083 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
1084 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
1085 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
1086 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
1087 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
1088 {},
1089 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
1090 }, *mthd = _methods;
1091 const char *name = "CPU";
1092 int ret;
1093
1094 do {
1095 struct nouveau_channel *chan;
1096
1097 if (mthd->engine)
1098 chan = drm->cechan;
1099 else
1100 chan = drm->channel;
1101 if (chan == NULL)
1102 continue;
1103
1104 ret = nvif_object_init(&chan->user,
1105 mthd->oclass | (mthd->engine << 16),
1106 mthd->oclass, NULL, 0,
1107 &drm->ttm.copy);
1108 if (ret == 0) {
1109 ret = mthd->init(chan, drm->ttm.copy.handle);
1110 if (ret) {
1111 nvif_object_fini(&drm->ttm.copy);
1112 continue;
1113 }
1114
1115 drm->ttm.move = mthd->exec;
1116 drm->ttm.chan = chan;
1117 name = mthd->name;
1118 break;
1119 }
1120 } while ((++mthd)->exec);
1121
1122 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
1123}
1124
1125static int
1126nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
1127 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1128{
1129 struct ttm_place placement_memtype = {
1130 .fpfn = 0,
1131 .lpfn = 0,
1132 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
1133 };
1134 struct ttm_placement placement;
1135 struct ttm_mem_reg tmp_mem;
1136 int ret;
1137
1138 placement.num_placement = placement.num_busy_placement = 1;
1139 placement.placement = placement.busy_placement = &placement_memtype;
1140
1141 tmp_mem = *new_mem;
1142 tmp_mem.mm_node = NULL;
1143 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1144 if (ret)
1145 return ret;
1146
1147 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
1148 if (ret)
1149 goto out;
1150
1151 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_mem);
1152 if (ret)
1153 goto out;
1154
1155 ret = ttm_bo_move_ttm(bo, intr, no_wait_gpu, new_mem);
1156out:
1157 ttm_bo_mem_put(bo, &tmp_mem);
1158 return ret;
1159}
1160
1161static int
1162nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
1163 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1164{
1165 struct ttm_place placement_memtype = {
1166 .fpfn = 0,
1167 .lpfn = 0,
1168 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
1169 };
1170 struct ttm_placement placement;
1171 struct ttm_mem_reg tmp_mem;
1172 int ret;
1173
1174 placement.num_placement = placement.num_busy_placement = 1;
1175 placement.placement = placement.busy_placement = &placement_memtype;
1176
1177 tmp_mem = *new_mem;
1178 tmp_mem.mm_node = NULL;
1179 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1180 if (ret)
1181 return ret;
1182
1183 ret = ttm_bo_move_ttm(bo, intr, no_wait_gpu, &tmp_mem);
1184 if (ret)
1185 goto out;
1186
1187 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_mem);
1188 if (ret)
1189 goto out;
1190
1191out:
1192 ttm_bo_mem_put(bo, &tmp_mem);
1193 return ret;
1194}
1195
1196static void
1197nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
1198{
1199 struct nouveau_bo *nvbo = nouveau_bo(bo);
1200 struct nvkm_vma *vma;
1201
1202 /* ttm can now (stupidly) pass the driver bos it didn't create... */
1203 if (bo->destroy != nouveau_bo_del_ttm)
1204 return;
1205
1206 list_for_each_entry(vma, &nvbo->vma_list, head) {
1207 if (new_mem && new_mem->mem_type != TTM_PL_SYSTEM &&
1208 (new_mem->mem_type == TTM_PL_VRAM ||
1209 nvbo->page_shift != vma->vm->mmu->lpg_shift)) {
1210 nvkm_vm_map(vma, new_mem->mm_node);
1211 } else {
1212 WARN_ON(ttm_bo_wait(bo, false, false));
1213 nvkm_vm_unmap(vma);
1214 }
1215 }
1216}
1217
1218static int
1219nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
1220 struct nouveau_drm_tile **new_tile)
1221{
1222 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1223 struct drm_device *dev = drm->dev;
1224 struct nouveau_bo *nvbo = nouveau_bo(bo);
1225 u64 offset = new_mem->start << PAGE_SHIFT;
1226
1227 *new_tile = NULL;
1228 if (new_mem->mem_type != TTM_PL_VRAM)
1229 return 0;
1230
1231 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
1232 *new_tile = nv10_bo_set_tiling(dev, offset, new_mem->size,
1233 nvbo->tile_mode,
1234 nvbo->tile_flags);
1235 }
1236
1237 return 0;
1238}
1239
1240static void
1241nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1242 struct nouveau_drm_tile *new_tile,
1243 struct nouveau_drm_tile **old_tile)
1244{
1245 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1246 struct drm_device *dev = drm->dev;
1247 struct dma_fence *fence = reservation_object_get_excl(bo->resv);
1248
1249 nv10_bo_put_tile_region(dev, *old_tile, fence);
1250 *old_tile = new_tile;
1251}
1252
1253static int
1254nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
1255 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1256{
1257 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1258 struct nouveau_bo *nvbo = nouveau_bo(bo);
1259 struct ttm_mem_reg *old_mem = &bo->mem;
1260 struct nouveau_drm_tile *new_tile = NULL;
1261 int ret = 0;
1262
1263 ret = ttm_bo_wait(bo, intr, no_wait_gpu);
1264 if (ret)
1265 return ret;
1266
1267 if (nvbo->pin_refcnt)
1268 NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
1269
1270 if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1271 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
1272 if (ret)
1273 return ret;
1274 }
1275
1276 /* Fake bo copy. */
1277 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1278 BUG_ON(bo->mem.mm_node != NULL);
1279 bo->mem = *new_mem;
1280 new_mem->mm_node = NULL;
1281 goto out;
1282 }
1283
1284 /* Hardware assisted copy. */
1285 if (drm->ttm.move) {
1286 if (new_mem->mem_type == TTM_PL_SYSTEM)
1287 ret = nouveau_bo_move_flipd(bo, evict, intr,
1288 no_wait_gpu, new_mem);
1289 else if (old_mem->mem_type == TTM_PL_SYSTEM)
1290 ret = nouveau_bo_move_flips(bo, evict, intr,
1291 no_wait_gpu, new_mem);
1292 else
1293 ret = nouveau_bo_move_m2mf(bo, evict, intr,
1294 no_wait_gpu, new_mem);
1295 if (!ret)
1296 goto out;
1297 }
1298
1299 /* Fallback to software copy. */
1300 ret = ttm_bo_wait(bo, intr, no_wait_gpu);
1301 if (ret == 0)
1302 ret = ttm_bo_move_memcpy(bo, intr, no_wait_gpu, new_mem);
1303
1304out:
1305 if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1306 if (ret)
1307 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1308 else
1309 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1310 }
1311
1312 return ret;
1313}
1314
1315static int
1316nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1317{
1318 struct nouveau_bo *nvbo = nouveau_bo(bo);
1319
1320 return drm_vma_node_verify_access(&nvbo->gem.vma_node,
1321 filp->private_data);
1322}
1323
1324static int
1325nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1326{
1327 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
1328 struct nouveau_drm *drm = nouveau_bdev(bdev);
1329 struct nvkm_device *device = nvxx_device(&drm->device);
1330 struct nvkm_mem *node = mem->mm_node;
1331 int ret;
1332
1333 mem->bus.addr = NULL;
1334 mem->bus.offset = 0;
1335 mem->bus.size = mem->num_pages << PAGE_SHIFT;
1336 mem->bus.base = 0;
1337 mem->bus.is_iomem = false;
1338 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
1339 return -EINVAL;
1340 switch (mem->mem_type) {
1341 case TTM_PL_SYSTEM:
1342 /* System memory */
1343 return 0;
1344 case TTM_PL_TT:
1345#if IS_ENABLED(CONFIG_AGP)
1346 if (drm->agp.bridge) {
1347 mem->bus.offset = mem->start << PAGE_SHIFT;
1348 mem->bus.base = drm->agp.base;
1349 mem->bus.is_iomem = !drm->agp.cma;
1350 }
1351#endif
1352 if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA || !node->memtype)
1353 /* untiled */
1354 break;
1355 /* fallthrough, tiled memory */
1356 case TTM_PL_VRAM:
1357 mem->bus.offset = mem->start << PAGE_SHIFT;
1358 mem->bus.base = device->func->resource_addr(device, 1);
1359 mem->bus.is_iomem = true;
1360 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
1361 struct nvkm_bar *bar = nvxx_bar(&drm->device);
1362 int page_shift = 12;
1363 if (drm->device.info.family >= NV_DEVICE_INFO_V0_FERMI)
1364 page_shift = node->page_shift;
1365
1366 ret = nvkm_bar_umap(bar, node->size << 12, page_shift,
1367 &node->bar_vma);
1368 if (ret)
1369 return ret;
1370
1371 nvkm_vm_map(&node->bar_vma, node);
1372 mem->bus.offset = node->bar_vma.offset;
1373 }
1374 break;
1375 default:
1376 return -EINVAL;
1377 }
1378 return 0;
1379}
1380
1381static void
1382nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1383{
1384 struct nvkm_mem *node = mem->mm_node;
1385
1386 if (!node->bar_vma.node)
1387 return;
1388
1389 nvkm_vm_unmap(&node->bar_vma);
1390 nvkm_vm_put(&node->bar_vma);
1391}
1392
1393static int
1394nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1395{
1396 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1397 struct nouveau_bo *nvbo = nouveau_bo(bo);
1398 struct nvkm_device *device = nvxx_device(&drm->device);
1399 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1400 int i, ret;
1401
1402 /* as long as the bo isn't in vram, and isn't tiled, we've got
1403 * nothing to do here.
1404 */
1405 if (bo->mem.mem_type != TTM_PL_VRAM) {
1406 if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1407 !nouveau_bo_tile_layout(nvbo))
1408 return 0;
1409
1410 if (bo->mem.mem_type == TTM_PL_SYSTEM) {
1411 nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0);
1412
1413 ret = nouveau_bo_validate(nvbo, false, false);
1414 if (ret)
1415 return ret;
1416 }
1417 return 0;
1418 }
1419
1420 /* make sure bo is in mappable vram */
1421 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1422 bo->mem.start + bo->mem.num_pages < mappable)
1423 return 0;
1424
1425 for (i = 0; i < nvbo->placement.num_placement; ++i) {
1426 nvbo->placements[i].fpfn = 0;
1427 nvbo->placements[i].lpfn = mappable;
1428 }
1429
1430 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1431 nvbo->busy_placements[i].fpfn = 0;
1432 nvbo->busy_placements[i].lpfn = mappable;
1433 }
1434
1435 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
1436 return nouveau_bo_validate(nvbo, false, false);
1437}
1438
1439static int
1440nouveau_ttm_tt_populate(struct ttm_tt *ttm)
1441{
1442 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1443 struct nouveau_drm *drm;
1444 struct nvkm_device *device;
1445 struct drm_device *dev;
1446 struct device *pdev;
1447 unsigned i;
1448 int r;
1449 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1450
1451 if (ttm->state != tt_unpopulated)
1452 return 0;
1453
1454 if (slave && ttm->sg) {
1455 /* make userspace faulting work */
1456 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1457 ttm_dma->dma_address, ttm->num_pages);
1458 ttm->state = tt_unbound;
1459 return 0;
1460 }
1461
1462 drm = nouveau_bdev(ttm->bdev);
1463 device = nvxx_device(&drm->device);
1464 dev = drm->dev;
1465 pdev = device->dev;
1466
1467#if IS_ENABLED(CONFIG_AGP)
1468 if (drm->agp.bridge) {
1469 return ttm_agp_tt_populate(ttm);
1470 }
1471#endif
1472
1473#if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1474 if (swiotlb_nr_tbl()) {
1475 return ttm_dma_populate((void *)ttm, dev->dev);
1476 }
1477#endif
1478
1479 r = ttm_pool_populate(ttm);
1480 if (r) {
1481 return r;
1482 }
1483
1484 for (i = 0; i < ttm->num_pages; i++) {
1485 dma_addr_t addr;
1486
1487 addr = dma_map_page(pdev, ttm->pages[i], 0, PAGE_SIZE,
1488 DMA_BIDIRECTIONAL);
1489
1490 if (dma_mapping_error(pdev, addr)) {
1491 while (i--) {
1492 dma_unmap_page(pdev, ttm_dma->dma_address[i],
1493 PAGE_SIZE, DMA_BIDIRECTIONAL);
1494 ttm_dma->dma_address[i] = 0;
1495 }
1496 ttm_pool_unpopulate(ttm);
1497 return -EFAULT;
1498 }
1499
1500 ttm_dma->dma_address[i] = addr;
1501 }
1502 return 0;
1503}
1504
1505static void
1506nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1507{
1508 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1509 struct nouveau_drm *drm;
1510 struct nvkm_device *device;
1511 struct drm_device *dev;
1512 struct device *pdev;
1513 unsigned i;
1514 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1515
1516 if (slave)
1517 return;
1518
1519 drm = nouveau_bdev(ttm->bdev);
1520 device = nvxx_device(&drm->device);
1521 dev = drm->dev;
1522 pdev = device->dev;
1523
1524#if IS_ENABLED(CONFIG_AGP)
1525 if (drm->agp.bridge) {
1526 ttm_agp_tt_unpopulate(ttm);
1527 return;
1528 }
1529#endif
1530
1531#if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1532 if (swiotlb_nr_tbl()) {
1533 ttm_dma_unpopulate((void *)ttm, dev->dev);
1534 return;
1535 }
1536#endif
1537
1538 for (i = 0; i < ttm->num_pages; i++) {
1539 if (ttm_dma->dma_address[i]) {
1540 dma_unmap_page(pdev, ttm_dma->dma_address[i], PAGE_SIZE,
1541 DMA_BIDIRECTIONAL);
1542 }
1543 }
1544
1545 ttm_pool_unpopulate(ttm);
1546}
1547
1548void
1549nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1550{
1551 struct reservation_object *resv = nvbo->bo.resv;
1552
1553 if (exclusive)
1554 reservation_object_add_excl_fence(resv, &fence->base);
1555 else if (fence)
1556 reservation_object_add_shared_fence(resv, &fence->base);
1557}
1558
1559struct ttm_bo_driver nouveau_bo_driver = {
1560 .ttm_tt_create = &nouveau_ttm_tt_create,
1561 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1562 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1563 .invalidate_caches = nouveau_bo_invalidate_caches,
1564 .init_mem_type = nouveau_bo_init_mem_type,
1565 .eviction_valuable = ttm_bo_eviction_valuable,
1566 .evict_flags = nouveau_bo_evict_flags,
1567 .move_notify = nouveau_bo_move_ntfy,
1568 .move = nouveau_bo_move,
1569 .verify_access = nouveau_bo_verify_access,
1570 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1571 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1572 .io_mem_free = &nouveau_ttm_io_mem_free,
1573 .lru_tail = &ttm_bo_default_lru_tail,
1574 .swap_lru_tail = &ttm_bo_default_swap_lru_tail,
1575};
1576
1577struct nvkm_vma *
1578nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nvkm_vm *vm)
1579{
1580 struct nvkm_vma *vma;
1581 list_for_each_entry(vma, &nvbo->vma_list, head) {
1582 if (vma->vm == vm)
1583 return vma;
1584 }
1585
1586 return NULL;
1587}
1588
1589int
1590nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nvkm_vm *vm,
1591 struct nvkm_vma *vma)
1592{
1593 const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1594 int ret;
1595
1596 ret = nvkm_vm_get(vm, size, nvbo->page_shift,
1597 NV_MEM_ACCESS_RW, vma);
1598 if (ret)
1599 return ret;
1600
1601 if ( nvbo->bo.mem.mem_type != TTM_PL_SYSTEM &&
1602 (nvbo->bo.mem.mem_type == TTM_PL_VRAM ||
1603 nvbo->page_shift != vma->vm->mmu->lpg_shift))
1604 nvkm_vm_map(vma, nvbo->bo.mem.mm_node);
1605
1606 list_add_tail(&vma->head, &nvbo->vma_list);
1607 vma->refcount = 1;
1608 return 0;
1609}
1610
1611void
1612nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nvkm_vma *vma)
1613{
1614 if (vma->node) {
1615 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM)
1616 nvkm_vm_unmap(vma);
1617 nvkm_vm_put(vma);
1618 list_del(&vma->head);
1619 }
1620}