Loading...
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
4 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
5 */
6
7/* Does not work. Warning may block system in capture mode */
8/* #define USE_VAR48KRATE */
9
10#include <linux/io.h>
11#include <linux/delay.h>
12#include <linux/interrupt.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15#include <linux/slab.h>
16#include <linux/gameport.h>
17#include <linux/module.h>
18#include <linux/mutex.h>
19#include <sound/core.h>
20#include <sound/info.h>
21#include <sound/control.h>
22#include <sound/pcm.h>
23#include <sound/rawmidi.h>
24#include <sound/mpu401.h>
25#include <sound/opl3.h>
26#include <sound/sb.h>
27#include <sound/asoundef.h>
28#include <sound/initval.h>
29
30MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
31MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
32MODULE_LICENSE("GPL");
33MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
34 "{C-Media,CMI8738B},"
35 "{C-Media,CMI8338A},"
36 "{C-Media,CMI8338B}}");
37
38#if IS_REACHABLE(CONFIG_GAMEPORT)
39#define SUPPORT_JOYSTICK 1
40#endif
41
42static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
43static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
44static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
45static long mpu_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 1};
46static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
47static bool soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
48#ifdef SUPPORT_JOYSTICK
49static int joystick_port[SNDRV_CARDS];
50#endif
51
52module_param_array(index, int, NULL, 0444);
53MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
54module_param_array(id, charp, NULL, 0444);
55MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
56module_param_array(enable, bool, NULL, 0444);
57MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
58module_param_hw_array(mpu_port, long, ioport, NULL, 0444);
59MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
60module_param_hw_array(fm_port, long, ioport, NULL, 0444);
61MODULE_PARM_DESC(fm_port, "FM port.");
62module_param_array(soft_ac3, bool, NULL, 0444);
63MODULE_PARM_DESC(soft_ac3, "Software-conversion of raw SPDIF packets (model 033 only).");
64#ifdef SUPPORT_JOYSTICK
65module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
66MODULE_PARM_DESC(joystick_port, "Joystick port address.");
67#endif
68
69/*
70 * CM8x38 registers definition
71 */
72
73#define CM_REG_FUNCTRL0 0x00
74#define CM_RST_CH1 0x00080000
75#define CM_RST_CH0 0x00040000
76#define CM_CHEN1 0x00020000 /* ch1: enable */
77#define CM_CHEN0 0x00010000 /* ch0: enable */
78#define CM_PAUSE1 0x00000008 /* ch1: pause */
79#define CM_PAUSE0 0x00000004 /* ch0: pause */
80#define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
81#define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
82
83#define CM_REG_FUNCTRL1 0x04
84#define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
85#define CM_DSFC_SHIFT 13
86#define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
87#define CM_ASFC_SHIFT 10
88#define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
89#define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
90#define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
91#define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
92#define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
93#define CM_BREQ 0x00000010 /* bus master enabled */
94#define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
95#define CM_UART_EN 0x00000004 /* legacy UART */
96#define CM_JYSTK_EN 0x00000002 /* legacy joystick */
97#define CM_ZVPORT 0x00000001 /* ZVPORT */
98
99#define CM_REG_CHFORMAT 0x08
100
101#define CM_CHB3D5C 0x80000000 /* 5,6 channels */
102#define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
103#define CM_CHB3D 0x20000000 /* 4 channels */
104
105#define CM_CHIP_MASK1 0x1f000000
106#define CM_CHIP_037 0x01000000
107#define CM_SETLAT48 0x00800000 /* set latency timer 48h */
108#define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
109#define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
110#define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
111#define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
112#define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
113/* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
114
115#define CM_ADCBITLEN_MASK 0x0000C000
116#define CM_ADCBITLEN_16 0x00000000
117#define CM_ADCBITLEN_15 0x00004000
118#define CM_ADCBITLEN_14 0x00008000
119#define CM_ADCBITLEN_13 0x0000C000
120
121#define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
122#define CM_ADCDACLEN_060 0x00000000
123#define CM_ADCDACLEN_066 0x00001000
124#define CM_ADCDACLEN_130 0x00002000
125#define CM_ADCDACLEN_280 0x00003000
126
127#define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
128#define CM_ADCDLEN_ORIGINAL 0x00000000
129#define CM_ADCDLEN_EXTRA 0x00001000
130#define CM_ADCDLEN_24K 0x00002000
131#define CM_ADCDLEN_WEIGHT 0x00003000
132
133#define CM_CH1_SRATE_176K 0x00000800
134#define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
135#define CM_CH1_SRATE_88K 0x00000400
136#define CM_CH0_SRATE_176K 0x00000200
137#define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
138#define CM_CH0_SRATE_88K 0x00000100
139#define CM_CH0_SRATE_128K 0x00000300
140#define CM_CH0_SRATE_MASK 0x00000300
141
142#define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
143#define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
144#define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
145#define CM_SPDLOCKED 0x00000010
146
147#define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
148#define CM_CH1FMT_SHIFT 2
149#define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
150#define CM_CH0FMT_SHIFT 0
151
152#define CM_REG_INT_HLDCLR 0x0C
153#define CM_CHIP_MASK2 0xff000000
154#define CM_CHIP_8768 0x20000000
155#define CM_CHIP_055 0x08000000
156#define CM_CHIP_039 0x04000000
157#define CM_CHIP_039_6CH 0x01000000
158#define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
159#define CM_TDMA_INT_EN 0x00040000
160#define CM_CH1_INT_EN 0x00020000
161#define CM_CH0_INT_EN 0x00010000
162
163#define CM_REG_INT_STATUS 0x10
164#define CM_INTR 0x80000000
165#define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
166#define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
167#define CM_UARTINT 0x00010000
168#define CM_LTDMAINT 0x00008000
169#define CM_HTDMAINT 0x00004000
170#define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
171#define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
172#define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
173#define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
174#define CM_CH1BUSY 0x00000008
175#define CM_CH0BUSY 0x00000004
176#define CM_CHINT1 0x00000002
177#define CM_CHINT0 0x00000001
178
179#define CM_REG_LEGACY_CTRL 0x14
180#define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
181#define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
182#define CM_VMPU_330 0x00000000
183#define CM_VMPU_320 0x20000000
184#define CM_VMPU_310 0x40000000
185#define CM_VMPU_300 0x60000000
186#define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
187#define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
188#define CM_VSBSEL_220 0x00000000
189#define CM_VSBSEL_240 0x04000000
190#define CM_VSBSEL_260 0x08000000
191#define CM_VSBSEL_280 0x0C000000
192#define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
193#define CM_FMSEL_388 0x00000000
194#define CM_FMSEL_3C8 0x01000000
195#define CM_FMSEL_3E0 0x02000000
196#define CM_FMSEL_3E8 0x03000000
197#define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
198#define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
199#define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
200#define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
201#define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
202#define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
203#define CM_C_EECS 0x00040000
204#define CM_C_EEDI46 0x00020000
205#define CM_C_EECK46 0x00010000
206#define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
207#define CM_CENTR2LIN 0x00004000 /* line-in as center out */
208#define CM_BASE2LIN 0x00002000 /* line-in as bass out */
209#define CM_EXBASEN 0x00001000 /* external bass input enable */
210
211#define CM_REG_MISC_CTRL 0x18
212#define CM_PWD 0x80000000 /* power down */
213#define CM_RESET 0x40000000
214#define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
215#define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
216#define CM_TXVX 0x08000000 /* model 037? */
217#define CM_N4SPK3D 0x04000000 /* copy front to rear */
218#define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
219#define CM_SPDIF48K 0x01000000 /* write */
220#define CM_SPATUS48K 0x01000000 /* read */
221#define CM_ENDBDAC 0x00800000 /* enable double dac */
222#define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
223#define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
224#define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
225#define CM_FM_EN 0x00080000 /* enable legacy FM */
226#define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
227#define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
228#define CM_VIDWPDSB 0x00010000 /* model 037? */
229#define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
230#define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
231#define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
232#define CM_VIDWPPRT 0x00002000 /* model 037? */
233#define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
234#define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
235#define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
236#define CM_ENCENTER 0x00000080
237#define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */
238#define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
239#define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */
240#define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
241#define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
242#define CM_UPDDMA_2048 0x00000000
243#define CM_UPDDMA_1024 0x00000004
244#define CM_UPDDMA_512 0x00000008
245#define CM_UPDDMA_256 0x0000000C
246#define CM_TWAIT_MASK 0x00000003 /* model 037 */
247#define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
248#define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
249
250#define CM_REG_TDMA_POSITION 0x1C
251#define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
252#define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
253
254 /* byte */
255#define CM_REG_MIXER0 0x20
256#define CM_REG_SBVR 0x20 /* write: sb16 version */
257#define CM_REG_DEV 0x20 /* read: hardware device version */
258
259#define CM_REG_MIXER21 0x21
260#define CM_UNKNOWN_21_MASK 0x78 /* ? */
261#define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
262#define CM_PROINV 0x02 /* SBPro left/right channel switching */
263#define CM_X_SB16 0x01 /* SB16 compatible */
264
265#define CM_REG_SB16_DATA 0x22
266#define CM_REG_SB16_ADDR 0x23
267
268#define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
269#define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
270#define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
271#define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
272
273#define CM_REG_MIXER1 0x24
274#define CM_FMMUTE 0x80 /* mute FM */
275#define CM_FMMUTE_SHIFT 7
276#define CM_WSMUTE 0x40 /* mute PCM */
277#define CM_WSMUTE_SHIFT 6
278#define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
279#define CM_REAR2LIN_SHIFT 5
280#define CM_REAR2FRONT 0x10 /* exchange rear/front */
281#define CM_REAR2FRONT_SHIFT 4
282#define CM_WAVEINL 0x08 /* digital wave rec. left chan */
283#define CM_WAVEINL_SHIFT 3
284#define CM_WAVEINR 0x04 /* digical wave rec. right */
285#define CM_WAVEINR_SHIFT 2
286#define CM_X3DEN 0x02 /* 3D surround enable */
287#define CM_X3DEN_SHIFT 1
288#define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
289#define CM_CDPLAY_SHIFT 0
290
291#define CM_REG_MIXER2 0x25
292#define CM_RAUXREN 0x80 /* AUX right capture */
293#define CM_RAUXREN_SHIFT 7
294#define CM_RAUXLEN 0x40 /* AUX left capture */
295#define CM_RAUXLEN_SHIFT 6
296#define CM_VAUXRM 0x20 /* AUX right mute */
297#define CM_VAUXRM_SHIFT 5
298#define CM_VAUXLM 0x10 /* AUX left mute */
299#define CM_VAUXLM_SHIFT 4
300#define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
301#define CM_VADMIC_SHIFT 1
302#define CM_MICGAINZ 0x01 /* mic boost */
303#define CM_MICGAINZ_SHIFT 0
304
305#define CM_REG_MIXER3 0x24
306#define CM_REG_AUX_VOL 0x26
307#define CM_VAUXL_MASK 0xf0
308#define CM_VAUXR_MASK 0x0f
309
310#define CM_REG_MISC 0x27
311#define CM_UNKNOWN_27_MASK 0xd8 /* ? */
312#define CM_XGPO1 0x20
313// #define CM_XGPBIO 0x04
314#define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
315#define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
316#define CM_SPDVALID 0x02 /* spdif input valid check */
317#define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
318
319#define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
320/*
321 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
322 * or identical with AC97 codec?
323 */
324#define CM_REG_EXTERN_CODEC CM_REG_AC97
325
326/*
327 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
328 */
329#define CM_REG_MPU_PCI 0x40
330
331/*
332 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
333 */
334#define CM_REG_FM_PCI 0x50
335
336/*
337 * access from SB-mixer port
338 */
339#define CM_REG_EXTENT_IND 0xf0
340#define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
341#define CM_VPHONE_SHIFT 5
342#define CM_VPHOM 0x10 /* Phone mute control */
343#define CM_VSPKM 0x08 /* Speaker mute control, default high */
344#define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
345#define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
346#define CM_VADMIC3 0x01 /* Mic record boost */
347
348/*
349 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
350 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
351 * unit (readonly?).
352 */
353#define CM_REG_PLL 0xf8
354
355/*
356 * extended registers
357 */
358#define CM_REG_CH0_FRAME1 0x80 /* write: base address */
359#define CM_REG_CH0_FRAME2 0x84 /* read: current address */
360#define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
361#define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
362
363#define CM_REG_EXT_MISC 0x90
364#define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
365#define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
366#define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
367#define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
368#define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
369#define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
370#define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
371#define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
372
373/*
374 * size of i/o region
375 */
376#define CM_EXTENT_CODEC 0x100
377#define CM_EXTENT_MIDI 0x2
378#define CM_EXTENT_SYNTH 0x4
379
380
381/*
382 * channels for playback / capture
383 */
384#define CM_CH_PLAY 0
385#define CM_CH_CAPT 1
386
387/*
388 * flags to check device open/close
389 */
390#define CM_OPEN_NONE 0
391#define CM_OPEN_CH_MASK 0x01
392#define CM_OPEN_DAC 0x10
393#define CM_OPEN_ADC 0x20
394#define CM_OPEN_SPDIF 0x40
395#define CM_OPEN_MCHAN 0x80
396#define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
397#define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
398#define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
399#define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
400#define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
401#define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
402
403
404#if CM_CH_PLAY == 1
405#define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
406#define CM_PLAYBACK_SPDF CM_SPDF_1
407#define CM_CAPTURE_SPDF CM_SPDF_0
408#else
409#define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
410#define CM_PLAYBACK_SPDF CM_SPDF_0
411#define CM_CAPTURE_SPDF CM_SPDF_1
412#endif
413
414
415/*
416 * driver data
417 */
418
419struct cmipci_pcm {
420 struct snd_pcm_substream *substream;
421 u8 running; /* dac/adc running? */
422 u8 fmt; /* format bits */
423 u8 is_dac;
424 u8 needs_silencing;
425 unsigned int dma_size; /* in frames */
426 unsigned int shift;
427 unsigned int ch; /* channel (0/1) */
428 unsigned int offset; /* physical address of the buffer */
429};
430
431/* mixer elements toggled/resumed during ac3 playback */
432struct cmipci_mixer_auto_switches {
433 const char *name; /* switch to toggle */
434 int toggle_on; /* value to change when ac3 mode */
435};
436static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
437 {"PCM Playback Switch", 0},
438 {"IEC958 Output Switch", 1},
439 {"IEC958 Mix Analog", 0},
440 // {"IEC958 Out To DAC", 1}, // no longer used
441 {"IEC958 Loop", 0},
442};
443#define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
444
445struct cmipci {
446 struct snd_card *card;
447
448 struct pci_dev *pci;
449 unsigned int device; /* device ID */
450 int irq;
451
452 unsigned long iobase;
453 unsigned int ctrl; /* FUNCTRL0 current value */
454
455 struct snd_pcm *pcm; /* DAC/ADC PCM */
456 struct snd_pcm *pcm2; /* 2nd DAC */
457 struct snd_pcm *pcm_spdif; /* SPDIF */
458
459 int chip_version;
460 int max_channels;
461 unsigned int can_ac3_sw: 1;
462 unsigned int can_ac3_hw: 1;
463 unsigned int can_multi_ch: 1;
464 unsigned int can_96k: 1; /* samplerate above 48k */
465 unsigned int do_soft_ac3: 1;
466
467 unsigned int spdif_playback_avail: 1; /* spdif ready? */
468 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
469 int spdif_counter; /* for software AC3 */
470
471 unsigned int dig_status;
472 unsigned int dig_pcm_status;
473
474 struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
475
476 int opened[2]; /* open mode */
477 struct mutex open_mutex;
478
479 unsigned int mixer_insensitive: 1;
480 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
481 int mixer_res_status[CM_SAVED_MIXERS];
482
483 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
484
485 /* external MIDI */
486 struct snd_rawmidi *rmidi;
487
488#ifdef SUPPORT_JOYSTICK
489 struct gameport *gameport;
490#endif
491
492 spinlock_t reg_lock;
493
494#ifdef CONFIG_PM_SLEEP
495 unsigned int saved_regs[0x20];
496 unsigned char saved_mixers[0x20];
497#endif
498};
499
500
501/* read/write operations for dword register */
502static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
503{
504 outl(data, cm->iobase + cmd);
505}
506
507static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
508{
509 return inl(cm->iobase + cmd);
510}
511
512/* read/write operations for word register */
513static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
514{
515 outw(data, cm->iobase + cmd);
516}
517
518static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
519{
520 return inw(cm->iobase + cmd);
521}
522
523/* read/write operations for byte register */
524static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
525{
526 outb(data, cm->iobase + cmd);
527}
528
529static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
530{
531 return inb(cm->iobase + cmd);
532}
533
534/* bit operations for dword register */
535static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
536{
537 unsigned int val, oval;
538 val = oval = inl(cm->iobase + cmd);
539 val |= flag;
540 if (val == oval)
541 return 0;
542 outl(val, cm->iobase + cmd);
543 return 1;
544}
545
546static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
547{
548 unsigned int val, oval;
549 val = oval = inl(cm->iobase + cmd);
550 val &= ~flag;
551 if (val == oval)
552 return 0;
553 outl(val, cm->iobase + cmd);
554 return 1;
555}
556
557/* bit operations for byte register */
558static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
559{
560 unsigned char val, oval;
561 val = oval = inb(cm->iobase + cmd);
562 val |= flag;
563 if (val == oval)
564 return 0;
565 outb(val, cm->iobase + cmd);
566 return 1;
567}
568
569static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
570{
571 unsigned char val, oval;
572 val = oval = inb(cm->iobase + cmd);
573 val &= ~flag;
574 if (val == oval)
575 return 0;
576 outb(val, cm->iobase + cmd);
577 return 1;
578}
579
580
581/*
582 * PCM interface
583 */
584
585/*
586 * calculate frequency
587 */
588
589static const unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
590
591static unsigned int snd_cmipci_rate_freq(unsigned int rate)
592{
593 unsigned int i;
594
595 for (i = 0; i < ARRAY_SIZE(rates); i++) {
596 if (rates[i] == rate)
597 return i;
598 }
599 snd_BUG();
600 return 0;
601}
602
603#ifdef USE_VAR48KRATE
604/*
605 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
606 * does it this way .. maybe not. Never get any information from C-Media about
607 * that <werner@suse.de>.
608 */
609static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
610{
611 unsigned int delta, tolerance;
612 int xm, xn, xr;
613
614 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
615 rate <<= 1;
616 *n = -1;
617 if (*r > 0xff)
618 goto out;
619 tolerance = rate*CM_TOLERANCE_RATE;
620
621 for (xn = (1+2); xn < (0x1f+2); xn++) {
622 for (xm = (1+2); xm < (0xff+2); xm++) {
623 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
624
625 if (xr < rate)
626 delta = rate - xr;
627 else
628 delta = xr - rate;
629
630 /*
631 * If we found one, remember this,
632 * and try to find a closer one
633 */
634 if (delta < tolerance) {
635 tolerance = delta;
636 *m = xm - 2;
637 *n = xn - 2;
638 }
639 }
640 }
641out:
642 return (*n > -1);
643}
644
645/*
646 * Program pll register bits, I assume that the 8 registers 0xf8 up to 0xff
647 * are mapped onto the 8 ADC/DAC sampling frequency which can be chosen
648 * at the register CM_REG_FUNCTRL1 (0x04).
649 * Problem: other ways are also possible (any information about that?)
650 */
651static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
652{
653 unsigned int reg = CM_REG_PLL + slot;
654 /*
655 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
656 * for DSFC/ASFC (000 up to 111).
657 */
658
659 /* FIXME: Init (Do we've to set an other register first before programming?) */
660
661 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
662 snd_cmipci_write_b(cm, reg, rate>>8);
663 snd_cmipci_write_b(cm, reg, rate&0xff);
664
665 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
666}
667#endif /* USE_VAR48KRATE */
668
669static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
670 struct snd_pcm_hw_params *hw_params)
671{
672 struct cmipci *cm = snd_pcm_substream_chip(substream);
673 if (params_channels(hw_params) > 2) {
674 mutex_lock(&cm->open_mutex);
675 if (cm->opened[CM_CH_PLAY]) {
676 mutex_unlock(&cm->open_mutex);
677 return -EBUSY;
678 }
679 /* reserve the channel A */
680 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
681 mutex_unlock(&cm->open_mutex);
682 }
683 return 0;
684}
685
686static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
687{
688 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
689 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
690 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
691 udelay(10);
692}
693
694
695/*
696 */
697
698static const unsigned int hw_channels[] = {1, 2, 4, 6, 8};
699static const struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
700 .count = 3,
701 .list = hw_channels,
702 .mask = 0,
703};
704static const struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
705 .count = 4,
706 .list = hw_channels,
707 .mask = 0,
708};
709static const struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
710 .count = 5,
711 .list = hw_channels,
712 .mask = 0,
713};
714
715static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
716{
717 if (channels > 2) {
718 if (!cm->can_multi_ch || !rec->ch)
719 return -EINVAL;
720 if (rec->fmt != 0x03) /* stereo 16bit only */
721 return -EINVAL;
722 }
723
724 if (cm->can_multi_ch) {
725 spin_lock_irq(&cm->reg_lock);
726 if (channels > 2) {
727 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
728 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
729 } else {
730 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
731 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
732 }
733 if (channels == 8)
734 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
735 else
736 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
737 if (channels == 6) {
738 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
739 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
740 } else {
741 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
742 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
743 }
744 if (channels == 4)
745 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
746 else
747 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
748 spin_unlock_irq(&cm->reg_lock);
749 }
750 return 0;
751}
752
753
754/*
755 * prepare playback/capture channel
756 * channel to be used must have been set in rec->ch.
757 */
758static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
759 struct snd_pcm_substream *substream)
760{
761 unsigned int reg, freq, freq_ext, val;
762 unsigned int period_size;
763 struct snd_pcm_runtime *runtime = substream->runtime;
764
765 rec->fmt = 0;
766 rec->shift = 0;
767 if (snd_pcm_format_width(runtime->format) >= 16) {
768 rec->fmt |= 0x02;
769 if (snd_pcm_format_width(runtime->format) > 16)
770 rec->shift++; /* 24/32bit */
771 }
772 if (runtime->channels > 1)
773 rec->fmt |= 0x01;
774 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
775 dev_dbg(cm->card->dev, "cannot set dac channels\n");
776 return -EINVAL;
777 }
778
779 rec->offset = runtime->dma_addr;
780 /* buffer and period sizes in frame */
781 rec->dma_size = runtime->buffer_size << rec->shift;
782 period_size = runtime->period_size << rec->shift;
783 if (runtime->channels > 2) {
784 /* multi-channels */
785 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
786 period_size = (period_size * runtime->channels) / 2;
787 }
788
789 spin_lock_irq(&cm->reg_lock);
790
791 /* set buffer address */
792 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
793 snd_cmipci_write(cm, reg, rec->offset);
794 /* program sample counts */
795 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
796 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
797 snd_cmipci_write_w(cm, reg + 2, period_size - 1);
798
799 /* set adc/dac flag */
800 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
801 if (rec->is_dac)
802 cm->ctrl &= ~val;
803 else
804 cm->ctrl |= val;
805 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
806 /* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */
807
808 /* set sample rate */
809 freq = 0;
810 freq_ext = 0;
811 if (runtime->rate > 48000)
812 switch (runtime->rate) {
813 case 88200: freq_ext = CM_CH0_SRATE_88K; break;
814 case 96000: freq_ext = CM_CH0_SRATE_96K; break;
815 case 128000: freq_ext = CM_CH0_SRATE_128K; break;
816 default: snd_BUG(); break;
817 }
818 else
819 freq = snd_cmipci_rate_freq(runtime->rate);
820 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
821 if (rec->ch) {
822 val &= ~CM_DSFC_MASK;
823 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
824 } else {
825 val &= ~CM_ASFC_MASK;
826 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
827 }
828 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
829 dev_dbg(cm->card->dev, "functrl1 = %08x\n", val);
830
831 /* set format */
832 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
833 if (rec->ch) {
834 val &= ~CM_CH1FMT_MASK;
835 val |= rec->fmt << CM_CH1FMT_SHIFT;
836 } else {
837 val &= ~CM_CH0FMT_MASK;
838 val |= rec->fmt << CM_CH0FMT_SHIFT;
839 }
840 if (cm->can_96k) {
841 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
842 val |= freq_ext << (rec->ch * 2);
843 }
844 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
845 dev_dbg(cm->card->dev, "chformat = %08x\n", val);
846
847 if (!rec->is_dac && cm->chip_version) {
848 if (runtime->rate > 44100)
849 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
850 else
851 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
852 }
853
854 rec->running = 0;
855 spin_unlock_irq(&cm->reg_lock);
856
857 return 0;
858}
859
860/*
861 * PCM trigger/stop
862 */
863static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
864 int cmd)
865{
866 unsigned int inthld, chen, reset, pause;
867 int result = 0;
868
869 inthld = CM_CH0_INT_EN << rec->ch;
870 chen = CM_CHEN0 << rec->ch;
871 reset = CM_RST_CH0 << rec->ch;
872 pause = CM_PAUSE0 << rec->ch;
873
874 spin_lock(&cm->reg_lock);
875 switch (cmd) {
876 case SNDRV_PCM_TRIGGER_START:
877 rec->running = 1;
878 /* set interrupt */
879 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
880 cm->ctrl |= chen;
881 /* enable channel */
882 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
883 dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl);
884 break;
885 case SNDRV_PCM_TRIGGER_STOP:
886 rec->running = 0;
887 /* disable interrupt */
888 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
889 /* reset */
890 cm->ctrl &= ~chen;
891 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
892 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
893 rec->needs_silencing = rec->is_dac;
894 break;
895 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
896 case SNDRV_PCM_TRIGGER_SUSPEND:
897 cm->ctrl |= pause;
898 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
899 break;
900 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
901 case SNDRV_PCM_TRIGGER_RESUME:
902 cm->ctrl &= ~pause;
903 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
904 break;
905 default:
906 result = -EINVAL;
907 break;
908 }
909 spin_unlock(&cm->reg_lock);
910 return result;
911}
912
913/*
914 * return the current pointer
915 */
916static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
917 struct snd_pcm_substream *substream)
918{
919 size_t ptr;
920 unsigned int reg, rem, tries;
921
922 if (!rec->running)
923 return 0;
924#if 1 // this seems better..
925 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
926 for (tries = 0; tries < 3; tries++) {
927 rem = snd_cmipci_read_w(cm, reg);
928 if (rem < rec->dma_size)
929 goto ok;
930 }
931 dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem);
932 return SNDRV_PCM_POS_XRUN;
933ok:
934 ptr = (rec->dma_size - (rem + 1)) >> rec->shift;
935#else
936 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
937 ptr = snd_cmipci_read(cm, reg) - rec->offset;
938 ptr = bytes_to_frames(substream->runtime, ptr);
939#endif
940 if (substream->runtime->channels > 2)
941 ptr = (ptr * 2) / substream->runtime->channels;
942 return ptr;
943}
944
945/*
946 * playback
947 */
948
949static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
950 int cmd)
951{
952 struct cmipci *cm = snd_pcm_substream_chip(substream);
953 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
954}
955
956static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
957{
958 struct cmipci *cm = snd_pcm_substream_chip(substream);
959 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
960}
961
962
963
964/*
965 * capture
966 */
967
968static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
969 int cmd)
970{
971 struct cmipci *cm = snd_pcm_substream_chip(substream);
972 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
973}
974
975static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
976{
977 struct cmipci *cm = snd_pcm_substream_chip(substream);
978 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
979}
980
981
982/*
983 * hw preparation for spdif
984 */
985
986static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
987 struct snd_ctl_elem_info *uinfo)
988{
989 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
990 uinfo->count = 1;
991 return 0;
992}
993
994static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
995 struct snd_ctl_elem_value *ucontrol)
996{
997 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
998 int i;
999
1000 spin_lock_irq(&chip->reg_lock);
1001 for (i = 0; i < 4; i++)
1002 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
1003 spin_unlock_irq(&chip->reg_lock);
1004 return 0;
1005}
1006
1007static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1008 struct snd_ctl_elem_value *ucontrol)
1009{
1010 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1011 int i, change;
1012 unsigned int val;
1013
1014 val = 0;
1015 spin_lock_irq(&chip->reg_lock);
1016 for (i = 0; i < 4; i++)
1017 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1018 change = val != chip->dig_status;
1019 chip->dig_status = val;
1020 spin_unlock_irq(&chip->reg_lock);
1021 return change;
1022}
1023
1024static const struct snd_kcontrol_new snd_cmipci_spdif_default =
1025{
1026 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1027 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1028 .info = snd_cmipci_spdif_default_info,
1029 .get = snd_cmipci_spdif_default_get,
1030 .put = snd_cmipci_spdif_default_put
1031};
1032
1033static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1034 struct snd_ctl_elem_info *uinfo)
1035{
1036 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1037 uinfo->count = 1;
1038 return 0;
1039}
1040
1041static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1042 struct snd_ctl_elem_value *ucontrol)
1043{
1044 ucontrol->value.iec958.status[0] = 0xff;
1045 ucontrol->value.iec958.status[1] = 0xff;
1046 ucontrol->value.iec958.status[2] = 0xff;
1047 ucontrol->value.iec958.status[3] = 0xff;
1048 return 0;
1049}
1050
1051static const struct snd_kcontrol_new snd_cmipci_spdif_mask =
1052{
1053 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1054 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1055 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1056 .info = snd_cmipci_spdif_mask_info,
1057 .get = snd_cmipci_spdif_mask_get,
1058};
1059
1060static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1061 struct snd_ctl_elem_info *uinfo)
1062{
1063 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1064 uinfo->count = 1;
1065 return 0;
1066}
1067
1068static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1069 struct snd_ctl_elem_value *ucontrol)
1070{
1071 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1072 int i;
1073
1074 spin_lock_irq(&chip->reg_lock);
1075 for (i = 0; i < 4; i++)
1076 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1077 spin_unlock_irq(&chip->reg_lock);
1078 return 0;
1079}
1080
1081static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1082 struct snd_ctl_elem_value *ucontrol)
1083{
1084 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1085 int i, change;
1086 unsigned int val;
1087
1088 val = 0;
1089 spin_lock_irq(&chip->reg_lock);
1090 for (i = 0; i < 4; i++)
1091 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1092 change = val != chip->dig_pcm_status;
1093 chip->dig_pcm_status = val;
1094 spin_unlock_irq(&chip->reg_lock);
1095 return change;
1096}
1097
1098static const struct snd_kcontrol_new snd_cmipci_spdif_stream =
1099{
1100 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1101 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1102 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1103 .info = snd_cmipci_spdif_stream_info,
1104 .get = snd_cmipci_spdif_stream_get,
1105 .put = snd_cmipci_spdif_stream_put
1106};
1107
1108/*
1109 */
1110
1111/* save mixer setting and mute for AC3 playback */
1112static int save_mixer_state(struct cmipci *cm)
1113{
1114 if (! cm->mixer_insensitive) {
1115 struct snd_ctl_elem_value *val;
1116 unsigned int i;
1117
1118 val = kmalloc(sizeof(*val), GFP_KERNEL);
1119 if (!val)
1120 return -ENOMEM;
1121 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1122 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1123 if (ctl) {
1124 int event;
1125 memset(val, 0, sizeof(*val));
1126 ctl->get(ctl, val);
1127 cm->mixer_res_status[i] = val->value.integer.value[0];
1128 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1129 event = SNDRV_CTL_EVENT_MASK_INFO;
1130 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1131 ctl->put(ctl, val); /* toggle */
1132 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1133 }
1134 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1135 snd_ctl_notify(cm->card, event, &ctl->id);
1136 }
1137 }
1138 kfree(val);
1139 cm->mixer_insensitive = 1;
1140 }
1141 return 0;
1142}
1143
1144
1145/* restore the previously saved mixer status */
1146static void restore_mixer_state(struct cmipci *cm)
1147{
1148 if (cm->mixer_insensitive) {
1149 struct snd_ctl_elem_value *val;
1150 unsigned int i;
1151
1152 val = kmalloc(sizeof(*val), GFP_KERNEL);
1153 if (!val)
1154 return;
1155 cm->mixer_insensitive = 0; /* at first clear this;
1156 otherwise the changes will be ignored */
1157 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1158 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1159 if (ctl) {
1160 int event;
1161
1162 memset(val, 0, sizeof(*val));
1163 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1164 ctl->get(ctl, val);
1165 event = SNDRV_CTL_EVENT_MASK_INFO;
1166 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1167 val->value.integer.value[0] = cm->mixer_res_status[i];
1168 ctl->put(ctl, val);
1169 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1170 }
1171 snd_ctl_notify(cm->card, event, &ctl->id);
1172 }
1173 }
1174 kfree(val);
1175 }
1176}
1177
1178/* spinlock held! */
1179static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1180{
1181 if (do_ac3) {
1182 /* AC3EN for 037 */
1183 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1184 /* AC3EN for 039 */
1185 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1186
1187 if (cm->can_ac3_hw) {
1188 /* SPD24SEL for 037, 0x02 */
1189 /* SPD24SEL for 039, 0x20, but cannot be set */
1190 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1191 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1192 } else { /* can_ac3_sw */
1193 /* SPD32SEL for 037 & 039, 0x20 */
1194 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1195 /* set 176K sample rate to fix 033 HW bug */
1196 if (cm->chip_version == 33) {
1197 if (rate >= 48000) {
1198 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1199 } else {
1200 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1201 }
1202 }
1203 }
1204
1205 } else {
1206 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1207 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1208
1209 if (cm->can_ac3_hw) {
1210 /* chip model >= 37 */
1211 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1212 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1213 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1214 } else {
1215 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1216 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1217 }
1218 } else {
1219 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1220 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1221 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1222 }
1223 }
1224}
1225
1226static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1227{
1228 int rate, err;
1229
1230 rate = subs->runtime->rate;
1231
1232 if (up && do_ac3)
1233 if ((err = save_mixer_state(cm)) < 0)
1234 return err;
1235
1236 spin_lock_irq(&cm->reg_lock);
1237 cm->spdif_playback_avail = up;
1238 if (up) {
1239 /* they are controlled via "IEC958 Output Switch" */
1240 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1241 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1242 if (cm->spdif_playback_enabled)
1243 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1244 setup_ac3(cm, subs, do_ac3, rate);
1245
1246 if (rate == 48000 || rate == 96000)
1247 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1248 else
1249 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1250 if (rate > 48000)
1251 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1252 else
1253 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1254 } else {
1255 /* they are controlled via "IEC958 Output Switch" */
1256 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1257 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1258 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1259 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1260 setup_ac3(cm, subs, 0, 0);
1261 }
1262 spin_unlock_irq(&cm->reg_lock);
1263 return 0;
1264}
1265
1266
1267/*
1268 * preparation
1269 */
1270
1271/* playback - enable spdif only on the certain condition */
1272static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1273{
1274 struct cmipci *cm = snd_pcm_substream_chip(substream);
1275 int rate = substream->runtime->rate;
1276 int err, do_spdif, do_ac3 = 0;
1277
1278 do_spdif = (rate >= 44100 && rate <= 96000 &&
1279 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1280 substream->runtime->channels == 2);
1281 if (do_spdif && cm->can_ac3_hw)
1282 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1283 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1284 return err;
1285 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1286}
1287
1288/* playback (via device #2) - enable spdif always */
1289static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1290{
1291 struct cmipci *cm = snd_pcm_substream_chip(substream);
1292 int err, do_ac3;
1293
1294 if (cm->can_ac3_hw)
1295 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1296 else
1297 do_ac3 = 1; /* doesn't matter */
1298 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1299 return err;
1300 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1301}
1302
1303/*
1304 * Apparently, the samples last played on channel A stay in some buffer, even
1305 * after the channel is reset, and get added to the data for the rear DACs when
1306 * playing a multichannel stream on channel B. This is likely to generate
1307 * wraparounds and thus distortions.
1308 * To avoid this, we play at least one zero sample after the actual stream has
1309 * stopped.
1310 */
1311static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1312{
1313 struct snd_pcm_runtime *runtime = rec->substream->runtime;
1314 unsigned int reg, val;
1315
1316 if (rec->needs_silencing && runtime && runtime->dma_area) {
1317 /* set up a small silence buffer */
1318 memset(runtime->dma_area, 0, PAGE_SIZE);
1319 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1320 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1321 snd_cmipci_write(cm, reg, val);
1322
1323 /* configure for 16 bits, 2 channels, 8 kHz */
1324 if (runtime->channels > 2)
1325 set_dac_channels(cm, rec, 2);
1326 spin_lock_irq(&cm->reg_lock);
1327 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1328 val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1329 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1330 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1331 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1332 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1333 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1334 if (cm->can_96k)
1335 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
1336 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1337
1338 /* start stream (we don't need interrupts) */
1339 cm->ctrl |= CM_CHEN0 << rec->ch;
1340 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1341 spin_unlock_irq(&cm->reg_lock);
1342
1343 msleep(1);
1344
1345 /* stop and reset stream */
1346 spin_lock_irq(&cm->reg_lock);
1347 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1348 val = CM_RST_CH0 << rec->ch;
1349 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1350 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1351 spin_unlock_irq(&cm->reg_lock);
1352
1353 rec->needs_silencing = 0;
1354 }
1355}
1356
1357static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1358{
1359 struct cmipci *cm = snd_pcm_substream_chip(substream);
1360 setup_spdif_playback(cm, substream, 0, 0);
1361 restore_mixer_state(cm);
1362 snd_cmipci_silence_hack(cm, &cm->channel[0]);
1363 return 0;
1364}
1365
1366static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1367{
1368 struct cmipci *cm = snd_pcm_substream_chip(substream);
1369 snd_cmipci_silence_hack(cm, &cm->channel[1]);
1370 return 0;
1371}
1372
1373/* capture */
1374static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1375{
1376 struct cmipci *cm = snd_pcm_substream_chip(substream);
1377 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1378}
1379
1380/* capture with spdif (via device #2) */
1381static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1382{
1383 struct cmipci *cm = snd_pcm_substream_chip(substream);
1384
1385 spin_lock_irq(&cm->reg_lock);
1386 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1387 if (cm->can_96k) {
1388 if (substream->runtime->rate > 48000)
1389 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1390 else
1391 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1392 }
1393 if (snd_pcm_format_width(substream->runtime->format) > 16)
1394 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1395 else
1396 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1397
1398 spin_unlock_irq(&cm->reg_lock);
1399
1400 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1401}
1402
1403static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1404{
1405 struct cmipci *cm = snd_pcm_substream_chip(subs);
1406
1407 spin_lock_irq(&cm->reg_lock);
1408 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1409 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1410 spin_unlock_irq(&cm->reg_lock);
1411
1412 return 0;
1413}
1414
1415
1416/*
1417 * interrupt handler
1418 */
1419static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1420{
1421 struct cmipci *cm = dev_id;
1422 unsigned int status, mask = 0;
1423
1424 /* fastpath out, to ease interrupt sharing */
1425 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1426 if (!(status & CM_INTR))
1427 return IRQ_NONE;
1428
1429 /* acknowledge interrupt */
1430 spin_lock(&cm->reg_lock);
1431 if (status & CM_CHINT0)
1432 mask |= CM_CH0_INT_EN;
1433 if (status & CM_CHINT1)
1434 mask |= CM_CH1_INT_EN;
1435 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1436 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1437 spin_unlock(&cm->reg_lock);
1438
1439 if (cm->rmidi && (status & CM_UARTINT))
1440 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1441
1442 if (cm->pcm) {
1443 if ((status & CM_CHINT0) && cm->channel[0].running)
1444 snd_pcm_period_elapsed(cm->channel[0].substream);
1445 if ((status & CM_CHINT1) && cm->channel[1].running)
1446 snd_pcm_period_elapsed(cm->channel[1].substream);
1447 }
1448 return IRQ_HANDLED;
1449}
1450
1451/*
1452 * h/w infos
1453 */
1454
1455/* playback on channel A */
1456static const struct snd_pcm_hardware snd_cmipci_playback =
1457{
1458 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1459 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1460 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1461 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1462 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1463 .rate_min = 5512,
1464 .rate_max = 48000,
1465 .channels_min = 1,
1466 .channels_max = 2,
1467 .buffer_bytes_max = (128*1024),
1468 .period_bytes_min = 64,
1469 .period_bytes_max = (128*1024),
1470 .periods_min = 2,
1471 .periods_max = 1024,
1472 .fifo_size = 0,
1473};
1474
1475/* capture on channel B */
1476static const struct snd_pcm_hardware snd_cmipci_capture =
1477{
1478 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1479 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1480 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1481 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1482 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1483 .rate_min = 5512,
1484 .rate_max = 48000,
1485 .channels_min = 1,
1486 .channels_max = 2,
1487 .buffer_bytes_max = (128*1024),
1488 .period_bytes_min = 64,
1489 .period_bytes_max = (128*1024),
1490 .periods_min = 2,
1491 .periods_max = 1024,
1492 .fifo_size = 0,
1493};
1494
1495/* playback on channel B - stereo 16bit only? */
1496static const struct snd_pcm_hardware snd_cmipci_playback2 =
1497{
1498 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1499 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1500 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1501 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1502 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1503 .rate_min = 5512,
1504 .rate_max = 48000,
1505 .channels_min = 2,
1506 .channels_max = 2,
1507 .buffer_bytes_max = (128*1024),
1508 .period_bytes_min = 64,
1509 .period_bytes_max = (128*1024),
1510 .periods_min = 2,
1511 .periods_max = 1024,
1512 .fifo_size = 0,
1513};
1514
1515/* spdif playback on channel A */
1516static const struct snd_pcm_hardware snd_cmipci_playback_spdif =
1517{
1518 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1519 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1520 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1521 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1522 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1523 .rate_min = 44100,
1524 .rate_max = 48000,
1525 .channels_min = 2,
1526 .channels_max = 2,
1527 .buffer_bytes_max = (128*1024),
1528 .period_bytes_min = 64,
1529 .period_bytes_max = (128*1024),
1530 .periods_min = 2,
1531 .periods_max = 1024,
1532 .fifo_size = 0,
1533};
1534
1535/* spdif playback on channel A (32bit, IEC958 subframes) */
1536static const struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1537{
1538 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1539 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1540 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1541 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1542 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1543 .rate_min = 44100,
1544 .rate_max = 48000,
1545 .channels_min = 2,
1546 .channels_max = 2,
1547 .buffer_bytes_max = (128*1024),
1548 .period_bytes_min = 64,
1549 .period_bytes_max = (128*1024),
1550 .periods_min = 2,
1551 .periods_max = 1024,
1552 .fifo_size = 0,
1553};
1554
1555/* spdif capture on channel B */
1556static const struct snd_pcm_hardware snd_cmipci_capture_spdif =
1557{
1558 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1559 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1560 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1561 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1562 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1563 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1564 .rate_min = 44100,
1565 .rate_max = 48000,
1566 .channels_min = 2,
1567 .channels_max = 2,
1568 .buffer_bytes_max = (128*1024),
1569 .period_bytes_min = 64,
1570 .period_bytes_max = (128*1024),
1571 .periods_min = 2,
1572 .periods_max = 1024,
1573 .fifo_size = 0,
1574};
1575
1576static const unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050,
1577 32000, 44100, 48000, 88200, 96000, 128000 };
1578static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1579 .count = ARRAY_SIZE(rate_constraints),
1580 .list = rate_constraints,
1581 .mask = 0,
1582};
1583
1584/*
1585 * check device open/close
1586 */
1587static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1588{
1589 int ch = mode & CM_OPEN_CH_MASK;
1590
1591 /* FIXME: a file should wait until the device becomes free
1592 * when it's opened on blocking mode. however, since the current
1593 * pcm framework doesn't pass file pointer before actually opened,
1594 * we can't know whether blocking mode or not in open callback..
1595 */
1596 mutex_lock(&cm->open_mutex);
1597 if (cm->opened[ch]) {
1598 mutex_unlock(&cm->open_mutex);
1599 return -EBUSY;
1600 }
1601 cm->opened[ch] = mode;
1602 cm->channel[ch].substream = subs;
1603 if (! (mode & CM_OPEN_DAC)) {
1604 /* disable dual DAC mode */
1605 cm->channel[ch].is_dac = 0;
1606 spin_lock_irq(&cm->reg_lock);
1607 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1608 spin_unlock_irq(&cm->reg_lock);
1609 }
1610 mutex_unlock(&cm->open_mutex);
1611 return 0;
1612}
1613
1614static void close_device_check(struct cmipci *cm, int mode)
1615{
1616 int ch = mode & CM_OPEN_CH_MASK;
1617
1618 mutex_lock(&cm->open_mutex);
1619 if (cm->opened[ch] == mode) {
1620 if (cm->channel[ch].substream) {
1621 snd_cmipci_ch_reset(cm, ch);
1622 cm->channel[ch].running = 0;
1623 cm->channel[ch].substream = NULL;
1624 }
1625 cm->opened[ch] = 0;
1626 if (! cm->channel[ch].is_dac) {
1627 /* enable dual DAC mode again */
1628 cm->channel[ch].is_dac = 1;
1629 spin_lock_irq(&cm->reg_lock);
1630 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1631 spin_unlock_irq(&cm->reg_lock);
1632 }
1633 }
1634 mutex_unlock(&cm->open_mutex);
1635}
1636
1637/*
1638 */
1639
1640static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1641{
1642 struct cmipci *cm = snd_pcm_substream_chip(substream);
1643 struct snd_pcm_runtime *runtime = substream->runtime;
1644 int err;
1645
1646 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1647 return err;
1648 runtime->hw = snd_cmipci_playback;
1649 if (cm->chip_version == 68) {
1650 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1651 SNDRV_PCM_RATE_96000;
1652 runtime->hw.rate_max = 96000;
1653 } else if (cm->chip_version == 55) {
1654 err = snd_pcm_hw_constraint_list(runtime, 0,
1655 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1656 if (err < 0)
1657 return err;
1658 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1659 runtime->hw.rate_max = 128000;
1660 }
1661 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1662 cm->dig_pcm_status = cm->dig_status;
1663 return 0;
1664}
1665
1666static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1667{
1668 struct cmipci *cm = snd_pcm_substream_chip(substream);
1669 struct snd_pcm_runtime *runtime = substream->runtime;
1670 int err;
1671
1672 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1673 return err;
1674 runtime->hw = snd_cmipci_capture;
1675 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1676 runtime->hw.rate_min = 41000;
1677 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1678 } else if (cm->chip_version == 55) {
1679 err = snd_pcm_hw_constraint_list(runtime, 0,
1680 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1681 if (err < 0)
1682 return err;
1683 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1684 runtime->hw.rate_max = 128000;
1685 }
1686 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1687 return 0;
1688}
1689
1690static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1691{
1692 struct cmipci *cm = snd_pcm_substream_chip(substream);
1693 struct snd_pcm_runtime *runtime = substream->runtime;
1694 int err;
1695
1696 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1697 return err;
1698 runtime->hw = snd_cmipci_playback2;
1699 mutex_lock(&cm->open_mutex);
1700 if (! cm->opened[CM_CH_PLAY]) {
1701 if (cm->can_multi_ch) {
1702 runtime->hw.channels_max = cm->max_channels;
1703 if (cm->max_channels == 4)
1704 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1705 else if (cm->max_channels == 6)
1706 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1707 else if (cm->max_channels == 8)
1708 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1709 }
1710 }
1711 mutex_unlock(&cm->open_mutex);
1712 if (cm->chip_version == 68) {
1713 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1714 SNDRV_PCM_RATE_96000;
1715 runtime->hw.rate_max = 96000;
1716 } else if (cm->chip_version == 55) {
1717 err = snd_pcm_hw_constraint_list(runtime, 0,
1718 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1719 if (err < 0)
1720 return err;
1721 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1722 runtime->hw.rate_max = 128000;
1723 }
1724 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1725 return 0;
1726}
1727
1728static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1729{
1730 struct cmipci *cm = snd_pcm_substream_chip(substream);
1731 struct snd_pcm_runtime *runtime = substream->runtime;
1732 int err;
1733
1734 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1735 return err;
1736 if (cm->can_ac3_hw) {
1737 runtime->hw = snd_cmipci_playback_spdif;
1738 if (cm->chip_version >= 37) {
1739 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1740 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1741 }
1742 if (cm->can_96k) {
1743 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1744 SNDRV_PCM_RATE_96000;
1745 runtime->hw.rate_max = 96000;
1746 }
1747 } else {
1748 runtime->hw = snd_cmipci_playback_iec958_subframe;
1749 }
1750 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1751 cm->dig_pcm_status = cm->dig_status;
1752 return 0;
1753}
1754
1755static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1756{
1757 struct cmipci *cm = snd_pcm_substream_chip(substream);
1758 struct snd_pcm_runtime *runtime = substream->runtime;
1759 int err;
1760
1761 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1762 return err;
1763 runtime->hw = snd_cmipci_capture_spdif;
1764 if (cm->can_96k && !(cm->chip_version == 68)) {
1765 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1766 SNDRV_PCM_RATE_96000;
1767 runtime->hw.rate_max = 96000;
1768 }
1769 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1770 return 0;
1771}
1772
1773
1774/*
1775 */
1776
1777static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1778{
1779 struct cmipci *cm = snd_pcm_substream_chip(substream);
1780 close_device_check(cm, CM_OPEN_PLAYBACK);
1781 return 0;
1782}
1783
1784static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1785{
1786 struct cmipci *cm = snd_pcm_substream_chip(substream);
1787 close_device_check(cm, CM_OPEN_CAPTURE);
1788 return 0;
1789}
1790
1791static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1792{
1793 struct cmipci *cm = snd_pcm_substream_chip(substream);
1794 close_device_check(cm, CM_OPEN_PLAYBACK2);
1795 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1796 return 0;
1797}
1798
1799static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1800{
1801 struct cmipci *cm = snd_pcm_substream_chip(substream);
1802 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1803 return 0;
1804}
1805
1806static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1807{
1808 struct cmipci *cm = snd_pcm_substream_chip(substream);
1809 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1810 return 0;
1811}
1812
1813
1814/*
1815 */
1816
1817static const struct snd_pcm_ops snd_cmipci_playback_ops = {
1818 .open = snd_cmipci_playback_open,
1819 .close = snd_cmipci_playback_close,
1820 .hw_free = snd_cmipci_playback_hw_free,
1821 .prepare = snd_cmipci_playback_prepare,
1822 .trigger = snd_cmipci_playback_trigger,
1823 .pointer = snd_cmipci_playback_pointer,
1824};
1825
1826static const struct snd_pcm_ops snd_cmipci_capture_ops = {
1827 .open = snd_cmipci_capture_open,
1828 .close = snd_cmipci_capture_close,
1829 .prepare = snd_cmipci_capture_prepare,
1830 .trigger = snd_cmipci_capture_trigger,
1831 .pointer = snd_cmipci_capture_pointer,
1832};
1833
1834static const struct snd_pcm_ops snd_cmipci_playback2_ops = {
1835 .open = snd_cmipci_playback2_open,
1836 .close = snd_cmipci_playback2_close,
1837 .hw_params = snd_cmipci_playback2_hw_params,
1838 .hw_free = snd_cmipci_playback2_hw_free,
1839 .prepare = snd_cmipci_capture_prepare, /* channel B */
1840 .trigger = snd_cmipci_capture_trigger, /* channel B */
1841 .pointer = snd_cmipci_capture_pointer, /* channel B */
1842};
1843
1844static const struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1845 .open = snd_cmipci_playback_spdif_open,
1846 .close = snd_cmipci_playback_spdif_close,
1847 .hw_free = snd_cmipci_playback_hw_free,
1848 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1849 .trigger = snd_cmipci_playback_trigger,
1850 .pointer = snd_cmipci_playback_pointer,
1851};
1852
1853static const struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1854 .open = snd_cmipci_capture_spdif_open,
1855 .close = snd_cmipci_capture_spdif_close,
1856 .hw_free = snd_cmipci_capture_spdif_hw_free,
1857 .prepare = snd_cmipci_capture_spdif_prepare,
1858 .trigger = snd_cmipci_capture_trigger,
1859 .pointer = snd_cmipci_capture_pointer,
1860};
1861
1862
1863/*
1864 */
1865
1866static int snd_cmipci_pcm_new(struct cmipci *cm, int device)
1867{
1868 struct snd_pcm *pcm;
1869 int err;
1870
1871 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1872 if (err < 0)
1873 return err;
1874
1875 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1876 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1877
1878 pcm->private_data = cm;
1879 pcm->info_flags = 0;
1880 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1881 cm->pcm = pcm;
1882
1883 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1884 &cm->pci->dev, 64*1024, 128*1024);
1885
1886 return 0;
1887}
1888
1889static int snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1890{
1891 struct snd_pcm *pcm;
1892 int err;
1893
1894 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1895 if (err < 0)
1896 return err;
1897
1898 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1899
1900 pcm->private_data = cm;
1901 pcm->info_flags = 0;
1902 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1903 cm->pcm2 = pcm;
1904
1905 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1906 &cm->pci->dev, 64*1024, 128*1024);
1907
1908 return 0;
1909}
1910
1911static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1912{
1913 struct snd_pcm *pcm;
1914 int err;
1915
1916 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1917 if (err < 0)
1918 return err;
1919
1920 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1921 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1922
1923 pcm->private_data = cm;
1924 pcm->info_flags = 0;
1925 strcpy(pcm->name, "C-Media PCI IEC958");
1926 cm->pcm_spdif = pcm;
1927
1928 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1929 &cm->pci->dev, 64*1024, 128*1024);
1930
1931 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1932 snd_pcm_alt_chmaps, cm->max_channels, 0,
1933 NULL);
1934 if (err < 0)
1935 return err;
1936
1937 return 0;
1938}
1939
1940/*
1941 * mixer interface:
1942 * - CM8338/8738 has a compatible mixer interface with SB16, but
1943 * lack of some elements like tone control, i/o gain and AGC.
1944 * - Access to native registers:
1945 * - A 3D switch
1946 * - Output mute switches
1947 */
1948
1949static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1950{
1951 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1952 outb(data, s->iobase + CM_REG_SB16_DATA);
1953}
1954
1955static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1956{
1957 unsigned char v;
1958
1959 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1960 v = inb(s->iobase + CM_REG_SB16_DATA);
1961 return v;
1962}
1963
1964/*
1965 * general mixer element
1966 */
1967struct cmipci_sb_reg {
1968 unsigned int left_reg, right_reg;
1969 unsigned int left_shift, right_shift;
1970 unsigned int mask;
1971 unsigned int invert: 1;
1972 unsigned int stereo: 1;
1973};
1974
1975#define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1976 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1977
1978#define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1979{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1980 .info = snd_cmipci_info_volume, \
1981 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1982 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1983}
1984
1985#define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1986#define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1987#define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1988#define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1989
1990static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
1991{
1992 r->left_reg = val & 0xff;
1993 r->right_reg = (val >> 8) & 0xff;
1994 r->left_shift = (val >> 16) & 0x07;
1995 r->right_shift = (val >> 19) & 0x07;
1996 r->invert = (val >> 22) & 1;
1997 r->stereo = (val >> 23) & 1;
1998 r->mask = (val >> 24) & 0xff;
1999}
2000
2001static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
2002 struct snd_ctl_elem_info *uinfo)
2003{
2004 struct cmipci_sb_reg reg;
2005
2006 cmipci_sb_reg_decode(®, kcontrol->private_value);
2007 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2008 uinfo->count = reg.stereo + 1;
2009 uinfo->value.integer.min = 0;
2010 uinfo->value.integer.max = reg.mask;
2011 return 0;
2012}
2013
2014static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
2015 struct snd_ctl_elem_value *ucontrol)
2016{
2017 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2018 struct cmipci_sb_reg reg;
2019 int val;
2020
2021 cmipci_sb_reg_decode(®, kcontrol->private_value);
2022 spin_lock_irq(&cm->reg_lock);
2023 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
2024 if (reg.invert)
2025 val = reg.mask - val;
2026 ucontrol->value.integer.value[0] = val;
2027 if (reg.stereo) {
2028 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
2029 if (reg.invert)
2030 val = reg.mask - val;
2031 ucontrol->value.integer.value[1] = val;
2032 }
2033 spin_unlock_irq(&cm->reg_lock);
2034 return 0;
2035}
2036
2037static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
2038 struct snd_ctl_elem_value *ucontrol)
2039{
2040 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2041 struct cmipci_sb_reg reg;
2042 int change;
2043 int left, right, oleft, oright;
2044
2045 cmipci_sb_reg_decode(®, kcontrol->private_value);
2046 left = ucontrol->value.integer.value[0] & reg.mask;
2047 if (reg.invert)
2048 left = reg.mask - left;
2049 left <<= reg.left_shift;
2050 if (reg.stereo) {
2051 right = ucontrol->value.integer.value[1] & reg.mask;
2052 if (reg.invert)
2053 right = reg.mask - right;
2054 right <<= reg.right_shift;
2055 } else
2056 right = 0;
2057 spin_lock_irq(&cm->reg_lock);
2058 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2059 left |= oleft & ~(reg.mask << reg.left_shift);
2060 change = left != oleft;
2061 if (reg.stereo) {
2062 if (reg.left_reg != reg.right_reg) {
2063 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2064 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2065 } else
2066 oright = left;
2067 right |= oright & ~(reg.mask << reg.right_shift);
2068 change |= right != oright;
2069 snd_cmipci_mixer_write(cm, reg.right_reg, right);
2070 } else
2071 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2072 spin_unlock_irq(&cm->reg_lock);
2073 return change;
2074}
2075
2076/*
2077 * input route (left,right) -> (left,right)
2078 */
2079#define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2080{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2081 .info = snd_cmipci_info_input_sw, \
2082 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2083 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2084}
2085
2086static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
2087 struct snd_ctl_elem_info *uinfo)
2088{
2089 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2090 uinfo->count = 4;
2091 uinfo->value.integer.min = 0;
2092 uinfo->value.integer.max = 1;
2093 return 0;
2094}
2095
2096static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2097 struct snd_ctl_elem_value *ucontrol)
2098{
2099 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2100 struct cmipci_sb_reg reg;
2101 int val1, val2;
2102
2103 cmipci_sb_reg_decode(®, kcontrol->private_value);
2104 spin_lock_irq(&cm->reg_lock);
2105 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2106 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2107 spin_unlock_irq(&cm->reg_lock);
2108 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2109 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2110 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2111 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2112 return 0;
2113}
2114
2115static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2116 struct snd_ctl_elem_value *ucontrol)
2117{
2118 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2119 struct cmipci_sb_reg reg;
2120 int change;
2121 int val1, val2, oval1, oval2;
2122
2123 cmipci_sb_reg_decode(®, kcontrol->private_value);
2124 spin_lock_irq(&cm->reg_lock);
2125 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2126 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2127 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2128 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2129 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2130 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2131 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2132 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2133 change = val1 != oval1 || val2 != oval2;
2134 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2135 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2136 spin_unlock_irq(&cm->reg_lock);
2137 return change;
2138}
2139
2140/*
2141 * native mixer switches/volumes
2142 */
2143
2144#define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2145{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2146 .info = snd_cmipci_info_native_mixer, \
2147 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2148 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2149}
2150
2151#define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2152{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2153 .info = snd_cmipci_info_native_mixer, \
2154 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2155 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2156}
2157
2158#define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2159{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2160 .info = snd_cmipci_info_native_mixer, \
2161 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2162 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2163}
2164
2165#define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2166{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2167 .info = snd_cmipci_info_native_mixer, \
2168 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2169 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2170}
2171
2172static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2173 struct snd_ctl_elem_info *uinfo)
2174{
2175 struct cmipci_sb_reg reg;
2176
2177 cmipci_sb_reg_decode(®, kcontrol->private_value);
2178 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2179 uinfo->count = reg.stereo + 1;
2180 uinfo->value.integer.min = 0;
2181 uinfo->value.integer.max = reg.mask;
2182 return 0;
2183
2184}
2185
2186static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2187 struct snd_ctl_elem_value *ucontrol)
2188{
2189 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2190 struct cmipci_sb_reg reg;
2191 unsigned char oreg, val;
2192
2193 cmipci_sb_reg_decode(®, kcontrol->private_value);
2194 spin_lock_irq(&cm->reg_lock);
2195 oreg = inb(cm->iobase + reg.left_reg);
2196 val = (oreg >> reg.left_shift) & reg.mask;
2197 if (reg.invert)
2198 val = reg.mask - val;
2199 ucontrol->value.integer.value[0] = val;
2200 if (reg.stereo) {
2201 val = (oreg >> reg.right_shift) & reg.mask;
2202 if (reg.invert)
2203 val = reg.mask - val;
2204 ucontrol->value.integer.value[1] = val;
2205 }
2206 spin_unlock_irq(&cm->reg_lock);
2207 return 0;
2208}
2209
2210static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2211 struct snd_ctl_elem_value *ucontrol)
2212{
2213 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2214 struct cmipci_sb_reg reg;
2215 unsigned char oreg, nreg, val;
2216
2217 cmipci_sb_reg_decode(®, kcontrol->private_value);
2218 spin_lock_irq(&cm->reg_lock);
2219 oreg = inb(cm->iobase + reg.left_reg);
2220 val = ucontrol->value.integer.value[0] & reg.mask;
2221 if (reg.invert)
2222 val = reg.mask - val;
2223 nreg = oreg & ~(reg.mask << reg.left_shift);
2224 nreg |= (val << reg.left_shift);
2225 if (reg.stereo) {
2226 val = ucontrol->value.integer.value[1] & reg.mask;
2227 if (reg.invert)
2228 val = reg.mask - val;
2229 nreg &= ~(reg.mask << reg.right_shift);
2230 nreg |= (val << reg.right_shift);
2231 }
2232 outb(nreg, cm->iobase + reg.left_reg);
2233 spin_unlock_irq(&cm->reg_lock);
2234 return (nreg != oreg);
2235}
2236
2237/*
2238 * special case - check mixer sensitivity
2239 */
2240static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2241 struct snd_ctl_elem_value *ucontrol)
2242{
2243 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2244 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2245}
2246
2247static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2248 struct snd_ctl_elem_value *ucontrol)
2249{
2250 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2251 if (cm->mixer_insensitive) {
2252 /* ignored */
2253 return 0;
2254 }
2255 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2256}
2257
2258
2259static const struct snd_kcontrol_new snd_cmipci_mixers[] = {
2260 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2261 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2262 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2263 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2264 { /* switch with sensitivity */
2265 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2266 .name = "PCM Playback Switch",
2267 .info = snd_cmipci_info_native_mixer,
2268 .get = snd_cmipci_get_native_mixer_sensitive,
2269 .put = snd_cmipci_put_native_mixer_sensitive,
2270 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2271 },
2272 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2273 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2274 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2275 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2276 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2277 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2278 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2279 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2280 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2281 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2282 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2283 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2284 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2285 CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2286 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2287 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2288 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2289 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2290 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2291 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2292 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2293 CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2294 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2295};
2296
2297/*
2298 * other switches
2299 */
2300
2301struct cmipci_switch_args {
2302 int reg; /* register index */
2303 unsigned int mask; /* mask bits */
2304 unsigned int mask_on; /* mask bits to turn on */
2305 unsigned int is_byte: 1; /* byte access? */
2306 unsigned int ac3_sensitive: 1; /* access forbidden during
2307 * non-audio operation?
2308 */
2309};
2310
2311#define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
2312
2313static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2314 struct snd_ctl_elem_value *ucontrol,
2315 struct cmipci_switch_args *args)
2316{
2317 unsigned int val;
2318 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2319
2320 spin_lock_irq(&cm->reg_lock);
2321 if (args->ac3_sensitive && cm->mixer_insensitive) {
2322 ucontrol->value.integer.value[0] = 0;
2323 spin_unlock_irq(&cm->reg_lock);
2324 return 0;
2325 }
2326 if (args->is_byte)
2327 val = inb(cm->iobase + args->reg);
2328 else
2329 val = snd_cmipci_read(cm, args->reg);
2330 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2331 spin_unlock_irq(&cm->reg_lock);
2332 return 0;
2333}
2334
2335static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2336 struct snd_ctl_elem_value *ucontrol)
2337{
2338 struct cmipci_switch_args *args;
2339 args = (struct cmipci_switch_args *)kcontrol->private_value;
2340 if (snd_BUG_ON(!args))
2341 return -EINVAL;
2342 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2343}
2344
2345static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2346 struct snd_ctl_elem_value *ucontrol,
2347 struct cmipci_switch_args *args)
2348{
2349 unsigned int val;
2350 int change;
2351 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2352
2353 spin_lock_irq(&cm->reg_lock);
2354 if (args->ac3_sensitive && cm->mixer_insensitive) {
2355 /* ignored */
2356 spin_unlock_irq(&cm->reg_lock);
2357 return 0;
2358 }
2359 if (args->is_byte)
2360 val = inb(cm->iobase + args->reg);
2361 else
2362 val = snd_cmipci_read(cm, args->reg);
2363 change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2364 args->mask_on : (args->mask & ~args->mask_on));
2365 if (change) {
2366 val &= ~args->mask;
2367 if (ucontrol->value.integer.value[0])
2368 val |= args->mask_on;
2369 else
2370 val |= (args->mask & ~args->mask_on);
2371 if (args->is_byte)
2372 outb((unsigned char)val, cm->iobase + args->reg);
2373 else
2374 snd_cmipci_write(cm, args->reg, val);
2375 }
2376 spin_unlock_irq(&cm->reg_lock);
2377 return change;
2378}
2379
2380static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2381 struct snd_ctl_elem_value *ucontrol)
2382{
2383 struct cmipci_switch_args *args;
2384 args = (struct cmipci_switch_args *)kcontrol->private_value;
2385 if (snd_BUG_ON(!args))
2386 return -EINVAL;
2387 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2388}
2389
2390#define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2391static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2392 .reg = xreg, \
2393 .mask = xmask, \
2394 .mask_on = xmask_on, \
2395 .is_byte = xis_byte, \
2396 .ac3_sensitive = xac3, \
2397}
2398
2399#define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2400 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2401
2402#if 0 /* these will be controlled in pcm device */
2403DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2404DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2405#endif
2406DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2407DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2408DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2409DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2410DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2411DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2412DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2413DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2414// DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2415DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2416DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2417/* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2418DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2419DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2420#if CM_CH_PLAY == 1
2421DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2422#else
2423DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2424#endif
2425DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2426// DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2427// DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2428// DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2429DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2430
2431#define DEFINE_SWITCH(sname, stype, sarg) \
2432{ .name = sname, \
2433 .iface = stype, \
2434 .info = snd_cmipci_uswitch_info, \
2435 .get = snd_cmipci_uswitch_get, \
2436 .put = snd_cmipci_uswitch_put, \
2437 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2438}
2439
2440#define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2441#define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2442
2443
2444/*
2445 * callbacks for spdif output switch
2446 * needs toggle two registers..
2447 */
2448static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2449 struct snd_ctl_elem_value *ucontrol)
2450{
2451 int changed;
2452 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2453 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2454 return changed;
2455}
2456
2457static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2458 struct snd_ctl_elem_value *ucontrol)
2459{
2460 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2461 int changed;
2462 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2463 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2464 if (changed) {
2465 if (ucontrol->value.integer.value[0]) {
2466 if (chip->spdif_playback_avail)
2467 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2468 } else {
2469 if (chip->spdif_playback_avail)
2470 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2471 }
2472 }
2473 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2474 return changed;
2475}
2476
2477
2478static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2479 struct snd_ctl_elem_info *uinfo)
2480{
2481 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2482 static const char *const texts[3] = {
2483 "Line-In", "Rear Output", "Bass Output"
2484 };
2485
2486 return snd_ctl_enum_info(uinfo, 1,
2487 cm->chip_version >= 39 ? 3 : 2, texts);
2488}
2489
2490static inline unsigned int get_line_in_mode(struct cmipci *cm)
2491{
2492 unsigned int val;
2493 if (cm->chip_version >= 39) {
2494 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2495 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2496 return 2;
2497 }
2498 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2499 if (val & CM_REAR2LIN)
2500 return 1;
2501 return 0;
2502}
2503
2504static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2505 struct snd_ctl_elem_value *ucontrol)
2506{
2507 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2508
2509 spin_lock_irq(&cm->reg_lock);
2510 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2511 spin_unlock_irq(&cm->reg_lock);
2512 return 0;
2513}
2514
2515static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2516 struct snd_ctl_elem_value *ucontrol)
2517{
2518 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2519 int change;
2520
2521 spin_lock_irq(&cm->reg_lock);
2522 if (ucontrol->value.enumerated.item[0] == 2)
2523 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2524 else
2525 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2526 if (ucontrol->value.enumerated.item[0] == 1)
2527 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2528 else
2529 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2530 spin_unlock_irq(&cm->reg_lock);
2531 return change;
2532}
2533
2534static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2535 struct snd_ctl_elem_info *uinfo)
2536{
2537 static const char *const texts[2] = { "Mic-In", "Center/LFE Output" };
2538
2539 return snd_ctl_enum_info(uinfo, 1, 2, texts);
2540}
2541
2542static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2543 struct snd_ctl_elem_value *ucontrol)
2544{
2545 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2546 /* same bit as spdi_phase */
2547 spin_lock_irq(&cm->reg_lock);
2548 ucontrol->value.enumerated.item[0] =
2549 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2550 spin_unlock_irq(&cm->reg_lock);
2551 return 0;
2552}
2553
2554static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2555 struct snd_ctl_elem_value *ucontrol)
2556{
2557 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2558 int change;
2559
2560 spin_lock_irq(&cm->reg_lock);
2561 if (ucontrol->value.enumerated.item[0])
2562 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2563 else
2564 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2565 spin_unlock_irq(&cm->reg_lock);
2566 return change;
2567}
2568
2569/* both for CM8338/8738 */
2570static const struct snd_kcontrol_new snd_cmipci_mixer_switches[] = {
2571 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2572 {
2573 .name = "Line-In Mode",
2574 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2575 .info = snd_cmipci_line_in_mode_info,
2576 .get = snd_cmipci_line_in_mode_get,
2577 .put = snd_cmipci_line_in_mode_put,
2578 },
2579};
2580
2581/* for non-multichannel chips */
2582static const struct snd_kcontrol_new snd_cmipci_nomulti_switch =
2583DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2584
2585/* only for CM8738 */
2586static const struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] = {
2587#if 0 /* controlled in pcm device */
2588 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2589 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2590 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2591#endif
2592 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2593 { .name = "IEC958 Output Switch",
2594 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2595 .info = snd_cmipci_uswitch_info,
2596 .get = snd_cmipci_spdout_enable_get,
2597 .put = snd_cmipci_spdout_enable_put,
2598 },
2599 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2600 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2601 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2602// DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2603 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2604 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2605};
2606
2607/* only for model 033/037 */
2608static const struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] = {
2609 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2610 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2611 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2612};
2613
2614/* only for model 039 or later */
2615static const struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] = {
2616 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2617 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2618 {
2619 .name = "Mic-In Mode",
2620 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2621 .info = snd_cmipci_mic_in_mode_info,
2622 .get = snd_cmipci_mic_in_mode_get,
2623 .put = snd_cmipci_mic_in_mode_put,
2624 }
2625};
2626
2627/* card control switches */
2628static const struct snd_kcontrol_new snd_cmipci_modem_switch =
2629DEFINE_CARD_SWITCH("Modem", modem);
2630
2631
2632static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2633{
2634 struct snd_card *card;
2635 const struct snd_kcontrol_new *sw;
2636 struct snd_kcontrol *kctl;
2637 unsigned int idx;
2638 int err;
2639
2640 if (snd_BUG_ON(!cm || !cm->card))
2641 return -EINVAL;
2642
2643 card = cm->card;
2644
2645 strcpy(card->mixername, "CMedia PCI");
2646
2647 spin_lock_irq(&cm->reg_lock);
2648 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2649 spin_unlock_irq(&cm->reg_lock);
2650
2651 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2652 if (cm->chip_version == 68) { // 8768 has no PCM volume
2653 if (!strcmp(snd_cmipci_mixers[idx].name,
2654 "PCM Playback Volume"))
2655 continue;
2656 }
2657 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2658 return err;
2659 }
2660
2661 /* mixer switches */
2662 sw = snd_cmipci_mixer_switches;
2663 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2664 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2665 if (err < 0)
2666 return err;
2667 }
2668 if (! cm->can_multi_ch) {
2669 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2670 if (err < 0)
2671 return err;
2672 }
2673 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2674 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2675 sw = snd_cmipci_8738_mixer_switches;
2676 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2677 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2678 if (err < 0)
2679 return err;
2680 }
2681 if (cm->can_ac3_hw) {
2682 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2683 return err;
2684 kctl->id.device = pcm_spdif_device;
2685 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2686 return err;
2687 kctl->id.device = pcm_spdif_device;
2688 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2689 return err;
2690 kctl->id.device = pcm_spdif_device;
2691 }
2692 if (cm->chip_version <= 37) {
2693 sw = snd_cmipci_old_mixer_switches;
2694 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2695 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2696 if (err < 0)
2697 return err;
2698 }
2699 }
2700 }
2701 if (cm->chip_version >= 39) {
2702 sw = snd_cmipci_extra_mixer_switches;
2703 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2704 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2705 if (err < 0)
2706 return err;
2707 }
2708 }
2709
2710 /* card switches */
2711 /*
2712 * newer chips don't have the register bits to force modem link
2713 * detection; the bit that was FLINKON now mutes CH1
2714 */
2715 if (cm->chip_version < 39) {
2716 err = snd_ctl_add(cm->card,
2717 snd_ctl_new1(&snd_cmipci_modem_switch, cm));
2718 if (err < 0)
2719 return err;
2720 }
2721
2722 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2723 struct snd_ctl_elem_id elem_id;
2724 struct snd_kcontrol *ctl;
2725 memset(&elem_id, 0, sizeof(elem_id));
2726 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2727 strcpy(elem_id.name, cm_saved_mixer[idx].name);
2728 ctl = snd_ctl_find_id(cm->card, &elem_id);
2729 if (ctl)
2730 cm->mixer_res_ctl[idx] = ctl;
2731 }
2732
2733 return 0;
2734}
2735
2736
2737/*
2738 * proc interface
2739 */
2740
2741static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2742 struct snd_info_buffer *buffer)
2743{
2744 struct cmipci *cm = entry->private_data;
2745 int i, v;
2746
2747 snd_iprintf(buffer, "%s\n", cm->card->longname);
2748 for (i = 0; i < 0x94; i++) {
2749 if (i == 0x28)
2750 i = 0x90;
2751 v = inb(cm->iobase + i);
2752 if (i % 4 == 0)
2753 snd_iprintf(buffer, "\n%02x:", i);
2754 snd_iprintf(buffer, " %02x", v);
2755 }
2756 snd_iprintf(buffer, "\n");
2757}
2758
2759static void snd_cmipci_proc_init(struct cmipci *cm)
2760{
2761 snd_card_ro_proc_new(cm->card, "cmipci", cm, snd_cmipci_proc_read);
2762}
2763
2764static const struct pci_device_id snd_cmipci_ids[] = {
2765 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0},
2766 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0},
2767 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2768 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0},
2769 {PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2770 {0,},
2771};
2772
2773
2774/*
2775 * check chip version and capabilities
2776 * driver name is modified according to the chip model
2777 */
2778static void query_chip(struct cmipci *cm)
2779{
2780 unsigned int detect;
2781
2782 /* check reg 0Ch, bit 24-31 */
2783 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2784 if (! detect) {
2785 /* check reg 08h, bit 24-28 */
2786 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2787 switch (detect) {
2788 case 0:
2789 cm->chip_version = 33;
2790 if (cm->do_soft_ac3)
2791 cm->can_ac3_sw = 1;
2792 else
2793 cm->can_ac3_hw = 1;
2794 break;
2795 case CM_CHIP_037:
2796 cm->chip_version = 37;
2797 cm->can_ac3_hw = 1;
2798 break;
2799 default:
2800 cm->chip_version = 39;
2801 cm->can_ac3_hw = 1;
2802 break;
2803 }
2804 cm->max_channels = 2;
2805 } else {
2806 if (detect & CM_CHIP_039) {
2807 cm->chip_version = 39;
2808 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2809 cm->max_channels = 6;
2810 else
2811 cm->max_channels = 4;
2812 } else if (detect & CM_CHIP_8768) {
2813 cm->chip_version = 68;
2814 cm->max_channels = 8;
2815 cm->can_96k = 1;
2816 } else {
2817 cm->chip_version = 55;
2818 cm->max_channels = 6;
2819 cm->can_96k = 1;
2820 }
2821 cm->can_ac3_hw = 1;
2822 cm->can_multi_ch = 1;
2823 }
2824}
2825
2826#ifdef SUPPORT_JOYSTICK
2827static int snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2828{
2829 static const int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2830 struct gameport *gp;
2831 struct resource *r = NULL;
2832 int i, io_port = 0;
2833
2834 if (joystick_port[dev] == 0)
2835 return -ENODEV;
2836
2837 if (joystick_port[dev] == 1) { /* auto-detect */
2838 for (i = 0; ports[i]; i++) {
2839 io_port = ports[i];
2840 r = request_region(io_port, 1, "CMIPCI gameport");
2841 if (r)
2842 break;
2843 }
2844 } else {
2845 io_port = joystick_port[dev];
2846 r = request_region(io_port, 1, "CMIPCI gameport");
2847 }
2848
2849 if (!r) {
2850 dev_warn(cm->card->dev, "cannot reserve joystick ports\n");
2851 return -EBUSY;
2852 }
2853
2854 cm->gameport = gp = gameport_allocate_port();
2855 if (!gp) {
2856 dev_err(cm->card->dev, "cannot allocate memory for gameport\n");
2857 release_and_free_resource(r);
2858 return -ENOMEM;
2859 }
2860 gameport_set_name(gp, "C-Media Gameport");
2861 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2862 gameport_set_dev_parent(gp, &cm->pci->dev);
2863 gp->io = io_port;
2864 gameport_set_port_data(gp, r);
2865
2866 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2867
2868 gameport_register_port(cm->gameport);
2869
2870 return 0;
2871}
2872
2873static void snd_cmipci_free_gameport(struct cmipci *cm)
2874{
2875 if (cm->gameport) {
2876 struct resource *r = gameport_get_port_data(cm->gameport);
2877
2878 gameport_unregister_port(cm->gameport);
2879 cm->gameport = NULL;
2880
2881 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2882 release_and_free_resource(r);
2883 }
2884}
2885#else
2886static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2887static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2888#endif
2889
2890static int snd_cmipci_free(struct cmipci *cm)
2891{
2892 if (cm->irq >= 0) {
2893 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2894 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2895 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2896 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2897 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2898 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2899 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2900
2901 /* reset mixer */
2902 snd_cmipci_mixer_write(cm, 0, 0);
2903
2904 free_irq(cm->irq, cm);
2905 }
2906
2907 snd_cmipci_free_gameport(cm);
2908 pci_release_regions(cm->pci);
2909 pci_disable_device(cm->pci);
2910 kfree(cm);
2911 return 0;
2912}
2913
2914static int snd_cmipci_dev_free(struct snd_device *device)
2915{
2916 struct cmipci *cm = device->device_data;
2917 return snd_cmipci_free(cm);
2918}
2919
2920static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2921{
2922 long iosynth;
2923 unsigned int val;
2924 struct snd_opl3 *opl3;
2925 int err;
2926
2927 if (!fm_port)
2928 goto disable_fm;
2929
2930 if (cm->chip_version >= 39) {
2931 /* first try FM regs in PCI port range */
2932 iosynth = cm->iobase + CM_REG_FM_PCI;
2933 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2934 OPL3_HW_OPL3, 1, &opl3);
2935 } else {
2936 err = -EIO;
2937 }
2938 if (err < 0) {
2939 /* then try legacy ports */
2940 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2941 iosynth = fm_port;
2942 switch (iosynth) {
2943 case 0x3E8: val |= CM_FMSEL_3E8; break;
2944 case 0x3E0: val |= CM_FMSEL_3E0; break;
2945 case 0x3C8: val |= CM_FMSEL_3C8; break;
2946 case 0x388: val |= CM_FMSEL_388; break;
2947 default:
2948 goto disable_fm;
2949 }
2950 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2951 /* enable FM */
2952 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2953
2954 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2955 OPL3_HW_OPL3, 0, &opl3) < 0) {
2956 dev_err(cm->card->dev,
2957 "no OPL device at %#lx, skipping...\n",
2958 iosynth);
2959 goto disable_fm;
2960 }
2961 }
2962 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
2963 dev_err(cm->card->dev, "cannot create OPL3 hwdep\n");
2964 return err;
2965 }
2966 return 0;
2967
2968 disable_fm:
2969 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
2970 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2971 return 0;
2972}
2973
2974static int snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2975 int dev, struct cmipci **rcmipci)
2976{
2977 struct cmipci *cm;
2978 int err;
2979 static const struct snd_device_ops ops = {
2980 .dev_free = snd_cmipci_dev_free,
2981 };
2982 unsigned int val;
2983 long iomidi = 0;
2984 int integrated_midi = 0;
2985 char modelstr[16];
2986 int pcm_index, pcm_spdif_index;
2987 static const struct pci_device_id intel_82437vx[] = {
2988 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
2989 { },
2990 };
2991
2992 *rcmipci = NULL;
2993
2994 if ((err = pci_enable_device(pci)) < 0)
2995 return err;
2996
2997 cm = kzalloc(sizeof(*cm), GFP_KERNEL);
2998 if (cm == NULL) {
2999 pci_disable_device(pci);
3000 return -ENOMEM;
3001 }
3002
3003 spin_lock_init(&cm->reg_lock);
3004 mutex_init(&cm->open_mutex);
3005 cm->device = pci->device;
3006 cm->card = card;
3007 cm->pci = pci;
3008 cm->irq = -1;
3009 cm->channel[0].ch = 0;
3010 cm->channel[1].ch = 1;
3011 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
3012
3013 if ((err = pci_request_regions(pci, card->driver)) < 0) {
3014 kfree(cm);
3015 pci_disable_device(pci);
3016 return err;
3017 }
3018 cm->iobase = pci_resource_start(pci, 0);
3019
3020 if (request_irq(pci->irq, snd_cmipci_interrupt,
3021 IRQF_SHARED, KBUILD_MODNAME, cm)) {
3022 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3023 snd_cmipci_free(cm);
3024 return -EBUSY;
3025 }
3026 cm->irq = pci->irq;
3027 card->sync_irq = cm->irq;
3028
3029 pci_set_master(cm->pci);
3030
3031 /*
3032 * check chip version, max channels and capabilities
3033 */
3034
3035 cm->chip_version = 0;
3036 cm->max_channels = 2;
3037 cm->do_soft_ac3 = soft_ac3[dev];
3038
3039 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
3040 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
3041 query_chip(cm);
3042 /* added -MCx suffix for chip supporting multi-channels */
3043 if (cm->can_multi_ch)
3044 sprintf(cm->card->driver + strlen(cm->card->driver),
3045 "-MC%d", cm->max_channels);
3046 else if (cm->can_ac3_sw)
3047 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3048
3049 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3050 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3051
3052#if CM_CH_PLAY == 1
3053 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
3054#else
3055 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
3056#endif
3057
3058 /* initialize codec registers */
3059 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3060 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3061 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
3062 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3063 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3064 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
3065 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3066
3067 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3068 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3069#if CM_CH_PLAY == 1
3070 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3071#else
3072 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3073#endif
3074 if (cm->chip_version) {
3075 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3076 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3077 }
3078 /* Set Bus Master Request */
3079 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3080
3081 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3082 switch (pci->device) {
3083 case PCI_DEVICE_ID_CMEDIA_CM8738:
3084 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3085 if (!pci_dev_present(intel_82437vx))
3086 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3087 break;
3088 default:
3089 break;
3090 }
3091
3092 if (cm->chip_version < 68) {
3093 val = pci->device < 0x110 ? 8338 : 8738;
3094 } else {
3095 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3096 case 0:
3097 val = 8769;
3098 break;
3099 case 2:
3100 val = 8762;
3101 break;
3102 default:
3103 switch ((pci->subsystem_vendor << 16) |
3104 pci->subsystem_device) {
3105 case 0x13f69761:
3106 case 0x584d3741:
3107 case 0x584d3751:
3108 case 0x584d3761:
3109 case 0x584d3771:
3110 case 0x72848384:
3111 val = 8770;
3112 break;
3113 default:
3114 val = 8768;
3115 break;
3116 }
3117 }
3118 }
3119 sprintf(card->shortname, "C-Media CMI%d", val);
3120 if (cm->chip_version < 68)
3121 sprintf(modelstr, " (model %d)", cm->chip_version);
3122 else
3123 modelstr[0] = '\0';
3124 sprintf(card->longname, "%s%s at %#lx, irq %i",
3125 card->shortname, modelstr, cm->iobase, cm->irq);
3126
3127 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
3128 snd_cmipci_free(cm);
3129 return err;
3130 }
3131
3132 if (cm->chip_version >= 39) {
3133 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3134 if (val != 0x00 && val != 0xff) {
3135 if (mpu_port[dev])
3136 iomidi = cm->iobase + CM_REG_MPU_PCI;
3137 integrated_midi = 1;
3138 }
3139 }
3140 if (!integrated_midi) {
3141 val = 0;
3142 iomidi = mpu_port[dev];
3143 switch (iomidi) {
3144 case 0x320: val = CM_VMPU_320; break;
3145 case 0x310: val = CM_VMPU_310; break;
3146 case 0x300: val = CM_VMPU_300; break;
3147 case 0x330: val = CM_VMPU_330; break;
3148 default:
3149 iomidi = 0; break;
3150 }
3151 if (iomidi > 0) {
3152 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3153 /* enable UART */
3154 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3155 if (inb(iomidi + 1) == 0xff) {
3156 dev_err(cm->card->dev,
3157 "cannot enable MPU-401 port at %#lx\n",
3158 iomidi);
3159 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3160 CM_UART_EN);
3161 iomidi = 0;
3162 }
3163 }
3164 }
3165
3166 if (cm->chip_version < 68) {
3167 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3168 if (err < 0)
3169 return err;
3170 }
3171
3172 /* reset mixer */
3173 snd_cmipci_mixer_write(cm, 0, 0);
3174
3175 snd_cmipci_proc_init(cm);
3176
3177 /* create pcm devices */
3178 pcm_index = pcm_spdif_index = 0;
3179 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
3180 return err;
3181 pcm_index++;
3182 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
3183 return err;
3184 pcm_index++;
3185 if (cm->can_ac3_hw || cm->can_ac3_sw) {
3186 pcm_spdif_index = pcm_index;
3187 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
3188 return err;
3189 }
3190
3191 /* create mixer interface & switches */
3192 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
3193 return err;
3194
3195 if (iomidi > 0) {
3196 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3197 iomidi,
3198 (integrated_midi ?
3199 MPU401_INFO_INTEGRATED : 0) |
3200 MPU401_INFO_IRQ_HOOK,
3201 -1, &cm->rmidi)) < 0) {
3202 dev_err(cm->card->dev,
3203 "no UART401 device at 0x%lx\n", iomidi);
3204 }
3205 }
3206
3207#ifdef USE_VAR48KRATE
3208 for (val = 0; val < ARRAY_SIZE(rates); val++)
3209 snd_cmipci_set_pll(cm, rates[val], val);
3210
3211 /*
3212 * (Re-)Enable external switch spdo_48k
3213 */
3214 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3215#endif /* USE_VAR48KRATE */
3216
3217 if (snd_cmipci_create_gameport(cm, dev) < 0)
3218 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3219
3220 *rcmipci = cm;
3221 return 0;
3222}
3223
3224/*
3225 */
3226
3227MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3228
3229static int snd_cmipci_probe(struct pci_dev *pci,
3230 const struct pci_device_id *pci_id)
3231{
3232 static int dev;
3233 struct snd_card *card;
3234 struct cmipci *cm;
3235 int err;
3236
3237 if (dev >= SNDRV_CARDS)
3238 return -ENODEV;
3239 if (! enable[dev]) {
3240 dev++;
3241 return -ENOENT;
3242 }
3243
3244 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
3245 0, &card);
3246 if (err < 0)
3247 return err;
3248
3249 switch (pci->device) {
3250 case PCI_DEVICE_ID_CMEDIA_CM8738:
3251 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3252 strcpy(card->driver, "CMI8738");
3253 break;
3254 case PCI_DEVICE_ID_CMEDIA_CM8338A:
3255 case PCI_DEVICE_ID_CMEDIA_CM8338B:
3256 strcpy(card->driver, "CMI8338");
3257 break;
3258 default:
3259 strcpy(card->driver, "CMIPCI");
3260 break;
3261 }
3262
3263 err = snd_cmipci_create(card, pci, dev, &cm);
3264 if (err < 0)
3265 goto free_card;
3266
3267 card->private_data = cm;
3268
3269 err = snd_card_register(card);
3270 if (err < 0)
3271 goto free_card;
3272
3273 pci_set_drvdata(pci, card);
3274 dev++;
3275 return 0;
3276
3277free_card:
3278 snd_card_free(card);
3279 return err;
3280}
3281
3282static void snd_cmipci_remove(struct pci_dev *pci)
3283{
3284 snd_card_free(pci_get_drvdata(pci));
3285}
3286
3287
3288#ifdef CONFIG_PM_SLEEP
3289/*
3290 * power management
3291 */
3292static const unsigned char saved_regs[] = {
3293 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3294 CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL,
3295 CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3296 CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3297 CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3298};
3299
3300static const unsigned char saved_mixers[] = {
3301 SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3302 SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3303 SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3304 SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3305 SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3306 SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3307 CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3308 SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3309};
3310
3311static int snd_cmipci_suspend(struct device *dev)
3312{
3313 struct snd_card *card = dev_get_drvdata(dev);
3314 struct cmipci *cm = card->private_data;
3315 int i;
3316
3317 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3318
3319 /* save registers */
3320 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3321 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3322 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3323 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3324
3325 /* disable ints */
3326 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3327 return 0;
3328}
3329
3330static int snd_cmipci_resume(struct device *dev)
3331{
3332 struct snd_card *card = dev_get_drvdata(dev);
3333 struct cmipci *cm = card->private_data;
3334 int i;
3335
3336 /* reset / initialize to a sane state */
3337 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3338 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3339 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3340 snd_cmipci_mixer_write(cm, 0, 0);
3341
3342 /* restore registers */
3343 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3344 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3345 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3346 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3347
3348 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3349 return 0;
3350}
3351
3352static SIMPLE_DEV_PM_OPS(snd_cmipci_pm, snd_cmipci_suspend, snd_cmipci_resume);
3353#define SND_CMIPCI_PM_OPS &snd_cmipci_pm
3354#else
3355#define SND_CMIPCI_PM_OPS NULL
3356#endif /* CONFIG_PM_SLEEP */
3357
3358static struct pci_driver cmipci_driver = {
3359 .name = KBUILD_MODNAME,
3360 .id_table = snd_cmipci_ids,
3361 .probe = snd_cmipci_probe,
3362 .remove = snd_cmipci_remove,
3363 .driver = {
3364 .pm = SND_CMIPCI_PM_OPS,
3365 },
3366};
3367
3368module_pci_driver(cmipci_driver);
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
4 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
5 */
6
7/* Does not work. Warning may block system in capture mode */
8/* #define USE_VAR48KRATE */
9
10#include <linux/io.h>
11#include <linux/delay.h>
12#include <linux/interrupt.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15#include <linux/slab.h>
16#include <linux/gameport.h>
17#include <linux/module.h>
18#include <linux/mutex.h>
19#include <sound/core.h>
20#include <sound/info.h>
21#include <sound/control.h>
22#include <sound/pcm.h>
23#include <sound/rawmidi.h>
24#include <sound/mpu401.h>
25#include <sound/opl3.h>
26#include <sound/sb.h>
27#include <sound/asoundef.h>
28#include <sound/initval.h>
29
30MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
31MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
32MODULE_LICENSE("GPL");
33
34#if IS_REACHABLE(CONFIG_GAMEPORT)
35#define SUPPORT_JOYSTICK 1
36#endif
37
38static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
39static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
40static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
41static long mpu_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 1};
42static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
43static bool soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
44#ifdef SUPPORT_JOYSTICK
45static int joystick_port[SNDRV_CARDS];
46#endif
47
48module_param_array(index, int, NULL, 0444);
49MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
50module_param_array(id, charp, NULL, 0444);
51MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
52module_param_array(enable, bool, NULL, 0444);
53MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
54module_param_hw_array(mpu_port, long, ioport, NULL, 0444);
55MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
56module_param_hw_array(fm_port, long, ioport, NULL, 0444);
57MODULE_PARM_DESC(fm_port, "FM port.");
58module_param_array(soft_ac3, bool, NULL, 0444);
59MODULE_PARM_DESC(soft_ac3, "Software-conversion of raw SPDIF packets (model 033 only).");
60#ifdef SUPPORT_JOYSTICK
61module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
62MODULE_PARM_DESC(joystick_port, "Joystick port address.");
63#endif
64
65/*
66 * CM8x38 registers definition
67 */
68
69#define CM_REG_FUNCTRL0 0x00
70#define CM_RST_CH1 0x00080000
71#define CM_RST_CH0 0x00040000
72#define CM_CHEN1 0x00020000 /* ch1: enable */
73#define CM_CHEN0 0x00010000 /* ch0: enable */
74#define CM_PAUSE1 0x00000008 /* ch1: pause */
75#define CM_PAUSE0 0x00000004 /* ch0: pause */
76#define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
77#define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
78
79#define CM_REG_FUNCTRL1 0x04
80#define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
81#define CM_DSFC_SHIFT 13
82#define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
83#define CM_ASFC_SHIFT 10
84#define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
85#define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
86#define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
87#define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
88#define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
89#define CM_BREQ 0x00000010 /* bus master enabled */
90#define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
91#define CM_UART_EN 0x00000004 /* legacy UART */
92#define CM_JYSTK_EN 0x00000002 /* legacy joystick */
93#define CM_ZVPORT 0x00000001 /* ZVPORT */
94
95#define CM_REG_CHFORMAT 0x08
96
97#define CM_CHB3D5C 0x80000000 /* 5,6 channels */
98#define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
99#define CM_CHB3D 0x20000000 /* 4 channels */
100
101#define CM_CHIP_MASK1 0x1f000000
102#define CM_CHIP_037 0x01000000
103#define CM_SETLAT48 0x00800000 /* set latency timer 48h */
104#define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
105#define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
106#define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
107#define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
108#define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
109/* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
110
111#define CM_ADCBITLEN_MASK 0x0000C000
112#define CM_ADCBITLEN_16 0x00000000
113#define CM_ADCBITLEN_15 0x00004000
114#define CM_ADCBITLEN_14 0x00008000
115#define CM_ADCBITLEN_13 0x0000C000
116
117#define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
118#define CM_ADCDACLEN_060 0x00000000
119#define CM_ADCDACLEN_066 0x00001000
120#define CM_ADCDACLEN_130 0x00002000
121#define CM_ADCDACLEN_280 0x00003000
122
123#define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
124#define CM_ADCDLEN_ORIGINAL 0x00000000
125#define CM_ADCDLEN_EXTRA 0x00001000
126#define CM_ADCDLEN_24K 0x00002000
127#define CM_ADCDLEN_WEIGHT 0x00003000
128
129#define CM_CH1_SRATE_176K 0x00000800
130#define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
131#define CM_CH1_SRATE_88K 0x00000400
132#define CM_CH0_SRATE_176K 0x00000200
133#define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
134#define CM_CH0_SRATE_88K 0x00000100
135#define CM_CH0_SRATE_128K 0x00000300
136#define CM_CH0_SRATE_MASK 0x00000300
137
138#define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
139#define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
140#define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
141#define CM_SPDLOCKED 0x00000010
142
143#define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
144#define CM_CH1FMT_SHIFT 2
145#define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
146#define CM_CH0FMT_SHIFT 0
147
148#define CM_REG_INT_HLDCLR 0x0C
149#define CM_CHIP_MASK2 0xff000000
150#define CM_CHIP_8768 0x20000000
151#define CM_CHIP_055 0x08000000
152#define CM_CHIP_039 0x04000000
153#define CM_CHIP_039_6CH 0x01000000
154#define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
155#define CM_TDMA_INT_EN 0x00040000
156#define CM_CH1_INT_EN 0x00020000
157#define CM_CH0_INT_EN 0x00010000
158
159#define CM_REG_INT_STATUS 0x10
160#define CM_INTR 0x80000000
161#define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
162#define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
163#define CM_UARTINT 0x00010000
164#define CM_LTDMAINT 0x00008000
165#define CM_HTDMAINT 0x00004000
166#define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
167#define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
168#define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
169#define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
170#define CM_CH1BUSY 0x00000008
171#define CM_CH0BUSY 0x00000004
172#define CM_CHINT1 0x00000002
173#define CM_CHINT0 0x00000001
174
175#define CM_REG_LEGACY_CTRL 0x14
176#define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
177#define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
178#define CM_VMPU_330 0x00000000
179#define CM_VMPU_320 0x20000000
180#define CM_VMPU_310 0x40000000
181#define CM_VMPU_300 0x60000000
182#define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
183#define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
184#define CM_VSBSEL_220 0x00000000
185#define CM_VSBSEL_240 0x04000000
186#define CM_VSBSEL_260 0x08000000
187#define CM_VSBSEL_280 0x0C000000
188#define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
189#define CM_FMSEL_388 0x00000000
190#define CM_FMSEL_3C8 0x01000000
191#define CM_FMSEL_3E0 0x02000000
192#define CM_FMSEL_3E8 0x03000000
193#define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
194#define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
195#define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
196#define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
197#define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
198#define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
199#define CM_C_EECS 0x00040000
200#define CM_C_EEDI46 0x00020000
201#define CM_C_EECK46 0x00010000
202#define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
203#define CM_CENTR2LIN 0x00004000 /* line-in as center out */
204#define CM_BASE2LIN 0x00002000 /* line-in as bass out */
205#define CM_EXBASEN 0x00001000 /* external bass input enable */
206
207#define CM_REG_MISC_CTRL 0x18
208#define CM_PWD 0x80000000 /* power down */
209#define CM_RESET 0x40000000
210#define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
211#define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
212#define CM_TXVX 0x08000000 /* model 037? */
213#define CM_N4SPK3D 0x04000000 /* copy front to rear */
214#define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
215#define CM_SPDIF48K 0x01000000 /* write */
216#define CM_SPATUS48K 0x01000000 /* read */
217#define CM_ENDBDAC 0x00800000 /* enable double dac */
218#define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
219#define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
220#define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
221#define CM_FM_EN 0x00080000 /* enable legacy FM */
222#define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
223#define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
224#define CM_VIDWPDSB 0x00010000 /* model 037? */
225#define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
226#define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
227#define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
228#define CM_VIDWPPRT 0x00002000 /* model 037? */
229#define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
230#define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
231#define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
232#define CM_ENCENTER 0x00000080
233#define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */
234#define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
235#define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */
236#define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
237#define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
238#define CM_UPDDMA_2048 0x00000000
239#define CM_UPDDMA_1024 0x00000004
240#define CM_UPDDMA_512 0x00000008
241#define CM_UPDDMA_256 0x0000000C
242#define CM_TWAIT_MASK 0x00000003 /* model 037 */
243#define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
244#define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
245
246#define CM_REG_TDMA_POSITION 0x1C
247#define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
248#define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
249
250 /* byte */
251#define CM_REG_MIXER0 0x20
252#define CM_REG_SBVR 0x20 /* write: sb16 version */
253#define CM_REG_DEV 0x20 /* read: hardware device version */
254
255#define CM_REG_MIXER21 0x21
256#define CM_UNKNOWN_21_MASK 0x78 /* ? */
257#define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
258#define CM_PROINV 0x02 /* SBPro left/right channel switching */
259#define CM_X_SB16 0x01 /* SB16 compatible */
260
261#define CM_REG_SB16_DATA 0x22
262#define CM_REG_SB16_ADDR 0x23
263
264#define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
265#define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
266#define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
267#define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
268
269#define CM_REG_MIXER1 0x24
270#define CM_FMMUTE 0x80 /* mute FM */
271#define CM_FMMUTE_SHIFT 7
272#define CM_WSMUTE 0x40 /* mute PCM */
273#define CM_WSMUTE_SHIFT 6
274#define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
275#define CM_REAR2LIN_SHIFT 5
276#define CM_REAR2FRONT 0x10 /* exchange rear/front */
277#define CM_REAR2FRONT_SHIFT 4
278#define CM_WAVEINL 0x08 /* digital wave rec. left chan */
279#define CM_WAVEINL_SHIFT 3
280#define CM_WAVEINR 0x04 /* digical wave rec. right */
281#define CM_WAVEINR_SHIFT 2
282#define CM_X3DEN 0x02 /* 3D surround enable */
283#define CM_X3DEN_SHIFT 1
284#define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
285#define CM_CDPLAY_SHIFT 0
286
287#define CM_REG_MIXER2 0x25
288#define CM_RAUXREN 0x80 /* AUX right capture */
289#define CM_RAUXREN_SHIFT 7
290#define CM_RAUXLEN 0x40 /* AUX left capture */
291#define CM_RAUXLEN_SHIFT 6
292#define CM_VAUXRM 0x20 /* AUX right mute */
293#define CM_VAUXRM_SHIFT 5
294#define CM_VAUXLM 0x10 /* AUX left mute */
295#define CM_VAUXLM_SHIFT 4
296#define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
297#define CM_VADMIC_SHIFT 1
298#define CM_MICGAINZ 0x01 /* mic boost */
299#define CM_MICGAINZ_SHIFT 0
300
301#define CM_REG_AUX_VOL 0x26
302#define CM_VAUXL_MASK 0xf0
303#define CM_VAUXR_MASK 0x0f
304
305#define CM_REG_MISC 0x27
306#define CM_UNKNOWN_27_MASK 0xd8 /* ? */
307#define CM_XGPO1 0x20
308// #define CM_XGPBIO 0x04
309#define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
310#define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
311#define CM_SPDVALID 0x02 /* spdif input valid check */
312#define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
313
314#define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
315/*
316 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
317 * or identical with AC97 codec?
318 */
319#define CM_REG_EXTERN_CODEC CM_REG_AC97
320
321/*
322 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
323 */
324#define CM_REG_MPU_PCI 0x40
325
326/*
327 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
328 */
329#define CM_REG_FM_PCI 0x50
330
331/*
332 * access from SB-mixer port
333 */
334#define CM_REG_EXTENT_IND 0xf0
335#define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
336#define CM_VPHONE_SHIFT 5
337#define CM_VPHOM 0x10 /* Phone mute control */
338#define CM_VSPKM 0x08 /* Speaker mute control, default high */
339#define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
340#define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
341#define CM_VADMIC3 0x01 /* Mic record boost */
342
343/*
344 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
345 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
346 * unit (readonly?).
347 */
348#define CM_REG_PLL 0xf8
349
350/*
351 * extended registers
352 */
353#define CM_REG_CH0_FRAME1 0x80 /* write: base address */
354#define CM_REG_CH0_FRAME2 0x84 /* read: current address */
355#define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
356#define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
357
358#define CM_REG_EXT_MISC 0x90
359#define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
360#define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
361#define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
362#define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
363#define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
364#define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
365#define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
366#define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
367
368/*
369 * size of i/o region
370 */
371#define CM_EXTENT_CODEC 0x100
372#define CM_EXTENT_MIDI 0x2
373#define CM_EXTENT_SYNTH 0x4
374
375
376/*
377 * channels for playback / capture
378 */
379#define CM_CH_PLAY 0
380#define CM_CH_CAPT 1
381
382/*
383 * flags to check device open/close
384 */
385#define CM_OPEN_NONE 0
386#define CM_OPEN_CH_MASK 0x01
387#define CM_OPEN_DAC 0x10
388#define CM_OPEN_ADC 0x20
389#define CM_OPEN_SPDIF 0x40
390#define CM_OPEN_MCHAN 0x80
391#define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
392#define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
393#define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
394#define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
395#define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
396#define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
397
398
399#if CM_CH_PLAY == 1
400#define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
401#define CM_PLAYBACK_SPDF CM_SPDF_1
402#define CM_CAPTURE_SPDF CM_SPDF_0
403#else
404#define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
405#define CM_PLAYBACK_SPDF CM_SPDF_0
406#define CM_CAPTURE_SPDF CM_SPDF_1
407#endif
408
409
410/*
411 * driver data
412 */
413
414struct cmipci_pcm {
415 struct snd_pcm_substream *substream;
416 u8 running; /* dac/adc running? */
417 u8 fmt; /* format bits */
418 u8 is_dac;
419 u8 needs_silencing;
420 unsigned int dma_size; /* in frames */
421 unsigned int shift;
422 unsigned int ch; /* channel (0/1) */
423 unsigned int offset; /* physical address of the buffer */
424};
425
426/* mixer elements toggled/resumed during ac3 playback */
427struct cmipci_mixer_auto_switches {
428 const char *name; /* switch to toggle */
429 int toggle_on; /* value to change when ac3 mode */
430};
431static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
432 {"PCM Playback Switch", 0},
433 {"IEC958 Output Switch", 1},
434 {"IEC958 Mix Analog", 0},
435 // {"IEC958 Out To DAC", 1}, // no longer used
436 {"IEC958 Loop", 0},
437};
438#define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
439
440struct cmipci {
441 struct snd_card *card;
442
443 struct pci_dev *pci;
444 unsigned int device; /* device ID */
445 int irq;
446
447 unsigned long iobase;
448 unsigned int ctrl; /* FUNCTRL0 current value */
449
450 struct snd_pcm *pcm; /* DAC/ADC PCM */
451 struct snd_pcm *pcm2; /* 2nd DAC */
452 struct snd_pcm *pcm_spdif; /* SPDIF */
453
454 int chip_version;
455 int max_channels;
456 unsigned int can_ac3_sw: 1;
457 unsigned int can_ac3_hw: 1;
458 unsigned int can_multi_ch: 1;
459 unsigned int can_96k: 1; /* samplerate above 48k */
460 unsigned int do_soft_ac3: 1;
461
462 unsigned int spdif_playback_avail: 1; /* spdif ready? */
463 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
464 int spdif_counter; /* for software AC3 */
465
466 unsigned int dig_status;
467 unsigned int dig_pcm_status;
468
469 struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
470
471 int opened[2]; /* open mode */
472 struct mutex open_mutex;
473
474 unsigned int mixer_insensitive: 1;
475 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
476 int mixer_res_status[CM_SAVED_MIXERS];
477
478 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
479
480 /* external MIDI */
481 struct snd_rawmidi *rmidi;
482
483#ifdef SUPPORT_JOYSTICK
484 struct gameport *gameport;
485#endif
486
487 spinlock_t reg_lock;
488
489#ifdef CONFIG_PM_SLEEP
490 unsigned int saved_regs[0x20];
491 unsigned char saved_mixers[0x20];
492#endif
493};
494
495
496/* read/write operations for dword register */
497static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
498{
499 outl(data, cm->iobase + cmd);
500}
501
502static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
503{
504 return inl(cm->iobase + cmd);
505}
506
507/* read/write operations for word register */
508static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
509{
510 outw(data, cm->iobase + cmd);
511}
512
513static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
514{
515 return inw(cm->iobase + cmd);
516}
517
518/* read/write operations for byte register */
519static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
520{
521 outb(data, cm->iobase + cmd);
522}
523
524static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
525{
526 return inb(cm->iobase + cmd);
527}
528
529/* bit operations for dword register */
530static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
531{
532 unsigned int val, oval;
533 val = oval = inl(cm->iobase + cmd);
534 val |= flag;
535 if (val == oval)
536 return 0;
537 outl(val, cm->iobase + cmd);
538 return 1;
539}
540
541static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
542{
543 unsigned int val, oval;
544 val = oval = inl(cm->iobase + cmd);
545 val &= ~flag;
546 if (val == oval)
547 return 0;
548 outl(val, cm->iobase + cmd);
549 return 1;
550}
551
552/* bit operations for byte register */
553static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
554{
555 unsigned char val, oval;
556 val = oval = inb(cm->iobase + cmd);
557 val |= flag;
558 if (val == oval)
559 return 0;
560 outb(val, cm->iobase + cmd);
561 return 1;
562}
563
564static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
565{
566 unsigned char val, oval;
567 val = oval = inb(cm->iobase + cmd);
568 val &= ~flag;
569 if (val == oval)
570 return 0;
571 outb(val, cm->iobase + cmd);
572 return 1;
573}
574
575
576/*
577 * PCM interface
578 */
579
580/*
581 * calculate frequency
582 */
583
584static const unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
585
586static unsigned int snd_cmipci_rate_freq(unsigned int rate)
587{
588 unsigned int i;
589
590 for (i = 0; i < ARRAY_SIZE(rates); i++) {
591 if (rates[i] == rate)
592 return i;
593 }
594 snd_BUG();
595 return 0;
596}
597
598#ifdef USE_VAR48KRATE
599/*
600 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
601 * does it this way .. maybe not. Never get any information from C-Media about
602 * that <werner@suse.de>.
603 */
604static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
605{
606 unsigned int delta, tolerance;
607 int xm, xn, xr;
608
609 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
610 rate <<= 1;
611 *n = -1;
612 if (*r > 0xff)
613 goto out;
614 tolerance = rate*CM_TOLERANCE_RATE;
615
616 for (xn = (1+2); xn < (0x1f+2); xn++) {
617 for (xm = (1+2); xm < (0xff+2); xm++) {
618 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
619
620 if (xr < rate)
621 delta = rate - xr;
622 else
623 delta = xr - rate;
624
625 /*
626 * If we found one, remember this,
627 * and try to find a closer one
628 */
629 if (delta < tolerance) {
630 tolerance = delta;
631 *m = xm - 2;
632 *n = xn - 2;
633 }
634 }
635 }
636out:
637 return (*n > -1);
638}
639
640/*
641 * Program pll register bits, I assume that the 8 registers 0xf8 up to 0xff
642 * are mapped onto the 8 ADC/DAC sampling frequency which can be chosen
643 * at the register CM_REG_FUNCTRL1 (0x04).
644 * Problem: other ways are also possible (any information about that?)
645 */
646static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
647{
648 unsigned int reg = CM_REG_PLL + slot;
649 /*
650 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
651 * for DSFC/ASFC (000 up to 111).
652 */
653
654 /* FIXME: Init (Do we've to set an other register first before programming?) */
655
656 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
657 snd_cmipci_write_b(cm, reg, rate>>8);
658 snd_cmipci_write_b(cm, reg, rate&0xff);
659
660 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
661}
662#endif /* USE_VAR48KRATE */
663
664static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
665 struct snd_pcm_hw_params *hw_params)
666{
667 struct cmipci *cm = snd_pcm_substream_chip(substream);
668 if (params_channels(hw_params) > 2) {
669 mutex_lock(&cm->open_mutex);
670 if (cm->opened[CM_CH_PLAY]) {
671 mutex_unlock(&cm->open_mutex);
672 return -EBUSY;
673 }
674 /* reserve the channel A */
675 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
676 mutex_unlock(&cm->open_mutex);
677 }
678 return 0;
679}
680
681static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
682{
683 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
684 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
685 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
686 udelay(10);
687}
688
689
690/*
691 */
692
693static const unsigned int hw_channels[] = {1, 2, 4, 6, 8};
694static const struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
695 .count = 3,
696 .list = hw_channels,
697 .mask = 0,
698};
699static const struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
700 .count = 4,
701 .list = hw_channels,
702 .mask = 0,
703};
704static const struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
705 .count = 5,
706 .list = hw_channels,
707 .mask = 0,
708};
709
710static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
711{
712 if (channels > 2) {
713 if (!cm->can_multi_ch || !rec->ch)
714 return -EINVAL;
715 if (rec->fmt != 0x03) /* stereo 16bit only */
716 return -EINVAL;
717 }
718
719 if (cm->can_multi_ch) {
720 spin_lock_irq(&cm->reg_lock);
721 if (channels > 2) {
722 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
723 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
724 } else {
725 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
726 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
727 }
728 if (channels == 8)
729 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
730 else
731 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
732 if (channels == 6) {
733 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
734 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
735 } else {
736 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
737 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
738 }
739 if (channels == 4)
740 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
741 else
742 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
743 spin_unlock_irq(&cm->reg_lock);
744 }
745 return 0;
746}
747
748
749/*
750 * prepare playback/capture channel
751 * channel to be used must have been set in rec->ch.
752 */
753static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
754 struct snd_pcm_substream *substream)
755{
756 unsigned int reg, freq, freq_ext, val;
757 unsigned int period_size;
758 struct snd_pcm_runtime *runtime = substream->runtime;
759
760 rec->fmt = 0;
761 rec->shift = 0;
762 if (snd_pcm_format_width(runtime->format) >= 16) {
763 rec->fmt |= 0x02;
764 if (snd_pcm_format_width(runtime->format) > 16)
765 rec->shift++; /* 24/32bit */
766 }
767 if (runtime->channels > 1)
768 rec->fmt |= 0x01;
769 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
770 dev_dbg(cm->card->dev, "cannot set dac channels\n");
771 return -EINVAL;
772 }
773
774 rec->offset = runtime->dma_addr;
775 /* buffer and period sizes in frame */
776 rec->dma_size = runtime->buffer_size << rec->shift;
777 period_size = runtime->period_size << rec->shift;
778 if (runtime->channels > 2) {
779 /* multi-channels */
780 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
781 period_size = (period_size * runtime->channels) / 2;
782 }
783
784 spin_lock_irq(&cm->reg_lock);
785
786 /* set buffer address */
787 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
788 snd_cmipci_write(cm, reg, rec->offset);
789 /* program sample counts */
790 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
791 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
792 snd_cmipci_write_w(cm, reg + 2, period_size - 1);
793
794 /* set adc/dac flag */
795 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
796 if (rec->is_dac)
797 cm->ctrl &= ~val;
798 else
799 cm->ctrl |= val;
800 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
801 /* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */
802
803 /* set sample rate */
804 freq = 0;
805 freq_ext = 0;
806 if (runtime->rate > 48000)
807 switch (runtime->rate) {
808 case 88200: freq_ext = CM_CH0_SRATE_88K; break;
809 case 96000: freq_ext = CM_CH0_SRATE_96K; break;
810 case 128000: freq_ext = CM_CH0_SRATE_128K; break;
811 default: snd_BUG(); break;
812 }
813 else
814 freq = snd_cmipci_rate_freq(runtime->rate);
815 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
816 if (rec->ch) {
817 val &= ~CM_DSFC_MASK;
818 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
819 } else {
820 val &= ~CM_ASFC_MASK;
821 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
822 }
823 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
824 dev_dbg(cm->card->dev, "functrl1 = %08x\n", val);
825
826 /* set format */
827 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
828 if (rec->ch) {
829 val &= ~CM_CH1FMT_MASK;
830 val |= rec->fmt << CM_CH1FMT_SHIFT;
831 } else {
832 val &= ~CM_CH0FMT_MASK;
833 val |= rec->fmt << CM_CH0FMT_SHIFT;
834 }
835 if (cm->can_96k) {
836 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
837 val |= freq_ext << (rec->ch * 2);
838 }
839 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
840 dev_dbg(cm->card->dev, "chformat = %08x\n", val);
841
842 if (!rec->is_dac && cm->chip_version) {
843 if (runtime->rate > 44100)
844 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
845 else
846 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
847 }
848
849 rec->running = 0;
850 spin_unlock_irq(&cm->reg_lock);
851
852 return 0;
853}
854
855/*
856 * PCM trigger/stop
857 */
858static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
859 int cmd)
860{
861 unsigned int inthld, chen, reset, pause;
862 int result = 0;
863
864 inthld = CM_CH0_INT_EN << rec->ch;
865 chen = CM_CHEN0 << rec->ch;
866 reset = CM_RST_CH0 << rec->ch;
867 pause = CM_PAUSE0 << rec->ch;
868
869 spin_lock(&cm->reg_lock);
870 switch (cmd) {
871 case SNDRV_PCM_TRIGGER_START:
872 rec->running = 1;
873 /* set interrupt */
874 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
875 cm->ctrl |= chen;
876 /* enable channel */
877 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
878 dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl);
879 break;
880 case SNDRV_PCM_TRIGGER_STOP:
881 rec->running = 0;
882 /* disable interrupt */
883 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
884 /* reset */
885 cm->ctrl &= ~chen;
886 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
887 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
888 rec->needs_silencing = rec->is_dac;
889 break;
890 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
891 case SNDRV_PCM_TRIGGER_SUSPEND:
892 cm->ctrl |= pause;
893 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
894 break;
895 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
896 case SNDRV_PCM_TRIGGER_RESUME:
897 cm->ctrl &= ~pause;
898 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
899 break;
900 default:
901 result = -EINVAL;
902 break;
903 }
904 spin_unlock(&cm->reg_lock);
905 return result;
906}
907
908/*
909 * return the current pointer
910 */
911static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
912 struct snd_pcm_substream *substream)
913{
914 size_t ptr;
915 unsigned int reg, rem, tries;
916
917 if (!rec->running)
918 return 0;
919#if 1 // this seems better..
920 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
921 for (tries = 0; tries < 3; tries++) {
922 rem = snd_cmipci_read_w(cm, reg);
923 if (rem < rec->dma_size)
924 goto ok;
925 }
926 dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem);
927 return SNDRV_PCM_POS_XRUN;
928ok:
929 ptr = (rec->dma_size - (rem + 1)) >> rec->shift;
930#else
931 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
932 ptr = snd_cmipci_read(cm, reg) - rec->offset;
933 ptr = bytes_to_frames(substream->runtime, ptr);
934#endif
935 if (substream->runtime->channels > 2)
936 ptr = (ptr * 2) / substream->runtime->channels;
937 return ptr;
938}
939
940/*
941 * playback
942 */
943
944static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
945 int cmd)
946{
947 struct cmipci *cm = snd_pcm_substream_chip(substream);
948 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
949}
950
951static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
952{
953 struct cmipci *cm = snd_pcm_substream_chip(substream);
954 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
955}
956
957
958
959/*
960 * capture
961 */
962
963static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
964 int cmd)
965{
966 struct cmipci *cm = snd_pcm_substream_chip(substream);
967 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
968}
969
970static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
971{
972 struct cmipci *cm = snd_pcm_substream_chip(substream);
973 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
974}
975
976
977/*
978 * hw preparation for spdif
979 */
980
981static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
982 struct snd_ctl_elem_info *uinfo)
983{
984 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
985 uinfo->count = 1;
986 return 0;
987}
988
989static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
990 struct snd_ctl_elem_value *ucontrol)
991{
992 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
993 int i;
994
995 spin_lock_irq(&chip->reg_lock);
996 for (i = 0; i < 4; i++)
997 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
998 spin_unlock_irq(&chip->reg_lock);
999 return 0;
1000}
1001
1002static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1003 struct snd_ctl_elem_value *ucontrol)
1004{
1005 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1006 int i, change;
1007 unsigned int val;
1008
1009 val = 0;
1010 spin_lock_irq(&chip->reg_lock);
1011 for (i = 0; i < 4; i++)
1012 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1013 change = val != chip->dig_status;
1014 chip->dig_status = val;
1015 spin_unlock_irq(&chip->reg_lock);
1016 return change;
1017}
1018
1019static const struct snd_kcontrol_new snd_cmipci_spdif_default =
1020{
1021 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1022 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1023 .info = snd_cmipci_spdif_default_info,
1024 .get = snd_cmipci_spdif_default_get,
1025 .put = snd_cmipci_spdif_default_put
1026};
1027
1028static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1029 struct snd_ctl_elem_info *uinfo)
1030{
1031 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1032 uinfo->count = 1;
1033 return 0;
1034}
1035
1036static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1037 struct snd_ctl_elem_value *ucontrol)
1038{
1039 ucontrol->value.iec958.status[0] = 0xff;
1040 ucontrol->value.iec958.status[1] = 0xff;
1041 ucontrol->value.iec958.status[2] = 0xff;
1042 ucontrol->value.iec958.status[3] = 0xff;
1043 return 0;
1044}
1045
1046static const struct snd_kcontrol_new snd_cmipci_spdif_mask =
1047{
1048 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1049 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1050 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1051 .info = snd_cmipci_spdif_mask_info,
1052 .get = snd_cmipci_spdif_mask_get,
1053};
1054
1055static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1056 struct snd_ctl_elem_info *uinfo)
1057{
1058 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1059 uinfo->count = 1;
1060 return 0;
1061}
1062
1063static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1064 struct snd_ctl_elem_value *ucontrol)
1065{
1066 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1067 int i;
1068
1069 spin_lock_irq(&chip->reg_lock);
1070 for (i = 0; i < 4; i++)
1071 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1072 spin_unlock_irq(&chip->reg_lock);
1073 return 0;
1074}
1075
1076static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1077 struct snd_ctl_elem_value *ucontrol)
1078{
1079 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1080 int i, change;
1081 unsigned int val;
1082
1083 val = 0;
1084 spin_lock_irq(&chip->reg_lock);
1085 for (i = 0; i < 4; i++)
1086 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1087 change = val != chip->dig_pcm_status;
1088 chip->dig_pcm_status = val;
1089 spin_unlock_irq(&chip->reg_lock);
1090 return change;
1091}
1092
1093static const struct snd_kcontrol_new snd_cmipci_spdif_stream =
1094{
1095 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1096 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1097 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1098 .info = snd_cmipci_spdif_stream_info,
1099 .get = snd_cmipci_spdif_stream_get,
1100 .put = snd_cmipci_spdif_stream_put
1101};
1102
1103/*
1104 */
1105
1106/* save mixer setting and mute for AC3 playback */
1107static int save_mixer_state(struct cmipci *cm)
1108{
1109 if (! cm->mixer_insensitive) {
1110 struct snd_ctl_elem_value *val;
1111 unsigned int i;
1112
1113 val = kmalloc(sizeof(*val), GFP_KERNEL);
1114 if (!val)
1115 return -ENOMEM;
1116 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1117 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1118 if (ctl) {
1119 int event;
1120 memset(val, 0, sizeof(*val));
1121 ctl->get(ctl, val);
1122 cm->mixer_res_status[i] = val->value.integer.value[0];
1123 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1124 event = SNDRV_CTL_EVENT_MASK_INFO;
1125 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1126 ctl->put(ctl, val); /* toggle */
1127 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1128 }
1129 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1130 snd_ctl_notify(cm->card, event, &ctl->id);
1131 }
1132 }
1133 kfree(val);
1134 cm->mixer_insensitive = 1;
1135 }
1136 return 0;
1137}
1138
1139
1140/* restore the previously saved mixer status */
1141static void restore_mixer_state(struct cmipci *cm)
1142{
1143 if (cm->mixer_insensitive) {
1144 struct snd_ctl_elem_value *val;
1145 unsigned int i;
1146
1147 val = kmalloc(sizeof(*val), GFP_KERNEL);
1148 if (!val)
1149 return;
1150 cm->mixer_insensitive = 0; /* at first clear this;
1151 otherwise the changes will be ignored */
1152 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1153 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1154 if (ctl) {
1155 int event;
1156
1157 memset(val, 0, sizeof(*val));
1158 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1159 ctl->get(ctl, val);
1160 event = SNDRV_CTL_EVENT_MASK_INFO;
1161 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1162 val->value.integer.value[0] = cm->mixer_res_status[i];
1163 ctl->put(ctl, val);
1164 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1165 }
1166 snd_ctl_notify(cm->card, event, &ctl->id);
1167 }
1168 }
1169 kfree(val);
1170 }
1171}
1172
1173/* spinlock held! */
1174static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1175{
1176 if (do_ac3) {
1177 /* AC3EN for 037 */
1178 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1179 /* AC3EN for 039 */
1180 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1181
1182 if (cm->can_ac3_hw) {
1183 /* SPD24SEL for 037, 0x02 */
1184 /* SPD24SEL for 039, 0x20, but cannot be set */
1185 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1186 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1187 } else { /* can_ac3_sw */
1188 /* SPD32SEL for 037 & 039, 0x20 */
1189 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1190 /* set 176K sample rate to fix 033 HW bug */
1191 if (cm->chip_version == 33) {
1192 if (rate >= 48000) {
1193 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1194 } else {
1195 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1196 }
1197 }
1198 }
1199
1200 } else {
1201 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1202 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1203
1204 if (cm->can_ac3_hw) {
1205 /* chip model >= 37 */
1206 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1207 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1208 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1209 } else {
1210 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1211 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1212 }
1213 } else {
1214 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1215 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1216 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1217 }
1218 }
1219}
1220
1221static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1222{
1223 int rate, err;
1224
1225 rate = subs->runtime->rate;
1226
1227 if (up && do_ac3) {
1228 err = save_mixer_state(cm);
1229 if (err < 0)
1230 return err;
1231 }
1232
1233 spin_lock_irq(&cm->reg_lock);
1234 cm->spdif_playback_avail = up;
1235 if (up) {
1236 /* they are controlled via "IEC958 Output Switch" */
1237 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1238 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1239 if (cm->spdif_playback_enabled)
1240 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1241 setup_ac3(cm, subs, do_ac3, rate);
1242
1243 if (rate == 48000 || rate == 96000)
1244 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1245 else
1246 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1247 if (rate > 48000)
1248 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1249 else
1250 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1251 } else {
1252 /* they are controlled via "IEC958 Output Switch" */
1253 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1254 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1255 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1256 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1257 setup_ac3(cm, subs, 0, 0);
1258 }
1259 spin_unlock_irq(&cm->reg_lock);
1260 return 0;
1261}
1262
1263
1264/*
1265 * preparation
1266 */
1267
1268/* playback - enable spdif only on the certain condition */
1269static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1270{
1271 struct cmipci *cm = snd_pcm_substream_chip(substream);
1272 int rate = substream->runtime->rate;
1273 int err, do_spdif, do_ac3 = 0;
1274
1275 do_spdif = (rate >= 44100 && rate <= 96000 &&
1276 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1277 substream->runtime->channels == 2);
1278 if (do_spdif && cm->can_ac3_hw)
1279 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1280 err = setup_spdif_playback(cm, substream, do_spdif, do_ac3);
1281 if (err < 0)
1282 return err;
1283 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1284}
1285
1286/* playback (via device #2) - enable spdif always */
1287static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1288{
1289 struct cmipci *cm = snd_pcm_substream_chip(substream);
1290 int err, do_ac3;
1291
1292 if (cm->can_ac3_hw)
1293 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1294 else
1295 do_ac3 = 1; /* doesn't matter */
1296 err = setup_spdif_playback(cm, substream, 1, do_ac3);
1297 if (err < 0)
1298 return err;
1299 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1300}
1301
1302/*
1303 * Apparently, the samples last played on channel A stay in some buffer, even
1304 * after the channel is reset, and get added to the data for the rear DACs when
1305 * playing a multichannel stream on channel B. This is likely to generate
1306 * wraparounds and thus distortions.
1307 * To avoid this, we play at least one zero sample after the actual stream has
1308 * stopped.
1309 */
1310static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1311{
1312 struct snd_pcm_runtime *runtime = rec->substream->runtime;
1313 unsigned int reg, val;
1314
1315 if (rec->needs_silencing && runtime && runtime->dma_area) {
1316 /* set up a small silence buffer */
1317 memset(runtime->dma_area, 0, PAGE_SIZE);
1318 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1319 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1320 snd_cmipci_write(cm, reg, val);
1321
1322 /* configure for 16 bits, 2 channels, 8 kHz */
1323 if (runtime->channels > 2)
1324 set_dac_channels(cm, rec, 2);
1325 spin_lock_irq(&cm->reg_lock);
1326 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1327 val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1328 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1329 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1330 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1331 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1332 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1333 if (cm->can_96k)
1334 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
1335 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1336
1337 /* start stream (we don't need interrupts) */
1338 cm->ctrl |= CM_CHEN0 << rec->ch;
1339 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1340 spin_unlock_irq(&cm->reg_lock);
1341
1342 msleep(1);
1343
1344 /* stop and reset stream */
1345 spin_lock_irq(&cm->reg_lock);
1346 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1347 val = CM_RST_CH0 << rec->ch;
1348 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1349 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1350 spin_unlock_irq(&cm->reg_lock);
1351
1352 rec->needs_silencing = 0;
1353 }
1354}
1355
1356static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1357{
1358 struct cmipci *cm = snd_pcm_substream_chip(substream);
1359 setup_spdif_playback(cm, substream, 0, 0);
1360 restore_mixer_state(cm);
1361 snd_cmipci_silence_hack(cm, &cm->channel[0]);
1362 return 0;
1363}
1364
1365static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1366{
1367 struct cmipci *cm = snd_pcm_substream_chip(substream);
1368 snd_cmipci_silence_hack(cm, &cm->channel[1]);
1369 return 0;
1370}
1371
1372/* capture */
1373static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1374{
1375 struct cmipci *cm = snd_pcm_substream_chip(substream);
1376 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1377}
1378
1379/* capture with spdif (via device #2) */
1380static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1381{
1382 struct cmipci *cm = snd_pcm_substream_chip(substream);
1383
1384 spin_lock_irq(&cm->reg_lock);
1385 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1386 if (cm->can_96k) {
1387 if (substream->runtime->rate > 48000)
1388 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1389 else
1390 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1391 }
1392 if (snd_pcm_format_width(substream->runtime->format) > 16)
1393 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1394 else
1395 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1396
1397 spin_unlock_irq(&cm->reg_lock);
1398
1399 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1400}
1401
1402static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1403{
1404 struct cmipci *cm = snd_pcm_substream_chip(subs);
1405
1406 spin_lock_irq(&cm->reg_lock);
1407 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1408 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1409 spin_unlock_irq(&cm->reg_lock);
1410
1411 return 0;
1412}
1413
1414
1415/*
1416 * interrupt handler
1417 */
1418static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1419{
1420 struct cmipci *cm = dev_id;
1421 unsigned int status, mask = 0;
1422
1423 /* fastpath out, to ease interrupt sharing */
1424 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1425 if (!(status & CM_INTR))
1426 return IRQ_NONE;
1427
1428 /* acknowledge interrupt */
1429 spin_lock(&cm->reg_lock);
1430 if (status & CM_CHINT0)
1431 mask |= CM_CH0_INT_EN;
1432 if (status & CM_CHINT1)
1433 mask |= CM_CH1_INT_EN;
1434 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1435 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1436 spin_unlock(&cm->reg_lock);
1437
1438 if (cm->rmidi && (status & CM_UARTINT))
1439 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1440
1441 if (cm->pcm) {
1442 if ((status & CM_CHINT0) && cm->channel[0].running)
1443 snd_pcm_period_elapsed(cm->channel[0].substream);
1444 if ((status & CM_CHINT1) && cm->channel[1].running)
1445 snd_pcm_period_elapsed(cm->channel[1].substream);
1446 }
1447 return IRQ_HANDLED;
1448}
1449
1450/*
1451 * h/w infos
1452 */
1453
1454/* playback on channel A */
1455static const struct snd_pcm_hardware snd_cmipci_playback =
1456{
1457 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1458 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1459 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1460 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1461 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1462 .rate_min = 5512,
1463 .rate_max = 48000,
1464 .channels_min = 1,
1465 .channels_max = 2,
1466 .buffer_bytes_max = (128*1024),
1467 .period_bytes_min = 64,
1468 .period_bytes_max = (128*1024),
1469 .periods_min = 2,
1470 .periods_max = 1024,
1471 .fifo_size = 0,
1472};
1473
1474/* capture on channel B */
1475static const struct snd_pcm_hardware snd_cmipci_capture =
1476{
1477 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1478 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1479 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1480 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1481 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1482 .rate_min = 5512,
1483 .rate_max = 48000,
1484 .channels_min = 1,
1485 .channels_max = 2,
1486 .buffer_bytes_max = (128*1024),
1487 .period_bytes_min = 64,
1488 .period_bytes_max = (128*1024),
1489 .periods_min = 2,
1490 .periods_max = 1024,
1491 .fifo_size = 0,
1492};
1493
1494/* playback on channel B - stereo 16bit only? */
1495static const struct snd_pcm_hardware snd_cmipci_playback2 =
1496{
1497 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1498 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1499 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1500 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1501 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1502 .rate_min = 5512,
1503 .rate_max = 48000,
1504 .channels_min = 2,
1505 .channels_max = 2,
1506 .buffer_bytes_max = (128*1024),
1507 .period_bytes_min = 64,
1508 .period_bytes_max = (128*1024),
1509 .periods_min = 2,
1510 .periods_max = 1024,
1511 .fifo_size = 0,
1512};
1513
1514/* spdif playback on channel A */
1515static const struct snd_pcm_hardware snd_cmipci_playback_spdif =
1516{
1517 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1518 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1519 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1520 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1521 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1522 .rate_min = 44100,
1523 .rate_max = 48000,
1524 .channels_min = 2,
1525 .channels_max = 2,
1526 .buffer_bytes_max = (128*1024),
1527 .period_bytes_min = 64,
1528 .period_bytes_max = (128*1024),
1529 .periods_min = 2,
1530 .periods_max = 1024,
1531 .fifo_size = 0,
1532};
1533
1534/* spdif playback on channel A (32bit, IEC958 subframes) */
1535static const struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1536{
1537 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1538 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1539 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1540 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1541 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1542 .rate_min = 44100,
1543 .rate_max = 48000,
1544 .channels_min = 2,
1545 .channels_max = 2,
1546 .buffer_bytes_max = (128*1024),
1547 .period_bytes_min = 64,
1548 .period_bytes_max = (128*1024),
1549 .periods_min = 2,
1550 .periods_max = 1024,
1551 .fifo_size = 0,
1552};
1553
1554/* spdif capture on channel B */
1555static const struct snd_pcm_hardware snd_cmipci_capture_spdif =
1556{
1557 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1558 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1559 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1560 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1561 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1562 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1563 .rate_min = 44100,
1564 .rate_max = 48000,
1565 .channels_min = 2,
1566 .channels_max = 2,
1567 .buffer_bytes_max = (128*1024),
1568 .period_bytes_min = 64,
1569 .period_bytes_max = (128*1024),
1570 .periods_min = 2,
1571 .periods_max = 1024,
1572 .fifo_size = 0,
1573};
1574
1575static const unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050,
1576 32000, 44100, 48000, 88200, 96000, 128000 };
1577static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1578 .count = ARRAY_SIZE(rate_constraints),
1579 .list = rate_constraints,
1580 .mask = 0,
1581};
1582
1583/*
1584 * check device open/close
1585 */
1586static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1587{
1588 int ch = mode & CM_OPEN_CH_MASK;
1589
1590 /* FIXME: a file should wait until the device becomes free
1591 * when it's opened on blocking mode. however, since the current
1592 * pcm framework doesn't pass file pointer before actually opened,
1593 * we can't know whether blocking mode or not in open callback..
1594 */
1595 mutex_lock(&cm->open_mutex);
1596 if (cm->opened[ch]) {
1597 mutex_unlock(&cm->open_mutex);
1598 return -EBUSY;
1599 }
1600 cm->opened[ch] = mode;
1601 cm->channel[ch].substream = subs;
1602 if (! (mode & CM_OPEN_DAC)) {
1603 /* disable dual DAC mode */
1604 cm->channel[ch].is_dac = 0;
1605 spin_lock_irq(&cm->reg_lock);
1606 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1607 spin_unlock_irq(&cm->reg_lock);
1608 }
1609 mutex_unlock(&cm->open_mutex);
1610 return 0;
1611}
1612
1613static void close_device_check(struct cmipci *cm, int mode)
1614{
1615 int ch = mode & CM_OPEN_CH_MASK;
1616
1617 mutex_lock(&cm->open_mutex);
1618 if (cm->opened[ch] == mode) {
1619 if (cm->channel[ch].substream) {
1620 snd_cmipci_ch_reset(cm, ch);
1621 cm->channel[ch].running = 0;
1622 cm->channel[ch].substream = NULL;
1623 }
1624 cm->opened[ch] = 0;
1625 if (! cm->channel[ch].is_dac) {
1626 /* enable dual DAC mode again */
1627 cm->channel[ch].is_dac = 1;
1628 spin_lock_irq(&cm->reg_lock);
1629 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1630 spin_unlock_irq(&cm->reg_lock);
1631 }
1632 }
1633 mutex_unlock(&cm->open_mutex);
1634}
1635
1636/*
1637 */
1638
1639static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1640{
1641 struct cmipci *cm = snd_pcm_substream_chip(substream);
1642 struct snd_pcm_runtime *runtime = substream->runtime;
1643 int err;
1644
1645 err = open_device_check(cm, CM_OPEN_PLAYBACK, substream);
1646 if (err < 0)
1647 return err;
1648 runtime->hw = snd_cmipci_playback;
1649 if (cm->chip_version == 68) {
1650 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1651 SNDRV_PCM_RATE_96000;
1652 runtime->hw.rate_max = 96000;
1653 } else if (cm->chip_version == 55) {
1654 err = snd_pcm_hw_constraint_list(runtime, 0,
1655 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1656 if (err < 0)
1657 return err;
1658 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1659 runtime->hw.rate_max = 128000;
1660 }
1661 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1662 cm->dig_pcm_status = cm->dig_status;
1663 return 0;
1664}
1665
1666static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1667{
1668 struct cmipci *cm = snd_pcm_substream_chip(substream);
1669 struct snd_pcm_runtime *runtime = substream->runtime;
1670 int err;
1671
1672 err = open_device_check(cm, CM_OPEN_CAPTURE, substream);
1673 if (err < 0)
1674 return err;
1675 runtime->hw = snd_cmipci_capture;
1676 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1677 runtime->hw.rate_min = 41000;
1678 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1679 } else if (cm->chip_version == 55) {
1680 err = snd_pcm_hw_constraint_list(runtime, 0,
1681 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1682 if (err < 0)
1683 return err;
1684 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1685 runtime->hw.rate_max = 128000;
1686 }
1687 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1688 return 0;
1689}
1690
1691static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1692{
1693 struct cmipci *cm = snd_pcm_substream_chip(substream);
1694 struct snd_pcm_runtime *runtime = substream->runtime;
1695 int err;
1696
1697 /* use channel B */
1698 err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream);
1699 if (err < 0)
1700 return err;
1701 runtime->hw = snd_cmipci_playback2;
1702 mutex_lock(&cm->open_mutex);
1703 if (! cm->opened[CM_CH_PLAY]) {
1704 if (cm->can_multi_ch) {
1705 runtime->hw.channels_max = cm->max_channels;
1706 if (cm->max_channels == 4)
1707 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1708 else if (cm->max_channels == 6)
1709 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1710 else if (cm->max_channels == 8)
1711 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1712 }
1713 }
1714 mutex_unlock(&cm->open_mutex);
1715 if (cm->chip_version == 68) {
1716 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1717 SNDRV_PCM_RATE_96000;
1718 runtime->hw.rate_max = 96000;
1719 } else if (cm->chip_version == 55) {
1720 err = snd_pcm_hw_constraint_list(runtime, 0,
1721 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1722 if (err < 0)
1723 return err;
1724 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1725 runtime->hw.rate_max = 128000;
1726 }
1727 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1728 return 0;
1729}
1730
1731static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1732{
1733 struct cmipci *cm = snd_pcm_substream_chip(substream);
1734 struct snd_pcm_runtime *runtime = substream->runtime;
1735 int err;
1736
1737 /* use channel A */
1738 err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream);
1739 if (err < 0)
1740 return err;
1741 if (cm->can_ac3_hw) {
1742 runtime->hw = snd_cmipci_playback_spdif;
1743 if (cm->chip_version >= 37) {
1744 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1745 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1746 }
1747 if (cm->can_96k) {
1748 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1749 SNDRV_PCM_RATE_96000;
1750 runtime->hw.rate_max = 96000;
1751 }
1752 } else {
1753 runtime->hw = snd_cmipci_playback_iec958_subframe;
1754 }
1755 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1756 cm->dig_pcm_status = cm->dig_status;
1757 return 0;
1758}
1759
1760static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1761{
1762 struct cmipci *cm = snd_pcm_substream_chip(substream);
1763 struct snd_pcm_runtime *runtime = substream->runtime;
1764 int err;
1765
1766 /* use channel B */
1767 err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream);
1768 if (err < 0)
1769 return err;
1770 runtime->hw = snd_cmipci_capture_spdif;
1771 if (cm->can_96k && !(cm->chip_version == 68)) {
1772 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1773 SNDRV_PCM_RATE_96000;
1774 runtime->hw.rate_max = 96000;
1775 }
1776 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1777 return 0;
1778}
1779
1780
1781/*
1782 */
1783
1784static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1785{
1786 struct cmipci *cm = snd_pcm_substream_chip(substream);
1787 close_device_check(cm, CM_OPEN_PLAYBACK);
1788 return 0;
1789}
1790
1791static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1792{
1793 struct cmipci *cm = snd_pcm_substream_chip(substream);
1794 close_device_check(cm, CM_OPEN_CAPTURE);
1795 return 0;
1796}
1797
1798static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1799{
1800 struct cmipci *cm = snd_pcm_substream_chip(substream);
1801 close_device_check(cm, CM_OPEN_PLAYBACK2);
1802 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1803 return 0;
1804}
1805
1806static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1807{
1808 struct cmipci *cm = snd_pcm_substream_chip(substream);
1809 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1810 return 0;
1811}
1812
1813static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1814{
1815 struct cmipci *cm = snd_pcm_substream_chip(substream);
1816 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1817 return 0;
1818}
1819
1820
1821/*
1822 */
1823
1824static const struct snd_pcm_ops snd_cmipci_playback_ops = {
1825 .open = snd_cmipci_playback_open,
1826 .close = snd_cmipci_playback_close,
1827 .hw_free = snd_cmipci_playback_hw_free,
1828 .prepare = snd_cmipci_playback_prepare,
1829 .trigger = snd_cmipci_playback_trigger,
1830 .pointer = snd_cmipci_playback_pointer,
1831};
1832
1833static const struct snd_pcm_ops snd_cmipci_capture_ops = {
1834 .open = snd_cmipci_capture_open,
1835 .close = snd_cmipci_capture_close,
1836 .prepare = snd_cmipci_capture_prepare,
1837 .trigger = snd_cmipci_capture_trigger,
1838 .pointer = snd_cmipci_capture_pointer,
1839};
1840
1841static const struct snd_pcm_ops snd_cmipci_playback2_ops = {
1842 .open = snd_cmipci_playback2_open,
1843 .close = snd_cmipci_playback2_close,
1844 .hw_params = snd_cmipci_playback2_hw_params,
1845 .hw_free = snd_cmipci_playback2_hw_free,
1846 .prepare = snd_cmipci_capture_prepare, /* channel B */
1847 .trigger = snd_cmipci_capture_trigger, /* channel B */
1848 .pointer = snd_cmipci_capture_pointer, /* channel B */
1849};
1850
1851static const struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1852 .open = snd_cmipci_playback_spdif_open,
1853 .close = snd_cmipci_playback_spdif_close,
1854 .hw_free = snd_cmipci_playback_hw_free,
1855 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1856 .trigger = snd_cmipci_playback_trigger,
1857 .pointer = snd_cmipci_playback_pointer,
1858};
1859
1860static const struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1861 .open = snd_cmipci_capture_spdif_open,
1862 .close = snd_cmipci_capture_spdif_close,
1863 .hw_free = snd_cmipci_capture_spdif_hw_free,
1864 .prepare = snd_cmipci_capture_spdif_prepare,
1865 .trigger = snd_cmipci_capture_trigger,
1866 .pointer = snd_cmipci_capture_pointer,
1867};
1868
1869
1870/*
1871 */
1872
1873static int snd_cmipci_pcm_new(struct cmipci *cm, int device)
1874{
1875 struct snd_pcm *pcm;
1876 int err;
1877
1878 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1879 if (err < 0)
1880 return err;
1881
1882 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1883 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1884
1885 pcm->private_data = cm;
1886 pcm->info_flags = 0;
1887 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1888 cm->pcm = pcm;
1889
1890 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1891 &cm->pci->dev, 64*1024, 128*1024);
1892
1893 return 0;
1894}
1895
1896static int snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1897{
1898 struct snd_pcm *pcm;
1899 int err;
1900
1901 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1902 if (err < 0)
1903 return err;
1904
1905 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1906
1907 pcm->private_data = cm;
1908 pcm->info_flags = 0;
1909 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1910 cm->pcm2 = pcm;
1911
1912 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1913 &cm->pci->dev, 64*1024, 128*1024);
1914
1915 return 0;
1916}
1917
1918static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1919{
1920 struct snd_pcm *pcm;
1921 int err;
1922
1923 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1924 if (err < 0)
1925 return err;
1926
1927 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1928 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1929
1930 pcm->private_data = cm;
1931 pcm->info_flags = 0;
1932 strcpy(pcm->name, "C-Media PCI IEC958");
1933 cm->pcm_spdif = pcm;
1934
1935 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1936 &cm->pci->dev, 64*1024, 128*1024);
1937
1938 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1939 snd_pcm_alt_chmaps, cm->max_channels, 0,
1940 NULL);
1941 if (err < 0)
1942 return err;
1943
1944 return 0;
1945}
1946
1947/*
1948 * mixer interface:
1949 * - CM8338/8738 has a compatible mixer interface with SB16, but
1950 * lack of some elements like tone control, i/o gain and AGC.
1951 * - Access to native registers:
1952 * - A 3D switch
1953 * - Output mute switches
1954 */
1955
1956static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1957{
1958 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1959 outb(data, s->iobase + CM_REG_SB16_DATA);
1960}
1961
1962static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1963{
1964 unsigned char v;
1965
1966 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1967 v = inb(s->iobase + CM_REG_SB16_DATA);
1968 return v;
1969}
1970
1971/*
1972 * general mixer element
1973 */
1974struct cmipci_sb_reg {
1975 unsigned int left_reg, right_reg;
1976 unsigned int left_shift, right_shift;
1977 unsigned int mask;
1978 unsigned int invert: 1;
1979 unsigned int stereo: 1;
1980};
1981
1982#define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1983 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1984
1985#define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1986{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1987 .info = snd_cmipci_info_volume, \
1988 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1989 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1990}
1991
1992#define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1993#define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1994#define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1995#define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1996
1997static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
1998{
1999 r->left_reg = val & 0xff;
2000 r->right_reg = (val >> 8) & 0xff;
2001 r->left_shift = (val >> 16) & 0x07;
2002 r->right_shift = (val >> 19) & 0x07;
2003 r->invert = (val >> 22) & 1;
2004 r->stereo = (val >> 23) & 1;
2005 r->mask = (val >> 24) & 0xff;
2006}
2007
2008static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
2009 struct snd_ctl_elem_info *uinfo)
2010{
2011 struct cmipci_sb_reg reg;
2012
2013 cmipci_sb_reg_decode(®, kcontrol->private_value);
2014 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2015 uinfo->count = reg.stereo + 1;
2016 uinfo->value.integer.min = 0;
2017 uinfo->value.integer.max = reg.mask;
2018 return 0;
2019}
2020
2021static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
2022 struct snd_ctl_elem_value *ucontrol)
2023{
2024 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2025 struct cmipci_sb_reg reg;
2026 int val;
2027
2028 cmipci_sb_reg_decode(®, kcontrol->private_value);
2029 spin_lock_irq(&cm->reg_lock);
2030 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
2031 if (reg.invert)
2032 val = reg.mask - val;
2033 ucontrol->value.integer.value[0] = val;
2034 if (reg.stereo) {
2035 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
2036 if (reg.invert)
2037 val = reg.mask - val;
2038 ucontrol->value.integer.value[1] = val;
2039 }
2040 spin_unlock_irq(&cm->reg_lock);
2041 return 0;
2042}
2043
2044static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
2045 struct snd_ctl_elem_value *ucontrol)
2046{
2047 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2048 struct cmipci_sb_reg reg;
2049 int change;
2050 int left, right, oleft, oright;
2051
2052 cmipci_sb_reg_decode(®, kcontrol->private_value);
2053 left = ucontrol->value.integer.value[0] & reg.mask;
2054 if (reg.invert)
2055 left = reg.mask - left;
2056 left <<= reg.left_shift;
2057 if (reg.stereo) {
2058 right = ucontrol->value.integer.value[1] & reg.mask;
2059 if (reg.invert)
2060 right = reg.mask - right;
2061 right <<= reg.right_shift;
2062 } else
2063 right = 0;
2064 spin_lock_irq(&cm->reg_lock);
2065 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2066 left |= oleft & ~(reg.mask << reg.left_shift);
2067 change = left != oleft;
2068 if (reg.stereo) {
2069 if (reg.left_reg != reg.right_reg) {
2070 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2071 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2072 } else
2073 oright = left;
2074 right |= oright & ~(reg.mask << reg.right_shift);
2075 change |= right != oright;
2076 snd_cmipci_mixer_write(cm, reg.right_reg, right);
2077 } else
2078 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2079 spin_unlock_irq(&cm->reg_lock);
2080 return change;
2081}
2082
2083/*
2084 * input route (left,right) -> (left,right)
2085 */
2086#define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2087{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2088 .info = snd_cmipci_info_input_sw, \
2089 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2090 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2091}
2092
2093static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
2094 struct snd_ctl_elem_info *uinfo)
2095{
2096 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2097 uinfo->count = 4;
2098 uinfo->value.integer.min = 0;
2099 uinfo->value.integer.max = 1;
2100 return 0;
2101}
2102
2103static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2104 struct snd_ctl_elem_value *ucontrol)
2105{
2106 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2107 struct cmipci_sb_reg reg;
2108 int val1, val2;
2109
2110 cmipci_sb_reg_decode(®, kcontrol->private_value);
2111 spin_lock_irq(&cm->reg_lock);
2112 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2113 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2114 spin_unlock_irq(&cm->reg_lock);
2115 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2116 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2117 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2118 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2119 return 0;
2120}
2121
2122static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2123 struct snd_ctl_elem_value *ucontrol)
2124{
2125 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2126 struct cmipci_sb_reg reg;
2127 int change;
2128 int val1, val2, oval1, oval2;
2129
2130 cmipci_sb_reg_decode(®, kcontrol->private_value);
2131 spin_lock_irq(&cm->reg_lock);
2132 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2133 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2134 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2135 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2136 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2137 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2138 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2139 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2140 change = val1 != oval1 || val2 != oval2;
2141 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2142 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2143 spin_unlock_irq(&cm->reg_lock);
2144 return change;
2145}
2146
2147/*
2148 * native mixer switches/volumes
2149 */
2150
2151#define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2152{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2153 .info = snd_cmipci_info_native_mixer, \
2154 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2155 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2156}
2157
2158#define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2159{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2160 .info = snd_cmipci_info_native_mixer, \
2161 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2162 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2163}
2164
2165#define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2166{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2167 .info = snd_cmipci_info_native_mixer, \
2168 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2169 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2170}
2171
2172#define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2173{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2174 .info = snd_cmipci_info_native_mixer, \
2175 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2176 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2177}
2178
2179static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2180 struct snd_ctl_elem_info *uinfo)
2181{
2182 struct cmipci_sb_reg reg;
2183
2184 cmipci_sb_reg_decode(®, kcontrol->private_value);
2185 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2186 uinfo->count = reg.stereo + 1;
2187 uinfo->value.integer.min = 0;
2188 uinfo->value.integer.max = reg.mask;
2189 return 0;
2190
2191}
2192
2193static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2194 struct snd_ctl_elem_value *ucontrol)
2195{
2196 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2197 struct cmipci_sb_reg reg;
2198 unsigned char oreg, val;
2199
2200 cmipci_sb_reg_decode(®, kcontrol->private_value);
2201 spin_lock_irq(&cm->reg_lock);
2202 oreg = inb(cm->iobase + reg.left_reg);
2203 val = (oreg >> reg.left_shift) & reg.mask;
2204 if (reg.invert)
2205 val = reg.mask - val;
2206 ucontrol->value.integer.value[0] = val;
2207 if (reg.stereo) {
2208 val = (oreg >> reg.right_shift) & reg.mask;
2209 if (reg.invert)
2210 val = reg.mask - val;
2211 ucontrol->value.integer.value[1] = val;
2212 }
2213 spin_unlock_irq(&cm->reg_lock);
2214 return 0;
2215}
2216
2217static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2218 struct snd_ctl_elem_value *ucontrol)
2219{
2220 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2221 struct cmipci_sb_reg reg;
2222 unsigned char oreg, nreg, val;
2223
2224 cmipci_sb_reg_decode(®, kcontrol->private_value);
2225 spin_lock_irq(&cm->reg_lock);
2226 oreg = inb(cm->iobase + reg.left_reg);
2227 val = ucontrol->value.integer.value[0] & reg.mask;
2228 if (reg.invert)
2229 val = reg.mask - val;
2230 nreg = oreg & ~(reg.mask << reg.left_shift);
2231 nreg |= (val << reg.left_shift);
2232 if (reg.stereo) {
2233 val = ucontrol->value.integer.value[1] & reg.mask;
2234 if (reg.invert)
2235 val = reg.mask - val;
2236 nreg &= ~(reg.mask << reg.right_shift);
2237 nreg |= (val << reg.right_shift);
2238 }
2239 outb(nreg, cm->iobase + reg.left_reg);
2240 spin_unlock_irq(&cm->reg_lock);
2241 return (nreg != oreg);
2242}
2243
2244/*
2245 * special case - check mixer sensitivity
2246 */
2247static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2248 struct snd_ctl_elem_value *ucontrol)
2249{
2250 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2251 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2252}
2253
2254static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2255 struct snd_ctl_elem_value *ucontrol)
2256{
2257 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2258 if (cm->mixer_insensitive) {
2259 /* ignored */
2260 return 0;
2261 }
2262 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2263}
2264
2265
2266static const struct snd_kcontrol_new snd_cmipci_mixers[] = {
2267 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2268 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2269 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2270 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2271 { /* switch with sensitivity */
2272 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2273 .name = "PCM Playback Switch",
2274 .info = snd_cmipci_info_native_mixer,
2275 .get = snd_cmipci_get_native_mixer_sensitive,
2276 .put = snd_cmipci_put_native_mixer_sensitive,
2277 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2278 },
2279 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2280 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2281 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2282 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2283 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2284 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2285 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2286 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2287 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2288 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2289 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2290 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2291 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2292 CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2293 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2294 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2295 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2296 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2297 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2298 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2299 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2300 CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2301 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2302};
2303
2304/*
2305 * other switches
2306 */
2307
2308struct cmipci_switch_args {
2309 int reg; /* register index */
2310 unsigned int mask; /* mask bits */
2311 unsigned int mask_on; /* mask bits to turn on */
2312 unsigned int is_byte: 1; /* byte access? */
2313 unsigned int ac3_sensitive: 1; /* access forbidden during
2314 * non-audio operation?
2315 */
2316};
2317
2318#define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
2319
2320static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2321 struct snd_ctl_elem_value *ucontrol,
2322 struct cmipci_switch_args *args)
2323{
2324 unsigned int val;
2325 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2326
2327 spin_lock_irq(&cm->reg_lock);
2328 if (args->ac3_sensitive && cm->mixer_insensitive) {
2329 ucontrol->value.integer.value[0] = 0;
2330 spin_unlock_irq(&cm->reg_lock);
2331 return 0;
2332 }
2333 if (args->is_byte)
2334 val = inb(cm->iobase + args->reg);
2335 else
2336 val = snd_cmipci_read(cm, args->reg);
2337 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2338 spin_unlock_irq(&cm->reg_lock);
2339 return 0;
2340}
2341
2342static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2343 struct snd_ctl_elem_value *ucontrol)
2344{
2345 struct cmipci_switch_args *args;
2346 args = (struct cmipci_switch_args *)kcontrol->private_value;
2347 if (snd_BUG_ON(!args))
2348 return -EINVAL;
2349 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2350}
2351
2352static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2353 struct snd_ctl_elem_value *ucontrol,
2354 struct cmipci_switch_args *args)
2355{
2356 unsigned int val;
2357 int change;
2358 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2359
2360 spin_lock_irq(&cm->reg_lock);
2361 if (args->ac3_sensitive && cm->mixer_insensitive) {
2362 /* ignored */
2363 spin_unlock_irq(&cm->reg_lock);
2364 return 0;
2365 }
2366 if (args->is_byte)
2367 val = inb(cm->iobase + args->reg);
2368 else
2369 val = snd_cmipci_read(cm, args->reg);
2370 change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2371 args->mask_on : (args->mask & ~args->mask_on));
2372 if (change) {
2373 val &= ~args->mask;
2374 if (ucontrol->value.integer.value[0])
2375 val |= args->mask_on;
2376 else
2377 val |= (args->mask & ~args->mask_on);
2378 if (args->is_byte)
2379 outb((unsigned char)val, cm->iobase + args->reg);
2380 else
2381 snd_cmipci_write(cm, args->reg, val);
2382 }
2383 spin_unlock_irq(&cm->reg_lock);
2384 return change;
2385}
2386
2387static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2388 struct snd_ctl_elem_value *ucontrol)
2389{
2390 struct cmipci_switch_args *args;
2391 args = (struct cmipci_switch_args *)kcontrol->private_value;
2392 if (snd_BUG_ON(!args))
2393 return -EINVAL;
2394 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2395}
2396
2397#define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2398static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2399 .reg = xreg, \
2400 .mask = xmask, \
2401 .mask_on = xmask_on, \
2402 .is_byte = xis_byte, \
2403 .ac3_sensitive = xac3, \
2404}
2405
2406#define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2407 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2408
2409#if 0 /* these will be controlled in pcm device */
2410DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2411DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2412#endif
2413DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2414DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2415DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2416DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2417DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2418DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2419DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2420DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2421// DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2422DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2423DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2424/* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2425DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2426DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2427#if CM_CH_PLAY == 1
2428DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2429#else
2430DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2431#endif
2432DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2433// DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2434// DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2435// DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2436DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2437
2438#define DEFINE_SWITCH(sname, stype, sarg) \
2439{ .name = sname, \
2440 .iface = stype, \
2441 .info = snd_cmipci_uswitch_info, \
2442 .get = snd_cmipci_uswitch_get, \
2443 .put = snd_cmipci_uswitch_put, \
2444 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2445}
2446
2447#define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2448#define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2449
2450
2451/*
2452 * callbacks for spdif output switch
2453 * needs toggle two registers..
2454 */
2455static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2456 struct snd_ctl_elem_value *ucontrol)
2457{
2458 int changed;
2459 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2460 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2461 return changed;
2462}
2463
2464static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2465 struct snd_ctl_elem_value *ucontrol)
2466{
2467 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2468 int changed;
2469 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2470 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2471 if (changed) {
2472 if (ucontrol->value.integer.value[0]) {
2473 if (chip->spdif_playback_avail)
2474 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2475 } else {
2476 if (chip->spdif_playback_avail)
2477 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2478 }
2479 }
2480 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2481 return changed;
2482}
2483
2484
2485static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2486 struct snd_ctl_elem_info *uinfo)
2487{
2488 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2489 static const char *const texts[3] = {
2490 "Line-In", "Rear Output", "Bass Output"
2491 };
2492
2493 return snd_ctl_enum_info(uinfo, 1,
2494 cm->chip_version >= 39 ? 3 : 2, texts);
2495}
2496
2497static inline unsigned int get_line_in_mode(struct cmipci *cm)
2498{
2499 unsigned int val;
2500 if (cm->chip_version >= 39) {
2501 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2502 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2503 return 2;
2504 }
2505 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2506 if (val & CM_REAR2LIN)
2507 return 1;
2508 return 0;
2509}
2510
2511static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2512 struct snd_ctl_elem_value *ucontrol)
2513{
2514 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2515
2516 spin_lock_irq(&cm->reg_lock);
2517 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2518 spin_unlock_irq(&cm->reg_lock);
2519 return 0;
2520}
2521
2522static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2523 struct snd_ctl_elem_value *ucontrol)
2524{
2525 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2526 int change;
2527
2528 spin_lock_irq(&cm->reg_lock);
2529 if (ucontrol->value.enumerated.item[0] == 2)
2530 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2531 else
2532 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2533 if (ucontrol->value.enumerated.item[0] == 1)
2534 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2535 else
2536 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2537 spin_unlock_irq(&cm->reg_lock);
2538 return change;
2539}
2540
2541static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2542 struct snd_ctl_elem_info *uinfo)
2543{
2544 static const char *const texts[2] = { "Mic-In", "Center/LFE Output" };
2545
2546 return snd_ctl_enum_info(uinfo, 1, 2, texts);
2547}
2548
2549static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2550 struct snd_ctl_elem_value *ucontrol)
2551{
2552 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2553 /* same bit as spdi_phase */
2554 spin_lock_irq(&cm->reg_lock);
2555 ucontrol->value.enumerated.item[0] =
2556 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2557 spin_unlock_irq(&cm->reg_lock);
2558 return 0;
2559}
2560
2561static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2562 struct snd_ctl_elem_value *ucontrol)
2563{
2564 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2565 int change;
2566
2567 spin_lock_irq(&cm->reg_lock);
2568 if (ucontrol->value.enumerated.item[0])
2569 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2570 else
2571 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2572 spin_unlock_irq(&cm->reg_lock);
2573 return change;
2574}
2575
2576/* both for CM8338/8738 */
2577static const struct snd_kcontrol_new snd_cmipci_mixer_switches[] = {
2578 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2579 {
2580 .name = "Line-In Mode",
2581 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2582 .info = snd_cmipci_line_in_mode_info,
2583 .get = snd_cmipci_line_in_mode_get,
2584 .put = snd_cmipci_line_in_mode_put,
2585 },
2586};
2587
2588/* for non-multichannel chips */
2589static const struct snd_kcontrol_new snd_cmipci_nomulti_switch =
2590DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2591
2592/* only for CM8738 */
2593static const struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] = {
2594#if 0 /* controlled in pcm device */
2595 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2596 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2597 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2598#endif
2599 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2600 { .name = "IEC958 Output Switch",
2601 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2602 .info = snd_cmipci_uswitch_info,
2603 .get = snd_cmipci_spdout_enable_get,
2604 .put = snd_cmipci_spdout_enable_put,
2605 },
2606 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2607 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2608 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2609// DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2610 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2611 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2612};
2613
2614/* only for model 033/037 */
2615static const struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] = {
2616 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2617 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2618 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2619};
2620
2621/* only for model 039 or later */
2622static const struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] = {
2623 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2624 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2625 {
2626 .name = "Mic-In Mode",
2627 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2628 .info = snd_cmipci_mic_in_mode_info,
2629 .get = snd_cmipci_mic_in_mode_get,
2630 .put = snd_cmipci_mic_in_mode_put,
2631 }
2632};
2633
2634/* card control switches */
2635static const struct snd_kcontrol_new snd_cmipci_modem_switch =
2636DEFINE_CARD_SWITCH("Modem", modem);
2637
2638
2639static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2640{
2641 struct snd_card *card;
2642 const struct snd_kcontrol_new *sw;
2643 struct snd_kcontrol *kctl;
2644 unsigned int idx;
2645 int err;
2646
2647 if (snd_BUG_ON(!cm || !cm->card))
2648 return -EINVAL;
2649
2650 card = cm->card;
2651
2652 strcpy(card->mixername, "CMedia PCI");
2653
2654 spin_lock_irq(&cm->reg_lock);
2655 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2656 spin_unlock_irq(&cm->reg_lock);
2657
2658 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2659 if (cm->chip_version == 68) { // 8768 has no PCM volume
2660 if (!strcmp(snd_cmipci_mixers[idx].name,
2661 "PCM Playback Volume"))
2662 continue;
2663 }
2664 err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm));
2665 if (err < 0)
2666 return err;
2667 }
2668
2669 /* mixer switches */
2670 sw = snd_cmipci_mixer_switches;
2671 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2672 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2673 if (err < 0)
2674 return err;
2675 }
2676 if (! cm->can_multi_ch) {
2677 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2678 if (err < 0)
2679 return err;
2680 }
2681 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2682 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2683 sw = snd_cmipci_8738_mixer_switches;
2684 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2685 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2686 if (err < 0)
2687 return err;
2688 }
2689 if (cm->can_ac3_hw) {
2690 kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm);
2691 kctl->id.device = pcm_spdif_device;
2692 err = snd_ctl_add(card, kctl);
2693 if (err < 0)
2694 return err;
2695 kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm);
2696 kctl->id.device = pcm_spdif_device;
2697 err = snd_ctl_add(card, kctl);
2698 if (err < 0)
2699 return err;
2700 kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm);
2701 kctl->id.device = pcm_spdif_device;
2702 err = snd_ctl_add(card, kctl);
2703 if (err < 0)
2704 return err;
2705 }
2706 if (cm->chip_version <= 37) {
2707 sw = snd_cmipci_old_mixer_switches;
2708 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2709 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2710 if (err < 0)
2711 return err;
2712 }
2713 }
2714 }
2715 if (cm->chip_version >= 39) {
2716 sw = snd_cmipci_extra_mixer_switches;
2717 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2718 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2719 if (err < 0)
2720 return err;
2721 }
2722 }
2723
2724 /* card switches */
2725 /*
2726 * newer chips don't have the register bits to force modem link
2727 * detection; the bit that was FLINKON now mutes CH1
2728 */
2729 if (cm->chip_version < 39) {
2730 err = snd_ctl_add(cm->card,
2731 snd_ctl_new1(&snd_cmipci_modem_switch, cm));
2732 if (err < 0)
2733 return err;
2734 }
2735
2736 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2737 struct snd_kcontrol *ctl;
2738 ctl = snd_ctl_find_id_mixer(cm->card, cm_saved_mixer[idx].name);
2739 if (ctl)
2740 cm->mixer_res_ctl[idx] = ctl;
2741 }
2742
2743 return 0;
2744}
2745
2746
2747/*
2748 * proc interface
2749 */
2750
2751static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2752 struct snd_info_buffer *buffer)
2753{
2754 struct cmipci *cm = entry->private_data;
2755 int i, v;
2756
2757 snd_iprintf(buffer, "%s\n", cm->card->longname);
2758 for (i = 0; i < 0x94; i++) {
2759 if (i == 0x28)
2760 i = 0x90;
2761 v = inb(cm->iobase + i);
2762 if (i % 4 == 0)
2763 snd_iprintf(buffer, "\n%02x:", i);
2764 snd_iprintf(buffer, " %02x", v);
2765 }
2766 snd_iprintf(buffer, "\n");
2767}
2768
2769static void snd_cmipci_proc_init(struct cmipci *cm)
2770{
2771 snd_card_ro_proc_new(cm->card, "cmipci", cm, snd_cmipci_proc_read);
2772}
2773
2774static const struct pci_device_id snd_cmipci_ids[] = {
2775 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0},
2776 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0},
2777 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2778 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0},
2779 {PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2780 {0,},
2781};
2782
2783
2784/*
2785 * check chip version and capabilities
2786 * driver name is modified according to the chip model
2787 */
2788static void query_chip(struct cmipci *cm)
2789{
2790 unsigned int detect;
2791
2792 /* check reg 0Ch, bit 24-31 */
2793 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2794 if (! detect) {
2795 /* check reg 08h, bit 24-28 */
2796 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2797 switch (detect) {
2798 case 0:
2799 cm->chip_version = 33;
2800 if (cm->do_soft_ac3)
2801 cm->can_ac3_sw = 1;
2802 else
2803 cm->can_ac3_hw = 1;
2804 break;
2805 case CM_CHIP_037:
2806 cm->chip_version = 37;
2807 cm->can_ac3_hw = 1;
2808 break;
2809 default:
2810 cm->chip_version = 39;
2811 cm->can_ac3_hw = 1;
2812 break;
2813 }
2814 cm->max_channels = 2;
2815 } else {
2816 if (detect & CM_CHIP_039) {
2817 cm->chip_version = 39;
2818 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2819 cm->max_channels = 6;
2820 else
2821 cm->max_channels = 4;
2822 } else if (detect & CM_CHIP_8768) {
2823 cm->chip_version = 68;
2824 cm->max_channels = 8;
2825 cm->can_96k = 1;
2826 } else {
2827 cm->chip_version = 55;
2828 cm->max_channels = 6;
2829 cm->can_96k = 1;
2830 }
2831 cm->can_ac3_hw = 1;
2832 cm->can_multi_ch = 1;
2833 }
2834}
2835
2836#ifdef SUPPORT_JOYSTICK
2837static int snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2838{
2839 static const int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2840 struct gameport *gp;
2841 struct resource *r = NULL;
2842 int i, io_port = 0;
2843
2844 if (joystick_port[dev] == 0)
2845 return -ENODEV;
2846
2847 if (joystick_port[dev] == 1) { /* auto-detect */
2848 for (i = 0; ports[i]; i++) {
2849 io_port = ports[i];
2850 r = devm_request_region(&cm->pci->dev, io_port, 1,
2851 "CMIPCI gameport");
2852 if (r)
2853 break;
2854 }
2855 } else {
2856 io_port = joystick_port[dev];
2857 r = devm_request_region(&cm->pci->dev, io_port, 1,
2858 "CMIPCI gameport");
2859 }
2860
2861 if (!r) {
2862 dev_warn(cm->card->dev, "cannot reserve joystick ports\n");
2863 return -EBUSY;
2864 }
2865
2866 cm->gameport = gp = gameport_allocate_port();
2867 if (!gp) {
2868 dev_err(cm->card->dev, "cannot allocate memory for gameport\n");
2869 return -ENOMEM;
2870 }
2871 gameport_set_name(gp, "C-Media Gameport");
2872 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2873 gameport_set_dev_parent(gp, &cm->pci->dev);
2874 gp->io = io_port;
2875
2876 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2877
2878 gameport_register_port(cm->gameport);
2879
2880 return 0;
2881}
2882
2883static void snd_cmipci_free_gameport(struct cmipci *cm)
2884{
2885 if (cm->gameport) {
2886 gameport_unregister_port(cm->gameport);
2887 cm->gameport = NULL;
2888
2889 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2890 }
2891}
2892#else
2893static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2894static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2895#endif
2896
2897static void snd_cmipci_free(struct snd_card *card)
2898{
2899 struct cmipci *cm = card->private_data;
2900
2901 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2902 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2903 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2904 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2905 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2906 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2907 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2908
2909 /* reset mixer */
2910 snd_cmipci_mixer_write(cm, 0, 0);
2911
2912 snd_cmipci_free_gameport(cm);
2913}
2914
2915static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2916{
2917 long iosynth;
2918 unsigned int val;
2919 struct snd_opl3 *opl3;
2920 int err;
2921
2922 if (!fm_port)
2923 goto disable_fm;
2924
2925 if (cm->chip_version >= 39) {
2926 /* first try FM regs in PCI port range */
2927 iosynth = cm->iobase + CM_REG_FM_PCI;
2928 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2929 OPL3_HW_OPL3, 1, &opl3);
2930 } else {
2931 err = -EIO;
2932 }
2933 if (err < 0) {
2934 /* then try legacy ports */
2935 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2936 iosynth = fm_port;
2937 switch (iosynth) {
2938 case 0x3E8: val |= CM_FMSEL_3E8; break;
2939 case 0x3E0: val |= CM_FMSEL_3E0; break;
2940 case 0x3C8: val |= CM_FMSEL_3C8; break;
2941 case 0x388: val |= CM_FMSEL_388; break;
2942 default:
2943 goto disable_fm;
2944 }
2945 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2946 /* enable FM */
2947 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2948
2949 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2950 OPL3_HW_OPL3, 0, &opl3) < 0) {
2951 dev_err(cm->card->dev,
2952 "no OPL device at %#lx, skipping...\n",
2953 iosynth);
2954 goto disable_fm;
2955 }
2956 }
2957 err = snd_opl3_hwdep_new(opl3, 0, 1, NULL);
2958 if (err < 0) {
2959 dev_err(cm->card->dev, "cannot create OPL3 hwdep\n");
2960 return err;
2961 }
2962 return 0;
2963
2964 disable_fm:
2965 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
2966 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2967 return 0;
2968}
2969
2970static int snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2971 int dev)
2972{
2973 struct cmipci *cm = card->private_data;
2974 int err;
2975 unsigned int val;
2976 long iomidi = 0;
2977 int integrated_midi = 0;
2978 char modelstr[16];
2979 int pcm_index, pcm_spdif_index;
2980 static const struct pci_device_id intel_82437vx[] = {
2981 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
2982 { },
2983 };
2984
2985 err = pcim_enable_device(pci);
2986 if (err < 0)
2987 return err;
2988
2989 spin_lock_init(&cm->reg_lock);
2990 mutex_init(&cm->open_mutex);
2991 cm->device = pci->device;
2992 cm->card = card;
2993 cm->pci = pci;
2994 cm->irq = -1;
2995 cm->channel[0].ch = 0;
2996 cm->channel[1].ch = 1;
2997 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
2998
2999 err = pci_request_regions(pci, card->driver);
3000 if (err < 0)
3001 return err;
3002 cm->iobase = pci_resource_start(pci, 0);
3003
3004 if (devm_request_irq(&pci->dev, pci->irq, snd_cmipci_interrupt,
3005 IRQF_SHARED, KBUILD_MODNAME, cm)) {
3006 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3007 return -EBUSY;
3008 }
3009 cm->irq = pci->irq;
3010 card->sync_irq = cm->irq;
3011 card->private_free = snd_cmipci_free;
3012
3013 pci_set_master(cm->pci);
3014
3015 /*
3016 * check chip version, max channels and capabilities
3017 */
3018
3019 cm->chip_version = 0;
3020 cm->max_channels = 2;
3021 cm->do_soft_ac3 = soft_ac3[dev];
3022
3023 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
3024 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
3025 query_chip(cm);
3026 /* added -MCx suffix for chip supporting multi-channels */
3027 if (cm->can_multi_ch)
3028 sprintf(cm->card->driver + strlen(cm->card->driver),
3029 "-MC%d", cm->max_channels);
3030 else if (cm->can_ac3_sw)
3031 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3032
3033 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3034 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3035
3036#if CM_CH_PLAY == 1
3037 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
3038#else
3039 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
3040#endif
3041
3042 /* initialize codec registers */
3043 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3044 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3045 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
3046 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3047 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3048 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
3049 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3050
3051 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3052 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3053#if CM_CH_PLAY == 1
3054 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3055#else
3056 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3057#endif
3058 if (cm->chip_version) {
3059 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3060 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3061 }
3062 /* Set Bus Master Request */
3063 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3064
3065 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3066 switch (pci->device) {
3067 case PCI_DEVICE_ID_CMEDIA_CM8738:
3068 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3069 if (!pci_dev_present(intel_82437vx))
3070 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3071 break;
3072 default:
3073 break;
3074 }
3075
3076 if (cm->chip_version < 68) {
3077 val = pci->device < 0x110 ? 8338 : 8738;
3078 } else {
3079 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3080 case 0:
3081 val = 8769;
3082 break;
3083 case 2:
3084 val = 8762;
3085 break;
3086 default:
3087 switch ((pci->subsystem_vendor << 16) |
3088 pci->subsystem_device) {
3089 case 0x13f69761:
3090 case 0x584d3741:
3091 case 0x584d3751:
3092 case 0x584d3761:
3093 case 0x584d3771:
3094 case 0x72848384:
3095 val = 8770;
3096 break;
3097 default:
3098 val = 8768;
3099 break;
3100 }
3101 }
3102 }
3103 sprintf(card->shortname, "C-Media CMI%d", val);
3104 if (cm->chip_version < 68)
3105 scnprintf(modelstr, sizeof(modelstr),
3106 " (model %d)", cm->chip_version);
3107 else
3108 modelstr[0] = '\0';
3109 scnprintf(card->longname, sizeof(card->longname),
3110 "%s%s at %#lx, irq %i",
3111 card->shortname, modelstr, cm->iobase, cm->irq);
3112
3113 if (cm->chip_version >= 39) {
3114 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3115 if (val != 0x00 && val != 0xff) {
3116 if (mpu_port[dev])
3117 iomidi = cm->iobase + CM_REG_MPU_PCI;
3118 integrated_midi = 1;
3119 }
3120 }
3121 if (!integrated_midi) {
3122 val = 0;
3123 iomidi = mpu_port[dev];
3124 switch (iomidi) {
3125 case 0x320: val = CM_VMPU_320; break;
3126 case 0x310: val = CM_VMPU_310; break;
3127 case 0x300: val = CM_VMPU_300; break;
3128 case 0x330: val = CM_VMPU_330; break;
3129 default:
3130 iomidi = 0; break;
3131 }
3132 if (iomidi > 0) {
3133 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3134 /* enable UART */
3135 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3136 if (inb(iomidi + 1) == 0xff) {
3137 dev_err(cm->card->dev,
3138 "cannot enable MPU-401 port at %#lx\n",
3139 iomidi);
3140 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3141 CM_UART_EN);
3142 iomidi = 0;
3143 }
3144 }
3145 }
3146
3147 if (cm->chip_version < 68) {
3148 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3149 if (err < 0)
3150 return err;
3151 }
3152
3153 /* reset mixer */
3154 snd_cmipci_mixer_write(cm, 0, 0);
3155
3156 snd_cmipci_proc_init(cm);
3157
3158 /* create pcm devices */
3159 pcm_index = pcm_spdif_index = 0;
3160 err = snd_cmipci_pcm_new(cm, pcm_index);
3161 if (err < 0)
3162 return err;
3163 pcm_index++;
3164 err = snd_cmipci_pcm2_new(cm, pcm_index);
3165 if (err < 0)
3166 return err;
3167 pcm_index++;
3168 if (cm->can_ac3_hw || cm->can_ac3_sw) {
3169 pcm_spdif_index = pcm_index;
3170 err = snd_cmipci_pcm_spdif_new(cm, pcm_index);
3171 if (err < 0)
3172 return err;
3173 }
3174
3175 /* create mixer interface & switches */
3176 err = snd_cmipci_mixer_new(cm, pcm_spdif_index);
3177 if (err < 0)
3178 return err;
3179
3180 if (iomidi > 0) {
3181 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3182 iomidi,
3183 (integrated_midi ?
3184 MPU401_INFO_INTEGRATED : 0) |
3185 MPU401_INFO_IRQ_HOOK,
3186 -1, &cm->rmidi);
3187 if (err < 0)
3188 dev_err(cm->card->dev,
3189 "no UART401 device at 0x%lx\n", iomidi);
3190 }
3191
3192#ifdef USE_VAR48KRATE
3193 for (val = 0; val < ARRAY_SIZE(rates); val++)
3194 snd_cmipci_set_pll(cm, rates[val], val);
3195
3196 /*
3197 * (Re-)Enable external switch spdo_48k
3198 */
3199 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3200#endif /* USE_VAR48KRATE */
3201
3202 if (snd_cmipci_create_gameport(cm, dev) < 0)
3203 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3204
3205 return 0;
3206}
3207
3208/*
3209 */
3210
3211MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3212
3213static int snd_cmipci_probe(struct pci_dev *pci,
3214 const struct pci_device_id *pci_id)
3215{
3216 static int dev;
3217 struct snd_card *card;
3218 int err;
3219
3220 if (dev >= SNDRV_CARDS)
3221 return -ENODEV;
3222 if (! enable[dev]) {
3223 dev++;
3224 return -ENOENT;
3225 }
3226
3227 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
3228 sizeof(struct cmipci), &card);
3229 if (err < 0)
3230 return err;
3231
3232 switch (pci->device) {
3233 case PCI_DEVICE_ID_CMEDIA_CM8738:
3234 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3235 strcpy(card->driver, "CMI8738");
3236 break;
3237 case PCI_DEVICE_ID_CMEDIA_CM8338A:
3238 case PCI_DEVICE_ID_CMEDIA_CM8338B:
3239 strcpy(card->driver, "CMI8338");
3240 break;
3241 default:
3242 strcpy(card->driver, "CMIPCI");
3243 break;
3244 }
3245
3246 err = snd_cmipci_create(card, pci, dev);
3247 if (err < 0)
3248 goto error;
3249
3250 err = snd_card_register(card);
3251 if (err < 0)
3252 goto error;
3253
3254 pci_set_drvdata(pci, card);
3255 dev++;
3256 return 0;
3257
3258 error:
3259 snd_card_free(card);
3260 return err;
3261}
3262
3263#ifdef CONFIG_PM_SLEEP
3264/*
3265 * power management
3266 */
3267static const unsigned char saved_regs[] = {
3268 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3269 CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_AUX_VOL, CM_REG_PLL,
3270 CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3271 CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3272 CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3273};
3274
3275static const unsigned char saved_mixers[] = {
3276 SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3277 SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3278 SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3279 SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3280 SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3281 SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3282 CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3283 SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3284};
3285
3286static int snd_cmipci_suspend(struct device *dev)
3287{
3288 struct snd_card *card = dev_get_drvdata(dev);
3289 struct cmipci *cm = card->private_data;
3290 int i;
3291
3292 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3293
3294 /* save registers */
3295 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3296 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3297 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3298 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3299
3300 /* disable ints */
3301 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3302 return 0;
3303}
3304
3305static int snd_cmipci_resume(struct device *dev)
3306{
3307 struct snd_card *card = dev_get_drvdata(dev);
3308 struct cmipci *cm = card->private_data;
3309 int i;
3310
3311 /* reset / initialize to a sane state */
3312 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3313 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3314 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3315 snd_cmipci_mixer_write(cm, 0, 0);
3316
3317 /* restore registers */
3318 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3319 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3320 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3321 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3322
3323 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3324 return 0;
3325}
3326
3327static SIMPLE_DEV_PM_OPS(snd_cmipci_pm, snd_cmipci_suspend, snd_cmipci_resume);
3328#define SND_CMIPCI_PM_OPS &snd_cmipci_pm
3329#else
3330#define SND_CMIPCI_PM_OPS NULL
3331#endif /* CONFIG_PM_SLEEP */
3332
3333static struct pci_driver cmipci_driver = {
3334 .name = KBUILD_MODNAME,
3335 .id_table = snd_cmipci_ids,
3336 .probe = snd_cmipci_probe,
3337 .driver = {
3338 .pm = SND_CMIPCI_PM_OPS,
3339 },
3340};
3341
3342module_pci_driver(cmipci_driver);