Loading...
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
4 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
5 */
6
7/* Does not work. Warning may block system in capture mode */
8/* #define USE_VAR48KRATE */
9
10#include <linux/io.h>
11#include <linux/delay.h>
12#include <linux/interrupt.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15#include <linux/slab.h>
16#include <linux/gameport.h>
17#include <linux/module.h>
18#include <linux/mutex.h>
19#include <sound/core.h>
20#include <sound/info.h>
21#include <sound/control.h>
22#include <sound/pcm.h>
23#include <sound/rawmidi.h>
24#include <sound/mpu401.h>
25#include <sound/opl3.h>
26#include <sound/sb.h>
27#include <sound/asoundef.h>
28#include <sound/initval.h>
29
30MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
31MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
32MODULE_LICENSE("GPL");
33MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
34 "{C-Media,CMI8738B},"
35 "{C-Media,CMI8338A},"
36 "{C-Media,CMI8338B}}");
37
38#if IS_REACHABLE(CONFIG_GAMEPORT)
39#define SUPPORT_JOYSTICK 1
40#endif
41
42static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
43static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
44static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
45static long mpu_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 1};
46static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
47static bool soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
48#ifdef SUPPORT_JOYSTICK
49static int joystick_port[SNDRV_CARDS];
50#endif
51
52module_param_array(index, int, NULL, 0444);
53MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
54module_param_array(id, charp, NULL, 0444);
55MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
56module_param_array(enable, bool, NULL, 0444);
57MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
58module_param_hw_array(mpu_port, long, ioport, NULL, 0444);
59MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
60module_param_hw_array(fm_port, long, ioport, NULL, 0444);
61MODULE_PARM_DESC(fm_port, "FM port.");
62module_param_array(soft_ac3, bool, NULL, 0444);
63MODULE_PARM_DESC(soft_ac3, "Software-conversion of raw SPDIF packets (model 033 only).");
64#ifdef SUPPORT_JOYSTICK
65module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
66MODULE_PARM_DESC(joystick_port, "Joystick port address.");
67#endif
68
69/*
70 * CM8x38 registers definition
71 */
72
73#define CM_REG_FUNCTRL0 0x00
74#define CM_RST_CH1 0x00080000
75#define CM_RST_CH0 0x00040000
76#define CM_CHEN1 0x00020000 /* ch1: enable */
77#define CM_CHEN0 0x00010000 /* ch0: enable */
78#define CM_PAUSE1 0x00000008 /* ch1: pause */
79#define CM_PAUSE0 0x00000004 /* ch0: pause */
80#define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
81#define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
82
83#define CM_REG_FUNCTRL1 0x04
84#define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
85#define CM_DSFC_SHIFT 13
86#define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
87#define CM_ASFC_SHIFT 10
88#define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
89#define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
90#define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
91#define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
92#define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
93#define CM_BREQ 0x00000010 /* bus master enabled */
94#define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
95#define CM_UART_EN 0x00000004 /* legacy UART */
96#define CM_JYSTK_EN 0x00000002 /* legacy joystick */
97#define CM_ZVPORT 0x00000001 /* ZVPORT */
98
99#define CM_REG_CHFORMAT 0x08
100
101#define CM_CHB3D5C 0x80000000 /* 5,6 channels */
102#define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
103#define CM_CHB3D 0x20000000 /* 4 channels */
104
105#define CM_CHIP_MASK1 0x1f000000
106#define CM_CHIP_037 0x01000000
107#define CM_SETLAT48 0x00800000 /* set latency timer 48h */
108#define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
109#define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
110#define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
111#define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
112#define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
113/* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
114
115#define CM_ADCBITLEN_MASK 0x0000C000
116#define CM_ADCBITLEN_16 0x00000000
117#define CM_ADCBITLEN_15 0x00004000
118#define CM_ADCBITLEN_14 0x00008000
119#define CM_ADCBITLEN_13 0x0000C000
120
121#define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
122#define CM_ADCDACLEN_060 0x00000000
123#define CM_ADCDACLEN_066 0x00001000
124#define CM_ADCDACLEN_130 0x00002000
125#define CM_ADCDACLEN_280 0x00003000
126
127#define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
128#define CM_ADCDLEN_ORIGINAL 0x00000000
129#define CM_ADCDLEN_EXTRA 0x00001000
130#define CM_ADCDLEN_24K 0x00002000
131#define CM_ADCDLEN_WEIGHT 0x00003000
132
133#define CM_CH1_SRATE_176K 0x00000800
134#define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
135#define CM_CH1_SRATE_88K 0x00000400
136#define CM_CH0_SRATE_176K 0x00000200
137#define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
138#define CM_CH0_SRATE_88K 0x00000100
139#define CM_CH0_SRATE_128K 0x00000300
140#define CM_CH0_SRATE_MASK 0x00000300
141
142#define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
143#define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
144#define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
145#define CM_SPDLOCKED 0x00000010
146
147#define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
148#define CM_CH1FMT_SHIFT 2
149#define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
150#define CM_CH0FMT_SHIFT 0
151
152#define CM_REG_INT_HLDCLR 0x0C
153#define CM_CHIP_MASK2 0xff000000
154#define CM_CHIP_8768 0x20000000
155#define CM_CHIP_055 0x08000000
156#define CM_CHIP_039 0x04000000
157#define CM_CHIP_039_6CH 0x01000000
158#define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
159#define CM_TDMA_INT_EN 0x00040000
160#define CM_CH1_INT_EN 0x00020000
161#define CM_CH0_INT_EN 0x00010000
162
163#define CM_REG_INT_STATUS 0x10
164#define CM_INTR 0x80000000
165#define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
166#define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
167#define CM_UARTINT 0x00010000
168#define CM_LTDMAINT 0x00008000
169#define CM_HTDMAINT 0x00004000
170#define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
171#define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
172#define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
173#define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
174#define CM_CH1BUSY 0x00000008
175#define CM_CH0BUSY 0x00000004
176#define CM_CHINT1 0x00000002
177#define CM_CHINT0 0x00000001
178
179#define CM_REG_LEGACY_CTRL 0x14
180#define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
181#define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
182#define CM_VMPU_330 0x00000000
183#define CM_VMPU_320 0x20000000
184#define CM_VMPU_310 0x40000000
185#define CM_VMPU_300 0x60000000
186#define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
187#define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
188#define CM_VSBSEL_220 0x00000000
189#define CM_VSBSEL_240 0x04000000
190#define CM_VSBSEL_260 0x08000000
191#define CM_VSBSEL_280 0x0C000000
192#define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
193#define CM_FMSEL_388 0x00000000
194#define CM_FMSEL_3C8 0x01000000
195#define CM_FMSEL_3E0 0x02000000
196#define CM_FMSEL_3E8 0x03000000
197#define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
198#define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
199#define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
200#define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
201#define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
202#define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
203#define CM_C_EECS 0x00040000
204#define CM_C_EEDI46 0x00020000
205#define CM_C_EECK46 0x00010000
206#define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
207#define CM_CENTR2LIN 0x00004000 /* line-in as center out */
208#define CM_BASE2LIN 0x00002000 /* line-in as bass out */
209#define CM_EXBASEN 0x00001000 /* external bass input enable */
210
211#define CM_REG_MISC_CTRL 0x18
212#define CM_PWD 0x80000000 /* power down */
213#define CM_RESET 0x40000000
214#define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
215#define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
216#define CM_TXVX 0x08000000 /* model 037? */
217#define CM_N4SPK3D 0x04000000 /* copy front to rear */
218#define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
219#define CM_SPDIF48K 0x01000000 /* write */
220#define CM_SPATUS48K 0x01000000 /* read */
221#define CM_ENDBDAC 0x00800000 /* enable double dac */
222#define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
223#define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
224#define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
225#define CM_FM_EN 0x00080000 /* enable legacy FM */
226#define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
227#define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
228#define CM_VIDWPDSB 0x00010000 /* model 037? */
229#define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
230#define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
231#define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
232#define CM_VIDWPPRT 0x00002000 /* model 037? */
233#define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
234#define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
235#define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
236#define CM_ENCENTER 0x00000080
237#define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */
238#define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
239#define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */
240#define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
241#define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
242#define CM_UPDDMA_2048 0x00000000
243#define CM_UPDDMA_1024 0x00000004
244#define CM_UPDDMA_512 0x00000008
245#define CM_UPDDMA_256 0x0000000C
246#define CM_TWAIT_MASK 0x00000003 /* model 037 */
247#define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
248#define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
249
250#define CM_REG_TDMA_POSITION 0x1C
251#define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
252#define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
253
254 /* byte */
255#define CM_REG_MIXER0 0x20
256#define CM_REG_SBVR 0x20 /* write: sb16 version */
257#define CM_REG_DEV 0x20 /* read: hardware device version */
258
259#define CM_REG_MIXER21 0x21
260#define CM_UNKNOWN_21_MASK 0x78 /* ? */
261#define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
262#define CM_PROINV 0x02 /* SBPro left/right channel switching */
263#define CM_X_SB16 0x01 /* SB16 compatible */
264
265#define CM_REG_SB16_DATA 0x22
266#define CM_REG_SB16_ADDR 0x23
267
268#define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
269#define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
270#define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
271#define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
272
273#define CM_REG_MIXER1 0x24
274#define CM_FMMUTE 0x80 /* mute FM */
275#define CM_FMMUTE_SHIFT 7
276#define CM_WSMUTE 0x40 /* mute PCM */
277#define CM_WSMUTE_SHIFT 6
278#define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
279#define CM_REAR2LIN_SHIFT 5
280#define CM_REAR2FRONT 0x10 /* exchange rear/front */
281#define CM_REAR2FRONT_SHIFT 4
282#define CM_WAVEINL 0x08 /* digital wave rec. left chan */
283#define CM_WAVEINL_SHIFT 3
284#define CM_WAVEINR 0x04 /* digical wave rec. right */
285#define CM_WAVEINR_SHIFT 2
286#define CM_X3DEN 0x02 /* 3D surround enable */
287#define CM_X3DEN_SHIFT 1
288#define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
289#define CM_CDPLAY_SHIFT 0
290
291#define CM_REG_MIXER2 0x25
292#define CM_RAUXREN 0x80 /* AUX right capture */
293#define CM_RAUXREN_SHIFT 7
294#define CM_RAUXLEN 0x40 /* AUX left capture */
295#define CM_RAUXLEN_SHIFT 6
296#define CM_VAUXRM 0x20 /* AUX right mute */
297#define CM_VAUXRM_SHIFT 5
298#define CM_VAUXLM 0x10 /* AUX left mute */
299#define CM_VAUXLM_SHIFT 4
300#define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
301#define CM_VADMIC_SHIFT 1
302#define CM_MICGAINZ 0x01 /* mic boost */
303#define CM_MICGAINZ_SHIFT 0
304
305#define CM_REG_MIXER3 0x24
306#define CM_REG_AUX_VOL 0x26
307#define CM_VAUXL_MASK 0xf0
308#define CM_VAUXR_MASK 0x0f
309
310#define CM_REG_MISC 0x27
311#define CM_UNKNOWN_27_MASK 0xd8 /* ? */
312#define CM_XGPO1 0x20
313// #define CM_XGPBIO 0x04
314#define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
315#define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
316#define CM_SPDVALID 0x02 /* spdif input valid check */
317#define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
318
319#define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
320/*
321 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
322 * or identical with AC97 codec?
323 */
324#define CM_REG_EXTERN_CODEC CM_REG_AC97
325
326/*
327 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
328 */
329#define CM_REG_MPU_PCI 0x40
330
331/*
332 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
333 */
334#define CM_REG_FM_PCI 0x50
335
336/*
337 * access from SB-mixer port
338 */
339#define CM_REG_EXTENT_IND 0xf0
340#define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
341#define CM_VPHONE_SHIFT 5
342#define CM_VPHOM 0x10 /* Phone mute control */
343#define CM_VSPKM 0x08 /* Speaker mute control, default high */
344#define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
345#define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
346#define CM_VADMIC3 0x01 /* Mic record boost */
347
348/*
349 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
350 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
351 * unit (readonly?).
352 */
353#define CM_REG_PLL 0xf8
354
355/*
356 * extended registers
357 */
358#define CM_REG_CH0_FRAME1 0x80 /* write: base address */
359#define CM_REG_CH0_FRAME2 0x84 /* read: current address */
360#define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
361#define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
362
363#define CM_REG_EXT_MISC 0x90
364#define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
365#define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
366#define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
367#define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
368#define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
369#define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
370#define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
371#define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
372
373/*
374 * size of i/o region
375 */
376#define CM_EXTENT_CODEC 0x100
377#define CM_EXTENT_MIDI 0x2
378#define CM_EXTENT_SYNTH 0x4
379
380
381/*
382 * channels for playback / capture
383 */
384#define CM_CH_PLAY 0
385#define CM_CH_CAPT 1
386
387/*
388 * flags to check device open/close
389 */
390#define CM_OPEN_NONE 0
391#define CM_OPEN_CH_MASK 0x01
392#define CM_OPEN_DAC 0x10
393#define CM_OPEN_ADC 0x20
394#define CM_OPEN_SPDIF 0x40
395#define CM_OPEN_MCHAN 0x80
396#define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
397#define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
398#define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
399#define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
400#define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
401#define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
402
403
404#if CM_CH_PLAY == 1
405#define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
406#define CM_PLAYBACK_SPDF CM_SPDF_1
407#define CM_CAPTURE_SPDF CM_SPDF_0
408#else
409#define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
410#define CM_PLAYBACK_SPDF CM_SPDF_0
411#define CM_CAPTURE_SPDF CM_SPDF_1
412#endif
413
414
415/*
416 * driver data
417 */
418
419struct cmipci_pcm {
420 struct snd_pcm_substream *substream;
421 u8 running; /* dac/adc running? */
422 u8 fmt; /* format bits */
423 u8 is_dac;
424 u8 needs_silencing;
425 unsigned int dma_size; /* in frames */
426 unsigned int shift;
427 unsigned int ch; /* channel (0/1) */
428 unsigned int offset; /* physical address of the buffer */
429};
430
431/* mixer elements toggled/resumed during ac3 playback */
432struct cmipci_mixer_auto_switches {
433 const char *name; /* switch to toggle */
434 int toggle_on; /* value to change when ac3 mode */
435};
436static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
437 {"PCM Playback Switch", 0},
438 {"IEC958 Output Switch", 1},
439 {"IEC958 Mix Analog", 0},
440 // {"IEC958 Out To DAC", 1}, // no longer used
441 {"IEC958 Loop", 0},
442};
443#define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
444
445struct cmipci {
446 struct snd_card *card;
447
448 struct pci_dev *pci;
449 unsigned int device; /* device ID */
450 int irq;
451
452 unsigned long iobase;
453 unsigned int ctrl; /* FUNCTRL0 current value */
454
455 struct snd_pcm *pcm; /* DAC/ADC PCM */
456 struct snd_pcm *pcm2; /* 2nd DAC */
457 struct snd_pcm *pcm_spdif; /* SPDIF */
458
459 int chip_version;
460 int max_channels;
461 unsigned int can_ac3_sw: 1;
462 unsigned int can_ac3_hw: 1;
463 unsigned int can_multi_ch: 1;
464 unsigned int can_96k: 1; /* samplerate above 48k */
465 unsigned int do_soft_ac3: 1;
466
467 unsigned int spdif_playback_avail: 1; /* spdif ready? */
468 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
469 int spdif_counter; /* for software AC3 */
470
471 unsigned int dig_status;
472 unsigned int dig_pcm_status;
473
474 struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
475
476 int opened[2]; /* open mode */
477 struct mutex open_mutex;
478
479 unsigned int mixer_insensitive: 1;
480 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
481 int mixer_res_status[CM_SAVED_MIXERS];
482
483 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
484
485 /* external MIDI */
486 struct snd_rawmidi *rmidi;
487
488#ifdef SUPPORT_JOYSTICK
489 struct gameport *gameport;
490#endif
491
492 spinlock_t reg_lock;
493
494#ifdef CONFIG_PM_SLEEP
495 unsigned int saved_regs[0x20];
496 unsigned char saved_mixers[0x20];
497#endif
498};
499
500
501/* read/write operations for dword register */
502static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
503{
504 outl(data, cm->iobase + cmd);
505}
506
507static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
508{
509 return inl(cm->iobase + cmd);
510}
511
512/* read/write operations for word register */
513static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
514{
515 outw(data, cm->iobase + cmd);
516}
517
518static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
519{
520 return inw(cm->iobase + cmd);
521}
522
523/* read/write operations for byte register */
524static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
525{
526 outb(data, cm->iobase + cmd);
527}
528
529static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
530{
531 return inb(cm->iobase + cmd);
532}
533
534/* bit operations for dword register */
535static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
536{
537 unsigned int val, oval;
538 val = oval = inl(cm->iobase + cmd);
539 val |= flag;
540 if (val == oval)
541 return 0;
542 outl(val, cm->iobase + cmd);
543 return 1;
544}
545
546static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
547{
548 unsigned int val, oval;
549 val = oval = inl(cm->iobase + cmd);
550 val &= ~flag;
551 if (val == oval)
552 return 0;
553 outl(val, cm->iobase + cmd);
554 return 1;
555}
556
557/* bit operations for byte register */
558static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
559{
560 unsigned char val, oval;
561 val = oval = inb(cm->iobase + cmd);
562 val |= flag;
563 if (val == oval)
564 return 0;
565 outb(val, cm->iobase + cmd);
566 return 1;
567}
568
569static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
570{
571 unsigned char val, oval;
572 val = oval = inb(cm->iobase + cmd);
573 val &= ~flag;
574 if (val == oval)
575 return 0;
576 outb(val, cm->iobase + cmd);
577 return 1;
578}
579
580
581/*
582 * PCM interface
583 */
584
585/*
586 * calculate frequency
587 */
588
589static const unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
590
591static unsigned int snd_cmipci_rate_freq(unsigned int rate)
592{
593 unsigned int i;
594
595 for (i = 0; i < ARRAY_SIZE(rates); i++) {
596 if (rates[i] == rate)
597 return i;
598 }
599 snd_BUG();
600 return 0;
601}
602
603#ifdef USE_VAR48KRATE
604/*
605 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
606 * does it this way .. maybe not. Never get any information from C-Media about
607 * that <werner@suse.de>.
608 */
609static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
610{
611 unsigned int delta, tolerance;
612 int xm, xn, xr;
613
614 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
615 rate <<= 1;
616 *n = -1;
617 if (*r > 0xff)
618 goto out;
619 tolerance = rate*CM_TOLERANCE_RATE;
620
621 for (xn = (1+2); xn < (0x1f+2); xn++) {
622 for (xm = (1+2); xm < (0xff+2); xm++) {
623 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
624
625 if (xr < rate)
626 delta = rate - xr;
627 else
628 delta = xr - rate;
629
630 /*
631 * If we found one, remember this,
632 * and try to find a closer one
633 */
634 if (delta < tolerance) {
635 tolerance = delta;
636 *m = xm - 2;
637 *n = xn - 2;
638 }
639 }
640 }
641out:
642 return (*n > -1);
643}
644
645/*
646 * Program pll register bits, I assume that the 8 registers 0xf8 up to 0xff
647 * are mapped onto the 8 ADC/DAC sampling frequency which can be chosen
648 * at the register CM_REG_FUNCTRL1 (0x04).
649 * Problem: other ways are also possible (any information about that?)
650 */
651static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
652{
653 unsigned int reg = CM_REG_PLL + slot;
654 /*
655 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
656 * for DSFC/ASFC (000 up to 111).
657 */
658
659 /* FIXME: Init (Do we've to set an other register first before programming?) */
660
661 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
662 snd_cmipci_write_b(cm, reg, rate>>8);
663 snd_cmipci_write_b(cm, reg, rate&0xff);
664
665 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
666}
667#endif /* USE_VAR48KRATE */
668
669static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
670 struct snd_pcm_hw_params *hw_params)
671{
672 struct cmipci *cm = snd_pcm_substream_chip(substream);
673 if (params_channels(hw_params) > 2) {
674 mutex_lock(&cm->open_mutex);
675 if (cm->opened[CM_CH_PLAY]) {
676 mutex_unlock(&cm->open_mutex);
677 return -EBUSY;
678 }
679 /* reserve the channel A */
680 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
681 mutex_unlock(&cm->open_mutex);
682 }
683 return 0;
684}
685
686static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
687{
688 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
689 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
690 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
691 udelay(10);
692}
693
694
695/*
696 */
697
698static const unsigned int hw_channels[] = {1, 2, 4, 6, 8};
699static const struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
700 .count = 3,
701 .list = hw_channels,
702 .mask = 0,
703};
704static const struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
705 .count = 4,
706 .list = hw_channels,
707 .mask = 0,
708};
709static const struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
710 .count = 5,
711 .list = hw_channels,
712 .mask = 0,
713};
714
715static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
716{
717 if (channels > 2) {
718 if (!cm->can_multi_ch || !rec->ch)
719 return -EINVAL;
720 if (rec->fmt != 0x03) /* stereo 16bit only */
721 return -EINVAL;
722 }
723
724 if (cm->can_multi_ch) {
725 spin_lock_irq(&cm->reg_lock);
726 if (channels > 2) {
727 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
728 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
729 } else {
730 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
731 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
732 }
733 if (channels == 8)
734 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
735 else
736 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
737 if (channels == 6) {
738 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
739 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
740 } else {
741 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
742 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
743 }
744 if (channels == 4)
745 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
746 else
747 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
748 spin_unlock_irq(&cm->reg_lock);
749 }
750 return 0;
751}
752
753
754/*
755 * prepare playback/capture channel
756 * channel to be used must have been set in rec->ch.
757 */
758static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
759 struct snd_pcm_substream *substream)
760{
761 unsigned int reg, freq, freq_ext, val;
762 unsigned int period_size;
763 struct snd_pcm_runtime *runtime = substream->runtime;
764
765 rec->fmt = 0;
766 rec->shift = 0;
767 if (snd_pcm_format_width(runtime->format) >= 16) {
768 rec->fmt |= 0x02;
769 if (snd_pcm_format_width(runtime->format) > 16)
770 rec->shift++; /* 24/32bit */
771 }
772 if (runtime->channels > 1)
773 rec->fmt |= 0x01;
774 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
775 dev_dbg(cm->card->dev, "cannot set dac channels\n");
776 return -EINVAL;
777 }
778
779 rec->offset = runtime->dma_addr;
780 /* buffer and period sizes in frame */
781 rec->dma_size = runtime->buffer_size << rec->shift;
782 period_size = runtime->period_size << rec->shift;
783 if (runtime->channels > 2) {
784 /* multi-channels */
785 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
786 period_size = (period_size * runtime->channels) / 2;
787 }
788
789 spin_lock_irq(&cm->reg_lock);
790
791 /* set buffer address */
792 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
793 snd_cmipci_write(cm, reg, rec->offset);
794 /* program sample counts */
795 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
796 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
797 snd_cmipci_write_w(cm, reg + 2, period_size - 1);
798
799 /* set adc/dac flag */
800 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
801 if (rec->is_dac)
802 cm->ctrl &= ~val;
803 else
804 cm->ctrl |= val;
805 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
806 /* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */
807
808 /* set sample rate */
809 freq = 0;
810 freq_ext = 0;
811 if (runtime->rate > 48000)
812 switch (runtime->rate) {
813 case 88200: freq_ext = CM_CH0_SRATE_88K; break;
814 case 96000: freq_ext = CM_CH0_SRATE_96K; break;
815 case 128000: freq_ext = CM_CH0_SRATE_128K; break;
816 default: snd_BUG(); break;
817 }
818 else
819 freq = snd_cmipci_rate_freq(runtime->rate);
820 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
821 if (rec->ch) {
822 val &= ~CM_DSFC_MASK;
823 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
824 } else {
825 val &= ~CM_ASFC_MASK;
826 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
827 }
828 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
829 dev_dbg(cm->card->dev, "functrl1 = %08x\n", val);
830
831 /* set format */
832 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
833 if (rec->ch) {
834 val &= ~CM_CH1FMT_MASK;
835 val |= rec->fmt << CM_CH1FMT_SHIFT;
836 } else {
837 val &= ~CM_CH0FMT_MASK;
838 val |= rec->fmt << CM_CH0FMT_SHIFT;
839 }
840 if (cm->can_96k) {
841 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
842 val |= freq_ext << (rec->ch * 2);
843 }
844 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
845 dev_dbg(cm->card->dev, "chformat = %08x\n", val);
846
847 if (!rec->is_dac && cm->chip_version) {
848 if (runtime->rate > 44100)
849 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
850 else
851 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
852 }
853
854 rec->running = 0;
855 spin_unlock_irq(&cm->reg_lock);
856
857 return 0;
858}
859
860/*
861 * PCM trigger/stop
862 */
863static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
864 int cmd)
865{
866 unsigned int inthld, chen, reset, pause;
867 int result = 0;
868
869 inthld = CM_CH0_INT_EN << rec->ch;
870 chen = CM_CHEN0 << rec->ch;
871 reset = CM_RST_CH0 << rec->ch;
872 pause = CM_PAUSE0 << rec->ch;
873
874 spin_lock(&cm->reg_lock);
875 switch (cmd) {
876 case SNDRV_PCM_TRIGGER_START:
877 rec->running = 1;
878 /* set interrupt */
879 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
880 cm->ctrl |= chen;
881 /* enable channel */
882 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
883 dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl);
884 break;
885 case SNDRV_PCM_TRIGGER_STOP:
886 rec->running = 0;
887 /* disable interrupt */
888 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
889 /* reset */
890 cm->ctrl &= ~chen;
891 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
892 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
893 rec->needs_silencing = rec->is_dac;
894 break;
895 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
896 case SNDRV_PCM_TRIGGER_SUSPEND:
897 cm->ctrl |= pause;
898 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
899 break;
900 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
901 case SNDRV_PCM_TRIGGER_RESUME:
902 cm->ctrl &= ~pause;
903 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
904 break;
905 default:
906 result = -EINVAL;
907 break;
908 }
909 spin_unlock(&cm->reg_lock);
910 return result;
911}
912
913/*
914 * return the current pointer
915 */
916static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
917 struct snd_pcm_substream *substream)
918{
919 size_t ptr;
920 unsigned int reg, rem, tries;
921
922 if (!rec->running)
923 return 0;
924#if 1 // this seems better..
925 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
926 for (tries = 0; tries < 3; tries++) {
927 rem = snd_cmipci_read_w(cm, reg);
928 if (rem < rec->dma_size)
929 goto ok;
930 }
931 dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem);
932 return SNDRV_PCM_POS_XRUN;
933ok:
934 ptr = (rec->dma_size - (rem + 1)) >> rec->shift;
935#else
936 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
937 ptr = snd_cmipci_read(cm, reg) - rec->offset;
938 ptr = bytes_to_frames(substream->runtime, ptr);
939#endif
940 if (substream->runtime->channels > 2)
941 ptr = (ptr * 2) / substream->runtime->channels;
942 return ptr;
943}
944
945/*
946 * playback
947 */
948
949static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
950 int cmd)
951{
952 struct cmipci *cm = snd_pcm_substream_chip(substream);
953 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
954}
955
956static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
957{
958 struct cmipci *cm = snd_pcm_substream_chip(substream);
959 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
960}
961
962
963
964/*
965 * capture
966 */
967
968static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
969 int cmd)
970{
971 struct cmipci *cm = snd_pcm_substream_chip(substream);
972 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
973}
974
975static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
976{
977 struct cmipci *cm = snd_pcm_substream_chip(substream);
978 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
979}
980
981
982/*
983 * hw preparation for spdif
984 */
985
986static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
987 struct snd_ctl_elem_info *uinfo)
988{
989 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
990 uinfo->count = 1;
991 return 0;
992}
993
994static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
995 struct snd_ctl_elem_value *ucontrol)
996{
997 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
998 int i;
999
1000 spin_lock_irq(&chip->reg_lock);
1001 for (i = 0; i < 4; i++)
1002 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
1003 spin_unlock_irq(&chip->reg_lock);
1004 return 0;
1005}
1006
1007static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1008 struct snd_ctl_elem_value *ucontrol)
1009{
1010 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1011 int i, change;
1012 unsigned int val;
1013
1014 val = 0;
1015 spin_lock_irq(&chip->reg_lock);
1016 for (i = 0; i < 4; i++)
1017 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1018 change = val != chip->dig_status;
1019 chip->dig_status = val;
1020 spin_unlock_irq(&chip->reg_lock);
1021 return change;
1022}
1023
1024static const struct snd_kcontrol_new snd_cmipci_spdif_default =
1025{
1026 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1027 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1028 .info = snd_cmipci_spdif_default_info,
1029 .get = snd_cmipci_spdif_default_get,
1030 .put = snd_cmipci_spdif_default_put
1031};
1032
1033static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1034 struct snd_ctl_elem_info *uinfo)
1035{
1036 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1037 uinfo->count = 1;
1038 return 0;
1039}
1040
1041static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1042 struct snd_ctl_elem_value *ucontrol)
1043{
1044 ucontrol->value.iec958.status[0] = 0xff;
1045 ucontrol->value.iec958.status[1] = 0xff;
1046 ucontrol->value.iec958.status[2] = 0xff;
1047 ucontrol->value.iec958.status[3] = 0xff;
1048 return 0;
1049}
1050
1051static const struct snd_kcontrol_new snd_cmipci_spdif_mask =
1052{
1053 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1054 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1055 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1056 .info = snd_cmipci_spdif_mask_info,
1057 .get = snd_cmipci_spdif_mask_get,
1058};
1059
1060static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1061 struct snd_ctl_elem_info *uinfo)
1062{
1063 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1064 uinfo->count = 1;
1065 return 0;
1066}
1067
1068static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1069 struct snd_ctl_elem_value *ucontrol)
1070{
1071 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1072 int i;
1073
1074 spin_lock_irq(&chip->reg_lock);
1075 for (i = 0; i < 4; i++)
1076 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1077 spin_unlock_irq(&chip->reg_lock);
1078 return 0;
1079}
1080
1081static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1082 struct snd_ctl_elem_value *ucontrol)
1083{
1084 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1085 int i, change;
1086 unsigned int val;
1087
1088 val = 0;
1089 spin_lock_irq(&chip->reg_lock);
1090 for (i = 0; i < 4; i++)
1091 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1092 change = val != chip->dig_pcm_status;
1093 chip->dig_pcm_status = val;
1094 spin_unlock_irq(&chip->reg_lock);
1095 return change;
1096}
1097
1098static const struct snd_kcontrol_new snd_cmipci_spdif_stream =
1099{
1100 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1101 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1102 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1103 .info = snd_cmipci_spdif_stream_info,
1104 .get = snd_cmipci_spdif_stream_get,
1105 .put = snd_cmipci_spdif_stream_put
1106};
1107
1108/*
1109 */
1110
1111/* save mixer setting and mute for AC3 playback */
1112static int save_mixer_state(struct cmipci *cm)
1113{
1114 if (! cm->mixer_insensitive) {
1115 struct snd_ctl_elem_value *val;
1116 unsigned int i;
1117
1118 val = kmalloc(sizeof(*val), GFP_KERNEL);
1119 if (!val)
1120 return -ENOMEM;
1121 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1122 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1123 if (ctl) {
1124 int event;
1125 memset(val, 0, sizeof(*val));
1126 ctl->get(ctl, val);
1127 cm->mixer_res_status[i] = val->value.integer.value[0];
1128 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1129 event = SNDRV_CTL_EVENT_MASK_INFO;
1130 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1131 ctl->put(ctl, val); /* toggle */
1132 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1133 }
1134 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1135 snd_ctl_notify(cm->card, event, &ctl->id);
1136 }
1137 }
1138 kfree(val);
1139 cm->mixer_insensitive = 1;
1140 }
1141 return 0;
1142}
1143
1144
1145/* restore the previously saved mixer status */
1146static void restore_mixer_state(struct cmipci *cm)
1147{
1148 if (cm->mixer_insensitive) {
1149 struct snd_ctl_elem_value *val;
1150 unsigned int i;
1151
1152 val = kmalloc(sizeof(*val), GFP_KERNEL);
1153 if (!val)
1154 return;
1155 cm->mixer_insensitive = 0; /* at first clear this;
1156 otherwise the changes will be ignored */
1157 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1158 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1159 if (ctl) {
1160 int event;
1161
1162 memset(val, 0, sizeof(*val));
1163 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1164 ctl->get(ctl, val);
1165 event = SNDRV_CTL_EVENT_MASK_INFO;
1166 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1167 val->value.integer.value[0] = cm->mixer_res_status[i];
1168 ctl->put(ctl, val);
1169 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1170 }
1171 snd_ctl_notify(cm->card, event, &ctl->id);
1172 }
1173 }
1174 kfree(val);
1175 }
1176}
1177
1178/* spinlock held! */
1179static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1180{
1181 if (do_ac3) {
1182 /* AC3EN for 037 */
1183 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1184 /* AC3EN for 039 */
1185 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1186
1187 if (cm->can_ac3_hw) {
1188 /* SPD24SEL for 037, 0x02 */
1189 /* SPD24SEL for 039, 0x20, but cannot be set */
1190 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1191 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1192 } else { /* can_ac3_sw */
1193 /* SPD32SEL for 037 & 039, 0x20 */
1194 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1195 /* set 176K sample rate to fix 033 HW bug */
1196 if (cm->chip_version == 33) {
1197 if (rate >= 48000) {
1198 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1199 } else {
1200 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1201 }
1202 }
1203 }
1204
1205 } else {
1206 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1207 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1208
1209 if (cm->can_ac3_hw) {
1210 /* chip model >= 37 */
1211 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1212 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1213 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1214 } else {
1215 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1216 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1217 }
1218 } else {
1219 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1220 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1221 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1222 }
1223 }
1224}
1225
1226static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1227{
1228 int rate, err;
1229
1230 rate = subs->runtime->rate;
1231
1232 if (up && do_ac3)
1233 if ((err = save_mixer_state(cm)) < 0)
1234 return err;
1235
1236 spin_lock_irq(&cm->reg_lock);
1237 cm->spdif_playback_avail = up;
1238 if (up) {
1239 /* they are controlled via "IEC958 Output Switch" */
1240 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1241 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1242 if (cm->spdif_playback_enabled)
1243 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1244 setup_ac3(cm, subs, do_ac3, rate);
1245
1246 if (rate == 48000 || rate == 96000)
1247 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1248 else
1249 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1250 if (rate > 48000)
1251 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1252 else
1253 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1254 } else {
1255 /* they are controlled via "IEC958 Output Switch" */
1256 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1257 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1258 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1259 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1260 setup_ac3(cm, subs, 0, 0);
1261 }
1262 spin_unlock_irq(&cm->reg_lock);
1263 return 0;
1264}
1265
1266
1267/*
1268 * preparation
1269 */
1270
1271/* playback - enable spdif only on the certain condition */
1272static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1273{
1274 struct cmipci *cm = snd_pcm_substream_chip(substream);
1275 int rate = substream->runtime->rate;
1276 int err, do_spdif, do_ac3 = 0;
1277
1278 do_spdif = (rate >= 44100 && rate <= 96000 &&
1279 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1280 substream->runtime->channels == 2);
1281 if (do_spdif && cm->can_ac3_hw)
1282 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1283 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1284 return err;
1285 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1286}
1287
1288/* playback (via device #2) - enable spdif always */
1289static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1290{
1291 struct cmipci *cm = snd_pcm_substream_chip(substream);
1292 int err, do_ac3;
1293
1294 if (cm->can_ac3_hw)
1295 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1296 else
1297 do_ac3 = 1; /* doesn't matter */
1298 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1299 return err;
1300 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1301}
1302
1303/*
1304 * Apparently, the samples last played on channel A stay in some buffer, even
1305 * after the channel is reset, and get added to the data for the rear DACs when
1306 * playing a multichannel stream on channel B. This is likely to generate
1307 * wraparounds and thus distortions.
1308 * To avoid this, we play at least one zero sample after the actual stream has
1309 * stopped.
1310 */
1311static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1312{
1313 struct snd_pcm_runtime *runtime = rec->substream->runtime;
1314 unsigned int reg, val;
1315
1316 if (rec->needs_silencing && runtime && runtime->dma_area) {
1317 /* set up a small silence buffer */
1318 memset(runtime->dma_area, 0, PAGE_SIZE);
1319 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1320 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1321 snd_cmipci_write(cm, reg, val);
1322
1323 /* configure for 16 bits, 2 channels, 8 kHz */
1324 if (runtime->channels > 2)
1325 set_dac_channels(cm, rec, 2);
1326 spin_lock_irq(&cm->reg_lock);
1327 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1328 val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1329 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1330 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1331 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1332 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1333 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1334 if (cm->can_96k)
1335 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
1336 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1337
1338 /* start stream (we don't need interrupts) */
1339 cm->ctrl |= CM_CHEN0 << rec->ch;
1340 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1341 spin_unlock_irq(&cm->reg_lock);
1342
1343 msleep(1);
1344
1345 /* stop and reset stream */
1346 spin_lock_irq(&cm->reg_lock);
1347 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1348 val = CM_RST_CH0 << rec->ch;
1349 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1350 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1351 spin_unlock_irq(&cm->reg_lock);
1352
1353 rec->needs_silencing = 0;
1354 }
1355}
1356
1357static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1358{
1359 struct cmipci *cm = snd_pcm_substream_chip(substream);
1360 setup_spdif_playback(cm, substream, 0, 0);
1361 restore_mixer_state(cm);
1362 snd_cmipci_silence_hack(cm, &cm->channel[0]);
1363 return 0;
1364}
1365
1366static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1367{
1368 struct cmipci *cm = snd_pcm_substream_chip(substream);
1369 snd_cmipci_silence_hack(cm, &cm->channel[1]);
1370 return 0;
1371}
1372
1373/* capture */
1374static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1375{
1376 struct cmipci *cm = snd_pcm_substream_chip(substream);
1377 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1378}
1379
1380/* capture with spdif (via device #2) */
1381static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1382{
1383 struct cmipci *cm = snd_pcm_substream_chip(substream);
1384
1385 spin_lock_irq(&cm->reg_lock);
1386 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1387 if (cm->can_96k) {
1388 if (substream->runtime->rate > 48000)
1389 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1390 else
1391 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1392 }
1393 if (snd_pcm_format_width(substream->runtime->format) > 16)
1394 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1395 else
1396 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1397
1398 spin_unlock_irq(&cm->reg_lock);
1399
1400 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1401}
1402
1403static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1404{
1405 struct cmipci *cm = snd_pcm_substream_chip(subs);
1406
1407 spin_lock_irq(&cm->reg_lock);
1408 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1409 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1410 spin_unlock_irq(&cm->reg_lock);
1411
1412 return 0;
1413}
1414
1415
1416/*
1417 * interrupt handler
1418 */
1419static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1420{
1421 struct cmipci *cm = dev_id;
1422 unsigned int status, mask = 0;
1423
1424 /* fastpath out, to ease interrupt sharing */
1425 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1426 if (!(status & CM_INTR))
1427 return IRQ_NONE;
1428
1429 /* acknowledge interrupt */
1430 spin_lock(&cm->reg_lock);
1431 if (status & CM_CHINT0)
1432 mask |= CM_CH0_INT_EN;
1433 if (status & CM_CHINT1)
1434 mask |= CM_CH1_INT_EN;
1435 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1436 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1437 spin_unlock(&cm->reg_lock);
1438
1439 if (cm->rmidi && (status & CM_UARTINT))
1440 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1441
1442 if (cm->pcm) {
1443 if ((status & CM_CHINT0) && cm->channel[0].running)
1444 snd_pcm_period_elapsed(cm->channel[0].substream);
1445 if ((status & CM_CHINT1) && cm->channel[1].running)
1446 snd_pcm_period_elapsed(cm->channel[1].substream);
1447 }
1448 return IRQ_HANDLED;
1449}
1450
1451/*
1452 * h/w infos
1453 */
1454
1455/* playback on channel A */
1456static const struct snd_pcm_hardware snd_cmipci_playback =
1457{
1458 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1459 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1460 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1461 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1462 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1463 .rate_min = 5512,
1464 .rate_max = 48000,
1465 .channels_min = 1,
1466 .channels_max = 2,
1467 .buffer_bytes_max = (128*1024),
1468 .period_bytes_min = 64,
1469 .period_bytes_max = (128*1024),
1470 .periods_min = 2,
1471 .periods_max = 1024,
1472 .fifo_size = 0,
1473};
1474
1475/* capture on channel B */
1476static const struct snd_pcm_hardware snd_cmipci_capture =
1477{
1478 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1479 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1480 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1481 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1482 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1483 .rate_min = 5512,
1484 .rate_max = 48000,
1485 .channels_min = 1,
1486 .channels_max = 2,
1487 .buffer_bytes_max = (128*1024),
1488 .period_bytes_min = 64,
1489 .period_bytes_max = (128*1024),
1490 .periods_min = 2,
1491 .periods_max = 1024,
1492 .fifo_size = 0,
1493};
1494
1495/* playback on channel B - stereo 16bit only? */
1496static const struct snd_pcm_hardware snd_cmipci_playback2 =
1497{
1498 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1499 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1500 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1501 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1502 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1503 .rate_min = 5512,
1504 .rate_max = 48000,
1505 .channels_min = 2,
1506 .channels_max = 2,
1507 .buffer_bytes_max = (128*1024),
1508 .period_bytes_min = 64,
1509 .period_bytes_max = (128*1024),
1510 .periods_min = 2,
1511 .periods_max = 1024,
1512 .fifo_size = 0,
1513};
1514
1515/* spdif playback on channel A */
1516static const struct snd_pcm_hardware snd_cmipci_playback_spdif =
1517{
1518 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1519 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1520 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1521 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1522 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1523 .rate_min = 44100,
1524 .rate_max = 48000,
1525 .channels_min = 2,
1526 .channels_max = 2,
1527 .buffer_bytes_max = (128*1024),
1528 .period_bytes_min = 64,
1529 .period_bytes_max = (128*1024),
1530 .periods_min = 2,
1531 .periods_max = 1024,
1532 .fifo_size = 0,
1533};
1534
1535/* spdif playback on channel A (32bit, IEC958 subframes) */
1536static const struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1537{
1538 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1539 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1540 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1541 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1542 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1543 .rate_min = 44100,
1544 .rate_max = 48000,
1545 .channels_min = 2,
1546 .channels_max = 2,
1547 .buffer_bytes_max = (128*1024),
1548 .period_bytes_min = 64,
1549 .period_bytes_max = (128*1024),
1550 .periods_min = 2,
1551 .periods_max = 1024,
1552 .fifo_size = 0,
1553};
1554
1555/* spdif capture on channel B */
1556static const struct snd_pcm_hardware snd_cmipci_capture_spdif =
1557{
1558 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1559 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1560 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1561 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1562 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1563 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1564 .rate_min = 44100,
1565 .rate_max = 48000,
1566 .channels_min = 2,
1567 .channels_max = 2,
1568 .buffer_bytes_max = (128*1024),
1569 .period_bytes_min = 64,
1570 .period_bytes_max = (128*1024),
1571 .periods_min = 2,
1572 .periods_max = 1024,
1573 .fifo_size = 0,
1574};
1575
1576static const unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050,
1577 32000, 44100, 48000, 88200, 96000, 128000 };
1578static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1579 .count = ARRAY_SIZE(rate_constraints),
1580 .list = rate_constraints,
1581 .mask = 0,
1582};
1583
1584/*
1585 * check device open/close
1586 */
1587static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1588{
1589 int ch = mode & CM_OPEN_CH_MASK;
1590
1591 /* FIXME: a file should wait until the device becomes free
1592 * when it's opened on blocking mode. however, since the current
1593 * pcm framework doesn't pass file pointer before actually opened,
1594 * we can't know whether blocking mode or not in open callback..
1595 */
1596 mutex_lock(&cm->open_mutex);
1597 if (cm->opened[ch]) {
1598 mutex_unlock(&cm->open_mutex);
1599 return -EBUSY;
1600 }
1601 cm->opened[ch] = mode;
1602 cm->channel[ch].substream = subs;
1603 if (! (mode & CM_OPEN_DAC)) {
1604 /* disable dual DAC mode */
1605 cm->channel[ch].is_dac = 0;
1606 spin_lock_irq(&cm->reg_lock);
1607 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1608 spin_unlock_irq(&cm->reg_lock);
1609 }
1610 mutex_unlock(&cm->open_mutex);
1611 return 0;
1612}
1613
1614static void close_device_check(struct cmipci *cm, int mode)
1615{
1616 int ch = mode & CM_OPEN_CH_MASK;
1617
1618 mutex_lock(&cm->open_mutex);
1619 if (cm->opened[ch] == mode) {
1620 if (cm->channel[ch].substream) {
1621 snd_cmipci_ch_reset(cm, ch);
1622 cm->channel[ch].running = 0;
1623 cm->channel[ch].substream = NULL;
1624 }
1625 cm->opened[ch] = 0;
1626 if (! cm->channel[ch].is_dac) {
1627 /* enable dual DAC mode again */
1628 cm->channel[ch].is_dac = 1;
1629 spin_lock_irq(&cm->reg_lock);
1630 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1631 spin_unlock_irq(&cm->reg_lock);
1632 }
1633 }
1634 mutex_unlock(&cm->open_mutex);
1635}
1636
1637/*
1638 */
1639
1640static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1641{
1642 struct cmipci *cm = snd_pcm_substream_chip(substream);
1643 struct snd_pcm_runtime *runtime = substream->runtime;
1644 int err;
1645
1646 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1647 return err;
1648 runtime->hw = snd_cmipci_playback;
1649 if (cm->chip_version == 68) {
1650 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1651 SNDRV_PCM_RATE_96000;
1652 runtime->hw.rate_max = 96000;
1653 } else if (cm->chip_version == 55) {
1654 err = snd_pcm_hw_constraint_list(runtime, 0,
1655 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1656 if (err < 0)
1657 return err;
1658 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1659 runtime->hw.rate_max = 128000;
1660 }
1661 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1662 cm->dig_pcm_status = cm->dig_status;
1663 return 0;
1664}
1665
1666static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1667{
1668 struct cmipci *cm = snd_pcm_substream_chip(substream);
1669 struct snd_pcm_runtime *runtime = substream->runtime;
1670 int err;
1671
1672 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1673 return err;
1674 runtime->hw = snd_cmipci_capture;
1675 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1676 runtime->hw.rate_min = 41000;
1677 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1678 } else if (cm->chip_version == 55) {
1679 err = snd_pcm_hw_constraint_list(runtime, 0,
1680 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1681 if (err < 0)
1682 return err;
1683 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1684 runtime->hw.rate_max = 128000;
1685 }
1686 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1687 return 0;
1688}
1689
1690static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1691{
1692 struct cmipci *cm = snd_pcm_substream_chip(substream);
1693 struct snd_pcm_runtime *runtime = substream->runtime;
1694 int err;
1695
1696 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1697 return err;
1698 runtime->hw = snd_cmipci_playback2;
1699 mutex_lock(&cm->open_mutex);
1700 if (! cm->opened[CM_CH_PLAY]) {
1701 if (cm->can_multi_ch) {
1702 runtime->hw.channels_max = cm->max_channels;
1703 if (cm->max_channels == 4)
1704 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1705 else if (cm->max_channels == 6)
1706 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1707 else if (cm->max_channels == 8)
1708 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1709 }
1710 }
1711 mutex_unlock(&cm->open_mutex);
1712 if (cm->chip_version == 68) {
1713 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1714 SNDRV_PCM_RATE_96000;
1715 runtime->hw.rate_max = 96000;
1716 } else if (cm->chip_version == 55) {
1717 err = snd_pcm_hw_constraint_list(runtime, 0,
1718 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1719 if (err < 0)
1720 return err;
1721 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1722 runtime->hw.rate_max = 128000;
1723 }
1724 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1725 return 0;
1726}
1727
1728static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1729{
1730 struct cmipci *cm = snd_pcm_substream_chip(substream);
1731 struct snd_pcm_runtime *runtime = substream->runtime;
1732 int err;
1733
1734 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1735 return err;
1736 if (cm->can_ac3_hw) {
1737 runtime->hw = snd_cmipci_playback_spdif;
1738 if (cm->chip_version >= 37) {
1739 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1740 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1741 }
1742 if (cm->can_96k) {
1743 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1744 SNDRV_PCM_RATE_96000;
1745 runtime->hw.rate_max = 96000;
1746 }
1747 } else {
1748 runtime->hw = snd_cmipci_playback_iec958_subframe;
1749 }
1750 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1751 cm->dig_pcm_status = cm->dig_status;
1752 return 0;
1753}
1754
1755static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1756{
1757 struct cmipci *cm = snd_pcm_substream_chip(substream);
1758 struct snd_pcm_runtime *runtime = substream->runtime;
1759 int err;
1760
1761 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1762 return err;
1763 runtime->hw = snd_cmipci_capture_spdif;
1764 if (cm->can_96k && !(cm->chip_version == 68)) {
1765 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1766 SNDRV_PCM_RATE_96000;
1767 runtime->hw.rate_max = 96000;
1768 }
1769 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1770 return 0;
1771}
1772
1773
1774/*
1775 */
1776
1777static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1778{
1779 struct cmipci *cm = snd_pcm_substream_chip(substream);
1780 close_device_check(cm, CM_OPEN_PLAYBACK);
1781 return 0;
1782}
1783
1784static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1785{
1786 struct cmipci *cm = snd_pcm_substream_chip(substream);
1787 close_device_check(cm, CM_OPEN_CAPTURE);
1788 return 0;
1789}
1790
1791static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1792{
1793 struct cmipci *cm = snd_pcm_substream_chip(substream);
1794 close_device_check(cm, CM_OPEN_PLAYBACK2);
1795 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1796 return 0;
1797}
1798
1799static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1800{
1801 struct cmipci *cm = snd_pcm_substream_chip(substream);
1802 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1803 return 0;
1804}
1805
1806static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1807{
1808 struct cmipci *cm = snd_pcm_substream_chip(substream);
1809 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1810 return 0;
1811}
1812
1813
1814/*
1815 */
1816
1817static const struct snd_pcm_ops snd_cmipci_playback_ops = {
1818 .open = snd_cmipci_playback_open,
1819 .close = snd_cmipci_playback_close,
1820 .hw_free = snd_cmipci_playback_hw_free,
1821 .prepare = snd_cmipci_playback_prepare,
1822 .trigger = snd_cmipci_playback_trigger,
1823 .pointer = snd_cmipci_playback_pointer,
1824};
1825
1826static const struct snd_pcm_ops snd_cmipci_capture_ops = {
1827 .open = snd_cmipci_capture_open,
1828 .close = snd_cmipci_capture_close,
1829 .prepare = snd_cmipci_capture_prepare,
1830 .trigger = snd_cmipci_capture_trigger,
1831 .pointer = snd_cmipci_capture_pointer,
1832};
1833
1834static const struct snd_pcm_ops snd_cmipci_playback2_ops = {
1835 .open = snd_cmipci_playback2_open,
1836 .close = snd_cmipci_playback2_close,
1837 .hw_params = snd_cmipci_playback2_hw_params,
1838 .hw_free = snd_cmipci_playback2_hw_free,
1839 .prepare = snd_cmipci_capture_prepare, /* channel B */
1840 .trigger = snd_cmipci_capture_trigger, /* channel B */
1841 .pointer = snd_cmipci_capture_pointer, /* channel B */
1842};
1843
1844static const struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1845 .open = snd_cmipci_playback_spdif_open,
1846 .close = snd_cmipci_playback_spdif_close,
1847 .hw_free = snd_cmipci_playback_hw_free,
1848 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1849 .trigger = snd_cmipci_playback_trigger,
1850 .pointer = snd_cmipci_playback_pointer,
1851};
1852
1853static const struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1854 .open = snd_cmipci_capture_spdif_open,
1855 .close = snd_cmipci_capture_spdif_close,
1856 .hw_free = snd_cmipci_capture_spdif_hw_free,
1857 .prepare = snd_cmipci_capture_spdif_prepare,
1858 .trigger = snd_cmipci_capture_trigger,
1859 .pointer = snd_cmipci_capture_pointer,
1860};
1861
1862
1863/*
1864 */
1865
1866static int snd_cmipci_pcm_new(struct cmipci *cm, int device)
1867{
1868 struct snd_pcm *pcm;
1869 int err;
1870
1871 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1872 if (err < 0)
1873 return err;
1874
1875 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1876 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1877
1878 pcm->private_data = cm;
1879 pcm->info_flags = 0;
1880 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1881 cm->pcm = pcm;
1882
1883 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1884 &cm->pci->dev, 64*1024, 128*1024);
1885
1886 return 0;
1887}
1888
1889static int snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1890{
1891 struct snd_pcm *pcm;
1892 int err;
1893
1894 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1895 if (err < 0)
1896 return err;
1897
1898 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1899
1900 pcm->private_data = cm;
1901 pcm->info_flags = 0;
1902 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1903 cm->pcm2 = pcm;
1904
1905 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1906 &cm->pci->dev, 64*1024, 128*1024);
1907
1908 return 0;
1909}
1910
1911static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1912{
1913 struct snd_pcm *pcm;
1914 int err;
1915
1916 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1917 if (err < 0)
1918 return err;
1919
1920 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1921 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1922
1923 pcm->private_data = cm;
1924 pcm->info_flags = 0;
1925 strcpy(pcm->name, "C-Media PCI IEC958");
1926 cm->pcm_spdif = pcm;
1927
1928 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1929 &cm->pci->dev, 64*1024, 128*1024);
1930
1931 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1932 snd_pcm_alt_chmaps, cm->max_channels, 0,
1933 NULL);
1934 if (err < 0)
1935 return err;
1936
1937 return 0;
1938}
1939
1940/*
1941 * mixer interface:
1942 * - CM8338/8738 has a compatible mixer interface with SB16, but
1943 * lack of some elements like tone control, i/o gain and AGC.
1944 * - Access to native registers:
1945 * - A 3D switch
1946 * - Output mute switches
1947 */
1948
1949static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1950{
1951 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1952 outb(data, s->iobase + CM_REG_SB16_DATA);
1953}
1954
1955static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1956{
1957 unsigned char v;
1958
1959 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1960 v = inb(s->iobase + CM_REG_SB16_DATA);
1961 return v;
1962}
1963
1964/*
1965 * general mixer element
1966 */
1967struct cmipci_sb_reg {
1968 unsigned int left_reg, right_reg;
1969 unsigned int left_shift, right_shift;
1970 unsigned int mask;
1971 unsigned int invert: 1;
1972 unsigned int stereo: 1;
1973};
1974
1975#define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1976 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1977
1978#define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1979{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1980 .info = snd_cmipci_info_volume, \
1981 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1982 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1983}
1984
1985#define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1986#define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1987#define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1988#define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1989
1990static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
1991{
1992 r->left_reg = val & 0xff;
1993 r->right_reg = (val >> 8) & 0xff;
1994 r->left_shift = (val >> 16) & 0x07;
1995 r->right_shift = (val >> 19) & 0x07;
1996 r->invert = (val >> 22) & 1;
1997 r->stereo = (val >> 23) & 1;
1998 r->mask = (val >> 24) & 0xff;
1999}
2000
2001static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
2002 struct snd_ctl_elem_info *uinfo)
2003{
2004 struct cmipci_sb_reg reg;
2005
2006 cmipci_sb_reg_decode(®, kcontrol->private_value);
2007 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2008 uinfo->count = reg.stereo + 1;
2009 uinfo->value.integer.min = 0;
2010 uinfo->value.integer.max = reg.mask;
2011 return 0;
2012}
2013
2014static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
2015 struct snd_ctl_elem_value *ucontrol)
2016{
2017 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2018 struct cmipci_sb_reg reg;
2019 int val;
2020
2021 cmipci_sb_reg_decode(®, kcontrol->private_value);
2022 spin_lock_irq(&cm->reg_lock);
2023 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
2024 if (reg.invert)
2025 val = reg.mask - val;
2026 ucontrol->value.integer.value[0] = val;
2027 if (reg.stereo) {
2028 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
2029 if (reg.invert)
2030 val = reg.mask - val;
2031 ucontrol->value.integer.value[1] = val;
2032 }
2033 spin_unlock_irq(&cm->reg_lock);
2034 return 0;
2035}
2036
2037static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
2038 struct snd_ctl_elem_value *ucontrol)
2039{
2040 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2041 struct cmipci_sb_reg reg;
2042 int change;
2043 int left, right, oleft, oright;
2044
2045 cmipci_sb_reg_decode(®, kcontrol->private_value);
2046 left = ucontrol->value.integer.value[0] & reg.mask;
2047 if (reg.invert)
2048 left = reg.mask - left;
2049 left <<= reg.left_shift;
2050 if (reg.stereo) {
2051 right = ucontrol->value.integer.value[1] & reg.mask;
2052 if (reg.invert)
2053 right = reg.mask - right;
2054 right <<= reg.right_shift;
2055 } else
2056 right = 0;
2057 spin_lock_irq(&cm->reg_lock);
2058 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2059 left |= oleft & ~(reg.mask << reg.left_shift);
2060 change = left != oleft;
2061 if (reg.stereo) {
2062 if (reg.left_reg != reg.right_reg) {
2063 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2064 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2065 } else
2066 oright = left;
2067 right |= oright & ~(reg.mask << reg.right_shift);
2068 change |= right != oright;
2069 snd_cmipci_mixer_write(cm, reg.right_reg, right);
2070 } else
2071 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2072 spin_unlock_irq(&cm->reg_lock);
2073 return change;
2074}
2075
2076/*
2077 * input route (left,right) -> (left,right)
2078 */
2079#define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2080{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2081 .info = snd_cmipci_info_input_sw, \
2082 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2083 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2084}
2085
2086static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
2087 struct snd_ctl_elem_info *uinfo)
2088{
2089 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2090 uinfo->count = 4;
2091 uinfo->value.integer.min = 0;
2092 uinfo->value.integer.max = 1;
2093 return 0;
2094}
2095
2096static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2097 struct snd_ctl_elem_value *ucontrol)
2098{
2099 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2100 struct cmipci_sb_reg reg;
2101 int val1, val2;
2102
2103 cmipci_sb_reg_decode(®, kcontrol->private_value);
2104 spin_lock_irq(&cm->reg_lock);
2105 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2106 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2107 spin_unlock_irq(&cm->reg_lock);
2108 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2109 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2110 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2111 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2112 return 0;
2113}
2114
2115static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2116 struct snd_ctl_elem_value *ucontrol)
2117{
2118 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2119 struct cmipci_sb_reg reg;
2120 int change;
2121 int val1, val2, oval1, oval2;
2122
2123 cmipci_sb_reg_decode(®, kcontrol->private_value);
2124 spin_lock_irq(&cm->reg_lock);
2125 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2126 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2127 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2128 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2129 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2130 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2131 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2132 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2133 change = val1 != oval1 || val2 != oval2;
2134 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2135 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2136 spin_unlock_irq(&cm->reg_lock);
2137 return change;
2138}
2139
2140/*
2141 * native mixer switches/volumes
2142 */
2143
2144#define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2145{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2146 .info = snd_cmipci_info_native_mixer, \
2147 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2148 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2149}
2150
2151#define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2152{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2153 .info = snd_cmipci_info_native_mixer, \
2154 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2155 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2156}
2157
2158#define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2159{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2160 .info = snd_cmipci_info_native_mixer, \
2161 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2162 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2163}
2164
2165#define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2166{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2167 .info = snd_cmipci_info_native_mixer, \
2168 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2169 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2170}
2171
2172static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2173 struct snd_ctl_elem_info *uinfo)
2174{
2175 struct cmipci_sb_reg reg;
2176
2177 cmipci_sb_reg_decode(®, kcontrol->private_value);
2178 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2179 uinfo->count = reg.stereo + 1;
2180 uinfo->value.integer.min = 0;
2181 uinfo->value.integer.max = reg.mask;
2182 return 0;
2183
2184}
2185
2186static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2187 struct snd_ctl_elem_value *ucontrol)
2188{
2189 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2190 struct cmipci_sb_reg reg;
2191 unsigned char oreg, val;
2192
2193 cmipci_sb_reg_decode(®, kcontrol->private_value);
2194 spin_lock_irq(&cm->reg_lock);
2195 oreg = inb(cm->iobase + reg.left_reg);
2196 val = (oreg >> reg.left_shift) & reg.mask;
2197 if (reg.invert)
2198 val = reg.mask - val;
2199 ucontrol->value.integer.value[0] = val;
2200 if (reg.stereo) {
2201 val = (oreg >> reg.right_shift) & reg.mask;
2202 if (reg.invert)
2203 val = reg.mask - val;
2204 ucontrol->value.integer.value[1] = val;
2205 }
2206 spin_unlock_irq(&cm->reg_lock);
2207 return 0;
2208}
2209
2210static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2211 struct snd_ctl_elem_value *ucontrol)
2212{
2213 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2214 struct cmipci_sb_reg reg;
2215 unsigned char oreg, nreg, val;
2216
2217 cmipci_sb_reg_decode(®, kcontrol->private_value);
2218 spin_lock_irq(&cm->reg_lock);
2219 oreg = inb(cm->iobase + reg.left_reg);
2220 val = ucontrol->value.integer.value[0] & reg.mask;
2221 if (reg.invert)
2222 val = reg.mask - val;
2223 nreg = oreg & ~(reg.mask << reg.left_shift);
2224 nreg |= (val << reg.left_shift);
2225 if (reg.stereo) {
2226 val = ucontrol->value.integer.value[1] & reg.mask;
2227 if (reg.invert)
2228 val = reg.mask - val;
2229 nreg &= ~(reg.mask << reg.right_shift);
2230 nreg |= (val << reg.right_shift);
2231 }
2232 outb(nreg, cm->iobase + reg.left_reg);
2233 spin_unlock_irq(&cm->reg_lock);
2234 return (nreg != oreg);
2235}
2236
2237/*
2238 * special case - check mixer sensitivity
2239 */
2240static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2241 struct snd_ctl_elem_value *ucontrol)
2242{
2243 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2244 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2245}
2246
2247static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2248 struct snd_ctl_elem_value *ucontrol)
2249{
2250 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2251 if (cm->mixer_insensitive) {
2252 /* ignored */
2253 return 0;
2254 }
2255 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2256}
2257
2258
2259static const struct snd_kcontrol_new snd_cmipci_mixers[] = {
2260 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2261 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2262 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2263 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2264 { /* switch with sensitivity */
2265 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2266 .name = "PCM Playback Switch",
2267 .info = snd_cmipci_info_native_mixer,
2268 .get = snd_cmipci_get_native_mixer_sensitive,
2269 .put = snd_cmipci_put_native_mixer_sensitive,
2270 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2271 },
2272 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2273 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2274 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2275 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2276 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2277 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2278 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2279 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2280 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2281 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2282 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2283 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2284 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2285 CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2286 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2287 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2288 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2289 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2290 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2291 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2292 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2293 CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2294 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2295};
2296
2297/*
2298 * other switches
2299 */
2300
2301struct cmipci_switch_args {
2302 int reg; /* register index */
2303 unsigned int mask; /* mask bits */
2304 unsigned int mask_on; /* mask bits to turn on */
2305 unsigned int is_byte: 1; /* byte access? */
2306 unsigned int ac3_sensitive: 1; /* access forbidden during
2307 * non-audio operation?
2308 */
2309};
2310
2311#define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
2312
2313static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2314 struct snd_ctl_elem_value *ucontrol,
2315 struct cmipci_switch_args *args)
2316{
2317 unsigned int val;
2318 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2319
2320 spin_lock_irq(&cm->reg_lock);
2321 if (args->ac3_sensitive && cm->mixer_insensitive) {
2322 ucontrol->value.integer.value[0] = 0;
2323 spin_unlock_irq(&cm->reg_lock);
2324 return 0;
2325 }
2326 if (args->is_byte)
2327 val = inb(cm->iobase + args->reg);
2328 else
2329 val = snd_cmipci_read(cm, args->reg);
2330 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2331 spin_unlock_irq(&cm->reg_lock);
2332 return 0;
2333}
2334
2335static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2336 struct snd_ctl_elem_value *ucontrol)
2337{
2338 struct cmipci_switch_args *args;
2339 args = (struct cmipci_switch_args *)kcontrol->private_value;
2340 if (snd_BUG_ON(!args))
2341 return -EINVAL;
2342 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2343}
2344
2345static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2346 struct snd_ctl_elem_value *ucontrol,
2347 struct cmipci_switch_args *args)
2348{
2349 unsigned int val;
2350 int change;
2351 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2352
2353 spin_lock_irq(&cm->reg_lock);
2354 if (args->ac3_sensitive && cm->mixer_insensitive) {
2355 /* ignored */
2356 spin_unlock_irq(&cm->reg_lock);
2357 return 0;
2358 }
2359 if (args->is_byte)
2360 val = inb(cm->iobase + args->reg);
2361 else
2362 val = snd_cmipci_read(cm, args->reg);
2363 change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2364 args->mask_on : (args->mask & ~args->mask_on));
2365 if (change) {
2366 val &= ~args->mask;
2367 if (ucontrol->value.integer.value[0])
2368 val |= args->mask_on;
2369 else
2370 val |= (args->mask & ~args->mask_on);
2371 if (args->is_byte)
2372 outb((unsigned char)val, cm->iobase + args->reg);
2373 else
2374 snd_cmipci_write(cm, args->reg, val);
2375 }
2376 spin_unlock_irq(&cm->reg_lock);
2377 return change;
2378}
2379
2380static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2381 struct snd_ctl_elem_value *ucontrol)
2382{
2383 struct cmipci_switch_args *args;
2384 args = (struct cmipci_switch_args *)kcontrol->private_value;
2385 if (snd_BUG_ON(!args))
2386 return -EINVAL;
2387 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2388}
2389
2390#define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2391static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2392 .reg = xreg, \
2393 .mask = xmask, \
2394 .mask_on = xmask_on, \
2395 .is_byte = xis_byte, \
2396 .ac3_sensitive = xac3, \
2397}
2398
2399#define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2400 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2401
2402#if 0 /* these will be controlled in pcm device */
2403DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2404DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2405#endif
2406DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2407DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2408DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2409DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2410DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2411DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2412DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2413DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2414// DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2415DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2416DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2417/* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2418DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2419DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2420#if CM_CH_PLAY == 1
2421DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2422#else
2423DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2424#endif
2425DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2426// DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2427// DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2428// DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2429DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2430
2431#define DEFINE_SWITCH(sname, stype, sarg) \
2432{ .name = sname, \
2433 .iface = stype, \
2434 .info = snd_cmipci_uswitch_info, \
2435 .get = snd_cmipci_uswitch_get, \
2436 .put = snd_cmipci_uswitch_put, \
2437 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2438}
2439
2440#define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2441#define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2442
2443
2444/*
2445 * callbacks for spdif output switch
2446 * needs toggle two registers..
2447 */
2448static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2449 struct snd_ctl_elem_value *ucontrol)
2450{
2451 int changed;
2452 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2453 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2454 return changed;
2455}
2456
2457static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2458 struct snd_ctl_elem_value *ucontrol)
2459{
2460 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2461 int changed;
2462 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2463 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2464 if (changed) {
2465 if (ucontrol->value.integer.value[0]) {
2466 if (chip->spdif_playback_avail)
2467 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2468 } else {
2469 if (chip->spdif_playback_avail)
2470 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2471 }
2472 }
2473 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2474 return changed;
2475}
2476
2477
2478static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2479 struct snd_ctl_elem_info *uinfo)
2480{
2481 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2482 static const char *const texts[3] = {
2483 "Line-In", "Rear Output", "Bass Output"
2484 };
2485
2486 return snd_ctl_enum_info(uinfo, 1,
2487 cm->chip_version >= 39 ? 3 : 2, texts);
2488}
2489
2490static inline unsigned int get_line_in_mode(struct cmipci *cm)
2491{
2492 unsigned int val;
2493 if (cm->chip_version >= 39) {
2494 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2495 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2496 return 2;
2497 }
2498 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2499 if (val & CM_REAR2LIN)
2500 return 1;
2501 return 0;
2502}
2503
2504static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2505 struct snd_ctl_elem_value *ucontrol)
2506{
2507 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2508
2509 spin_lock_irq(&cm->reg_lock);
2510 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2511 spin_unlock_irq(&cm->reg_lock);
2512 return 0;
2513}
2514
2515static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2516 struct snd_ctl_elem_value *ucontrol)
2517{
2518 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2519 int change;
2520
2521 spin_lock_irq(&cm->reg_lock);
2522 if (ucontrol->value.enumerated.item[0] == 2)
2523 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2524 else
2525 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2526 if (ucontrol->value.enumerated.item[0] == 1)
2527 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2528 else
2529 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2530 spin_unlock_irq(&cm->reg_lock);
2531 return change;
2532}
2533
2534static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2535 struct snd_ctl_elem_info *uinfo)
2536{
2537 static const char *const texts[2] = { "Mic-In", "Center/LFE Output" };
2538
2539 return snd_ctl_enum_info(uinfo, 1, 2, texts);
2540}
2541
2542static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2543 struct snd_ctl_elem_value *ucontrol)
2544{
2545 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2546 /* same bit as spdi_phase */
2547 spin_lock_irq(&cm->reg_lock);
2548 ucontrol->value.enumerated.item[0] =
2549 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2550 spin_unlock_irq(&cm->reg_lock);
2551 return 0;
2552}
2553
2554static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2555 struct snd_ctl_elem_value *ucontrol)
2556{
2557 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2558 int change;
2559
2560 spin_lock_irq(&cm->reg_lock);
2561 if (ucontrol->value.enumerated.item[0])
2562 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2563 else
2564 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2565 spin_unlock_irq(&cm->reg_lock);
2566 return change;
2567}
2568
2569/* both for CM8338/8738 */
2570static const struct snd_kcontrol_new snd_cmipci_mixer_switches[] = {
2571 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2572 {
2573 .name = "Line-In Mode",
2574 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2575 .info = snd_cmipci_line_in_mode_info,
2576 .get = snd_cmipci_line_in_mode_get,
2577 .put = snd_cmipci_line_in_mode_put,
2578 },
2579};
2580
2581/* for non-multichannel chips */
2582static const struct snd_kcontrol_new snd_cmipci_nomulti_switch =
2583DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2584
2585/* only for CM8738 */
2586static const struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] = {
2587#if 0 /* controlled in pcm device */
2588 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2589 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2590 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2591#endif
2592 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2593 { .name = "IEC958 Output Switch",
2594 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2595 .info = snd_cmipci_uswitch_info,
2596 .get = snd_cmipci_spdout_enable_get,
2597 .put = snd_cmipci_spdout_enable_put,
2598 },
2599 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2600 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2601 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2602// DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2603 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2604 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2605};
2606
2607/* only for model 033/037 */
2608static const struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] = {
2609 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2610 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2611 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2612};
2613
2614/* only for model 039 or later */
2615static const struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] = {
2616 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2617 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2618 {
2619 .name = "Mic-In Mode",
2620 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2621 .info = snd_cmipci_mic_in_mode_info,
2622 .get = snd_cmipci_mic_in_mode_get,
2623 .put = snd_cmipci_mic_in_mode_put,
2624 }
2625};
2626
2627/* card control switches */
2628static const struct snd_kcontrol_new snd_cmipci_modem_switch =
2629DEFINE_CARD_SWITCH("Modem", modem);
2630
2631
2632static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2633{
2634 struct snd_card *card;
2635 const struct snd_kcontrol_new *sw;
2636 struct snd_kcontrol *kctl;
2637 unsigned int idx;
2638 int err;
2639
2640 if (snd_BUG_ON(!cm || !cm->card))
2641 return -EINVAL;
2642
2643 card = cm->card;
2644
2645 strcpy(card->mixername, "CMedia PCI");
2646
2647 spin_lock_irq(&cm->reg_lock);
2648 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2649 spin_unlock_irq(&cm->reg_lock);
2650
2651 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2652 if (cm->chip_version == 68) { // 8768 has no PCM volume
2653 if (!strcmp(snd_cmipci_mixers[idx].name,
2654 "PCM Playback Volume"))
2655 continue;
2656 }
2657 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2658 return err;
2659 }
2660
2661 /* mixer switches */
2662 sw = snd_cmipci_mixer_switches;
2663 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2664 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2665 if (err < 0)
2666 return err;
2667 }
2668 if (! cm->can_multi_ch) {
2669 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2670 if (err < 0)
2671 return err;
2672 }
2673 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2674 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2675 sw = snd_cmipci_8738_mixer_switches;
2676 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2677 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2678 if (err < 0)
2679 return err;
2680 }
2681 if (cm->can_ac3_hw) {
2682 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2683 return err;
2684 kctl->id.device = pcm_spdif_device;
2685 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2686 return err;
2687 kctl->id.device = pcm_spdif_device;
2688 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2689 return err;
2690 kctl->id.device = pcm_spdif_device;
2691 }
2692 if (cm->chip_version <= 37) {
2693 sw = snd_cmipci_old_mixer_switches;
2694 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2695 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2696 if (err < 0)
2697 return err;
2698 }
2699 }
2700 }
2701 if (cm->chip_version >= 39) {
2702 sw = snd_cmipci_extra_mixer_switches;
2703 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2704 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2705 if (err < 0)
2706 return err;
2707 }
2708 }
2709
2710 /* card switches */
2711 /*
2712 * newer chips don't have the register bits to force modem link
2713 * detection; the bit that was FLINKON now mutes CH1
2714 */
2715 if (cm->chip_version < 39) {
2716 err = snd_ctl_add(cm->card,
2717 snd_ctl_new1(&snd_cmipci_modem_switch, cm));
2718 if (err < 0)
2719 return err;
2720 }
2721
2722 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2723 struct snd_ctl_elem_id elem_id;
2724 struct snd_kcontrol *ctl;
2725 memset(&elem_id, 0, sizeof(elem_id));
2726 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2727 strcpy(elem_id.name, cm_saved_mixer[idx].name);
2728 ctl = snd_ctl_find_id(cm->card, &elem_id);
2729 if (ctl)
2730 cm->mixer_res_ctl[idx] = ctl;
2731 }
2732
2733 return 0;
2734}
2735
2736
2737/*
2738 * proc interface
2739 */
2740
2741static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2742 struct snd_info_buffer *buffer)
2743{
2744 struct cmipci *cm = entry->private_data;
2745 int i, v;
2746
2747 snd_iprintf(buffer, "%s\n", cm->card->longname);
2748 for (i = 0; i < 0x94; i++) {
2749 if (i == 0x28)
2750 i = 0x90;
2751 v = inb(cm->iobase + i);
2752 if (i % 4 == 0)
2753 snd_iprintf(buffer, "\n%02x:", i);
2754 snd_iprintf(buffer, " %02x", v);
2755 }
2756 snd_iprintf(buffer, "\n");
2757}
2758
2759static void snd_cmipci_proc_init(struct cmipci *cm)
2760{
2761 snd_card_ro_proc_new(cm->card, "cmipci", cm, snd_cmipci_proc_read);
2762}
2763
2764static const struct pci_device_id snd_cmipci_ids[] = {
2765 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0},
2766 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0},
2767 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2768 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0},
2769 {PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2770 {0,},
2771};
2772
2773
2774/*
2775 * check chip version and capabilities
2776 * driver name is modified according to the chip model
2777 */
2778static void query_chip(struct cmipci *cm)
2779{
2780 unsigned int detect;
2781
2782 /* check reg 0Ch, bit 24-31 */
2783 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2784 if (! detect) {
2785 /* check reg 08h, bit 24-28 */
2786 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2787 switch (detect) {
2788 case 0:
2789 cm->chip_version = 33;
2790 if (cm->do_soft_ac3)
2791 cm->can_ac3_sw = 1;
2792 else
2793 cm->can_ac3_hw = 1;
2794 break;
2795 case CM_CHIP_037:
2796 cm->chip_version = 37;
2797 cm->can_ac3_hw = 1;
2798 break;
2799 default:
2800 cm->chip_version = 39;
2801 cm->can_ac3_hw = 1;
2802 break;
2803 }
2804 cm->max_channels = 2;
2805 } else {
2806 if (detect & CM_CHIP_039) {
2807 cm->chip_version = 39;
2808 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2809 cm->max_channels = 6;
2810 else
2811 cm->max_channels = 4;
2812 } else if (detect & CM_CHIP_8768) {
2813 cm->chip_version = 68;
2814 cm->max_channels = 8;
2815 cm->can_96k = 1;
2816 } else {
2817 cm->chip_version = 55;
2818 cm->max_channels = 6;
2819 cm->can_96k = 1;
2820 }
2821 cm->can_ac3_hw = 1;
2822 cm->can_multi_ch = 1;
2823 }
2824}
2825
2826#ifdef SUPPORT_JOYSTICK
2827static int snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2828{
2829 static const int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2830 struct gameport *gp;
2831 struct resource *r = NULL;
2832 int i, io_port = 0;
2833
2834 if (joystick_port[dev] == 0)
2835 return -ENODEV;
2836
2837 if (joystick_port[dev] == 1) { /* auto-detect */
2838 for (i = 0; ports[i]; i++) {
2839 io_port = ports[i];
2840 r = request_region(io_port, 1, "CMIPCI gameport");
2841 if (r)
2842 break;
2843 }
2844 } else {
2845 io_port = joystick_port[dev];
2846 r = request_region(io_port, 1, "CMIPCI gameport");
2847 }
2848
2849 if (!r) {
2850 dev_warn(cm->card->dev, "cannot reserve joystick ports\n");
2851 return -EBUSY;
2852 }
2853
2854 cm->gameport = gp = gameport_allocate_port();
2855 if (!gp) {
2856 dev_err(cm->card->dev, "cannot allocate memory for gameport\n");
2857 release_and_free_resource(r);
2858 return -ENOMEM;
2859 }
2860 gameport_set_name(gp, "C-Media Gameport");
2861 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2862 gameport_set_dev_parent(gp, &cm->pci->dev);
2863 gp->io = io_port;
2864 gameport_set_port_data(gp, r);
2865
2866 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2867
2868 gameport_register_port(cm->gameport);
2869
2870 return 0;
2871}
2872
2873static void snd_cmipci_free_gameport(struct cmipci *cm)
2874{
2875 if (cm->gameport) {
2876 struct resource *r = gameport_get_port_data(cm->gameport);
2877
2878 gameport_unregister_port(cm->gameport);
2879 cm->gameport = NULL;
2880
2881 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2882 release_and_free_resource(r);
2883 }
2884}
2885#else
2886static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2887static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2888#endif
2889
2890static int snd_cmipci_free(struct cmipci *cm)
2891{
2892 if (cm->irq >= 0) {
2893 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2894 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2895 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2896 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2897 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2898 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2899 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2900
2901 /* reset mixer */
2902 snd_cmipci_mixer_write(cm, 0, 0);
2903
2904 free_irq(cm->irq, cm);
2905 }
2906
2907 snd_cmipci_free_gameport(cm);
2908 pci_release_regions(cm->pci);
2909 pci_disable_device(cm->pci);
2910 kfree(cm);
2911 return 0;
2912}
2913
2914static int snd_cmipci_dev_free(struct snd_device *device)
2915{
2916 struct cmipci *cm = device->device_data;
2917 return snd_cmipci_free(cm);
2918}
2919
2920static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2921{
2922 long iosynth;
2923 unsigned int val;
2924 struct snd_opl3 *opl3;
2925 int err;
2926
2927 if (!fm_port)
2928 goto disable_fm;
2929
2930 if (cm->chip_version >= 39) {
2931 /* first try FM regs in PCI port range */
2932 iosynth = cm->iobase + CM_REG_FM_PCI;
2933 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2934 OPL3_HW_OPL3, 1, &opl3);
2935 } else {
2936 err = -EIO;
2937 }
2938 if (err < 0) {
2939 /* then try legacy ports */
2940 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2941 iosynth = fm_port;
2942 switch (iosynth) {
2943 case 0x3E8: val |= CM_FMSEL_3E8; break;
2944 case 0x3E0: val |= CM_FMSEL_3E0; break;
2945 case 0x3C8: val |= CM_FMSEL_3C8; break;
2946 case 0x388: val |= CM_FMSEL_388; break;
2947 default:
2948 goto disable_fm;
2949 }
2950 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2951 /* enable FM */
2952 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2953
2954 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2955 OPL3_HW_OPL3, 0, &opl3) < 0) {
2956 dev_err(cm->card->dev,
2957 "no OPL device at %#lx, skipping...\n",
2958 iosynth);
2959 goto disable_fm;
2960 }
2961 }
2962 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
2963 dev_err(cm->card->dev, "cannot create OPL3 hwdep\n");
2964 return err;
2965 }
2966 return 0;
2967
2968 disable_fm:
2969 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
2970 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2971 return 0;
2972}
2973
2974static int snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2975 int dev, struct cmipci **rcmipci)
2976{
2977 struct cmipci *cm;
2978 int err;
2979 static const struct snd_device_ops ops = {
2980 .dev_free = snd_cmipci_dev_free,
2981 };
2982 unsigned int val;
2983 long iomidi = 0;
2984 int integrated_midi = 0;
2985 char modelstr[16];
2986 int pcm_index, pcm_spdif_index;
2987 static const struct pci_device_id intel_82437vx[] = {
2988 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
2989 { },
2990 };
2991
2992 *rcmipci = NULL;
2993
2994 if ((err = pci_enable_device(pci)) < 0)
2995 return err;
2996
2997 cm = kzalloc(sizeof(*cm), GFP_KERNEL);
2998 if (cm == NULL) {
2999 pci_disable_device(pci);
3000 return -ENOMEM;
3001 }
3002
3003 spin_lock_init(&cm->reg_lock);
3004 mutex_init(&cm->open_mutex);
3005 cm->device = pci->device;
3006 cm->card = card;
3007 cm->pci = pci;
3008 cm->irq = -1;
3009 cm->channel[0].ch = 0;
3010 cm->channel[1].ch = 1;
3011 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
3012
3013 if ((err = pci_request_regions(pci, card->driver)) < 0) {
3014 kfree(cm);
3015 pci_disable_device(pci);
3016 return err;
3017 }
3018 cm->iobase = pci_resource_start(pci, 0);
3019
3020 if (request_irq(pci->irq, snd_cmipci_interrupt,
3021 IRQF_SHARED, KBUILD_MODNAME, cm)) {
3022 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3023 snd_cmipci_free(cm);
3024 return -EBUSY;
3025 }
3026 cm->irq = pci->irq;
3027 card->sync_irq = cm->irq;
3028
3029 pci_set_master(cm->pci);
3030
3031 /*
3032 * check chip version, max channels and capabilities
3033 */
3034
3035 cm->chip_version = 0;
3036 cm->max_channels = 2;
3037 cm->do_soft_ac3 = soft_ac3[dev];
3038
3039 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
3040 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
3041 query_chip(cm);
3042 /* added -MCx suffix for chip supporting multi-channels */
3043 if (cm->can_multi_ch)
3044 sprintf(cm->card->driver + strlen(cm->card->driver),
3045 "-MC%d", cm->max_channels);
3046 else if (cm->can_ac3_sw)
3047 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3048
3049 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3050 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3051
3052#if CM_CH_PLAY == 1
3053 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
3054#else
3055 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
3056#endif
3057
3058 /* initialize codec registers */
3059 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3060 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3061 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
3062 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3063 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3064 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
3065 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3066
3067 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3068 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3069#if CM_CH_PLAY == 1
3070 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3071#else
3072 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3073#endif
3074 if (cm->chip_version) {
3075 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3076 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3077 }
3078 /* Set Bus Master Request */
3079 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3080
3081 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3082 switch (pci->device) {
3083 case PCI_DEVICE_ID_CMEDIA_CM8738:
3084 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3085 if (!pci_dev_present(intel_82437vx))
3086 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3087 break;
3088 default:
3089 break;
3090 }
3091
3092 if (cm->chip_version < 68) {
3093 val = pci->device < 0x110 ? 8338 : 8738;
3094 } else {
3095 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3096 case 0:
3097 val = 8769;
3098 break;
3099 case 2:
3100 val = 8762;
3101 break;
3102 default:
3103 switch ((pci->subsystem_vendor << 16) |
3104 pci->subsystem_device) {
3105 case 0x13f69761:
3106 case 0x584d3741:
3107 case 0x584d3751:
3108 case 0x584d3761:
3109 case 0x584d3771:
3110 case 0x72848384:
3111 val = 8770;
3112 break;
3113 default:
3114 val = 8768;
3115 break;
3116 }
3117 }
3118 }
3119 sprintf(card->shortname, "C-Media CMI%d", val);
3120 if (cm->chip_version < 68)
3121 sprintf(modelstr, " (model %d)", cm->chip_version);
3122 else
3123 modelstr[0] = '\0';
3124 sprintf(card->longname, "%s%s at %#lx, irq %i",
3125 card->shortname, modelstr, cm->iobase, cm->irq);
3126
3127 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
3128 snd_cmipci_free(cm);
3129 return err;
3130 }
3131
3132 if (cm->chip_version >= 39) {
3133 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3134 if (val != 0x00 && val != 0xff) {
3135 if (mpu_port[dev])
3136 iomidi = cm->iobase + CM_REG_MPU_PCI;
3137 integrated_midi = 1;
3138 }
3139 }
3140 if (!integrated_midi) {
3141 val = 0;
3142 iomidi = mpu_port[dev];
3143 switch (iomidi) {
3144 case 0x320: val = CM_VMPU_320; break;
3145 case 0x310: val = CM_VMPU_310; break;
3146 case 0x300: val = CM_VMPU_300; break;
3147 case 0x330: val = CM_VMPU_330; break;
3148 default:
3149 iomidi = 0; break;
3150 }
3151 if (iomidi > 0) {
3152 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3153 /* enable UART */
3154 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3155 if (inb(iomidi + 1) == 0xff) {
3156 dev_err(cm->card->dev,
3157 "cannot enable MPU-401 port at %#lx\n",
3158 iomidi);
3159 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3160 CM_UART_EN);
3161 iomidi = 0;
3162 }
3163 }
3164 }
3165
3166 if (cm->chip_version < 68) {
3167 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3168 if (err < 0)
3169 return err;
3170 }
3171
3172 /* reset mixer */
3173 snd_cmipci_mixer_write(cm, 0, 0);
3174
3175 snd_cmipci_proc_init(cm);
3176
3177 /* create pcm devices */
3178 pcm_index = pcm_spdif_index = 0;
3179 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
3180 return err;
3181 pcm_index++;
3182 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
3183 return err;
3184 pcm_index++;
3185 if (cm->can_ac3_hw || cm->can_ac3_sw) {
3186 pcm_spdif_index = pcm_index;
3187 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
3188 return err;
3189 }
3190
3191 /* create mixer interface & switches */
3192 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
3193 return err;
3194
3195 if (iomidi > 0) {
3196 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3197 iomidi,
3198 (integrated_midi ?
3199 MPU401_INFO_INTEGRATED : 0) |
3200 MPU401_INFO_IRQ_HOOK,
3201 -1, &cm->rmidi)) < 0) {
3202 dev_err(cm->card->dev,
3203 "no UART401 device at 0x%lx\n", iomidi);
3204 }
3205 }
3206
3207#ifdef USE_VAR48KRATE
3208 for (val = 0; val < ARRAY_SIZE(rates); val++)
3209 snd_cmipci_set_pll(cm, rates[val], val);
3210
3211 /*
3212 * (Re-)Enable external switch spdo_48k
3213 */
3214 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3215#endif /* USE_VAR48KRATE */
3216
3217 if (snd_cmipci_create_gameport(cm, dev) < 0)
3218 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3219
3220 *rcmipci = cm;
3221 return 0;
3222}
3223
3224/*
3225 */
3226
3227MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3228
3229static int snd_cmipci_probe(struct pci_dev *pci,
3230 const struct pci_device_id *pci_id)
3231{
3232 static int dev;
3233 struct snd_card *card;
3234 struct cmipci *cm;
3235 int err;
3236
3237 if (dev >= SNDRV_CARDS)
3238 return -ENODEV;
3239 if (! enable[dev]) {
3240 dev++;
3241 return -ENOENT;
3242 }
3243
3244 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
3245 0, &card);
3246 if (err < 0)
3247 return err;
3248
3249 switch (pci->device) {
3250 case PCI_DEVICE_ID_CMEDIA_CM8738:
3251 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3252 strcpy(card->driver, "CMI8738");
3253 break;
3254 case PCI_DEVICE_ID_CMEDIA_CM8338A:
3255 case PCI_DEVICE_ID_CMEDIA_CM8338B:
3256 strcpy(card->driver, "CMI8338");
3257 break;
3258 default:
3259 strcpy(card->driver, "CMIPCI");
3260 break;
3261 }
3262
3263 err = snd_cmipci_create(card, pci, dev, &cm);
3264 if (err < 0)
3265 goto free_card;
3266
3267 card->private_data = cm;
3268
3269 err = snd_card_register(card);
3270 if (err < 0)
3271 goto free_card;
3272
3273 pci_set_drvdata(pci, card);
3274 dev++;
3275 return 0;
3276
3277free_card:
3278 snd_card_free(card);
3279 return err;
3280}
3281
3282static void snd_cmipci_remove(struct pci_dev *pci)
3283{
3284 snd_card_free(pci_get_drvdata(pci));
3285}
3286
3287
3288#ifdef CONFIG_PM_SLEEP
3289/*
3290 * power management
3291 */
3292static const unsigned char saved_regs[] = {
3293 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3294 CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL,
3295 CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3296 CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3297 CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3298};
3299
3300static const unsigned char saved_mixers[] = {
3301 SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3302 SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3303 SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3304 SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3305 SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3306 SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3307 CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3308 SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3309};
3310
3311static int snd_cmipci_suspend(struct device *dev)
3312{
3313 struct snd_card *card = dev_get_drvdata(dev);
3314 struct cmipci *cm = card->private_data;
3315 int i;
3316
3317 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3318
3319 /* save registers */
3320 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3321 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3322 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3323 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3324
3325 /* disable ints */
3326 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3327 return 0;
3328}
3329
3330static int snd_cmipci_resume(struct device *dev)
3331{
3332 struct snd_card *card = dev_get_drvdata(dev);
3333 struct cmipci *cm = card->private_data;
3334 int i;
3335
3336 /* reset / initialize to a sane state */
3337 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3338 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3339 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3340 snd_cmipci_mixer_write(cm, 0, 0);
3341
3342 /* restore registers */
3343 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3344 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3345 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3346 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3347
3348 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3349 return 0;
3350}
3351
3352static SIMPLE_DEV_PM_OPS(snd_cmipci_pm, snd_cmipci_suspend, snd_cmipci_resume);
3353#define SND_CMIPCI_PM_OPS &snd_cmipci_pm
3354#else
3355#define SND_CMIPCI_PM_OPS NULL
3356#endif /* CONFIG_PM_SLEEP */
3357
3358static struct pci_driver cmipci_driver = {
3359 .name = KBUILD_MODNAME,
3360 .id_table = snd_cmipci_ids,
3361 .probe = snd_cmipci_probe,
3362 .remove = snd_cmipci_remove,
3363 .driver = {
3364 .pm = SND_CMIPCI_PM_OPS,
3365 },
3366};
3367
3368module_pci_driver(cmipci_driver);
1/*
2 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20/* Does not work. Warning may block system in capture mode */
21/* #define USE_VAR48KRATE */
22
23#include <linux/io.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/init.h>
27#include <linux/pci.h>
28#include <linux/slab.h>
29#include <linux/gameport.h>
30#include <linux/module.h>
31#include <linux/mutex.h>
32#include <sound/core.h>
33#include <sound/info.h>
34#include <sound/control.h>
35#include <sound/pcm.h>
36#include <sound/rawmidi.h>
37#include <sound/mpu401.h>
38#include <sound/opl3.h>
39#include <sound/sb.h>
40#include <sound/asoundef.h>
41#include <sound/initval.h>
42
43MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
44MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
45MODULE_LICENSE("GPL");
46MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
47 "{C-Media,CMI8738B},"
48 "{C-Media,CMI8338A},"
49 "{C-Media,CMI8338B}}");
50
51#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
52#define SUPPORT_JOYSTICK 1
53#endif
54
55static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
56static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
57static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
58static long mpu_port[SNDRV_CARDS];
59static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
60static bool soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
61#ifdef SUPPORT_JOYSTICK
62static int joystick_port[SNDRV_CARDS];
63#endif
64
65module_param_array(index, int, NULL, 0444);
66MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
67module_param_array(id, charp, NULL, 0444);
68MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
69module_param_array(enable, bool, NULL, 0444);
70MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
71module_param_array(mpu_port, long, NULL, 0444);
72MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
73module_param_array(fm_port, long, NULL, 0444);
74MODULE_PARM_DESC(fm_port, "FM port.");
75module_param_array(soft_ac3, bool, NULL, 0444);
76MODULE_PARM_DESC(soft_ac3, "Software-conversion of raw SPDIF packets (model 033 only).");
77#ifdef SUPPORT_JOYSTICK
78module_param_array(joystick_port, int, NULL, 0444);
79MODULE_PARM_DESC(joystick_port, "Joystick port address.");
80#endif
81
82/*
83 * CM8x38 registers definition
84 */
85
86#define CM_REG_FUNCTRL0 0x00
87#define CM_RST_CH1 0x00080000
88#define CM_RST_CH0 0x00040000
89#define CM_CHEN1 0x00020000 /* ch1: enable */
90#define CM_CHEN0 0x00010000 /* ch0: enable */
91#define CM_PAUSE1 0x00000008 /* ch1: pause */
92#define CM_PAUSE0 0x00000004 /* ch0: pause */
93#define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
94#define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
95
96#define CM_REG_FUNCTRL1 0x04
97#define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
98#define CM_DSFC_SHIFT 13
99#define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
100#define CM_ASFC_SHIFT 10
101#define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
102#define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
103#define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
104#define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
105#define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
106#define CM_BREQ 0x00000010 /* bus master enabled */
107#define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
108#define CM_UART_EN 0x00000004 /* legacy UART */
109#define CM_JYSTK_EN 0x00000002 /* legacy joystick */
110#define CM_ZVPORT 0x00000001 /* ZVPORT */
111
112#define CM_REG_CHFORMAT 0x08
113
114#define CM_CHB3D5C 0x80000000 /* 5,6 channels */
115#define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
116#define CM_CHB3D 0x20000000 /* 4 channels */
117
118#define CM_CHIP_MASK1 0x1f000000
119#define CM_CHIP_037 0x01000000
120#define CM_SETLAT48 0x00800000 /* set latency timer 48h */
121#define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
122#define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
123#define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
124#define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
125#define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
126/* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
127
128#define CM_ADCBITLEN_MASK 0x0000C000
129#define CM_ADCBITLEN_16 0x00000000
130#define CM_ADCBITLEN_15 0x00004000
131#define CM_ADCBITLEN_14 0x00008000
132#define CM_ADCBITLEN_13 0x0000C000
133
134#define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
135#define CM_ADCDACLEN_060 0x00000000
136#define CM_ADCDACLEN_066 0x00001000
137#define CM_ADCDACLEN_130 0x00002000
138#define CM_ADCDACLEN_280 0x00003000
139
140#define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
141#define CM_ADCDLEN_ORIGINAL 0x00000000
142#define CM_ADCDLEN_EXTRA 0x00001000
143#define CM_ADCDLEN_24K 0x00002000
144#define CM_ADCDLEN_WEIGHT 0x00003000
145
146#define CM_CH1_SRATE_176K 0x00000800
147#define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
148#define CM_CH1_SRATE_88K 0x00000400
149#define CM_CH0_SRATE_176K 0x00000200
150#define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
151#define CM_CH0_SRATE_88K 0x00000100
152#define CM_CH0_SRATE_128K 0x00000300
153#define CM_CH0_SRATE_MASK 0x00000300
154
155#define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
156#define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
157#define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
158#define CM_SPDLOCKED 0x00000010
159
160#define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
161#define CM_CH1FMT_SHIFT 2
162#define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
163#define CM_CH0FMT_SHIFT 0
164
165#define CM_REG_INT_HLDCLR 0x0C
166#define CM_CHIP_MASK2 0xff000000
167#define CM_CHIP_8768 0x20000000
168#define CM_CHIP_055 0x08000000
169#define CM_CHIP_039 0x04000000
170#define CM_CHIP_039_6CH 0x01000000
171#define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
172#define CM_TDMA_INT_EN 0x00040000
173#define CM_CH1_INT_EN 0x00020000
174#define CM_CH0_INT_EN 0x00010000
175
176#define CM_REG_INT_STATUS 0x10
177#define CM_INTR 0x80000000
178#define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
179#define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
180#define CM_UARTINT 0x00010000
181#define CM_LTDMAINT 0x00008000
182#define CM_HTDMAINT 0x00004000
183#define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
184#define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
185#define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
186#define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
187#define CM_CH1BUSY 0x00000008
188#define CM_CH0BUSY 0x00000004
189#define CM_CHINT1 0x00000002
190#define CM_CHINT0 0x00000001
191
192#define CM_REG_LEGACY_CTRL 0x14
193#define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
194#define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
195#define CM_VMPU_330 0x00000000
196#define CM_VMPU_320 0x20000000
197#define CM_VMPU_310 0x40000000
198#define CM_VMPU_300 0x60000000
199#define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
200#define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
201#define CM_VSBSEL_220 0x00000000
202#define CM_VSBSEL_240 0x04000000
203#define CM_VSBSEL_260 0x08000000
204#define CM_VSBSEL_280 0x0C000000
205#define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
206#define CM_FMSEL_388 0x00000000
207#define CM_FMSEL_3C8 0x01000000
208#define CM_FMSEL_3E0 0x02000000
209#define CM_FMSEL_3E8 0x03000000
210#define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
211#define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
212#define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
213#define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
214#define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
215#define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
216#define CM_C_EECS 0x00040000
217#define CM_C_EEDI46 0x00020000
218#define CM_C_EECK46 0x00010000
219#define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
220#define CM_CENTR2LIN 0x00004000 /* line-in as center out */
221#define CM_BASE2LIN 0x00002000 /* line-in as bass out */
222#define CM_EXBASEN 0x00001000 /* external bass input enable */
223
224#define CM_REG_MISC_CTRL 0x18
225#define CM_PWD 0x80000000 /* power down */
226#define CM_RESET 0x40000000
227#define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
228#define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
229#define CM_TXVX 0x08000000 /* model 037? */
230#define CM_N4SPK3D 0x04000000 /* copy front to rear */
231#define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
232#define CM_SPDIF48K 0x01000000 /* write */
233#define CM_SPATUS48K 0x01000000 /* read */
234#define CM_ENDBDAC 0x00800000 /* enable double dac */
235#define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
236#define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
237#define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
238#define CM_FM_EN 0x00080000 /* enable legacy FM */
239#define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
240#define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
241#define CM_VIDWPDSB 0x00010000 /* model 037? */
242#define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
243#define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
244#define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
245#define CM_VIDWPPRT 0x00002000 /* model 037? */
246#define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
247#define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
248#define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
249#define CM_ENCENTER 0x00000080
250#define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */
251#define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
252#define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */
253#define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
254#define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
255#define CM_UPDDMA_2048 0x00000000
256#define CM_UPDDMA_1024 0x00000004
257#define CM_UPDDMA_512 0x00000008
258#define CM_UPDDMA_256 0x0000000C
259#define CM_TWAIT_MASK 0x00000003 /* model 037 */
260#define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
261#define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
262
263#define CM_REG_TDMA_POSITION 0x1C
264#define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
265#define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
266
267 /* byte */
268#define CM_REG_MIXER0 0x20
269#define CM_REG_SBVR 0x20 /* write: sb16 version */
270#define CM_REG_DEV 0x20 /* read: hardware device version */
271
272#define CM_REG_MIXER21 0x21
273#define CM_UNKNOWN_21_MASK 0x78 /* ? */
274#define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
275#define CM_PROINV 0x02 /* SBPro left/right channel switching */
276#define CM_X_SB16 0x01 /* SB16 compatible */
277
278#define CM_REG_SB16_DATA 0x22
279#define CM_REG_SB16_ADDR 0x23
280
281#define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
282#define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
283#define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
284#define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
285
286#define CM_REG_MIXER1 0x24
287#define CM_FMMUTE 0x80 /* mute FM */
288#define CM_FMMUTE_SHIFT 7
289#define CM_WSMUTE 0x40 /* mute PCM */
290#define CM_WSMUTE_SHIFT 6
291#define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
292#define CM_REAR2LIN_SHIFT 5
293#define CM_REAR2FRONT 0x10 /* exchange rear/front */
294#define CM_REAR2FRONT_SHIFT 4
295#define CM_WAVEINL 0x08 /* digital wave rec. left chan */
296#define CM_WAVEINL_SHIFT 3
297#define CM_WAVEINR 0x04 /* digical wave rec. right */
298#define CM_WAVEINR_SHIFT 2
299#define CM_X3DEN 0x02 /* 3D surround enable */
300#define CM_X3DEN_SHIFT 1
301#define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
302#define CM_CDPLAY_SHIFT 0
303
304#define CM_REG_MIXER2 0x25
305#define CM_RAUXREN 0x80 /* AUX right capture */
306#define CM_RAUXREN_SHIFT 7
307#define CM_RAUXLEN 0x40 /* AUX left capture */
308#define CM_RAUXLEN_SHIFT 6
309#define CM_VAUXRM 0x20 /* AUX right mute */
310#define CM_VAUXRM_SHIFT 5
311#define CM_VAUXLM 0x10 /* AUX left mute */
312#define CM_VAUXLM_SHIFT 4
313#define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
314#define CM_VADMIC_SHIFT 1
315#define CM_MICGAINZ 0x01 /* mic boost */
316#define CM_MICGAINZ_SHIFT 0
317
318#define CM_REG_MIXER3 0x24
319#define CM_REG_AUX_VOL 0x26
320#define CM_VAUXL_MASK 0xf0
321#define CM_VAUXR_MASK 0x0f
322
323#define CM_REG_MISC 0x27
324#define CM_UNKNOWN_27_MASK 0xd8 /* ? */
325#define CM_XGPO1 0x20
326// #define CM_XGPBIO 0x04
327#define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
328#define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
329#define CM_SPDVALID 0x02 /* spdif input valid check */
330#define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
331
332#define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
333/*
334 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
335 * or identical with AC97 codec?
336 */
337#define CM_REG_EXTERN_CODEC CM_REG_AC97
338
339/*
340 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
341 */
342#define CM_REG_MPU_PCI 0x40
343
344/*
345 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
346 */
347#define CM_REG_FM_PCI 0x50
348
349/*
350 * access from SB-mixer port
351 */
352#define CM_REG_EXTENT_IND 0xf0
353#define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
354#define CM_VPHONE_SHIFT 5
355#define CM_VPHOM 0x10 /* Phone mute control */
356#define CM_VSPKM 0x08 /* Speaker mute control, default high */
357#define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
358#define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
359#define CM_VADMIC3 0x01 /* Mic record boost */
360
361/*
362 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
363 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
364 * unit (readonly?).
365 */
366#define CM_REG_PLL 0xf8
367
368/*
369 * extended registers
370 */
371#define CM_REG_CH0_FRAME1 0x80 /* write: base address */
372#define CM_REG_CH0_FRAME2 0x84 /* read: current address */
373#define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
374#define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
375
376#define CM_REG_EXT_MISC 0x90
377#define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
378#define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
379#define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
380#define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
381#define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
382#define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
383#define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
384#define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
385
386/*
387 * size of i/o region
388 */
389#define CM_EXTENT_CODEC 0x100
390#define CM_EXTENT_MIDI 0x2
391#define CM_EXTENT_SYNTH 0x4
392
393
394/*
395 * channels for playback / capture
396 */
397#define CM_CH_PLAY 0
398#define CM_CH_CAPT 1
399
400/*
401 * flags to check device open/close
402 */
403#define CM_OPEN_NONE 0
404#define CM_OPEN_CH_MASK 0x01
405#define CM_OPEN_DAC 0x10
406#define CM_OPEN_ADC 0x20
407#define CM_OPEN_SPDIF 0x40
408#define CM_OPEN_MCHAN 0x80
409#define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
410#define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
411#define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
412#define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
413#define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
414#define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
415
416
417#if CM_CH_PLAY == 1
418#define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
419#define CM_PLAYBACK_SPDF CM_SPDF_1
420#define CM_CAPTURE_SPDF CM_SPDF_0
421#else
422#define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
423#define CM_PLAYBACK_SPDF CM_SPDF_0
424#define CM_CAPTURE_SPDF CM_SPDF_1
425#endif
426
427
428/*
429 * driver data
430 */
431
432struct cmipci_pcm {
433 struct snd_pcm_substream *substream;
434 u8 running; /* dac/adc running? */
435 u8 fmt; /* format bits */
436 u8 is_dac;
437 u8 needs_silencing;
438 unsigned int dma_size; /* in frames */
439 unsigned int shift;
440 unsigned int ch; /* channel (0/1) */
441 unsigned int offset; /* physical address of the buffer */
442};
443
444/* mixer elements toggled/resumed during ac3 playback */
445struct cmipci_mixer_auto_switches {
446 const char *name; /* switch to toggle */
447 int toggle_on; /* value to change when ac3 mode */
448};
449static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
450 {"PCM Playback Switch", 0},
451 {"IEC958 Output Switch", 1},
452 {"IEC958 Mix Analog", 0},
453 // {"IEC958 Out To DAC", 1}, // no longer used
454 {"IEC958 Loop", 0},
455};
456#define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
457
458struct cmipci {
459 struct snd_card *card;
460
461 struct pci_dev *pci;
462 unsigned int device; /* device ID */
463 int irq;
464
465 unsigned long iobase;
466 unsigned int ctrl; /* FUNCTRL0 current value */
467
468 struct snd_pcm *pcm; /* DAC/ADC PCM */
469 struct snd_pcm *pcm2; /* 2nd DAC */
470 struct snd_pcm *pcm_spdif; /* SPDIF */
471
472 int chip_version;
473 int max_channels;
474 unsigned int can_ac3_sw: 1;
475 unsigned int can_ac3_hw: 1;
476 unsigned int can_multi_ch: 1;
477 unsigned int can_96k: 1; /* samplerate above 48k */
478 unsigned int do_soft_ac3: 1;
479
480 unsigned int spdif_playback_avail: 1; /* spdif ready? */
481 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
482 int spdif_counter; /* for software AC3 */
483
484 unsigned int dig_status;
485 unsigned int dig_pcm_status;
486
487 struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
488
489 int opened[2]; /* open mode */
490 struct mutex open_mutex;
491
492 unsigned int mixer_insensitive: 1;
493 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
494 int mixer_res_status[CM_SAVED_MIXERS];
495
496 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
497
498 /* external MIDI */
499 struct snd_rawmidi *rmidi;
500
501#ifdef SUPPORT_JOYSTICK
502 struct gameport *gameport;
503#endif
504
505 spinlock_t reg_lock;
506
507#ifdef CONFIG_PM_SLEEP
508 unsigned int saved_regs[0x20];
509 unsigned char saved_mixers[0x20];
510#endif
511};
512
513
514/* read/write operations for dword register */
515static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
516{
517 outl(data, cm->iobase + cmd);
518}
519
520static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
521{
522 return inl(cm->iobase + cmd);
523}
524
525/* read/write operations for word register */
526static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
527{
528 outw(data, cm->iobase + cmd);
529}
530
531static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
532{
533 return inw(cm->iobase + cmd);
534}
535
536/* read/write operations for byte register */
537static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
538{
539 outb(data, cm->iobase + cmd);
540}
541
542static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
543{
544 return inb(cm->iobase + cmd);
545}
546
547/* bit operations for dword register */
548static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
549{
550 unsigned int val, oval;
551 val = oval = inl(cm->iobase + cmd);
552 val |= flag;
553 if (val == oval)
554 return 0;
555 outl(val, cm->iobase + cmd);
556 return 1;
557}
558
559static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
560{
561 unsigned int val, oval;
562 val = oval = inl(cm->iobase + cmd);
563 val &= ~flag;
564 if (val == oval)
565 return 0;
566 outl(val, cm->iobase + cmd);
567 return 1;
568}
569
570/* bit operations for byte register */
571static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
572{
573 unsigned char val, oval;
574 val = oval = inb(cm->iobase + cmd);
575 val |= flag;
576 if (val == oval)
577 return 0;
578 outb(val, cm->iobase + cmd);
579 return 1;
580}
581
582static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
583{
584 unsigned char val, oval;
585 val = oval = inb(cm->iobase + cmd);
586 val &= ~flag;
587 if (val == oval)
588 return 0;
589 outb(val, cm->iobase + cmd);
590 return 1;
591}
592
593
594/*
595 * PCM interface
596 */
597
598/*
599 * calculate frequency
600 */
601
602static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
603
604static unsigned int snd_cmipci_rate_freq(unsigned int rate)
605{
606 unsigned int i;
607
608 for (i = 0; i < ARRAY_SIZE(rates); i++) {
609 if (rates[i] == rate)
610 return i;
611 }
612 snd_BUG();
613 return 0;
614}
615
616#ifdef USE_VAR48KRATE
617/*
618 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
619 * does it this way .. maybe not. Never get any information from C-Media about
620 * that <werner@suse.de>.
621 */
622static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
623{
624 unsigned int delta, tolerance;
625 int xm, xn, xr;
626
627 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
628 rate <<= 1;
629 *n = -1;
630 if (*r > 0xff)
631 goto out;
632 tolerance = rate*CM_TOLERANCE_RATE;
633
634 for (xn = (1+2); xn < (0x1f+2); xn++) {
635 for (xm = (1+2); xm < (0xff+2); xm++) {
636 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
637
638 if (xr < rate)
639 delta = rate - xr;
640 else
641 delta = xr - rate;
642
643 /*
644 * If we found one, remember this,
645 * and try to find a closer one
646 */
647 if (delta < tolerance) {
648 tolerance = delta;
649 *m = xm - 2;
650 *n = xn - 2;
651 }
652 }
653 }
654out:
655 return (*n > -1);
656}
657
658/*
659 * Program pll register bits, I assume that the 8 registers 0xf8 up to 0xff
660 * are mapped onto the 8 ADC/DAC sampling frequency which can be chosen
661 * at the register CM_REG_FUNCTRL1 (0x04).
662 * Problem: other ways are also possible (any information about that?)
663 */
664static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
665{
666 unsigned int reg = CM_REG_PLL + slot;
667 /*
668 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
669 * for DSFC/ASFC (000 up to 111).
670 */
671
672 /* FIXME: Init (Do we've to set an other register first before programming?) */
673
674 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
675 snd_cmipci_write_b(cm, reg, rate>>8);
676 snd_cmipci_write_b(cm, reg, rate&0xff);
677
678 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
679}
680#endif /* USE_VAR48KRATE */
681
682static int snd_cmipci_hw_params(struct snd_pcm_substream *substream,
683 struct snd_pcm_hw_params *hw_params)
684{
685 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
686}
687
688static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
689 struct snd_pcm_hw_params *hw_params)
690{
691 struct cmipci *cm = snd_pcm_substream_chip(substream);
692 if (params_channels(hw_params) > 2) {
693 mutex_lock(&cm->open_mutex);
694 if (cm->opened[CM_CH_PLAY]) {
695 mutex_unlock(&cm->open_mutex);
696 return -EBUSY;
697 }
698 /* reserve the channel A */
699 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
700 mutex_unlock(&cm->open_mutex);
701 }
702 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
703}
704
705static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
706{
707 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
708 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
709 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
710 udelay(10);
711}
712
713static int snd_cmipci_hw_free(struct snd_pcm_substream *substream)
714{
715 return snd_pcm_lib_free_pages(substream);
716}
717
718
719/*
720 */
721
722static unsigned int hw_channels[] = {1, 2, 4, 6, 8};
723static struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
724 .count = 3,
725 .list = hw_channels,
726 .mask = 0,
727};
728static struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
729 .count = 4,
730 .list = hw_channels,
731 .mask = 0,
732};
733static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
734 .count = 5,
735 .list = hw_channels,
736 .mask = 0,
737};
738
739static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
740{
741 if (channels > 2) {
742 if (!cm->can_multi_ch || !rec->ch)
743 return -EINVAL;
744 if (rec->fmt != 0x03) /* stereo 16bit only */
745 return -EINVAL;
746 }
747
748 if (cm->can_multi_ch) {
749 spin_lock_irq(&cm->reg_lock);
750 if (channels > 2) {
751 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
752 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
753 } else {
754 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
755 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
756 }
757 if (channels == 8)
758 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
759 else
760 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
761 if (channels == 6) {
762 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
763 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
764 } else {
765 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
766 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
767 }
768 if (channels == 4)
769 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
770 else
771 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
772 spin_unlock_irq(&cm->reg_lock);
773 }
774 return 0;
775}
776
777
778/*
779 * prepare playback/capture channel
780 * channel to be used must have been set in rec->ch.
781 */
782static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
783 struct snd_pcm_substream *substream)
784{
785 unsigned int reg, freq, freq_ext, val;
786 unsigned int period_size;
787 struct snd_pcm_runtime *runtime = substream->runtime;
788
789 rec->fmt = 0;
790 rec->shift = 0;
791 if (snd_pcm_format_width(runtime->format) >= 16) {
792 rec->fmt |= 0x02;
793 if (snd_pcm_format_width(runtime->format) > 16)
794 rec->shift++; /* 24/32bit */
795 }
796 if (runtime->channels > 1)
797 rec->fmt |= 0x01;
798 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
799 dev_dbg(cm->card->dev, "cannot set dac channels\n");
800 return -EINVAL;
801 }
802
803 rec->offset = runtime->dma_addr;
804 /* buffer and period sizes in frame */
805 rec->dma_size = runtime->buffer_size << rec->shift;
806 period_size = runtime->period_size << rec->shift;
807 if (runtime->channels > 2) {
808 /* multi-channels */
809 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
810 period_size = (period_size * runtime->channels) / 2;
811 }
812
813 spin_lock_irq(&cm->reg_lock);
814
815 /* set buffer address */
816 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
817 snd_cmipci_write(cm, reg, rec->offset);
818 /* program sample counts */
819 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
820 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
821 snd_cmipci_write_w(cm, reg + 2, period_size - 1);
822
823 /* set adc/dac flag */
824 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
825 if (rec->is_dac)
826 cm->ctrl &= ~val;
827 else
828 cm->ctrl |= val;
829 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
830 /* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */
831
832 /* set sample rate */
833 freq = 0;
834 freq_ext = 0;
835 if (runtime->rate > 48000)
836 switch (runtime->rate) {
837 case 88200: freq_ext = CM_CH0_SRATE_88K; break;
838 case 96000: freq_ext = CM_CH0_SRATE_96K; break;
839 case 128000: freq_ext = CM_CH0_SRATE_128K; break;
840 default: snd_BUG(); break;
841 }
842 else
843 freq = snd_cmipci_rate_freq(runtime->rate);
844 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
845 if (rec->ch) {
846 val &= ~CM_DSFC_MASK;
847 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
848 } else {
849 val &= ~CM_ASFC_MASK;
850 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
851 }
852 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
853 dev_dbg(cm->card->dev, "functrl1 = %08x\n", val);
854
855 /* set format */
856 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
857 if (rec->ch) {
858 val &= ~CM_CH1FMT_MASK;
859 val |= rec->fmt << CM_CH1FMT_SHIFT;
860 } else {
861 val &= ~CM_CH0FMT_MASK;
862 val |= rec->fmt << CM_CH0FMT_SHIFT;
863 }
864 if (cm->can_96k) {
865 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
866 val |= freq_ext << (rec->ch * 2);
867 }
868 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
869 dev_dbg(cm->card->dev, "chformat = %08x\n", val);
870
871 if (!rec->is_dac && cm->chip_version) {
872 if (runtime->rate > 44100)
873 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
874 else
875 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
876 }
877
878 rec->running = 0;
879 spin_unlock_irq(&cm->reg_lock);
880
881 return 0;
882}
883
884/*
885 * PCM trigger/stop
886 */
887static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
888 int cmd)
889{
890 unsigned int inthld, chen, reset, pause;
891 int result = 0;
892
893 inthld = CM_CH0_INT_EN << rec->ch;
894 chen = CM_CHEN0 << rec->ch;
895 reset = CM_RST_CH0 << rec->ch;
896 pause = CM_PAUSE0 << rec->ch;
897
898 spin_lock(&cm->reg_lock);
899 switch (cmd) {
900 case SNDRV_PCM_TRIGGER_START:
901 rec->running = 1;
902 /* set interrupt */
903 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
904 cm->ctrl |= chen;
905 /* enable channel */
906 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
907 dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl);
908 break;
909 case SNDRV_PCM_TRIGGER_STOP:
910 rec->running = 0;
911 /* disable interrupt */
912 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
913 /* reset */
914 cm->ctrl &= ~chen;
915 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
916 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
917 rec->needs_silencing = rec->is_dac;
918 break;
919 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
920 case SNDRV_PCM_TRIGGER_SUSPEND:
921 cm->ctrl |= pause;
922 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
923 break;
924 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
925 case SNDRV_PCM_TRIGGER_RESUME:
926 cm->ctrl &= ~pause;
927 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
928 break;
929 default:
930 result = -EINVAL;
931 break;
932 }
933 spin_unlock(&cm->reg_lock);
934 return result;
935}
936
937/*
938 * return the current pointer
939 */
940static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
941 struct snd_pcm_substream *substream)
942{
943 size_t ptr;
944 unsigned int reg, rem, tries;
945
946 if (!rec->running)
947 return 0;
948#if 1 // this seems better..
949 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
950 for (tries = 0; tries < 3; tries++) {
951 rem = snd_cmipci_read_w(cm, reg);
952 if (rem < rec->dma_size)
953 goto ok;
954 }
955 dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem);
956 return SNDRV_PCM_POS_XRUN;
957ok:
958 ptr = (rec->dma_size - (rem + 1)) >> rec->shift;
959#else
960 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
961 ptr = snd_cmipci_read(cm, reg) - rec->offset;
962 ptr = bytes_to_frames(substream->runtime, ptr);
963#endif
964 if (substream->runtime->channels > 2)
965 ptr = (ptr * 2) / substream->runtime->channels;
966 return ptr;
967}
968
969/*
970 * playback
971 */
972
973static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
974 int cmd)
975{
976 struct cmipci *cm = snd_pcm_substream_chip(substream);
977 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
978}
979
980static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
981{
982 struct cmipci *cm = snd_pcm_substream_chip(substream);
983 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
984}
985
986
987
988/*
989 * capture
990 */
991
992static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
993 int cmd)
994{
995 struct cmipci *cm = snd_pcm_substream_chip(substream);
996 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
997}
998
999static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
1000{
1001 struct cmipci *cm = snd_pcm_substream_chip(substream);
1002 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
1003}
1004
1005
1006/*
1007 * hw preparation for spdif
1008 */
1009
1010static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
1011 struct snd_ctl_elem_info *uinfo)
1012{
1013 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1014 uinfo->count = 1;
1015 return 0;
1016}
1017
1018static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
1019 struct snd_ctl_elem_value *ucontrol)
1020{
1021 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1022 int i;
1023
1024 spin_lock_irq(&chip->reg_lock);
1025 for (i = 0; i < 4; i++)
1026 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
1027 spin_unlock_irq(&chip->reg_lock);
1028 return 0;
1029}
1030
1031static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1032 struct snd_ctl_elem_value *ucontrol)
1033{
1034 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1035 int i, change;
1036 unsigned int val;
1037
1038 val = 0;
1039 spin_lock_irq(&chip->reg_lock);
1040 for (i = 0; i < 4; i++)
1041 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1042 change = val != chip->dig_status;
1043 chip->dig_status = val;
1044 spin_unlock_irq(&chip->reg_lock);
1045 return change;
1046}
1047
1048static struct snd_kcontrol_new snd_cmipci_spdif_default =
1049{
1050 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1051 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1052 .info = snd_cmipci_spdif_default_info,
1053 .get = snd_cmipci_spdif_default_get,
1054 .put = snd_cmipci_spdif_default_put
1055};
1056
1057static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1058 struct snd_ctl_elem_info *uinfo)
1059{
1060 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1061 uinfo->count = 1;
1062 return 0;
1063}
1064
1065static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1066 struct snd_ctl_elem_value *ucontrol)
1067{
1068 ucontrol->value.iec958.status[0] = 0xff;
1069 ucontrol->value.iec958.status[1] = 0xff;
1070 ucontrol->value.iec958.status[2] = 0xff;
1071 ucontrol->value.iec958.status[3] = 0xff;
1072 return 0;
1073}
1074
1075static struct snd_kcontrol_new snd_cmipci_spdif_mask =
1076{
1077 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1078 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1079 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1080 .info = snd_cmipci_spdif_mask_info,
1081 .get = snd_cmipci_spdif_mask_get,
1082};
1083
1084static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1085 struct snd_ctl_elem_info *uinfo)
1086{
1087 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1088 uinfo->count = 1;
1089 return 0;
1090}
1091
1092static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1093 struct snd_ctl_elem_value *ucontrol)
1094{
1095 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1096 int i;
1097
1098 spin_lock_irq(&chip->reg_lock);
1099 for (i = 0; i < 4; i++)
1100 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1101 spin_unlock_irq(&chip->reg_lock);
1102 return 0;
1103}
1104
1105static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1106 struct snd_ctl_elem_value *ucontrol)
1107{
1108 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1109 int i, change;
1110 unsigned int val;
1111
1112 val = 0;
1113 spin_lock_irq(&chip->reg_lock);
1114 for (i = 0; i < 4; i++)
1115 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1116 change = val != chip->dig_pcm_status;
1117 chip->dig_pcm_status = val;
1118 spin_unlock_irq(&chip->reg_lock);
1119 return change;
1120}
1121
1122static struct snd_kcontrol_new snd_cmipci_spdif_stream =
1123{
1124 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1125 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1126 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1127 .info = snd_cmipci_spdif_stream_info,
1128 .get = snd_cmipci_spdif_stream_get,
1129 .put = snd_cmipci_spdif_stream_put
1130};
1131
1132/*
1133 */
1134
1135/* save mixer setting and mute for AC3 playback */
1136static int save_mixer_state(struct cmipci *cm)
1137{
1138 if (! cm->mixer_insensitive) {
1139 struct snd_ctl_elem_value *val;
1140 unsigned int i;
1141
1142 val = kmalloc(sizeof(*val), GFP_ATOMIC);
1143 if (!val)
1144 return -ENOMEM;
1145 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1146 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1147 if (ctl) {
1148 int event;
1149 memset(val, 0, sizeof(*val));
1150 ctl->get(ctl, val);
1151 cm->mixer_res_status[i] = val->value.integer.value[0];
1152 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1153 event = SNDRV_CTL_EVENT_MASK_INFO;
1154 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1155 ctl->put(ctl, val); /* toggle */
1156 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1157 }
1158 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1159 snd_ctl_notify(cm->card, event, &ctl->id);
1160 }
1161 }
1162 kfree(val);
1163 cm->mixer_insensitive = 1;
1164 }
1165 return 0;
1166}
1167
1168
1169/* restore the previously saved mixer status */
1170static void restore_mixer_state(struct cmipci *cm)
1171{
1172 if (cm->mixer_insensitive) {
1173 struct snd_ctl_elem_value *val;
1174 unsigned int i;
1175
1176 val = kmalloc(sizeof(*val), GFP_KERNEL);
1177 if (!val)
1178 return;
1179 cm->mixer_insensitive = 0; /* at first clear this;
1180 otherwise the changes will be ignored */
1181 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1182 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1183 if (ctl) {
1184 int event;
1185
1186 memset(val, 0, sizeof(*val));
1187 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1188 ctl->get(ctl, val);
1189 event = SNDRV_CTL_EVENT_MASK_INFO;
1190 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1191 val->value.integer.value[0] = cm->mixer_res_status[i];
1192 ctl->put(ctl, val);
1193 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1194 }
1195 snd_ctl_notify(cm->card, event, &ctl->id);
1196 }
1197 }
1198 kfree(val);
1199 }
1200}
1201
1202/* spinlock held! */
1203static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1204{
1205 if (do_ac3) {
1206 /* AC3EN for 037 */
1207 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1208 /* AC3EN for 039 */
1209 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1210
1211 if (cm->can_ac3_hw) {
1212 /* SPD24SEL for 037, 0x02 */
1213 /* SPD24SEL for 039, 0x20, but cannot be set */
1214 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1215 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1216 } else { /* can_ac3_sw */
1217 /* SPD32SEL for 037 & 039, 0x20 */
1218 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1219 /* set 176K sample rate to fix 033 HW bug */
1220 if (cm->chip_version == 33) {
1221 if (rate >= 48000) {
1222 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1223 } else {
1224 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1225 }
1226 }
1227 }
1228
1229 } else {
1230 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1231 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1232
1233 if (cm->can_ac3_hw) {
1234 /* chip model >= 37 */
1235 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1236 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1237 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1238 } else {
1239 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1240 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1241 }
1242 } else {
1243 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1244 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1245 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1246 }
1247 }
1248}
1249
1250static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1251{
1252 int rate, err;
1253
1254 rate = subs->runtime->rate;
1255
1256 if (up && do_ac3)
1257 if ((err = save_mixer_state(cm)) < 0)
1258 return err;
1259
1260 spin_lock_irq(&cm->reg_lock);
1261 cm->spdif_playback_avail = up;
1262 if (up) {
1263 /* they are controlled via "IEC958 Output Switch" */
1264 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1265 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1266 if (cm->spdif_playback_enabled)
1267 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1268 setup_ac3(cm, subs, do_ac3, rate);
1269
1270 if (rate == 48000 || rate == 96000)
1271 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1272 else
1273 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1274 if (rate > 48000)
1275 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1276 else
1277 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1278 } else {
1279 /* they are controlled via "IEC958 Output Switch" */
1280 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1281 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1282 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1283 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1284 setup_ac3(cm, subs, 0, 0);
1285 }
1286 spin_unlock_irq(&cm->reg_lock);
1287 return 0;
1288}
1289
1290
1291/*
1292 * preparation
1293 */
1294
1295/* playback - enable spdif only on the certain condition */
1296static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1297{
1298 struct cmipci *cm = snd_pcm_substream_chip(substream);
1299 int rate = substream->runtime->rate;
1300 int err, do_spdif, do_ac3 = 0;
1301
1302 do_spdif = (rate >= 44100 && rate <= 96000 &&
1303 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1304 substream->runtime->channels == 2);
1305 if (do_spdif && cm->can_ac3_hw)
1306 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1307 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1308 return err;
1309 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1310}
1311
1312/* playback (via device #2) - enable spdif always */
1313static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1314{
1315 struct cmipci *cm = snd_pcm_substream_chip(substream);
1316 int err, do_ac3;
1317
1318 if (cm->can_ac3_hw)
1319 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1320 else
1321 do_ac3 = 1; /* doesn't matter */
1322 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1323 return err;
1324 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1325}
1326
1327/*
1328 * Apparently, the samples last played on channel A stay in some buffer, even
1329 * after the channel is reset, and get added to the data for the rear DACs when
1330 * playing a multichannel stream on channel B. This is likely to generate
1331 * wraparounds and thus distortions.
1332 * To avoid this, we play at least one zero sample after the actual stream has
1333 * stopped.
1334 */
1335static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1336{
1337 struct snd_pcm_runtime *runtime = rec->substream->runtime;
1338 unsigned int reg, val;
1339
1340 if (rec->needs_silencing && runtime && runtime->dma_area) {
1341 /* set up a small silence buffer */
1342 memset(runtime->dma_area, 0, PAGE_SIZE);
1343 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1344 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1345 snd_cmipci_write(cm, reg, val);
1346
1347 /* configure for 16 bits, 2 channels, 8 kHz */
1348 if (runtime->channels > 2)
1349 set_dac_channels(cm, rec, 2);
1350 spin_lock_irq(&cm->reg_lock);
1351 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1352 val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1353 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1354 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1355 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1356 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1357 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1358 if (cm->can_96k)
1359 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
1360 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1361
1362 /* start stream (we don't need interrupts) */
1363 cm->ctrl |= CM_CHEN0 << rec->ch;
1364 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1365 spin_unlock_irq(&cm->reg_lock);
1366
1367 msleep(1);
1368
1369 /* stop and reset stream */
1370 spin_lock_irq(&cm->reg_lock);
1371 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1372 val = CM_RST_CH0 << rec->ch;
1373 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1374 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1375 spin_unlock_irq(&cm->reg_lock);
1376
1377 rec->needs_silencing = 0;
1378 }
1379}
1380
1381static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1382{
1383 struct cmipci *cm = snd_pcm_substream_chip(substream);
1384 setup_spdif_playback(cm, substream, 0, 0);
1385 restore_mixer_state(cm);
1386 snd_cmipci_silence_hack(cm, &cm->channel[0]);
1387 return snd_cmipci_hw_free(substream);
1388}
1389
1390static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1391{
1392 struct cmipci *cm = snd_pcm_substream_chip(substream);
1393 snd_cmipci_silence_hack(cm, &cm->channel[1]);
1394 return snd_cmipci_hw_free(substream);
1395}
1396
1397/* capture */
1398static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1399{
1400 struct cmipci *cm = snd_pcm_substream_chip(substream);
1401 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1402}
1403
1404/* capture with spdif (via device #2) */
1405static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1406{
1407 struct cmipci *cm = snd_pcm_substream_chip(substream);
1408
1409 spin_lock_irq(&cm->reg_lock);
1410 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1411 if (cm->can_96k) {
1412 if (substream->runtime->rate > 48000)
1413 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1414 else
1415 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1416 }
1417 if (snd_pcm_format_width(substream->runtime->format) > 16)
1418 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1419 else
1420 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1421
1422 spin_unlock_irq(&cm->reg_lock);
1423
1424 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1425}
1426
1427static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1428{
1429 struct cmipci *cm = snd_pcm_substream_chip(subs);
1430
1431 spin_lock_irq(&cm->reg_lock);
1432 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1433 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1434 spin_unlock_irq(&cm->reg_lock);
1435
1436 return snd_cmipci_hw_free(subs);
1437}
1438
1439
1440/*
1441 * interrupt handler
1442 */
1443static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1444{
1445 struct cmipci *cm = dev_id;
1446 unsigned int status, mask = 0;
1447
1448 /* fastpath out, to ease interrupt sharing */
1449 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1450 if (!(status & CM_INTR))
1451 return IRQ_NONE;
1452
1453 /* acknowledge interrupt */
1454 spin_lock(&cm->reg_lock);
1455 if (status & CM_CHINT0)
1456 mask |= CM_CH0_INT_EN;
1457 if (status & CM_CHINT1)
1458 mask |= CM_CH1_INT_EN;
1459 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1460 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1461 spin_unlock(&cm->reg_lock);
1462
1463 if (cm->rmidi && (status & CM_UARTINT))
1464 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1465
1466 if (cm->pcm) {
1467 if ((status & CM_CHINT0) && cm->channel[0].running)
1468 snd_pcm_period_elapsed(cm->channel[0].substream);
1469 if ((status & CM_CHINT1) && cm->channel[1].running)
1470 snd_pcm_period_elapsed(cm->channel[1].substream);
1471 }
1472 return IRQ_HANDLED;
1473}
1474
1475/*
1476 * h/w infos
1477 */
1478
1479/* playback on channel A */
1480static struct snd_pcm_hardware snd_cmipci_playback =
1481{
1482 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1483 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1484 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1485 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1486 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1487 .rate_min = 5512,
1488 .rate_max = 48000,
1489 .channels_min = 1,
1490 .channels_max = 2,
1491 .buffer_bytes_max = (128*1024),
1492 .period_bytes_min = 64,
1493 .period_bytes_max = (128*1024),
1494 .periods_min = 2,
1495 .periods_max = 1024,
1496 .fifo_size = 0,
1497};
1498
1499/* capture on channel B */
1500static struct snd_pcm_hardware snd_cmipci_capture =
1501{
1502 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1503 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1504 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1505 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1506 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1507 .rate_min = 5512,
1508 .rate_max = 48000,
1509 .channels_min = 1,
1510 .channels_max = 2,
1511 .buffer_bytes_max = (128*1024),
1512 .period_bytes_min = 64,
1513 .period_bytes_max = (128*1024),
1514 .periods_min = 2,
1515 .periods_max = 1024,
1516 .fifo_size = 0,
1517};
1518
1519/* playback on channel B - stereo 16bit only? */
1520static struct snd_pcm_hardware snd_cmipci_playback2 =
1521{
1522 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1523 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1524 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1525 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1526 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1527 .rate_min = 5512,
1528 .rate_max = 48000,
1529 .channels_min = 2,
1530 .channels_max = 2,
1531 .buffer_bytes_max = (128*1024),
1532 .period_bytes_min = 64,
1533 .period_bytes_max = (128*1024),
1534 .periods_min = 2,
1535 .periods_max = 1024,
1536 .fifo_size = 0,
1537};
1538
1539/* spdif playback on channel A */
1540static struct snd_pcm_hardware snd_cmipci_playback_spdif =
1541{
1542 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1543 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1544 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1545 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1546 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1547 .rate_min = 44100,
1548 .rate_max = 48000,
1549 .channels_min = 2,
1550 .channels_max = 2,
1551 .buffer_bytes_max = (128*1024),
1552 .period_bytes_min = 64,
1553 .period_bytes_max = (128*1024),
1554 .periods_min = 2,
1555 .periods_max = 1024,
1556 .fifo_size = 0,
1557};
1558
1559/* spdif playback on channel A (32bit, IEC958 subframes) */
1560static struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1561{
1562 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1563 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1564 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1565 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1566 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1567 .rate_min = 44100,
1568 .rate_max = 48000,
1569 .channels_min = 2,
1570 .channels_max = 2,
1571 .buffer_bytes_max = (128*1024),
1572 .period_bytes_min = 64,
1573 .period_bytes_max = (128*1024),
1574 .periods_min = 2,
1575 .periods_max = 1024,
1576 .fifo_size = 0,
1577};
1578
1579/* spdif capture on channel B */
1580static struct snd_pcm_hardware snd_cmipci_capture_spdif =
1581{
1582 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1583 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1584 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1585 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1586 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1587 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1588 .rate_min = 44100,
1589 .rate_max = 48000,
1590 .channels_min = 2,
1591 .channels_max = 2,
1592 .buffer_bytes_max = (128*1024),
1593 .period_bytes_min = 64,
1594 .period_bytes_max = (128*1024),
1595 .periods_min = 2,
1596 .periods_max = 1024,
1597 .fifo_size = 0,
1598};
1599
1600static unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050,
1601 32000, 44100, 48000, 88200, 96000, 128000 };
1602static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1603 .count = ARRAY_SIZE(rate_constraints),
1604 .list = rate_constraints,
1605 .mask = 0,
1606};
1607
1608/*
1609 * check device open/close
1610 */
1611static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1612{
1613 int ch = mode & CM_OPEN_CH_MASK;
1614
1615 /* FIXME: a file should wait until the device becomes free
1616 * when it's opened on blocking mode. however, since the current
1617 * pcm framework doesn't pass file pointer before actually opened,
1618 * we can't know whether blocking mode or not in open callback..
1619 */
1620 mutex_lock(&cm->open_mutex);
1621 if (cm->opened[ch]) {
1622 mutex_unlock(&cm->open_mutex);
1623 return -EBUSY;
1624 }
1625 cm->opened[ch] = mode;
1626 cm->channel[ch].substream = subs;
1627 if (! (mode & CM_OPEN_DAC)) {
1628 /* disable dual DAC mode */
1629 cm->channel[ch].is_dac = 0;
1630 spin_lock_irq(&cm->reg_lock);
1631 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1632 spin_unlock_irq(&cm->reg_lock);
1633 }
1634 mutex_unlock(&cm->open_mutex);
1635 return 0;
1636}
1637
1638static void close_device_check(struct cmipci *cm, int mode)
1639{
1640 int ch = mode & CM_OPEN_CH_MASK;
1641
1642 mutex_lock(&cm->open_mutex);
1643 if (cm->opened[ch] == mode) {
1644 if (cm->channel[ch].substream) {
1645 snd_cmipci_ch_reset(cm, ch);
1646 cm->channel[ch].running = 0;
1647 cm->channel[ch].substream = NULL;
1648 }
1649 cm->opened[ch] = 0;
1650 if (! cm->channel[ch].is_dac) {
1651 /* enable dual DAC mode again */
1652 cm->channel[ch].is_dac = 1;
1653 spin_lock_irq(&cm->reg_lock);
1654 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1655 spin_unlock_irq(&cm->reg_lock);
1656 }
1657 }
1658 mutex_unlock(&cm->open_mutex);
1659}
1660
1661/*
1662 */
1663
1664static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1665{
1666 struct cmipci *cm = snd_pcm_substream_chip(substream);
1667 struct snd_pcm_runtime *runtime = substream->runtime;
1668 int err;
1669
1670 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1671 return err;
1672 runtime->hw = snd_cmipci_playback;
1673 if (cm->chip_version == 68) {
1674 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1675 SNDRV_PCM_RATE_96000;
1676 runtime->hw.rate_max = 96000;
1677 } else if (cm->chip_version == 55) {
1678 err = snd_pcm_hw_constraint_list(runtime, 0,
1679 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1680 if (err < 0)
1681 return err;
1682 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1683 runtime->hw.rate_max = 128000;
1684 }
1685 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1686 cm->dig_pcm_status = cm->dig_status;
1687 return 0;
1688}
1689
1690static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1691{
1692 struct cmipci *cm = snd_pcm_substream_chip(substream);
1693 struct snd_pcm_runtime *runtime = substream->runtime;
1694 int err;
1695
1696 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1697 return err;
1698 runtime->hw = snd_cmipci_capture;
1699 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1700 runtime->hw.rate_min = 41000;
1701 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1702 } else if (cm->chip_version == 55) {
1703 err = snd_pcm_hw_constraint_list(runtime, 0,
1704 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1705 if (err < 0)
1706 return err;
1707 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1708 runtime->hw.rate_max = 128000;
1709 }
1710 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1711 return 0;
1712}
1713
1714static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1715{
1716 struct cmipci *cm = snd_pcm_substream_chip(substream);
1717 struct snd_pcm_runtime *runtime = substream->runtime;
1718 int err;
1719
1720 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1721 return err;
1722 runtime->hw = snd_cmipci_playback2;
1723 mutex_lock(&cm->open_mutex);
1724 if (! cm->opened[CM_CH_PLAY]) {
1725 if (cm->can_multi_ch) {
1726 runtime->hw.channels_max = cm->max_channels;
1727 if (cm->max_channels == 4)
1728 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1729 else if (cm->max_channels == 6)
1730 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1731 else if (cm->max_channels == 8)
1732 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1733 }
1734 }
1735 mutex_unlock(&cm->open_mutex);
1736 if (cm->chip_version == 68) {
1737 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1738 SNDRV_PCM_RATE_96000;
1739 runtime->hw.rate_max = 96000;
1740 } else if (cm->chip_version == 55) {
1741 err = snd_pcm_hw_constraint_list(runtime, 0,
1742 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1743 if (err < 0)
1744 return err;
1745 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1746 runtime->hw.rate_max = 128000;
1747 }
1748 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1749 return 0;
1750}
1751
1752static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1753{
1754 struct cmipci *cm = snd_pcm_substream_chip(substream);
1755 struct snd_pcm_runtime *runtime = substream->runtime;
1756 int err;
1757
1758 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1759 return err;
1760 if (cm->can_ac3_hw) {
1761 runtime->hw = snd_cmipci_playback_spdif;
1762 if (cm->chip_version >= 37) {
1763 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1764 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1765 }
1766 if (cm->can_96k) {
1767 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1768 SNDRV_PCM_RATE_96000;
1769 runtime->hw.rate_max = 96000;
1770 }
1771 } else {
1772 runtime->hw = snd_cmipci_playback_iec958_subframe;
1773 }
1774 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1775 cm->dig_pcm_status = cm->dig_status;
1776 return 0;
1777}
1778
1779static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1780{
1781 struct cmipci *cm = snd_pcm_substream_chip(substream);
1782 struct snd_pcm_runtime *runtime = substream->runtime;
1783 int err;
1784
1785 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1786 return err;
1787 runtime->hw = snd_cmipci_capture_spdif;
1788 if (cm->can_96k && !(cm->chip_version == 68)) {
1789 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1790 SNDRV_PCM_RATE_96000;
1791 runtime->hw.rate_max = 96000;
1792 }
1793 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1794 return 0;
1795}
1796
1797
1798/*
1799 */
1800
1801static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1802{
1803 struct cmipci *cm = snd_pcm_substream_chip(substream);
1804 close_device_check(cm, CM_OPEN_PLAYBACK);
1805 return 0;
1806}
1807
1808static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1809{
1810 struct cmipci *cm = snd_pcm_substream_chip(substream);
1811 close_device_check(cm, CM_OPEN_CAPTURE);
1812 return 0;
1813}
1814
1815static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1816{
1817 struct cmipci *cm = snd_pcm_substream_chip(substream);
1818 close_device_check(cm, CM_OPEN_PLAYBACK2);
1819 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1820 return 0;
1821}
1822
1823static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1824{
1825 struct cmipci *cm = snd_pcm_substream_chip(substream);
1826 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1827 return 0;
1828}
1829
1830static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1831{
1832 struct cmipci *cm = snd_pcm_substream_chip(substream);
1833 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1834 return 0;
1835}
1836
1837
1838/*
1839 */
1840
1841static struct snd_pcm_ops snd_cmipci_playback_ops = {
1842 .open = snd_cmipci_playback_open,
1843 .close = snd_cmipci_playback_close,
1844 .ioctl = snd_pcm_lib_ioctl,
1845 .hw_params = snd_cmipci_hw_params,
1846 .hw_free = snd_cmipci_playback_hw_free,
1847 .prepare = snd_cmipci_playback_prepare,
1848 .trigger = snd_cmipci_playback_trigger,
1849 .pointer = snd_cmipci_playback_pointer,
1850};
1851
1852static struct snd_pcm_ops snd_cmipci_capture_ops = {
1853 .open = snd_cmipci_capture_open,
1854 .close = snd_cmipci_capture_close,
1855 .ioctl = snd_pcm_lib_ioctl,
1856 .hw_params = snd_cmipci_hw_params,
1857 .hw_free = snd_cmipci_hw_free,
1858 .prepare = snd_cmipci_capture_prepare,
1859 .trigger = snd_cmipci_capture_trigger,
1860 .pointer = snd_cmipci_capture_pointer,
1861};
1862
1863static struct snd_pcm_ops snd_cmipci_playback2_ops = {
1864 .open = snd_cmipci_playback2_open,
1865 .close = snd_cmipci_playback2_close,
1866 .ioctl = snd_pcm_lib_ioctl,
1867 .hw_params = snd_cmipci_playback2_hw_params,
1868 .hw_free = snd_cmipci_playback2_hw_free,
1869 .prepare = snd_cmipci_capture_prepare, /* channel B */
1870 .trigger = snd_cmipci_capture_trigger, /* channel B */
1871 .pointer = snd_cmipci_capture_pointer, /* channel B */
1872};
1873
1874static struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1875 .open = snd_cmipci_playback_spdif_open,
1876 .close = snd_cmipci_playback_spdif_close,
1877 .ioctl = snd_pcm_lib_ioctl,
1878 .hw_params = snd_cmipci_hw_params,
1879 .hw_free = snd_cmipci_playback_hw_free,
1880 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1881 .trigger = snd_cmipci_playback_trigger,
1882 .pointer = snd_cmipci_playback_pointer,
1883};
1884
1885static struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1886 .open = snd_cmipci_capture_spdif_open,
1887 .close = snd_cmipci_capture_spdif_close,
1888 .ioctl = snd_pcm_lib_ioctl,
1889 .hw_params = snd_cmipci_hw_params,
1890 .hw_free = snd_cmipci_capture_spdif_hw_free,
1891 .prepare = snd_cmipci_capture_spdif_prepare,
1892 .trigger = snd_cmipci_capture_trigger,
1893 .pointer = snd_cmipci_capture_pointer,
1894};
1895
1896
1897/*
1898 */
1899
1900static int snd_cmipci_pcm_new(struct cmipci *cm, int device)
1901{
1902 struct snd_pcm *pcm;
1903 int err;
1904
1905 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1906 if (err < 0)
1907 return err;
1908
1909 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1910 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1911
1912 pcm->private_data = cm;
1913 pcm->info_flags = 0;
1914 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1915 cm->pcm = pcm;
1916
1917 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1918 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1919
1920 return 0;
1921}
1922
1923static int snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1924{
1925 struct snd_pcm *pcm;
1926 int err;
1927
1928 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1929 if (err < 0)
1930 return err;
1931
1932 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1933
1934 pcm->private_data = cm;
1935 pcm->info_flags = 0;
1936 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1937 cm->pcm2 = pcm;
1938
1939 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1940 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1941
1942 return 0;
1943}
1944
1945static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1946{
1947 struct snd_pcm *pcm;
1948 int err;
1949
1950 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1951 if (err < 0)
1952 return err;
1953
1954 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1955 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1956
1957 pcm->private_data = cm;
1958 pcm->info_flags = 0;
1959 strcpy(pcm->name, "C-Media PCI IEC958");
1960 cm->pcm_spdif = pcm;
1961
1962 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1963 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1964
1965 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1966 snd_pcm_alt_chmaps, cm->max_channels, 0,
1967 NULL);
1968 if (err < 0)
1969 return err;
1970
1971 return 0;
1972}
1973
1974/*
1975 * mixer interface:
1976 * - CM8338/8738 has a compatible mixer interface with SB16, but
1977 * lack of some elements like tone control, i/o gain and AGC.
1978 * - Access to native registers:
1979 * - A 3D switch
1980 * - Output mute switches
1981 */
1982
1983static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1984{
1985 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1986 outb(data, s->iobase + CM_REG_SB16_DATA);
1987}
1988
1989static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1990{
1991 unsigned char v;
1992
1993 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1994 v = inb(s->iobase + CM_REG_SB16_DATA);
1995 return v;
1996}
1997
1998/*
1999 * general mixer element
2000 */
2001struct cmipci_sb_reg {
2002 unsigned int left_reg, right_reg;
2003 unsigned int left_shift, right_shift;
2004 unsigned int mask;
2005 unsigned int invert: 1;
2006 unsigned int stereo: 1;
2007};
2008
2009#define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
2010 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
2011
2012#define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
2013{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2014 .info = snd_cmipci_info_volume, \
2015 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
2016 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
2017}
2018
2019#define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
2020#define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
2021#define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
2022#define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
2023
2024static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
2025{
2026 r->left_reg = val & 0xff;
2027 r->right_reg = (val >> 8) & 0xff;
2028 r->left_shift = (val >> 16) & 0x07;
2029 r->right_shift = (val >> 19) & 0x07;
2030 r->invert = (val >> 22) & 1;
2031 r->stereo = (val >> 23) & 1;
2032 r->mask = (val >> 24) & 0xff;
2033}
2034
2035static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
2036 struct snd_ctl_elem_info *uinfo)
2037{
2038 struct cmipci_sb_reg reg;
2039
2040 cmipci_sb_reg_decode(®, kcontrol->private_value);
2041 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2042 uinfo->count = reg.stereo + 1;
2043 uinfo->value.integer.min = 0;
2044 uinfo->value.integer.max = reg.mask;
2045 return 0;
2046}
2047
2048static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
2049 struct snd_ctl_elem_value *ucontrol)
2050{
2051 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2052 struct cmipci_sb_reg reg;
2053 int val;
2054
2055 cmipci_sb_reg_decode(®, kcontrol->private_value);
2056 spin_lock_irq(&cm->reg_lock);
2057 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
2058 if (reg.invert)
2059 val = reg.mask - val;
2060 ucontrol->value.integer.value[0] = val;
2061 if (reg.stereo) {
2062 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
2063 if (reg.invert)
2064 val = reg.mask - val;
2065 ucontrol->value.integer.value[1] = val;
2066 }
2067 spin_unlock_irq(&cm->reg_lock);
2068 return 0;
2069}
2070
2071static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
2072 struct snd_ctl_elem_value *ucontrol)
2073{
2074 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2075 struct cmipci_sb_reg reg;
2076 int change;
2077 int left, right, oleft, oright;
2078
2079 cmipci_sb_reg_decode(®, kcontrol->private_value);
2080 left = ucontrol->value.integer.value[0] & reg.mask;
2081 if (reg.invert)
2082 left = reg.mask - left;
2083 left <<= reg.left_shift;
2084 if (reg.stereo) {
2085 right = ucontrol->value.integer.value[1] & reg.mask;
2086 if (reg.invert)
2087 right = reg.mask - right;
2088 right <<= reg.right_shift;
2089 } else
2090 right = 0;
2091 spin_lock_irq(&cm->reg_lock);
2092 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2093 left |= oleft & ~(reg.mask << reg.left_shift);
2094 change = left != oleft;
2095 if (reg.stereo) {
2096 if (reg.left_reg != reg.right_reg) {
2097 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2098 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2099 } else
2100 oright = left;
2101 right |= oright & ~(reg.mask << reg.right_shift);
2102 change |= right != oright;
2103 snd_cmipci_mixer_write(cm, reg.right_reg, right);
2104 } else
2105 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2106 spin_unlock_irq(&cm->reg_lock);
2107 return change;
2108}
2109
2110/*
2111 * input route (left,right) -> (left,right)
2112 */
2113#define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2114{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2115 .info = snd_cmipci_info_input_sw, \
2116 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2117 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2118}
2119
2120static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
2121 struct snd_ctl_elem_info *uinfo)
2122{
2123 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2124 uinfo->count = 4;
2125 uinfo->value.integer.min = 0;
2126 uinfo->value.integer.max = 1;
2127 return 0;
2128}
2129
2130static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2131 struct snd_ctl_elem_value *ucontrol)
2132{
2133 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2134 struct cmipci_sb_reg reg;
2135 int val1, val2;
2136
2137 cmipci_sb_reg_decode(®, kcontrol->private_value);
2138 spin_lock_irq(&cm->reg_lock);
2139 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2140 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2141 spin_unlock_irq(&cm->reg_lock);
2142 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2143 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2144 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2145 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2146 return 0;
2147}
2148
2149static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2150 struct snd_ctl_elem_value *ucontrol)
2151{
2152 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2153 struct cmipci_sb_reg reg;
2154 int change;
2155 int val1, val2, oval1, oval2;
2156
2157 cmipci_sb_reg_decode(®, kcontrol->private_value);
2158 spin_lock_irq(&cm->reg_lock);
2159 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2160 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2161 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2162 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2163 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2164 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2165 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2166 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2167 change = val1 != oval1 || val2 != oval2;
2168 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2169 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2170 spin_unlock_irq(&cm->reg_lock);
2171 return change;
2172}
2173
2174/*
2175 * native mixer switches/volumes
2176 */
2177
2178#define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2179{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2180 .info = snd_cmipci_info_native_mixer, \
2181 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2182 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2183}
2184
2185#define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2186{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2187 .info = snd_cmipci_info_native_mixer, \
2188 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2189 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2190}
2191
2192#define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2193{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2194 .info = snd_cmipci_info_native_mixer, \
2195 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2196 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2197}
2198
2199#define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2200{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2201 .info = snd_cmipci_info_native_mixer, \
2202 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2203 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2204}
2205
2206static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2207 struct snd_ctl_elem_info *uinfo)
2208{
2209 struct cmipci_sb_reg reg;
2210
2211 cmipci_sb_reg_decode(®, kcontrol->private_value);
2212 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2213 uinfo->count = reg.stereo + 1;
2214 uinfo->value.integer.min = 0;
2215 uinfo->value.integer.max = reg.mask;
2216 return 0;
2217
2218}
2219
2220static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2221 struct snd_ctl_elem_value *ucontrol)
2222{
2223 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2224 struct cmipci_sb_reg reg;
2225 unsigned char oreg, val;
2226
2227 cmipci_sb_reg_decode(®, kcontrol->private_value);
2228 spin_lock_irq(&cm->reg_lock);
2229 oreg = inb(cm->iobase + reg.left_reg);
2230 val = (oreg >> reg.left_shift) & reg.mask;
2231 if (reg.invert)
2232 val = reg.mask - val;
2233 ucontrol->value.integer.value[0] = val;
2234 if (reg.stereo) {
2235 val = (oreg >> reg.right_shift) & reg.mask;
2236 if (reg.invert)
2237 val = reg.mask - val;
2238 ucontrol->value.integer.value[1] = val;
2239 }
2240 spin_unlock_irq(&cm->reg_lock);
2241 return 0;
2242}
2243
2244static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2245 struct snd_ctl_elem_value *ucontrol)
2246{
2247 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2248 struct cmipci_sb_reg reg;
2249 unsigned char oreg, nreg, val;
2250
2251 cmipci_sb_reg_decode(®, kcontrol->private_value);
2252 spin_lock_irq(&cm->reg_lock);
2253 oreg = inb(cm->iobase + reg.left_reg);
2254 val = ucontrol->value.integer.value[0] & reg.mask;
2255 if (reg.invert)
2256 val = reg.mask - val;
2257 nreg = oreg & ~(reg.mask << reg.left_shift);
2258 nreg |= (val << reg.left_shift);
2259 if (reg.stereo) {
2260 val = ucontrol->value.integer.value[1] & reg.mask;
2261 if (reg.invert)
2262 val = reg.mask - val;
2263 nreg &= ~(reg.mask << reg.right_shift);
2264 nreg |= (val << reg.right_shift);
2265 }
2266 outb(nreg, cm->iobase + reg.left_reg);
2267 spin_unlock_irq(&cm->reg_lock);
2268 return (nreg != oreg);
2269}
2270
2271/*
2272 * special case - check mixer sensitivity
2273 */
2274static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2275 struct snd_ctl_elem_value *ucontrol)
2276{
2277 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2278 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2279}
2280
2281static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2282 struct snd_ctl_elem_value *ucontrol)
2283{
2284 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2285 if (cm->mixer_insensitive) {
2286 /* ignored */
2287 return 0;
2288 }
2289 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2290}
2291
2292
2293static struct snd_kcontrol_new snd_cmipci_mixers[] = {
2294 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2295 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2296 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2297 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2298 { /* switch with sensitivity */
2299 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2300 .name = "PCM Playback Switch",
2301 .info = snd_cmipci_info_native_mixer,
2302 .get = snd_cmipci_get_native_mixer_sensitive,
2303 .put = snd_cmipci_put_native_mixer_sensitive,
2304 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2305 },
2306 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2307 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2308 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2309 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2310 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2311 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2312 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2313 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2314 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2315 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2316 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2317 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2318 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2319 CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2320 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2321 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2322 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2323 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2324 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2325 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2326 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2327 CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2328 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2329};
2330
2331/*
2332 * other switches
2333 */
2334
2335struct cmipci_switch_args {
2336 int reg; /* register index */
2337 unsigned int mask; /* mask bits */
2338 unsigned int mask_on; /* mask bits to turn on */
2339 unsigned int is_byte: 1; /* byte access? */
2340 unsigned int ac3_sensitive: 1; /* access forbidden during
2341 * non-audio operation?
2342 */
2343};
2344
2345#define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
2346
2347static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2348 struct snd_ctl_elem_value *ucontrol,
2349 struct cmipci_switch_args *args)
2350{
2351 unsigned int val;
2352 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2353
2354 spin_lock_irq(&cm->reg_lock);
2355 if (args->ac3_sensitive && cm->mixer_insensitive) {
2356 ucontrol->value.integer.value[0] = 0;
2357 spin_unlock_irq(&cm->reg_lock);
2358 return 0;
2359 }
2360 if (args->is_byte)
2361 val = inb(cm->iobase + args->reg);
2362 else
2363 val = snd_cmipci_read(cm, args->reg);
2364 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2365 spin_unlock_irq(&cm->reg_lock);
2366 return 0;
2367}
2368
2369static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2370 struct snd_ctl_elem_value *ucontrol)
2371{
2372 struct cmipci_switch_args *args;
2373 args = (struct cmipci_switch_args *)kcontrol->private_value;
2374 if (snd_BUG_ON(!args))
2375 return -EINVAL;
2376 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2377}
2378
2379static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2380 struct snd_ctl_elem_value *ucontrol,
2381 struct cmipci_switch_args *args)
2382{
2383 unsigned int val;
2384 int change;
2385 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2386
2387 spin_lock_irq(&cm->reg_lock);
2388 if (args->ac3_sensitive && cm->mixer_insensitive) {
2389 /* ignored */
2390 spin_unlock_irq(&cm->reg_lock);
2391 return 0;
2392 }
2393 if (args->is_byte)
2394 val = inb(cm->iobase + args->reg);
2395 else
2396 val = snd_cmipci_read(cm, args->reg);
2397 change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2398 args->mask_on : (args->mask & ~args->mask_on));
2399 if (change) {
2400 val &= ~args->mask;
2401 if (ucontrol->value.integer.value[0])
2402 val |= args->mask_on;
2403 else
2404 val |= (args->mask & ~args->mask_on);
2405 if (args->is_byte)
2406 outb((unsigned char)val, cm->iobase + args->reg);
2407 else
2408 snd_cmipci_write(cm, args->reg, val);
2409 }
2410 spin_unlock_irq(&cm->reg_lock);
2411 return change;
2412}
2413
2414static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2415 struct snd_ctl_elem_value *ucontrol)
2416{
2417 struct cmipci_switch_args *args;
2418 args = (struct cmipci_switch_args *)kcontrol->private_value;
2419 if (snd_BUG_ON(!args))
2420 return -EINVAL;
2421 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2422}
2423
2424#define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2425static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2426 .reg = xreg, \
2427 .mask = xmask, \
2428 .mask_on = xmask_on, \
2429 .is_byte = xis_byte, \
2430 .ac3_sensitive = xac3, \
2431}
2432
2433#define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2434 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2435
2436#if 0 /* these will be controlled in pcm device */
2437DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2438DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2439#endif
2440DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2441DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2442DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2443DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2444DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2445DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2446DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2447DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2448// DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2449DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2450DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2451/* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2452DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2453DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2454#if CM_CH_PLAY == 1
2455DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2456#else
2457DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2458#endif
2459DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2460// DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2461// DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2462// DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2463DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2464
2465#define DEFINE_SWITCH(sname, stype, sarg) \
2466{ .name = sname, \
2467 .iface = stype, \
2468 .info = snd_cmipci_uswitch_info, \
2469 .get = snd_cmipci_uswitch_get, \
2470 .put = snd_cmipci_uswitch_put, \
2471 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2472}
2473
2474#define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2475#define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2476
2477
2478/*
2479 * callbacks for spdif output switch
2480 * needs toggle two registers..
2481 */
2482static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2483 struct snd_ctl_elem_value *ucontrol)
2484{
2485 int changed;
2486 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2487 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2488 return changed;
2489}
2490
2491static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2492 struct snd_ctl_elem_value *ucontrol)
2493{
2494 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2495 int changed;
2496 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2497 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2498 if (changed) {
2499 if (ucontrol->value.integer.value[0]) {
2500 if (chip->spdif_playback_avail)
2501 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2502 } else {
2503 if (chip->spdif_playback_avail)
2504 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2505 }
2506 }
2507 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2508 return changed;
2509}
2510
2511
2512static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2513 struct snd_ctl_elem_info *uinfo)
2514{
2515 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2516 static const char *const texts[3] = {
2517 "Line-In", "Rear Output", "Bass Output"
2518 };
2519
2520 return snd_ctl_enum_info(uinfo, 1,
2521 cm->chip_version >= 39 ? 3 : 2, texts);
2522}
2523
2524static inline unsigned int get_line_in_mode(struct cmipci *cm)
2525{
2526 unsigned int val;
2527 if (cm->chip_version >= 39) {
2528 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2529 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2530 return 2;
2531 }
2532 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2533 if (val & CM_REAR2LIN)
2534 return 1;
2535 return 0;
2536}
2537
2538static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2539 struct snd_ctl_elem_value *ucontrol)
2540{
2541 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2542
2543 spin_lock_irq(&cm->reg_lock);
2544 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2545 spin_unlock_irq(&cm->reg_lock);
2546 return 0;
2547}
2548
2549static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2550 struct snd_ctl_elem_value *ucontrol)
2551{
2552 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2553 int change;
2554
2555 spin_lock_irq(&cm->reg_lock);
2556 if (ucontrol->value.enumerated.item[0] == 2)
2557 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2558 else
2559 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2560 if (ucontrol->value.enumerated.item[0] == 1)
2561 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2562 else
2563 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2564 spin_unlock_irq(&cm->reg_lock);
2565 return change;
2566}
2567
2568static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2569 struct snd_ctl_elem_info *uinfo)
2570{
2571 static const char *const texts[2] = { "Mic-In", "Center/LFE Output" };
2572
2573 return snd_ctl_enum_info(uinfo, 1, 2, texts);
2574}
2575
2576static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2577 struct snd_ctl_elem_value *ucontrol)
2578{
2579 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2580 /* same bit as spdi_phase */
2581 spin_lock_irq(&cm->reg_lock);
2582 ucontrol->value.enumerated.item[0] =
2583 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2584 spin_unlock_irq(&cm->reg_lock);
2585 return 0;
2586}
2587
2588static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2589 struct snd_ctl_elem_value *ucontrol)
2590{
2591 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2592 int change;
2593
2594 spin_lock_irq(&cm->reg_lock);
2595 if (ucontrol->value.enumerated.item[0])
2596 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2597 else
2598 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2599 spin_unlock_irq(&cm->reg_lock);
2600 return change;
2601}
2602
2603/* both for CM8338/8738 */
2604static struct snd_kcontrol_new snd_cmipci_mixer_switches[] = {
2605 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2606 {
2607 .name = "Line-In Mode",
2608 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2609 .info = snd_cmipci_line_in_mode_info,
2610 .get = snd_cmipci_line_in_mode_get,
2611 .put = snd_cmipci_line_in_mode_put,
2612 },
2613};
2614
2615/* for non-multichannel chips */
2616static struct snd_kcontrol_new snd_cmipci_nomulti_switch =
2617DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2618
2619/* only for CM8738 */
2620static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] = {
2621#if 0 /* controlled in pcm device */
2622 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2623 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2624 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2625#endif
2626 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2627 { .name = "IEC958 Output Switch",
2628 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2629 .info = snd_cmipci_uswitch_info,
2630 .get = snd_cmipci_spdout_enable_get,
2631 .put = snd_cmipci_spdout_enable_put,
2632 },
2633 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2634 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2635 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2636// DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2637 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2638 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2639};
2640
2641/* only for model 033/037 */
2642static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] = {
2643 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2644 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2645 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2646};
2647
2648/* only for model 039 or later */
2649static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] = {
2650 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2651 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2652 {
2653 .name = "Mic-In Mode",
2654 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2655 .info = snd_cmipci_mic_in_mode_info,
2656 .get = snd_cmipci_mic_in_mode_get,
2657 .put = snd_cmipci_mic_in_mode_put,
2658 }
2659};
2660
2661/* card control switches */
2662static struct snd_kcontrol_new snd_cmipci_modem_switch =
2663DEFINE_CARD_SWITCH("Modem", modem);
2664
2665
2666static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2667{
2668 struct snd_card *card;
2669 struct snd_kcontrol_new *sw;
2670 struct snd_kcontrol *kctl;
2671 unsigned int idx;
2672 int err;
2673
2674 if (snd_BUG_ON(!cm || !cm->card))
2675 return -EINVAL;
2676
2677 card = cm->card;
2678
2679 strcpy(card->mixername, "CMedia PCI");
2680
2681 spin_lock_irq(&cm->reg_lock);
2682 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2683 spin_unlock_irq(&cm->reg_lock);
2684
2685 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2686 if (cm->chip_version == 68) { // 8768 has no PCM volume
2687 if (!strcmp(snd_cmipci_mixers[idx].name,
2688 "PCM Playback Volume"))
2689 continue;
2690 }
2691 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2692 return err;
2693 }
2694
2695 /* mixer switches */
2696 sw = snd_cmipci_mixer_switches;
2697 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2698 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2699 if (err < 0)
2700 return err;
2701 }
2702 if (! cm->can_multi_ch) {
2703 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2704 if (err < 0)
2705 return err;
2706 }
2707 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2708 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2709 sw = snd_cmipci_8738_mixer_switches;
2710 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2711 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2712 if (err < 0)
2713 return err;
2714 }
2715 if (cm->can_ac3_hw) {
2716 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2717 return err;
2718 kctl->id.device = pcm_spdif_device;
2719 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2720 return err;
2721 kctl->id.device = pcm_spdif_device;
2722 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2723 return err;
2724 kctl->id.device = pcm_spdif_device;
2725 }
2726 if (cm->chip_version <= 37) {
2727 sw = snd_cmipci_old_mixer_switches;
2728 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2729 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2730 if (err < 0)
2731 return err;
2732 }
2733 }
2734 }
2735 if (cm->chip_version >= 39) {
2736 sw = snd_cmipci_extra_mixer_switches;
2737 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2738 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2739 if (err < 0)
2740 return err;
2741 }
2742 }
2743
2744 /* card switches */
2745 /*
2746 * newer chips don't have the register bits to force modem link
2747 * detection; the bit that was FLINKON now mutes CH1
2748 */
2749 if (cm->chip_version < 39) {
2750 err = snd_ctl_add(cm->card,
2751 snd_ctl_new1(&snd_cmipci_modem_switch, cm));
2752 if (err < 0)
2753 return err;
2754 }
2755
2756 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2757 struct snd_ctl_elem_id elem_id;
2758 struct snd_kcontrol *ctl;
2759 memset(&elem_id, 0, sizeof(elem_id));
2760 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2761 strcpy(elem_id.name, cm_saved_mixer[idx].name);
2762 ctl = snd_ctl_find_id(cm->card, &elem_id);
2763 if (ctl)
2764 cm->mixer_res_ctl[idx] = ctl;
2765 }
2766
2767 return 0;
2768}
2769
2770
2771/*
2772 * proc interface
2773 */
2774
2775static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2776 struct snd_info_buffer *buffer)
2777{
2778 struct cmipci *cm = entry->private_data;
2779 int i, v;
2780
2781 snd_iprintf(buffer, "%s\n", cm->card->longname);
2782 for (i = 0; i < 0x94; i++) {
2783 if (i == 0x28)
2784 i = 0x90;
2785 v = inb(cm->iobase + i);
2786 if (i % 4 == 0)
2787 snd_iprintf(buffer, "\n%02x:", i);
2788 snd_iprintf(buffer, " %02x", v);
2789 }
2790 snd_iprintf(buffer, "\n");
2791}
2792
2793static void snd_cmipci_proc_init(struct cmipci *cm)
2794{
2795 struct snd_info_entry *entry;
2796
2797 if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2798 snd_info_set_text_ops(entry, cm, snd_cmipci_proc_read);
2799}
2800
2801static const struct pci_device_id snd_cmipci_ids[] = {
2802 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0},
2803 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0},
2804 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2805 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0},
2806 {PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2807 {0,},
2808};
2809
2810
2811/*
2812 * check chip version and capabilities
2813 * driver name is modified according to the chip model
2814 */
2815static void query_chip(struct cmipci *cm)
2816{
2817 unsigned int detect;
2818
2819 /* check reg 0Ch, bit 24-31 */
2820 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2821 if (! detect) {
2822 /* check reg 08h, bit 24-28 */
2823 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2824 switch (detect) {
2825 case 0:
2826 cm->chip_version = 33;
2827 if (cm->do_soft_ac3)
2828 cm->can_ac3_sw = 1;
2829 else
2830 cm->can_ac3_hw = 1;
2831 break;
2832 case CM_CHIP_037:
2833 cm->chip_version = 37;
2834 cm->can_ac3_hw = 1;
2835 break;
2836 default:
2837 cm->chip_version = 39;
2838 cm->can_ac3_hw = 1;
2839 break;
2840 }
2841 cm->max_channels = 2;
2842 } else {
2843 if (detect & CM_CHIP_039) {
2844 cm->chip_version = 39;
2845 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2846 cm->max_channels = 6;
2847 else
2848 cm->max_channels = 4;
2849 } else if (detect & CM_CHIP_8768) {
2850 cm->chip_version = 68;
2851 cm->max_channels = 8;
2852 cm->can_96k = 1;
2853 } else {
2854 cm->chip_version = 55;
2855 cm->max_channels = 6;
2856 cm->can_96k = 1;
2857 }
2858 cm->can_ac3_hw = 1;
2859 cm->can_multi_ch = 1;
2860 }
2861}
2862
2863#ifdef SUPPORT_JOYSTICK
2864static int snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2865{
2866 static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2867 struct gameport *gp;
2868 struct resource *r = NULL;
2869 int i, io_port = 0;
2870
2871 if (joystick_port[dev] == 0)
2872 return -ENODEV;
2873
2874 if (joystick_port[dev] == 1) { /* auto-detect */
2875 for (i = 0; ports[i]; i++) {
2876 io_port = ports[i];
2877 r = request_region(io_port, 1, "CMIPCI gameport");
2878 if (r)
2879 break;
2880 }
2881 } else {
2882 io_port = joystick_port[dev];
2883 r = request_region(io_port, 1, "CMIPCI gameport");
2884 }
2885
2886 if (!r) {
2887 dev_warn(cm->card->dev, "cannot reserve joystick ports\n");
2888 return -EBUSY;
2889 }
2890
2891 cm->gameport = gp = gameport_allocate_port();
2892 if (!gp) {
2893 dev_err(cm->card->dev, "cannot allocate memory for gameport\n");
2894 release_and_free_resource(r);
2895 return -ENOMEM;
2896 }
2897 gameport_set_name(gp, "C-Media Gameport");
2898 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2899 gameport_set_dev_parent(gp, &cm->pci->dev);
2900 gp->io = io_port;
2901 gameport_set_port_data(gp, r);
2902
2903 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2904
2905 gameport_register_port(cm->gameport);
2906
2907 return 0;
2908}
2909
2910static void snd_cmipci_free_gameport(struct cmipci *cm)
2911{
2912 if (cm->gameport) {
2913 struct resource *r = gameport_get_port_data(cm->gameport);
2914
2915 gameport_unregister_port(cm->gameport);
2916 cm->gameport = NULL;
2917
2918 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2919 release_and_free_resource(r);
2920 }
2921}
2922#else
2923static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2924static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2925#endif
2926
2927static int snd_cmipci_free(struct cmipci *cm)
2928{
2929 if (cm->irq >= 0) {
2930 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2931 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2932 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2933 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2934 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2935 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2936 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2937
2938 /* reset mixer */
2939 snd_cmipci_mixer_write(cm, 0, 0);
2940
2941 free_irq(cm->irq, cm);
2942 }
2943
2944 snd_cmipci_free_gameport(cm);
2945 pci_release_regions(cm->pci);
2946 pci_disable_device(cm->pci);
2947 kfree(cm);
2948 return 0;
2949}
2950
2951static int snd_cmipci_dev_free(struct snd_device *device)
2952{
2953 struct cmipci *cm = device->device_data;
2954 return snd_cmipci_free(cm);
2955}
2956
2957static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2958{
2959 long iosynth;
2960 unsigned int val;
2961 struct snd_opl3 *opl3;
2962 int err;
2963
2964 if (!fm_port)
2965 goto disable_fm;
2966
2967 if (cm->chip_version >= 39) {
2968 /* first try FM regs in PCI port range */
2969 iosynth = cm->iobase + CM_REG_FM_PCI;
2970 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2971 OPL3_HW_OPL3, 1, &opl3);
2972 } else {
2973 err = -EIO;
2974 }
2975 if (err < 0) {
2976 /* then try legacy ports */
2977 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2978 iosynth = fm_port;
2979 switch (iosynth) {
2980 case 0x3E8: val |= CM_FMSEL_3E8; break;
2981 case 0x3E0: val |= CM_FMSEL_3E0; break;
2982 case 0x3C8: val |= CM_FMSEL_3C8; break;
2983 case 0x388: val |= CM_FMSEL_388; break;
2984 default:
2985 goto disable_fm;
2986 }
2987 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2988 /* enable FM */
2989 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2990
2991 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2992 OPL3_HW_OPL3, 0, &opl3) < 0) {
2993 dev_err(cm->card->dev,
2994 "no OPL device at %#lx, skipping...\n",
2995 iosynth);
2996 goto disable_fm;
2997 }
2998 }
2999 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
3000 dev_err(cm->card->dev, "cannot create OPL3 hwdep\n");
3001 return err;
3002 }
3003 return 0;
3004
3005 disable_fm:
3006 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
3007 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
3008 return 0;
3009}
3010
3011static int snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
3012 int dev, struct cmipci **rcmipci)
3013{
3014 struct cmipci *cm;
3015 int err;
3016 static struct snd_device_ops ops = {
3017 .dev_free = snd_cmipci_dev_free,
3018 };
3019 unsigned int val;
3020 long iomidi = 0;
3021 int integrated_midi = 0;
3022 char modelstr[16];
3023 int pcm_index, pcm_spdif_index;
3024 static const struct pci_device_id intel_82437vx[] = {
3025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
3026 { },
3027 };
3028
3029 *rcmipci = NULL;
3030
3031 if ((err = pci_enable_device(pci)) < 0)
3032 return err;
3033
3034 cm = kzalloc(sizeof(*cm), GFP_KERNEL);
3035 if (cm == NULL) {
3036 pci_disable_device(pci);
3037 return -ENOMEM;
3038 }
3039
3040 spin_lock_init(&cm->reg_lock);
3041 mutex_init(&cm->open_mutex);
3042 cm->device = pci->device;
3043 cm->card = card;
3044 cm->pci = pci;
3045 cm->irq = -1;
3046 cm->channel[0].ch = 0;
3047 cm->channel[1].ch = 1;
3048 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
3049
3050 if ((err = pci_request_regions(pci, card->driver)) < 0) {
3051 kfree(cm);
3052 pci_disable_device(pci);
3053 return err;
3054 }
3055 cm->iobase = pci_resource_start(pci, 0);
3056
3057 if (request_irq(pci->irq, snd_cmipci_interrupt,
3058 IRQF_SHARED, KBUILD_MODNAME, cm)) {
3059 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3060 snd_cmipci_free(cm);
3061 return -EBUSY;
3062 }
3063 cm->irq = pci->irq;
3064
3065 pci_set_master(cm->pci);
3066
3067 /*
3068 * check chip version, max channels and capabilities
3069 */
3070
3071 cm->chip_version = 0;
3072 cm->max_channels = 2;
3073 cm->do_soft_ac3 = soft_ac3[dev];
3074
3075 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
3076 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
3077 query_chip(cm);
3078 /* added -MCx suffix for chip supporting multi-channels */
3079 if (cm->can_multi_ch)
3080 sprintf(cm->card->driver + strlen(cm->card->driver),
3081 "-MC%d", cm->max_channels);
3082 else if (cm->can_ac3_sw)
3083 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3084
3085 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3086 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3087
3088#if CM_CH_PLAY == 1
3089 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
3090#else
3091 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
3092#endif
3093
3094 /* initialize codec registers */
3095 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3096 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3097 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
3098 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3099 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3100 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
3101 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3102
3103 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3104 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3105#if CM_CH_PLAY == 1
3106 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3107#else
3108 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3109#endif
3110 if (cm->chip_version) {
3111 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3112 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3113 }
3114 /* Set Bus Master Request */
3115 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3116
3117 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3118 switch (pci->device) {
3119 case PCI_DEVICE_ID_CMEDIA_CM8738:
3120 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3121 if (!pci_dev_present(intel_82437vx))
3122 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3123 break;
3124 default:
3125 break;
3126 }
3127
3128 if (cm->chip_version < 68) {
3129 val = pci->device < 0x110 ? 8338 : 8738;
3130 } else {
3131 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3132 case 0:
3133 val = 8769;
3134 break;
3135 case 2:
3136 val = 8762;
3137 break;
3138 default:
3139 switch ((pci->subsystem_vendor << 16) |
3140 pci->subsystem_device) {
3141 case 0x13f69761:
3142 case 0x584d3741:
3143 case 0x584d3751:
3144 case 0x584d3761:
3145 case 0x584d3771:
3146 case 0x72848384:
3147 val = 8770;
3148 break;
3149 default:
3150 val = 8768;
3151 break;
3152 }
3153 }
3154 }
3155 sprintf(card->shortname, "C-Media CMI%d", val);
3156 if (cm->chip_version < 68)
3157 sprintf(modelstr, " (model %d)", cm->chip_version);
3158 else
3159 modelstr[0] = '\0';
3160 sprintf(card->longname, "%s%s at %#lx, irq %i",
3161 card->shortname, modelstr, cm->iobase, cm->irq);
3162
3163 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
3164 snd_cmipci_free(cm);
3165 return err;
3166 }
3167
3168 if (cm->chip_version >= 39) {
3169 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3170 if (val != 0x00 && val != 0xff) {
3171 iomidi = cm->iobase + CM_REG_MPU_PCI;
3172 integrated_midi = 1;
3173 }
3174 }
3175 if (!integrated_midi) {
3176 val = 0;
3177 iomidi = mpu_port[dev];
3178 switch (iomidi) {
3179 case 0x320: val = CM_VMPU_320; break;
3180 case 0x310: val = CM_VMPU_310; break;
3181 case 0x300: val = CM_VMPU_300; break;
3182 case 0x330: val = CM_VMPU_330; break;
3183 default:
3184 iomidi = 0; break;
3185 }
3186 if (iomidi > 0) {
3187 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3188 /* enable UART */
3189 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3190 if (inb(iomidi + 1) == 0xff) {
3191 dev_err(cm->card->dev,
3192 "cannot enable MPU-401 port at %#lx\n",
3193 iomidi);
3194 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3195 CM_UART_EN);
3196 iomidi = 0;
3197 }
3198 }
3199 }
3200
3201 if (cm->chip_version < 68) {
3202 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3203 if (err < 0)
3204 return err;
3205 }
3206
3207 /* reset mixer */
3208 snd_cmipci_mixer_write(cm, 0, 0);
3209
3210 snd_cmipci_proc_init(cm);
3211
3212 /* create pcm devices */
3213 pcm_index = pcm_spdif_index = 0;
3214 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
3215 return err;
3216 pcm_index++;
3217 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
3218 return err;
3219 pcm_index++;
3220 if (cm->can_ac3_hw || cm->can_ac3_sw) {
3221 pcm_spdif_index = pcm_index;
3222 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
3223 return err;
3224 }
3225
3226 /* create mixer interface & switches */
3227 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
3228 return err;
3229
3230 if (iomidi > 0) {
3231 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3232 iomidi,
3233 (integrated_midi ?
3234 MPU401_INFO_INTEGRATED : 0) |
3235 MPU401_INFO_IRQ_HOOK,
3236 -1, &cm->rmidi)) < 0) {
3237 dev_err(cm->card->dev,
3238 "no UART401 device at 0x%lx\n", iomidi);
3239 }
3240 }
3241
3242#ifdef USE_VAR48KRATE
3243 for (val = 0; val < ARRAY_SIZE(rates); val++)
3244 snd_cmipci_set_pll(cm, rates[val], val);
3245
3246 /*
3247 * (Re-)Enable external switch spdo_48k
3248 */
3249 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3250#endif /* USE_VAR48KRATE */
3251
3252 if (snd_cmipci_create_gameport(cm, dev) < 0)
3253 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3254
3255 *rcmipci = cm;
3256 return 0;
3257}
3258
3259/*
3260 */
3261
3262MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3263
3264static int snd_cmipci_probe(struct pci_dev *pci,
3265 const struct pci_device_id *pci_id)
3266{
3267 static int dev;
3268 struct snd_card *card;
3269 struct cmipci *cm;
3270 int err;
3271
3272 if (dev >= SNDRV_CARDS)
3273 return -ENODEV;
3274 if (! enable[dev]) {
3275 dev++;
3276 return -ENOENT;
3277 }
3278
3279 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
3280 0, &card);
3281 if (err < 0)
3282 return err;
3283
3284 switch (pci->device) {
3285 case PCI_DEVICE_ID_CMEDIA_CM8738:
3286 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3287 strcpy(card->driver, "CMI8738");
3288 break;
3289 case PCI_DEVICE_ID_CMEDIA_CM8338A:
3290 case PCI_DEVICE_ID_CMEDIA_CM8338B:
3291 strcpy(card->driver, "CMI8338");
3292 break;
3293 default:
3294 strcpy(card->driver, "CMIPCI");
3295 break;
3296 }
3297
3298 if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) {
3299 snd_card_free(card);
3300 return err;
3301 }
3302 card->private_data = cm;
3303
3304 if ((err = snd_card_register(card)) < 0) {
3305 snd_card_free(card);
3306 return err;
3307 }
3308 pci_set_drvdata(pci, card);
3309 dev++;
3310 return 0;
3311
3312}
3313
3314static void snd_cmipci_remove(struct pci_dev *pci)
3315{
3316 snd_card_free(pci_get_drvdata(pci));
3317}
3318
3319
3320#ifdef CONFIG_PM_SLEEP
3321/*
3322 * power management
3323 */
3324static unsigned char saved_regs[] = {
3325 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3326 CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL,
3327 CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3328 CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3329 CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3330};
3331
3332static unsigned char saved_mixers[] = {
3333 SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3334 SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3335 SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3336 SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3337 SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3338 SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3339 CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3340 SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3341};
3342
3343static int snd_cmipci_suspend(struct device *dev)
3344{
3345 struct snd_card *card = dev_get_drvdata(dev);
3346 struct cmipci *cm = card->private_data;
3347 int i;
3348
3349 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3350
3351 snd_pcm_suspend_all(cm->pcm);
3352 snd_pcm_suspend_all(cm->pcm2);
3353 snd_pcm_suspend_all(cm->pcm_spdif);
3354
3355 /* save registers */
3356 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3357 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3358 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3359 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3360
3361 /* disable ints */
3362 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3363 return 0;
3364}
3365
3366static int snd_cmipci_resume(struct device *dev)
3367{
3368 struct snd_card *card = dev_get_drvdata(dev);
3369 struct cmipci *cm = card->private_data;
3370 int i;
3371
3372 /* reset / initialize to a sane state */
3373 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3374 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3375 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3376 snd_cmipci_mixer_write(cm, 0, 0);
3377
3378 /* restore registers */
3379 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3380 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3381 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3382 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3383
3384 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3385 return 0;
3386}
3387
3388static SIMPLE_DEV_PM_OPS(snd_cmipci_pm, snd_cmipci_suspend, snd_cmipci_resume);
3389#define SND_CMIPCI_PM_OPS &snd_cmipci_pm
3390#else
3391#define SND_CMIPCI_PM_OPS NULL
3392#endif /* CONFIG_PM_SLEEP */
3393
3394static struct pci_driver cmipci_driver = {
3395 .name = KBUILD_MODNAME,
3396 .id_table = snd_cmipci_ids,
3397 .probe = snd_cmipci_probe,
3398 .remove = snd_cmipci_remove,
3399 .driver = {
3400 .pm = SND_CMIPCI_PM_OPS,
3401 },
3402};
3403
3404module_pci_driver(cmipci_driver);