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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * PCA953x 4/8/16/24/40 bit I/O ports
4 *
5 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
6 * Copyright (C) 2007 Marvell International Ltd.
7 *
8 * Derived from drivers/i2c/chips/pca9539.c
9 */
10
11#include <linux/acpi.h>
12#include <linux/bitmap.h>
13#include <linux/gpio/driver.h>
14#include <linux/gpio/consumer.h>
15#include <linux/i2c.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/module.h>
19#include <linux/of_platform.h>
20#include <linux/platform_data/pca953x.h>
21#include <linux/regmap.h>
22#include <linux/regulator/consumer.h>
23#include <linux/slab.h>
24
25#include <asm/unaligned.h>
26
27#define PCA953X_INPUT 0x00
28#define PCA953X_OUTPUT 0x01
29#define PCA953X_INVERT 0x02
30#define PCA953X_DIRECTION 0x03
31
32#define REG_ADDR_MASK GENMASK(5, 0)
33#define REG_ADDR_EXT BIT(6)
34#define REG_ADDR_AI BIT(7)
35
36#define PCA957X_IN 0x00
37#define PCA957X_INVRT 0x01
38#define PCA957X_BKEN 0x02
39#define PCA957X_PUPD 0x03
40#define PCA957X_CFG 0x04
41#define PCA957X_OUT 0x05
42#define PCA957X_MSK 0x06
43#define PCA957X_INTS 0x07
44
45#define PCAL953X_OUT_STRENGTH 0x20
46#define PCAL953X_IN_LATCH 0x22
47#define PCAL953X_PULL_EN 0x23
48#define PCAL953X_PULL_SEL 0x24
49#define PCAL953X_INT_MASK 0x25
50#define PCAL953X_INT_STAT 0x26
51#define PCAL953X_OUT_CONF 0x27
52
53#define PCAL6524_INT_EDGE 0x28
54#define PCAL6524_INT_CLR 0x2a
55#define PCAL6524_IN_STATUS 0x2b
56#define PCAL6524_OUT_INDCONF 0x2c
57#define PCAL6524_DEBOUNCE 0x2d
58
59#define PCA_GPIO_MASK GENMASK(7, 0)
60
61#define PCAL_GPIO_MASK GENMASK(4, 0)
62#define PCAL_PINCTRL_MASK GENMASK(6, 5)
63
64#define PCA_INT BIT(8)
65#define PCA_PCAL BIT(9)
66#define PCA_LATCH_INT (PCA_PCAL | PCA_INT)
67#define PCA953X_TYPE BIT(12)
68#define PCA957X_TYPE BIT(13)
69#define PCA_TYPE_MASK GENMASK(15, 12)
70
71#define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
72
73static const struct i2c_device_id pca953x_id[] = {
74 { "pca6416", 16 | PCA953X_TYPE | PCA_INT, },
75 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
76 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
77 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
78 { "pca9536", 4 | PCA953X_TYPE, },
79 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
80 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
81 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
82 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
83 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
84 { "pca9556", 8 | PCA953X_TYPE, },
85 { "pca9557", 8 | PCA953X_TYPE, },
86 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
87 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
88 { "pca9698", 40 | PCA953X_TYPE, },
89
90 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
91 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, },
92 { "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
93 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
94
95 { "max7310", 8 | PCA953X_TYPE, },
96 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
97 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
98 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
99 { "max7318", 16 | PCA953X_TYPE | PCA_INT, },
100 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
101 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
102 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
103 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
104 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
105 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, },
106 { "xra1202", 8 | PCA953X_TYPE },
107 { }
108};
109MODULE_DEVICE_TABLE(i2c, pca953x_id);
110
111#ifdef CONFIG_GPIO_PCA953X_IRQ
112
113#include <linux/dmi.h>
114#include <linux/gpio.h>
115#include <linux/list.h>
116
117static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = {
118 {
119 /*
120 * On Intel Galileo Gen 2 board the IRQ pin of one of
121 * the I²C GPIO expanders, which has GpioInt() resource,
122 * is provided as an absolute number instead of being
123 * relative. Since first controller (gpio-sch.c) and
124 * second (gpio-dwapb.c) are at the fixed bases, we may
125 * safely refer to the number in the global space to get
126 * an IRQ out of it.
127 */
128 .matches = {
129 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
130 },
131 },
132 {}
133};
134
135#ifdef CONFIG_ACPI
136static int pca953x_acpi_get_pin(struct acpi_resource *ares, void *data)
137{
138 struct acpi_resource_gpio *agpio;
139 int *pin = data;
140
141 if (acpi_gpio_get_irq_resource(ares, &agpio))
142 *pin = agpio->pin_table[0];
143 return 1;
144}
145
146static int pca953x_acpi_find_pin(struct device *dev)
147{
148 struct acpi_device *adev = ACPI_COMPANION(dev);
149 int pin = -ENOENT, ret;
150 LIST_HEAD(r);
151
152 ret = acpi_dev_get_resources(adev, &r, pca953x_acpi_get_pin, &pin);
153 acpi_dev_free_resource_list(&r);
154 if (ret < 0)
155 return ret;
156
157 return pin;
158}
159#else
160static inline int pca953x_acpi_find_pin(struct device *dev) { return -ENXIO; }
161#endif
162
163static int pca953x_acpi_get_irq(struct device *dev)
164{
165 int pin, ret;
166
167 pin = pca953x_acpi_find_pin(dev);
168 if (pin < 0)
169 return pin;
170
171 dev_info(dev, "Applying ACPI interrupt quirk (GPIO %d)\n", pin);
172
173 if (!gpio_is_valid(pin))
174 return -EINVAL;
175
176 ret = gpio_request(pin, "pca953x interrupt");
177 if (ret)
178 return ret;
179
180 ret = gpio_to_irq(pin);
181
182 /* When pin is used as an IRQ, no need to keep it requested */
183 gpio_free(pin);
184
185 return ret;
186}
187#endif
188
189static const struct acpi_device_id pca953x_acpi_ids[] = {
190 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
191 { }
192};
193MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
194
195#define MAX_BANK 5
196#define BANK_SZ 8
197#define MAX_LINE (MAX_BANK * BANK_SZ)
198
199#define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
200
201struct pca953x_reg_config {
202 int direction;
203 int output;
204 int input;
205 int invert;
206};
207
208static const struct pca953x_reg_config pca953x_regs = {
209 .direction = PCA953X_DIRECTION,
210 .output = PCA953X_OUTPUT,
211 .input = PCA953X_INPUT,
212 .invert = PCA953X_INVERT,
213};
214
215static const struct pca953x_reg_config pca957x_regs = {
216 .direction = PCA957X_CFG,
217 .output = PCA957X_OUT,
218 .input = PCA957X_IN,
219 .invert = PCA957X_INVRT,
220};
221
222struct pca953x_chip {
223 unsigned gpio_start;
224 struct mutex i2c_lock;
225 struct regmap *regmap;
226
227#ifdef CONFIG_GPIO_PCA953X_IRQ
228 struct mutex irq_lock;
229 DECLARE_BITMAP(irq_mask, MAX_LINE);
230 DECLARE_BITMAP(irq_stat, MAX_LINE);
231 DECLARE_BITMAP(irq_trig_raise, MAX_LINE);
232 DECLARE_BITMAP(irq_trig_fall, MAX_LINE);
233 struct irq_chip irq_chip;
234#endif
235 atomic_t wakeup_path;
236
237 struct i2c_client *client;
238 struct gpio_chip gpio_chip;
239 const char *const *names;
240 unsigned long driver_data;
241 struct regulator *regulator;
242
243 const struct pca953x_reg_config *regs;
244};
245
246static int pca953x_bank_shift(struct pca953x_chip *chip)
247{
248 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
249}
250
251#define PCA953x_BANK_INPUT BIT(0)
252#define PCA953x_BANK_OUTPUT BIT(1)
253#define PCA953x_BANK_POLARITY BIT(2)
254#define PCA953x_BANK_CONFIG BIT(3)
255
256#define PCA957x_BANK_INPUT BIT(0)
257#define PCA957x_BANK_POLARITY BIT(1)
258#define PCA957x_BANK_BUSHOLD BIT(2)
259#define PCA957x_BANK_CONFIG BIT(4)
260#define PCA957x_BANK_OUTPUT BIT(5)
261
262#define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2)
263#define PCAL9xxx_BANK_PULL_EN BIT(8 + 3)
264#define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4)
265#define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5)
266#define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6)
267
268/*
269 * We care about the following registers:
270 * - Standard set, below 0x40, each port can be replicated up to 8 times
271 * - PCA953x standard
272 * Input port 0x00 + 0 * bank_size R
273 * Output port 0x00 + 1 * bank_size RW
274 * Polarity Inversion port 0x00 + 2 * bank_size RW
275 * Configuration port 0x00 + 3 * bank_size RW
276 * - PCA957x with mixed up registers
277 * Input port 0x00 + 0 * bank_size R
278 * Polarity Inversion port 0x00 + 1 * bank_size RW
279 * Bus hold port 0x00 + 2 * bank_size RW
280 * Configuration port 0x00 + 4 * bank_size RW
281 * Output port 0x00 + 5 * bank_size RW
282 *
283 * - Extended set, above 0x40, often chip specific.
284 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling:
285 * Input latch register 0x40 + 2 * bank_size RW
286 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW
287 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW
288 * Interrupt mask register 0x40 + 5 * bank_size RW
289 * Interrupt status register 0x40 + 6 * bank_size R
290 *
291 * - Registers with bit 0x80 set, the AI bit
292 * The bit is cleared and the registers fall into one of the
293 * categories above.
294 */
295
296static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg,
297 u32 checkbank)
298{
299 int bank_shift = pca953x_bank_shift(chip);
300 int bank = (reg & REG_ADDR_MASK) >> bank_shift;
301 int offset = reg & (BIT(bank_shift) - 1);
302
303 /* Special PCAL extended register check. */
304 if (reg & REG_ADDR_EXT) {
305 if (!(chip->driver_data & PCA_PCAL))
306 return false;
307 bank += 8;
308 }
309
310 /* Register is not in the matching bank. */
311 if (!(BIT(bank) & checkbank))
312 return false;
313
314 /* Register is not within allowed range of bank. */
315 if (offset >= NBANK(chip))
316 return false;
317
318 return true;
319}
320
321static bool pca953x_readable_register(struct device *dev, unsigned int reg)
322{
323 struct pca953x_chip *chip = dev_get_drvdata(dev);
324 u32 bank;
325
326 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
327 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT |
328 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG;
329 } else {
330 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT |
331 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG |
332 PCA957x_BANK_BUSHOLD;
333 }
334
335 if (chip->driver_data & PCA_PCAL) {
336 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
337 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK |
338 PCAL9xxx_BANK_IRQ_STAT;
339 }
340
341 return pca953x_check_register(chip, reg, bank);
342}
343
344static bool pca953x_writeable_register(struct device *dev, unsigned int reg)
345{
346 struct pca953x_chip *chip = dev_get_drvdata(dev);
347 u32 bank;
348
349 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
350 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY |
351 PCA953x_BANK_CONFIG;
352 } else {
353 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY |
354 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD;
355 }
356
357 if (chip->driver_data & PCA_PCAL)
358 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
359 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK;
360
361 return pca953x_check_register(chip, reg, bank);
362}
363
364static bool pca953x_volatile_register(struct device *dev, unsigned int reg)
365{
366 struct pca953x_chip *chip = dev_get_drvdata(dev);
367 u32 bank;
368
369 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)
370 bank = PCA953x_BANK_INPUT;
371 else
372 bank = PCA957x_BANK_INPUT;
373
374 if (chip->driver_data & PCA_PCAL)
375 bank |= PCAL9xxx_BANK_IRQ_STAT;
376
377 return pca953x_check_register(chip, reg, bank);
378}
379
380static const struct regmap_config pca953x_i2c_regmap = {
381 .reg_bits = 8,
382 .val_bits = 8,
383
384 .readable_reg = pca953x_readable_register,
385 .writeable_reg = pca953x_writeable_register,
386 .volatile_reg = pca953x_volatile_register,
387
388 .disable_locking = true,
389 .cache_type = REGCACHE_RBTREE,
390 .max_register = 0x7f,
391};
392
393static const struct regmap_config pca953x_ai_i2c_regmap = {
394 .reg_bits = 8,
395 .val_bits = 8,
396
397 .read_flag_mask = REG_ADDR_AI,
398 .write_flag_mask = REG_ADDR_AI,
399
400 .readable_reg = pca953x_readable_register,
401 .writeable_reg = pca953x_writeable_register,
402 .volatile_reg = pca953x_volatile_register,
403
404 .disable_locking = true,
405 .cache_type = REGCACHE_RBTREE,
406 .max_register = 0x7f,
407};
408
409static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off)
410{
411 int bank_shift = pca953x_bank_shift(chip);
412 int addr = (reg & PCAL_GPIO_MASK) << bank_shift;
413 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1;
414 u8 regaddr = pinctrl | addr | (off / BANK_SZ);
415
416 return regaddr;
417}
418
419static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
420{
421 u8 regaddr = pca953x_recalc_addr(chip, reg, 0);
422 u8 value[MAX_BANK];
423 int i, ret;
424
425 for (i = 0; i < NBANK(chip); i++)
426 value[i] = bitmap_get_value8(val, i * BANK_SZ);
427
428 ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip));
429 if (ret < 0) {
430 dev_err(&chip->client->dev, "failed writing register\n");
431 return ret;
432 }
433
434 return 0;
435}
436
437static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
438{
439 u8 regaddr = pca953x_recalc_addr(chip, reg, 0);
440 u8 value[MAX_BANK];
441 int i, ret;
442
443 ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip));
444 if (ret < 0) {
445 dev_err(&chip->client->dev, "failed reading register\n");
446 return ret;
447 }
448
449 for (i = 0; i < NBANK(chip); i++)
450 bitmap_set_value8(val, value[i], i * BANK_SZ);
451
452 return 0;
453}
454
455static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
456{
457 struct pca953x_chip *chip = gpiochip_get_data(gc);
458 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off);
459 u8 bit = BIT(off % BANK_SZ);
460 int ret;
461
462 mutex_lock(&chip->i2c_lock);
463 ret = regmap_write_bits(chip->regmap, dirreg, bit, bit);
464 mutex_unlock(&chip->i2c_lock);
465 return ret;
466}
467
468static int pca953x_gpio_direction_output(struct gpio_chip *gc,
469 unsigned off, int val)
470{
471 struct pca953x_chip *chip = gpiochip_get_data(gc);
472 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off);
473 u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off);
474 u8 bit = BIT(off % BANK_SZ);
475 int ret;
476
477 mutex_lock(&chip->i2c_lock);
478 /* set output level */
479 ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
480 if (ret)
481 goto exit;
482
483 /* then direction */
484 ret = regmap_write_bits(chip->regmap, dirreg, bit, 0);
485exit:
486 mutex_unlock(&chip->i2c_lock);
487 return ret;
488}
489
490static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
491{
492 struct pca953x_chip *chip = gpiochip_get_data(gc);
493 u8 inreg = pca953x_recalc_addr(chip, chip->regs->input, off);
494 u8 bit = BIT(off % BANK_SZ);
495 u32 reg_val;
496 int ret;
497
498 mutex_lock(&chip->i2c_lock);
499 ret = regmap_read(chip->regmap, inreg, ®_val);
500 mutex_unlock(&chip->i2c_lock);
501 if (ret < 0) {
502 /*
503 * NOTE:
504 * diagnostic already emitted; that's all we should
505 * do unless gpio_*_value_cansleep() calls become different
506 * from their nonsleeping siblings (and report faults).
507 */
508 return 0;
509 }
510
511 return !!(reg_val & bit);
512}
513
514static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
515{
516 struct pca953x_chip *chip = gpiochip_get_data(gc);
517 u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off);
518 u8 bit = BIT(off % BANK_SZ);
519
520 mutex_lock(&chip->i2c_lock);
521 regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
522 mutex_unlock(&chip->i2c_lock);
523}
524
525static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off)
526{
527 struct pca953x_chip *chip = gpiochip_get_data(gc);
528 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off);
529 u8 bit = BIT(off % BANK_SZ);
530 u32 reg_val;
531 int ret;
532
533 mutex_lock(&chip->i2c_lock);
534 ret = regmap_read(chip->regmap, dirreg, ®_val);
535 mutex_unlock(&chip->i2c_lock);
536 if (ret < 0)
537 return ret;
538
539 if (reg_val & bit)
540 return GPIO_LINE_DIRECTION_IN;
541
542 return GPIO_LINE_DIRECTION_OUT;
543}
544
545static int pca953x_gpio_get_multiple(struct gpio_chip *gc,
546 unsigned long *mask, unsigned long *bits)
547{
548 struct pca953x_chip *chip = gpiochip_get_data(gc);
549 DECLARE_BITMAP(reg_val, MAX_LINE);
550 int ret;
551
552 mutex_lock(&chip->i2c_lock);
553 ret = pca953x_read_regs(chip, chip->regs->input, reg_val);
554 mutex_unlock(&chip->i2c_lock);
555 if (ret)
556 return ret;
557
558 bitmap_replace(bits, bits, reg_val, mask, gc->ngpio);
559 return 0;
560}
561
562static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
563 unsigned long *mask, unsigned long *bits)
564{
565 struct pca953x_chip *chip = gpiochip_get_data(gc);
566 DECLARE_BITMAP(reg_val, MAX_LINE);
567 int ret;
568
569 mutex_lock(&chip->i2c_lock);
570 ret = pca953x_read_regs(chip, chip->regs->output, reg_val);
571 if (ret)
572 goto exit;
573
574 bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio);
575
576 pca953x_write_regs(chip, chip->regs->output, reg_val);
577exit:
578 mutex_unlock(&chip->i2c_lock);
579}
580
581static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip,
582 unsigned int offset,
583 unsigned long config)
584{
585 u8 pull_en_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_EN, offset);
586 u8 pull_sel_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_SEL, offset);
587 u8 bit = BIT(offset % BANK_SZ);
588 int ret;
589
590 /*
591 * pull-up/pull-down configuration requires PCAL extended
592 * registers
593 */
594 if (!(chip->driver_data & PCA_PCAL))
595 return -ENOTSUPP;
596
597 mutex_lock(&chip->i2c_lock);
598
599 /* Disable pull-up/pull-down */
600 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0);
601 if (ret)
602 goto exit;
603
604 /* Configure pull-up/pull-down */
605 if (config == PIN_CONFIG_BIAS_PULL_UP)
606 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit);
607 else if (config == PIN_CONFIG_BIAS_PULL_DOWN)
608 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0);
609 if (ret)
610 goto exit;
611
612 /* Enable pull-up/pull-down */
613 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit);
614
615exit:
616 mutex_unlock(&chip->i2c_lock);
617 return ret;
618}
619
620static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
621 unsigned long config)
622{
623 struct pca953x_chip *chip = gpiochip_get_data(gc);
624
625 switch (pinconf_to_config_param(config)) {
626 case PIN_CONFIG_BIAS_PULL_UP:
627 case PIN_CONFIG_BIAS_PULL_DOWN:
628 return pca953x_gpio_set_pull_up_down(chip, offset, config);
629 default:
630 return -ENOTSUPP;
631 }
632}
633
634static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
635{
636 struct gpio_chip *gc;
637
638 gc = &chip->gpio_chip;
639
640 gc->direction_input = pca953x_gpio_direction_input;
641 gc->direction_output = pca953x_gpio_direction_output;
642 gc->get = pca953x_gpio_get_value;
643 gc->set = pca953x_gpio_set_value;
644 gc->get_direction = pca953x_gpio_get_direction;
645 gc->get_multiple = pca953x_gpio_get_multiple;
646 gc->set_multiple = pca953x_gpio_set_multiple;
647 gc->set_config = pca953x_gpio_set_config;
648 gc->can_sleep = true;
649
650 gc->base = chip->gpio_start;
651 gc->ngpio = gpios;
652 gc->label = dev_name(&chip->client->dev);
653 gc->parent = &chip->client->dev;
654 gc->owner = THIS_MODULE;
655 gc->names = chip->names;
656}
657
658#ifdef CONFIG_GPIO_PCA953X_IRQ
659static void pca953x_irq_mask(struct irq_data *d)
660{
661 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
662 struct pca953x_chip *chip = gpiochip_get_data(gc);
663 irq_hw_number_t hwirq = irqd_to_hwirq(d);
664
665 clear_bit(hwirq, chip->irq_mask);
666}
667
668static void pca953x_irq_unmask(struct irq_data *d)
669{
670 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
671 struct pca953x_chip *chip = gpiochip_get_data(gc);
672 irq_hw_number_t hwirq = irqd_to_hwirq(d);
673
674 set_bit(hwirq, chip->irq_mask);
675}
676
677static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on)
678{
679 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
680 struct pca953x_chip *chip = gpiochip_get_data(gc);
681
682 if (on)
683 atomic_inc(&chip->wakeup_path);
684 else
685 atomic_dec(&chip->wakeup_path);
686
687 return irq_set_irq_wake(chip->client->irq, on);
688}
689
690static void pca953x_irq_bus_lock(struct irq_data *d)
691{
692 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
693 struct pca953x_chip *chip = gpiochip_get_data(gc);
694
695 mutex_lock(&chip->irq_lock);
696}
697
698static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
699{
700 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
701 struct pca953x_chip *chip = gpiochip_get_data(gc);
702 DECLARE_BITMAP(irq_mask, MAX_LINE);
703 DECLARE_BITMAP(reg_direction, MAX_LINE);
704 int level;
705
706 if (chip->driver_data & PCA_PCAL) {
707 /* Enable latch on interrupt-enabled inputs */
708 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
709
710 bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio);
711
712 /* Unmask enabled interrupts */
713 pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask);
714 }
715
716 /* Switch direction to input if needed */
717 pca953x_read_regs(chip, chip->regs->direction, reg_direction);
718
719 bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio);
720 bitmap_complement(reg_direction, reg_direction, gc->ngpio);
721 bitmap_and(irq_mask, irq_mask, reg_direction, gc->ngpio);
722
723 /* Look for any newly setup interrupt */
724 for_each_set_bit(level, irq_mask, gc->ngpio)
725 pca953x_gpio_direction_input(&chip->gpio_chip, level);
726
727 mutex_unlock(&chip->irq_lock);
728}
729
730static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
731{
732 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
733 struct pca953x_chip *chip = gpiochip_get_data(gc);
734 irq_hw_number_t hwirq = irqd_to_hwirq(d);
735
736 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
737 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
738 d->irq, type);
739 return -EINVAL;
740 }
741
742 assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING);
743 assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING);
744
745 return 0;
746}
747
748static void pca953x_irq_shutdown(struct irq_data *d)
749{
750 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
751 struct pca953x_chip *chip = gpiochip_get_data(gc);
752 irq_hw_number_t hwirq = irqd_to_hwirq(d);
753
754 clear_bit(hwirq, chip->irq_trig_raise);
755 clear_bit(hwirq, chip->irq_trig_fall);
756}
757
758static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending)
759{
760 struct gpio_chip *gc = &chip->gpio_chip;
761 DECLARE_BITMAP(reg_direction, MAX_LINE);
762 DECLARE_BITMAP(old_stat, MAX_LINE);
763 DECLARE_BITMAP(cur_stat, MAX_LINE);
764 DECLARE_BITMAP(new_stat, MAX_LINE);
765 DECLARE_BITMAP(trigger, MAX_LINE);
766 int ret;
767
768 if (chip->driver_data & PCA_PCAL) {
769 /* Read the current interrupt status from the device */
770 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
771 if (ret)
772 return false;
773
774 /* Check latched inputs and clear interrupt status */
775 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
776 if (ret)
777 return false;
778
779 /* Apply filter for rising/falling edge selection */
780 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, cur_stat, gc->ngpio);
781
782 bitmap_and(pending, new_stat, trigger, gc->ngpio);
783
784 return !bitmap_empty(pending, gc->ngpio);
785 }
786
787 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
788 if (ret)
789 return false;
790
791 /* Remove output pins from the equation */
792 pca953x_read_regs(chip, chip->regs->direction, reg_direction);
793
794 bitmap_copy(old_stat, chip->irq_stat, gc->ngpio);
795
796 bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio);
797 bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio);
798 bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio);
799
800 if (bitmap_empty(trigger, gc->ngpio))
801 return false;
802
803 bitmap_copy(chip->irq_stat, new_stat, gc->ngpio);
804
805 bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio);
806 bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio);
807 bitmap_or(new_stat, old_stat, cur_stat, gc->ngpio);
808 bitmap_and(pending, new_stat, trigger, gc->ngpio);
809
810 return !bitmap_empty(pending, gc->ngpio);
811}
812
813static irqreturn_t pca953x_irq_handler(int irq, void *devid)
814{
815 struct pca953x_chip *chip = devid;
816 struct gpio_chip *gc = &chip->gpio_chip;
817 DECLARE_BITMAP(pending, MAX_LINE);
818 int level;
819 bool ret;
820
821 bitmap_zero(pending, MAX_LINE);
822
823 mutex_lock(&chip->i2c_lock);
824 ret = pca953x_irq_pending(chip, pending);
825 mutex_unlock(&chip->i2c_lock);
826
827 if (ret) {
828 ret = 0;
829
830 for_each_set_bit(level, pending, gc->ngpio) {
831 int nested_irq = irq_find_mapping(gc->irq.domain, level);
832
833 if (unlikely(nested_irq <= 0)) {
834 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);
835 continue;
836 }
837
838 handle_nested_irq(nested_irq);
839 ret = 1;
840 }
841 }
842
843 return IRQ_RETVAL(ret);
844}
845
846static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base)
847{
848 struct i2c_client *client = chip->client;
849 struct irq_chip *irq_chip = &chip->irq_chip;
850 DECLARE_BITMAP(reg_direction, MAX_LINE);
851 DECLARE_BITMAP(irq_stat, MAX_LINE);
852 struct gpio_irq_chip *girq;
853 int ret;
854
855 if (dmi_first_match(pca953x_dmi_acpi_irq_info)) {
856 ret = pca953x_acpi_get_irq(&client->dev);
857 if (ret > 0)
858 client->irq = ret;
859 }
860
861 if (!client->irq)
862 return 0;
863
864 if (irq_base == -1)
865 return 0;
866
867 if (!(chip->driver_data & PCA_INT))
868 return 0;
869
870 ret = pca953x_read_regs(chip, chip->regs->input, irq_stat);
871 if (ret)
872 return ret;
873
874 /*
875 * There is no way to know which GPIO line generated the
876 * interrupt. We have to rely on the previous read for
877 * this purpose.
878 */
879 pca953x_read_regs(chip, chip->regs->direction, reg_direction);
880 bitmap_and(chip->irq_stat, irq_stat, reg_direction, chip->gpio_chip.ngpio);
881 mutex_init(&chip->irq_lock);
882
883 irq_chip->name = dev_name(&client->dev);
884 irq_chip->irq_mask = pca953x_irq_mask;
885 irq_chip->irq_unmask = pca953x_irq_unmask;
886 irq_chip->irq_set_wake = pca953x_irq_set_wake;
887 irq_chip->irq_bus_lock = pca953x_irq_bus_lock;
888 irq_chip->irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock;
889 irq_chip->irq_set_type = pca953x_irq_set_type;
890 irq_chip->irq_shutdown = pca953x_irq_shutdown;
891
892 girq = &chip->gpio_chip.irq;
893 girq->chip = irq_chip;
894 /* This will let us handle the parent IRQ in the driver */
895 girq->parent_handler = NULL;
896 girq->num_parents = 0;
897 girq->parents = NULL;
898 girq->default_type = IRQ_TYPE_NONE;
899 girq->handler = handle_simple_irq;
900 girq->threaded = true;
901 girq->first = irq_base; /* FIXME: get rid of this */
902
903 ret = devm_request_threaded_irq(&client->dev, client->irq,
904 NULL, pca953x_irq_handler,
905 IRQF_ONESHOT | IRQF_SHARED,
906 dev_name(&client->dev), chip);
907 if (ret) {
908 dev_err(&client->dev, "failed to request irq %d\n",
909 client->irq);
910 return ret;
911 }
912
913 return 0;
914}
915
916#else /* CONFIG_GPIO_PCA953X_IRQ */
917static int pca953x_irq_setup(struct pca953x_chip *chip,
918 int irq_base)
919{
920 struct i2c_client *client = chip->client;
921
922 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT))
923 dev_warn(&client->dev, "interrupt support not compiled in\n");
924
925 return 0;
926}
927#endif
928
929static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert)
930{
931 DECLARE_BITMAP(val, MAX_LINE);
932 int ret;
933
934 ret = regcache_sync_region(chip->regmap, chip->regs->output,
935 chip->regs->output + NBANK(chip));
936 if (ret)
937 goto out;
938
939 ret = regcache_sync_region(chip->regmap, chip->regs->direction,
940 chip->regs->direction + NBANK(chip));
941 if (ret)
942 goto out;
943
944 /* set platform specific polarity inversion */
945 if (invert)
946 bitmap_fill(val, MAX_LINE);
947 else
948 bitmap_zero(val, MAX_LINE);
949
950 ret = pca953x_write_regs(chip, chip->regs->invert, val);
951out:
952 return ret;
953}
954
955static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
956{
957 DECLARE_BITMAP(val, MAX_LINE);
958 unsigned int i;
959 int ret;
960
961 ret = device_pca95xx_init(chip, invert);
962 if (ret)
963 goto out;
964
965 /* To enable register 6, 7 to control pull up and pull down */
966 for (i = 0; i < NBANK(chip); i++)
967 bitmap_set_value8(val, 0x02, i * BANK_SZ);
968
969 ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
970 if (ret)
971 goto out;
972
973 return 0;
974out:
975 return ret;
976}
977
978static int pca953x_probe(struct i2c_client *client,
979 const struct i2c_device_id *i2c_id)
980{
981 struct pca953x_platform_data *pdata;
982 struct pca953x_chip *chip;
983 int irq_base = 0;
984 int ret;
985 u32 invert = 0;
986 struct regulator *reg;
987 const struct regmap_config *regmap_config;
988
989 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
990 if (chip == NULL)
991 return -ENOMEM;
992
993 pdata = dev_get_platdata(&client->dev);
994 if (pdata) {
995 irq_base = pdata->irq_base;
996 chip->gpio_start = pdata->gpio_base;
997 invert = pdata->invert;
998 chip->names = pdata->names;
999 } else {
1000 struct gpio_desc *reset_gpio;
1001
1002 chip->gpio_start = -1;
1003 irq_base = 0;
1004
1005 /*
1006 * See if we need to de-assert a reset pin.
1007 *
1008 * There is no known ACPI-enabled platforms that are
1009 * using "reset" GPIO. Otherwise any of those platform
1010 * must use _DSD method with corresponding property.
1011 */
1012 reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1013 GPIOD_OUT_LOW);
1014 if (IS_ERR(reset_gpio))
1015 return PTR_ERR(reset_gpio);
1016 }
1017
1018 chip->client = client;
1019
1020 reg = devm_regulator_get(&client->dev, "vcc");
1021 if (IS_ERR(reg)) {
1022 ret = PTR_ERR(reg);
1023 if (ret != -EPROBE_DEFER)
1024 dev_err(&client->dev, "reg get err: %d\n", ret);
1025 return ret;
1026 }
1027 ret = regulator_enable(reg);
1028 if (ret) {
1029 dev_err(&client->dev, "reg en err: %d\n", ret);
1030 return ret;
1031 }
1032 chip->regulator = reg;
1033
1034 if (i2c_id) {
1035 chip->driver_data = i2c_id->driver_data;
1036 } else {
1037 const void *match;
1038
1039 match = device_get_match_data(&client->dev);
1040 if (!match) {
1041 ret = -ENODEV;
1042 goto err_exit;
1043 }
1044
1045 chip->driver_data = (uintptr_t)match;
1046 }
1047
1048 i2c_set_clientdata(client, chip);
1049
1050 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
1051
1052 if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
1053 dev_info(&client->dev, "using AI\n");
1054 regmap_config = &pca953x_ai_i2c_regmap;
1055 } else {
1056 dev_info(&client->dev, "using no AI\n");
1057 regmap_config = &pca953x_i2c_regmap;
1058 }
1059
1060 chip->regmap = devm_regmap_init_i2c(client, regmap_config);
1061 if (IS_ERR(chip->regmap)) {
1062 ret = PTR_ERR(chip->regmap);
1063 goto err_exit;
1064 }
1065
1066 regcache_mark_dirty(chip->regmap);
1067
1068 mutex_init(&chip->i2c_lock);
1069 /*
1070 * In case we have an i2c-mux controlled by a GPIO provided by an
1071 * expander using the same driver higher on the device tree, read the
1072 * i2c adapter nesting depth and use the retrieved value as lockdep
1073 * subclass for chip->i2c_lock.
1074 *
1075 * REVISIT: This solution is not complete. It protects us from lockdep
1076 * false positives when the expander controlling the i2c-mux is on
1077 * a different level on the device tree, but not when it's on the same
1078 * level on a different branch (in which case the subclass number
1079 * would be the same).
1080 *
1081 * TODO: Once a correct solution is developed, a similar fix should be
1082 * applied to all other i2c-controlled GPIO expanders (and potentially
1083 * regmap-i2c).
1084 */
1085 lockdep_set_subclass(&chip->i2c_lock,
1086 i2c_adapter_depth(client->adapter));
1087
1088 /* initialize cached registers from their original values.
1089 * we can't share this chip with another i2c master.
1090 */
1091
1092 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
1093 chip->regs = &pca953x_regs;
1094 ret = device_pca95xx_init(chip, invert);
1095 } else {
1096 chip->regs = &pca957x_regs;
1097 ret = device_pca957x_init(chip, invert);
1098 }
1099 if (ret)
1100 goto err_exit;
1101
1102 ret = pca953x_irq_setup(chip, irq_base);
1103 if (ret)
1104 goto err_exit;
1105
1106 ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
1107 if (ret)
1108 goto err_exit;
1109
1110 if (pdata && pdata->setup) {
1111 ret = pdata->setup(client, chip->gpio_chip.base,
1112 chip->gpio_chip.ngpio, pdata->context);
1113 if (ret < 0)
1114 dev_warn(&client->dev, "setup failed, %d\n", ret);
1115 }
1116
1117 return 0;
1118
1119err_exit:
1120 regulator_disable(chip->regulator);
1121 return ret;
1122}
1123
1124static int pca953x_remove(struct i2c_client *client)
1125{
1126 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
1127 struct pca953x_chip *chip = i2c_get_clientdata(client);
1128 int ret;
1129
1130 if (pdata && pdata->teardown) {
1131 ret = pdata->teardown(client, chip->gpio_chip.base,
1132 chip->gpio_chip.ngpio, pdata->context);
1133 if (ret < 0)
1134 dev_err(&client->dev, "teardown failed, %d\n", ret);
1135 } else {
1136 ret = 0;
1137 }
1138
1139 regulator_disable(chip->regulator);
1140
1141 return ret;
1142}
1143
1144#ifdef CONFIG_PM_SLEEP
1145static int pca953x_regcache_sync(struct device *dev)
1146{
1147 struct pca953x_chip *chip = dev_get_drvdata(dev);
1148 int ret;
1149
1150 /*
1151 * The ordering between direction and output is important,
1152 * sync these registers first and only then sync the rest.
1153 */
1154 ret = regcache_sync_region(chip->regmap, chip->regs->direction,
1155 chip->regs->direction + NBANK(chip));
1156 if (ret) {
1157 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret);
1158 return ret;
1159 }
1160
1161 ret = regcache_sync_region(chip->regmap, chip->regs->output,
1162 chip->regs->output + NBANK(chip));
1163 if (ret) {
1164 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret);
1165 return ret;
1166 }
1167
1168#ifdef CONFIG_GPIO_PCA953X_IRQ
1169 if (chip->driver_data & PCA_PCAL) {
1170 ret = regcache_sync_region(chip->regmap, PCAL953X_IN_LATCH,
1171 PCAL953X_IN_LATCH + NBANK(chip));
1172 if (ret) {
1173 dev_err(dev, "Failed to sync INT latch registers: %d\n",
1174 ret);
1175 return ret;
1176 }
1177
1178 ret = regcache_sync_region(chip->regmap, PCAL953X_INT_MASK,
1179 PCAL953X_INT_MASK + NBANK(chip));
1180 if (ret) {
1181 dev_err(dev, "Failed to sync INT mask registers: %d\n",
1182 ret);
1183 return ret;
1184 }
1185 }
1186#endif
1187
1188 return 0;
1189}
1190
1191static int pca953x_suspend(struct device *dev)
1192{
1193 struct pca953x_chip *chip = dev_get_drvdata(dev);
1194
1195 regcache_cache_only(chip->regmap, true);
1196
1197 if (atomic_read(&chip->wakeup_path))
1198 device_set_wakeup_path(dev);
1199 else
1200 regulator_disable(chip->regulator);
1201
1202 return 0;
1203}
1204
1205static int pca953x_resume(struct device *dev)
1206{
1207 struct pca953x_chip *chip = dev_get_drvdata(dev);
1208 int ret;
1209
1210 if (!atomic_read(&chip->wakeup_path)) {
1211 ret = regulator_enable(chip->regulator);
1212 if (ret) {
1213 dev_err(dev, "Failed to enable regulator: %d\n", ret);
1214 return 0;
1215 }
1216 }
1217
1218 regcache_cache_only(chip->regmap, false);
1219 regcache_mark_dirty(chip->regmap);
1220 ret = pca953x_regcache_sync(dev);
1221 if (ret)
1222 return ret;
1223
1224 ret = regcache_sync(chip->regmap);
1225 if (ret) {
1226 dev_err(dev, "Failed to restore register map: %d\n", ret);
1227 return ret;
1228 }
1229
1230 return 0;
1231}
1232#endif
1233
1234/* convenience to stop overlong match-table lines */
1235#define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
1236#define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
1237
1238static const struct of_device_id pca953x_dt_ids[] = {
1239 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), },
1240 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
1241 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
1242 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
1243 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
1244 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
1245 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
1246 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
1247 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
1248 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
1249 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
1250 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
1251 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
1252 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
1253 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
1254
1255 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), },
1256 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
1257 { .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), },
1258 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), },
1259
1260 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
1261 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
1262 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
1263 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
1264 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), },
1265
1266 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
1267 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
1268 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
1269 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
1270 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
1271 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), },
1272
1273 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), },
1274 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), },
1275
1276 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
1277 { }
1278};
1279
1280MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
1281
1282static SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume);
1283
1284static struct i2c_driver pca953x_driver = {
1285 .driver = {
1286 .name = "pca953x",
1287 .pm = &pca953x_pm_ops,
1288 .of_match_table = pca953x_dt_ids,
1289 .acpi_match_table = pca953x_acpi_ids,
1290 },
1291 .probe = pca953x_probe,
1292 .remove = pca953x_remove,
1293 .id_table = pca953x_id,
1294};
1295
1296static int __init pca953x_init(void)
1297{
1298 return i2c_add_driver(&pca953x_driver);
1299}
1300/* register after i2c postcore initcall and before
1301 * subsys initcalls that may rely on these GPIOs
1302 */
1303subsys_initcall(pca953x_init);
1304
1305static void __exit pca953x_exit(void)
1306{
1307 i2c_del_driver(&pca953x_driver);
1308}
1309module_exit(pca953x_exit);
1310
1311MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
1312MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
1313MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * PCA953x 4/8/16/24/40 bit I/O ports
4 *
5 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
6 * Copyright (C) 2007 Marvell International Ltd.
7 *
8 * Derived from drivers/i2c/chips/pca9539.c
9 */
10
11#include <linux/acpi.h>
12#include <linux/bitmap.h>
13#include <linux/gpio/consumer.h>
14#include <linux/gpio/driver.h>
15#include <linux/i2c.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/module.h>
19#include <linux/of_platform.h>
20#include <linux/platform_data/pca953x.h>
21#include <linux/regmap.h>
22#include <linux/regulator/consumer.h>
23#include <linux/seq_file.h>
24#include <linux/slab.h>
25
26#include <asm/unaligned.h>
27
28#define PCA953X_INPUT 0x00
29#define PCA953X_OUTPUT 0x01
30#define PCA953X_INVERT 0x02
31#define PCA953X_DIRECTION 0x03
32
33#define REG_ADDR_MASK GENMASK(5, 0)
34#define REG_ADDR_EXT BIT(6)
35#define REG_ADDR_AI BIT(7)
36
37#define PCA957X_IN 0x00
38#define PCA957X_INVRT 0x01
39#define PCA957X_BKEN 0x02
40#define PCA957X_PUPD 0x03
41#define PCA957X_CFG 0x04
42#define PCA957X_OUT 0x05
43#define PCA957X_MSK 0x06
44#define PCA957X_INTS 0x07
45
46#define PCAL953X_OUT_STRENGTH 0x20
47#define PCAL953X_IN_LATCH 0x22
48#define PCAL953X_PULL_EN 0x23
49#define PCAL953X_PULL_SEL 0x24
50#define PCAL953X_INT_MASK 0x25
51#define PCAL953X_INT_STAT 0x26
52#define PCAL953X_OUT_CONF 0x27
53
54#define PCAL6524_INT_EDGE 0x28
55#define PCAL6524_INT_CLR 0x2a
56#define PCAL6524_IN_STATUS 0x2b
57#define PCAL6524_OUT_INDCONF 0x2c
58#define PCAL6524_DEBOUNCE 0x2d
59
60#define PCA_GPIO_MASK GENMASK(7, 0)
61
62#define PCAL_GPIO_MASK GENMASK(4, 0)
63#define PCAL_PINCTRL_MASK GENMASK(6, 5)
64
65#define PCA_INT BIT(8)
66#define PCA_PCAL BIT(9)
67#define PCA_LATCH_INT (PCA_PCAL | PCA_INT)
68#define PCA953X_TYPE BIT(12)
69#define PCA957X_TYPE BIT(13)
70#define PCAL653X_TYPE BIT(14)
71#define PCA_TYPE_MASK GENMASK(15, 12)
72
73#define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
74
75static const struct i2c_device_id pca953x_id[] = {
76 { "pca6408", 8 | PCA953X_TYPE | PCA_INT, },
77 { "pca6416", 16 | PCA953X_TYPE | PCA_INT, },
78 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
79 { "pca9506", 40 | PCA953X_TYPE | PCA_INT, },
80 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
81 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
82 { "pca9536", 4 | PCA953X_TYPE, },
83 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
84 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
85 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
86 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
87 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
88 { "pca9556", 8 | PCA953X_TYPE, },
89 { "pca9557", 8 | PCA953X_TYPE, },
90 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
91 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
92 { "pca9698", 40 | PCA953X_TYPE, },
93
94 { "pcal6408", 8 | PCA953X_TYPE | PCA_LATCH_INT, },
95 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
96 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, },
97 { "pcal6534", 34 | PCAL653X_TYPE | PCA_LATCH_INT, },
98 { "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
99 { "pcal9554b", 8 | PCA953X_TYPE | PCA_LATCH_INT, },
100 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
101
102 { "max7310", 8 | PCA953X_TYPE, },
103 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
104 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
105 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
106 { "max7318", 16 | PCA953X_TYPE | PCA_INT, },
107 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
108 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
109 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
110 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
111 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
112 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, },
113 { "xra1202", 8 | PCA953X_TYPE },
114 { }
115};
116MODULE_DEVICE_TABLE(i2c, pca953x_id);
117
118#ifdef CONFIG_GPIO_PCA953X_IRQ
119
120#include <linux/dmi.h>
121
122static const struct acpi_gpio_params pca953x_irq_gpios = { 0, 0, true };
123
124static const struct acpi_gpio_mapping pca953x_acpi_irq_gpios[] = {
125 { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
126 { }
127};
128
129static int pca953x_acpi_get_irq(struct device *dev)
130{
131 int ret;
132
133 ret = devm_acpi_dev_add_driver_gpios(dev, pca953x_acpi_irq_gpios);
134 if (ret)
135 dev_warn(dev, "can't add GPIO ACPI mapping\n");
136
137 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq-gpios", 0);
138 if (ret < 0)
139 return ret;
140
141 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret);
142 return ret;
143}
144
145static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = {
146 {
147 /*
148 * On Intel Galileo Gen 2 board the IRQ pin of one of
149 * the I²C GPIO expanders, which has GpioInt() resource,
150 * is provided as an absolute number instead of being
151 * relative. Since first controller (gpio-sch.c) and
152 * second (gpio-dwapb.c) are at the fixed bases, we may
153 * safely refer to the number in the global space to get
154 * an IRQ out of it.
155 */
156 .matches = {
157 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
158 },
159 },
160 {}
161};
162#endif
163
164static const struct acpi_device_id pca953x_acpi_ids[] = {
165 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
166 { }
167};
168MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
169
170#define MAX_BANK 5
171#define BANK_SZ 8
172#define MAX_LINE (MAX_BANK * BANK_SZ)
173
174#define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
175
176struct pca953x_reg_config {
177 int direction;
178 int output;
179 int input;
180 int invert;
181};
182
183static const struct pca953x_reg_config pca953x_regs = {
184 .direction = PCA953X_DIRECTION,
185 .output = PCA953X_OUTPUT,
186 .input = PCA953X_INPUT,
187 .invert = PCA953X_INVERT,
188};
189
190static const struct pca953x_reg_config pca957x_regs = {
191 .direction = PCA957X_CFG,
192 .output = PCA957X_OUT,
193 .input = PCA957X_IN,
194 .invert = PCA957X_INVRT,
195};
196
197struct pca953x_chip {
198 unsigned gpio_start;
199 struct mutex i2c_lock;
200 struct regmap *regmap;
201
202#ifdef CONFIG_GPIO_PCA953X_IRQ
203 struct mutex irq_lock;
204 DECLARE_BITMAP(irq_mask, MAX_LINE);
205 DECLARE_BITMAP(irq_stat, MAX_LINE);
206 DECLARE_BITMAP(irq_trig_raise, MAX_LINE);
207 DECLARE_BITMAP(irq_trig_fall, MAX_LINE);
208#endif
209 atomic_t wakeup_path;
210
211 struct i2c_client *client;
212 struct gpio_chip gpio_chip;
213 const char *const *names;
214 unsigned long driver_data;
215 struct regulator *regulator;
216
217 const struct pca953x_reg_config *regs;
218
219 u8 (*recalc_addr)(struct pca953x_chip *chip, int reg, int off);
220 bool (*check_reg)(struct pca953x_chip *chip, unsigned int reg,
221 u32 checkbank);
222};
223
224static int pca953x_bank_shift(struct pca953x_chip *chip)
225{
226 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
227}
228
229#define PCA953x_BANK_INPUT BIT(0)
230#define PCA953x_BANK_OUTPUT BIT(1)
231#define PCA953x_BANK_POLARITY BIT(2)
232#define PCA953x_BANK_CONFIG BIT(3)
233
234#define PCA957x_BANK_INPUT BIT(0)
235#define PCA957x_BANK_POLARITY BIT(1)
236#define PCA957x_BANK_BUSHOLD BIT(2)
237#define PCA957x_BANK_CONFIG BIT(4)
238#define PCA957x_BANK_OUTPUT BIT(5)
239
240#define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2)
241#define PCAL9xxx_BANK_PULL_EN BIT(8 + 3)
242#define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4)
243#define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5)
244#define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6)
245
246/*
247 * We care about the following registers:
248 * - Standard set, below 0x40, each port can be replicated up to 8 times
249 * - PCA953x standard
250 * Input port 0x00 + 0 * bank_size R
251 * Output port 0x00 + 1 * bank_size RW
252 * Polarity Inversion port 0x00 + 2 * bank_size RW
253 * Configuration port 0x00 + 3 * bank_size RW
254 * - PCA957x with mixed up registers
255 * Input port 0x00 + 0 * bank_size R
256 * Polarity Inversion port 0x00 + 1 * bank_size RW
257 * Bus hold port 0x00 + 2 * bank_size RW
258 * Configuration port 0x00 + 4 * bank_size RW
259 * Output port 0x00 + 5 * bank_size RW
260 *
261 * - Extended set, above 0x40, often chip specific.
262 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling:
263 * Input latch register 0x40 + 2 * bank_size RW
264 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW
265 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW
266 * Interrupt mask register 0x40 + 5 * bank_size RW
267 * Interrupt status register 0x40 + 6 * bank_size R
268 *
269 * - Registers with bit 0x80 set, the AI bit
270 * The bit is cleared and the registers fall into one of the
271 * categories above.
272 */
273
274static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg,
275 u32 checkbank)
276{
277 int bank_shift = pca953x_bank_shift(chip);
278 int bank = (reg & REG_ADDR_MASK) >> bank_shift;
279 int offset = reg & (BIT(bank_shift) - 1);
280
281 /* Special PCAL extended register check. */
282 if (reg & REG_ADDR_EXT) {
283 if (!(chip->driver_data & PCA_PCAL))
284 return false;
285 bank += 8;
286 }
287
288 /* Register is not in the matching bank. */
289 if (!(BIT(bank) & checkbank))
290 return false;
291
292 /* Register is not within allowed range of bank. */
293 if (offset >= NBANK(chip))
294 return false;
295
296 return true;
297}
298
299/*
300 * Unfortunately, whilst the PCAL6534 chip (and compatibles) broadly follow the
301 * same register layout as the PCAL6524, the spacing of the registers has been
302 * fundamentally altered by compacting them and thus does not obey the same
303 * rules, including being able to use bit shifting to determine bank. These
304 * chips hence need special handling here.
305 */
306static bool pcal6534_check_register(struct pca953x_chip *chip, unsigned int reg,
307 u32 checkbank)
308{
309 int bank;
310 int offset;
311
312 if (reg >= 0x30) {
313 /*
314 * Reserved block between 14h and 2Fh does not align on
315 * expected bank boundaries like other devices.
316 */
317 int temp = reg - 0x30;
318
319 bank = temp / NBANK(chip);
320 offset = temp - (bank * NBANK(chip));
321 bank += 8;
322 } else if (reg >= 0x54) {
323 /*
324 * Handle lack of reserved registers after output port
325 * configuration register to form a bank.
326 */
327 int temp = reg - 0x54;
328
329 bank = temp / NBANK(chip);
330 offset = temp - (bank * NBANK(chip));
331 bank += 16;
332 } else {
333 bank = reg / NBANK(chip);
334 offset = reg - (bank * NBANK(chip));
335 }
336
337 /* Register is not in the matching bank. */
338 if (!(BIT(bank) & checkbank))
339 return false;
340
341 /* Register is not within allowed range of bank. */
342 if (offset >= NBANK(chip))
343 return false;
344
345 return true;
346}
347
348static bool pca953x_readable_register(struct device *dev, unsigned int reg)
349{
350 struct pca953x_chip *chip = dev_get_drvdata(dev);
351 u32 bank;
352
353 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
354 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT |
355 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG |
356 PCA957x_BANK_BUSHOLD;
357 } else {
358 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT |
359 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG;
360 }
361
362 if (chip->driver_data & PCA_PCAL) {
363 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
364 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK |
365 PCAL9xxx_BANK_IRQ_STAT;
366 }
367
368 return chip->check_reg(chip, reg, bank);
369}
370
371static bool pca953x_writeable_register(struct device *dev, unsigned int reg)
372{
373 struct pca953x_chip *chip = dev_get_drvdata(dev);
374 u32 bank;
375
376 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
377 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY |
378 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD;
379 } else {
380 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY |
381 PCA953x_BANK_CONFIG;
382 }
383
384 if (chip->driver_data & PCA_PCAL)
385 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
386 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK;
387
388 return chip->check_reg(chip, reg, bank);
389}
390
391static bool pca953x_volatile_register(struct device *dev, unsigned int reg)
392{
393 struct pca953x_chip *chip = dev_get_drvdata(dev);
394 u32 bank;
395
396 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE)
397 bank = PCA957x_BANK_INPUT;
398 else
399 bank = PCA953x_BANK_INPUT;
400
401 if (chip->driver_data & PCA_PCAL)
402 bank |= PCAL9xxx_BANK_IRQ_STAT;
403
404 return chip->check_reg(chip, reg, bank);
405}
406
407static const struct regmap_config pca953x_i2c_regmap = {
408 .reg_bits = 8,
409 .val_bits = 8,
410
411 .use_single_read = true,
412 .use_single_write = true,
413
414 .readable_reg = pca953x_readable_register,
415 .writeable_reg = pca953x_writeable_register,
416 .volatile_reg = pca953x_volatile_register,
417
418 .disable_locking = true,
419 .cache_type = REGCACHE_RBTREE,
420 .max_register = 0x7f,
421};
422
423static const struct regmap_config pca953x_ai_i2c_regmap = {
424 .reg_bits = 8,
425 .val_bits = 8,
426
427 .read_flag_mask = REG_ADDR_AI,
428 .write_flag_mask = REG_ADDR_AI,
429
430 .readable_reg = pca953x_readable_register,
431 .writeable_reg = pca953x_writeable_register,
432 .volatile_reg = pca953x_volatile_register,
433
434 .disable_locking = true,
435 .cache_type = REGCACHE_RBTREE,
436 .max_register = 0x7f,
437};
438
439static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off)
440{
441 int bank_shift = pca953x_bank_shift(chip);
442 int addr = (reg & PCAL_GPIO_MASK) << bank_shift;
443 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1;
444 u8 regaddr = pinctrl | addr | (off / BANK_SZ);
445
446 return regaddr;
447}
448
449/*
450 * The PCAL6534 and compatible chips have altered bank alignment that doesn't
451 * fit within the bit shifting scheme used for other devices.
452 */
453static u8 pcal6534_recalc_addr(struct pca953x_chip *chip, int reg, int off)
454{
455 int addr;
456 int pinctrl;
457
458 addr = (reg & PCAL_GPIO_MASK) * NBANK(chip);
459
460 switch (reg) {
461 case PCAL953X_OUT_STRENGTH:
462 case PCAL953X_IN_LATCH:
463 case PCAL953X_PULL_EN:
464 case PCAL953X_PULL_SEL:
465 case PCAL953X_INT_MASK:
466 case PCAL953X_INT_STAT:
467 case PCAL953X_OUT_CONF:
468 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x20;
469 break;
470 case PCAL6524_INT_EDGE:
471 case PCAL6524_INT_CLR:
472 case PCAL6524_IN_STATUS:
473 case PCAL6524_OUT_INDCONF:
474 case PCAL6524_DEBOUNCE:
475 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x1c;
476 break;
477 default:
478 pinctrl = 0;
479 break;
480 }
481
482 return pinctrl + addr + (off / BANK_SZ);
483}
484
485static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
486{
487 u8 regaddr = chip->recalc_addr(chip, reg, 0);
488 u8 value[MAX_BANK];
489 int i, ret;
490
491 for (i = 0; i < NBANK(chip); i++)
492 value[i] = bitmap_get_value8(val, i * BANK_SZ);
493
494 ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip));
495 if (ret < 0) {
496 dev_err(&chip->client->dev, "failed writing register\n");
497 return ret;
498 }
499
500 return 0;
501}
502
503static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
504{
505 u8 regaddr = chip->recalc_addr(chip, reg, 0);
506 u8 value[MAX_BANK];
507 int i, ret;
508
509 ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip));
510 if (ret < 0) {
511 dev_err(&chip->client->dev, "failed reading register\n");
512 return ret;
513 }
514
515 for (i = 0; i < NBANK(chip); i++)
516 bitmap_set_value8(val, value[i], i * BANK_SZ);
517
518 return 0;
519}
520
521static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
522{
523 struct pca953x_chip *chip = gpiochip_get_data(gc);
524 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
525 u8 bit = BIT(off % BANK_SZ);
526 int ret;
527
528 mutex_lock(&chip->i2c_lock);
529 ret = regmap_write_bits(chip->regmap, dirreg, bit, bit);
530 mutex_unlock(&chip->i2c_lock);
531 return ret;
532}
533
534static int pca953x_gpio_direction_output(struct gpio_chip *gc,
535 unsigned off, int val)
536{
537 struct pca953x_chip *chip = gpiochip_get_data(gc);
538 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
539 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off);
540 u8 bit = BIT(off % BANK_SZ);
541 int ret;
542
543 mutex_lock(&chip->i2c_lock);
544 /* set output level */
545 ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
546 if (ret)
547 goto exit;
548
549 /* then direction */
550 ret = regmap_write_bits(chip->regmap, dirreg, bit, 0);
551exit:
552 mutex_unlock(&chip->i2c_lock);
553 return ret;
554}
555
556static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
557{
558 struct pca953x_chip *chip = gpiochip_get_data(gc);
559 u8 inreg = chip->recalc_addr(chip, chip->regs->input, off);
560 u8 bit = BIT(off % BANK_SZ);
561 u32 reg_val;
562 int ret;
563
564 mutex_lock(&chip->i2c_lock);
565 ret = regmap_read(chip->regmap, inreg, ®_val);
566 mutex_unlock(&chip->i2c_lock);
567 if (ret < 0)
568 return ret;
569
570 return !!(reg_val & bit);
571}
572
573static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
574{
575 struct pca953x_chip *chip = gpiochip_get_data(gc);
576 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off);
577 u8 bit = BIT(off % BANK_SZ);
578
579 mutex_lock(&chip->i2c_lock);
580 regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
581 mutex_unlock(&chip->i2c_lock);
582}
583
584static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off)
585{
586 struct pca953x_chip *chip = gpiochip_get_data(gc);
587 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
588 u8 bit = BIT(off % BANK_SZ);
589 u32 reg_val;
590 int ret;
591
592 mutex_lock(&chip->i2c_lock);
593 ret = regmap_read(chip->regmap, dirreg, ®_val);
594 mutex_unlock(&chip->i2c_lock);
595 if (ret < 0)
596 return ret;
597
598 if (reg_val & bit)
599 return GPIO_LINE_DIRECTION_IN;
600
601 return GPIO_LINE_DIRECTION_OUT;
602}
603
604static int pca953x_gpio_get_multiple(struct gpio_chip *gc,
605 unsigned long *mask, unsigned long *bits)
606{
607 struct pca953x_chip *chip = gpiochip_get_data(gc);
608 DECLARE_BITMAP(reg_val, MAX_LINE);
609 int ret;
610
611 mutex_lock(&chip->i2c_lock);
612 ret = pca953x_read_regs(chip, chip->regs->input, reg_val);
613 mutex_unlock(&chip->i2c_lock);
614 if (ret)
615 return ret;
616
617 bitmap_replace(bits, bits, reg_val, mask, gc->ngpio);
618 return 0;
619}
620
621static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
622 unsigned long *mask, unsigned long *bits)
623{
624 struct pca953x_chip *chip = gpiochip_get_data(gc);
625 DECLARE_BITMAP(reg_val, MAX_LINE);
626 int ret;
627
628 mutex_lock(&chip->i2c_lock);
629 ret = pca953x_read_regs(chip, chip->regs->output, reg_val);
630 if (ret)
631 goto exit;
632
633 bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio);
634
635 pca953x_write_regs(chip, chip->regs->output, reg_val);
636exit:
637 mutex_unlock(&chip->i2c_lock);
638}
639
640static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip,
641 unsigned int offset,
642 unsigned long config)
643{
644 enum pin_config_param param = pinconf_to_config_param(config);
645
646 u8 pull_en_reg = chip->recalc_addr(chip, PCAL953X_PULL_EN, offset);
647 u8 pull_sel_reg = chip->recalc_addr(chip, PCAL953X_PULL_SEL, offset);
648 u8 bit = BIT(offset % BANK_SZ);
649 int ret;
650
651 /*
652 * pull-up/pull-down configuration requires PCAL extended
653 * registers
654 */
655 if (!(chip->driver_data & PCA_PCAL))
656 return -ENOTSUPP;
657
658 mutex_lock(&chip->i2c_lock);
659
660 /* Configure pull-up/pull-down */
661 if (param == PIN_CONFIG_BIAS_PULL_UP)
662 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit);
663 else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
664 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0);
665 else
666 ret = 0;
667 if (ret)
668 goto exit;
669
670 /* Disable/Enable pull-up/pull-down */
671 if (param == PIN_CONFIG_BIAS_DISABLE)
672 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0);
673 else
674 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit);
675
676exit:
677 mutex_unlock(&chip->i2c_lock);
678 return ret;
679}
680
681static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
682 unsigned long config)
683{
684 struct pca953x_chip *chip = gpiochip_get_data(gc);
685
686 switch (pinconf_to_config_param(config)) {
687 case PIN_CONFIG_BIAS_PULL_UP:
688 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
689 case PIN_CONFIG_BIAS_PULL_DOWN:
690 case PIN_CONFIG_BIAS_DISABLE:
691 return pca953x_gpio_set_pull_up_down(chip, offset, config);
692 default:
693 return -ENOTSUPP;
694 }
695}
696
697static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
698{
699 struct gpio_chip *gc;
700
701 gc = &chip->gpio_chip;
702
703 gc->direction_input = pca953x_gpio_direction_input;
704 gc->direction_output = pca953x_gpio_direction_output;
705 gc->get = pca953x_gpio_get_value;
706 gc->set = pca953x_gpio_set_value;
707 gc->get_direction = pca953x_gpio_get_direction;
708 gc->get_multiple = pca953x_gpio_get_multiple;
709 gc->set_multiple = pca953x_gpio_set_multiple;
710 gc->set_config = pca953x_gpio_set_config;
711 gc->can_sleep = true;
712
713 gc->base = chip->gpio_start;
714 gc->ngpio = gpios;
715 gc->label = dev_name(&chip->client->dev);
716 gc->parent = &chip->client->dev;
717 gc->owner = THIS_MODULE;
718 gc->names = chip->names;
719}
720
721#ifdef CONFIG_GPIO_PCA953X_IRQ
722static void pca953x_irq_mask(struct irq_data *d)
723{
724 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
725 struct pca953x_chip *chip = gpiochip_get_data(gc);
726 irq_hw_number_t hwirq = irqd_to_hwirq(d);
727
728 clear_bit(hwirq, chip->irq_mask);
729 gpiochip_disable_irq(gc, hwirq);
730}
731
732static void pca953x_irq_unmask(struct irq_data *d)
733{
734 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
735 struct pca953x_chip *chip = gpiochip_get_data(gc);
736 irq_hw_number_t hwirq = irqd_to_hwirq(d);
737
738 gpiochip_enable_irq(gc, hwirq);
739 set_bit(hwirq, chip->irq_mask);
740}
741
742static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on)
743{
744 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
745 struct pca953x_chip *chip = gpiochip_get_data(gc);
746
747 if (on)
748 atomic_inc(&chip->wakeup_path);
749 else
750 atomic_dec(&chip->wakeup_path);
751
752 return irq_set_irq_wake(chip->client->irq, on);
753}
754
755static void pca953x_irq_bus_lock(struct irq_data *d)
756{
757 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
758 struct pca953x_chip *chip = gpiochip_get_data(gc);
759
760 mutex_lock(&chip->irq_lock);
761}
762
763static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
764{
765 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
766 struct pca953x_chip *chip = gpiochip_get_data(gc);
767 DECLARE_BITMAP(irq_mask, MAX_LINE);
768 DECLARE_BITMAP(reg_direction, MAX_LINE);
769 int level;
770
771 if (chip->driver_data & PCA_PCAL) {
772 /* Enable latch on interrupt-enabled inputs */
773 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
774
775 bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio);
776
777 /* Unmask enabled interrupts */
778 pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask);
779 }
780
781 /* Switch direction to input if needed */
782 pca953x_read_regs(chip, chip->regs->direction, reg_direction);
783
784 bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio);
785 bitmap_complement(reg_direction, reg_direction, gc->ngpio);
786 bitmap_and(irq_mask, irq_mask, reg_direction, gc->ngpio);
787
788 /* Look for any newly setup interrupt */
789 for_each_set_bit(level, irq_mask, gc->ngpio)
790 pca953x_gpio_direction_input(&chip->gpio_chip, level);
791
792 mutex_unlock(&chip->irq_lock);
793}
794
795static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
796{
797 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
798 struct pca953x_chip *chip = gpiochip_get_data(gc);
799 irq_hw_number_t hwirq = irqd_to_hwirq(d);
800
801 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
802 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
803 d->irq, type);
804 return -EINVAL;
805 }
806
807 assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING);
808 assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING);
809
810 return 0;
811}
812
813static void pca953x_irq_shutdown(struct irq_data *d)
814{
815 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
816 struct pca953x_chip *chip = gpiochip_get_data(gc);
817 irq_hw_number_t hwirq = irqd_to_hwirq(d);
818
819 clear_bit(hwirq, chip->irq_trig_raise);
820 clear_bit(hwirq, chip->irq_trig_fall);
821}
822
823static void pca953x_irq_print_chip(struct irq_data *data, struct seq_file *p)
824{
825 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
826
827 seq_printf(p, dev_name(gc->parent));
828}
829
830static const struct irq_chip pca953x_irq_chip = {
831 .irq_mask = pca953x_irq_mask,
832 .irq_unmask = pca953x_irq_unmask,
833 .irq_set_wake = pca953x_irq_set_wake,
834 .irq_bus_lock = pca953x_irq_bus_lock,
835 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
836 .irq_set_type = pca953x_irq_set_type,
837 .irq_shutdown = pca953x_irq_shutdown,
838 .irq_print_chip = pca953x_irq_print_chip,
839 .flags = IRQCHIP_IMMUTABLE,
840 GPIOCHIP_IRQ_RESOURCE_HELPERS,
841};
842
843static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending)
844{
845 struct gpio_chip *gc = &chip->gpio_chip;
846 DECLARE_BITMAP(reg_direction, MAX_LINE);
847 DECLARE_BITMAP(old_stat, MAX_LINE);
848 DECLARE_BITMAP(cur_stat, MAX_LINE);
849 DECLARE_BITMAP(new_stat, MAX_LINE);
850 DECLARE_BITMAP(trigger, MAX_LINE);
851 int ret;
852
853 if (chip->driver_data & PCA_PCAL) {
854 /* Read the current interrupt status from the device */
855 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
856 if (ret)
857 return false;
858
859 /* Check latched inputs and clear interrupt status */
860 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
861 if (ret)
862 return false;
863
864 /* Apply filter for rising/falling edge selection */
865 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, cur_stat, gc->ngpio);
866
867 bitmap_and(pending, new_stat, trigger, gc->ngpio);
868
869 return !bitmap_empty(pending, gc->ngpio);
870 }
871
872 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
873 if (ret)
874 return false;
875
876 /* Remove output pins from the equation */
877 pca953x_read_regs(chip, chip->regs->direction, reg_direction);
878
879 bitmap_copy(old_stat, chip->irq_stat, gc->ngpio);
880
881 bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio);
882 bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio);
883 bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio);
884
885 bitmap_copy(chip->irq_stat, new_stat, gc->ngpio);
886
887 if (bitmap_empty(trigger, gc->ngpio))
888 return false;
889
890 bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio);
891 bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio);
892 bitmap_or(new_stat, old_stat, cur_stat, gc->ngpio);
893 bitmap_and(pending, new_stat, trigger, gc->ngpio);
894
895 return !bitmap_empty(pending, gc->ngpio);
896}
897
898static irqreturn_t pca953x_irq_handler(int irq, void *devid)
899{
900 struct pca953x_chip *chip = devid;
901 struct gpio_chip *gc = &chip->gpio_chip;
902 DECLARE_BITMAP(pending, MAX_LINE);
903 int level;
904 bool ret;
905
906 bitmap_zero(pending, MAX_LINE);
907
908 mutex_lock(&chip->i2c_lock);
909 ret = pca953x_irq_pending(chip, pending);
910 mutex_unlock(&chip->i2c_lock);
911
912 if (ret) {
913 ret = 0;
914
915 for_each_set_bit(level, pending, gc->ngpio) {
916 int nested_irq = irq_find_mapping(gc->irq.domain, level);
917
918 if (unlikely(nested_irq <= 0)) {
919 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);
920 continue;
921 }
922
923 handle_nested_irq(nested_irq);
924 ret = 1;
925 }
926 }
927
928 return IRQ_RETVAL(ret);
929}
930
931static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base)
932{
933 struct i2c_client *client = chip->client;
934 DECLARE_BITMAP(reg_direction, MAX_LINE);
935 DECLARE_BITMAP(irq_stat, MAX_LINE);
936 struct gpio_irq_chip *girq;
937 int ret;
938
939 if (dmi_first_match(pca953x_dmi_acpi_irq_info)) {
940 ret = pca953x_acpi_get_irq(&client->dev);
941 if (ret > 0)
942 client->irq = ret;
943 }
944
945 if (!client->irq)
946 return 0;
947
948 if (irq_base == -1)
949 return 0;
950
951 if (!(chip->driver_data & PCA_INT))
952 return 0;
953
954 ret = pca953x_read_regs(chip, chip->regs->input, irq_stat);
955 if (ret)
956 return ret;
957
958 /*
959 * There is no way to know which GPIO line generated the
960 * interrupt. We have to rely on the previous read for
961 * this purpose.
962 */
963 pca953x_read_regs(chip, chip->regs->direction, reg_direction);
964 bitmap_and(chip->irq_stat, irq_stat, reg_direction, chip->gpio_chip.ngpio);
965 mutex_init(&chip->irq_lock);
966
967 girq = &chip->gpio_chip.irq;
968 gpio_irq_chip_set_chip(girq, &pca953x_irq_chip);
969 /* This will let us handle the parent IRQ in the driver */
970 girq->parent_handler = NULL;
971 girq->num_parents = 0;
972 girq->parents = NULL;
973 girq->default_type = IRQ_TYPE_NONE;
974 girq->handler = handle_simple_irq;
975 girq->threaded = true;
976 girq->first = irq_base; /* FIXME: get rid of this */
977
978 ret = devm_request_threaded_irq(&client->dev, client->irq,
979 NULL, pca953x_irq_handler,
980 IRQF_ONESHOT | IRQF_SHARED,
981 dev_name(&client->dev), chip);
982 if (ret) {
983 dev_err(&client->dev, "failed to request irq %d\n",
984 client->irq);
985 return ret;
986 }
987
988 return 0;
989}
990
991#else /* CONFIG_GPIO_PCA953X_IRQ */
992static int pca953x_irq_setup(struct pca953x_chip *chip,
993 int irq_base)
994{
995 struct i2c_client *client = chip->client;
996
997 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT))
998 dev_warn(&client->dev, "interrupt support not compiled in\n");
999
1000 return 0;
1001}
1002#endif
1003
1004static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert)
1005{
1006 DECLARE_BITMAP(val, MAX_LINE);
1007 u8 regaddr;
1008 int ret;
1009
1010 regaddr = chip->recalc_addr(chip, chip->regs->output, 0);
1011 ret = regcache_sync_region(chip->regmap, regaddr,
1012 regaddr + NBANK(chip) - 1);
1013 if (ret)
1014 goto out;
1015
1016 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0);
1017 ret = regcache_sync_region(chip->regmap, regaddr,
1018 regaddr + NBANK(chip) - 1);
1019 if (ret)
1020 goto out;
1021
1022 /* set platform specific polarity inversion */
1023 if (invert)
1024 bitmap_fill(val, MAX_LINE);
1025 else
1026 bitmap_zero(val, MAX_LINE);
1027
1028 ret = pca953x_write_regs(chip, chip->regs->invert, val);
1029out:
1030 return ret;
1031}
1032
1033static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
1034{
1035 DECLARE_BITMAP(val, MAX_LINE);
1036 unsigned int i;
1037 int ret;
1038
1039 ret = device_pca95xx_init(chip, invert);
1040 if (ret)
1041 goto out;
1042
1043 /* To enable register 6, 7 to control pull up and pull down */
1044 for (i = 0; i < NBANK(chip); i++)
1045 bitmap_set_value8(val, 0x02, i * BANK_SZ);
1046
1047 ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
1048 if (ret)
1049 goto out;
1050
1051 return 0;
1052out:
1053 return ret;
1054}
1055
1056static int pca953x_probe(struct i2c_client *client)
1057{
1058 const struct i2c_device_id *i2c_id = i2c_client_get_device_id(client);
1059 struct pca953x_platform_data *pdata;
1060 struct pca953x_chip *chip;
1061 int irq_base = 0;
1062 int ret;
1063 u32 invert = 0;
1064 struct regulator *reg;
1065 const struct regmap_config *regmap_config;
1066
1067 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
1068 if (chip == NULL)
1069 return -ENOMEM;
1070
1071 pdata = dev_get_platdata(&client->dev);
1072 if (pdata) {
1073 irq_base = pdata->irq_base;
1074 chip->gpio_start = pdata->gpio_base;
1075 invert = pdata->invert;
1076 chip->names = pdata->names;
1077 } else {
1078 struct gpio_desc *reset_gpio;
1079
1080 chip->gpio_start = -1;
1081 irq_base = 0;
1082
1083 /*
1084 * See if we need to de-assert a reset pin.
1085 *
1086 * There is no known ACPI-enabled platforms that are
1087 * using "reset" GPIO. Otherwise any of those platform
1088 * must use _DSD method with corresponding property.
1089 */
1090 reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1091 GPIOD_OUT_LOW);
1092 if (IS_ERR(reset_gpio))
1093 return PTR_ERR(reset_gpio);
1094 }
1095
1096 chip->client = client;
1097
1098 reg = devm_regulator_get(&client->dev, "vcc");
1099 if (IS_ERR(reg))
1100 return dev_err_probe(&client->dev, PTR_ERR(reg), "reg get err\n");
1101
1102 ret = regulator_enable(reg);
1103 if (ret) {
1104 dev_err(&client->dev, "reg en err: %d\n", ret);
1105 return ret;
1106 }
1107 chip->regulator = reg;
1108
1109 if (i2c_id) {
1110 chip->driver_data = i2c_id->driver_data;
1111 } else {
1112 const void *match;
1113
1114 match = device_get_match_data(&client->dev);
1115 if (!match) {
1116 ret = -ENODEV;
1117 goto err_exit;
1118 }
1119
1120 chip->driver_data = (uintptr_t)match;
1121 }
1122
1123 i2c_set_clientdata(client, chip);
1124
1125 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
1126
1127 if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
1128 dev_info(&client->dev, "using AI\n");
1129 regmap_config = &pca953x_ai_i2c_regmap;
1130 } else {
1131 dev_info(&client->dev, "using no AI\n");
1132 regmap_config = &pca953x_i2c_regmap;
1133 }
1134
1135 if (PCA_CHIP_TYPE(chip->driver_data) == PCAL653X_TYPE) {
1136 chip->recalc_addr = pcal6534_recalc_addr;
1137 chip->check_reg = pcal6534_check_register;
1138 } else {
1139 chip->recalc_addr = pca953x_recalc_addr;
1140 chip->check_reg = pca953x_check_register;
1141 }
1142
1143 chip->regmap = devm_regmap_init_i2c(client, regmap_config);
1144 if (IS_ERR(chip->regmap)) {
1145 ret = PTR_ERR(chip->regmap);
1146 goto err_exit;
1147 }
1148
1149 regcache_mark_dirty(chip->regmap);
1150
1151 mutex_init(&chip->i2c_lock);
1152 /*
1153 * In case we have an i2c-mux controlled by a GPIO provided by an
1154 * expander using the same driver higher on the device tree, read the
1155 * i2c adapter nesting depth and use the retrieved value as lockdep
1156 * subclass for chip->i2c_lock.
1157 *
1158 * REVISIT: This solution is not complete. It protects us from lockdep
1159 * false positives when the expander controlling the i2c-mux is on
1160 * a different level on the device tree, but not when it's on the same
1161 * level on a different branch (in which case the subclass number
1162 * would be the same).
1163 *
1164 * TODO: Once a correct solution is developed, a similar fix should be
1165 * applied to all other i2c-controlled GPIO expanders (and potentially
1166 * regmap-i2c).
1167 */
1168 lockdep_set_subclass(&chip->i2c_lock,
1169 i2c_adapter_depth(client->adapter));
1170
1171 /* initialize cached registers from their original values.
1172 * we can't share this chip with another i2c master.
1173 */
1174 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
1175 chip->regs = &pca957x_regs;
1176 ret = device_pca957x_init(chip, invert);
1177 } else {
1178 chip->regs = &pca953x_regs;
1179 ret = device_pca95xx_init(chip, invert);
1180 }
1181 if (ret)
1182 goto err_exit;
1183
1184 ret = pca953x_irq_setup(chip, irq_base);
1185 if (ret)
1186 goto err_exit;
1187
1188 ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
1189 if (ret)
1190 goto err_exit;
1191
1192 if (pdata && pdata->setup) {
1193 ret = pdata->setup(client, chip->gpio_chip.base,
1194 chip->gpio_chip.ngpio, pdata->context);
1195 if (ret < 0)
1196 dev_warn(&client->dev, "setup failed, %d\n", ret);
1197 }
1198
1199 return 0;
1200
1201err_exit:
1202 regulator_disable(chip->regulator);
1203 return ret;
1204}
1205
1206static void pca953x_remove(struct i2c_client *client)
1207{
1208 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
1209 struct pca953x_chip *chip = i2c_get_clientdata(client);
1210
1211 if (pdata && pdata->teardown) {
1212 pdata->teardown(client, chip->gpio_chip.base,
1213 chip->gpio_chip.ngpio, pdata->context);
1214 }
1215
1216 regulator_disable(chip->regulator);
1217}
1218
1219#ifdef CONFIG_PM_SLEEP
1220static int pca953x_regcache_sync(struct device *dev)
1221{
1222 struct pca953x_chip *chip = dev_get_drvdata(dev);
1223 int ret;
1224 u8 regaddr;
1225
1226 /*
1227 * The ordering between direction and output is important,
1228 * sync these registers first and only then sync the rest.
1229 */
1230 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0);
1231 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1);
1232 if (ret) {
1233 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret);
1234 return ret;
1235 }
1236
1237 regaddr = chip->recalc_addr(chip, chip->regs->output, 0);
1238 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1);
1239 if (ret) {
1240 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret);
1241 return ret;
1242 }
1243
1244#ifdef CONFIG_GPIO_PCA953X_IRQ
1245 if (chip->driver_data & PCA_PCAL) {
1246 regaddr = chip->recalc_addr(chip, PCAL953X_IN_LATCH, 0);
1247 ret = regcache_sync_region(chip->regmap, regaddr,
1248 regaddr + NBANK(chip) - 1);
1249 if (ret) {
1250 dev_err(dev, "Failed to sync INT latch registers: %d\n",
1251 ret);
1252 return ret;
1253 }
1254
1255 regaddr = chip->recalc_addr(chip, PCAL953X_INT_MASK, 0);
1256 ret = regcache_sync_region(chip->regmap, regaddr,
1257 regaddr + NBANK(chip) - 1);
1258 if (ret) {
1259 dev_err(dev, "Failed to sync INT mask registers: %d\n",
1260 ret);
1261 return ret;
1262 }
1263 }
1264#endif
1265
1266 return 0;
1267}
1268
1269static int pca953x_suspend(struct device *dev)
1270{
1271 struct pca953x_chip *chip = dev_get_drvdata(dev);
1272
1273 mutex_lock(&chip->i2c_lock);
1274 regcache_cache_only(chip->regmap, true);
1275 mutex_unlock(&chip->i2c_lock);
1276
1277 if (atomic_read(&chip->wakeup_path))
1278 device_set_wakeup_path(dev);
1279 else
1280 regulator_disable(chip->regulator);
1281
1282 return 0;
1283}
1284
1285static int pca953x_resume(struct device *dev)
1286{
1287 struct pca953x_chip *chip = dev_get_drvdata(dev);
1288 int ret;
1289
1290 if (!atomic_read(&chip->wakeup_path)) {
1291 ret = regulator_enable(chip->regulator);
1292 if (ret) {
1293 dev_err(dev, "Failed to enable regulator: %d\n", ret);
1294 return 0;
1295 }
1296 }
1297
1298 mutex_lock(&chip->i2c_lock);
1299 regcache_cache_only(chip->regmap, false);
1300 regcache_mark_dirty(chip->regmap);
1301 ret = pca953x_regcache_sync(dev);
1302 if (ret) {
1303 mutex_unlock(&chip->i2c_lock);
1304 return ret;
1305 }
1306
1307 ret = regcache_sync(chip->regmap);
1308 mutex_unlock(&chip->i2c_lock);
1309 if (ret) {
1310 dev_err(dev, "Failed to restore register map: %d\n", ret);
1311 return ret;
1312 }
1313
1314 return 0;
1315}
1316#endif
1317
1318/* convenience to stop overlong match-table lines */
1319#define OF_653X(__nrgpio, __int) ((void *)(__nrgpio | PCAL653X_TYPE | __int))
1320#define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
1321#define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
1322
1323static const struct of_device_id pca953x_dt_ids[] = {
1324 { .compatible = "nxp,pca6408", .data = OF_953X(8, PCA_INT), },
1325 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), },
1326 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
1327 { .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_INT), },
1328 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
1329 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
1330 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
1331 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
1332 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
1333 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
1334 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
1335 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
1336 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
1337 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
1338 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
1339 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
1340 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
1341
1342 { .compatible = "nxp,pcal6408", .data = OF_953X(8, PCA_LATCH_INT), },
1343 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), },
1344 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
1345 { .compatible = "nxp,pcal6534", .data = OF_653X(34, PCA_LATCH_INT), },
1346 { .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), },
1347 { .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), },
1348 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), },
1349
1350 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
1351 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
1352 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
1353 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
1354 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), },
1355
1356 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
1357 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
1358 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
1359 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
1360 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
1361 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), },
1362
1363 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), },
1364 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), },
1365 { .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), },
1366
1367 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
1368 { }
1369};
1370
1371MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
1372
1373static SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume);
1374
1375static struct i2c_driver pca953x_driver = {
1376 .driver = {
1377 .name = "pca953x",
1378 .pm = &pca953x_pm_ops,
1379 .of_match_table = pca953x_dt_ids,
1380 .acpi_match_table = pca953x_acpi_ids,
1381 },
1382 .probe_new = pca953x_probe,
1383 .remove = pca953x_remove,
1384 .id_table = pca953x_id,
1385};
1386
1387static int __init pca953x_init(void)
1388{
1389 return i2c_add_driver(&pca953x_driver);
1390}
1391/* register after i2c postcore initcall and before
1392 * subsys initcalls that may rely on these GPIOs
1393 */
1394subsys_initcall(pca953x_init);
1395
1396static void __exit pca953x_exit(void)
1397{
1398 i2c_del_driver(&pca953x_driver);
1399}
1400module_exit(pca953x_exit);
1401
1402MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
1403MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
1404MODULE_LICENSE("GPL");