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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Contains common pci routines for ALL ppc platform
4 * (based on pci_32.c and pci_64.c)
5 *
6 * Port for PPC64 David Engebretsen, IBM Corp.
7 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 *
9 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
10 * Rework, based on alpha PCI code.
11 *
12 * Common pmac/prep/chrp pci routines. -- Cort
13 */
14
15#include <linux/kernel.h>
16#include <linux/pci.h>
17#include <linux/string.h>
18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/export.h>
21#include <linux/of_address.h>
22#include <linux/of_pci.h>
23#include <linux/mm.h>
24#include <linux/shmem_fs.h>
25#include <linux/list.h>
26#include <linux/syscalls.h>
27#include <linux/irq.h>
28#include <linux/vmalloc.h>
29#include <linux/slab.h>
30#include <linux/vgaarb.h>
31#include <linux/numa.h>
32
33#include <asm/processor.h>
34#include <asm/io.h>
35#include <asm/prom.h>
36#include <asm/pci-bridge.h>
37#include <asm/byteorder.h>
38#include <asm/machdep.h>
39#include <asm/ppc-pci.h>
40#include <asm/eeh.h>
41
42#include "../../../drivers/pci/pci.h"
43
44/* hose_spinlock protects accesses to the the phb_bitmap. */
45static DEFINE_SPINLOCK(hose_spinlock);
46LIST_HEAD(hose_list);
47
48/* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */
49#define MAX_PHBS 0x10000
50
51/*
52 * For dynamic PHB numbering: used/free PHBs tracking bitmap.
53 * Accesses to this bitmap should be protected by hose_spinlock.
54 */
55static DECLARE_BITMAP(phb_bitmap, MAX_PHBS);
56
57/* ISA Memory physical address */
58resource_size_t isa_mem_base;
59EXPORT_SYMBOL(isa_mem_base);
60
61
62static const struct dma_map_ops *pci_dma_ops;
63
64void set_pci_dma_ops(const struct dma_map_ops *dma_ops)
65{
66 pci_dma_ops = dma_ops;
67}
68
69/*
70 * This function should run under locking protection, specifically
71 * hose_spinlock.
72 */
73static int get_phb_number(struct device_node *dn)
74{
75 int ret, phb_id = -1;
76 u32 prop_32;
77 u64 prop;
78
79 /*
80 * Try fixed PHB numbering first, by checking archs and reading
81 * the respective device-tree properties. Firstly, try powernv by
82 * reading "ibm,opal-phbid", only present in OPAL environment.
83 */
84 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
85 if (ret) {
86 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32);
87 prop = prop_32;
88 }
89
90 if (!ret)
91 phb_id = (int)(prop & (MAX_PHBS - 1));
92
93 /* We need to be sure to not use the same PHB number twice. */
94 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap))
95 return phb_id;
96
97 /*
98 * If not pseries nor powernv, or if fixed PHB numbering tried to add
99 * the same PHB number twice, then fallback to dynamic PHB numbering.
100 */
101 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS);
102 BUG_ON(phb_id >= MAX_PHBS);
103 set_bit(phb_id, phb_bitmap);
104
105 return phb_id;
106}
107
108struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
109{
110 struct pci_controller *phb;
111
112 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
113 if (phb == NULL)
114 return NULL;
115 spin_lock(&hose_spinlock);
116 phb->global_number = get_phb_number(dev);
117 list_add_tail(&phb->list_node, &hose_list);
118 spin_unlock(&hose_spinlock);
119 phb->dn = dev;
120 phb->is_dynamic = slab_is_available();
121#ifdef CONFIG_PPC64
122 if (dev) {
123 int nid = of_node_to_nid(dev);
124
125 if (nid < 0 || !node_online(nid))
126 nid = NUMA_NO_NODE;
127
128 PHB_SET_NODE(phb, nid);
129 }
130#endif
131 return phb;
132}
133EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
134
135void pcibios_free_controller(struct pci_controller *phb)
136{
137 spin_lock(&hose_spinlock);
138
139 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */
140 if (phb->global_number < MAX_PHBS)
141 clear_bit(phb->global_number, phb_bitmap);
142
143 list_del(&phb->list_node);
144 spin_unlock(&hose_spinlock);
145
146 if (phb->is_dynamic)
147 kfree(phb);
148}
149EXPORT_SYMBOL_GPL(pcibios_free_controller);
150
151/*
152 * This function is used to call pcibios_free_controller()
153 * in a deferred manner: a callback from the PCI subsystem.
154 *
155 * _*DO NOT*_ call pcibios_free_controller() explicitly if
156 * this is used (or it may access an invalid *phb pointer).
157 *
158 * The callback occurs when all references to the root bus
159 * are dropped (e.g., child buses/devices and their users).
160 *
161 * It's called as .release_fn() of 'struct pci_host_bridge'
162 * which is associated with the 'struct pci_controller.bus'
163 * (root bus) - it expects .release_data to hold a pointer
164 * to 'struct pci_controller'.
165 *
166 * In order to use it, register .release_fn()/release_data
167 * like this:
168 *
169 * pci_set_host_bridge_release(bridge,
170 * pcibios_free_controller_deferred
171 * (void *) phb);
172 *
173 * e.g. in the pcibios_root_bridge_prepare() callback from
174 * pci_create_root_bus().
175 */
176void pcibios_free_controller_deferred(struct pci_host_bridge *bridge)
177{
178 struct pci_controller *phb = (struct pci_controller *)
179 bridge->release_data;
180
181 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic);
182
183 pcibios_free_controller(phb);
184}
185EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred);
186
187/*
188 * The function is used to return the minimal alignment
189 * for memory or I/O windows of the associated P2P bridge.
190 * By default, 4KiB alignment for I/O windows and 1MiB for
191 * memory windows.
192 */
193resource_size_t pcibios_window_alignment(struct pci_bus *bus,
194 unsigned long type)
195{
196 struct pci_controller *phb = pci_bus_to_host(bus);
197
198 if (phb->controller_ops.window_alignment)
199 return phb->controller_ops.window_alignment(bus, type);
200
201 /*
202 * PCI core will figure out the default
203 * alignment: 4KiB for I/O and 1MiB for
204 * memory window.
205 */
206 return 1;
207}
208
209void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
210{
211 struct pci_controller *hose = pci_bus_to_host(bus);
212
213 if (hose->controller_ops.setup_bridge)
214 hose->controller_ops.setup_bridge(bus, type);
215}
216
217void pcibios_reset_secondary_bus(struct pci_dev *dev)
218{
219 struct pci_controller *phb = pci_bus_to_host(dev->bus);
220
221 if (phb->controller_ops.reset_secondary_bus) {
222 phb->controller_ops.reset_secondary_bus(dev);
223 return;
224 }
225
226 pci_reset_secondary_bus(dev);
227}
228
229resource_size_t pcibios_default_alignment(void)
230{
231 if (ppc_md.pcibios_default_alignment)
232 return ppc_md.pcibios_default_alignment();
233
234 return 0;
235}
236
237#ifdef CONFIG_PCI_IOV
238resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
239{
240 if (ppc_md.pcibios_iov_resource_alignment)
241 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
242
243 return pci_iov_resource_size(pdev, resno);
244}
245
246int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
247{
248 if (ppc_md.pcibios_sriov_enable)
249 return ppc_md.pcibios_sriov_enable(pdev, num_vfs);
250
251 return 0;
252}
253
254int pcibios_sriov_disable(struct pci_dev *pdev)
255{
256 if (ppc_md.pcibios_sriov_disable)
257 return ppc_md.pcibios_sriov_disable(pdev);
258
259 return 0;
260}
261
262#endif /* CONFIG_PCI_IOV */
263
264static resource_size_t pcibios_io_size(const struct pci_controller *hose)
265{
266#ifdef CONFIG_PPC64
267 return hose->pci_io_size;
268#else
269 return resource_size(&hose->io_resource);
270#endif
271}
272
273int pcibios_vaddr_is_ioport(void __iomem *address)
274{
275 int ret = 0;
276 struct pci_controller *hose;
277 resource_size_t size;
278
279 spin_lock(&hose_spinlock);
280 list_for_each_entry(hose, &hose_list, list_node) {
281 size = pcibios_io_size(hose);
282 if (address >= hose->io_base_virt &&
283 address < (hose->io_base_virt + size)) {
284 ret = 1;
285 break;
286 }
287 }
288 spin_unlock(&hose_spinlock);
289 return ret;
290}
291
292unsigned long pci_address_to_pio(phys_addr_t address)
293{
294 struct pci_controller *hose;
295 resource_size_t size;
296 unsigned long ret = ~0;
297
298 spin_lock(&hose_spinlock);
299 list_for_each_entry(hose, &hose_list, list_node) {
300 size = pcibios_io_size(hose);
301 if (address >= hose->io_base_phys &&
302 address < (hose->io_base_phys + size)) {
303 unsigned long base =
304 (unsigned long)hose->io_base_virt - _IO_BASE;
305 ret = base + (address - hose->io_base_phys);
306 break;
307 }
308 }
309 spin_unlock(&hose_spinlock);
310
311 return ret;
312}
313EXPORT_SYMBOL_GPL(pci_address_to_pio);
314
315/*
316 * Return the domain number for this bus.
317 */
318int pci_domain_nr(struct pci_bus *bus)
319{
320 struct pci_controller *hose = pci_bus_to_host(bus);
321
322 return hose->global_number;
323}
324EXPORT_SYMBOL(pci_domain_nr);
325
326/* This routine is meant to be used early during boot, when the
327 * PCI bus numbers have not yet been assigned, and you need to
328 * issue PCI config cycles to an OF device.
329 * It could also be used to "fix" RTAS config cycles if you want
330 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
331 * config cycles.
332 */
333struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
334{
335 while(node) {
336 struct pci_controller *hose, *tmp;
337 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
338 if (hose->dn == node)
339 return hose;
340 node = node->parent;
341 }
342 return NULL;
343}
344
345struct pci_controller *pci_find_controller_for_domain(int domain_nr)
346{
347 struct pci_controller *hose;
348
349 list_for_each_entry(hose, &hose_list, list_node)
350 if (hose->global_number == domain_nr)
351 return hose;
352
353 return NULL;
354}
355
356/*
357 * Reads the interrupt pin to determine if interrupt is use by card.
358 * If the interrupt is used, then gets the interrupt line from the
359 * openfirmware and sets it in the pci_dev and pci_config line.
360 */
361static int pci_read_irq_line(struct pci_dev *pci_dev)
362{
363 int virq;
364
365 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
366
367 /* Try to get a mapping from the device-tree */
368 virq = of_irq_parse_and_map_pci(pci_dev, 0, 0);
369 if (virq <= 0) {
370 u8 line, pin;
371
372 /* If that fails, lets fallback to what is in the config
373 * space and map that through the default controller. We
374 * also set the type to level low since that's what PCI
375 * interrupts are. If your platform does differently, then
376 * either provide a proper interrupt tree or don't use this
377 * function.
378 */
379 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
380 return -1;
381 if (pin == 0)
382 return -1;
383 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
384 line == 0xff || line == 0) {
385 return -1;
386 }
387 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
388 line, pin);
389
390 virq = irq_create_mapping(NULL, line);
391 if (virq)
392 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
393 }
394
395 if (!virq) {
396 pr_debug(" Failed to map !\n");
397 return -1;
398 }
399
400 pr_debug(" Mapped to linux irq %d\n", virq);
401
402 pci_dev->irq = virq;
403
404 return 0;
405}
406
407/*
408 * Platform support for /proc/bus/pci/X/Y mmap()s.
409 * -- paulus.
410 */
411int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
412{
413 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
414 resource_size_t ioaddr = pci_resource_start(pdev, bar);
415
416 if (!hose)
417 return -EINVAL;
418
419 /* Convert to an offset within this PCI controller */
420 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
421
422 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
423 return 0;
424}
425
426/*
427 * This one is used by /dev/mem and fbdev who have no clue about the
428 * PCI device, it tries to find the PCI device first and calls the
429 * above routine
430 */
431pgprot_t pci_phys_mem_access_prot(struct file *file,
432 unsigned long pfn,
433 unsigned long size,
434 pgprot_t prot)
435{
436 struct pci_dev *pdev = NULL;
437 struct resource *found = NULL;
438 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
439 int i;
440
441 if (page_is_ram(pfn))
442 return prot;
443
444 prot = pgprot_noncached(prot);
445 for_each_pci_dev(pdev) {
446 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
447 struct resource *rp = &pdev->resource[i];
448 int flags = rp->flags;
449
450 /* Active and same type? */
451 if ((flags & IORESOURCE_MEM) == 0)
452 continue;
453 /* In the range of this resource? */
454 if (offset < (rp->start & PAGE_MASK) ||
455 offset > rp->end)
456 continue;
457 found = rp;
458 break;
459 }
460 if (found)
461 break;
462 }
463 if (found) {
464 if (found->flags & IORESOURCE_PREFETCH)
465 prot = pgprot_noncached_wc(prot);
466 pci_dev_put(pdev);
467 }
468
469 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
470 (unsigned long long)offset, pgprot_val(prot));
471
472 return prot;
473}
474
475/* This provides legacy IO read access on a bus */
476int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
477{
478 unsigned long offset;
479 struct pci_controller *hose = pci_bus_to_host(bus);
480 struct resource *rp = &hose->io_resource;
481 void __iomem *addr;
482
483 /* Check if port can be supported by that bus. We only check
484 * the ranges of the PHB though, not the bus itself as the rules
485 * for forwarding legacy cycles down bridges are not our problem
486 * here. So if the host bridge supports it, we do it.
487 */
488 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
489 offset += port;
490
491 if (!(rp->flags & IORESOURCE_IO))
492 return -ENXIO;
493 if (offset < rp->start || (offset + size) > rp->end)
494 return -ENXIO;
495 addr = hose->io_base_virt + port;
496
497 switch(size) {
498 case 1:
499 *((u8 *)val) = in_8(addr);
500 return 1;
501 case 2:
502 if (port & 1)
503 return -EINVAL;
504 *((u16 *)val) = in_le16(addr);
505 return 2;
506 case 4:
507 if (port & 3)
508 return -EINVAL;
509 *((u32 *)val) = in_le32(addr);
510 return 4;
511 }
512 return -EINVAL;
513}
514
515/* This provides legacy IO write access on a bus */
516int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
517{
518 unsigned long offset;
519 struct pci_controller *hose = pci_bus_to_host(bus);
520 struct resource *rp = &hose->io_resource;
521 void __iomem *addr;
522
523 /* Check if port can be supported by that bus. We only check
524 * the ranges of the PHB though, not the bus itself as the rules
525 * for forwarding legacy cycles down bridges are not our problem
526 * here. So if the host bridge supports it, we do it.
527 */
528 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
529 offset += port;
530
531 if (!(rp->flags & IORESOURCE_IO))
532 return -ENXIO;
533 if (offset < rp->start || (offset + size) > rp->end)
534 return -ENXIO;
535 addr = hose->io_base_virt + port;
536
537 /* WARNING: The generic code is idiotic. It gets passed a pointer
538 * to what can be a 1, 2 or 4 byte quantity and always reads that
539 * as a u32, which means that we have to correct the location of
540 * the data read within those 32 bits for size 1 and 2
541 */
542 switch(size) {
543 case 1:
544 out_8(addr, val >> 24);
545 return 1;
546 case 2:
547 if (port & 1)
548 return -EINVAL;
549 out_le16(addr, val >> 16);
550 return 2;
551 case 4:
552 if (port & 3)
553 return -EINVAL;
554 out_le32(addr, val);
555 return 4;
556 }
557 return -EINVAL;
558}
559
560/* This provides legacy IO or memory mmap access on a bus */
561int pci_mmap_legacy_page_range(struct pci_bus *bus,
562 struct vm_area_struct *vma,
563 enum pci_mmap_state mmap_state)
564{
565 struct pci_controller *hose = pci_bus_to_host(bus);
566 resource_size_t offset =
567 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
568 resource_size_t size = vma->vm_end - vma->vm_start;
569 struct resource *rp;
570
571 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
572 pci_domain_nr(bus), bus->number,
573 mmap_state == pci_mmap_mem ? "MEM" : "IO",
574 (unsigned long long)offset,
575 (unsigned long long)(offset + size - 1));
576
577 if (mmap_state == pci_mmap_mem) {
578 /* Hack alert !
579 *
580 * Because X is lame and can fail starting if it gets an error trying
581 * to mmap legacy_mem (instead of just moving on without legacy memory
582 * access) we fake it here by giving it anonymous memory, effectively
583 * behaving just like /dev/zero
584 */
585 if ((offset + size) > hose->isa_mem_size) {
586 printk(KERN_DEBUG
587 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
588 current->comm, current->pid, pci_domain_nr(bus), bus->number);
589 if (vma->vm_flags & VM_SHARED)
590 return shmem_zero_setup(vma);
591 return 0;
592 }
593 offset += hose->isa_mem_phys;
594 } else {
595 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
596 unsigned long roffset = offset + io_offset;
597 rp = &hose->io_resource;
598 if (!(rp->flags & IORESOURCE_IO))
599 return -ENXIO;
600 if (roffset < rp->start || (roffset + size) > rp->end)
601 return -ENXIO;
602 offset += hose->io_base_phys;
603 }
604 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
605
606 vma->vm_pgoff = offset >> PAGE_SHIFT;
607 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
608 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
609 vma->vm_end - vma->vm_start,
610 vma->vm_page_prot);
611}
612
613void pci_resource_to_user(const struct pci_dev *dev, int bar,
614 const struct resource *rsrc,
615 resource_size_t *start, resource_size_t *end)
616{
617 struct pci_bus_region region;
618
619 if (rsrc->flags & IORESOURCE_IO) {
620 pcibios_resource_to_bus(dev->bus, ®ion,
621 (struct resource *) rsrc);
622 *start = region.start;
623 *end = region.end;
624 return;
625 }
626
627 /* We pass a CPU physical address to userland for MMIO instead of a
628 * BAR value because X is lame and expects to be able to use that
629 * to pass to /dev/mem!
630 *
631 * That means we may have 64-bit values where some apps only expect
632 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
633 */
634 *start = rsrc->start;
635 *end = rsrc->end;
636}
637
638/**
639 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
640 * @hose: newly allocated pci_controller to be setup
641 * @dev: device node of the host bridge
642 * @primary: set if primary bus (32 bits only, soon to be deprecated)
643 *
644 * This function will parse the "ranges" property of a PCI host bridge device
645 * node and setup the resource mapping of a pci controller based on its
646 * content.
647 *
648 * Life would be boring if it wasn't for a few issues that we have to deal
649 * with here:
650 *
651 * - We can only cope with one IO space range and up to 3 Memory space
652 * ranges. However, some machines (thanks Apple !) tend to split their
653 * space into lots of small contiguous ranges. So we have to coalesce.
654 *
655 * - Some busses have IO space not starting at 0, which causes trouble with
656 * the way we do our IO resource renumbering. The code somewhat deals with
657 * it for 64 bits but I would expect problems on 32 bits.
658 *
659 * - Some 32 bits platforms such as 4xx can have physical space larger than
660 * 32 bits so we need to use 64 bits values for the parsing
661 */
662void pci_process_bridge_OF_ranges(struct pci_controller *hose,
663 struct device_node *dev, int primary)
664{
665 int memno = 0;
666 struct resource *res;
667 struct of_pci_range range;
668 struct of_pci_range_parser parser;
669
670 printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n",
671 dev, primary ? "(primary)" : "");
672
673 /* Check for ranges property */
674 if (of_pci_range_parser_init(&parser, dev))
675 return;
676
677 /* Parse it */
678 for_each_of_pci_range(&parser, &range) {
679 /* If we failed translation or got a zero-sized region
680 * (some FW try to feed us with non sensical zero sized regions
681 * such as power3 which look like some kind of attempt at exposing
682 * the VGA memory hole)
683 */
684 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
685 continue;
686
687 /* Act based on address space type */
688 res = NULL;
689 switch (range.flags & IORESOURCE_TYPE_BITS) {
690 case IORESOURCE_IO:
691 printk(KERN_INFO
692 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
693 range.cpu_addr, range.cpu_addr + range.size - 1,
694 range.pci_addr);
695
696 /* We support only one IO range */
697 if (hose->pci_io_size) {
698 printk(KERN_INFO
699 " \\--> Skipped (too many) !\n");
700 continue;
701 }
702#ifdef CONFIG_PPC32
703 /* On 32 bits, limit I/O space to 16MB */
704 if (range.size > 0x01000000)
705 range.size = 0x01000000;
706
707 /* 32 bits needs to map IOs here */
708 hose->io_base_virt = ioremap(range.cpu_addr,
709 range.size);
710
711 /* Expect trouble if pci_addr is not 0 */
712 if (primary)
713 isa_io_base =
714 (unsigned long)hose->io_base_virt;
715#endif /* CONFIG_PPC32 */
716 /* pci_io_size and io_base_phys always represent IO
717 * space starting at 0 so we factor in pci_addr
718 */
719 hose->pci_io_size = range.pci_addr + range.size;
720 hose->io_base_phys = range.cpu_addr - range.pci_addr;
721
722 /* Build resource */
723 res = &hose->io_resource;
724 range.cpu_addr = range.pci_addr;
725 break;
726 case IORESOURCE_MEM:
727 printk(KERN_INFO
728 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
729 range.cpu_addr, range.cpu_addr + range.size - 1,
730 range.pci_addr,
731 (range.flags & IORESOURCE_PREFETCH) ?
732 "Prefetch" : "");
733
734 /* We support only 3 memory ranges */
735 if (memno >= 3) {
736 printk(KERN_INFO
737 " \\--> Skipped (too many) !\n");
738 continue;
739 }
740 /* Handles ISA memory hole space here */
741 if (range.pci_addr == 0) {
742 if (primary || isa_mem_base == 0)
743 isa_mem_base = range.cpu_addr;
744 hose->isa_mem_phys = range.cpu_addr;
745 hose->isa_mem_size = range.size;
746 }
747
748 /* Build resource */
749 hose->mem_offset[memno] = range.cpu_addr -
750 range.pci_addr;
751 res = &hose->mem_resources[memno++];
752 break;
753 }
754 if (res != NULL) {
755 res->name = dev->full_name;
756 res->flags = range.flags;
757 res->start = range.cpu_addr;
758 res->end = range.cpu_addr + range.size - 1;
759 res->parent = res->child = res->sibling = NULL;
760 }
761 }
762}
763
764/* Decide whether to display the domain number in /proc */
765int pci_proc_domain(struct pci_bus *bus)
766{
767 struct pci_controller *hose = pci_bus_to_host(bus);
768
769 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
770 return 0;
771 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
772 return hose->global_number != 0;
773 return 1;
774}
775
776int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
777{
778 if (ppc_md.pcibios_root_bridge_prepare)
779 return ppc_md.pcibios_root_bridge_prepare(bridge);
780
781 return 0;
782}
783
784/* This header fixup will do the resource fixup for all devices as they are
785 * probed, but not for bridge ranges
786 */
787static void pcibios_fixup_resources(struct pci_dev *dev)
788{
789 struct pci_controller *hose = pci_bus_to_host(dev->bus);
790 int i;
791
792 if (!hose) {
793 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
794 pci_name(dev));
795 return;
796 }
797
798 if (dev->is_virtfn)
799 return;
800
801 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
802 struct resource *res = dev->resource + i;
803 struct pci_bus_region reg;
804 if (!res->flags)
805 continue;
806
807 /* If we're going to re-assign everything, we mark all resources
808 * as unset (and 0-base them). In addition, we mark BARs starting
809 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
810 * since in that case, we don't want to re-assign anything
811 */
812 pcibios_resource_to_bus(dev->bus, ®, res);
813 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
814 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
815 /* Only print message if not re-assigning */
816 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
817 pr_debug("PCI:%s Resource %d %pR is unassigned\n",
818 pci_name(dev), i, res);
819 res->end -= res->start;
820 res->start = 0;
821 res->flags |= IORESOURCE_UNSET;
822 continue;
823 }
824
825 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
826 }
827
828 /* Call machine specific resource fixup */
829 if (ppc_md.pcibios_fixup_resources)
830 ppc_md.pcibios_fixup_resources(dev);
831}
832DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
833
834/* This function tries to figure out if a bridge resource has been initialized
835 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
836 * things go more smoothly when it gets it right. It should covers cases such
837 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
838 */
839static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
840 struct resource *res)
841{
842 struct pci_controller *hose = pci_bus_to_host(bus);
843 struct pci_dev *dev = bus->self;
844 resource_size_t offset;
845 struct pci_bus_region region;
846 u16 command;
847 int i;
848
849 /* We don't do anything if PCI_PROBE_ONLY is set */
850 if (pci_has_flag(PCI_PROBE_ONLY))
851 return 0;
852
853 /* Job is a bit different between memory and IO */
854 if (res->flags & IORESOURCE_MEM) {
855 pcibios_resource_to_bus(dev->bus, ®ion, res);
856
857 /* If the BAR is non-0 then it's probably been initialized */
858 if (region.start != 0)
859 return 0;
860
861 /* The BAR is 0, let's check if memory decoding is enabled on
862 * the bridge. If not, we consider it unassigned
863 */
864 pci_read_config_word(dev, PCI_COMMAND, &command);
865 if ((command & PCI_COMMAND_MEMORY) == 0)
866 return 1;
867
868 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
869 * resources covers that starting address (0 then it's good enough for
870 * us for memory space)
871 */
872 for (i = 0; i < 3; i++) {
873 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
874 hose->mem_resources[i].start == hose->mem_offset[i])
875 return 0;
876 }
877
878 /* Well, it starts at 0 and we know it will collide so we may as
879 * well consider it as unassigned. That covers the Apple case.
880 */
881 return 1;
882 } else {
883 /* If the BAR is non-0, then we consider it assigned */
884 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
885 if (((res->start - offset) & 0xfffffffful) != 0)
886 return 0;
887
888 /* Here, we are a bit different than memory as typically IO space
889 * starting at low addresses -is- valid. What we do instead if that
890 * we consider as unassigned anything that doesn't have IO enabled
891 * in the PCI command register, and that's it.
892 */
893 pci_read_config_word(dev, PCI_COMMAND, &command);
894 if (command & PCI_COMMAND_IO)
895 return 0;
896
897 /* It's starting at 0 and IO is disabled in the bridge, consider
898 * it unassigned
899 */
900 return 1;
901 }
902}
903
904/* Fixup resources of a PCI<->PCI bridge */
905static void pcibios_fixup_bridge(struct pci_bus *bus)
906{
907 struct resource *res;
908 int i;
909
910 struct pci_dev *dev = bus->self;
911
912 pci_bus_for_each_resource(bus, res, i) {
913 if (!res || !res->flags)
914 continue;
915 if (i >= 3 && bus->self->transparent)
916 continue;
917
918 /* If we're going to reassign everything, we can
919 * shrink the P2P resource to have size as being
920 * of 0 in order to save space.
921 */
922 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
923 res->flags |= IORESOURCE_UNSET;
924 res->start = 0;
925 res->end = -1;
926 continue;
927 }
928
929 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
930
931 /* Try to detect uninitialized P2P bridge resources,
932 * and clear them out so they get re-assigned later
933 */
934 if (pcibios_uninitialized_bridge_resource(bus, res)) {
935 res->flags = 0;
936 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
937 }
938 }
939}
940
941void pcibios_setup_bus_self(struct pci_bus *bus)
942{
943 struct pci_controller *phb;
944
945 /* Fix up the bus resources for P2P bridges */
946 if (bus->self != NULL)
947 pcibios_fixup_bridge(bus);
948
949 /* Platform specific bus fixups. This is currently only used
950 * by fsl_pci and I'm hoping to get rid of it at some point
951 */
952 if (ppc_md.pcibios_fixup_bus)
953 ppc_md.pcibios_fixup_bus(bus);
954
955 /* Setup bus DMA mappings */
956 phb = pci_bus_to_host(bus);
957 if (phb->controller_ops.dma_bus_setup)
958 phb->controller_ops.dma_bus_setup(bus);
959}
960
961void pcibios_bus_add_device(struct pci_dev *dev)
962{
963 struct pci_controller *phb;
964 /* Fixup NUMA node as it may not be setup yet by the generic
965 * code and is needed by the DMA init
966 */
967 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
968
969 /* Hook up default DMA ops */
970 set_dma_ops(&dev->dev, pci_dma_ops);
971 dev->dev.archdata.dma_offset = PCI_DRAM_OFFSET;
972
973 /* Additional platform DMA/iommu setup */
974 phb = pci_bus_to_host(dev->bus);
975 if (phb->controller_ops.dma_dev_setup)
976 phb->controller_ops.dma_dev_setup(dev);
977
978 /* Read default IRQs and fixup if necessary */
979 pci_read_irq_line(dev);
980 if (ppc_md.pci_irq_fixup)
981 ppc_md.pci_irq_fixup(dev);
982
983 if (ppc_md.pcibios_bus_add_device)
984 ppc_md.pcibios_bus_add_device(dev);
985}
986
987int pcibios_add_device(struct pci_dev *dev)
988{
989#ifdef CONFIG_PCI_IOV
990 if (ppc_md.pcibios_fixup_sriov)
991 ppc_md.pcibios_fixup_sriov(dev);
992#endif /* CONFIG_PCI_IOV */
993
994 return 0;
995}
996
997void pcibios_set_master(struct pci_dev *dev)
998{
999 /* No special bus mastering setup handling */
1000}
1001
1002void pcibios_fixup_bus(struct pci_bus *bus)
1003{
1004 /* When called from the generic PCI probe, read PCI<->PCI bridge
1005 * bases. This is -not- called when generating the PCI tree from
1006 * the OF device-tree.
1007 */
1008 pci_read_bridge_bases(bus);
1009
1010 /* Now fixup the bus bus */
1011 pcibios_setup_bus_self(bus);
1012}
1013EXPORT_SYMBOL(pcibios_fixup_bus);
1014
1015static int skip_isa_ioresource_align(struct pci_dev *dev)
1016{
1017 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1018 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1019 return 1;
1020 return 0;
1021}
1022
1023/*
1024 * We need to avoid collisions with `mirrored' VGA ports
1025 * and other strange ISA hardware, so we always want the
1026 * addresses to be allocated in the 0x000-0x0ff region
1027 * modulo 0x400.
1028 *
1029 * Why? Because some silly external IO cards only decode
1030 * the low 10 bits of the IO address. The 0x00-0xff region
1031 * is reserved for motherboard devices that decode all 16
1032 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1033 * but we want to try to avoid allocating at 0x2900-0x2bff
1034 * which might have be mirrored at 0x0100-0x03ff..
1035 */
1036resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1037 resource_size_t size, resource_size_t align)
1038{
1039 struct pci_dev *dev = data;
1040 resource_size_t start = res->start;
1041
1042 if (res->flags & IORESOURCE_IO) {
1043 if (skip_isa_ioresource_align(dev))
1044 return start;
1045 if (start & 0x300)
1046 start = (start + 0x3ff) & ~0x3ff;
1047 }
1048
1049 return start;
1050}
1051EXPORT_SYMBOL(pcibios_align_resource);
1052
1053/*
1054 * Reparent resource children of pr that conflict with res
1055 * under res, and make res replace those children.
1056 */
1057static int reparent_resources(struct resource *parent,
1058 struct resource *res)
1059{
1060 struct resource *p, **pp;
1061 struct resource **firstpp = NULL;
1062
1063 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1064 if (p->end < res->start)
1065 continue;
1066 if (res->end < p->start)
1067 break;
1068 if (p->start < res->start || p->end > res->end)
1069 return -1; /* not completely contained */
1070 if (firstpp == NULL)
1071 firstpp = pp;
1072 }
1073 if (firstpp == NULL)
1074 return -1; /* didn't find any conflicting entries? */
1075 res->parent = parent;
1076 res->child = *firstpp;
1077 res->sibling = *pp;
1078 *firstpp = res;
1079 *pp = NULL;
1080 for (p = res->child; p != NULL; p = p->sibling) {
1081 p->parent = res;
1082 pr_debug("PCI: Reparented %s %pR under %s\n",
1083 p->name, p, res->name);
1084 }
1085 return 0;
1086}
1087
1088/*
1089 * Handle resources of PCI devices. If the world were perfect, we could
1090 * just allocate all the resource regions and do nothing more. It isn't.
1091 * On the other hand, we cannot just re-allocate all devices, as it would
1092 * require us to know lots of host bridge internals. So we attempt to
1093 * keep as much of the original configuration as possible, but tweak it
1094 * when it's found to be wrong.
1095 *
1096 * Known BIOS problems we have to work around:
1097 * - I/O or memory regions not configured
1098 * - regions configured, but not enabled in the command register
1099 * - bogus I/O addresses above 64K used
1100 * - expansion ROMs left enabled (this may sound harmless, but given
1101 * the fact the PCI specs explicitly allow address decoders to be
1102 * shared between expansion ROMs and other resource regions, it's
1103 * at least dangerous)
1104 *
1105 * Our solution:
1106 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1107 * This gives us fixed barriers on where we can allocate.
1108 * (2) Allocate resources for all enabled devices. If there is
1109 * a collision, just mark the resource as unallocated. Also
1110 * disable expansion ROMs during this step.
1111 * (3) Try to allocate resources for disabled devices. If the
1112 * resources were assigned correctly, everything goes well,
1113 * if they weren't, they won't disturb allocation of other
1114 * resources.
1115 * (4) Assign new addresses to resources which were either
1116 * not configured at all or misconfigured. If explicitly
1117 * requested by the user, configure expansion ROM address
1118 * as well.
1119 */
1120
1121static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1122{
1123 struct pci_bus *b;
1124 int i;
1125 struct resource *res, *pr;
1126
1127 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1128 pci_domain_nr(bus), bus->number);
1129
1130 pci_bus_for_each_resource(bus, res, i) {
1131 if (!res || !res->flags || res->start > res->end || res->parent)
1132 continue;
1133
1134 /* If the resource was left unset at this point, we clear it */
1135 if (res->flags & IORESOURCE_UNSET)
1136 goto clear_resource;
1137
1138 if (bus->parent == NULL)
1139 pr = (res->flags & IORESOURCE_IO) ?
1140 &ioport_resource : &iomem_resource;
1141 else {
1142 pr = pci_find_parent_resource(bus->self, res);
1143 if (pr == res) {
1144 /* this happens when the generic PCI
1145 * code (wrongly) decides that this
1146 * bridge is transparent -- paulus
1147 */
1148 continue;
1149 }
1150 }
1151
1152 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1153 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1154 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1155
1156 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1157 struct pci_dev *dev = bus->self;
1158
1159 if (request_resource(pr, res) == 0)
1160 continue;
1161 /*
1162 * Must be a conflict with an existing entry.
1163 * Move that entry (or entries) under the
1164 * bridge resource and try again.
1165 */
1166 if (reparent_resources(pr, res) == 0)
1167 continue;
1168
1169 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1170 pci_claim_bridge_resource(dev,
1171 i + PCI_BRIDGE_RESOURCES) == 0)
1172 continue;
1173 }
1174 pr_warn("PCI: Cannot allocate resource region %d of PCI bridge %d, will remap\n",
1175 i, bus->number);
1176 clear_resource:
1177 /* The resource might be figured out when doing
1178 * reassignment based on the resources required
1179 * by the downstream PCI devices. Here we set
1180 * the size of the resource to be 0 in order to
1181 * save more space.
1182 */
1183 res->start = 0;
1184 res->end = -1;
1185 res->flags = 0;
1186 }
1187
1188 list_for_each_entry(b, &bus->children, node)
1189 pcibios_allocate_bus_resources(b);
1190}
1191
1192static inline void alloc_resource(struct pci_dev *dev, int idx)
1193{
1194 struct resource *pr, *r = &dev->resource[idx];
1195
1196 pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1197 pci_name(dev), idx, r);
1198
1199 pr = pci_find_parent_resource(dev, r);
1200 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1201 request_resource(pr, r) < 0) {
1202 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1203 " of device %s, will remap\n", idx, pci_name(dev));
1204 if (pr)
1205 pr_debug("PCI: parent is %p: %pR\n", pr, pr);
1206 /* We'll assign a new address later */
1207 r->flags |= IORESOURCE_UNSET;
1208 r->end -= r->start;
1209 r->start = 0;
1210 }
1211}
1212
1213static void __init pcibios_allocate_resources(int pass)
1214{
1215 struct pci_dev *dev = NULL;
1216 int idx, disabled;
1217 u16 command;
1218 struct resource *r;
1219
1220 for_each_pci_dev(dev) {
1221 pci_read_config_word(dev, PCI_COMMAND, &command);
1222 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1223 r = &dev->resource[idx];
1224 if (r->parent) /* Already allocated */
1225 continue;
1226 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1227 continue; /* Not assigned at all */
1228 /* We only allocate ROMs on pass 1 just in case they
1229 * have been screwed up by firmware
1230 */
1231 if (idx == PCI_ROM_RESOURCE )
1232 disabled = 1;
1233 if (r->flags & IORESOURCE_IO)
1234 disabled = !(command & PCI_COMMAND_IO);
1235 else
1236 disabled = !(command & PCI_COMMAND_MEMORY);
1237 if (pass == disabled)
1238 alloc_resource(dev, idx);
1239 }
1240 if (pass)
1241 continue;
1242 r = &dev->resource[PCI_ROM_RESOURCE];
1243 if (r->flags) {
1244 /* Turn the ROM off, leave the resource region,
1245 * but keep it unregistered.
1246 */
1247 u32 reg;
1248 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1249 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1250 pr_debug("PCI: Switching off ROM of %s\n",
1251 pci_name(dev));
1252 r->flags &= ~IORESOURCE_ROM_ENABLE;
1253 pci_write_config_dword(dev, dev->rom_base_reg,
1254 reg & ~PCI_ROM_ADDRESS_ENABLE);
1255 }
1256 }
1257 }
1258}
1259
1260static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1261{
1262 struct pci_controller *hose = pci_bus_to_host(bus);
1263 resource_size_t offset;
1264 struct resource *res, *pres;
1265 int i;
1266
1267 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1268
1269 /* Check for IO */
1270 if (!(hose->io_resource.flags & IORESOURCE_IO))
1271 goto no_io;
1272 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1273 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1274 BUG_ON(res == NULL);
1275 res->name = "Legacy IO";
1276 res->flags = IORESOURCE_IO;
1277 res->start = offset;
1278 res->end = (offset + 0xfff) & 0xfffffffful;
1279 pr_debug("Candidate legacy IO: %pR\n", res);
1280 if (request_resource(&hose->io_resource, res)) {
1281 printk(KERN_DEBUG
1282 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1283 pci_domain_nr(bus), bus->number, res);
1284 kfree(res);
1285 }
1286
1287 no_io:
1288 /* Check for memory */
1289 for (i = 0; i < 3; i++) {
1290 pres = &hose->mem_resources[i];
1291 offset = hose->mem_offset[i];
1292 if (!(pres->flags & IORESOURCE_MEM))
1293 continue;
1294 pr_debug("hose mem res: %pR\n", pres);
1295 if ((pres->start - offset) <= 0xa0000 &&
1296 (pres->end - offset) >= 0xbffff)
1297 break;
1298 }
1299 if (i >= 3)
1300 return;
1301 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1302 BUG_ON(res == NULL);
1303 res->name = "Legacy VGA memory";
1304 res->flags = IORESOURCE_MEM;
1305 res->start = 0xa0000 + offset;
1306 res->end = 0xbffff + offset;
1307 pr_debug("Candidate VGA memory: %pR\n", res);
1308 if (request_resource(pres, res)) {
1309 printk(KERN_DEBUG
1310 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1311 pci_domain_nr(bus), bus->number, res);
1312 kfree(res);
1313 }
1314}
1315
1316void __init pcibios_resource_survey(void)
1317{
1318 struct pci_bus *b;
1319
1320 /* Allocate and assign resources */
1321 list_for_each_entry(b, &pci_root_buses, node)
1322 pcibios_allocate_bus_resources(b);
1323 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1324 pcibios_allocate_resources(0);
1325 pcibios_allocate_resources(1);
1326 }
1327
1328 /* Before we start assigning unassigned resource, we try to reserve
1329 * the low IO area and the VGA memory area if they intersect the
1330 * bus available resources to avoid allocating things on top of them
1331 */
1332 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1333 list_for_each_entry(b, &pci_root_buses, node)
1334 pcibios_reserve_legacy_regions(b);
1335 }
1336
1337 /* Now, if the platform didn't decide to blindly trust the firmware,
1338 * we proceed to assigning things that were left unassigned
1339 */
1340 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1341 pr_debug("PCI: Assigning unassigned resources...\n");
1342 pci_assign_unassigned_resources();
1343 }
1344}
1345
1346/* This is used by the PCI hotplug driver to allocate resource
1347 * of newly plugged busses. We can try to consolidate with the
1348 * rest of the code later, for now, keep it as-is as our main
1349 * resource allocation function doesn't deal with sub-trees yet.
1350 */
1351void pcibios_claim_one_bus(struct pci_bus *bus)
1352{
1353 struct pci_dev *dev;
1354 struct pci_bus *child_bus;
1355
1356 list_for_each_entry(dev, &bus->devices, bus_list) {
1357 int i;
1358
1359 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1360 struct resource *r = &dev->resource[i];
1361
1362 if (r->parent || !r->start || !r->flags)
1363 continue;
1364
1365 pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1366 pci_name(dev), i, r);
1367
1368 if (pci_claim_resource(dev, i) == 0)
1369 continue;
1370
1371 pci_claim_bridge_resource(dev, i);
1372 }
1373 }
1374
1375 list_for_each_entry(child_bus, &bus->children, node)
1376 pcibios_claim_one_bus(child_bus);
1377}
1378EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1379
1380
1381/* pcibios_finish_adding_to_bus
1382 *
1383 * This is to be called by the hotplug code after devices have been
1384 * added to a bus, this include calling it for a PHB that is just
1385 * being added
1386 */
1387void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1388{
1389 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1390 pci_domain_nr(bus), bus->number);
1391
1392 /* Allocate bus and devices resources */
1393 pcibios_allocate_bus_resources(bus);
1394 pcibios_claim_one_bus(bus);
1395 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1396 if (bus->self)
1397 pci_assign_unassigned_bridge_resources(bus->self);
1398 else
1399 pci_assign_unassigned_bus_resources(bus);
1400 }
1401
1402 /* Add new devices to global lists. Register in proc, sysfs. */
1403 pci_bus_add_devices(bus);
1404}
1405EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1406
1407int pcibios_enable_device(struct pci_dev *dev, int mask)
1408{
1409 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1410
1411 if (phb->controller_ops.enable_device_hook)
1412 if (!phb->controller_ops.enable_device_hook(dev))
1413 return -EINVAL;
1414
1415 return pci_enable_resources(dev, mask);
1416}
1417
1418void pcibios_disable_device(struct pci_dev *dev)
1419{
1420 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1421
1422 if (phb->controller_ops.disable_device)
1423 phb->controller_ops.disable_device(dev);
1424}
1425
1426resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1427{
1428 return (unsigned long) hose->io_base_virt - _IO_BASE;
1429}
1430
1431static void pcibios_setup_phb_resources(struct pci_controller *hose,
1432 struct list_head *resources)
1433{
1434 struct resource *res;
1435 resource_size_t offset;
1436 int i;
1437
1438 /* Hookup PHB IO resource */
1439 res = &hose->io_resource;
1440
1441 if (!res->flags) {
1442 pr_debug("PCI: I/O resource not set for host"
1443 " bridge %pOF (domain %d)\n",
1444 hose->dn, hose->global_number);
1445 } else {
1446 offset = pcibios_io_space_offset(hose);
1447
1448 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
1449 res, (unsigned long long)offset);
1450 pci_add_resource_offset(resources, res, offset);
1451 }
1452
1453 /* Hookup PHB Memory resources */
1454 for (i = 0; i < 3; ++i) {
1455 res = &hose->mem_resources[i];
1456 if (!res->flags)
1457 continue;
1458
1459 offset = hose->mem_offset[i];
1460 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1461 res, (unsigned long long)offset);
1462
1463 pci_add_resource_offset(resources, res, offset);
1464 }
1465}
1466
1467/*
1468 * Null PCI config access functions, for the case when we can't
1469 * find a hose.
1470 */
1471#define NULL_PCI_OP(rw, size, type) \
1472static int \
1473null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1474{ \
1475 return PCIBIOS_DEVICE_NOT_FOUND; \
1476}
1477
1478static int
1479null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1480 int len, u32 *val)
1481{
1482 return PCIBIOS_DEVICE_NOT_FOUND;
1483}
1484
1485static int
1486null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1487 int len, u32 val)
1488{
1489 return PCIBIOS_DEVICE_NOT_FOUND;
1490}
1491
1492static struct pci_ops null_pci_ops =
1493{
1494 .read = null_read_config,
1495 .write = null_write_config,
1496};
1497
1498/*
1499 * These functions are used early on before PCI scanning is done
1500 * and all of the pci_dev and pci_bus structures have been created.
1501 */
1502static struct pci_bus *
1503fake_pci_bus(struct pci_controller *hose, int busnr)
1504{
1505 static struct pci_bus bus;
1506
1507 if (hose == NULL) {
1508 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1509 }
1510 bus.number = busnr;
1511 bus.sysdata = hose;
1512 bus.ops = hose? hose->ops: &null_pci_ops;
1513 return &bus;
1514}
1515
1516#define EARLY_PCI_OP(rw, size, type) \
1517int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1518 int devfn, int offset, type value) \
1519{ \
1520 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1521 devfn, offset, value); \
1522}
1523
1524EARLY_PCI_OP(read, byte, u8 *)
1525EARLY_PCI_OP(read, word, u16 *)
1526EARLY_PCI_OP(read, dword, u32 *)
1527EARLY_PCI_OP(write, byte, u8)
1528EARLY_PCI_OP(write, word, u16)
1529EARLY_PCI_OP(write, dword, u32)
1530
1531int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1532 int cap)
1533{
1534 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1535}
1536
1537struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1538{
1539 struct pci_controller *hose = bus->sysdata;
1540
1541 return of_node_get(hose->dn);
1542}
1543
1544/**
1545 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1546 * @hose: Pointer to the PCI host controller instance structure
1547 */
1548void pcibios_scan_phb(struct pci_controller *hose)
1549{
1550 LIST_HEAD(resources);
1551 struct pci_bus *bus;
1552 struct device_node *node = hose->dn;
1553 int mode;
1554
1555 pr_debug("PCI: Scanning PHB %pOF\n", node);
1556
1557 /* Get some IO space for the new PHB */
1558 pcibios_setup_phb_io_space(hose);
1559
1560 /* Wire up PHB bus resources */
1561 pcibios_setup_phb_resources(hose, &resources);
1562
1563 hose->busn.start = hose->first_busno;
1564 hose->busn.end = hose->last_busno;
1565 hose->busn.flags = IORESOURCE_BUS;
1566 pci_add_resource(&resources, &hose->busn);
1567
1568 /* Create an empty bus for the toplevel */
1569 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1570 hose->ops, hose, &resources);
1571 if (bus == NULL) {
1572 pr_err("Failed to create bus for PCI domain %04x\n",
1573 hose->global_number);
1574 pci_free_resource_list(&resources);
1575 return;
1576 }
1577 hose->bus = bus;
1578
1579 /* Get probe mode and perform scan */
1580 mode = PCI_PROBE_NORMAL;
1581 if (node && hose->controller_ops.probe_mode)
1582 mode = hose->controller_ops.probe_mode(bus);
1583 pr_debug(" probe mode: %d\n", mode);
1584 if (mode == PCI_PROBE_DEVTREE)
1585 of_scan_bus(node, bus);
1586
1587 if (mode == PCI_PROBE_NORMAL) {
1588 pci_bus_update_busn_res_end(bus, 255);
1589 hose->last_busno = pci_scan_child_bus(bus);
1590 pci_bus_update_busn_res_end(bus, hose->last_busno);
1591 }
1592
1593 /* Platform gets a chance to do some global fixups before
1594 * we proceed to resource allocation
1595 */
1596 if (ppc_md.pcibios_fixup_phb)
1597 ppc_md.pcibios_fixup_phb(hose);
1598
1599 /* Configure PCI Express settings */
1600 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1601 struct pci_bus *child;
1602 list_for_each_entry(child, &bus->children, node)
1603 pcie_bus_configure_settings(child);
1604 }
1605}
1606EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1607
1608static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1609{
1610 int i, class = dev->class >> 8;
1611 /* When configured as agent, programing interface = 1 */
1612 int prog_if = dev->class & 0xf;
1613
1614 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1615 class == PCI_CLASS_BRIDGE_OTHER) &&
1616 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1617 (prog_if == 0) &&
1618 (dev->bus->parent == NULL)) {
1619 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1620 dev->resource[i].start = 0;
1621 dev->resource[i].end = 0;
1622 dev->resource[i].flags = 0;
1623 }
1624 }
1625}
1626DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1627DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1/*
2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
4 *
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
7 *
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
10 *
11 * Common pmac/prep/chrp pci routines. -- Cort
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/string.h>
22#include <linux/init.h>
23#include <linux/delay.h>
24#include <linux/export.h>
25#include <linux/of_address.h>
26#include <linux/of_pci.h>
27#include <linux/mm.h>
28#include <linux/list.h>
29#include <linux/syscalls.h>
30#include <linux/irq.h>
31#include <linux/vmalloc.h>
32#include <linux/slab.h>
33#include <linux/vgaarb.h>
34
35#include <asm/processor.h>
36#include <asm/io.h>
37#include <asm/prom.h>
38#include <asm/pci-bridge.h>
39#include <asm/byteorder.h>
40#include <asm/machdep.h>
41#include <asm/ppc-pci.h>
42#include <asm/eeh.h>
43
44static DEFINE_SPINLOCK(hose_spinlock);
45LIST_HEAD(hose_list);
46
47/* XXX kill that some day ... */
48static int global_phb_number; /* Global phb counter */
49
50/* ISA Memory physical address */
51resource_size_t isa_mem_base;
52
53
54static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
55
56void set_pci_dma_ops(struct dma_map_ops *dma_ops)
57{
58 pci_dma_ops = dma_ops;
59}
60
61struct dma_map_ops *get_pci_dma_ops(void)
62{
63 return pci_dma_ops;
64}
65EXPORT_SYMBOL(get_pci_dma_ops);
66
67struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
68{
69 struct pci_controller *phb;
70
71 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
72 if (phb == NULL)
73 return NULL;
74 spin_lock(&hose_spinlock);
75 phb->global_number = global_phb_number++;
76 list_add_tail(&phb->list_node, &hose_list);
77 spin_unlock(&hose_spinlock);
78 phb->dn = dev;
79 phb->is_dynamic = slab_is_available();
80#ifdef CONFIG_PPC64
81 if (dev) {
82 int nid = of_node_to_nid(dev);
83
84 if (nid < 0 || !node_online(nid))
85 nid = -1;
86
87 PHB_SET_NODE(phb, nid);
88 }
89#endif
90 return phb;
91}
92EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
93
94void pcibios_free_controller(struct pci_controller *phb)
95{
96 spin_lock(&hose_spinlock);
97 list_del(&phb->list_node);
98 spin_unlock(&hose_spinlock);
99
100 if (phb->is_dynamic)
101 kfree(phb);
102}
103EXPORT_SYMBOL_GPL(pcibios_free_controller);
104
105/*
106 * The function is used to return the minimal alignment
107 * for memory or I/O windows of the associated P2P bridge.
108 * By default, 4KiB alignment for I/O windows and 1MiB for
109 * memory windows.
110 */
111resource_size_t pcibios_window_alignment(struct pci_bus *bus,
112 unsigned long type)
113{
114 struct pci_controller *phb = pci_bus_to_host(bus);
115
116 if (phb->controller_ops.window_alignment)
117 return phb->controller_ops.window_alignment(bus, type);
118
119 /*
120 * PCI core will figure out the default
121 * alignment: 4KiB for I/O and 1MiB for
122 * memory window.
123 */
124 return 1;
125}
126
127void pcibios_reset_secondary_bus(struct pci_dev *dev)
128{
129 struct pci_controller *phb = pci_bus_to_host(dev->bus);
130
131 if (phb->controller_ops.reset_secondary_bus) {
132 phb->controller_ops.reset_secondary_bus(dev);
133 return;
134 }
135
136 pci_reset_secondary_bus(dev);
137}
138
139#ifdef CONFIG_PCI_IOV
140resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
141{
142 if (ppc_md.pcibios_iov_resource_alignment)
143 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
144
145 return pci_iov_resource_size(pdev, resno);
146}
147#endif /* CONFIG_PCI_IOV */
148
149static resource_size_t pcibios_io_size(const struct pci_controller *hose)
150{
151#ifdef CONFIG_PPC64
152 return hose->pci_io_size;
153#else
154 return resource_size(&hose->io_resource);
155#endif
156}
157
158int pcibios_vaddr_is_ioport(void __iomem *address)
159{
160 int ret = 0;
161 struct pci_controller *hose;
162 resource_size_t size;
163
164 spin_lock(&hose_spinlock);
165 list_for_each_entry(hose, &hose_list, list_node) {
166 size = pcibios_io_size(hose);
167 if (address >= hose->io_base_virt &&
168 address < (hose->io_base_virt + size)) {
169 ret = 1;
170 break;
171 }
172 }
173 spin_unlock(&hose_spinlock);
174 return ret;
175}
176
177unsigned long pci_address_to_pio(phys_addr_t address)
178{
179 struct pci_controller *hose;
180 resource_size_t size;
181 unsigned long ret = ~0;
182
183 spin_lock(&hose_spinlock);
184 list_for_each_entry(hose, &hose_list, list_node) {
185 size = pcibios_io_size(hose);
186 if (address >= hose->io_base_phys &&
187 address < (hose->io_base_phys + size)) {
188 unsigned long base =
189 (unsigned long)hose->io_base_virt - _IO_BASE;
190 ret = base + (address - hose->io_base_phys);
191 break;
192 }
193 }
194 spin_unlock(&hose_spinlock);
195
196 return ret;
197}
198EXPORT_SYMBOL_GPL(pci_address_to_pio);
199
200/*
201 * Return the domain number for this bus.
202 */
203int pci_domain_nr(struct pci_bus *bus)
204{
205 struct pci_controller *hose = pci_bus_to_host(bus);
206
207 return hose->global_number;
208}
209EXPORT_SYMBOL(pci_domain_nr);
210
211/* This routine is meant to be used early during boot, when the
212 * PCI bus numbers have not yet been assigned, and you need to
213 * issue PCI config cycles to an OF device.
214 * It could also be used to "fix" RTAS config cycles if you want
215 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
216 * config cycles.
217 */
218struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
219{
220 while(node) {
221 struct pci_controller *hose, *tmp;
222 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
223 if (hose->dn == node)
224 return hose;
225 node = node->parent;
226 }
227 return NULL;
228}
229
230/*
231 * Reads the interrupt pin to determine if interrupt is use by card.
232 * If the interrupt is used, then gets the interrupt line from the
233 * openfirmware and sets it in the pci_dev and pci_config line.
234 */
235static int pci_read_irq_line(struct pci_dev *pci_dev)
236{
237 struct of_phandle_args oirq;
238 unsigned int virq;
239
240 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
241
242#ifdef DEBUG
243 memset(&oirq, 0xff, sizeof(oirq));
244#endif
245 /* Try to get a mapping from the device-tree */
246 if (of_irq_parse_pci(pci_dev, &oirq)) {
247 u8 line, pin;
248
249 /* If that fails, lets fallback to what is in the config
250 * space and map that through the default controller. We
251 * also set the type to level low since that's what PCI
252 * interrupts are. If your platform does differently, then
253 * either provide a proper interrupt tree or don't use this
254 * function.
255 */
256 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
257 return -1;
258 if (pin == 0)
259 return -1;
260 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
261 line == 0xff || line == 0) {
262 return -1;
263 }
264 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
265 line, pin);
266
267 virq = irq_create_mapping(NULL, line);
268 if (virq != NO_IRQ)
269 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
270 } else {
271 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
272 oirq.args_count, oirq.args[0], oirq.args[1],
273 of_node_full_name(oirq.np));
274
275 virq = irq_create_of_mapping(&oirq);
276 }
277 if(virq == NO_IRQ) {
278 pr_debug(" Failed to map !\n");
279 return -1;
280 }
281
282 pr_debug(" Mapped to linux irq %d\n", virq);
283
284 pci_dev->irq = virq;
285
286 return 0;
287}
288
289/*
290 * Platform support for /proc/bus/pci/X/Y mmap()s,
291 * modelled on the sparc64 implementation by Dave Miller.
292 * -- paulus.
293 */
294
295/*
296 * Adjust vm_pgoff of VMA such that it is the physical page offset
297 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
298 *
299 * Basically, the user finds the base address for his device which he wishes
300 * to mmap. They read the 32-bit value from the config space base register,
301 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
302 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
303 *
304 * Returns negative error code on failure, zero on success.
305 */
306static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
307 resource_size_t *offset,
308 enum pci_mmap_state mmap_state)
309{
310 struct pci_controller *hose = pci_bus_to_host(dev->bus);
311 unsigned long io_offset = 0;
312 int i, res_bit;
313
314 if (hose == NULL)
315 return NULL; /* should never happen */
316
317 /* If memory, add on the PCI bridge address offset */
318 if (mmap_state == pci_mmap_mem) {
319#if 0 /* See comment in pci_resource_to_user() for why this is disabled */
320 *offset += hose->pci_mem_offset;
321#endif
322 res_bit = IORESOURCE_MEM;
323 } else {
324 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
325 *offset += io_offset;
326 res_bit = IORESOURCE_IO;
327 }
328
329 /*
330 * Check that the offset requested corresponds to one of the
331 * resources of the device.
332 */
333 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
334 struct resource *rp = &dev->resource[i];
335 int flags = rp->flags;
336
337 /* treat ROM as memory (should be already) */
338 if (i == PCI_ROM_RESOURCE)
339 flags |= IORESOURCE_MEM;
340
341 /* Active and same type? */
342 if ((flags & res_bit) == 0)
343 continue;
344
345 /* In the range of this resource? */
346 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
347 continue;
348
349 /* found it! construct the final physical address */
350 if (mmap_state == pci_mmap_io)
351 *offset += hose->io_base_phys - io_offset;
352 return rp;
353 }
354
355 return NULL;
356}
357
358/*
359 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
360 * device mapping.
361 */
362static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
363 pgprot_t protection,
364 enum pci_mmap_state mmap_state,
365 int write_combine)
366{
367
368 /* Write combine is always 0 on non-memory space mappings. On
369 * memory space, if the user didn't pass 1, we check for a
370 * "prefetchable" resource. This is a bit hackish, but we use
371 * this to workaround the inability of /sysfs to provide a write
372 * combine bit
373 */
374 if (mmap_state != pci_mmap_mem)
375 write_combine = 0;
376 else if (write_combine == 0) {
377 if (rp->flags & IORESOURCE_PREFETCH)
378 write_combine = 1;
379 }
380
381 /* XXX would be nice to have a way to ask for write-through */
382 if (write_combine)
383 return pgprot_noncached_wc(protection);
384 else
385 return pgprot_noncached(protection);
386}
387
388/*
389 * This one is used by /dev/mem and fbdev who have no clue about the
390 * PCI device, it tries to find the PCI device first and calls the
391 * above routine
392 */
393pgprot_t pci_phys_mem_access_prot(struct file *file,
394 unsigned long pfn,
395 unsigned long size,
396 pgprot_t prot)
397{
398 struct pci_dev *pdev = NULL;
399 struct resource *found = NULL;
400 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
401 int i;
402
403 if (page_is_ram(pfn))
404 return prot;
405
406 prot = pgprot_noncached(prot);
407 for_each_pci_dev(pdev) {
408 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
409 struct resource *rp = &pdev->resource[i];
410 int flags = rp->flags;
411
412 /* Active and same type? */
413 if ((flags & IORESOURCE_MEM) == 0)
414 continue;
415 /* In the range of this resource? */
416 if (offset < (rp->start & PAGE_MASK) ||
417 offset > rp->end)
418 continue;
419 found = rp;
420 break;
421 }
422 if (found)
423 break;
424 }
425 if (found) {
426 if (found->flags & IORESOURCE_PREFETCH)
427 prot = pgprot_noncached_wc(prot);
428 pci_dev_put(pdev);
429 }
430
431 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
432 (unsigned long long)offset, pgprot_val(prot));
433
434 return prot;
435}
436
437
438/*
439 * Perform the actual remap of the pages for a PCI device mapping, as
440 * appropriate for this architecture. The region in the process to map
441 * is described by vm_start and vm_end members of VMA, the base physical
442 * address is found in vm_pgoff.
443 * The pci device structure is provided so that architectures may make mapping
444 * decisions on a per-device or per-bus basis.
445 *
446 * Returns a negative error code on failure, zero on success.
447 */
448int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
449 enum pci_mmap_state mmap_state, int write_combine)
450{
451 resource_size_t offset =
452 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
453 struct resource *rp;
454 int ret;
455
456 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
457 if (rp == NULL)
458 return -EINVAL;
459
460 vma->vm_pgoff = offset >> PAGE_SHIFT;
461 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
462 vma->vm_page_prot,
463 mmap_state, write_combine);
464
465 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
466 vma->vm_end - vma->vm_start, vma->vm_page_prot);
467
468 return ret;
469}
470
471/* This provides legacy IO read access on a bus */
472int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
473{
474 unsigned long offset;
475 struct pci_controller *hose = pci_bus_to_host(bus);
476 struct resource *rp = &hose->io_resource;
477 void __iomem *addr;
478
479 /* Check if port can be supported by that bus. We only check
480 * the ranges of the PHB though, not the bus itself as the rules
481 * for forwarding legacy cycles down bridges are not our problem
482 * here. So if the host bridge supports it, we do it.
483 */
484 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
485 offset += port;
486
487 if (!(rp->flags & IORESOURCE_IO))
488 return -ENXIO;
489 if (offset < rp->start || (offset + size) > rp->end)
490 return -ENXIO;
491 addr = hose->io_base_virt + port;
492
493 switch(size) {
494 case 1:
495 *((u8 *)val) = in_8(addr);
496 return 1;
497 case 2:
498 if (port & 1)
499 return -EINVAL;
500 *((u16 *)val) = in_le16(addr);
501 return 2;
502 case 4:
503 if (port & 3)
504 return -EINVAL;
505 *((u32 *)val) = in_le32(addr);
506 return 4;
507 }
508 return -EINVAL;
509}
510
511/* This provides legacy IO write access on a bus */
512int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
513{
514 unsigned long offset;
515 struct pci_controller *hose = pci_bus_to_host(bus);
516 struct resource *rp = &hose->io_resource;
517 void __iomem *addr;
518
519 /* Check if port can be supported by that bus. We only check
520 * the ranges of the PHB though, not the bus itself as the rules
521 * for forwarding legacy cycles down bridges are not our problem
522 * here. So if the host bridge supports it, we do it.
523 */
524 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
525 offset += port;
526
527 if (!(rp->flags & IORESOURCE_IO))
528 return -ENXIO;
529 if (offset < rp->start || (offset + size) > rp->end)
530 return -ENXIO;
531 addr = hose->io_base_virt + port;
532
533 /* WARNING: The generic code is idiotic. It gets passed a pointer
534 * to what can be a 1, 2 or 4 byte quantity and always reads that
535 * as a u32, which means that we have to correct the location of
536 * the data read within those 32 bits for size 1 and 2
537 */
538 switch(size) {
539 case 1:
540 out_8(addr, val >> 24);
541 return 1;
542 case 2:
543 if (port & 1)
544 return -EINVAL;
545 out_le16(addr, val >> 16);
546 return 2;
547 case 4:
548 if (port & 3)
549 return -EINVAL;
550 out_le32(addr, val);
551 return 4;
552 }
553 return -EINVAL;
554}
555
556/* This provides legacy IO or memory mmap access on a bus */
557int pci_mmap_legacy_page_range(struct pci_bus *bus,
558 struct vm_area_struct *vma,
559 enum pci_mmap_state mmap_state)
560{
561 struct pci_controller *hose = pci_bus_to_host(bus);
562 resource_size_t offset =
563 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
564 resource_size_t size = vma->vm_end - vma->vm_start;
565 struct resource *rp;
566
567 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
568 pci_domain_nr(bus), bus->number,
569 mmap_state == pci_mmap_mem ? "MEM" : "IO",
570 (unsigned long long)offset,
571 (unsigned long long)(offset + size - 1));
572
573 if (mmap_state == pci_mmap_mem) {
574 /* Hack alert !
575 *
576 * Because X is lame and can fail starting if it gets an error trying
577 * to mmap legacy_mem (instead of just moving on without legacy memory
578 * access) we fake it here by giving it anonymous memory, effectively
579 * behaving just like /dev/zero
580 */
581 if ((offset + size) > hose->isa_mem_size) {
582 printk(KERN_DEBUG
583 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
584 current->comm, current->pid, pci_domain_nr(bus), bus->number);
585 if (vma->vm_flags & VM_SHARED)
586 return shmem_zero_setup(vma);
587 return 0;
588 }
589 offset += hose->isa_mem_phys;
590 } else {
591 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
592 unsigned long roffset = offset + io_offset;
593 rp = &hose->io_resource;
594 if (!(rp->flags & IORESOURCE_IO))
595 return -ENXIO;
596 if (roffset < rp->start || (roffset + size) > rp->end)
597 return -ENXIO;
598 offset += hose->io_base_phys;
599 }
600 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
601
602 vma->vm_pgoff = offset >> PAGE_SHIFT;
603 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
604 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
605 vma->vm_end - vma->vm_start,
606 vma->vm_page_prot);
607}
608
609void pci_resource_to_user(const struct pci_dev *dev, int bar,
610 const struct resource *rsrc,
611 resource_size_t *start, resource_size_t *end)
612{
613 struct pci_controller *hose = pci_bus_to_host(dev->bus);
614 resource_size_t offset = 0;
615
616 if (hose == NULL)
617 return;
618
619 if (rsrc->flags & IORESOURCE_IO)
620 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
621
622 /* We pass a fully fixed up address to userland for MMIO instead of
623 * a BAR value because X is lame and expects to be able to use that
624 * to pass to /dev/mem !
625 *
626 * That means that we'll have potentially 64 bits values where some
627 * userland apps only expect 32 (like X itself since it thinks only
628 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
629 * 32 bits CHRPs :-(
630 *
631 * Hopefully, the sysfs insterface is immune to that gunk. Once X
632 * has been fixed (and the fix spread enough), we can re-enable the
633 * 2 lines below and pass down a BAR value to userland. In that case
634 * we'll also have to re-enable the matching code in
635 * __pci_mmap_make_offset().
636 *
637 * BenH.
638 */
639#if 0
640 else if (rsrc->flags & IORESOURCE_MEM)
641 offset = hose->pci_mem_offset;
642#endif
643
644 *start = rsrc->start - offset;
645 *end = rsrc->end - offset;
646}
647
648/**
649 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
650 * @hose: newly allocated pci_controller to be setup
651 * @dev: device node of the host bridge
652 * @primary: set if primary bus (32 bits only, soon to be deprecated)
653 *
654 * This function will parse the "ranges" property of a PCI host bridge device
655 * node and setup the resource mapping of a pci controller based on its
656 * content.
657 *
658 * Life would be boring if it wasn't for a few issues that we have to deal
659 * with here:
660 *
661 * - We can only cope with one IO space range and up to 3 Memory space
662 * ranges. However, some machines (thanks Apple !) tend to split their
663 * space into lots of small contiguous ranges. So we have to coalesce.
664 *
665 * - Some busses have IO space not starting at 0, which causes trouble with
666 * the way we do our IO resource renumbering. The code somewhat deals with
667 * it for 64 bits but I would expect problems on 32 bits.
668 *
669 * - Some 32 bits platforms such as 4xx can have physical space larger than
670 * 32 bits so we need to use 64 bits values for the parsing
671 */
672void pci_process_bridge_OF_ranges(struct pci_controller *hose,
673 struct device_node *dev, int primary)
674{
675 int memno = 0;
676 struct resource *res;
677 struct of_pci_range range;
678 struct of_pci_range_parser parser;
679
680 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
681 dev->full_name, primary ? "(primary)" : "");
682
683 /* Check for ranges property */
684 if (of_pci_range_parser_init(&parser, dev))
685 return;
686
687 /* Parse it */
688 for_each_of_pci_range(&parser, &range) {
689 /* If we failed translation or got a zero-sized region
690 * (some FW try to feed us with non sensical zero sized regions
691 * such as power3 which look like some kind of attempt at exposing
692 * the VGA memory hole)
693 */
694 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
695 continue;
696
697 /* Act based on address space type */
698 res = NULL;
699 switch (range.flags & IORESOURCE_TYPE_BITS) {
700 case IORESOURCE_IO:
701 printk(KERN_INFO
702 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
703 range.cpu_addr, range.cpu_addr + range.size - 1,
704 range.pci_addr);
705
706 /* We support only one IO range */
707 if (hose->pci_io_size) {
708 printk(KERN_INFO
709 " \\--> Skipped (too many) !\n");
710 continue;
711 }
712#ifdef CONFIG_PPC32
713 /* On 32 bits, limit I/O space to 16MB */
714 if (range.size > 0x01000000)
715 range.size = 0x01000000;
716
717 /* 32 bits needs to map IOs here */
718 hose->io_base_virt = ioremap(range.cpu_addr,
719 range.size);
720
721 /* Expect trouble if pci_addr is not 0 */
722 if (primary)
723 isa_io_base =
724 (unsigned long)hose->io_base_virt;
725#endif /* CONFIG_PPC32 */
726 /* pci_io_size and io_base_phys always represent IO
727 * space starting at 0 so we factor in pci_addr
728 */
729 hose->pci_io_size = range.pci_addr + range.size;
730 hose->io_base_phys = range.cpu_addr - range.pci_addr;
731
732 /* Build resource */
733 res = &hose->io_resource;
734 range.cpu_addr = range.pci_addr;
735 break;
736 case IORESOURCE_MEM:
737 printk(KERN_INFO
738 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
739 range.cpu_addr, range.cpu_addr + range.size - 1,
740 range.pci_addr,
741 (range.pci_space & 0x40000000) ?
742 "Prefetch" : "");
743
744 /* We support only 3 memory ranges */
745 if (memno >= 3) {
746 printk(KERN_INFO
747 " \\--> Skipped (too many) !\n");
748 continue;
749 }
750 /* Handles ISA memory hole space here */
751 if (range.pci_addr == 0) {
752 if (primary || isa_mem_base == 0)
753 isa_mem_base = range.cpu_addr;
754 hose->isa_mem_phys = range.cpu_addr;
755 hose->isa_mem_size = range.size;
756 }
757
758 /* Build resource */
759 hose->mem_offset[memno] = range.cpu_addr -
760 range.pci_addr;
761 res = &hose->mem_resources[memno++];
762 break;
763 }
764 if (res != NULL) {
765 res->name = dev->full_name;
766 res->flags = range.flags;
767 res->start = range.cpu_addr;
768 res->end = range.cpu_addr + range.size - 1;
769 res->parent = res->child = res->sibling = NULL;
770 }
771 }
772}
773
774/* Decide whether to display the domain number in /proc */
775int pci_proc_domain(struct pci_bus *bus)
776{
777 struct pci_controller *hose = pci_bus_to_host(bus);
778
779 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
780 return 0;
781 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
782 return hose->global_number != 0;
783 return 1;
784}
785
786int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
787{
788 if (ppc_md.pcibios_root_bridge_prepare)
789 return ppc_md.pcibios_root_bridge_prepare(bridge);
790
791 return 0;
792}
793
794/* This header fixup will do the resource fixup for all devices as they are
795 * probed, but not for bridge ranges
796 */
797static void pcibios_fixup_resources(struct pci_dev *dev)
798{
799 struct pci_controller *hose = pci_bus_to_host(dev->bus);
800 int i;
801
802 if (!hose) {
803 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
804 pci_name(dev));
805 return;
806 }
807
808 if (dev->is_virtfn)
809 return;
810
811 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
812 struct resource *res = dev->resource + i;
813 struct pci_bus_region reg;
814 if (!res->flags)
815 continue;
816
817 /* If we're going to re-assign everything, we mark all resources
818 * as unset (and 0-base them). In addition, we mark BARs starting
819 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
820 * since in that case, we don't want to re-assign anything
821 */
822 pcibios_resource_to_bus(dev->bus, ®, res);
823 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
824 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
825 /* Only print message if not re-assigning */
826 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
827 pr_debug("PCI:%s Resource %d %pR is unassigned\n",
828 pci_name(dev), i, res);
829 res->end -= res->start;
830 res->start = 0;
831 res->flags |= IORESOURCE_UNSET;
832 continue;
833 }
834
835 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
836 }
837
838 /* Call machine specific resource fixup */
839 if (ppc_md.pcibios_fixup_resources)
840 ppc_md.pcibios_fixup_resources(dev);
841}
842DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
843
844/* This function tries to figure out if a bridge resource has been initialized
845 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
846 * things go more smoothly when it gets it right. It should covers cases such
847 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
848 */
849static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
850 struct resource *res)
851{
852 struct pci_controller *hose = pci_bus_to_host(bus);
853 struct pci_dev *dev = bus->self;
854 resource_size_t offset;
855 struct pci_bus_region region;
856 u16 command;
857 int i;
858
859 /* We don't do anything if PCI_PROBE_ONLY is set */
860 if (pci_has_flag(PCI_PROBE_ONLY))
861 return 0;
862
863 /* Job is a bit different between memory and IO */
864 if (res->flags & IORESOURCE_MEM) {
865 pcibios_resource_to_bus(dev->bus, ®ion, res);
866
867 /* If the BAR is non-0 then it's probably been initialized */
868 if (region.start != 0)
869 return 0;
870
871 /* The BAR is 0, let's check if memory decoding is enabled on
872 * the bridge. If not, we consider it unassigned
873 */
874 pci_read_config_word(dev, PCI_COMMAND, &command);
875 if ((command & PCI_COMMAND_MEMORY) == 0)
876 return 1;
877
878 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
879 * resources covers that starting address (0 then it's good enough for
880 * us for memory space)
881 */
882 for (i = 0; i < 3; i++) {
883 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
884 hose->mem_resources[i].start == hose->mem_offset[i])
885 return 0;
886 }
887
888 /* Well, it starts at 0 and we know it will collide so we may as
889 * well consider it as unassigned. That covers the Apple case.
890 */
891 return 1;
892 } else {
893 /* If the BAR is non-0, then we consider it assigned */
894 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
895 if (((res->start - offset) & 0xfffffffful) != 0)
896 return 0;
897
898 /* Here, we are a bit different than memory as typically IO space
899 * starting at low addresses -is- valid. What we do instead if that
900 * we consider as unassigned anything that doesn't have IO enabled
901 * in the PCI command register, and that's it.
902 */
903 pci_read_config_word(dev, PCI_COMMAND, &command);
904 if (command & PCI_COMMAND_IO)
905 return 0;
906
907 /* It's starting at 0 and IO is disabled in the bridge, consider
908 * it unassigned
909 */
910 return 1;
911 }
912}
913
914/* Fixup resources of a PCI<->PCI bridge */
915static void pcibios_fixup_bridge(struct pci_bus *bus)
916{
917 struct resource *res;
918 int i;
919
920 struct pci_dev *dev = bus->self;
921
922 pci_bus_for_each_resource(bus, res, i) {
923 if (!res || !res->flags)
924 continue;
925 if (i >= 3 && bus->self->transparent)
926 continue;
927
928 /* If we're going to reassign everything, we can
929 * shrink the P2P resource to have size as being
930 * of 0 in order to save space.
931 */
932 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
933 res->flags |= IORESOURCE_UNSET;
934 res->start = 0;
935 res->end = -1;
936 continue;
937 }
938
939 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
940
941 /* Try to detect uninitialized P2P bridge resources,
942 * and clear them out so they get re-assigned later
943 */
944 if (pcibios_uninitialized_bridge_resource(bus, res)) {
945 res->flags = 0;
946 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
947 }
948 }
949}
950
951void pcibios_setup_bus_self(struct pci_bus *bus)
952{
953 struct pci_controller *phb;
954
955 /* Fix up the bus resources for P2P bridges */
956 if (bus->self != NULL)
957 pcibios_fixup_bridge(bus);
958
959 /* Platform specific bus fixups. This is currently only used
960 * by fsl_pci and I'm hoping to get rid of it at some point
961 */
962 if (ppc_md.pcibios_fixup_bus)
963 ppc_md.pcibios_fixup_bus(bus);
964
965 /* Setup bus DMA mappings */
966 phb = pci_bus_to_host(bus);
967 if (phb->controller_ops.dma_bus_setup)
968 phb->controller_ops.dma_bus_setup(bus);
969}
970
971static void pcibios_setup_device(struct pci_dev *dev)
972{
973 struct pci_controller *phb;
974 /* Fixup NUMA node as it may not be setup yet by the generic
975 * code and is needed by the DMA init
976 */
977 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
978
979 /* Hook up default DMA ops */
980 set_dma_ops(&dev->dev, pci_dma_ops);
981 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
982
983 /* Additional platform DMA/iommu setup */
984 phb = pci_bus_to_host(dev->bus);
985 if (phb->controller_ops.dma_dev_setup)
986 phb->controller_ops.dma_dev_setup(dev);
987
988 /* Read default IRQs and fixup if necessary */
989 pci_read_irq_line(dev);
990 if (ppc_md.pci_irq_fixup)
991 ppc_md.pci_irq_fixup(dev);
992}
993
994int pcibios_add_device(struct pci_dev *dev)
995{
996 /*
997 * We can only call pcibios_setup_device() after bus setup is complete,
998 * since some of the platform specific DMA setup code depends on it.
999 */
1000 if (dev->bus->is_added)
1001 pcibios_setup_device(dev);
1002
1003#ifdef CONFIG_PCI_IOV
1004 if (ppc_md.pcibios_fixup_sriov)
1005 ppc_md.pcibios_fixup_sriov(dev);
1006#endif /* CONFIG_PCI_IOV */
1007
1008 return 0;
1009}
1010
1011void pcibios_setup_bus_devices(struct pci_bus *bus)
1012{
1013 struct pci_dev *dev;
1014
1015 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1016 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1017
1018 list_for_each_entry(dev, &bus->devices, bus_list) {
1019 /* Cardbus can call us to add new devices to a bus, so ignore
1020 * those who are already fully discovered
1021 */
1022 if (dev->is_added)
1023 continue;
1024
1025 pcibios_setup_device(dev);
1026 }
1027}
1028
1029void pcibios_set_master(struct pci_dev *dev)
1030{
1031 /* No special bus mastering setup handling */
1032}
1033
1034void pcibios_fixup_bus(struct pci_bus *bus)
1035{
1036 /* When called from the generic PCI probe, read PCI<->PCI bridge
1037 * bases. This is -not- called when generating the PCI tree from
1038 * the OF device-tree.
1039 */
1040 pci_read_bridge_bases(bus);
1041
1042 /* Now fixup the bus bus */
1043 pcibios_setup_bus_self(bus);
1044
1045 /* Now fixup devices on that bus */
1046 pcibios_setup_bus_devices(bus);
1047}
1048EXPORT_SYMBOL(pcibios_fixup_bus);
1049
1050void pci_fixup_cardbus(struct pci_bus *bus)
1051{
1052 /* Now fixup devices on that bus */
1053 pcibios_setup_bus_devices(bus);
1054}
1055
1056
1057static int skip_isa_ioresource_align(struct pci_dev *dev)
1058{
1059 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1060 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1061 return 1;
1062 return 0;
1063}
1064
1065/*
1066 * We need to avoid collisions with `mirrored' VGA ports
1067 * and other strange ISA hardware, so we always want the
1068 * addresses to be allocated in the 0x000-0x0ff region
1069 * modulo 0x400.
1070 *
1071 * Why? Because some silly external IO cards only decode
1072 * the low 10 bits of the IO address. The 0x00-0xff region
1073 * is reserved for motherboard devices that decode all 16
1074 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1075 * but we want to try to avoid allocating at 0x2900-0x2bff
1076 * which might have be mirrored at 0x0100-0x03ff..
1077 */
1078resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1079 resource_size_t size, resource_size_t align)
1080{
1081 struct pci_dev *dev = data;
1082 resource_size_t start = res->start;
1083
1084 if (res->flags & IORESOURCE_IO) {
1085 if (skip_isa_ioresource_align(dev))
1086 return start;
1087 if (start & 0x300)
1088 start = (start + 0x3ff) & ~0x3ff;
1089 }
1090
1091 return start;
1092}
1093EXPORT_SYMBOL(pcibios_align_resource);
1094
1095/*
1096 * Reparent resource children of pr that conflict with res
1097 * under res, and make res replace those children.
1098 */
1099static int reparent_resources(struct resource *parent,
1100 struct resource *res)
1101{
1102 struct resource *p, **pp;
1103 struct resource **firstpp = NULL;
1104
1105 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1106 if (p->end < res->start)
1107 continue;
1108 if (res->end < p->start)
1109 break;
1110 if (p->start < res->start || p->end > res->end)
1111 return -1; /* not completely contained */
1112 if (firstpp == NULL)
1113 firstpp = pp;
1114 }
1115 if (firstpp == NULL)
1116 return -1; /* didn't find any conflicting entries? */
1117 res->parent = parent;
1118 res->child = *firstpp;
1119 res->sibling = *pp;
1120 *firstpp = res;
1121 *pp = NULL;
1122 for (p = res->child; p != NULL; p = p->sibling) {
1123 p->parent = res;
1124 pr_debug("PCI: Reparented %s %pR under %s\n",
1125 p->name, p, res->name);
1126 }
1127 return 0;
1128}
1129
1130/*
1131 * Handle resources of PCI devices. If the world were perfect, we could
1132 * just allocate all the resource regions and do nothing more. It isn't.
1133 * On the other hand, we cannot just re-allocate all devices, as it would
1134 * require us to know lots of host bridge internals. So we attempt to
1135 * keep as much of the original configuration as possible, but tweak it
1136 * when it's found to be wrong.
1137 *
1138 * Known BIOS problems we have to work around:
1139 * - I/O or memory regions not configured
1140 * - regions configured, but not enabled in the command register
1141 * - bogus I/O addresses above 64K used
1142 * - expansion ROMs left enabled (this may sound harmless, but given
1143 * the fact the PCI specs explicitly allow address decoders to be
1144 * shared between expansion ROMs and other resource regions, it's
1145 * at least dangerous)
1146 *
1147 * Our solution:
1148 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1149 * This gives us fixed barriers on where we can allocate.
1150 * (2) Allocate resources for all enabled devices. If there is
1151 * a collision, just mark the resource as unallocated. Also
1152 * disable expansion ROMs during this step.
1153 * (3) Try to allocate resources for disabled devices. If the
1154 * resources were assigned correctly, everything goes well,
1155 * if they weren't, they won't disturb allocation of other
1156 * resources.
1157 * (4) Assign new addresses to resources which were either
1158 * not configured at all or misconfigured. If explicitly
1159 * requested by the user, configure expansion ROM address
1160 * as well.
1161 */
1162
1163static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1164{
1165 struct pci_bus *b;
1166 int i;
1167 struct resource *res, *pr;
1168
1169 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1170 pci_domain_nr(bus), bus->number);
1171
1172 pci_bus_for_each_resource(bus, res, i) {
1173 if (!res || !res->flags || res->start > res->end || res->parent)
1174 continue;
1175
1176 /* If the resource was left unset at this point, we clear it */
1177 if (res->flags & IORESOURCE_UNSET)
1178 goto clear_resource;
1179
1180 if (bus->parent == NULL)
1181 pr = (res->flags & IORESOURCE_IO) ?
1182 &ioport_resource : &iomem_resource;
1183 else {
1184 pr = pci_find_parent_resource(bus->self, res);
1185 if (pr == res) {
1186 /* this happens when the generic PCI
1187 * code (wrongly) decides that this
1188 * bridge is transparent -- paulus
1189 */
1190 continue;
1191 }
1192 }
1193
1194 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1195 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1196 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1197
1198 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1199 struct pci_dev *dev = bus->self;
1200
1201 if (request_resource(pr, res) == 0)
1202 continue;
1203 /*
1204 * Must be a conflict with an existing entry.
1205 * Move that entry (or entries) under the
1206 * bridge resource and try again.
1207 */
1208 if (reparent_resources(pr, res) == 0)
1209 continue;
1210
1211 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1212 pci_claim_bridge_resource(dev,
1213 i + PCI_BRIDGE_RESOURCES) == 0)
1214 continue;
1215 }
1216 pr_warning("PCI: Cannot allocate resource region "
1217 "%d of PCI bridge %d, will remap\n", i, bus->number);
1218 clear_resource:
1219 /* The resource might be figured out when doing
1220 * reassignment based on the resources required
1221 * by the downstream PCI devices. Here we set
1222 * the size of the resource to be 0 in order to
1223 * save more space.
1224 */
1225 res->start = 0;
1226 res->end = -1;
1227 res->flags = 0;
1228 }
1229
1230 list_for_each_entry(b, &bus->children, node)
1231 pcibios_allocate_bus_resources(b);
1232}
1233
1234static inline void alloc_resource(struct pci_dev *dev, int idx)
1235{
1236 struct resource *pr, *r = &dev->resource[idx];
1237
1238 pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1239 pci_name(dev), idx, r);
1240
1241 pr = pci_find_parent_resource(dev, r);
1242 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1243 request_resource(pr, r) < 0) {
1244 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1245 " of device %s, will remap\n", idx, pci_name(dev));
1246 if (pr)
1247 pr_debug("PCI: parent is %p: %pR\n", pr, pr);
1248 /* We'll assign a new address later */
1249 r->flags |= IORESOURCE_UNSET;
1250 r->end -= r->start;
1251 r->start = 0;
1252 }
1253}
1254
1255static void __init pcibios_allocate_resources(int pass)
1256{
1257 struct pci_dev *dev = NULL;
1258 int idx, disabled;
1259 u16 command;
1260 struct resource *r;
1261
1262 for_each_pci_dev(dev) {
1263 pci_read_config_word(dev, PCI_COMMAND, &command);
1264 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1265 r = &dev->resource[idx];
1266 if (r->parent) /* Already allocated */
1267 continue;
1268 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1269 continue; /* Not assigned at all */
1270 /* We only allocate ROMs on pass 1 just in case they
1271 * have been screwed up by firmware
1272 */
1273 if (idx == PCI_ROM_RESOURCE )
1274 disabled = 1;
1275 if (r->flags & IORESOURCE_IO)
1276 disabled = !(command & PCI_COMMAND_IO);
1277 else
1278 disabled = !(command & PCI_COMMAND_MEMORY);
1279 if (pass == disabled)
1280 alloc_resource(dev, idx);
1281 }
1282 if (pass)
1283 continue;
1284 r = &dev->resource[PCI_ROM_RESOURCE];
1285 if (r->flags) {
1286 /* Turn the ROM off, leave the resource region,
1287 * but keep it unregistered.
1288 */
1289 u32 reg;
1290 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1291 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1292 pr_debug("PCI: Switching off ROM of %s\n",
1293 pci_name(dev));
1294 r->flags &= ~IORESOURCE_ROM_ENABLE;
1295 pci_write_config_dword(dev, dev->rom_base_reg,
1296 reg & ~PCI_ROM_ADDRESS_ENABLE);
1297 }
1298 }
1299 }
1300}
1301
1302static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1303{
1304 struct pci_controller *hose = pci_bus_to_host(bus);
1305 resource_size_t offset;
1306 struct resource *res, *pres;
1307 int i;
1308
1309 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1310
1311 /* Check for IO */
1312 if (!(hose->io_resource.flags & IORESOURCE_IO))
1313 goto no_io;
1314 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1315 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1316 BUG_ON(res == NULL);
1317 res->name = "Legacy IO";
1318 res->flags = IORESOURCE_IO;
1319 res->start = offset;
1320 res->end = (offset + 0xfff) & 0xfffffffful;
1321 pr_debug("Candidate legacy IO: %pR\n", res);
1322 if (request_resource(&hose->io_resource, res)) {
1323 printk(KERN_DEBUG
1324 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1325 pci_domain_nr(bus), bus->number, res);
1326 kfree(res);
1327 }
1328
1329 no_io:
1330 /* Check for memory */
1331 for (i = 0; i < 3; i++) {
1332 pres = &hose->mem_resources[i];
1333 offset = hose->mem_offset[i];
1334 if (!(pres->flags & IORESOURCE_MEM))
1335 continue;
1336 pr_debug("hose mem res: %pR\n", pres);
1337 if ((pres->start - offset) <= 0xa0000 &&
1338 (pres->end - offset) >= 0xbffff)
1339 break;
1340 }
1341 if (i >= 3)
1342 return;
1343 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1344 BUG_ON(res == NULL);
1345 res->name = "Legacy VGA memory";
1346 res->flags = IORESOURCE_MEM;
1347 res->start = 0xa0000 + offset;
1348 res->end = 0xbffff + offset;
1349 pr_debug("Candidate VGA memory: %pR\n", res);
1350 if (request_resource(pres, res)) {
1351 printk(KERN_DEBUG
1352 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1353 pci_domain_nr(bus), bus->number, res);
1354 kfree(res);
1355 }
1356}
1357
1358void __init pcibios_resource_survey(void)
1359{
1360 struct pci_bus *b;
1361
1362 /* Allocate and assign resources */
1363 list_for_each_entry(b, &pci_root_buses, node)
1364 pcibios_allocate_bus_resources(b);
1365 pcibios_allocate_resources(0);
1366 pcibios_allocate_resources(1);
1367
1368 /* Before we start assigning unassigned resource, we try to reserve
1369 * the low IO area and the VGA memory area if they intersect the
1370 * bus available resources to avoid allocating things on top of them
1371 */
1372 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1373 list_for_each_entry(b, &pci_root_buses, node)
1374 pcibios_reserve_legacy_regions(b);
1375 }
1376
1377 /* Now, if the platform didn't decide to blindly trust the firmware,
1378 * we proceed to assigning things that were left unassigned
1379 */
1380 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1381 pr_debug("PCI: Assigning unassigned resources...\n");
1382 pci_assign_unassigned_resources();
1383 }
1384
1385 /* Call machine dependent fixup */
1386 if (ppc_md.pcibios_fixup)
1387 ppc_md.pcibios_fixup();
1388}
1389
1390/* This is used by the PCI hotplug driver to allocate resource
1391 * of newly plugged busses. We can try to consolidate with the
1392 * rest of the code later, for now, keep it as-is as our main
1393 * resource allocation function doesn't deal with sub-trees yet.
1394 */
1395void pcibios_claim_one_bus(struct pci_bus *bus)
1396{
1397 struct pci_dev *dev;
1398 struct pci_bus *child_bus;
1399
1400 list_for_each_entry(dev, &bus->devices, bus_list) {
1401 int i;
1402
1403 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1404 struct resource *r = &dev->resource[i];
1405
1406 if (r->parent || !r->start || !r->flags)
1407 continue;
1408
1409 pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1410 pci_name(dev), i, r);
1411
1412 if (pci_claim_resource(dev, i) == 0)
1413 continue;
1414
1415 pci_claim_bridge_resource(dev, i);
1416 }
1417 }
1418
1419 list_for_each_entry(child_bus, &bus->children, node)
1420 pcibios_claim_one_bus(child_bus);
1421}
1422EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1423
1424
1425/* pcibios_finish_adding_to_bus
1426 *
1427 * This is to be called by the hotplug code after devices have been
1428 * added to a bus, this include calling it for a PHB that is just
1429 * being added
1430 */
1431void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1432{
1433 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1434 pci_domain_nr(bus), bus->number);
1435
1436 /* Allocate bus and devices resources */
1437 pcibios_allocate_bus_resources(bus);
1438 pcibios_claim_one_bus(bus);
1439 if (!pci_has_flag(PCI_PROBE_ONLY))
1440 pci_assign_unassigned_bus_resources(bus);
1441
1442 /* Fixup EEH */
1443 eeh_add_device_tree_late(bus);
1444
1445 /* Add new devices to global lists. Register in proc, sysfs. */
1446 pci_bus_add_devices(bus);
1447
1448 /* sysfs files should only be added after devices are added */
1449 eeh_add_sysfs_files(bus);
1450}
1451EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1452
1453int pcibios_enable_device(struct pci_dev *dev, int mask)
1454{
1455 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1456
1457 if (phb->controller_ops.enable_device_hook)
1458 if (!phb->controller_ops.enable_device_hook(dev))
1459 return -EINVAL;
1460
1461 return pci_enable_resources(dev, mask);
1462}
1463
1464void pcibios_disable_device(struct pci_dev *dev)
1465{
1466 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1467
1468 if (phb->controller_ops.disable_device)
1469 phb->controller_ops.disable_device(dev);
1470}
1471
1472resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1473{
1474 return (unsigned long) hose->io_base_virt - _IO_BASE;
1475}
1476
1477static void pcibios_setup_phb_resources(struct pci_controller *hose,
1478 struct list_head *resources)
1479{
1480 struct resource *res;
1481 resource_size_t offset;
1482 int i;
1483
1484 /* Hookup PHB IO resource */
1485 res = &hose->io_resource;
1486
1487 if (!res->flags) {
1488 pr_info("PCI: I/O resource not set for host"
1489 " bridge %s (domain %d)\n",
1490 hose->dn->full_name, hose->global_number);
1491 } else {
1492 offset = pcibios_io_space_offset(hose);
1493
1494 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
1495 res, (unsigned long long)offset);
1496 pci_add_resource_offset(resources, res, offset);
1497 }
1498
1499 /* Hookup PHB Memory resources */
1500 for (i = 0; i < 3; ++i) {
1501 res = &hose->mem_resources[i];
1502 if (!res->flags) {
1503 if (i == 0)
1504 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1505 "host bridge %s (domain %d)\n",
1506 hose->dn->full_name, hose->global_number);
1507 continue;
1508 }
1509 offset = hose->mem_offset[i];
1510
1511
1512 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1513 res, (unsigned long long)offset);
1514
1515 pci_add_resource_offset(resources, res, offset);
1516 }
1517}
1518
1519/*
1520 * Null PCI config access functions, for the case when we can't
1521 * find a hose.
1522 */
1523#define NULL_PCI_OP(rw, size, type) \
1524static int \
1525null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1526{ \
1527 return PCIBIOS_DEVICE_NOT_FOUND; \
1528}
1529
1530static int
1531null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1532 int len, u32 *val)
1533{
1534 return PCIBIOS_DEVICE_NOT_FOUND;
1535}
1536
1537static int
1538null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1539 int len, u32 val)
1540{
1541 return PCIBIOS_DEVICE_NOT_FOUND;
1542}
1543
1544static struct pci_ops null_pci_ops =
1545{
1546 .read = null_read_config,
1547 .write = null_write_config,
1548};
1549
1550/*
1551 * These functions are used early on before PCI scanning is done
1552 * and all of the pci_dev and pci_bus structures have been created.
1553 */
1554static struct pci_bus *
1555fake_pci_bus(struct pci_controller *hose, int busnr)
1556{
1557 static struct pci_bus bus;
1558
1559 if (hose == NULL) {
1560 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1561 }
1562 bus.number = busnr;
1563 bus.sysdata = hose;
1564 bus.ops = hose? hose->ops: &null_pci_ops;
1565 return &bus;
1566}
1567
1568#define EARLY_PCI_OP(rw, size, type) \
1569int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1570 int devfn, int offset, type value) \
1571{ \
1572 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1573 devfn, offset, value); \
1574}
1575
1576EARLY_PCI_OP(read, byte, u8 *)
1577EARLY_PCI_OP(read, word, u16 *)
1578EARLY_PCI_OP(read, dword, u32 *)
1579EARLY_PCI_OP(write, byte, u8)
1580EARLY_PCI_OP(write, word, u16)
1581EARLY_PCI_OP(write, dword, u32)
1582
1583int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1584 int cap)
1585{
1586 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1587}
1588
1589struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1590{
1591 struct pci_controller *hose = bus->sysdata;
1592
1593 return of_node_get(hose->dn);
1594}
1595
1596/**
1597 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1598 * @hose: Pointer to the PCI host controller instance structure
1599 */
1600void pcibios_scan_phb(struct pci_controller *hose)
1601{
1602 LIST_HEAD(resources);
1603 struct pci_bus *bus;
1604 struct device_node *node = hose->dn;
1605 int mode;
1606
1607 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1608
1609 /* Get some IO space for the new PHB */
1610 pcibios_setup_phb_io_space(hose);
1611
1612 /* Wire up PHB bus resources */
1613 pcibios_setup_phb_resources(hose, &resources);
1614
1615 hose->busn.start = hose->first_busno;
1616 hose->busn.end = hose->last_busno;
1617 hose->busn.flags = IORESOURCE_BUS;
1618 pci_add_resource(&resources, &hose->busn);
1619
1620 /* Create an empty bus for the toplevel */
1621 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1622 hose->ops, hose, &resources);
1623 if (bus == NULL) {
1624 pr_err("Failed to create bus for PCI domain %04x\n",
1625 hose->global_number);
1626 pci_free_resource_list(&resources);
1627 return;
1628 }
1629 hose->bus = bus;
1630
1631 /* Get probe mode and perform scan */
1632 mode = PCI_PROBE_NORMAL;
1633 if (node && hose->controller_ops.probe_mode)
1634 mode = hose->controller_ops.probe_mode(bus);
1635 pr_debug(" probe mode: %d\n", mode);
1636 if (mode == PCI_PROBE_DEVTREE)
1637 of_scan_bus(node, bus);
1638
1639 if (mode == PCI_PROBE_NORMAL) {
1640 pci_bus_update_busn_res_end(bus, 255);
1641 hose->last_busno = pci_scan_child_bus(bus);
1642 pci_bus_update_busn_res_end(bus, hose->last_busno);
1643 }
1644
1645 /* Platform gets a chance to do some global fixups before
1646 * we proceed to resource allocation
1647 */
1648 if (ppc_md.pcibios_fixup_phb)
1649 ppc_md.pcibios_fixup_phb(hose);
1650
1651 /* Configure PCI Express settings */
1652 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1653 struct pci_bus *child;
1654 list_for_each_entry(child, &bus->children, node)
1655 pcie_bus_configure_settings(child);
1656 }
1657}
1658EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1659
1660static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1661{
1662 int i, class = dev->class >> 8;
1663 /* When configured as agent, programing interface = 1 */
1664 int prog_if = dev->class & 0xf;
1665
1666 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1667 class == PCI_CLASS_BRIDGE_OTHER) &&
1668 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1669 (prog_if == 0) &&
1670 (dev->bus->parent == NULL)) {
1671 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1672 dev->resource[i].start = 0;
1673 dev->resource[i].end = 0;
1674 dev->resource[i].flags = 0;
1675 }
1676 }
1677}
1678DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1679DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1680
1681static void fixup_vga(struct pci_dev *pdev)
1682{
1683 u16 cmd;
1684
1685 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1686 if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device())
1687 vga_set_default_device(pdev);
1688
1689}
1690DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1691 PCI_CLASS_DISPLAY_VGA, 8, fixup_vga);