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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Contains common pci routines for ALL ppc platform
4 * (based on pci_32.c and pci_64.c)
5 *
6 * Port for PPC64 David Engebretsen, IBM Corp.
7 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 *
9 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
10 * Rework, based on alpha PCI code.
11 *
12 * Common pmac/prep/chrp pci routines. -- Cort
13 */
14
15#include <linux/kernel.h>
16#include <linux/pci.h>
17#include <linux/string.h>
18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/export.h>
21#include <linux/of_address.h>
22#include <linux/of_pci.h>
23#include <linux/mm.h>
24#include <linux/shmem_fs.h>
25#include <linux/list.h>
26#include <linux/syscalls.h>
27#include <linux/irq.h>
28#include <linux/vmalloc.h>
29#include <linux/slab.h>
30#include <linux/vgaarb.h>
31#include <linux/numa.h>
32
33#include <asm/processor.h>
34#include <asm/io.h>
35#include <asm/prom.h>
36#include <asm/pci-bridge.h>
37#include <asm/byteorder.h>
38#include <asm/machdep.h>
39#include <asm/ppc-pci.h>
40#include <asm/eeh.h>
41
42#include "../../../drivers/pci/pci.h"
43
44/* hose_spinlock protects accesses to the the phb_bitmap. */
45static DEFINE_SPINLOCK(hose_spinlock);
46LIST_HEAD(hose_list);
47
48/* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */
49#define MAX_PHBS 0x10000
50
51/*
52 * For dynamic PHB numbering: used/free PHBs tracking bitmap.
53 * Accesses to this bitmap should be protected by hose_spinlock.
54 */
55static DECLARE_BITMAP(phb_bitmap, MAX_PHBS);
56
57/* ISA Memory physical address */
58resource_size_t isa_mem_base;
59EXPORT_SYMBOL(isa_mem_base);
60
61
62static const struct dma_map_ops *pci_dma_ops;
63
64void set_pci_dma_ops(const struct dma_map_ops *dma_ops)
65{
66 pci_dma_ops = dma_ops;
67}
68
69/*
70 * This function should run under locking protection, specifically
71 * hose_spinlock.
72 */
73static int get_phb_number(struct device_node *dn)
74{
75 int ret, phb_id = -1;
76 u32 prop_32;
77 u64 prop;
78
79 /*
80 * Try fixed PHB numbering first, by checking archs and reading
81 * the respective device-tree properties. Firstly, try powernv by
82 * reading "ibm,opal-phbid", only present in OPAL environment.
83 */
84 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
85 if (ret) {
86 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32);
87 prop = prop_32;
88 }
89
90 if (!ret)
91 phb_id = (int)(prop & (MAX_PHBS - 1));
92
93 /* We need to be sure to not use the same PHB number twice. */
94 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap))
95 return phb_id;
96
97 /*
98 * If not pseries nor powernv, or if fixed PHB numbering tried to add
99 * the same PHB number twice, then fallback to dynamic PHB numbering.
100 */
101 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS);
102 BUG_ON(phb_id >= MAX_PHBS);
103 set_bit(phb_id, phb_bitmap);
104
105 return phb_id;
106}
107
108struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
109{
110 struct pci_controller *phb;
111
112 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
113 if (phb == NULL)
114 return NULL;
115 spin_lock(&hose_spinlock);
116 phb->global_number = get_phb_number(dev);
117 list_add_tail(&phb->list_node, &hose_list);
118 spin_unlock(&hose_spinlock);
119 phb->dn = dev;
120 phb->is_dynamic = slab_is_available();
121#ifdef CONFIG_PPC64
122 if (dev) {
123 int nid = of_node_to_nid(dev);
124
125 if (nid < 0 || !node_online(nid))
126 nid = NUMA_NO_NODE;
127
128 PHB_SET_NODE(phb, nid);
129 }
130#endif
131 return phb;
132}
133EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
134
135void pcibios_free_controller(struct pci_controller *phb)
136{
137 spin_lock(&hose_spinlock);
138
139 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */
140 if (phb->global_number < MAX_PHBS)
141 clear_bit(phb->global_number, phb_bitmap);
142
143 list_del(&phb->list_node);
144 spin_unlock(&hose_spinlock);
145
146 if (phb->is_dynamic)
147 kfree(phb);
148}
149EXPORT_SYMBOL_GPL(pcibios_free_controller);
150
151/*
152 * This function is used to call pcibios_free_controller()
153 * in a deferred manner: a callback from the PCI subsystem.
154 *
155 * _*DO NOT*_ call pcibios_free_controller() explicitly if
156 * this is used (or it may access an invalid *phb pointer).
157 *
158 * The callback occurs when all references to the root bus
159 * are dropped (e.g., child buses/devices and their users).
160 *
161 * It's called as .release_fn() of 'struct pci_host_bridge'
162 * which is associated with the 'struct pci_controller.bus'
163 * (root bus) - it expects .release_data to hold a pointer
164 * to 'struct pci_controller'.
165 *
166 * In order to use it, register .release_fn()/release_data
167 * like this:
168 *
169 * pci_set_host_bridge_release(bridge,
170 * pcibios_free_controller_deferred
171 * (void *) phb);
172 *
173 * e.g. in the pcibios_root_bridge_prepare() callback from
174 * pci_create_root_bus().
175 */
176void pcibios_free_controller_deferred(struct pci_host_bridge *bridge)
177{
178 struct pci_controller *phb = (struct pci_controller *)
179 bridge->release_data;
180
181 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic);
182
183 pcibios_free_controller(phb);
184}
185EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred);
186
187/*
188 * The function is used to return the minimal alignment
189 * for memory or I/O windows of the associated P2P bridge.
190 * By default, 4KiB alignment for I/O windows and 1MiB for
191 * memory windows.
192 */
193resource_size_t pcibios_window_alignment(struct pci_bus *bus,
194 unsigned long type)
195{
196 struct pci_controller *phb = pci_bus_to_host(bus);
197
198 if (phb->controller_ops.window_alignment)
199 return phb->controller_ops.window_alignment(bus, type);
200
201 /*
202 * PCI core will figure out the default
203 * alignment: 4KiB for I/O and 1MiB for
204 * memory window.
205 */
206 return 1;
207}
208
209void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
210{
211 struct pci_controller *hose = pci_bus_to_host(bus);
212
213 if (hose->controller_ops.setup_bridge)
214 hose->controller_ops.setup_bridge(bus, type);
215}
216
217void pcibios_reset_secondary_bus(struct pci_dev *dev)
218{
219 struct pci_controller *phb = pci_bus_to_host(dev->bus);
220
221 if (phb->controller_ops.reset_secondary_bus) {
222 phb->controller_ops.reset_secondary_bus(dev);
223 return;
224 }
225
226 pci_reset_secondary_bus(dev);
227}
228
229resource_size_t pcibios_default_alignment(void)
230{
231 if (ppc_md.pcibios_default_alignment)
232 return ppc_md.pcibios_default_alignment();
233
234 return 0;
235}
236
237#ifdef CONFIG_PCI_IOV
238resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
239{
240 if (ppc_md.pcibios_iov_resource_alignment)
241 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
242
243 return pci_iov_resource_size(pdev, resno);
244}
245
246int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
247{
248 if (ppc_md.pcibios_sriov_enable)
249 return ppc_md.pcibios_sriov_enable(pdev, num_vfs);
250
251 return 0;
252}
253
254int pcibios_sriov_disable(struct pci_dev *pdev)
255{
256 if (ppc_md.pcibios_sriov_disable)
257 return ppc_md.pcibios_sriov_disable(pdev);
258
259 return 0;
260}
261
262#endif /* CONFIG_PCI_IOV */
263
264static resource_size_t pcibios_io_size(const struct pci_controller *hose)
265{
266#ifdef CONFIG_PPC64
267 return hose->pci_io_size;
268#else
269 return resource_size(&hose->io_resource);
270#endif
271}
272
273int pcibios_vaddr_is_ioport(void __iomem *address)
274{
275 int ret = 0;
276 struct pci_controller *hose;
277 resource_size_t size;
278
279 spin_lock(&hose_spinlock);
280 list_for_each_entry(hose, &hose_list, list_node) {
281 size = pcibios_io_size(hose);
282 if (address >= hose->io_base_virt &&
283 address < (hose->io_base_virt + size)) {
284 ret = 1;
285 break;
286 }
287 }
288 spin_unlock(&hose_spinlock);
289 return ret;
290}
291
292unsigned long pci_address_to_pio(phys_addr_t address)
293{
294 struct pci_controller *hose;
295 resource_size_t size;
296 unsigned long ret = ~0;
297
298 spin_lock(&hose_spinlock);
299 list_for_each_entry(hose, &hose_list, list_node) {
300 size = pcibios_io_size(hose);
301 if (address >= hose->io_base_phys &&
302 address < (hose->io_base_phys + size)) {
303 unsigned long base =
304 (unsigned long)hose->io_base_virt - _IO_BASE;
305 ret = base + (address - hose->io_base_phys);
306 break;
307 }
308 }
309 spin_unlock(&hose_spinlock);
310
311 return ret;
312}
313EXPORT_SYMBOL_GPL(pci_address_to_pio);
314
315/*
316 * Return the domain number for this bus.
317 */
318int pci_domain_nr(struct pci_bus *bus)
319{
320 struct pci_controller *hose = pci_bus_to_host(bus);
321
322 return hose->global_number;
323}
324EXPORT_SYMBOL(pci_domain_nr);
325
326/* This routine is meant to be used early during boot, when the
327 * PCI bus numbers have not yet been assigned, and you need to
328 * issue PCI config cycles to an OF device.
329 * It could also be used to "fix" RTAS config cycles if you want
330 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
331 * config cycles.
332 */
333struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
334{
335 while(node) {
336 struct pci_controller *hose, *tmp;
337 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
338 if (hose->dn == node)
339 return hose;
340 node = node->parent;
341 }
342 return NULL;
343}
344
345struct pci_controller *pci_find_controller_for_domain(int domain_nr)
346{
347 struct pci_controller *hose;
348
349 list_for_each_entry(hose, &hose_list, list_node)
350 if (hose->global_number == domain_nr)
351 return hose;
352
353 return NULL;
354}
355
356/*
357 * Reads the interrupt pin to determine if interrupt is use by card.
358 * If the interrupt is used, then gets the interrupt line from the
359 * openfirmware and sets it in the pci_dev and pci_config line.
360 */
361static int pci_read_irq_line(struct pci_dev *pci_dev)
362{
363 int virq;
364
365 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
366
367 /* Try to get a mapping from the device-tree */
368 virq = of_irq_parse_and_map_pci(pci_dev, 0, 0);
369 if (virq <= 0) {
370 u8 line, pin;
371
372 /* If that fails, lets fallback to what is in the config
373 * space and map that through the default controller. We
374 * also set the type to level low since that's what PCI
375 * interrupts are. If your platform does differently, then
376 * either provide a proper interrupt tree or don't use this
377 * function.
378 */
379 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
380 return -1;
381 if (pin == 0)
382 return -1;
383 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
384 line == 0xff || line == 0) {
385 return -1;
386 }
387 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
388 line, pin);
389
390 virq = irq_create_mapping(NULL, line);
391 if (virq)
392 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
393 }
394
395 if (!virq) {
396 pr_debug(" Failed to map !\n");
397 return -1;
398 }
399
400 pr_debug(" Mapped to linux irq %d\n", virq);
401
402 pci_dev->irq = virq;
403
404 return 0;
405}
406
407/*
408 * Platform support for /proc/bus/pci/X/Y mmap()s.
409 * -- paulus.
410 */
411int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
412{
413 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
414 resource_size_t ioaddr = pci_resource_start(pdev, bar);
415
416 if (!hose)
417 return -EINVAL;
418
419 /* Convert to an offset within this PCI controller */
420 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
421
422 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
423 return 0;
424}
425
426/*
427 * This one is used by /dev/mem and fbdev who have no clue about the
428 * PCI device, it tries to find the PCI device first and calls the
429 * above routine
430 */
431pgprot_t pci_phys_mem_access_prot(struct file *file,
432 unsigned long pfn,
433 unsigned long size,
434 pgprot_t prot)
435{
436 struct pci_dev *pdev = NULL;
437 struct resource *found = NULL;
438 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
439 int i;
440
441 if (page_is_ram(pfn))
442 return prot;
443
444 prot = pgprot_noncached(prot);
445 for_each_pci_dev(pdev) {
446 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
447 struct resource *rp = &pdev->resource[i];
448 int flags = rp->flags;
449
450 /* Active and same type? */
451 if ((flags & IORESOURCE_MEM) == 0)
452 continue;
453 /* In the range of this resource? */
454 if (offset < (rp->start & PAGE_MASK) ||
455 offset > rp->end)
456 continue;
457 found = rp;
458 break;
459 }
460 if (found)
461 break;
462 }
463 if (found) {
464 if (found->flags & IORESOURCE_PREFETCH)
465 prot = pgprot_noncached_wc(prot);
466 pci_dev_put(pdev);
467 }
468
469 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
470 (unsigned long long)offset, pgprot_val(prot));
471
472 return prot;
473}
474
475/* This provides legacy IO read access on a bus */
476int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
477{
478 unsigned long offset;
479 struct pci_controller *hose = pci_bus_to_host(bus);
480 struct resource *rp = &hose->io_resource;
481 void __iomem *addr;
482
483 /* Check if port can be supported by that bus. We only check
484 * the ranges of the PHB though, not the bus itself as the rules
485 * for forwarding legacy cycles down bridges are not our problem
486 * here. So if the host bridge supports it, we do it.
487 */
488 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
489 offset += port;
490
491 if (!(rp->flags & IORESOURCE_IO))
492 return -ENXIO;
493 if (offset < rp->start || (offset + size) > rp->end)
494 return -ENXIO;
495 addr = hose->io_base_virt + port;
496
497 switch(size) {
498 case 1:
499 *((u8 *)val) = in_8(addr);
500 return 1;
501 case 2:
502 if (port & 1)
503 return -EINVAL;
504 *((u16 *)val) = in_le16(addr);
505 return 2;
506 case 4:
507 if (port & 3)
508 return -EINVAL;
509 *((u32 *)val) = in_le32(addr);
510 return 4;
511 }
512 return -EINVAL;
513}
514
515/* This provides legacy IO write access on a bus */
516int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
517{
518 unsigned long offset;
519 struct pci_controller *hose = pci_bus_to_host(bus);
520 struct resource *rp = &hose->io_resource;
521 void __iomem *addr;
522
523 /* Check if port can be supported by that bus. We only check
524 * the ranges of the PHB though, not the bus itself as the rules
525 * for forwarding legacy cycles down bridges are not our problem
526 * here. So if the host bridge supports it, we do it.
527 */
528 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
529 offset += port;
530
531 if (!(rp->flags & IORESOURCE_IO))
532 return -ENXIO;
533 if (offset < rp->start || (offset + size) > rp->end)
534 return -ENXIO;
535 addr = hose->io_base_virt + port;
536
537 /* WARNING: The generic code is idiotic. It gets passed a pointer
538 * to what can be a 1, 2 or 4 byte quantity and always reads that
539 * as a u32, which means that we have to correct the location of
540 * the data read within those 32 bits for size 1 and 2
541 */
542 switch(size) {
543 case 1:
544 out_8(addr, val >> 24);
545 return 1;
546 case 2:
547 if (port & 1)
548 return -EINVAL;
549 out_le16(addr, val >> 16);
550 return 2;
551 case 4:
552 if (port & 3)
553 return -EINVAL;
554 out_le32(addr, val);
555 return 4;
556 }
557 return -EINVAL;
558}
559
560/* This provides legacy IO or memory mmap access on a bus */
561int pci_mmap_legacy_page_range(struct pci_bus *bus,
562 struct vm_area_struct *vma,
563 enum pci_mmap_state mmap_state)
564{
565 struct pci_controller *hose = pci_bus_to_host(bus);
566 resource_size_t offset =
567 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
568 resource_size_t size = vma->vm_end - vma->vm_start;
569 struct resource *rp;
570
571 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
572 pci_domain_nr(bus), bus->number,
573 mmap_state == pci_mmap_mem ? "MEM" : "IO",
574 (unsigned long long)offset,
575 (unsigned long long)(offset + size - 1));
576
577 if (mmap_state == pci_mmap_mem) {
578 /* Hack alert !
579 *
580 * Because X is lame and can fail starting if it gets an error trying
581 * to mmap legacy_mem (instead of just moving on without legacy memory
582 * access) we fake it here by giving it anonymous memory, effectively
583 * behaving just like /dev/zero
584 */
585 if ((offset + size) > hose->isa_mem_size) {
586 printk(KERN_DEBUG
587 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
588 current->comm, current->pid, pci_domain_nr(bus), bus->number);
589 if (vma->vm_flags & VM_SHARED)
590 return shmem_zero_setup(vma);
591 return 0;
592 }
593 offset += hose->isa_mem_phys;
594 } else {
595 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
596 unsigned long roffset = offset + io_offset;
597 rp = &hose->io_resource;
598 if (!(rp->flags & IORESOURCE_IO))
599 return -ENXIO;
600 if (roffset < rp->start || (roffset + size) > rp->end)
601 return -ENXIO;
602 offset += hose->io_base_phys;
603 }
604 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
605
606 vma->vm_pgoff = offset >> PAGE_SHIFT;
607 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
608 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
609 vma->vm_end - vma->vm_start,
610 vma->vm_page_prot);
611}
612
613void pci_resource_to_user(const struct pci_dev *dev, int bar,
614 const struct resource *rsrc,
615 resource_size_t *start, resource_size_t *end)
616{
617 struct pci_bus_region region;
618
619 if (rsrc->flags & IORESOURCE_IO) {
620 pcibios_resource_to_bus(dev->bus, ®ion,
621 (struct resource *) rsrc);
622 *start = region.start;
623 *end = region.end;
624 return;
625 }
626
627 /* We pass a CPU physical address to userland for MMIO instead of a
628 * BAR value because X is lame and expects to be able to use that
629 * to pass to /dev/mem!
630 *
631 * That means we may have 64-bit values where some apps only expect
632 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
633 */
634 *start = rsrc->start;
635 *end = rsrc->end;
636}
637
638/**
639 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
640 * @hose: newly allocated pci_controller to be setup
641 * @dev: device node of the host bridge
642 * @primary: set if primary bus (32 bits only, soon to be deprecated)
643 *
644 * This function will parse the "ranges" property of a PCI host bridge device
645 * node and setup the resource mapping of a pci controller based on its
646 * content.
647 *
648 * Life would be boring if it wasn't for a few issues that we have to deal
649 * with here:
650 *
651 * - We can only cope with one IO space range and up to 3 Memory space
652 * ranges. However, some machines (thanks Apple !) tend to split their
653 * space into lots of small contiguous ranges. So we have to coalesce.
654 *
655 * - Some busses have IO space not starting at 0, which causes trouble with
656 * the way we do our IO resource renumbering. The code somewhat deals with
657 * it for 64 bits but I would expect problems on 32 bits.
658 *
659 * - Some 32 bits platforms such as 4xx can have physical space larger than
660 * 32 bits so we need to use 64 bits values for the parsing
661 */
662void pci_process_bridge_OF_ranges(struct pci_controller *hose,
663 struct device_node *dev, int primary)
664{
665 int memno = 0;
666 struct resource *res;
667 struct of_pci_range range;
668 struct of_pci_range_parser parser;
669
670 printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n",
671 dev, primary ? "(primary)" : "");
672
673 /* Check for ranges property */
674 if (of_pci_range_parser_init(&parser, dev))
675 return;
676
677 /* Parse it */
678 for_each_of_pci_range(&parser, &range) {
679 /* If we failed translation or got a zero-sized region
680 * (some FW try to feed us with non sensical zero sized regions
681 * such as power3 which look like some kind of attempt at exposing
682 * the VGA memory hole)
683 */
684 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
685 continue;
686
687 /* Act based on address space type */
688 res = NULL;
689 switch (range.flags & IORESOURCE_TYPE_BITS) {
690 case IORESOURCE_IO:
691 printk(KERN_INFO
692 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
693 range.cpu_addr, range.cpu_addr + range.size - 1,
694 range.pci_addr);
695
696 /* We support only one IO range */
697 if (hose->pci_io_size) {
698 printk(KERN_INFO
699 " \\--> Skipped (too many) !\n");
700 continue;
701 }
702#ifdef CONFIG_PPC32
703 /* On 32 bits, limit I/O space to 16MB */
704 if (range.size > 0x01000000)
705 range.size = 0x01000000;
706
707 /* 32 bits needs to map IOs here */
708 hose->io_base_virt = ioremap(range.cpu_addr,
709 range.size);
710
711 /* Expect trouble if pci_addr is not 0 */
712 if (primary)
713 isa_io_base =
714 (unsigned long)hose->io_base_virt;
715#endif /* CONFIG_PPC32 */
716 /* pci_io_size and io_base_phys always represent IO
717 * space starting at 0 so we factor in pci_addr
718 */
719 hose->pci_io_size = range.pci_addr + range.size;
720 hose->io_base_phys = range.cpu_addr - range.pci_addr;
721
722 /* Build resource */
723 res = &hose->io_resource;
724 range.cpu_addr = range.pci_addr;
725 break;
726 case IORESOURCE_MEM:
727 printk(KERN_INFO
728 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
729 range.cpu_addr, range.cpu_addr + range.size - 1,
730 range.pci_addr,
731 (range.flags & IORESOURCE_PREFETCH) ?
732 "Prefetch" : "");
733
734 /* We support only 3 memory ranges */
735 if (memno >= 3) {
736 printk(KERN_INFO
737 " \\--> Skipped (too many) !\n");
738 continue;
739 }
740 /* Handles ISA memory hole space here */
741 if (range.pci_addr == 0) {
742 if (primary || isa_mem_base == 0)
743 isa_mem_base = range.cpu_addr;
744 hose->isa_mem_phys = range.cpu_addr;
745 hose->isa_mem_size = range.size;
746 }
747
748 /* Build resource */
749 hose->mem_offset[memno] = range.cpu_addr -
750 range.pci_addr;
751 res = &hose->mem_resources[memno++];
752 break;
753 }
754 if (res != NULL) {
755 res->name = dev->full_name;
756 res->flags = range.flags;
757 res->start = range.cpu_addr;
758 res->end = range.cpu_addr + range.size - 1;
759 res->parent = res->child = res->sibling = NULL;
760 }
761 }
762}
763
764/* Decide whether to display the domain number in /proc */
765int pci_proc_domain(struct pci_bus *bus)
766{
767 struct pci_controller *hose = pci_bus_to_host(bus);
768
769 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
770 return 0;
771 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
772 return hose->global_number != 0;
773 return 1;
774}
775
776int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
777{
778 if (ppc_md.pcibios_root_bridge_prepare)
779 return ppc_md.pcibios_root_bridge_prepare(bridge);
780
781 return 0;
782}
783
784/* This header fixup will do the resource fixup for all devices as they are
785 * probed, but not for bridge ranges
786 */
787static void pcibios_fixup_resources(struct pci_dev *dev)
788{
789 struct pci_controller *hose = pci_bus_to_host(dev->bus);
790 int i;
791
792 if (!hose) {
793 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
794 pci_name(dev));
795 return;
796 }
797
798 if (dev->is_virtfn)
799 return;
800
801 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
802 struct resource *res = dev->resource + i;
803 struct pci_bus_region reg;
804 if (!res->flags)
805 continue;
806
807 /* If we're going to re-assign everything, we mark all resources
808 * as unset (and 0-base them). In addition, we mark BARs starting
809 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
810 * since in that case, we don't want to re-assign anything
811 */
812 pcibios_resource_to_bus(dev->bus, ®, res);
813 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
814 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
815 /* Only print message if not re-assigning */
816 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
817 pr_debug("PCI:%s Resource %d %pR is unassigned\n",
818 pci_name(dev), i, res);
819 res->end -= res->start;
820 res->start = 0;
821 res->flags |= IORESOURCE_UNSET;
822 continue;
823 }
824
825 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
826 }
827
828 /* Call machine specific resource fixup */
829 if (ppc_md.pcibios_fixup_resources)
830 ppc_md.pcibios_fixup_resources(dev);
831}
832DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
833
834/* This function tries to figure out if a bridge resource has been initialized
835 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
836 * things go more smoothly when it gets it right. It should covers cases such
837 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
838 */
839static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
840 struct resource *res)
841{
842 struct pci_controller *hose = pci_bus_to_host(bus);
843 struct pci_dev *dev = bus->self;
844 resource_size_t offset;
845 struct pci_bus_region region;
846 u16 command;
847 int i;
848
849 /* We don't do anything if PCI_PROBE_ONLY is set */
850 if (pci_has_flag(PCI_PROBE_ONLY))
851 return 0;
852
853 /* Job is a bit different between memory and IO */
854 if (res->flags & IORESOURCE_MEM) {
855 pcibios_resource_to_bus(dev->bus, ®ion, res);
856
857 /* If the BAR is non-0 then it's probably been initialized */
858 if (region.start != 0)
859 return 0;
860
861 /* The BAR is 0, let's check if memory decoding is enabled on
862 * the bridge. If not, we consider it unassigned
863 */
864 pci_read_config_word(dev, PCI_COMMAND, &command);
865 if ((command & PCI_COMMAND_MEMORY) == 0)
866 return 1;
867
868 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
869 * resources covers that starting address (0 then it's good enough for
870 * us for memory space)
871 */
872 for (i = 0; i < 3; i++) {
873 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
874 hose->mem_resources[i].start == hose->mem_offset[i])
875 return 0;
876 }
877
878 /* Well, it starts at 0 and we know it will collide so we may as
879 * well consider it as unassigned. That covers the Apple case.
880 */
881 return 1;
882 } else {
883 /* If the BAR is non-0, then we consider it assigned */
884 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
885 if (((res->start - offset) & 0xfffffffful) != 0)
886 return 0;
887
888 /* Here, we are a bit different than memory as typically IO space
889 * starting at low addresses -is- valid. What we do instead if that
890 * we consider as unassigned anything that doesn't have IO enabled
891 * in the PCI command register, and that's it.
892 */
893 pci_read_config_word(dev, PCI_COMMAND, &command);
894 if (command & PCI_COMMAND_IO)
895 return 0;
896
897 /* It's starting at 0 and IO is disabled in the bridge, consider
898 * it unassigned
899 */
900 return 1;
901 }
902}
903
904/* Fixup resources of a PCI<->PCI bridge */
905static void pcibios_fixup_bridge(struct pci_bus *bus)
906{
907 struct resource *res;
908 int i;
909
910 struct pci_dev *dev = bus->self;
911
912 pci_bus_for_each_resource(bus, res, i) {
913 if (!res || !res->flags)
914 continue;
915 if (i >= 3 && bus->self->transparent)
916 continue;
917
918 /* If we're going to reassign everything, we can
919 * shrink the P2P resource to have size as being
920 * of 0 in order to save space.
921 */
922 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
923 res->flags |= IORESOURCE_UNSET;
924 res->start = 0;
925 res->end = -1;
926 continue;
927 }
928
929 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
930
931 /* Try to detect uninitialized P2P bridge resources,
932 * and clear them out so they get re-assigned later
933 */
934 if (pcibios_uninitialized_bridge_resource(bus, res)) {
935 res->flags = 0;
936 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
937 }
938 }
939}
940
941void pcibios_setup_bus_self(struct pci_bus *bus)
942{
943 struct pci_controller *phb;
944
945 /* Fix up the bus resources for P2P bridges */
946 if (bus->self != NULL)
947 pcibios_fixup_bridge(bus);
948
949 /* Platform specific bus fixups. This is currently only used
950 * by fsl_pci and I'm hoping to get rid of it at some point
951 */
952 if (ppc_md.pcibios_fixup_bus)
953 ppc_md.pcibios_fixup_bus(bus);
954
955 /* Setup bus DMA mappings */
956 phb = pci_bus_to_host(bus);
957 if (phb->controller_ops.dma_bus_setup)
958 phb->controller_ops.dma_bus_setup(bus);
959}
960
961void pcibios_bus_add_device(struct pci_dev *dev)
962{
963 struct pci_controller *phb;
964 /* Fixup NUMA node as it may not be setup yet by the generic
965 * code and is needed by the DMA init
966 */
967 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
968
969 /* Hook up default DMA ops */
970 set_dma_ops(&dev->dev, pci_dma_ops);
971 dev->dev.archdata.dma_offset = PCI_DRAM_OFFSET;
972
973 /* Additional platform DMA/iommu setup */
974 phb = pci_bus_to_host(dev->bus);
975 if (phb->controller_ops.dma_dev_setup)
976 phb->controller_ops.dma_dev_setup(dev);
977
978 /* Read default IRQs and fixup if necessary */
979 pci_read_irq_line(dev);
980 if (ppc_md.pci_irq_fixup)
981 ppc_md.pci_irq_fixup(dev);
982
983 if (ppc_md.pcibios_bus_add_device)
984 ppc_md.pcibios_bus_add_device(dev);
985}
986
987int pcibios_add_device(struct pci_dev *dev)
988{
989#ifdef CONFIG_PCI_IOV
990 if (ppc_md.pcibios_fixup_sriov)
991 ppc_md.pcibios_fixup_sriov(dev);
992#endif /* CONFIG_PCI_IOV */
993
994 return 0;
995}
996
997void pcibios_set_master(struct pci_dev *dev)
998{
999 /* No special bus mastering setup handling */
1000}
1001
1002void pcibios_fixup_bus(struct pci_bus *bus)
1003{
1004 /* When called from the generic PCI probe, read PCI<->PCI bridge
1005 * bases. This is -not- called when generating the PCI tree from
1006 * the OF device-tree.
1007 */
1008 pci_read_bridge_bases(bus);
1009
1010 /* Now fixup the bus bus */
1011 pcibios_setup_bus_self(bus);
1012}
1013EXPORT_SYMBOL(pcibios_fixup_bus);
1014
1015static int skip_isa_ioresource_align(struct pci_dev *dev)
1016{
1017 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1018 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1019 return 1;
1020 return 0;
1021}
1022
1023/*
1024 * We need to avoid collisions with `mirrored' VGA ports
1025 * and other strange ISA hardware, so we always want the
1026 * addresses to be allocated in the 0x000-0x0ff region
1027 * modulo 0x400.
1028 *
1029 * Why? Because some silly external IO cards only decode
1030 * the low 10 bits of the IO address. The 0x00-0xff region
1031 * is reserved for motherboard devices that decode all 16
1032 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1033 * but we want to try to avoid allocating at 0x2900-0x2bff
1034 * which might have be mirrored at 0x0100-0x03ff..
1035 */
1036resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1037 resource_size_t size, resource_size_t align)
1038{
1039 struct pci_dev *dev = data;
1040 resource_size_t start = res->start;
1041
1042 if (res->flags & IORESOURCE_IO) {
1043 if (skip_isa_ioresource_align(dev))
1044 return start;
1045 if (start & 0x300)
1046 start = (start + 0x3ff) & ~0x3ff;
1047 }
1048
1049 return start;
1050}
1051EXPORT_SYMBOL(pcibios_align_resource);
1052
1053/*
1054 * Reparent resource children of pr that conflict with res
1055 * under res, and make res replace those children.
1056 */
1057static int reparent_resources(struct resource *parent,
1058 struct resource *res)
1059{
1060 struct resource *p, **pp;
1061 struct resource **firstpp = NULL;
1062
1063 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1064 if (p->end < res->start)
1065 continue;
1066 if (res->end < p->start)
1067 break;
1068 if (p->start < res->start || p->end > res->end)
1069 return -1; /* not completely contained */
1070 if (firstpp == NULL)
1071 firstpp = pp;
1072 }
1073 if (firstpp == NULL)
1074 return -1; /* didn't find any conflicting entries? */
1075 res->parent = parent;
1076 res->child = *firstpp;
1077 res->sibling = *pp;
1078 *firstpp = res;
1079 *pp = NULL;
1080 for (p = res->child; p != NULL; p = p->sibling) {
1081 p->parent = res;
1082 pr_debug("PCI: Reparented %s %pR under %s\n",
1083 p->name, p, res->name);
1084 }
1085 return 0;
1086}
1087
1088/*
1089 * Handle resources of PCI devices. If the world were perfect, we could
1090 * just allocate all the resource regions and do nothing more. It isn't.
1091 * On the other hand, we cannot just re-allocate all devices, as it would
1092 * require us to know lots of host bridge internals. So we attempt to
1093 * keep as much of the original configuration as possible, but tweak it
1094 * when it's found to be wrong.
1095 *
1096 * Known BIOS problems we have to work around:
1097 * - I/O or memory regions not configured
1098 * - regions configured, but not enabled in the command register
1099 * - bogus I/O addresses above 64K used
1100 * - expansion ROMs left enabled (this may sound harmless, but given
1101 * the fact the PCI specs explicitly allow address decoders to be
1102 * shared between expansion ROMs and other resource regions, it's
1103 * at least dangerous)
1104 *
1105 * Our solution:
1106 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1107 * This gives us fixed barriers on where we can allocate.
1108 * (2) Allocate resources for all enabled devices. If there is
1109 * a collision, just mark the resource as unallocated. Also
1110 * disable expansion ROMs during this step.
1111 * (3) Try to allocate resources for disabled devices. If the
1112 * resources were assigned correctly, everything goes well,
1113 * if they weren't, they won't disturb allocation of other
1114 * resources.
1115 * (4) Assign new addresses to resources which were either
1116 * not configured at all or misconfigured. If explicitly
1117 * requested by the user, configure expansion ROM address
1118 * as well.
1119 */
1120
1121static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1122{
1123 struct pci_bus *b;
1124 int i;
1125 struct resource *res, *pr;
1126
1127 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1128 pci_domain_nr(bus), bus->number);
1129
1130 pci_bus_for_each_resource(bus, res, i) {
1131 if (!res || !res->flags || res->start > res->end || res->parent)
1132 continue;
1133
1134 /* If the resource was left unset at this point, we clear it */
1135 if (res->flags & IORESOURCE_UNSET)
1136 goto clear_resource;
1137
1138 if (bus->parent == NULL)
1139 pr = (res->flags & IORESOURCE_IO) ?
1140 &ioport_resource : &iomem_resource;
1141 else {
1142 pr = pci_find_parent_resource(bus->self, res);
1143 if (pr == res) {
1144 /* this happens when the generic PCI
1145 * code (wrongly) decides that this
1146 * bridge is transparent -- paulus
1147 */
1148 continue;
1149 }
1150 }
1151
1152 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1153 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1154 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1155
1156 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1157 struct pci_dev *dev = bus->self;
1158
1159 if (request_resource(pr, res) == 0)
1160 continue;
1161 /*
1162 * Must be a conflict with an existing entry.
1163 * Move that entry (or entries) under the
1164 * bridge resource and try again.
1165 */
1166 if (reparent_resources(pr, res) == 0)
1167 continue;
1168
1169 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1170 pci_claim_bridge_resource(dev,
1171 i + PCI_BRIDGE_RESOURCES) == 0)
1172 continue;
1173 }
1174 pr_warn("PCI: Cannot allocate resource region %d of PCI bridge %d, will remap\n",
1175 i, bus->number);
1176 clear_resource:
1177 /* The resource might be figured out when doing
1178 * reassignment based on the resources required
1179 * by the downstream PCI devices. Here we set
1180 * the size of the resource to be 0 in order to
1181 * save more space.
1182 */
1183 res->start = 0;
1184 res->end = -1;
1185 res->flags = 0;
1186 }
1187
1188 list_for_each_entry(b, &bus->children, node)
1189 pcibios_allocate_bus_resources(b);
1190}
1191
1192static inline void alloc_resource(struct pci_dev *dev, int idx)
1193{
1194 struct resource *pr, *r = &dev->resource[idx];
1195
1196 pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1197 pci_name(dev), idx, r);
1198
1199 pr = pci_find_parent_resource(dev, r);
1200 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1201 request_resource(pr, r) < 0) {
1202 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1203 " of device %s, will remap\n", idx, pci_name(dev));
1204 if (pr)
1205 pr_debug("PCI: parent is %p: %pR\n", pr, pr);
1206 /* We'll assign a new address later */
1207 r->flags |= IORESOURCE_UNSET;
1208 r->end -= r->start;
1209 r->start = 0;
1210 }
1211}
1212
1213static void __init pcibios_allocate_resources(int pass)
1214{
1215 struct pci_dev *dev = NULL;
1216 int idx, disabled;
1217 u16 command;
1218 struct resource *r;
1219
1220 for_each_pci_dev(dev) {
1221 pci_read_config_word(dev, PCI_COMMAND, &command);
1222 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1223 r = &dev->resource[idx];
1224 if (r->parent) /* Already allocated */
1225 continue;
1226 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1227 continue; /* Not assigned at all */
1228 /* We only allocate ROMs on pass 1 just in case they
1229 * have been screwed up by firmware
1230 */
1231 if (idx == PCI_ROM_RESOURCE )
1232 disabled = 1;
1233 if (r->flags & IORESOURCE_IO)
1234 disabled = !(command & PCI_COMMAND_IO);
1235 else
1236 disabled = !(command & PCI_COMMAND_MEMORY);
1237 if (pass == disabled)
1238 alloc_resource(dev, idx);
1239 }
1240 if (pass)
1241 continue;
1242 r = &dev->resource[PCI_ROM_RESOURCE];
1243 if (r->flags) {
1244 /* Turn the ROM off, leave the resource region,
1245 * but keep it unregistered.
1246 */
1247 u32 reg;
1248 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1249 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1250 pr_debug("PCI: Switching off ROM of %s\n",
1251 pci_name(dev));
1252 r->flags &= ~IORESOURCE_ROM_ENABLE;
1253 pci_write_config_dword(dev, dev->rom_base_reg,
1254 reg & ~PCI_ROM_ADDRESS_ENABLE);
1255 }
1256 }
1257 }
1258}
1259
1260static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1261{
1262 struct pci_controller *hose = pci_bus_to_host(bus);
1263 resource_size_t offset;
1264 struct resource *res, *pres;
1265 int i;
1266
1267 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1268
1269 /* Check for IO */
1270 if (!(hose->io_resource.flags & IORESOURCE_IO))
1271 goto no_io;
1272 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1273 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1274 BUG_ON(res == NULL);
1275 res->name = "Legacy IO";
1276 res->flags = IORESOURCE_IO;
1277 res->start = offset;
1278 res->end = (offset + 0xfff) & 0xfffffffful;
1279 pr_debug("Candidate legacy IO: %pR\n", res);
1280 if (request_resource(&hose->io_resource, res)) {
1281 printk(KERN_DEBUG
1282 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1283 pci_domain_nr(bus), bus->number, res);
1284 kfree(res);
1285 }
1286
1287 no_io:
1288 /* Check for memory */
1289 for (i = 0; i < 3; i++) {
1290 pres = &hose->mem_resources[i];
1291 offset = hose->mem_offset[i];
1292 if (!(pres->flags & IORESOURCE_MEM))
1293 continue;
1294 pr_debug("hose mem res: %pR\n", pres);
1295 if ((pres->start - offset) <= 0xa0000 &&
1296 (pres->end - offset) >= 0xbffff)
1297 break;
1298 }
1299 if (i >= 3)
1300 return;
1301 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1302 BUG_ON(res == NULL);
1303 res->name = "Legacy VGA memory";
1304 res->flags = IORESOURCE_MEM;
1305 res->start = 0xa0000 + offset;
1306 res->end = 0xbffff + offset;
1307 pr_debug("Candidate VGA memory: %pR\n", res);
1308 if (request_resource(pres, res)) {
1309 printk(KERN_DEBUG
1310 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1311 pci_domain_nr(bus), bus->number, res);
1312 kfree(res);
1313 }
1314}
1315
1316void __init pcibios_resource_survey(void)
1317{
1318 struct pci_bus *b;
1319
1320 /* Allocate and assign resources */
1321 list_for_each_entry(b, &pci_root_buses, node)
1322 pcibios_allocate_bus_resources(b);
1323 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1324 pcibios_allocate_resources(0);
1325 pcibios_allocate_resources(1);
1326 }
1327
1328 /* Before we start assigning unassigned resource, we try to reserve
1329 * the low IO area and the VGA memory area if they intersect the
1330 * bus available resources to avoid allocating things on top of them
1331 */
1332 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1333 list_for_each_entry(b, &pci_root_buses, node)
1334 pcibios_reserve_legacy_regions(b);
1335 }
1336
1337 /* Now, if the platform didn't decide to blindly trust the firmware,
1338 * we proceed to assigning things that were left unassigned
1339 */
1340 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1341 pr_debug("PCI: Assigning unassigned resources...\n");
1342 pci_assign_unassigned_resources();
1343 }
1344}
1345
1346/* This is used by the PCI hotplug driver to allocate resource
1347 * of newly plugged busses. We can try to consolidate with the
1348 * rest of the code later, for now, keep it as-is as our main
1349 * resource allocation function doesn't deal with sub-trees yet.
1350 */
1351void pcibios_claim_one_bus(struct pci_bus *bus)
1352{
1353 struct pci_dev *dev;
1354 struct pci_bus *child_bus;
1355
1356 list_for_each_entry(dev, &bus->devices, bus_list) {
1357 int i;
1358
1359 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1360 struct resource *r = &dev->resource[i];
1361
1362 if (r->parent || !r->start || !r->flags)
1363 continue;
1364
1365 pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1366 pci_name(dev), i, r);
1367
1368 if (pci_claim_resource(dev, i) == 0)
1369 continue;
1370
1371 pci_claim_bridge_resource(dev, i);
1372 }
1373 }
1374
1375 list_for_each_entry(child_bus, &bus->children, node)
1376 pcibios_claim_one_bus(child_bus);
1377}
1378EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1379
1380
1381/* pcibios_finish_adding_to_bus
1382 *
1383 * This is to be called by the hotplug code after devices have been
1384 * added to a bus, this include calling it for a PHB that is just
1385 * being added
1386 */
1387void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1388{
1389 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1390 pci_domain_nr(bus), bus->number);
1391
1392 /* Allocate bus and devices resources */
1393 pcibios_allocate_bus_resources(bus);
1394 pcibios_claim_one_bus(bus);
1395 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1396 if (bus->self)
1397 pci_assign_unassigned_bridge_resources(bus->self);
1398 else
1399 pci_assign_unassigned_bus_resources(bus);
1400 }
1401
1402 /* Add new devices to global lists. Register in proc, sysfs. */
1403 pci_bus_add_devices(bus);
1404}
1405EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1406
1407int pcibios_enable_device(struct pci_dev *dev, int mask)
1408{
1409 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1410
1411 if (phb->controller_ops.enable_device_hook)
1412 if (!phb->controller_ops.enable_device_hook(dev))
1413 return -EINVAL;
1414
1415 return pci_enable_resources(dev, mask);
1416}
1417
1418void pcibios_disable_device(struct pci_dev *dev)
1419{
1420 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1421
1422 if (phb->controller_ops.disable_device)
1423 phb->controller_ops.disable_device(dev);
1424}
1425
1426resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1427{
1428 return (unsigned long) hose->io_base_virt - _IO_BASE;
1429}
1430
1431static void pcibios_setup_phb_resources(struct pci_controller *hose,
1432 struct list_head *resources)
1433{
1434 struct resource *res;
1435 resource_size_t offset;
1436 int i;
1437
1438 /* Hookup PHB IO resource */
1439 res = &hose->io_resource;
1440
1441 if (!res->flags) {
1442 pr_debug("PCI: I/O resource not set for host"
1443 " bridge %pOF (domain %d)\n",
1444 hose->dn, hose->global_number);
1445 } else {
1446 offset = pcibios_io_space_offset(hose);
1447
1448 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
1449 res, (unsigned long long)offset);
1450 pci_add_resource_offset(resources, res, offset);
1451 }
1452
1453 /* Hookup PHB Memory resources */
1454 for (i = 0; i < 3; ++i) {
1455 res = &hose->mem_resources[i];
1456 if (!res->flags)
1457 continue;
1458
1459 offset = hose->mem_offset[i];
1460 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1461 res, (unsigned long long)offset);
1462
1463 pci_add_resource_offset(resources, res, offset);
1464 }
1465}
1466
1467/*
1468 * Null PCI config access functions, for the case when we can't
1469 * find a hose.
1470 */
1471#define NULL_PCI_OP(rw, size, type) \
1472static int \
1473null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1474{ \
1475 return PCIBIOS_DEVICE_NOT_FOUND; \
1476}
1477
1478static int
1479null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1480 int len, u32 *val)
1481{
1482 return PCIBIOS_DEVICE_NOT_FOUND;
1483}
1484
1485static int
1486null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1487 int len, u32 val)
1488{
1489 return PCIBIOS_DEVICE_NOT_FOUND;
1490}
1491
1492static struct pci_ops null_pci_ops =
1493{
1494 .read = null_read_config,
1495 .write = null_write_config,
1496};
1497
1498/*
1499 * These functions are used early on before PCI scanning is done
1500 * and all of the pci_dev and pci_bus structures have been created.
1501 */
1502static struct pci_bus *
1503fake_pci_bus(struct pci_controller *hose, int busnr)
1504{
1505 static struct pci_bus bus;
1506
1507 if (hose == NULL) {
1508 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1509 }
1510 bus.number = busnr;
1511 bus.sysdata = hose;
1512 bus.ops = hose? hose->ops: &null_pci_ops;
1513 return &bus;
1514}
1515
1516#define EARLY_PCI_OP(rw, size, type) \
1517int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1518 int devfn, int offset, type value) \
1519{ \
1520 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1521 devfn, offset, value); \
1522}
1523
1524EARLY_PCI_OP(read, byte, u8 *)
1525EARLY_PCI_OP(read, word, u16 *)
1526EARLY_PCI_OP(read, dword, u32 *)
1527EARLY_PCI_OP(write, byte, u8)
1528EARLY_PCI_OP(write, word, u16)
1529EARLY_PCI_OP(write, dword, u32)
1530
1531int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1532 int cap)
1533{
1534 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1535}
1536
1537struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1538{
1539 struct pci_controller *hose = bus->sysdata;
1540
1541 return of_node_get(hose->dn);
1542}
1543
1544/**
1545 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1546 * @hose: Pointer to the PCI host controller instance structure
1547 */
1548void pcibios_scan_phb(struct pci_controller *hose)
1549{
1550 LIST_HEAD(resources);
1551 struct pci_bus *bus;
1552 struct device_node *node = hose->dn;
1553 int mode;
1554
1555 pr_debug("PCI: Scanning PHB %pOF\n", node);
1556
1557 /* Get some IO space for the new PHB */
1558 pcibios_setup_phb_io_space(hose);
1559
1560 /* Wire up PHB bus resources */
1561 pcibios_setup_phb_resources(hose, &resources);
1562
1563 hose->busn.start = hose->first_busno;
1564 hose->busn.end = hose->last_busno;
1565 hose->busn.flags = IORESOURCE_BUS;
1566 pci_add_resource(&resources, &hose->busn);
1567
1568 /* Create an empty bus for the toplevel */
1569 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1570 hose->ops, hose, &resources);
1571 if (bus == NULL) {
1572 pr_err("Failed to create bus for PCI domain %04x\n",
1573 hose->global_number);
1574 pci_free_resource_list(&resources);
1575 return;
1576 }
1577 hose->bus = bus;
1578
1579 /* Get probe mode and perform scan */
1580 mode = PCI_PROBE_NORMAL;
1581 if (node && hose->controller_ops.probe_mode)
1582 mode = hose->controller_ops.probe_mode(bus);
1583 pr_debug(" probe mode: %d\n", mode);
1584 if (mode == PCI_PROBE_DEVTREE)
1585 of_scan_bus(node, bus);
1586
1587 if (mode == PCI_PROBE_NORMAL) {
1588 pci_bus_update_busn_res_end(bus, 255);
1589 hose->last_busno = pci_scan_child_bus(bus);
1590 pci_bus_update_busn_res_end(bus, hose->last_busno);
1591 }
1592
1593 /* Platform gets a chance to do some global fixups before
1594 * we proceed to resource allocation
1595 */
1596 if (ppc_md.pcibios_fixup_phb)
1597 ppc_md.pcibios_fixup_phb(hose);
1598
1599 /* Configure PCI Express settings */
1600 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1601 struct pci_bus *child;
1602 list_for_each_entry(child, &bus->children, node)
1603 pcie_bus_configure_settings(child);
1604 }
1605}
1606EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1607
1608static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1609{
1610 int i, class = dev->class >> 8;
1611 /* When configured as agent, programing interface = 1 */
1612 int prog_if = dev->class & 0xf;
1613
1614 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1615 class == PCI_CLASS_BRIDGE_OTHER) &&
1616 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1617 (prog_if == 0) &&
1618 (dev->bus->parent == NULL)) {
1619 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1620 dev->resource[i].start = 0;
1621 dev->resource[i].end = 0;
1622 dev->resource[i].flags = 0;
1623 }
1624 }
1625}
1626DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1627DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1/*
2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
4 *
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
7 *
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
10 *
11 * Common pmac/prep/chrp pci routines. -- Cort
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/string.h>
22#include <linux/init.h>
23#include <linux/delay.h>
24#include <linux/export.h>
25#include <linux/of_address.h>
26#include <linux/of_pci.h>
27#include <linux/mm.h>
28#include <linux/list.h>
29#include <linux/syscalls.h>
30#include <linux/irq.h>
31#include <linux/vmalloc.h>
32#include <linux/slab.h>
33#include <linux/vgaarb.h>
34
35#include <asm/processor.h>
36#include <asm/io.h>
37#include <asm/prom.h>
38#include <asm/pci-bridge.h>
39#include <asm/byteorder.h>
40#include <asm/machdep.h>
41#include <asm/ppc-pci.h>
42#include <asm/eeh.h>
43
44/* hose_spinlock protects accesses to the the phb_bitmap. */
45static DEFINE_SPINLOCK(hose_spinlock);
46LIST_HEAD(hose_list);
47
48/* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */
49#define MAX_PHBS 0x10000
50
51/*
52 * For dynamic PHB numbering: used/free PHBs tracking bitmap.
53 * Accesses to this bitmap should be protected by hose_spinlock.
54 */
55static DECLARE_BITMAP(phb_bitmap, MAX_PHBS);
56
57/* ISA Memory physical address */
58resource_size_t isa_mem_base;
59EXPORT_SYMBOL(isa_mem_base);
60
61
62static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
63
64void set_pci_dma_ops(struct dma_map_ops *dma_ops)
65{
66 pci_dma_ops = dma_ops;
67}
68
69struct dma_map_ops *get_pci_dma_ops(void)
70{
71 return pci_dma_ops;
72}
73EXPORT_SYMBOL(get_pci_dma_ops);
74
75/*
76 * This function should run under locking protection, specifically
77 * hose_spinlock.
78 */
79static int get_phb_number(struct device_node *dn)
80{
81 int ret, phb_id = -1;
82 u32 prop_32;
83 u64 prop;
84
85 /*
86 * Try fixed PHB numbering first, by checking archs and reading
87 * the respective device-tree properties. Firstly, try powernv by
88 * reading "ibm,opal-phbid", only present in OPAL environment.
89 */
90 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
91 if (ret) {
92 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32);
93 prop = prop_32;
94 }
95
96 if (!ret)
97 phb_id = (int)(prop & (MAX_PHBS - 1));
98
99 /* We need to be sure to not use the same PHB number twice. */
100 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap))
101 return phb_id;
102
103 /*
104 * If not pseries nor powernv, or if fixed PHB numbering tried to add
105 * the same PHB number twice, then fallback to dynamic PHB numbering.
106 */
107 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS);
108 BUG_ON(phb_id >= MAX_PHBS);
109 set_bit(phb_id, phb_bitmap);
110
111 return phb_id;
112}
113
114struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
115{
116 struct pci_controller *phb;
117
118 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
119 if (phb == NULL)
120 return NULL;
121 spin_lock(&hose_spinlock);
122 phb->global_number = get_phb_number(dev);
123 list_add_tail(&phb->list_node, &hose_list);
124 spin_unlock(&hose_spinlock);
125 phb->dn = dev;
126 phb->is_dynamic = slab_is_available();
127#ifdef CONFIG_PPC64
128 if (dev) {
129 int nid = of_node_to_nid(dev);
130
131 if (nid < 0 || !node_online(nid))
132 nid = -1;
133
134 PHB_SET_NODE(phb, nid);
135 }
136#endif
137 return phb;
138}
139EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
140
141void pcibios_free_controller(struct pci_controller *phb)
142{
143 spin_lock(&hose_spinlock);
144
145 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */
146 if (phb->global_number < MAX_PHBS)
147 clear_bit(phb->global_number, phb_bitmap);
148
149 list_del(&phb->list_node);
150 spin_unlock(&hose_spinlock);
151
152 if (phb->is_dynamic)
153 kfree(phb);
154}
155EXPORT_SYMBOL_GPL(pcibios_free_controller);
156
157/*
158 * This function is used to call pcibios_free_controller()
159 * in a deferred manner: a callback from the PCI subsystem.
160 *
161 * _*DO NOT*_ call pcibios_free_controller() explicitly if
162 * this is used (or it may access an invalid *phb pointer).
163 *
164 * The callback occurs when all references to the root bus
165 * are dropped (e.g., child buses/devices and their users).
166 *
167 * It's called as .release_fn() of 'struct pci_host_bridge'
168 * which is associated with the 'struct pci_controller.bus'
169 * (root bus) - it expects .release_data to hold a pointer
170 * to 'struct pci_controller'.
171 *
172 * In order to use it, register .release_fn()/release_data
173 * like this:
174 *
175 * pci_set_host_bridge_release(bridge,
176 * pcibios_free_controller_deferred
177 * (void *) phb);
178 *
179 * e.g. in the pcibios_root_bridge_prepare() callback from
180 * pci_create_root_bus().
181 */
182void pcibios_free_controller_deferred(struct pci_host_bridge *bridge)
183{
184 struct pci_controller *phb = (struct pci_controller *)
185 bridge->release_data;
186
187 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic);
188
189 pcibios_free_controller(phb);
190}
191EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred);
192
193/*
194 * The function is used to return the minimal alignment
195 * for memory or I/O windows of the associated P2P bridge.
196 * By default, 4KiB alignment for I/O windows and 1MiB for
197 * memory windows.
198 */
199resource_size_t pcibios_window_alignment(struct pci_bus *bus,
200 unsigned long type)
201{
202 struct pci_controller *phb = pci_bus_to_host(bus);
203
204 if (phb->controller_ops.window_alignment)
205 return phb->controller_ops.window_alignment(bus, type);
206
207 /*
208 * PCI core will figure out the default
209 * alignment: 4KiB for I/O and 1MiB for
210 * memory window.
211 */
212 return 1;
213}
214
215void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
216{
217 struct pci_controller *hose = pci_bus_to_host(bus);
218
219 if (hose->controller_ops.setup_bridge)
220 hose->controller_ops.setup_bridge(bus, type);
221}
222
223void pcibios_reset_secondary_bus(struct pci_dev *dev)
224{
225 struct pci_controller *phb = pci_bus_to_host(dev->bus);
226
227 if (phb->controller_ops.reset_secondary_bus) {
228 phb->controller_ops.reset_secondary_bus(dev);
229 return;
230 }
231
232 pci_reset_secondary_bus(dev);
233}
234
235#ifdef CONFIG_PCI_IOV
236resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
237{
238 if (ppc_md.pcibios_iov_resource_alignment)
239 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
240
241 return pci_iov_resource_size(pdev, resno);
242}
243#endif /* CONFIG_PCI_IOV */
244
245static resource_size_t pcibios_io_size(const struct pci_controller *hose)
246{
247#ifdef CONFIG_PPC64
248 return hose->pci_io_size;
249#else
250 return resource_size(&hose->io_resource);
251#endif
252}
253
254int pcibios_vaddr_is_ioport(void __iomem *address)
255{
256 int ret = 0;
257 struct pci_controller *hose;
258 resource_size_t size;
259
260 spin_lock(&hose_spinlock);
261 list_for_each_entry(hose, &hose_list, list_node) {
262 size = pcibios_io_size(hose);
263 if (address >= hose->io_base_virt &&
264 address < (hose->io_base_virt + size)) {
265 ret = 1;
266 break;
267 }
268 }
269 spin_unlock(&hose_spinlock);
270 return ret;
271}
272
273unsigned long pci_address_to_pio(phys_addr_t address)
274{
275 struct pci_controller *hose;
276 resource_size_t size;
277 unsigned long ret = ~0;
278
279 spin_lock(&hose_spinlock);
280 list_for_each_entry(hose, &hose_list, list_node) {
281 size = pcibios_io_size(hose);
282 if (address >= hose->io_base_phys &&
283 address < (hose->io_base_phys + size)) {
284 unsigned long base =
285 (unsigned long)hose->io_base_virt - _IO_BASE;
286 ret = base + (address - hose->io_base_phys);
287 break;
288 }
289 }
290 spin_unlock(&hose_spinlock);
291
292 return ret;
293}
294EXPORT_SYMBOL_GPL(pci_address_to_pio);
295
296/*
297 * Return the domain number for this bus.
298 */
299int pci_domain_nr(struct pci_bus *bus)
300{
301 struct pci_controller *hose = pci_bus_to_host(bus);
302
303 return hose->global_number;
304}
305EXPORT_SYMBOL(pci_domain_nr);
306
307/* This routine is meant to be used early during boot, when the
308 * PCI bus numbers have not yet been assigned, and you need to
309 * issue PCI config cycles to an OF device.
310 * It could also be used to "fix" RTAS config cycles if you want
311 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
312 * config cycles.
313 */
314struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
315{
316 while(node) {
317 struct pci_controller *hose, *tmp;
318 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
319 if (hose->dn == node)
320 return hose;
321 node = node->parent;
322 }
323 return NULL;
324}
325
326/*
327 * Reads the interrupt pin to determine if interrupt is use by card.
328 * If the interrupt is used, then gets the interrupt line from the
329 * openfirmware and sets it in the pci_dev and pci_config line.
330 */
331static int pci_read_irq_line(struct pci_dev *pci_dev)
332{
333 struct of_phandle_args oirq;
334 unsigned int virq;
335
336 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
337
338#ifdef DEBUG
339 memset(&oirq, 0xff, sizeof(oirq));
340#endif
341 /* Try to get a mapping from the device-tree */
342 if (of_irq_parse_pci(pci_dev, &oirq)) {
343 u8 line, pin;
344
345 /* If that fails, lets fallback to what is in the config
346 * space and map that through the default controller. We
347 * also set the type to level low since that's what PCI
348 * interrupts are. If your platform does differently, then
349 * either provide a proper interrupt tree or don't use this
350 * function.
351 */
352 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
353 return -1;
354 if (pin == 0)
355 return -1;
356 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
357 line == 0xff || line == 0) {
358 return -1;
359 }
360 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
361 line, pin);
362
363 virq = irq_create_mapping(NULL, line);
364 if (virq)
365 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
366 } else {
367 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
368 oirq.args_count, oirq.args[0], oirq.args[1],
369 of_node_full_name(oirq.np));
370
371 virq = irq_create_of_mapping(&oirq);
372 }
373
374 if (!virq) {
375 pr_debug(" Failed to map !\n");
376 return -1;
377 }
378
379 pr_debug(" Mapped to linux irq %d\n", virq);
380
381 pci_dev->irq = virq;
382
383 return 0;
384}
385
386/*
387 * Platform support for /proc/bus/pci/X/Y mmap()s,
388 * modelled on the sparc64 implementation by Dave Miller.
389 * -- paulus.
390 */
391
392/*
393 * Adjust vm_pgoff of VMA such that it is the physical page offset
394 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
395 *
396 * Basically, the user finds the base address for his device which he wishes
397 * to mmap. They read the 32-bit value from the config space base register,
398 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
399 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
400 *
401 * Returns negative error code on failure, zero on success.
402 */
403static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
404 resource_size_t *offset,
405 enum pci_mmap_state mmap_state)
406{
407 struct pci_controller *hose = pci_bus_to_host(dev->bus);
408 unsigned long io_offset = 0;
409 int i, res_bit;
410
411 if (hose == NULL)
412 return NULL; /* should never happen */
413
414 /* If memory, add on the PCI bridge address offset */
415 if (mmap_state == pci_mmap_mem) {
416#if 0 /* See comment in pci_resource_to_user() for why this is disabled */
417 *offset += hose->pci_mem_offset;
418#endif
419 res_bit = IORESOURCE_MEM;
420 } else {
421 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
422 *offset += io_offset;
423 res_bit = IORESOURCE_IO;
424 }
425
426 /*
427 * Check that the offset requested corresponds to one of the
428 * resources of the device.
429 */
430 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
431 struct resource *rp = &dev->resource[i];
432 int flags = rp->flags;
433
434 /* treat ROM as memory (should be already) */
435 if (i == PCI_ROM_RESOURCE)
436 flags |= IORESOURCE_MEM;
437
438 /* Active and same type? */
439 if ((flags & res_bit) == 0)
440 continue;
441
442 /* In the range of this resource? */
443 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
444 continue;
445
446 /* found it! construct the final physical address */
447 if (mmap_state == pci_mmap_io)
448 *offset += hose->io_base_phys - io_offset;
449 return rp;
450 }
451
452 return NULL;
453}
454
455/*
456 * This one is used by /dev/mem and fbdev who have no clue about the
457 * PCI device, it tries to find the PCI device first and calls the
458 * above routine
459 */
460pgprot_t pci_phys_mem_access_prot(struct file *file,
461 unsigned long pfn,
462 unsigned long size,
463 pgprot_t prot)
464{
465 struct pci_dev *pdev = NULL;
466 struct resource *found = NULL;
467 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
468 int i;
469
470 if (page_is_ram(pfn))
471 return prot;
472
473 prot = pgprot_noncached(prot);
474 for_each_pci_dev(pdev) {
475 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
476 struct resource *rp = &pdev->resource[i];
477 int flags = rp->flags;
478
479 /* Active and same type? */
480 if ((flags & IORESOURCE_MEM) == 0)
481 continue;
482 /* In the range of this resource? */
483 if (offset < (rp->start & PAGE_MASK) ||
484 offset > rp->end)
485 continue;
486 found = rp;
487 break;
488 }
489 if (found)
490 break;
491 }
492 if (found) {
493 if (found->flags & IORESOURCE_PREFETCH)
494 prot = pgprot_noncached_wc(prot);
495 pci_dev_put(pdev);
496 }
497
498 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
499 (unsigned long long)offset, pgprot_val(prot));
500
501 return prot;
502}
503
504
505/*
506 * Perform the actual remap of the pages for a PCI device mapping, as
507 * appropriate for this architecture. The region in the process to map
508 * is described by vm_start and vm_end members of VMA, the base physical
509 * address is found in vm_pgoff.
510 * The pci device structure is provided so that architectures may make mapping
511 * decisions on a per-device or per-bus basis.
512 *
513 * Returns a negative error code on failure, zero on success.
514 */
515int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
516 enum pci_mmap_state mmap_state, int write_combine)
517{
518 resource_size_t offset =
519 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
520 struct resource *rp;
521 int ret;
522
523 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
524 if (rp == NULL)
525 return -EINVAL;
526
527 vma->vm_pgoff = offset >> PAGE_SHIFT;
528 if (write_combine)
529 vma->vm_page_prot = pgprot_noncached_wc(vma->vm_page_prot);
530 else
531 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
532
533 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
534 vma->vm_end - vma->vm_start, vma->vm_page_prot);
535
536 return ret;
537}
538
539/* This provides legacy IO read access on a bus */
540int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
541{
542 unsigned long offset;
543 struct pci_controller *hose = pci_bus_to_host(bus);
544 struct resource *rp = &hose->io_resource;
545 void __iomem *addr;
546
547 /* Check if port can be supported by that bus. We only check
548 * the ranges of the PHB though, not the bus itself as the rules
549 * for forwarding legacy cycles down bridges are not our problem
550 * here. So if the host bridge supports it, we do it.
551 */
552 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
553 offset += port;
554
555 if (!(rp->flags & IORESOURCE_IO))
556 return -ENXIO;
557 if (offset < rp->start || (offset + size) > rp->end)
558 return -ENXIO;
559 addr = hose->io_base_virt + port;
560
561 switch(size) {
562 case 1:
563 *((u8 *)val) = in_8(addr);
564 return 1;
565 case 2:
566 if (port & 1)
567 return -EINVAL;
568 *((u16 *)val) = in_le16(addr);
569 return 2;
570 case 4:
571 if (port & 3)
572 return -EINVAL;
573 *((u32 *)val) = in_le32(addr);
574 return 4;
575 }
576 return -EINVAL;
577}
578
579/* This provides legacy IO write access on a bus */
580int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
581{
582 unsigned long offset;
583 struct pci_controller *hose = pci_bus_to_host(bus);
584 struct resource *rp = &hose->io_resource;
585 void __iomem *addr;
586
587 /* Check if port can be supported by that bus. We only check
588 * the ranges of the PHB though, not the bus itself as the rules
589 * for forwarding legacy cycles down bridges are not our problem
590 * here. So if the host bridge supports it, we do it.
591 */
592 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
593 offset += port;
594
595 if (!(rp->flags & IORESOURCE_IO))
596 return -ENXIO;
597 if (offset < rp->start || (offset + size) > rp->end)
598 return -ENXIO;
599 addr = hose->io_base_virt + port;
600
601 /* WARNING: The generic code is idiotic. It gets passed a pointer
602 * to what can be a 1, 2 or 4 byte quantity and always reads that
603 * as a u32, which means that we have to correct the location of
604 * the data read within those 32 bits for size 1 and 2
605 */
606 switch(size) {
607 case 1:
608 out_8(addr, val >> 24);
609 return 1;
610 case 2:
611 if (port & 1)
612 return -EINVAL;
613 out_le16(addr, val >> 16);
614 return 2;
615 case 4:
616 if (port & 3)
617 return -EINVAL;
618 out_le32(addr, val);
619 return 4;
620 }
621 return -EINVAL;
622}
623
624/* This provides legacy IO or memory mmap access on a bus */
625int pci_mmap_legacy_page_range(struct pci_bus *bus,
626 struct vm_area_struct *vma,
627 enum pci_mmap_state mmap_state)
628{
629 struct pci_controller *hose = pci_bus_to_host(bus);
630 resource_size_t offset =
631 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
632 resource_size_t size = vma->vm_end - vma->vm_start;
633 struct resource *rp;
634
635 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
636 pci_domain_nr(bus), bus->number,
637 mmap_state == pci_mmap_mem ? "MEM" : "IO",
638 (unsigned long long)offset,
639 (unsigned long long)(offset + size - 1));
640
641 if (mmap_state == pci_mmap_mem) {
642 /* Hack alert !
643 *
644 * Because X is lame and can fail starting if it gets an error trying
645 * to mmap legacy_mem (instead of just moving on without legacy memory
646 * access) we fake it here by giving it anonymous memory, effectively
647 * behaving just like /dev/zero
648 */
649 if ((offset + size) > hose->isa_mem_size) {
650 printk(KERN_DEBUG
651 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
652 current->comm, current->pid, pci_domain_nr(bus), bus->number);
653 if (vma->vm_flags & VM_SHARED)
654 return shmem_zero_setup(vma);
655 return 0;
656 }
657 offset += hose->isa_mem_phys;
658 } else {
659 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
660 unsigned long roffset = offset + io_offset;
661 rp = &hose->io_resource;
662 if (!(rp->flags & IORESOURCE_IO))
663 return -ENXIO;
664 if (roffset < rp->start || (roffset + size) > rp->end)
665 return -ENXIO;
666 offset += hose->io_base_phys;
667 }
668 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
669
670 vma->vm_pgoff = offset >> PAGE_SHIFT;
671 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
672 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
673 vma->vm_end - vma->vm_start,
674 vma->vm_page_prot);
675}
676
677void pci_resource_to_user(const struct pci_dev *dev, int bar,
678 const struct resource *rsrc,
679 resource_size_t *start, resource_size_t *end)
680{
681 struct pci_bus_region region;
682
683 if (rsrc->flags & IORESOURCE_IO) {
684 pcibios_resource_to_bus(dev->bus, ®ion,
685 (struct resource *) rsrc);
686 *start = region.start;
687 *end = region.end;
688 return;
689 }
690
691 /* We pass a CPU physical address to userland for MMIO instead of a
692 * BAR value because X is lame and expects to be able to use that
693 * to pass to /dev/mem!
694 *
695 * That means we may have 64-bit values where some apps only expect
696 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
697 */
698 *start = rsrc->start;
699 *end = rsrc->end;
700}
701
702/**
703 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
704 * @hose: newly allocated pci_controller to be setup
705 * @dev: device node of the host bridge
706 * @primary: set if primary bus (32 bits only, soon to be deprecated)
707 *
708 * This function will parse the "ranges" property of a PCI host bridge device
709 * node and setup the resource mapping of a pci controller based on its
710 * content.
711 *
712 * Life would be boring if it wasn't for a few issues that we have to deal
713 * with here:
714 *
715 * - We can only cope with one IO space range and up to 3 Memory space
716 * ranges. However, some machines (thanks Apple !) tend to split their
717 * space into lots of small contiguous ranges. So we have to coalesce.
718 *
719 * - Some busses have IO space not starting at 0, which causes trouble with
720 * the way we do our IO resource renumbering. The code somewhat deals with
721 * it for 64 bits but I would expect problems on 32 bits.
722 *
723 * - Some 32 bits platforms such as 4xx can have physical space larger than
724 * 32 bits so we need to use 64 bits values for the parsing
725 */
726void pci_process_bridge_OF_ranges(struct pci_controller *hose,
727 struct device_node *dev, int primary)
728{
729 int memno = 0;
730 struct resource *res;
731 struct of_pci_range range;
732 struct of_pci_range_parser parser;
733
734 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
735 dev->full_name, primary ? "(primary)" : "");
736
737 /* Check for ranges property */
738 if (of_pci_range_parser_init(&parser, dev))
739 return;
740
741 /* Parse it */
742 for_each_of_pci_range(&parser, &range) {
743 /* If we failed translation or got a zero-sized region
744 * (some FW try to feed us with non sensical zero sized regions
745 * such as power3 which look like some kind of attempt at exposing
746 * the VGA memory hole)
747 */
748 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
749 continue;
750
751 /* Act based on address space type */
752 res = NULL;
753 switch (range.flags & IORESOURCE_TYPE_BITS) {
754 case IORESOURCE_IO:
755 printk(KERN_INFO
756 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
757 range.cpu_addr, range.cpu_addr + range.size - 1,
758 range.pci_addr);
759
760 /* We support only one IO range */
761 if (hose->pci_io_size) {
762 printk(KERN_INFO
763 " \\--> Skipped (too many) !\n");
764 continue;
765 }
766#ifdef CONFIG_PPC32
767 /* On 32 bits, limit I/O space to 16MB */
768 if (range.size > 0x01000000)
769 range.size = 0x01000000;
770
771 /* 32 bits needs to map IOs here */
772 hose->io_base_virt = ioremap(range.cpu_addr,
773 range.size);
774
775 /* Expect trouble if pci_addr is not 0 */
776 if (primary)
777 isa_io_base =
778 (unsigned long)hose->io_base_virt;
779#endif /* CONFIG_PPC32 */
780 /* pci_io_size and io_base_phys always represent IO
781 * space starting at 0 so we factor in pci_addr
782 */
783 hose->pci_io_size = range.pci_addr + range.size;
784 hose->io_base_phys = range.cpu_addr - range.pci_addr;
785
786 /* Build resource */
787 res = &hose->io_resource;
788 range.cpu_addr = range.pci_addr;
789 break;
790 case IORESOURCE_MEM:
791 printk(KERN_INFO
792 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
793 range.cpu_addr, range.cpu_addr + range.size - 1,
794 range.pci_addr,
795 (range.pci_space & 0x40000000) ?
796 "Prefetch" : "");
797
798 /* We support only 3 memory ranges */
799 if (memno >= 3) {
800 printk(KERN_INFO
801 " \\--> Skipped (too many) !\n");
802 continue;
803 }
804 /* Handles ISA memory hole space here */
805 if (range.pci_addr == 0) {
806 if (primary || isa_mem_base == 0)
807 isa_mem_base = range.cpu_addr;
808 hose->isa_mem_phys = range.cpu_addr;
809 hose->isa_mem_size = range.size;
810 }
811
812 /* Build resource */
813 hose->mem_offset[memno] = range.cpu_addr -
814 range.pci_addr;
815 res = &hose->mem_resources[memno++];
816 break;
817 }
818 if (res != NULL) {
819 res->name = dev->full_name;
820 res->flags = range.flags;
821 res->start = range.cpu_addr;
822 res->end = range.cpu_addr + range.size - 1;
823 res->parent = res->child = res->sibling = NULL;
824 }
825 }
826}
827
828/* Decide whether to display the domain number in /proc */
829int pci_proc_domain(struct pci_bus *bus)
830{
831 struct pci_controller *hose = pci_bus_to_host(bus);
832
833 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
834 return 0;
835 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
836 return hose->global_number != 0;
837 return 1;
838}
839
840int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
841{
842 if (ppc_md.pcibios_root_bridge_prepare)
843 return ppc_md.pcibios_root_bridge_prepare(bridge);
844
845 return 0;
846}
847
848/* This header fixup will do the resource fixup for all devices as they are
849 * probed, but not for bridge ranges
850 */
851static void pcibios_fixup_resources(struct pci_dev *dev)
852{
853 struct pci_controller *hose = pci_bus_to_host(dev->bus);
854 int i;
855
856 if (!hose) {
857 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
858 pci_name(dev));
859 return;
860 }
861
862 if (dev->is_virtfn)
863 return;
864
865 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
866 struct resource *res = dev->resource + i;
867 struct pci_bus_region reg;
868 if (!res->flags)
869 continue;
870
871 /* If we're going to re-assign everything, we mark all resources
872 * as unset (and 0-base them). In addition, we mark BARs starting
873 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
874 * since in that case, we don't want to re-assign anything
875 */
876 pcibios_resource_to_bus(dev->bus, ®, res);
877 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
878 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
879 /* Only print message if not re-assigning */
880 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
881 pr_debug("PCI:%s Resource %d %pR is unassigned\n",
882 pci_name(dev), i, res);
883 res->end -= res->start;
884 res->start = 0;
885 res->flags |= IORESOURCE_UNSET;
886 continue;
887 }
888
889 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
890 }
891
892 /* Call machine specific resource fixup */
893 if (ppc_md.pcibios_fixup_resources)
894 ppc_md.pcibios_fixup_resources(dev);
895}
896DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
897
898/* This function tries to figure out if a bridge resource has been initialized
899 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
900 * things go more smoothly when it gets it right. It should covers cases such
901 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
902 */
903static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
904 struct resource *res)
905{
906 struct pci_controller *hose = pci_bus_to_host(bus);
907 struct pci_dev *dev = bus->self;
908 resource_size_t offset;
909 struct pci_bus_region region;
910 u16 command;
911 int i;
912
913 /* We don't do anything if PCI_PROBE_ONLY is set */
914 if (pci_has_flag(PCI_PROBE_ONLY))
915 return 0;
916
917 /* Job is a bit different between memory and IO */
918 if (res->flags & IORESOURCE_MEM) {
919 pcibios_resource_to_bus(dev->bus, ®ion, res);
920
921 /* If the BAR is non-0 then it's probably been initialized */
922 if (region.start != 0)
923 return 0;
924
925 /* The BAR is 0, let's check if memory decoding is enabled on
926 * the bridge. If not, we consider it unassigned
927 */
928 pci_read_config_word(dev, PCI_COMMAND, &command);
929 if ((command & PCI_COMMAND_MEMORY) == 0)
930 return 1;
931
932 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
933 * resources covers that starting address (0 then it's good enough for
934 * us for memory space)
935 */
936 for (i = 0; i < 3; i++) {
937 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
938 hose->mem_resources[i].start == hose->mem_offset[i])
939 return 0;
940 }
941
942 /* Well, it starts at 0 and we know it will collide so we may as
943 * well consider it as unassigned. That covers the Apple case.
944 */
945 return 1;
946 } else {
947 /* If the BAR is non-0, then we consider it assigned */
948 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
949 if (((res->start - offset) & 0xfffffffful) != 0)
950 return 0;
951
952 /* Here, we are a bit different than memory as typically IO space
953 * starting at low addresses -is- valid. What we do instead if that
954 * we consider as unassigned anything that doesn't have IO enabled
955 * in the PCI command register, and that's it.
956 */
957 pci_read_config_word(dev, PCI_COMMAND, &command);
958 if (command & PCI_COMMAND_IO)
959 return 0;
960
961 /* It's starting at 0 and IO is disabled in the bridge, consider
962 * it unassigned
963 */
964 return 1;
965 }
966}
967
968/* Fixup resources of a PCI<->PCI bridge */
969static void pcibios_fixup_bridge(struct pci_bus *bus)
970{
971 struct resource *res;
972 int i;
973
974 struct pci_dev *dev = bus->self;
975
976 pci_bus_for_each_resource(bus, res, i) {
977 if (!res || !res->flags)
978 continue;
979 if (i >= 3 && bus->self->transparent)
980 continue;
981
982 /* If we're going to reassign everything, we can
983 * shrink the P2P resource to have size as being
984 * of 0 in order to save space.
985 */
986 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
987 res->flags |= IORESOURCE_UNSET;
988 res->start = 0;
989 res->end = -1;
990 continue;
991 }
992
993 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
994
995 /* Try to detect uninitialized P2P bridge resources,
996 * and clear them out so they get re-assigned later
997 */
998 if (pcibios_uninitialized_bridge_resource(bus, res)) {
999 res->flags = 0;
1000 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
1001 }
1002 }
1003}
1004
1005void pcibios_setup_bus_self(struct pci_bus *bus)
1006{
1007 struct pci_controller *phb;
1008
1009 /* Fix up the bus resources for P2P bridges */
1010 if (bus->self != NULL)
1011 pcibios_fixup_bridge(bus);
1012
1013 /* Platform specific bus fixups. This is currently only used
1014 * by fsl_pci and I'm hoping to get rid of it at some point
1015 */
1016 if (ppc_md.pcibios_fixup_bus)
1017 ppc_md.pcibios_fixup_bus(bus);
1018
1019 /* Setup bus DMA mappings */
1020 phb = pci_bus_to_host(bus);
1021 if (phb->controller_ops.dma_bus_setup)
1022 phb->controller_ops.dma_bus_setup(bus);
1023}
1024
1025static void pcibios_setup_device(struct pci_dev *dev)
1026{
1027 struct pci_controller *phb;
1028 /* Fixup NUMA node as it may not be setup yet by the generic
1029 * code and is needed by the DMA init
1030 */
1031 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1032
1033 /* Hook up default DMA ops */
1034 set_dma_ops(&dev->dev, pci_dma_ops);
1035 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
1036
1037 /* Additional platform DMA/iommu setup */
1038 phb = pci_bus_to_host(dev->bus);
1039 if (phb->controller_ops.dma_dev_setup)
1040 phb->controller_ops.dma_dev_setup(dev);
1041
1042 /* Read default IRQs and fixup if necessary */
1043 pci_read_irq_line(dev);
1044 if (ppc_md.pci_irq_fixup)
1045 ppc_md.pci_irq_fixup(dev);
1046}
1047
1048int pcibios_add_device(struct pci_dev *dev)
1049{
1050 /*
1051 * We can only call pcibios_setup_device() after bus setup is complete,
1052 * since some of the platform specific DMA setup code depends on it.
1053 */
1054 if (dev->bus->is_added)
1055 pcibios_setup_device(dev);
1056
1057#ifdef CONFIG_PCI_IOV
1058 if (ppc_md.pcibios_fixup_sriov)
1059 ppc_md.pcibios_fixup_sriov(dev);
1060#endif /* CONFIG_PCI_IOV */
1061
1062 return 0;
1063}
1064
1065void pcibios_setup_bus_devices(struct pci_bus *bus)
1066{
1067 struct pci_dev *dev;
1068
1069 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1070 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1071
1072 list_for_each_entry(dev, &bus->devices, bus_list) {
1073 /* Cardbus can call us to add new devices to a bus, so ignore
1074 * those who are already fully discovered
1075 */
1076 if (dev->is_added)
1077 continue;
1078
1079 pcibios_setup_device(dev);
1080 }
1081}
1082
1083void pcibios_set_master(struct pci_dev *dev)
1084{
1085 /* No special bus mastering setup handling */
1086}
1087
1088void pcibios_fixup_bus(struct pci_bus *bus)
1089{
1090 /* When called from the generic PCI probe, read PCI<->PCI bridge
1091 * bases. This is -not- called when generating the PCI tree from
1092 * the OF device-tree.
1093 */
1094 pci_read_bridge_bases(bus);
1095
1096 /* Now fixup the bus bus */
1097 pcibios_setup_bus_self(bus);
1098
1099 /* Now fixup devices on that bus */
1100 pcibios_setup_bus_devices(bus);
1101}
1102EXPORT_SYMBOL(pcibios_fixup_bus);
1103
1104void pci_fixup_cardbus(struct pci_bus *bus)
1105{
1106 /* Now fixup devices on that bus */
1107 pcibios_setup_bus_devices(bus);
1108}
1109
1110
1111static int skip_isa_ioresource_align(struct pci_dev *dev)
1112{
1113 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1114 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1115 return 1;
1116 return 0;
1117}
1118
1119/*
1120 * We need to avoid collisions with `mirrored' VGA ports
1121 * and other strange ISA hardware, so we always want the
1122 * addresses to be allocated in the 0x000-0x0ff region
1123 * modulo 0x400.
1124 *
1125 * Why? Because some silly external IO cards only decode
1126 * the low 10 bits of the IO address. The 0x00-0xff region
1127 * is reserved for motherboard devices that decode all 16
1128 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1129 * but we want to try to avoid allocating at 0x2900-0x2bff
1130 * which might have be mirrored at 0x0100-0x03ff..
1131 */
1132resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1133 resource_size_t size, resource_size_t align)
1134{
1135 struct pci_dev *dev = data;
1136 resource_size_t start = res->start;
1137
1138 if (res->flags & IORESOURCE_IO) {
1139 if (skip_isa_ioresource_align(dev))
1140 return start;
1141 if (start & 0x300)
1142 start = (start + 0x3ff) & ~0x3ff;
1143 }
1144
1145 return start;
1146}
1147EXPORT_SYMBOL(pcibios_align_resource);
1148
1149/*
1150 * Reparent resource children of pr that conflict with res
1151 * under res, and make res replace those children.
1152 */
1153static int reparent_resources(struct resource *parent,
1154 struct resource *res)
1155{
1156 struct resource *p, **pp;
1157 struct resource **firstpp = NULL;
1158
1159 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1160 if (p->end < res->start)
1161 continue;
1162 if (res->end < p->start)
1163 break;
1164 if (p->start < res->start || p->end > res->end)
1165 return -1; /* not completely contained */
1166 if (firstpp == NULL)
1167 firstpp = pp;
1168 }
1169 if (firstpp == NULL)
1170 return -1; /* didn't find any conflicting entries? */
1171 res->parent = parent;
1172 res->child = *firstpp;
1173 res->sibling = *pp;
1174 *firstpp = res;
1175 *pp = NULL;
1176 for (p = res->child; p != NULL; p = p->sibling) {
1177 p->parent = res;
1178 pr_debug("PCI: Reparented %s %pR under %s\n",
1179 p->name, p, res->name);
1180 }
1181 return 0;
1182}
1183
1184/*
1185 * Handle resources of PCI devices. If the world were perfect, we could
1186 * just allocate all the resource regions and do nothing more. It isn't.
1187 * On the other hand, we cannot just re-allocate all devices, as it would
1188 * require us to know lots of host bridge internals. So we attempt to
1189 * keep as much of the original configuration as possible, but tweak it
1190 * when it's found to be wrong.
1191 *
1192 * Known BIOS problems we have to work around:
1193 * - I/O or memory regions not configured
1194 * - regions configured, but not enabled in the command register
1195 * - bogus I/O addresses above 64K used
1196 * - expansion ROMs left enabled (this may sound harmless, but given
1197 * the fact the PCI specs explicitly allow address decoders to be
1198 * shared between expansion ROMs and other resource regions, it's
1199 * at least dangerous)
1200 *
1201 * Our solution:
1202 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1203 * This gives us fixed barriers on where we can allocate.
1204 * (2) Allocate resources for all enabled devices. If there is
1205 * a collision, just mark the resource as unallocated. Also
1206 * disable expansion ROMs during this step.
1207 * (3) Try to allocate resources for disabled devices. If the
1208 * resources were assigned correctly, everything goes well,
1209 * if they weren't, they won't disturb allocation of other
1210 * resources.
1211 * (4) Assign new addresses to resources which were either
1212 * not configured at all or misconfigured. If explicitly
1213 * requested by the user, configure expansion ROM address
1214 * as well.
1215 */
1216
1217static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1218{
1219 struct pci_bus *b;
1220 int i;
1221 struct resource *res, *pr;
1222
1223 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1224 pci_domain_nr(bus), bus->number);
1225
1226 pci_bus_for_each_resource(bus, res, i) {
1227 if (!res || !res->flags || res->start > res->end || res->parent)
1228 continue;
1229
1230 /* If the resource was left unset at this point, we clear it */
1231 if (res->flags & IORESOURCE_UNSET)
1232 goto clear_resource;
1233
1234 if (bus->parent == NULL)
1235 pr = (res->flags & IORESOURCE_IO) ?
1236 &ioport_resource : &iomem_resource;
1237 else {
1238 pr = pci_find_parent_resource(bus->self, res);
1239 if (pr == res) {
1240 /* this happens when the generic PCI
1241 * code (wrongly) decides that this
1242 * bridge is transparent -- paulus
1243 */
1244 continue;
1245 }
1246 }
1247
1248 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1249 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1250 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1251
1252 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1253 struct pci_dev *dev = bus->self;
1254
1255 if (request_resource(pr, res) == 0)
1256 continue;
1257 /*
1258 * Must be a conflict with an existing entry.
1259 * Move that entry (or entries) under the
1260 * bridge resource and try again.
1261 */
1262 if (reparent_resources(pr, res) == 0)
1263 continue;
1264
1265 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1266 pci_claim_bridge_resource(dev,
1267 i + PCI_BRIDGE_RESOURCES) == 0)
1268 continue;
1269 }
1270 pr_warning("PCI: Cannot allocate resource region "
1271 "%d of PCI bridge %d, will remap\n", i, bus->number);
1272 clear_resource:
1273 /* The resource might be figured out when doing
1274 * reassignment based on the resources required
1275 * by the downstream PCI devices. Here we set
1276 * the size of the resource to be 0 in order to
1277 * save more space.
1278 */
1279 res->start = 0;
1280 res->end = -1;
1281 res->flags = 0;
1282 }
1283
1284 list_for_each_entry(b, &bus->children, node)
1285 pcibios_allocate_bus_resources(b);
1286}
1287
1288static inline void alloc_resource(struct pci_dev *dev, int idx)
1289{
1290 struct resource *pr, *r = &dev->resource[idx];
1291
1292 pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1293 pci_name(dev), idx, r);
1294
1295 pr = pci_find_parent_resource(dev, r);
1296 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1297 request_resource(pr, r) < 0) {
1298 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1299 " of device %s, will remap\n", idx, pci_name(dev));
1300 if (pr)
1301 pr_debug("PCI: parent is %p: %pR\n", pr, pr);
1302 /* We'll assign a new address later */
1303 r->flags |= IORESOURCE_UNSET;
1304 r->end -= r->start;
1305 r->start = 0;
1306 }
1307}
1308
1309static void __init pcibios_allocate_resources(int pass)
1310{
1311 struct pci_dev *dev = NULL;
1312 int idx, disabled;
1313 u16 command;
1314 struct resource *r;
1315
1316 for_each_pci_dev(dev) {
1317 pci_read_config_word(dev, PCI_COMMAND, &command);
1318 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1319 r = &dev->resource[idx];
1320 if (r->parent) /* Already allocated */
1321 continue;
1322 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1323 continue; /* Not assigned at all */
1324 /* We only allocate ROMs on pass 1 just in case they
1325 * have been screwed up by firmware
1326 */
1327 if (idx == PCI_ROM_RESOURCE )
1328 disabled = 1;
1329 if (r->flags & IORESOURCE_IO)
1330 disabled = !(command & PCI_COMMAND_IO);
1331 else
1332 disabled = !(command & PCI_COMMAND_MEMORY);
1333 if (pass == disabled)
1334 alloc_resource(dev, idx);
1335 }
1336 if (pass)
1337 continue;
1338 r = &dev->resource[PCI_ROM_RESOURCE];
1339 if (r->flags) {
1340 /* Turn the ROM off, leave the resource region,
1341 * but keep it unregistered.
1342 */
1343 u32 reg;
1344 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1345 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1346 pr_debug("PCI: Switching off ROM of %s\n",
1347 pci_name(dev));
1348 r->flags &= ~IORESOURCE_ROM_ENABLE;
1349 pci_write_config_dword(dev, dev->rom_base_reg,
1350 reg & ~PCI_ROM_ADDRESS_ENABLE);
1351 }
1352 }
1353 }
1354}
1355
1356static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1357{
1358 struct pci_controller *hose = pci_bus_to_host(bus);
1359 resource_size_t offset;
1360 struct resource *res, *pres;
1361 int i;
1362
1363 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1364
1365 /* Check for IO */
1366 if (!(hose->io_resource.flags & IORESOURCE_IO))
1367 goto no_io;
1368 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1369 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1370 BUG_ON(res == NULL);
1371 res->name = "Legacy IO";
1372 res->flags = IORESOURCE_IO;
1373 res->start = offset;
1374 res->end = (offset + 0xfff) & 0xfffffffful;
1375 pr_debug("Candidate legacy IO: %pR\n", res);
1376 if (request_resource(&hose->io_resource, res)) {
1377 printk(KERN_DEBUG
1378 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1379 pci_domain_nr(bus), bus->number, res);
1380 kfree(res);
1381 }
1382
1383 no_io:
1384 /* Check for memory */
1385 for (i = 0; i < 3; i++) {
1386 pres = &hose->mem_resources[i];
1387 offset = hose->mem_offset[i];
1388 if (!(pres->flags & IORESOURCE_MEM))
1389 continue;
1390 pr_debug("hose mem res: %pR\n", pres);
1391 if ((pres->start - offset) <= 0xa0000 &&
1392 (pres->end - offset) >= 0xbffff)
1393 break;
1394 }
1395 if (i >= 3)
1396 return;
1397 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1398 BUG_ON(res == NULL);
1399 res->name = "Legacy VGA memory";
1400 res->flags = IORESOURCE_MEM;
1401 res->start = 0xa0000 + offset;
1402 res->end = 0xbffff + offset;
1403 pr_debug("Candidate VGA memory: %pR\n", res);
1404 if (request_resource(pres, res)) {
1405 printk(KERN_DEBUG
1406 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1407 pci_domain_nr(bus), bus->number, res);
1408 kfree(res);
1409 }
1410}
1411
1412void __init pcibios_resource_survey(void)
1413{
1414 struct pci_bus *b;
1415
1416 /* Allocate and assign resources */
1417 list_for_each_entry(b, &pci_root_buses, node)
1418 pcibios_allocate_bus_resources(b);
1419 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1420 pcibios_allocate_resources(0);
1421 pcibios_allocate_resources(1);
1422 }
1423
1424 /* Before we start assigning unassigned resource, we try to reserve
1425 * the low IO area and the VGA memory area if they intersect the
1426 * bus available resources to avoid allocating things on top of them
1427 */
1428 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1429 list_for_each_entry(b, &pci_root_buses, node)
1430 pcibios_reserve_legacy_regions(b);
1431 }
1432
1433 /* Now, if the platform didn't decide to blindly trust the firmware,
1434 * we proceed to assigning things that were left unassigned
1435 */
1436 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1437 pr_debug("PCI: Assigning unassigned resources...\n");
1438 pci_assign_unassigned_resources();
1439 }
1440
1441 /* Call machine dependent fixup */
1442 if (ppc_md.pcibios_fixup)
1443 ppc_md.pcibios_fixup();
1444}
1445
1446/* This is used by the PCI hotplug driver to allocate resource
1447 * of newly plugged busses. We can try to consolidate with the
1448 * rest of the code later, for now, keep it as-is as our main
1449 * resource allocation function doesn't deal with sub-trees yet.
1450 */
1451void pcibios_claim_one_bus(struct pci_bus *bus)
1452{
1453 struct pci_dev *dev;
1454 struct pci_bus *child_bus;
1455
1456 list_for_each_entry(dev, &bus->devices, bus_list) {
1457 int i;
1458
1459 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1460 struct resource *r = &dev->resource[i];
1461
1462 if (r->parent || !r->start || !r->flags)
1463 continue;
1464
1465 pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1466 pci_name(dev), i, r);
1467
1468 if (pci_claim_resource(dev, i) == 0)
1469 continue;
1470
1471 pci_claim_bridge_resource(dev, i);
1472 }
1473 }
1474
1475 list_for_each_entry(child_bus, &bus->children, node)
1476 pcibios_claim_one_bus(child_bus);
1477}
1478EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1479
1480
1481/* pcibios_finish_adding_to_bus
1482 *
1483 * This is to be called by the hotplug code after devices have been
1484 * added to a bus, this include calling it for a PHB that is just
1485 * being added
1486 */
1487void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1488{
1489 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1490 pci_domain_nr(bus), bus->number);
1491
1492 /* Allocate bus and devices resources */
1493 pcibios_allocate_bus_resources(bus);
1494 pcibios_claim_one_bus(bus);
1495 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1496 if (bus->self)
1497 pci_assign_unassigned_bridge_resources(bus->self);
1498 else
1499 pci_assign_unassigned_bus_resources(bus);
1500 }
1501
1502 /* Fixup EEH */
1503 eeh_add_device_tree_late(bus);
1504
1505 /* Add new devices to global lists. Register in proc, sysfs. */
1506 pci_bus_add_devices(bus);
1507
1508 /* sysfs files should only be added after devices are added */
1509 eeh_add_sysfs_files(bus);
1510}
1511EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1512
1513int pcibios_enable_device(struct pci_dev *dev, int mask)
1514{
1515 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1516
1517 if (phb->controller_ops.enable_device_hook)
1518 if (!phb->controller_ops.enable_device_hook(dev))
1519 return -EINVAL;
1520
1521 return pci_enable_resources(dev, mask);
1522}
1523
1524void pcibios_disable_device(struct pci_dev *dev)
1525{
1526 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1527
1528 if (phb->controller_ops.disable_device)
1529 phb->controller_ops.disable_device(dev);
1530}
1531
1532resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1533{
1534 return (unsigned long) hose->io_base_virt - _IO_BASE;
1535}
1536
1537static void pcibios_setup_phb_resources(struct pci_controller *hose,
1538 struct list_head *resources)
1539{
1540 struct resource *res;
1541 resource_size_t offset;
1542 int i;
1543
1544 /* Hookup PHB IO resource */
1545 res = &hose->io_resource;
1546
1547 if (!res->flags) {
1548 pr_debug("PCI: I/O resource not set for host"
1549 " bridge %s (domain %d)\n",
1550 hose->dn->full_name, hose->global_number);
1551 } else {
1552 offset = pcibios_io_space_offset(hose);
1553
1554 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
1555 res, (unsigned long long)offset);
1556 pci_add_resource_offset(resources, res, offset);
1557 }
1558
1559 /* Hookup PHB Memory resources */
1560 for (i = 0; i < 3; ++i) {
1561 res = &hose->mem_resources[i];
1562 if (!res->flags) {
1563 if (i == 0)
1564 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1565 "host bridge %s (domain %d)\n",
1566 hose->dn->full_name, hose->global_number);
1567 continue;
1568 }
1569 offset = hose->mem_offset[i];
1570
1571
1572 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1573 res, (unsigned long long)offset);
1574
1575 pci_add_resource_offset(resources, res, offset);
1576 }
1577}
1578
1579/*
1580 * Null PCI config access functions, for the case when we can't
1581 * find a hose.
1582 */
1583#define NULL_PCI_OP(rw, size, type) \
1584static int \
1585null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1586{ \
1587 return PCIBIOS_DEVICE_NOT_FOUND; \
1588}
1589
1590static int
1591null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1592 int len, u32 *val)
1593{
1594 return PCIBIOS_DEVICE_NOT_FOUND;
1595}
1596
1597static int
1598null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1599 int len, u32 val)
1600{
1601 return PCIBIOS_DEVICE_NOT_FOUND;
1602}
1603
1604static struct pci_ops null_pci_ops =
1605{
1606 .read = null_read_config,
1607 .write = null_write_config,
1608};
1609
1610/*
1611 * These functions are used early on before PCI scanning is done
1612 * and all of the pci_dev and pci_bus structures have been created.
1613 */
1614static struct pci_bus *
1615fake_pci_bus(struct pci_controller *hose, int busnr)
1616{
1617 static struct pci_bus bus;
1618
1619 if (hose == NULL) {
1620 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1621 }
1622 bus.number = busnr;
1623 bus.sysdata = hose;
1624 bus.ops = hose? hose->ops: &null_pci_ops;
1625 return &bus;
1626}
1627
1628#define EARLY_PCI_OP(rw, size, type) \
1629int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1630 int devfn, int offset, type value) \
1631{ \
1632 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1633 devfn, offset, value); \
1634}
1635
1636EARLY_PCI_OP(read, byte, u8 *)
1637EARLY_PCI_OP(read, word, u16 *)
1638EARLY_PCI_OP(read, dword, u32 *)
1639EARLY_PCI_OP(write, byte, u8)
1640EARLY_PCI_OP(write, word, u16)
1641EARLY_PCI_OP(write, dword, u32)
1642
1643int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1644 int cap)
1645{
1646 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1647}
1648
1649struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1650{
1651 struct pci_controller *hose = bus->sysdata;
1652
1653 return of_node_get(hose->dn);
1654}
1655
1656/**
1657 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1658 * @hose: Pointer to the PCI host controller instance structure
1659 */
1660void pcibios_scan_phb(struct pci_controller *hose)
1661{
1662 LIST_HEAD(resources);
1663 struct pci_bus *bus;
1664 struct device_node *node = hose->dn;
1665 int mode;
1666
1667 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1668
1669 /* Get some IO space for the new PHB */
1670 pcibios_setup_phb_io_space(hose);
1671
1672 /* Wire up PHB bus resources */
1673 pcibios_setup_phb_resources(hose, &resources);
1674
1675 hose->busn.start = hose->first_busno;
1676 hose->busn.end = hose->last_busno;
1677 hose->busn.flags = IORESOURCE_BUS;
1678 pci_add_resource(&resources, &hose->busn);
1679
1680 /* Create an empty bus for the toplevel */
1681 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1682 hose->ops, hose, &resources);
1683 if (bus == NULL) {
1684 pr_err("Failed to create bus for PCI domain %04x\n",
1685 hose->global_number);
1686 pci_free_resource_list(&resources);
1687 return;
1688 }
1689 hose->bus = bus;
1690
1691 /* Get probe mode and perform scan */
1692 mode = PCI_PROBE_NORMAL;
1693 if (node && hose->controller_ops.probe_mode)
1694 mode = hose->controller_ops.probe_mode(bus);
1695 pr_debug(" probe mode: %d\n", mode);
1696 if (mode == PCI_PROBE_DEVTREE)
1697 of_scan_bus(node, bus);
1698
1699 if (mode == PCI_PROBE_NORMAL) {
1700 pci_bus_update_busn_res_end(bus, 255);
1701 hose->last_busno = pci_scan_child_bus(bus);
1702 pci_bus_update_busn_res_end(bus, hose->last_busno);
1703 }
1704
1705 /* Platform gets a chance to do some global fixups before
1706 * we proceed to resource allocation
1707 */
1708 if (ppc_md.pcibios_fixup_phb)
1709 ppc_md.pcibios_fixup_phb(hose);
1710
1711 /* Configure PCI Express settings */
1712 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1713 struct pci_bus *child;
1714 list_for_each_entry(child, &bus->children, node)
1715 pcie_bus_configure_settings(child);
1716 }
1717}
1718EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1719
1720static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1721{
1722 int i, class = dev->class >> 8;
1723 /* When configured as agent, programing interface = 1 */
1724 int prog_if = dev->class & 0xf;
1725
1726 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1727 class == PCI_CLASS_BRIDGE_OTHER) &&
1728 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1729 (prog_if == 0) &&
1730 (dev->bus->parent == NULL)) {
1731 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1732 dev->resource[i].start = 0;
1733 dev->resource[i].end = 0;
1734 dev->resource[i].flags = 0;
1735 }
1736 }
1737}
1738DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1739DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1740
1741static void fixup_vga(struct pci_dev *pdev)
1742{
1743 u16 cmd;
1744
1745 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1746 if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device())
1747 vga_set_default_device(pdev);
1748
1749}
1750DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1751 PCI_CLASS_DISPLAY_VGA, 8, fixup_vga);