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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Cadence SPI controller driver (master mode only)
4 *
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
6 *
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/gpio/consumer.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/of_irq.h>
17#include <linux/of_address.h>
18#include <linux/platform_device.h>
19#include <linux/pm_runtime.h>
20#include <linux/spi/spi.h>
21
22/* Name of this driver */
23#define CDNS_SPI_NAME "cdns-spi"
24
25/* Register offset definitions */
26#define CDNS_SPI_CR 0x00 /* Configuration Register, RW */
27#define CDNS_SPI_ISR 0x04 /* Interrupt Status Register, RO */
28#define CDNS_SPI_IER 0x08 /* Interrupt Enable Register, WO */
29#define CDNS_SPI_IDR 0x0c /* Interrupt Disable Register, WO */
30#define CDNS_SPI_IMR 0x10 /* Interrupt Enabled Mask Register, RO */
31#define CDNS_SPI_ER 0x14 /* Enable/Disable Register, RW */
32#define CDNS_SPI_DR 0x18 /* Delay Register, RW */
33#define CDNS_SPI_TXD 0x1C /* Data Transmit Register, WO */
34#define CDNS_SPI_RXD 0x20 /* Data Receive Register, RO */
35#define CDNS_SPI_SICR 0x24 /* Slave Idle Count Register, RW */
36#define CDNS_SPI_THLD 0x28 /* Transmit FIFO Watermark Register,RW */
37
38#define SPI_AUTOSUSPEND_TIMEOUT 3000
39/*
40 * SPI Configuration Register bit Masks
41 *
42 * This register contains various control bits that affect the operation
43 * of the SPI controller
44 */
45#define CDNS_SPI_CR_MANSTRT 0x00010000 /* Manual TX Start */
46#define CDNS_SPI_CR_CPHA 0x00000004 /* Clock Phase Control */
47#define CDNS_SPI_CR_CPOL 0x00000002 /* Clock Polarity Control */
48#define CDNS_SPI_CR_SSCTRL 0x00003C00 /* Slave Select Mask */
49#define CDNS_SPI_CR_PERI_SEL 0x00000200 /* Peripheral Select Decode */
50#define CDNS_SPI_CR_BAUD_DIV 0x00000038 /* Baud Rate Divisor Mask */
51#define CDNS_SPI_CR_MSTREN 0x00000001 /* Master Enable Mask */
52#define CDNS_SPI_CR_MANSTRTEN 0x00008000 /* Manual TX Enable Mask */
53#define CDNS_SPI_CR_SSFORCE 0x00004000 /* Manual SS Enable Mask */
54#define CDNS_SPI_CR_BAUD_DIV_4 0x00000008 /* Default Baud Div Mask */
55#define CDNS_SPI_CR_DEFAULT (CDNS_SPI_CR_MSTREN | \
56 CDNS_SPI_CR_SSCTRL | \
57 CDNS_SPI_CR_SSFORCE | \
58 CDNS_SPI_CR_BAUD_DIV_4)
59
60/*
61 * SPI Configuration Register - Baud rate and slave select
62 *
63 * These are the values used in the calculation of baud rate divisor and
64 * setting the slave select.
65 */
66
67#define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
68#define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */
69#define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */
70#define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */
71#define CDNS_SPI_SS0 0x1 /* Slave Select zero */
72
73/*
74 * SPI Interrupt Registers bit Masks
75 *
76 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
77 * bit definitions.
78 */
79#define CDNS_SPI_IXR_TXOW 0x00000004 /* SPI TX FIFO Overwater */
80#define CDNS_SPI_IXR_MODF 0x00000002 /* SPI Mode Fault */
81#define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
82#define CDNS_SPI_IXR_DEFAULT (CDNS_SPI_IXR_TXOW | \
83 CDNS_SPI_IXR_MODF)
84#define CDNS_SPI_IXR_TXFULL 0x00000008 /* SPI TX Full */
85#define CDNS_SPI_IXR_ALL 0x0000007F /* SPI all interrupts */
86
87/*
88 * SPI Enable Register bit Masks
89 *
90 * This register is used to enable or disable the SPI controller
91 */
92#define CDNS_SPI_ER_ENABLE 0x00000001 /* SPI Enable Bit Mask */
93#define CDNS_SPI_ER_DISABLE 0x0 /* SPI Disable Bit Mask */
94
95/* SPI FIFO depth in bytes */
96#define CDNS_SPI_FIFO_DEPTH 128
97
98/* Default number of chip select lines */
99#define CDNS_SPI_DEFAULT_NUM_CS 4
100
101/**
102 * struct cdns_spi - This definition defines spi driver instance
103 * @regs: Virtual address of the SPI controller registers
104 * @ref_clk: Pointer to the peripheral clock
105 * @pclk: Pointer to the APB clock
106 * @speed_hz: Current SPI bus clock speed in Hz
107 * @txbuf: Pointer to the TX buffer
108 * @rxbuf: Pointer to the RX buffer
109 * @tx_bytes: Number of bytes left to transfer
110 * @rx_bytes: Number of bytes requested
111 * @dev_busy: Device busy flag
112 * @is_decoded_cs: Flag for decoder property set or not
113 */
114struct cdns_spi {
115 void __iomem *regs;
116 struct clk *ref_clk;
117 struct clk *pclk;
118 u32 speed_hz;
119 const u8 *txbuf;
120 u8 *rxbuf;
121 int tx_bytes;
122 int rx_bytes;
123 u8 dev_busy;
124 u32 is_decoded_cs;
125};
126
127/* Macros for the SPI controller read/write */
128static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
129{
130 return readl_relaxed(xspi->regs + offset);
131}
132
133static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
134{
135 writel_relaxed(val, xspi->regs + offset);
136}
137
138/**
139 * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
140 * @xspi: Pointer to the cdns_spi structure
141 *
142 * On reset the SPI controller is configured to be in master mode, baud rate
143 * divisor is set to 4, threshold value for TX FIFO not full interrupt is set
144 * to 1 and size of the word to be transferred as 8 bit.
145 * This function initializes the SPI controller to disable and clear all the
146 * interrupts, enable manual slave select and manual start, deselect all the
147 * chip select lines, and enable the SPI controller.
148 */
149static void cdns_spi_init_hw(struct cdns_spi *xspi)
150{
151 u32 ctrl_reg = CDNS_SPI_CR_DEFAULT;
152
153 if (xspi->is_decoded_cs)
154 ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
155
156 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
157 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL);
158
159 /* Clear the RX FIFO */
160 while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY)
161 cdns_spi_read(xspi, CDNS_SPI_RXD);
162
163 cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL);
164 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
165 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
166}
167
168/**
169 * cdns_spi_chipselect - Select or deselect the chip select line
170 * @spi: Pointer to the spi_device structure
171 * @is_high: Select(0) or deselect (1) the chip select line
172 */
173static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
174{
175 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
176 u32 ctrl_reg;
177
178 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
179
180 if (is_high) {
181 /* Deselect the slave */
182 ctrl_reg |= CDNS_SPI_CR_SSCTRL;
183 } else {
184 /* Select the slave */
185 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
186 if (!(xspi->is_decoded_cs))
187 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) <<
188 CDNS_SPI_SS_SHIFT) &
189 CDNS_SPI_CR_SSCTRL;
190 else
191 ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) &
192 CDNS_SPI_CR_SSCTRL;
193 }
194
195 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
196}
197
198/**
199 * cdns_spi_config_clock_mode - Sets clock polarity and phase
200 * @spi: Pointer to the spi_device structure
201 *
202 * Sets the requested clock polarity and phase.
203 */
204static void cdns_spi_config_clock_mode(struct spi_device *spi)
205{
206 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
207 u32 ctrl_reg, new_ctrl_reg;
208
209 new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
210 ctrl_reg = new_ctrl_reg;
211
212 /* Set the SPI clock phase and clock polarity */
213 new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL);
214 if (spi->mode & SPI_CPHA)
215 new_ctrl_reg |= CDNS_SPI_CR_CPHA;
216 if (spi->mode & SPI_CPOL)
217 new_ctrl_reg |= CDNS_SPI_CR_CPOL;
218
219 if (new_ctrl_reg != ctrl_reg) {
220 /*
221 * Just writing the CR register does not seem to apply the clock
222 * setting changes. This is problematic when changing the clock
223 * polarity as it will cause the SPI slave to see spurious clock
224 * transitions. To workaround the issue toggle the ER register.
225 */
226 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
227 cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg);
228 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
229 }
230}
231
232/**
233 * cdns_spi_config_clock_freq - Sets clock frequency
234 * @spi: Pointer to the spi_device structure
235 * @transfer: Pointer to the spi_transfer structure which provides
236 * information about next transfer setup parameters
237 *
238 * Sets the requested clock frequency.
239 * Note: If the requested frequency is not an exact match with what can be
240 * obtained using the prescalar value the driver sets the clock frequency which
241 * is lower than the requested frequency (maximum lower) for the transfer. If
242 * the requested frequency is higher or lower than that is supported by the SPI
243 * controller the driver will set the highest or lowest frequency supported by
244 * controller.
245 */
246static void cdns_spi_config_clock_freq(struct spi_device *spi,
247 struct spi_transfer *transfer)
248{
249 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
250 u32 ctrl_reg, baud_rate_val;
251 unsigned long frequency;
252
253 frequency = clk_get_rate(xspi->ref_clk);
254
255 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
256
257 /* Set the clock frequency */
258 if (xspi->speed_hz != transfer->speed_hz) {
259 /* first valid value is 1 */
260 baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
261 while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
262 (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
263 baud_rate_val++;
264
265 ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
266 ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
267
268 xspi->speed_hz = frequency / (2 << baud_rate_val);
269 }
270 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
271}
272
273/**
274 * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
275 * @spi: Pointer to the spi_device structure
276 * @transfer: Pointer to the spi_transfer structure which provides
277 * information about next transfer setup parameters
278 *
279 * Sets the operational mode of SPI controller for the next SPI transfer and
280 * sets the requested clock frequency.
281 *
282 * Return: Always 0
283 */
284static int cdns_spi_setup_transfer(struct spi_device *spi,
285 struct spi_transfer *transfer)
286{
287 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
288
289 cdns_spi_config_clock_freq(spi, transfer);
290
291 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
292 __func__, spi->mode, spi->bits_per_word,
293 xspi->speed_hz);
294
295 return 0;
296}
297
298/**
299 * cdns_spi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
300 * @xspi: Pointer to the cdns_spi structure
301 */
302static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi)
303{
304 unsigned long trans_cnt = 0;
305
306 while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&
307 (xspi->tx_bytes > 0)) {
308
309 /* When xspi in busy condition, bytes may send failed,
310 * then spi control did't work thoroughly, add one byte delay
311 */
312 if (cdns_spi_read(xspi, CDNS_SPI_ISR) &
313 CDNS_SPI_IXR_TXFULL)
314 udelay(10);
315
316 if (xspi->txbuf)
317 cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
318 else
319 cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
320
321 xspi->tx_bytes--;
322 trans_cnt++;
323 }
324}
325
326/**
327 * cdns_spi_irq - Interrupt service routine of the SPI controller
328 * @irq: IRQ number
329 * @dev_id: Pointer to the xspi structure
330 *
331 * This function handles TX empty and Mode Fault interrupts only.
332 * On TX empty interrupt this function reads the received data from RX FIFO and
333 * fills the TX FIFO if there is any data remaining to be transferred.
334 * On Mode Fault interrupt this function indicates that transfer is completed,
335 * the SPI subsystem will identify the error as the remaining bytes to be
336 * transferred is non-zero.
337 *
338 * Return: IRQ_HANDLED when handled; IRQ_NONE otherwise.
339 */
340static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
341{
342 struct spi_master *master = dev_id;
343 struct cdns_spi *xspi = spi_master_get_devdata(master);
344 u32 intr_status, status;
345
346 status = IRQ_NONE;
347 intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
348 cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
349
350 if (intr_status & CDNS_SPI_IXR_MODF) {
351 /* Indicate that transfer is completed, the SPI subsystem will
352 * identify the error as the remaining bytes to be
353 * transferred is non-zero
354 */
355 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT);
356 spi_finalize_current_transfer(master);
357 status = IRQ_HANDLED;
358 } else if (intr_status & CDNS_SPI_IXR_TXOW) {
359 unsigned long trans_cnt;
360
361 trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
362
363 /* Read out the data from the RX FIFO */
364 while (trans_cnt) {
365 u8 data;
366
367 data = cdns_spi_read(xspi, CDNS_SPI_RXD);
368 if (xspi->rxbuf)
369 *xspi->rxbuf++ = data;
370
371 xspi->rx_bytes--;
372 trans_cnt--;
373 }
374
375 if (xspi->tx_bytes) {
376 /* There is more data to send */
377 cdns_spi_fill_tx_fifo(xspi);
378 } else {
379 /* Transfer is completed */
380 cdns_spi_write(xspi, CDNS_SPI_IDR,
381 CDNS_SPI_IXR_DEFAULT);
382 spi_finalize_current_transfer(master);
383 }
384 status = IRQ_HANDLED;
385 }
386
387 return status;
388}
389
390static int cdns_prepare_message(struct spi_master *master,
391 struct spi_message *msg)
392{
393 cdns_spi_config_clock_mode(msg->spi);
394 return 0;
395}
396
397/**
398 * cdns_transfer_one - Initiates the SPI transfer
399 * @master: Pointer to spi_master structure
400 * @spi: Pointer to the spi_device structure
401 * @transfer: Pointer to the spi_transfer structure which provides
402 * information about next transfer parameters
403 *
404 * This function fills the TX FIFO, starts the SPI transfer and
405 * returns a positive transfer count so that core will wait for completion.
406 *
407 * Return: Number of bytes transferred in the last transfer
408 */
409static int cdns_transfer_one(struct spi_master *master,
410 struct spi_device *spi,
411 struct spi_transfer *transfer)
412{
413 struct cdns_spi *xspi = spi_master_get_devdata(master);
414
415 xspi->txbuf = transfer->tx_buf;
416 xspi->rxbuf = transfer->rx_buf;
417 xspi->tx_bytes = transfer->len;
418 xspi->rx_bytes = transfer->len;
419
420 cdns_spi_setup_transfer(spi, transfer);
421
422 cdns_spi_fill_tx_fifo(xspi);
423
424 cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
425 return transfer->len;
426}
427
428/**
429 * cdns_prepare_transfer_hardware - Prepares hardware for transfer.
430 * @master: Pointer to the spi_master structure which provides
431 * information about the controller.
432 *
433 * This function enables SPI master controller.
434 *
435 * Return: 0 always
436 */
437static int cdns_prepare_transfer_hardware(struct spi_master *master)
438{
439 struct cdns_spi *xspi = spi_master_get_devdata(master);
440
441 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
442
443 return 0;
444}
445
446/**
447 * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
448 * @master: Pointer to the spi_master structure which provides
449 * information about the controller.
450 *
451 * This function disables the SPI master controller.
452 *
453 * Return: 0 always
454 */
455static int cdns_unprepare_transfer_hardware(struct spi_master *master)
456{
457 struct cdns_spi *xspi = spi_master_get_devdata(master);
458
459 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
460
461 return 0;
462}
463
464/**
465 * cdns_spi_probe - Probe method for the SPI driver
466 * @pdev: Pointer to the platform_device structure
467 *
468 * This function initializes the driver data structures and the hardware.
469 *
470 * Return: 0 on success and error value on error
471 */
472static int cdns_spi_probe(struct platform_device *pdev)
473{
474 int ret = 0, irq;
475 struct spi_master *master;
476 struct cdns_spi *xspi;
477 u32 num_cs;
478
479 master = spi_alloc_master(&pdev->dev, sizeof(*xspi));
480 if (!master)
481 return -ENOMEM;
482
483 xspi = spi_master_get_devdata(master);
484 master->dev.of_node = pdev->dev.of_node;
485 platform_set_drvdata(pdev, master);
486
487 xspi->regs = devm_platform_ioremap_resource(pdev, 0);
488 if (IS_ERR(xspi->regs)) {
489 ret = PTR_ERR(xspi->regs);
490 goto remove_master;
491 }
492
493 xspi->pclk = devm_clk_get(&pdev->dev, "pclk");
494 if (IS_ERR(xspi->pclk)) {
495 dev_err(&pdev->dev, "pclk clock not found.\n");
496 ret = PTR_ERR(xspi->pclk);
497 goto remove_master;
498 }
499
500 xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
501 if (IS_ERR(xspi->ref_clk)) {
502 dev_err(&pdev->dev, "ref_clk clock not found.\n");
503 ret = PTR_ERR(xspi->ref_clk);
504 goto remove_master;
505 }
506
507 ret = clk_prepare_enable(xspi->pclk);
508 if (ret) {
509 dev_err(&pdev->dev, "Unable to enable APB clock.\n");
510 goto remove_master;
511 }
512
513 ret = clk_prepare_enable(xspi->ref_clk);
514 if (ret) {
515 dev_err(&pdev->dev, "Unable to enable device clock.\n");
516 goto clk_dis_apb;
517 }
518
519 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
520 if (ret < 0)
521 master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
522 else
523 master->num_chipselect = num_cs;
524
525 ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
526 &xspi->is_decoded_cs);
527 if (ret < 0)
528 xspi->is_decoded_cs = 0;
529
530 /* SPI controller initializations */
531 cdns_spi_init_hw(xspi);
532
533 pm_runtime_set_active(&pdev->dev);
534 pm_runtime_enable(&pdev->dev);
535 pm_runtime_use_autosuspend(&pdev->dev);
536 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
537
538 irq = platform_get_irq(pdev, 0);
539 if (irq <= 0) {
540 ret = -ENXIO;
541 goto clk_dis_all;
542 }
543
544 ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
545 0, pdev->name, master);
546 if (ret != 0) {
547 ret = -ENXIO;
548 dev_err(&pdev->dev, "request_irq failed\n");
549 goto clk_dis_all;
550 }
551
552 master->use_gpio_descriptors = true;
553 master->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
554 master->prepare_message = cdns_prepare_message;
555 master->transfer_one = cdns_transfer_one;
556 master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
557 master->set_cs = cdns_spi_chipselect;
558 master->auto_runtime_pm = true;
559 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
560
561 /* Set to default valid value */
562 master->max_speed_hz = clk_get_rate(xspi->ref_clk) / 4;
563 xspi->speed_hz = master->max_speed_hz;
564
565 master->bits_per_word_mask = SPI_BPW_MASK(8);
566
567 ret = spi_register_master(master);
568 if (ret) {
569 dev_err(&pdev->dev, "spi_register_master failed\n");
570 goto clk_dis_all;
571 }
572
573 return ret;
574
575clk_dis_all:
576 pm_runtime_set_suspended(&pdev->dev);
577 pm_runtime_disable(&pdev->dev);
578 clk_disable_unprepare(xspi->ref_clk);
579clk_dis_apb:
580 clk_disable_unprepare(xspi->pclk);
581remove_master:
582 spi_master_put(master);
583 return ret;
584}
585
586/**
587 * cdns_spi_remove - Remove method for the SPI driver
588 * @pdev: Pointer to the platform_device structure
589 *
590 * This function is called if a device is physically removed from the system or
591 * if the driver module is being unloaded. It frees all resources allocated to
592 * the device.
593 *
594 * Return: 0 on success and error value on error
595 */
596static int cdns_spi_remove(struct platform_device *pdev)
597{
598 struct spi_master *master = platform_get_drvdata(pdev);
599 struct cdns_spi *xspi = spi_master_get_devdata(master);
600
601 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
602
603 clk_disable_unprepare(xspi->ref_clk);
604 clk_disable_unprepare(xspi->pclk);
605 pm_runtime_set_suspended(&pdev->dev);
606 pm_runtime_disable(&pdev->dev);
607
608 spi_unregister_master(master);
609
610 return 0;
611}
612
613/**
614 * cdns_spi_suspend - Suspend method for the SPI driver
615 * @dev: Address of the platform_device structure
616 *
617 * This function disables the SPI controller and
618 * changes the driver state to "suspend"
619 *
620 * Return: 0 on success and error value on error
621 */
622static int __maybe_unused cdns_spi_suspend(struct device *dev)
623{
624 struct spi_master *master = dev_get_drvdata(dev);
625
626 return spi_master_suspend(master);
627}
628
629/**
630 * cdns_spi_resume - Resume method for the SPI driver
631 * @dev: Address of the platform_device structure
632 *
633 * This function changes the driver state to "ready"
634 *
635 * Return: 0 on success and error value on error
636 */
637static int __maybe_unused cdns_spi_resume(struct device *dev)
638{
639 struct spi_master *master = dev_get_drvdata(dev);
640 struct cdns_spi *xspi = spi_master_get_devdata(master);
641
642 cdns_spi_init_hw(xspi);
643 return spi_master_resume(master);
644}
645
646/**
647 * cdns_spi_runtime_resume - Runtime resume method for the SPI driver
648 * @dev: Address of the platform_device structure
649 *
650 * This function enables the clocks
651 *
652 * Return: 0 on success and error value on error
653 */
654static int __maybe_unused cnds_runtime_resume(struct device *dev)
655{
656 struct spi_master *master = dev_get_drvdata(dev);
657 struct cdns_spi *xspi = spi_master_get_devdata(master);
658 int ret;
659
660 ret = clk_prepare_enable(xspi->pclk);
661 if (ret) {
662 dev_err(dev, "Cannot enable APB clock.\n");
663 return ret;
664 }
665
666 ret = clk_prepare_enable(xspi->ref_clk);
667 if (ret) {
668 dev_err(dev, "Cannot enable device clock.\n");
669 clk_disable_unprepare(xspi->pclk);
670 return ret;
671 }
672 return 0;
673}
674
675/**
676 * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver
677 * @dev: Address of the platform_device structure
678 *
679 * This function disables the clocks
680 *
681 * Return: Always 0
682 */
683static int __maybe_unused cnds_runtime_suspend(struct device *dev)
684{
685 struct spi_master *master = dev_get_drvdata(dev);
686 struct cdns_spi *xspi = spi_master_get_devdata(master);
687
688 clk_disable_unprepare(xspi->ref_clk);
689 clk_disable_unprepare(xspi->pclk);
690
691 return 0;
692}
693
694static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
695 SET_RUNTIME_PM_OPS(cnds_runtime_suspend,
696 cnds_runtime_resume, NULL)
697 SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume)
698};
699
700static const struct of_device_id cdns_spi_of_match[] = {
701 { .compatible = "xlnx,zynq-spi-r1p6" },
702 { .compatible = "cdns,spi-r1p6" },
703 { /* end of table */ }
704};
705MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
706
707/* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
708static struct platform_driver cdns_spi_driver = {
709 .probe = cdns_spi_probe,
710 .remove = cdns_spi_remove,
711 .driver = {
712 .name = CDNS_SPI_NAME,
713 .of_match_table = cdns_spi_of_match,
714 .pm = &cdns_spi_dev_pm_ops,
715 },
716};
717
718module_platform_driver(cdns_spi_driver);
719
720MODULE_AUTHOR("Xilinx, Inc.");
721MODULE_DESCRIPTION("Cadence SPI driver");
722MODULE_LICENSE("GPL");
1/*
2 * Cadence SPI controller driver (master mode only)
3 *
4 * Copyright (C) 2008 - 2014 Xilinx, Inc.
5 *
6 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
7 *
8 * This program is free software; you can redistribute it and/or modify it under
9 * the terms of the GNU General Public License version 2 as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/of_irq.h>
20#include <linux/of_address.h>
21#include <linux/platform_device.h>
22#include <linux/spi/spi.h>
23
24/* Name of this driver */
25#define CDNS_SPI_NAME "cdns-spi"
26
27/* Register offset definitions */
28#define CDNS_SPI_CR_OFFSET 0x00 /* Configuration Register, RW */
29#define CDNS_SPI_ISR_OFFSET 0x04 /* Interrupt Status Register, RO */
30#define CDNS_SPI_IER_OFFSET 0x08 /* Interrupt Enable Register, WO */
31#define CDNS_SPI_IDR_OFFSET 0x0c /* Interrupt Disable Register, WO */
32#define CDNS_SPI_IMR_OFFSET 0x10 /* Interrupt Enabled Mask Register, RO */
33#define CDNS_SPI_ER_OFFSET 0x14 /* Enable/Disable Register, RW */
34#define CDNS_SPI_DR_OFFSET 0x18 /* Delay Register, RW */
35#define CDNS_SPI_TXD_OFFSET 0x1C /* Data Transmit Register, WO */
36#define CDNS_SPI_RXD_OFFSET 0x20 /* Data Receive Register, RO */
37#define CDNS_SPI_SICR_OFFSET 0x24 /* Slave Idle Count Register, RW */
38#define CDNS_SPI_THLD_OFFSET 0x28 /* Transmit FIFO Watermark Register,RW */
39
40/*
41 * SPI Configuration Register bit Masks
42 *
43 * This register contains various control bits that affect the operation
44 * of the SPI controller
45 */
46#define CDNS_SPI_CR_MANSTRT_MASK 0x00010000 /* Manual TX Start */
47#define CDNS_SPI_CR_CPHA_MASK 0x00000004 /* Clock Phase Control */
48#define CDNS_SPI_CR_CPOL_MASK 0x00000002 /* Clock Polarity Control */
49#define CDNS_SPI_CR_SSCTRL_MASK 0x00003C00 /* Slave Select Mask */
50#define CDNS_SPI_CR_PERI_SEL_MASK 0x00000200 /* Peripheral Select Decode */
51#define CDNS_SPI_CR_BAUD_DIV_MASK 0x00000038 /* Baud Rate Divisor Mask */
52#define CDNS_SPI_CR_MSTREN_MASK 0x00000001 /* Master Enable Mask */
53#define CDNS_SPI_CR_MANSTRTEN_MASK 0x00008000 /* Manual TX Enable Mask */
54#define CDNS_SPI_CR_SSFORCE_MASK 0x00004000 /* Manual SS Enable Mask */
55#define CDNS_SPI_CR_BAUD_DIV_4_MASK 0x00000008 /* Default Baud Div Mask */
56#define CDNS_SPI_CR_DEFAULT_MASK (CDNS_SPI_CR_MSTREN_MASK | \
57 CDNS_SPI_CR_SSCTRL_MASK | \
58 CDNS_SPI_CR_SSFORCE_MASK | \
59 CDNS_SPI_CR_BAUD_DIV_4_MASK)
60
61/*
62 * SPI Configuration Register - Baud rate and slave select
63 *
64 * These are the values used in the calculation of baud rate divisor and
65 * setting the slave select.
66 */
67
68#define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
69#define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */
70#define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */
71#define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */
72#define CDNS_SPI_SS0 0x1 /* Slave Select zero */
73
74/*
75 * SPI Interrupt Registers bit Masks
76 *
77 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
78 * bit definitions.
79 */
80#define CDNS_SPI_IXR_TXOW_MASK 0x00000004 /* SPI TX FIFO Overwater */
81#define CDNS_SPI_IXR_MODF_MASK 0x00000002 /* SPI Mode Fault */
82#define CDNS_SPI_IXR_RXNEMTY_MASK 0x00000010 /* SPI RX FIFO Not Empty */
83#define CDNS_SPI_IXR_DEFAULT_MASK (CDNS_SPI_IXR_TXOW_MASK | \
84 CDNS_SPI_IXR_MODF_MASK)
85#define CDNS_SPI_IXR_TXFULL_MASK 0x00000008 /* SPI TX Full */
86#define CDNS_SPI_IXR_ALL_MASK 0x0000007F /* SPI all interrupts */
87
88/*
89 * SPI Enable Register bit Masks
90 *
91 * This register is used to enable or disable the SPI controller
92 */
93#define CDNS_SPI_ER_ENABLE_MASK 0x00000001 /* SPI Enable Bit Mask */
94#define CDNS_SPI_ER_DISABLE_MASK 0x0 /* SPI Disable Bit Mask */
95
96/* SPI FIFO depth in bytes */
97#define CDNS_SPI_FIFO_DEPTH 128
98
99/* Default number of chip select lines */
100#define CDNS_SPI_DEFAULT_NUM_CS 4
101
102/**
103 * struct cdns_spi - This definition defines spi driver instance
104 * @regs: Virtual address of the SPI controller registers
105 * @ref_clk: Pointer to the peripheral clock
106 * @pclk: Pointer to the APB clock
107 * @speed_hz: Current SPI bus clock speed in Hz
108 * @txbuf: Pointer to the TX buffer
109 * @rxbuf: Pointer to the RX buffer
110 * @tx_bytes: Number of bytes left to transfer
111 * @rx_bytes: Number of bytes requested
112 * @dev_busy: Device busy flag
113 * @is_decoded_cs: Flag for decoder property set or not
114 */
115struct cdns_spi {
116 void __iomem *regs;
117 struct clk *ref_clk;
118 struct clk *pclk;
119 u32 speed_hz;
120 const u8 *txbuf;
121 u8 *rxbuf;
122 int tx_bytes;
123 int rx_bytes;
124 u8 dev_busy;
125 u32 is_decoded_cs;
126};
127
128/* Macros for the SPI controller read/write */
129static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
130{
131 return readl_relaxed(xspi->regs + offset);
132}
133
134static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
135{
136 writel_relaxed(val, xspi->regs + offset);
137}
138
139/**
140 * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
141 * @xspi: Pointer to the cdns_spi structure
142 *
143 * On reset the SPI controller is configured to be in master mode, baud rate
144 * divisor is set to 4, threshold value for TX FIFO not full interrupt is set
145 * to 1 and size of the word to be transferred as 8 bit.
146 * This function initializes the SPI controller to disable and clear all the
147 * interrupts, enable manual slave select and manual start, deselect all the
148 * chip select lines, and enable the SPI controller.
149 */
150static void cdns_spi_init_hw(struct cdns_spi *xspi)
151{
152 u32 ctrl_reg = CDNS_SPI_CR_DEFAULT_MASK;
153
154 if (xspi->is_decoded_cs)
155 ctrl_reg |= CDNS_SPI_CR_PERI_SEL_MASK;
156
157 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
158 CDNS_SPI_ER_DISABLE_MASK);
159 cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET,
160 CDNS_SPI_IXR_ALL_MASK);
161
162 /* Clear the RX FIFO */
163 while (cdns_spi_read(xspi, CDNS_SPI_ISR_OFFSET) &
164 CDNS_SPI_IXR_RXNEMTY_MASK)
165 cdns_spi_read(xspi, CDNS_SPI_RXD_OFFSET);
166
167 cdns_spi_write(xspi, CDNS_SPI_ISR_OFFSET,
168 CDNS_SPI_IXR_ALL_MASK);
169 cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg);
170 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
171 CDNS_SPI_ER_ENABLE_MASK);
172}
173
174/**
175 * cdns_spi_chipselect - Select or deselect the chip select line
176 * @spi: Pointer to the spi_device structure
177 * @is_on: Select(0) or deselect (1) the chip select line
178 */
179static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
180{
181 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
182 u32 ctrl_reg;
183
184 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR_OFFSET);
185
186 if (is_high) {
187 /* Deselect the slave */
188 ctrl_reg |= CDNS_SPI_CR_SSCTRL_MASK;
189 } else {
190 /* Select the slave */
191 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL_MASK;
192 if (!(xspi->is_decoded_cs))
193 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) <<
194 CDNS_SPI_SS_SHIFT) &
195 CDNS_SPI_CR_SSCTRL_MASK;
196 else
197 ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) &
198 CDNS_SPI_CR_SSCTRL_MASK;
199 }
200
201 cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg);
202}
203
204/**
205 * cdns_spi_config_clock_mode - Sets clock polarity and phase
206 * @spi: Pointer to the spi_device structure
207 *
208 * Sets the requested clock polarity and phase.
209 */
210static void cdns_spi_config_clock_mode(struct spi_device *spi)
211{
212 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
213 u32 ctrl_reg, new_ctrl_reg;
214
215 new_ctrl_reg = ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR_OFFSET);
216
217 /* Set the SPI clock phase and clock polarity */
218 new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA_MASK | CDNS_SPI_CR_CPOL_MASK);
219 if (spi->mode & SPI_CPHA)
220 new_ctrl_reg |= CDNS_SPI_CR_CPHA_MASK;
221 if (spi->mode & SPI_CPOL)
222 new_ctrl_reg |= CDNS_SPI_CR_CPOL_MASK;
223
224 if (new_ctrl_reg != ctrl_reg) {
225 /*
226 * Just writing the CR register does not seem to apply the clock
227 * setting changes. This is problematic when changing the clock
228 * polarity as it will cause the SPI slave to see spurious clock
229 * transitions. To workaround the issue toggle the ER register.
230 */
231 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
232 CDNS_SPI_ER_DISABLE_MASK);
233 cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, new_ctrl_reg);
234 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
235 CDNS_SPI_ER_ENABLE_MASK);
236 }
237}
238
239/**
240 * cdns_spi_config_clock_freq - Sets clock frequency
241 * @spi: Pointer to the spi_device structure
242 * @transfer: Pointer to the spi_transfer structure which provides
243 * information about next transfer setup parameters
244 *
245 * Sets the requested clock frequency.
246 * Note: If the requested frequency is not an exact match with what can be
247 * obtained using the prescalar value the driver sets the clock frequency which
248 * is lower than the requested frequency (maximum lower) for the transfer. If
249 * the requested frequency is higher or lower than that is supported by the SPI
250 * controller the driver will set the highest or lowest frequency supported by
251 * controller.
252 */
253static void cdns_spi_config_clock_freq(struct spi_device *spi,
254 struct spi_transfer *transfer)
255{
256 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
257 u32 ctrl_reg, baud_rate_val;
258 unsigned long frequency;
259
260 frequency = clk_get_rate(xspi->ref_clk);
261
262 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR_OFFSET);
263
264 /* Set the clock frequency */
265 if (xspi->speed_hz != transfer->speed_hz) {
266 /* first valid value is 1 */
267 baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
268 while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
269 (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
270 baud_rate_val++;
271
272 ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV_MASK;
273 ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
274
275 xspi->speed_hz = frequency / (2 << baud_rate_val);
276 }
277 cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg);
278}
279
280/**
281 * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
282 * @spi: Pointer to the spi_device structure
283 * @transfer: Pointer to the spi_transfer structure which provides
284 * information about next transfer setup parameters
285 *
286 * Sets the operational mode of SPI controller for the next SPI transfer and
287 * sets the requested clock frequency.
288 *
289 * Return: Always 0
290 */
291static int cdns_spi_setup_transfer(struct spi_device *spi,
292 struct spi_transfer *transfer)
293{
294 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
295
296 cdns_spi_config_clock_freq(spi, transfer);
297
298 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
299 __func__, spi->mode, spi->bits_per_word,
300 xspi->speed_hz);
301
302 return 0;
303}
304
305/**
306 * cdns_spi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
307 * @xspi: Pointer to the cdns_spi structure
308 */
309static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi)
310{
311 unsigned long trans_cnt = 0;
312
313 while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&
314 (xspi->tx_bytes > 0)) {
315 if (xspi->txbuf)
316 cdns_spi_write(xspi, CDNS_SPI_TXD_OFFSET,
317 *xspi->txbuf++);
318 else
319 cdns_spi_write(xspi, CDNS_SPI_TXD_OFFSET, 0);
320
321 xspi->tx_bytes--;
322 trans_cnt++;
323 }
324}
325
326/**
327 * cdns_spi_irq - Interrupt service routine of the SPI controller
328 * @irq: IRQ number
329 * @dev_id: Pointer to the xspi structure
330 *
331 * This function handles TX empty and Mode Fault interrupts only.
332 * On TX empty interrupt this function reads the received data from RX FIFO and
333 * fills the TX FIFO if there is any data remaining to be transferred.
334 * On Mode Fault interrupt this function indicates that transfer is completed,
335 * the SPI subsystem will identify the error as the remaining bytes to be
336 * transferred is non-zero.
337 *
338 * Return: IRQ_HANDLED when handled; IRQ_NONE otherwise.
339 */
340static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
341{
342 struct spi_master *master = dev_id;
343 struct cdns_spi *xspi = spi_master_get_devdata(master);
344 u32 intr_status, status;
345
346 status = IRQ_NONE;
347 intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR_OFFSET);
348 cdns_spi_write(xspi, CDNS_SPI_ISR_OFFSET, intr_status);
349
350 if (intr_status & CDNS_SPI_IXR_MODF_MASK) {
351 /* Indicate that transfer is completed, the SPI subsystem will
352 * identify the error as the remaining bytes to be
353 * transferred is non-zero
354 */
355 cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET,
356 CDNS_SPI_IXR_DEFAULT_MASK);
357 spi_finalize_current_transfer(master);
358 status = IRQ_HANDLED;
359 } else if (intr_status & CDNS_SPI_IXR_TXOW_MASK) {
360 unsigned long trans_cnt;
361
362 trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
363
364 /* Read out the data from the RX FIFO */
365 while (trans_cnt) {
366 u8 data;
367
368 data = cdns_spi_read(xspi, CDNS_SPI_RXD_OFFSET);
369 if (xspi->rxbuf)
370 *xspi->rxbuf++ = data;
371
372 xspi->rx_bytes--;
373 trans_cnt--;
374 }
375
376 if (xspi->tx_bytes) {
377 /* There is more data to send */
378 cdns_spi_fill_tx_fifo(xspi);
379 } else {
380 /* Transfer is completed */
381 cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET,
382 CDNS_SPI_IXR_DEFAULT_MASK);
383 spi_finalize_current_transfer(master);
384 }
385 status = IRQ_HANDLED;
386 }
387
388 return status;
389}
390static int cdns_prepare_message(struct spi_master *master,
391 struct spi_message *msg)
392{
393 cdns_spi_config_clock_mode(msg->spi);
394 return 0;
395}
396
397/**
398 * cdns_transfer_one - Initiates the SPI transfer
399 * @master: Pointer to spi_master structure
400 * @spi: Pointer to the spi_device structure
401 * @transfer: Pointer to the spi_transfer structure which provides
402 * information about next transfer parameters
403 *
404 * This function fills the TX FIFO, starts the SPI transfer and
405 * returns a positive transfer count so that core will wait for completion.
406 *
407 * Return: Number of bytes transferred in the last transfer
408 */
409static int cdns_transfer_one(struct spi_master *master,
410 struct spi_device *spi,
411 struct spi_transfer *transfer)
412{
413 struct cdns_spi *xspi = spi_master_get_devdata(master);
414
415 xspi->txbuf = transfer->tx_buf;
416 xspi->rxbuf = transfer->rx_buf;
417 xspi->tx_bytes = transfer->len;
418 xspi->rx_bytes = transfer->len;
419
420 cdns_spi_setup_transfer(spi, transfer);
421
422 cdns_spi_fill_tx_fifo(xspi);
423
424 cdns_spi_write(xspi, CDNS_SPI_IER_OFFSET,
425 CDNS_SPI_IXR_DEFAULT_MASK);
426 return transfer->len;
427}
428
429/**
430 * cdns_prepare_transfer_hardware - Prepares hardware for transfer.
431 * @master: Pointer to the spi_master structure which provides
432 * information about the controller.
433 *
434 * This function enables SPI master controller.
435 *
436 * Return: 0 always
437 */
438static int cdns_prepare_transfer_hardware(struct spi_master *master)
439{
440 struct cdns_spi *xspi = spi_master_get_devdata(master);
441
442 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
443 CDNS_SPI_ER_ENABLE_MASK);
444
445 return 0;
446}
447
448/**
449 * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
450 * @master: Pointer to the spi_master structure which provides
451 * information about the controller.
452 *
453 * This function disables the SPI master controller.
454 *
455 * Return: 0 always
456 */
457static int cdns_unprepare_transfer_hardware(struct spi_master *master)
458{
459 struct cdns_spi *xspi = spi_master_get_devdata(master);
460
461 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
462 CDNS_SPI_ER_DISABLE_MASK);
463
464 return 0;
465}
466
467/**
468 * cdns_spi_probe - Probe method for the SPI driver
469 * @pdev: Pointer to the platform_device structure
470 *
471 * This function initializes the driver data structures and the hardware.
472 *
473 * Return: 0 on success and error value on error
474 */
475static int cdns_spi_probe(struct platform_device *pdev)
476{
477 int ret = 0, irq;
478 struct spi_master *master;
479 struct cdns_spi *xspi;
480 struct resource *res;
481 u32 num_cs;
482
483 master = spi_alloc_master(&pdev->dev, sizeof(*xspi));
484 if (master == NULL)
485 return -ENOMEM;
486
487 xspi = spi_master_get_devdata(master);
488 master->dev.of_node = pdev->dev.of_node;
489 platform_set_drvdata(pdev, master);
490
491 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
492 xspi->regs = devm_ioremap_resource(&pdev->dev, res);
493 if (IS_ERR(xspi->regs)) {
494 ret = PTR_ERR(xspi->regs);
495 goto remove_master;
496 }
497
498 xspi->pclk = devm_clk_get(&pdev->dev, "pclk");
499 if (IS_ERR(xspi->pclk)) {
500 dev_err(&pdev->dev, "pclk clock not found.\n");
501 ret = PTR_ERR(xspi->pclk);
502 goto remove_master;
503 }
504
505 xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
506 if (IS_ERR(xspi->ref_clk)) {
507 dev_err(&pdev->dev, "ref_clk clock not found.\n");
508 ret = PTR_ERR(xspi->ref_clk);
509 goto remove_master;
510 }
511
512 ret = clk_prepare_enable(xspi->pclk);
513 if (ret) {
514 dev_err(&pdev->dev, "Unable to enable APB clock.\n");
515 goto remove_master;
516 }
517
518 ret = clk_prepare_enable(xspi->ref_clk);
519 if (ret) {
520 dev_err(&pdev->dev, "Unable to enable device clock.\n");
521 goto clk_dis_apb;
522 }
523
524 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
525 if (ret < 0)
526 master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
527 else
528 master->num_chipselect = num_cs;
529
530 ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
531 &xspi->is_decoded_cs);
532 if (ret < 0)
533 xspi->is_decoded_cs = 0;
534
535 /* SPI controller initializations */
536 cdns_spi_init_hw(xspi);
537
538 irq = platform_get_irq(pdev, 0);
539 if (irq <= 0) {
540 ret = -ENXIO;
541 dev_err(&pdev->dev, "irq number is invalid\n");
542 goto remove_master;
543 }
544
545 ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
546 0, pdev->name, master);
547 if (ret != 0) {
548 ret = -ENXIO;
549 dev_err(&pdev->dev, "request_irq failed\n");
550 goto remove_master;
551 }
552
553 master->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
554 master->prepare_message = cdns_prepare_message;
555 master->transfer_one = cdns_transfer_one;
556 master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
557 master->set_cs = cdns_spi_chipselect;
558 master->mode_bits = SPI_CPOL | SPI_CPHA;
559
560 /* Set to default valid value */
561 master->max_speed_hz = clk_get_rate(xspi->ref_clk) / 4;
562 xspi->speed_hz = master->max_speed_hz;
563
564 master->bits_per_word_mask = SPI_BPW_MASK(8);
565
566 ret = spi_register_master(master);
567 if (ret) {
568 dev_err(&pdev->dev, "spi_register_master failed\n");
569 goto clk_dis_all;
570 }
571
572 return ret;
573
574clk_dis_all:
575 clk_disable_unprepare(xspi->ref_clk);
576clk_dis_apb:
577 clk_disable_unprepare(xspi->pclk);
578remove_master:
579 spi_master_put(master);
580 return ret;
581}
582
583/**
584 * cdns_spi_remove - Remove method for the SPI driver
585 * @pdev: Pointer to the platform_device structure
586 *
587 * This function is called if a device is physically removed from the system or
588 * if the driver module is being unloaded. It frees all resources allocated to
589 * the device.
590 *
591 * Return: 0 on success and error value on error
592 */
593static int cdns_spi_remove(struct platform_device *pdev)
594{
595 struct spi_master *master = platform_get_drvdata(pdev);
596 struct cdns_spi *xspi = spi_master_get_devdata(master);
597
598 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
599 CDNS_SPI_ER_DISABLE_MASK);
600
601 clk_disable_unprepare(xspi->ref_clk);
602 clk_disable_unprepare(xspi->pclk);
603
604 spi_unregister_master(master);
605
606 return 0;
607}
608
609/**
610 * cdns_spi_suspend - Suspend method for the SPI driver
611 * @dev: Address of the platform_device structure
612 *
613 * This function disables the SPI controller and
614 * changes the driver state to "suspend"
615 *
616 * Return: Always 0
617 */
618static int __maybe_unused cdns_spi_suspend(struct device *dev)
619{
620 struct platform_device *pdev = to_platform_device(dev);
621 struct spi_master *master = platform_get_drvdata(pdev);
622 struct cdns_spi *xspi = spi_master_get_devdata(master);
623
624 spi_master_suspend(master);
625
626 clk_disable_unprepare(xspi->ref_clk);
627
628 clk_disable_unprepare(xspi->pclk);
629
630 return 0;
631}
632
633/**
634 * cdns_spi_resume - Resume method for the SPI driver
635 * @dev: Address of the platform_device structure
636 *
637 * This function changes the driver state to "ready"
638 *
639 * Return: 0 on success and error value on error
640 */
641static int __maybe_unused cdns_spi_resume(struct device *dev)
642{
643 struct platform_device *pdev = to_platform_device(dev);
644 struct spi_master *master = platform_get_drvdata(pdev);
645 struct cdns_spi *xspi = spi_master_get_devdata(master);
646 int ret = 0;
647
648 ret = clk_prepare_enable(xspi->pclk);
649 if (ret) {
650 dev_err(dev, "Cannot enable APB clock.\n");
651 return ret;
652 }
653
654 ret = clk_prepare_enable(xspi->ref_clk);
655 if (ret) {
656 dev_err(dev, "Cannot enable device clock.\n");
657 clk_disable(xspi->pclk);
658 return ret;
659 }
660 spi_master_resume(master);
661
662 return 0;
663}
664
665static SIMPLE_DEV_PM_OPS(cdns_spi_dev_pm_ops, cdns_spi_suspend,
666 cdns_spi_resume);
667
668static const struct of_device_id cdns_spi_of_match[] = {
669 { .compatible = "xlnx,zynq-spi-r1p6" },
670 { .compatible = "cdns,spi-r1p6" },
671 { /* end of table */ }
672};
673MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
674
675/* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
676static struct platform_driver cdns_spi_driver = {
677 .probe = cdns_spi_probe,
678 .remove = cdns_spi_remove,
679 .driver = {
680 .name = CDNS_SPI_NAME,
681 .of_match_table = cdns_spi_of_match,
682 .pm = &cdns_spi_dev_pm_ops,
683 },
684};
685
686module_platform_driver(cdns_spi_driver);
687
688MODULE_AUTHOR("Xilinx, Inc.");
689MODULE_DESCRIPTION("Cadence SPI driver");
690MODULE_LICENSE("GPL");