Loading...
Note: File does not exist in v5.9.
1/*
2 * Copyright (C) 2010-2012 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#include <linux/mmu_notifier.h>
20#include <linux/amd-iommu.h>
21#include <linux/mm_types.h>
22#include <linux/profile.h>
23#include <linux/module.h>
24#include <linux/sched.h>
25#include <linux/iommu.h>
26#include <linux/wait.h>
27#include <linux/pci.h>
28#include <linux/gfp.h>
29
30#include "amd_iommu_types.h"
31#include "amd_iommu_proto.h"
32
33MODULE_LICENSE("GPL v2");
34MODULE_AUTHOR("Joerg Roedel <jroedel@suse.de>");
35
36#define MAX_DEVICES 0x10000
37#define PRI_QUEUE_SIZE 512
38
39struct pri_queue {
40 atomic_t inflight;
41 bool finish;
42 int status;
43};
44
45struct pasid_state {
46 struct list_head list; /* For global state-list */
47 atomic_t count; /* Reference count */
48 unsigned mmu_notifier_count; /* Counting nested mmu_notifier
49 calls */
50 struct mm_struct *mm; /* mm_struct for the faults */
51 struct mmu_notifier mn; /* mmu_notifier handle */
52 struct pri_queue pri[PRI_QUEUE_SIZE]; /* PRI tag states */
53 struct device_state *device_state; /* Link to our device_state */
54 int pasid; /* PASID index */
55 bool invalid; /* Used during setup and
56 teardown of the pasid */
57 spinlock_t lock; /* Protect pri_queues and
58 mmu_notifer_count */
59 wait_queue_head_t wq; /* To wait for count == 0 */
60};
61
62struct device_state {
63 struct list_head list;
64 u16 devid;
65 atomic_t count;
66 struct pci_dev *pdev;
67 struct pasid_state **states;
68 struct iommu_domain *domain;
69 int pasid_levels;
70 int max_pasids;
71 amd_iommu_invalid_ppr_cb inv_ppr_cb;
72 amd_iommu_invalidate_ctx inv_ctx_cb;
73 spinlock_t lock;
74 wait_queue_head_t wq;
75};
76
77struct fault {
78 struct work_struct work;
79 struct device_state *dev_state;
80 struct pasid_state *state;
81 struct mm_struct *mm;
82 u64 address;
83 u16 devid;
84 u16 pasid;
85 u16 tag;
86 u16 finish;
87 u16 flags;
88};
89
90static LIST_HEAD(state_list);
91static spinlock_t state_lock;
92
93static struct workqueue_struct *iommu_wq;
94
95static void free_pasid_states(struct device_state *dev_state);
96
97static u16 device_id(struct pci_dev *pdev)
98{
99 u16 devid;
100
101 devid = pdev->bus->number;
102 devid = (devid << 8) | pdev->devfn;
103
104 return devid;
105}
106
107static struct device_state *__get_device_state(u16 devid)
108{
109 struct device_state *dev_state;
110
111 list_for_each_entry(dev_state, &state_list, list) {
112 if (dev_state->devid == devid)
113 return dev_state;
114 }
115
116 return NULL;
117}
118
119static struct device_state *get_device_state(u16 devid)
120{
121 struct device_state *dev_state;
122 unsigned long flags;
123
124 spin_lock_irqsave(&state_lock, flags);
125 dev_state = __get_device_state(devid);
126 if (dev_state != NULL)
127 atomic_inc(&dev_state->count);
128 spin_unlock_irqrestore(&state_lock, flags);
129
130 return dev_state;
131}
132
133static void free_device_state(struct device_state *dev_state)
134{
135 struct iommu_group *group;
136
137 /*
138 * First detach device from domain - No more PRI requests will arrive
139 * from that device after it is unbound from the IOMMUv2 domain.
140 */
141 group = iommu_group_get(&dev_state->pdev->dev);
142 if (WARN_ON(!group))
143 return;
144
145 iommu_detach_group(dev_state->domain, group);
146
147 iommu_group_put(group);
148
149 /* Everything is down now, free the IOMMUv2 domain */
150 iommu_domain_free(dev_state->domain);
151
152 /* Finally get rid of the device-state */
153 kfree(dev_state);
154}
155
156static void put_device_state(struct device_state *dev_state)
157{
158 if (atomic_dec_and_test(&dev_state->count))
159 wake_up(&dev_state->wq);
160}
161
162/* Must be called under dev_state->lock */
163static struct pasid_state **__get_pasid_state_ptr(struct device_state *dev_state,
164 int pasid, bool alloc)
165{
166 struct pasid_state **root, **ptr;
167 int level, index;
168
169 level = dev_state->pasid_levels;
170 root = dev_state->states;
171
172 while (true) {
173
174 index = (pasid >> (9 * level)) & 0x1ff;
175 ptr = &root[index];
176
177 if (level == 0)
178 break;
179
180 if (*ptr == NULL) {
181 if (!alloc)
182 return NULL;
183
184 *ptr = (void *)get_zeroed_page(GFP_ATOMIC);
185 if (*ptr == NULL)
186 return NULL;
187 }
188
189 root = (struct pasid_state **)*ptr;
190 level -= 1;
191 }
192
193 return ptr;
194}
195
196static int set_pasid_state(struct device_state *dev_state,
197 struct pasid_state *pasid_state,
198 int pasid)
199{
200 struct pasid_state **ptr;
201 unsigned long flags;
202 int ret;
203
204 spin_lock_irqsave(&dev_state->lock, flags);
205 ptr = __get_pasid_state_ptr(dev_state, pasid, true);
206
207 ret = -ENOMEM;
208 if (ptr == NULL)
209 goto out_unlock;
210
211 ret = -ENOMEM;
212 if (*ptr != NULL)
213 goto out_unlock;
214
215 *ptr = pasid_state;
216
217 ret = 0;
218
219out_unlock:
220 spin_unlock_irqrestore(&dev_state->lock, flags);
221
222 return ret;
223}
224
225static void clear_pasid_state(struct device_state *dev_state, int pasid)
226{
227 struct pasid_state **ptr;
228 unsigned long flags;
229
230 spin_lock_irqsave(&dev_state->lock, flags);
231 ptr = __get_pasid_state_ptr(dev_state, pasid, true);
232
233 if (ptr == NULL)
234 goto out_unlock;
235
236 *ptr = NULL;
237
238out_unlock:
239 spin_unlock_irqrestore(&dev_state->lock, flags);
240}
241
242static struct pasid_state *get_pasid_state(struct device_state *dev_state,
243 int pasid)
244{
245 struct pasid_state **ptr, *ret = NULL;
246 unsigned long flags;
247
248 spin_lock_irqsave(&dev_state->lock, flags);
249 ptr = __get_pasid_state_ptr(dev_state, pasid, false);
250
251 if (ptr == NULL)
252 goto out_unlock;
253
254 ret = *ptr;
255 if (ret)
256 atomic_inc(&ret->count);
257
258out_unlock:
259 spin_unlock_irqrestore(&dev_state->lock, flags);
260
261 return ret;
262}
263
264static void free_pasid_state(struct pasid_state *pasid_state)
265{
266 kfree(pasid_state);
267}
268
269static void put_pasid_state(struct pasid_state *pasid_state)
270{
271 if (atomic_dec_and_test(&pasid_state->count))
272 wake_up(&pasid_state->wq);
273}
274
275static void put_pasid_state_wait(struct pasid_state *pasid_state)
276{
277 atomic_dec(&pasid_state->count);
278 wait_event(pasid_state->wq, !atomic_read(&pasid_state->count));
279 free_pasid_state(pasid_state);
280}
281
282static void unbind_pasid(struct pasid_state *pasid_state)
283{
284 struct iommu_domain *domain;
285
286 domain = pasid_state->device_state->domain;
287
288 /*
289 * Mark pasid_state as invalid, no more faults will we added to the
290 * work queue after this is visible everywhere.
291 */
292 pasid_state->invalid = true;
293
294 /* Make sure this is visible */
295 smp_wmb();
296
297 /* After this the device/pasid can't access the mm anymore */
298 amd_iommu_domain_clear_gcr3(domain, pasid_state->pasid);
299
300 /* Make sure no more pending faults are in the queue */
301 flush_workqueue(iommu_wq);
302}
303
304static void free_pasid_states_level1(struct pasid_state **tbl)
305{
306 int i;
307
308 for (i = 0; i < 512; ++i) {
309 if (tbl[i] == NULL)
310 continue;
311
312 free_page((unsigned long)tbl[i]);
313 }
314}
315
316static void free_pasid_states_level2(struct pasid_state **tbl)
317{
318 struct pasid_state **ptr;
319 int i;
320
321 for (i = 0; i < 512; ++i) {
322 if (tbl[i] == NULL)
323 continue;
324
325 ptr = (struct pasid_state **)tbl[i];
326 free_pasid_states_level1(ptr);
327 }
328}
329
330static void free_pasid_states(struct device_state *dev_state)
331{
332 struct pasid_state *pasid_state;
333 int i;
334
335 for (i = 0; i < dev_state->max_pasids; ++i) {
336 pasid_state = get_pasid_state(dev_state, i);
337 if (pasid_state == NULL)
338 continue;
339
340 put_pasid_state(pasid_state);
341
342 /*
343 * This will call the mn_release function and
344 * unbind the PASID
345 */
346 mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm);
347
348 put_pasid_state_wait(pasid_state); /* Reference taken in
349 amd_iommu_bind_pasid */
350
351 /* Drop reference taken in amd_iommu_bind_pasid */
352 put_device_state(dev_state);
353 }
354
355 if (dev_state->pasid_levels == 2)
356 free_pasid_states_level2(dev_state->states);
357 else if (dev_state->pasid_levels == 1)
358 free_pasid_states_level1(dev_state->states);
359 else
360 BUG_ON(dev_state->pasid_levels != 0);
361
362 free_page((unsigned long)dev_state->states);
363}
364
365static struct pasid_state *mn_to_state(struct mmu_notifier *mn)
366{
367 return container_of(mn, struct pasid_state, mn);
368}
369
370static void __mn_flush_page(struct mmu_notifier *mn,
371 unsigned long address)
372{
373 struct pasid_state *pasid_state;
374 struct device_state *dev_state;
375
376 pasid_state = mn_to_state(mn);
377 dev_state = pasid_state->device_state;
378
379 amd_iommu_flush_page(dev_state->domain, pasid_state->pasid, address);
380}
381
382static int mn_clear_flush_young(struct mmu_notifier *mn,
383 struct mm_struct *mm,
384 unsigned long start,
385 unsigned long end)
386{
387 for (; start < end; start += PAGE_SIZE)
388 __mn_flush_page(mn, start);
389
390 return 0;
391}
392
393static void mn_invalidate_page(struct mmu_notifier *mn,
394 struct mm_struct *mm,
395 unsigned long address)
396{
397 __mn_flush_page(mn, address);
398}
399
400static void mn_invalidate_range(struct mmu_notifier *mn,
401 struct mm_struct *mm,
402 unsigned long start, unsigned long end)
403{
404 struct pasid_state *pasid_state;
405 struct device_state *dev_state;
406
407 pasid_state = mn_to_state(mn);
408 dev_state = pasid_state->device_state;
409
410 if ((start ^ (end - 1)) < PAGE_SIZE)
411 amd_iommu_flush_page(dev_state->domain, pasid_state->pasid,
412 start);
413 else
414 amd_iommu_flush_tlb(dev_state->domain, pasid_state->pasid);
415}
416
417static void mn_release(struct mmu_notifier *mn, struct mm_struct *mm)
418{
419 struct pasid_state *pasid_state;
420 struct device_state *dev_state;
421 bool run_inv_ctx_cb;
422
423 might_sleep();
424
425 pasid_state = mn_to_state(mn);
426 dev_state = pasid_state->device_state;
427 run_inv_ctx_cb = !pasid_state->invalid;
428
429 if (run_inv_ctx_cb && dev_state->inv_ctx_cb)
430 dev_state->inv_ctx_cb(dev_state->pdev, pasid_state->pasid);
431
432 unbind_pasid(pasid_state);
433}
434
435static const struct mmu_notifier_ops iommu_mn = {
436 .release = mn_release,
437 .clear_flush_young = mn_clear_flush_young,
438 .invalidate_page = mn_invalidate_page,
439 .invalidate_range = mn_invalidate_range,
440};
441
442static void set_pri_tag_status(struct pasid_state *pasid_state,
443 u16 tag, int status)
444{
445 unsigned long flags;
446
447 spin_lock_irqsave(&pasid_state->lock, flags);
448 pasid_state->pri[tag].status = status;
449 spin_unlock_irqrestore(&pasid_state->lock, flags);
450}
451
452static void finish_pri_tag(struct device_state *dev_state,
453 struct pasid_state *pasid_state,
454 u16 tag)
455{
456 unsigned long flags;
457
458 spin_lock_irqsave(&pasid_state->lock, flags);
459 if (atomic_dec_and_test(&pasid_state->pri[tag].inflight) &&
460 pasid_state->pri[tag].finish) {
461 amd_iommu_complete_ppr(dev_state->pdev, pasid_state->pasid,
462 pasid_state->pri[tag].status, tag);
463 pasid_state->pri[tag].finish = false;
464 pasid_state->pri[tag].status = PPR_SUCCESS;
465 }
466 spin_unlock_irqrestore(&pasid_state->lock, flags);
467}
468
469static void handle_fault_error(struct fault *fault)
470{
471 int status;
472
473 if (!fault->dev_state->inv_ppr_cb) {
474 set_pri_tag_status(fault->state, fault->tag, PPR_INVALID);
475 return;
476 }
477
478 status = fault->dev_state->inv_ppr_cb(fault->dev_state->pdev,
479 fault->pasid,
480 fault->address,
481 fault->flags);
482 switch (status) {
483 case AMD_IOMMU_INV_PRI_RSP_SUCCESS:
484 set_pri_tag_status(fault->state, fault->tag, PPR_SUCCESS);
485 break;
486 case AMD_IOMMU_INV_PRI_RSP_INVALID:
487 set_pri_tag_status(fault->state, fault->tag, PPR_INVALID);
488 break;
489 case AMD_IOMMU_INV_PRI_RSP_FAIL:
490 set_pri_tag_status(fault->state, fault->tag, PPR_FAILURE);
491 break;
492 default:
493 BUG();
494 }
495}
496
497static bool access_error(struct vm_area_struct *vma, struct fault *fault)
498{
499 unsigned long requested = 0;
500
501 if (fault->flags & PPR_FAULT_EXEC)
502 requested |= VM_EXEC;
503
504 if (fault->flags & PPR_FAULT_READ)
505 requested |= VM_READ;
506
507 if (fault->flags & PPR_FAULT_WRITE)
508 requested |= VM_WRITE;
509
510 return (requested & ~vma->vm_flags) != 0;
511}
512
513static void do_fault(struct work_struct *work)
514{
515 struct fault *fault = container_of(work, struct fault, work);
516 struct vm_area_struct *vma;
517 int ret = VM_FAULT_ERROR;
518 unsigned int flags = 0;
519 struct mm_struct *mm;
520 u64 address;
521
522 mm = fault->state->mm;
523 address = fault->address;
524
525 if (fault->flags & PPR_FAULT_USER)
526 flags |= FAULT_FLAG_USER;
527 if (fault->flags & PPR_FAULT_WRITE)
528 flags |= FAULT_FLAG_WRITE;
529 flags |= FAULT_FLAG_REMOTE;
530
531 down_read(&mm->mmap_sem);
532 vma = find_extend_vma(mm, address);
533 if (!vma || address < vma->vm_start)
534 /* failed to get a vma in the right range */
535 goto out;
536
537 /* Check if we have the right permissions on the vma */
538 if (access_error(vma, fault))
539 goto out;
540
541 ret = handle_mm_fault(vma, address, flags);
542out:
543 up_read(&mm->mmap_sem);
544
545 if (ret & VM_FAULT_ERROR)
546 /* failed to service fault */
547 handle_fault_error(fault);
548
549 finish_pri_tag(fault->dev_state, fault->state, fault->tag);
550
551 put_pasid_state(fault->state);
552
553 kfree(fault);
554}
555
556static int ppr_notifier(struct notifier_block *nb, unsigned long e, void *data)
557{
558 struct amd_iommu_fault *iommu_fault;
559 struct pasid_state *pasid_state;
560 struct device_state *dev_state;
561 unsigned long flags;
562 struct fault *fault;
563 bool finish;
564 u16 tag;
565 int ret;
566
567 iommu_fault = data;
568 tag = iommu_fault->tag & 0x1ff;
569 finish = (iommu_fault->tag >> 9) & 1;
570
571 ret = NOTIFY_DONE;
572 dev_state = get_device_state(iommu_fault->device_id);
573 if (dev_state == NULL)
574 goto out;
575
576 pasid_state = get_pasid_state(dev_state, iommu_fault->pasid);
577 if (pasid_state == NULL || pasid_state->invalid) {
578 /* We know the device but not the PASID -> send INVALID */
579 amd_iommu_complete_ppr(dev_state->pdev, iommu_fault->pasid,
580 PPR_INVALID, tag);
581 goto out_drop_state;
582 }
583
584 spin_lock_irqsave(&pasid_state->lock, flags);
585 atomic_inc(&pasid_state->pri[tag].inflight);
586 if (finish)
587 pasid_state->pri[tag].finish = true;
588 spin_unlock_irqrestore(&pasid_state->lock, flags);
589
590 fault = kzalloc(sizeof(*fault), GFP_ATOMIC);
591 if (fault == NULL) {
592 /* We are OOM - send success and let the device re-fault */
593 finish_pri_tag(dev_state, pasid_state, tag);
594 goto out_drop_state;
595 }
596
597 fault->dev_state = dev_state;
598 fault->address = iommu_fault->address;
599 fault->state = pasid_state;
600 fault->tag = tag;
601 fault->finish = finish;
602 fault->pasid = iommu_fault->pasid;
603 fault->flags = iommu_fault->flags;
604 INIT_WORK(&fault->work, do_fault);
605
606 queue_work(iommu_wq, &fault->work);
607
608 ret = NOTIFY_OK;
609
610out_drop_state:
611
612 if (ret != NOTIFY_OK && pasid_state)
613 put_pasid_state(pasid_state);
614
615 put_device_state(dev_state);
616
617out:
618 return ret;
619}
620
621static struct notifier_block ppr_nb = {
622 .notifier_call = ppr_notifier,
623};
624
625int amd_iommu_bind_pasid(struct pci_dev *pdev, int pasid,
626 struct task_struct *task)
627{
628 struct pasid_state *pasid_state;
629 struct device_state *dev_state;
630 struct mm_struct *mm;
631 u16 devid;
632 int ret;
633
634 might_sleep();
635
636 if (!amd_iommu_v2_supported())
637 return -ENODEV;
638
639 devid = device_id(pdev);
640 dev_state = get_device_state(devid);
641
642 if (dev_state == NULL)
643 return -EINVAL;
644
645 ret = -EINVAL;
646 if (pasid < 0 || pasid >= dev_state->max_pasids)
647 goto out;
648
649 ret = -ENOMEM;
650 pasid_state = kzalloc(sizeof(*pasid_state), GFP_KERNEL);
651 if (pasid_state == NULL)
652 goto out;
653
654
655 atomic_set(&pasid_state->count, 1);
656 init_waitqueue_head(&pasid_state->wq);
657 spin_lock_init(&pasid_state->lock);
658
659 mm = get_task_mm(task);
660 pasid_state->mm = mm;
661 pasid_state->device_state = dev_state;
662 pasid_state->pasid = pasid;
663 pasid_state->invalid = true; /* Mark as valid only if we are
664 done with setting up the pasid */
665 pasid_state->mn.ops = &iommu_mn;
666
667 if (pasid_state->mm == NULL)
668 goto out_free;
669
670 mmu_notifier_register(&pasid_state->mn, mm);
671
672 ret = set_pasid_state(dev_state, pasid_state, pasid);
673 if (ret)
674 goto out_unregister;
675
676 ret = amd_iommu_domain_set_gcr3(dev_state->domain, pasid,
677 __pa(pasid_state->mm->pgd));
678 if (ret)
679 goto out_clear_state;
680
681 /* Now we are ready to handle faults */
682 pasid_state->invalid = false;
683
684 /*
685 * Drop the reference to the mm_struct here. We rely on the
686 * mmu_notifier release call-back to inform us when the mm
687 * is going away.
688 */
689 mmput(mm);
690
691 return 0;
692
693out_clear_state:
694 clear_pasid_state(dev_state, pasid);
695
696out_unregister:
697 mmu_notifier_unregister(&pasid_state->mn, mm);
698
699out_free:
700 mmput(mm);
701 free_pasid_state(pasid_state);
702
703out:
704 put_device_state(dev_state);
705
706 return ret;
707}
708EXPORT_SYMBOL(amd_iommu_bind_pasid);
709
710void amd_iommu_unbind_pasid(struct pci_dev *pdev, int pasid)
711{
712 struct pasid_state *pasid_state;
713 struct device_state *dev_state;
714 u16 devid;
715
716 might_sleep();
717
718 if (!amd_iommu_v2_supported())
719 return;
720
721 devid = device_id(pdev);
722 dev_state = get_device_state(devid);
723 if (dev_state == NULL)
724 return;
725
726 if (pasid < 0 || pasid >= dev_state->max_pasids)
727 goto out;
728
729 pasid_state = get_pasid_state(dev_state, pasid);
730 if (pasid_state == NULL)
731 goto out;
732 /*
733 * Drop reference taken here. We are safe because we still hold
734 * the reference taken in the amd_iommu_bind_pasid function.
735 */
736 put_pasid_state(pasid_state);
737
738 /* Clear the pasid state so that the pasid can be re-used */
739 clear_pasid_state(dev_state, pasid_state->pasid);
740
741 /*
742 * Call mmu_notifier_unregister to drop our reference
743 * to pasid_state->mm
744 */
745 mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm);
746
747 put_pasid_state_wait(pasid_state); /* Reference taken in
748 amd_iommu_bind_pasid */
749out:
750 /* Drop reference taken in this function */
751 put_device_state(dev_state);
752
753 /* Drop reference taken in amd_iommu_bind_pasid */
754 put_device_state(dev_state);
755}
756EXPORT_SYMBOL(amd_iommu_unbind_pasid);
757
758int amd_iommu_init_device(struct pci_dev *pdev, int pasids)
759{
760 struct device_state *dev_state;
761 struct iommu_group *group;
762 unsigned long flags;
763 int ret, tmp;
764 u16 devid;
765
766 might_sleep();
767
768 if (!amd_iommu_v2_supported())
769 return -ENODEV;
770
771 if (pasids <= 0 || pasids > (PASID_MASK + 1))
772 return -EINVAL;
773
774 devid = device_id(pdev);
775
776 dev_state = kzalloc(sizeof(*dev_state), GFP_KERNEL);
777 if (dev_state == NULL)
778 return -ENOMEM;
779
780 spin_lock_init(&dev_state->lock);
781 init_waitqueue_head(&dev_state->wq);
782 dev_state->pdev = pdev;
783 dev_state->devid = devid;
784
785 tmp = pasids;
786 for (dev_state->pasid_levels = 0; (tmp - 1) & ~0x1ff; tmp >>= 9)
787 dev_state->pasid_levels += 1;
788
789 atomic_set(&dev_state->count, 1);
790 dev_state->max_pasids = pasids;
791
792 ret = -ENOMEM;
793 dev_state->states = (void *)get_zeroed_page(GFP_KERNEL);
794 if (dev_state->states == NULL)
795 goto out_free_dev_state;
796
797 dev_state->domain = iommu_domain_alloc(&pci_bus_type);
798 if (dev_state->domain == NULL)
799 goto out_free_states;
800
801 amd_iommu_domain_direct_map(dev_state->domain);
802
803 ret = amd_iommu_domain_enable_v2(dev_state->domain, pasids);
804 if (ret)
805 goto out_free_domain;
806
807 group = iommu_group_get(&pdev->dev);
808 if (!group) {
809 ret = -EINVAL;
810 goto out_free_domain;
811 }
812
813 ret = iommu_attach_group(dev_state->domain, group);
814 if (ret != 0)
815 goto out_drop_group;
816
817 iommu_group_put(group);
818
819 spin_lock_irqsave(&state_lock, flags);
820
821 if (__get_device_state(devid) != NULL) {
822 spin_unlock_irqrestore(&state_lock, flags);
823 ret = -EBUSY;
824 goto out_free_domain;
825 }
826
827 list_add_tail(&dev_state->list, &state_list);
828
829 spin_unlock_irqrestore(&state_lock, flags);
830
831 return 0;
832
833out_drop_group:
834 iommu_group_put(group);
835
836out_free_domain:
837 iommu_domain_free(dev_state->domain);
838
839out_free_states:
840 free_page((unsigned long)dev_state->states);
841
842out_free_dev_state:
843 kfree(dev_state);
844
845 return ret;
846}
847EXPORT_SYMBOL(amd_iommu_init_device);
848
849void amd_iommu_free_device(struct pci_dev *pdev)
850{
851 struct device_state *dev_state;
852 unsigned long flags;
853 u16 devid;
854
855 if (!amd_iommu_v2_supported())
856 return;
857
858 devid = device_id(pdev);
859
860 spin_lock_irqsave(&state_lock, flags);
861
862 dev_state = __get_device_state(devid);
863 if (dev_state == NULL) {
864 spin_unlock_irqrestore(&state_lock, flags);
865 return;
866 }
867
868 list_del(&dev_state->list);
869
870 spin_unlock_irqrestore(&state_lock, flags);
871
872 /* Get rid of any remaining pasid states */
873 free_pasid_states(dev_state);
874
875 put_device_state(dev_state);
876 /*
877 * Wait until the last reference is dropped before freeing
878 * the device state.
879 */
880 wait_event(dev_state->wq, !atomic_read(&dev_state->count));
881 free_device_state(dev_state);
882}
883EXPORT_SYMBOL(amd_iommu_free_device);
884
885int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev,
886 amd_iommu_invalid_ppr_cb cb)
887{
888 struct device_state *dev_state;
889 unsigned long flags;
890 u16 devid;
891 int ret;
892
893 if (!amd_iommu_v2_supported())
894 return -ENODEV;
895
896 devid = device_id(pdev);
897
898 spin_lock_irqsave(&state_lock, flags);
899
900 ret = -EINVAL;
901 dev_state = __get_device_state(devid);
902 if (dev_state == NULL)
903 goto out_unlock;
904
905 dev_state->inv_ppr_cb = cb;
906
907 ret = 0;
908
909out_unlock:
910 spin_unlock_irqrestore(&state_lock, flags);
911
912 return ret;
913}
914EXPORT_SYMBOL(amd_iommu_set_invalid_ppr_cb);
915
916int amd_iommu_set_invalidate_ctx_cb(struct pci_dev *pdev,
917 amd_iommu_invalidate_ctx cb)
918{
919 struct device_state *dev_state;
920 unsigned long flags;
921 u16 devid;
922 int ret;
923
924 if (!amd_iommu_v2_supported())
925 return -ENODEV;
926
927 devid = device_id(pdev);
928
929 spin_lock_irqsave(&state_lock, flags);
930
931 ret = -EINVAL;
932 dev_state = __get_device_state(devid);
933 if (dev_state == NULL)
934 goto out_unlock;
935
936 dev_state->inv_ctx_cb = cb;
937
938 ret = 0;
939
940out_unlock:
941 spin_unlock_irqrestore(&state_lock, flags);
942
943 return ret;
944}
945EXPORT_SYMBOL(amd_iommu_set_invalidate_ctx_cb);
946
947static int __init amd_iommu_v2_init(void)
948{
949 int ret;
950
951 pr_info("AMD IOMMUv2 driver by Joerg Roedel <jroedel@suse.de>\n");
952
953 if (!amd_iommu_v2_supported()) {
954 pr_info("AMD IOMMUv2 functionality not available on this system\n");
955 /*
956 * Load anyway to provide the symbols to other modules
957 * which may use AMD IOMMUv2 optionally.
958 */
959 return 0;
960 }
961
962 spin_lock_init(&state_lock);
963
964 ret = -ENOMEM;
965 iommu_wq = alloc_workqueue("amd_iommu_v2", WQ_MEM_RECLAIM, 0);
966 if (iommu_wq == NULL)
967 goto out;
968
969 amd_iommu_register_ppr_notifier(&ppr_nb);
970
971 return 0;
972
973out:
974 return ret;
975}
976
977static void __exit amd_iommu_v2_exit(void)
978{
979 struct device_state *dev_state;
980 int i;
981
982 if (!amd_iommu_v2_supported())
983 return;
984
985 amd_iommu_unregister_ppr_notifier(&ppr_nb);
986
987 flush_workqueue(iommu_wq);
988
989 /*
990 * The loop below might call flush_workqueue(), so call
991 * destroy_workqueue() after it
992 */
993 for (i = 0; i < MAX_DEVICES; ++i) {
994 dev_state = get_device_state(i);
995
996 if (dev_state == NULL)
997 continue;
998
999 WARN_ON_ONCE(1);
1000
1001 put_device_state(dev_state);
1002 amd_iommu_free_device(dev_state->pdev);
1003 }
1004
1005 destroy_workqueue(iommu_wq);
1006}
1007
1008module_init(amd_iommu_v2_init);
1009module_exit(amd_iommu_v2_exit);