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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 */
18#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19#define SUPPORT_SYSRQ
20#endif
21
22#undef DEBUG
23
24#include <linux/clk.h>
25#include <linux/console.h>
26#include <linux/ctype.h>
27#include <linux/cpufreq.h>
28#include <linux/delay.h>
29#include <linux/dmaengine.h>
30#include <linux/dma-mapping.h>
31#include <linux/err.h>
32#include <linux/errno.h>
33#include <linux/init.h>
34#include <linux/interrupt.h>
35#include <linux/ioport.h>
36#include <linux/ktime.h>
37#include <linux/major.h>
38#include <linux/module.h>
39#include <linux/mm.h>
40#include <linux/of.h>
41#include <linux/of_device.h>
42#include <linux/platform_device.h>
43#include <linux/pm_runtime.h>
44#include <linux/scatterlist.h>
45#include <linux/serial.h>
46#include <linux/serial_sci.h>
47#include <linux/sh_dma.h>
48#include <linux/slab.h>
49#include <linux/string.h>
50#include <linux/sysrq.h>
51#include <linux/timer.h>
52#include <linux/tty.h>
53#include <linux/tty_flip.h>
54
55#ifdef CONFIG_SUPERH
56#include <asm/sh_bios.h>
57#endif
58
59#include "serial_mctrl_gpio.h"
60#include "sh-sci.h"
61
62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_DRI_IRQ,
69 SCIx_TEI_IRQ,
70 SCIx_NR_IRQS,
71
72 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
73};
74
75#define SCIx_IRQ_IS_MUXED(port) \
76 ((port)->irqs[SCIx_ERI_IRQ] == \
77 (port)->irqs[SCIx_RXI_IRQ]) || \
78 ((port)->irqs[SCIx_ERI_IRQ] && \
79 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80
81enum SCI_CLKS {
82 SCI_FCK, /* Functional Clock */
83 SCI_SCK, /* Optional External Clock */
84 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
85 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
86 SCI_NUM_CLKS
87};
88
89/* Bit x set means sampling rate x + 1 is supported */
90#define SCI_SR(x) BIT((x) - 1)
91#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
92
93#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
94 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
95 SCI_SR(19) | SCI_SR(27)
96
97#define min_sr(_port) ffs((_port)->sampling_rate_mask)
98#define max_sr(_port) fls((_port)->sampling_rate_mask)
99
100/* Iterate over all supported sampling rates, from high to low */
101#define for_each_sr(_sr, _port) \
102 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
103 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
104
105struct plat_sci_reg {
106 u8 offset, size;
107};
108
109struct sci_port_params {
110 const struct plat_sci_reg regs[SCIx_NR_REGS];
111 unsigned int fifosize;
112 unsigned int overrun_reg;
113 unsigned int overrun_mask;
114 unsigned int sampling_rate_mask;
115 unsigned int error_mask;
116 unsigned int error_clear;
117};
118
119struct sci_port {
120 struct uart_port port;
121
122 /* Platform configuration */
123 const struct sci_port_params *params;
124 const struct plat_sci_port *cfg;
125 unsigned int sampling_rate_mask;
126 resource_size_t reg_size;
127 struct mctrl_gpios *gpios;
128
129 /* Clocks */
130 struct clk *clks[SCI_NUM_CLKS];
131 unsigned long clk_rates[SCI_NUM_CLKS];
132
133 int irqs[SCIx_NR_IRQS];
134 char *irqstr[SCIx_NR_IRQS];
135
136 struct dma_chan *chan_tx;
137 struct dma_chan *chan_rx;
138
139#ifdef CONFIG_SERIAL_SH_SCI_DMA
140 struct dma_chan *chan_tx_saved;
141 struct dma_chan *chan_rx_saved;
142 dma_cookie_t cookie_tx;
143 dma_cookie_t cookie_rx[2];
144 dma_cookie_t active_rx;
145 dma_addr_t tx_dma_addr;
146 unsigned int tx_dma_len;
147 struct scatterlist sg_rx[2];
148 void *rx_buf[2];
149 size_t buf_len_rx;
150 struct work_struct work_tx;
151 struct hrtimer rx_timer;
152 unsigned int rx_timeout; /* microseconds */
153#endif
154 unsigned int rx_frame;
155 int rx_trigger;
156 struct timer_list rx_fifo_timer;
157 int rx_fifo_timeout;
158 u16 hscif_tot;
159
160 bool has_rtscts;
161 bool autorts;
162};
163
164#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
165
166static struct sci_port sci_ports[SCI_NPORTS];
167static unsigned long sci_ports_in_use;
168static struct uart_driver sci_uart_driver;
169
170static inline struct sci_port *
171to_sci_port(struct uart_port *uart)
172{
173 return container_of(uart, struct sci_port, port);
174}
175
176static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
177 /*
178 * Common SCI definitions, dependent on the port's regshift
179 * value.
180 */
181 [SCIx_SCI_REGTYPE] = {
182 .regs = {
183 [SCSMR] = { 0x00, 8 },
184 [SCBRR] = { 0x01, 8 },
185 [SCSCR] = { 0x02, 8 },
186 [SCxTDR] = { 0x03, 8 },
187 [SCxSR] = { 0x04, 8 },
188 [SCxRDR] = { 0x05, 8 },
189 },
190 .fifosize = 1,
191 .overrun_reg = SCxSR,
192 .overrun_mask = SCI_ORER,
193 .sampling_rate_mask = SCI_SR(32),
194 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
195 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
196 },
197
198 /*
199 * Common definitions for legacy IrDA ports.
200 */
201 [SCIx_IRDA_REGTYPE] = {
202 .regs = {
203 [SCSMR] = { 0x00, 8 },
204 [SCBRR] = { 0x02, 8 },
205 [SCSCR] = { 0x04, 8 },
206 [SCxTDR] = { 0x06, 8 },
207 [SCxSR] = { 0x08, 16 },
208 [SCxRDR] = { 0x0a, 8 },
209 [SCFCR] = { 0x0c, 8 },
210 [SCFDR] = { 0x0e, 16 },
211 },
212 .fifosize = 1,
213 .overrun_reg = SCxSR,
214 .overrun_mask = SCI_ORER,
215 .sampling_rate_mask = SCI_SR(32),
216 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
217 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
218 },
219
220 /*
221 * Common SCIFA definitions.
222 */
223 [SCIx_SCIFA_REGTYPE] = {
224 .regs = {
225 [SCSMR] = { 0x00, 16 },
226 [SCBRR] = { 0x04, 8 },
227 [SCSCR] = { 0x08, 16 },
228 [SCxTDR] = { 0x20, 8 },
229 [SCxSR] = { 0x14, 16 },
230 [SCxRDR] = { 0x24, 8 },
231 [SCFCR] = { 0x18, 16 },
232 [SCFDR] = { 0x1c, 16 },
233 [SCPCR] = { 0x30, 16 },
234 [SCPDR] = { 0x34, 16 },
235 },
236 .fifosize = 64,
237 .overrun_reg = SCxSR,
238 .overrun_mask = SCIFA_ORER,
239 .sampling_rate_mask = SCI_SR_SCIFAB,
240 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
241 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
242 },
243
244 /*
245 * Common SCIFB definitions.
246 */
247 [SCIx_SCIFB_REGTYPE] = {
248 .regs = {
249 [SCSMR] = { 0x00, 16 },
250 [SCBRR] = { 0x04, 8 },
251 [SCSCR] = { 0x08, 16 },
252 [SCxTDR] = { 0x40, 8 },
253 [SCxSR] = { 0x14, 16 },
254 [SCxRDR] = { 0x60, 8 },
255 [SCFCR] = { 0x18, 16 },
256 [SCTFDR] = { 0x38, 16 },
257 [SCRFDR] = { 0x3c, 16 },
258 [SCPCR] = { 0x30, 16 },
259 [SCPDR] = { 0x34, 16 },
260 },
261 .fifosize = 256,
262 .overrun_reg = SCxSR,
263 .overrun_mask = SCIFA_ORER,
264 .sampling_rate_mask = SCI_SR_SCIFAB,
265 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
266 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
267 },
268
269 /*
270 * Common SH-2(A) SCIF definitions for ports with FIFO data
271 * count registers.
272 */
273 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
274 .regs = {
275 [SCSMR] = { 0x00, 16 },
276 [SCBRR] = { 0x04, 8 },
277 [SCSCR] = { 0x08, 16 },
278 [SCxTDR] = { 0x0c, 8 },
279 [SCxSR] = { 0x10, 16 },
280 [SCxRDR] = { 0x14, 8 },
281 [SCFCR] = { 0x18, 16 },
282 [SCFDR] = { 0x1c, 16 },
283 [SCSPTR] = { 0x20, 16 },
284 [SCLSR] = { 0x24, 16 },
285 },
286 .fifosize = 16,
287 .overrun_reg = SCLSR,
288 .overrun_mask = SCLSR_ORER,
289 .sampling_rate_mask = SCI_SR(32),
290 .error_mask = SCIF_DEFAULT_ERROR_MASK,
291 .error_clear = SCIF_ERROR_CLEAR,
292 },
293
294 /*
295 * The "SCIFA" that is in RZ/T and RZ/A2.
296 * It looks like a normal SCIF with FIFO data, but with a
297 * compressed address space. Also, the break out of interrupts
298 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
299 */
300 [SCIx_RZ_SCIFA_REGTYPE] = {
301 .regs = {
302 [SCSMR] = { 0x00, 16 },
303 [SCBRR] = { 0x02, 8 },
304 [SCSCR] = { 0x04, 16 },
305 [SCxTDR] = { 0x06, 8 },
306 [SCxSR] = { 0x08, 16 },
307 [SCxRDR] = { 0x0A, 8 },
308 [SCFCR] = { 0x0C, 16 },
309 [SCFDR] = { 0x0E, 16 },
310 [SCSPTR] = { 0x10, 16 },
311 [SCLSR] = { 0x12, 16 },
312 },
313 .fifosize = 16,
314 .overrun_reg = SCLSR,
315 .overrun_mask = SCLSR_ORER,
316 .sampling_rate_mask = SCI_SR(32),
317 .error_mask = SCIF_DEFAULT_ERROR_MASK,
318 .error_clear = SCIF_ERROR_CLEAR,
319 },
320
321 /*
322 * Common SH-3 SCIF definitions.
323 */
324 [SCIx_SH3_SCIF_REGTYPE] = {
325 .regs = {
326 [SCSMR] = { 0x00, 8 },
327 [SCBRR] = { 0x02, 8 },
328 [SCSCR] = { 0x04, 8 },
329 [SCxTDR] = { 0x06, 8 },
330 [SCxSR] = { 0x08, 16 },
331 [SCxRDR] = { 0x0a, 8 },
332 [SCFCR] = { 0x0c, 8 },
333 [SCFDR] = { 0x0e, 16 },
334 },
335 .fifosize = 16,
336 .overrun_reg = SCLSR,
337 .overrun_mask = SCLSR_ORER,
338 .sampling_rate_mask = SCI_SR(32),
339 .error_mask = SCIF_DEFAULT_ERROR_MASK,
340 .error_clear = SCIF_ERROR_CLEAR,
341 },
342
343 /*
344 * Common SH-4(A) SCIF(B) definitions.
345 */
346 [SCIx_SH4_SCIF_REGTYPE] = {
347 .regs = {
348 [SCSMR] = { 0x00, 16 },
349 [SCBRR] = { 0x04, 8 },
350 [SCSCR] = { 0x08, 16 },
351 [SCxTDR] = { 0x0c, 8 },
352 [SCxSR] = { 0x10, 16 },
353 [SCxRDR] = { 0x14, 8 },
354 [SCFCR] = { 0x18, 16 },
355 [SCFDR] = { 0x1c, 16 },
356 [SCSPTR] = { 0x20, 16 },
357 [SCLSR] = { 0x24, 16 },
358 },
359 .fifosize = 16,
360 .overrun_reg = SCLSR,
361 .overrun_mask = SCLSR_ORER,
362 .sampling_rate_mask = SCI_SR(32),
363 .error_mask = SCIF_DEFAULT_ERROR_MASK,
364 .error_clear = SCIF_ERROR_CLEAR,
365 },
366
367 /*
368 * Common SCIF definitions for ports with a Baud Rate Generator for
369 * External Clock (BRG).
370 */
371 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
372 .regs = {
373 [SCSMR] = { 0x00, 16 },
374 [SCBRR] = { 0x04, 8 },
375 [SCSCR] = { 0x08, 16 },
376 [SCxTDR] = { 0x0c, 8 },
377 [SCxSR] = { 0x10, 16 },
378 [SCxRDR] = { 0x14, 8 },
379 [SCFCR] = { 0x18, 16 },
380 [SCFDR] = { 0x1c, 16 },
381 [SCSPTR] = { 0x20, 16 },
382 [SCLSR] = { 0x24, 16 },
383 [SCDL] = { 0x30, 16 },
384 [SCCKS] = { 0x34, 16 },
385 },
386 .fifosize = 16,
387 .overrun_reg = SCLSR,
388 .overrun_mask = SCLSR_ORER,
389 .sampling_rate_mask = SCI_SR(32),
390 .error_mask = SCIF_DEFAULT_ERROR_MASK,
391 .error_clear = SCIF_ERROR_CLEAR,
392 },
393
394 /*
395 * Common HSCIF definitions.
396 */
397 [SCIx_HSCIF_REGTYPE] = {
398 .regs = {
399 [SCSMR] = { 0x00, 16 },
400 [SCBRR] = { 0x04, 8 },
401 [SCSCR] = { 0x08, 16 },
402 [SCxTDR] = { 0x0c, 8 },
403 [SCxSR] = { 0x10, 16 },
404 [SCxRDR] = { 0x14, 8 },
405 [SCFCR] = { 0x18, 16 },
406 [SCFDR] = { 0x1c, 16 },
407 [SCSPTR] = { 0x20, 16 },
408 [SCLSR] = { 0x24, 16 },
409 [HSSRR] = { 0x40, 16 },
410 [SCDL] = { 0x30, 16 },
411 [SCCKS] = { 0x34, 16 },
412 [HSRTRGR] = { 0x54, 16 },
413 [HSTTRGR] = { 0x58, 16 },
414 },
415 .fifosize = 128,
416 .overrun_reg = SCLSR,
417 .overrun_mask = SCLSR_ORER,
418 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
419 .error_mask = SCIF_DEFAULT_ERROR_MASK,
420 .error_clear = SCIF_ERROR_CLEAR,
421 },
422
423 /*
424 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
425 * register.
426 */
427 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
428 .regs = {
429 [SCSMR] = { 0x00, 16 },
430 [SCBRR] = { 0x04, 8 },
431 [SCSCR] = { 0x08, 16 },
432 [SCxTDR] = { 0x0c, 8 },
433 [SCxSR] = { 0x10, 16 },
434 [SCxRDR] = { 0x14, 8 },
435 [SCFCR] = { 0x18, 16 },
436 [SCFDR] = { 0x1c, 16 },
437 [SCLSR] = { 0x24, 16 },
438 },
439 .fifosize = 16,
440 .overrun_reg = SCLSR,
441 .overrun_mask = SCLSR_ORER,
442 .sampling_rate_mask = SCI_SR(32),
443 .error_mask = SCIF_DEFAULT_ERROR_MASK,
444 .error_clear = SCIF_ERROR_CLEAR,
445 },
446
447 /*
448 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
449 * count registers.
450 */
451 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
452 .regs = {
453 [SCSMR] = { 0x00, 16 },
454 [SCBRR] = { 0x04, 8 },
455 [SCSCR] = { 0x08, 16 },
456 [SCxTDR] = { 0x0c, 8 },
457 [SCxSR] = { 0x10, 16 },
458 [SCxRDR] = { 0x14, 8 },
459 [SCFCR] = { 0x18, 16 },
460 [SCFDR] = { 0x1c, 16 },
461 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
462 [SCRFDR] = { 0x20, 16 },
463 [SCSPTR] = { 0x24, 16 },
464 [SCLSR] = { 0x28, 16 },
465 },
466 .fifosize = 16,
467 .overrun_reg = SCLSR,
468 .overrun_mask = SCLSR_ORER,
469 .sampling_rate_mask = SCI_SR(32),
470 .error_mask = SCIF_DEFAULT_ERROR_MASK,
471 .error_clear = SCIF_ERROR_CLEAR,
472 },
473
474 /*
475 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
476 * registers.
477 */
478 [SCIx_SH7705_SCIF_REGTYPE] = {
479 .regs = {
480 [SCSMR] = { 0x00, 16 },
481 [SCBRR] = { 0x04, 8 },
482 [SCSCR] = { 0x08, 16 },
483 [SCxTDR] = { 0x20, 8 },
484 [SCxSR] = { 0x14, 16 },
485 [SCxRDR] = { 0x24, 8 },
486 [SCFCR] = { 0x18, 16 },
487 [SCFDR] = { 0x1c, 16 },
488 },
489 .fifosize = 64,
490 .overrun_reg = SCxSR,
491 .overrun_mask = SCIFA_ORER,
492 .sampling_rate_mask = SCI_SR(16),
493 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
494 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
495 },
496};
497
498#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
499
500/*
501 * The "offset" here is rather misleading, in that it refers to an enum
502 * value relative to the port mapping rather than the fixed offset
503 * itself, which needs to be manually retrieved from the platform's
504 * register map for the given port.
505 */
506static unsigned int sci_serial_in(struct uart_port *p, int offset)
507{
508 const struct plat_sci_reg *reg = sci_getreg(p, offset);
509
510 if (reg->size == 8)
511 return ioread8(p->membase + (reg->offset << p->regshift));
512 else if (reg->size == 16)
513 return ioread16(p->membase + (reg->offset << p->regshift));
514 else
515 WARN(1, "Invalid register access\n");
516
517 return 0;
518}
519
520static void sci_serial_out(struct uart_port *p, int offset, int value)
521{
522 const struct plat_sci_reg *reg = sci_getreg(p, offset);
523
524 if (reg->size == 8)
525 iowrite8(value, p->membase + (reg->offset << p->regshift));
526 else if (reg->size == 16)
527 iowrite16(value, p->membase + (reg->offset << p->regshift));
528 else
529 WARN(1, "Invalid register access\n");
530}
531
532static void sci_port_enable(struct sci_port *sci_port)
533{
534 unsigned int i;
535
536 if (!sci_port->port.dev)
537 return;
538
539 pm_runtime_get_sync(sci_port->port.dev);
540
541 for (i = 0; i < SCI_NUM_CLKS; i++) {
542 clk_prepare_enable(sci_port->clks[i]);
543 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
544 }
545 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
546}
547
548static void sci_port_disable(struct sci_port *sci_port)
549{
550 unsigned int i;
551
552 if (!sci_port->port.dev)
553 return;
554
555 for (i = SCI_NUM_CLKS; i-- > 0; )
556 clk_disable_unprepare(sci_port->clks[i]);
557
558 pm_runtime_put_sync(sci_port->port.dev);
559}
560
561static inline unsigned long port_rx_irq_mask(struct uart_port *port)
562{
563 /*
564 * Not all ports (such as SCIFA) will support REIE. Rather than
565 * special-casing the port type, we check the port initialization
566 * IRQ enable mask to see whether the IRQ is desired at all. If
567 * it's unset, it's logically inferred that there's no point in
568 * testing for it.
569 */
570 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
571}
572
573static void sci_start_tx(struct uart_port *port)
574{
575 struct sci_port *s = to_sci_port(port);
576 unsigned short ctrl;
577
578#ifdef CONFIG_SERIAL_SH_SCI_DMA
579 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
580 u16 new, scr = serial_port_in(port, SCSCR);
581 if (s->chan_tx)
582 new = scr | SCSCR_TDRQE;
583 else
584 new = scr & ~SCSCR_TDRQE;
585 if (new != scr)
586 serial_port_out(port, SCSCR, new);
587 }
588
589 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
590 dma_submit_error(s->cookie_tx)) {
591 s->cookie_tx = 0;
592 schedule_work(&s->work_tx);
593 }
594#endif
595
596 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
597 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
598 ctrl = serial_port_in(port, SCSCR);
599 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
600 }
601}
602
603static void sci_stop_tx(struct uart_port *port)
604{
605 unsigned short ctrl;
606
607 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
608 ctrl = serial_port_in(port, SCSCR);
609
610 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
611 ctrl &= ~SCSCR_TDRQE;
612
613 ctrl &= ~SCSCR_TIE;
614
615 serial_port_out(port, SCSCR, ctrl);
616}
617
618static void sci_start_rx(struct uart_port *port)
619{
620 unsigned short ctrl;
621
622 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
623
624 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
625 ctrl &= ~SCSCR_RDRQE;
626
627 serial_port_out(port, SCSCR, ctrl);
628}
629
630static void sci_stop_rx(struct uart_port *port)
631{
632 unsigned short ctrl;
633
634 ctrl = serial_port_in(port, SCSCR);
635
636 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
637 ctrl &= ~SCSCR_RDRQE;
638
639 ctrl &= ~port_rx_irq_mask(port);
640
641 serial_port_out(port, SCSCR, ctrl);
642}
643
644static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
645{
646 if (port->type == PORT_SCI) {
647 /* Just store the mask */
648 serial_port_out(port, SCxSR, mask);
649 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
650 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
651 /* Only clear the status bits we want to clear */
652 serial_port_out(port, SCxSR,
653 serial_port_in(port, SCxSR) & mask);
654 } else {
655 /* Store the mask, clear parity/framing errors */
656 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
657 }
658}
659
660#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
661 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
662
663#ifdef CONFIG_CONSOLE_POLL
664static int sci_poll_get_char(struct uart_port *port)
665{
666 unsigned short status;
667 int c;
668
669 do {
670 status = serial_port_in(port, SCxSR);
671 if (status & SCxSR_ERRORS(port)) {
672 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
673 continue;
674 }
675 break;
676 } while (1);
677
678 if (!(status & SCxSR_RDxF(port)))
679 return NO_POLL_CHAR;
680
681 c = serial_port_in(port, SCxRDR);
682
683 /* Dummy read */
684 serial_port_in(port, SCxSR);
685 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
686
687 return c;
688}
689#endif
690
691static void sci_poll_put_char(struct uart_port *port, unsigned char c)
692{
693 unsigned short status;
694
695 do {
696 status = serial_port_in(port, SCxSR);
697 } while (!(status & SCxSR_TDxE(port)));
698
699 serial_port_out(port, SCxTDR, c);
700 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
701}
702#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
703 CONFIG_SERIAL_SH_SCI_EARLYCON */
704
705static void sci_init_pins(struct uart_port *port, unsigned int cflag)
706{
707 struct sci_port *s = to_sci_port(port);
708
709 /*
710 * Use port-specific handler if provided.
711 */
712 if (s->cfg->ops && s->cfg->ops->init_pins) {
713 s->cfg->ops->init_pins(port, cflag);
714 return;
715 }
716
717 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
718 u16 data = serial_port_in(port, SCPDR);
719 u16 ctrl = serial_port_in(port, SCPCR);
720
721 /* Enable RXD and TXD pin functions */
722 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
723 if (to_sci_port(port)->has_rtscts) {
724 /* RTS# is output, active low, unless autorts */
725 if (!(port->mctrl & TIOCM_RTS)) {
726 ctrl |= SCPCR_RTSC;
727 data |= SCPDR_RTSD;
728 } else if (!s->autorts) {
729 ctrl |= SCPCR_RTSC;
730 data &= ~SCPDR_RTSD;
731 } else {
732 /* Enable RTS# pin function */
733 ctrl &= ~SCPCR_RTSC;
734 }
735 /* Enable CTS# pin function */
736 ctrl &= ~SCPCR_CTSC;
737 }
738 serial_port_out(port, SCPDR, data);
739 serial_port_out(port, SCPCR, ctrl);
740 } else if (sci_getreg(port, SCSPTR)->size) {
741 u16 status = serial_port_in(port, SCSPTR);
742
743 /* RTS# is always output; and active low, unless autorts */
744 status |= SCSPTR_RTSIO;
745 if (!(port->mctrl & TIOCM_RTS))
746 status |= SCSPTR_RTSDT;
747 else if (!s->autorts)
748 status &= ~SCSPTR_RTSDT;
749 /* CTS# and SCK are inputs */
750 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
751 serial_port_out(port, SCSPTR, status);
752 }
753}
754
755static int sci_txfill(struct uart_port *port)
756{
757 struct sci_port *s = to_sci_port(port);
758 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
759 const struct plat_sci_reg *reg;
760
761 reg = sci_getreg(port, SCTFDR);
762 if (reg->size)
763 return serial_port_in(port, SCTFDR) & fifo_mask;
764
765 reg = sci_getreg(port, SCFDR);
766 if (reg->size)
767 return serial_port_in(port, SCFDR) >> 8;
768
769 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
770}
771
772static int sci_txroom(struct uart_port *port)
773{
774 return port->fifosize - sci_txfill(port);
775}
776
777static int sci_rxfill(struct uart_port *port)
778{
779 struct sci_port *s = to_sci_port(port);
780 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
781 const struct plat_sci_reg *reg;
782
783 reg = sci_getreg(port, SCRFDR);
784 if (reg->size)
785 return serial_port_in(port, SCRFDR) & fifo_mask;
786
787 reg = sci_getreg(port, SCFDR);
788 if (reg->size)
789 return serial_port_in(port, SCFDR) & fifo_mask;
790
791 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
792}
793
794/* ********************************************************************** *
795 * the interrupt related routines *
796 * ********************************************************************** */
797
798static void sci_transmit_chars(struct uart_port *port)
799{
800 struct circ_buf *xmit = &port->state->xmit;
801 unsigned int stopped = uart_tx_stopped(port);
802 unsigned short status;
803 unsigned short ctrl;
804 int count;
805
806 status = serial_port_in(port, SCxSR);
807 if (!(status & SCxSR_TDxE(port))) {
808 ctrl = serial_port_in(port, SCSCR);
809 if (uart_circ_empty(xmit))
810 ctrl &= ~SCSCR_TIE;
811 else
812 ctrl |= SCSCR_TIE;
813 serial_port_out(port, SCSCR, ctrl);
814 return;
815 }
816
817 count = sci_txroom(port);
818
819 do {
820 unsigned char c;
821
822 if (port->x_char) {
823 c = port->x_char;
824 port->x_char = 0;
825 } else if (!uart_circ_empty(xmit) && !stopped) {
826 c = xmit->buf[xmit->tail];
827 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
828 } else {
829 break;
830 }
831
832 serial_port_out(port, SCxTDR, c);
833
834 port->icount.tx++;
835 } while (--count > 0);
836
837 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
838
839 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
840 uart_write_wakeup(port);
841 if (uart_circ_empty(xmit))
842 sci_stop_tx(port);
843
844}
845
846/* On SH3, SCIF may read end-of-break as a space->mark char */
847#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
848
849static void sci_receive_chars(struct uart_port *port)
850{
851 struct tty_port *tport = &port->state->port;
852 int i, count, copied = 0;
853 unsigned short status;
854 unsigned char flag;
855
856 status = serial_port_in(port, SCxSR);
857 if (!(status & SCxSR_RDxF(port)))
858 return;
859
860 while (1) {
861 /* Don't copy more bytes than there is room for in the buffer */
862 count = tty_buffer_request_room(tport, sci_rxfill(port));
863
864 /* If for any reason we can't copy more data, we're done! */
865 if (count == 0)
866 break;
867
868 if (port->type == PORT_SCI) {
869 char c = serial_port_in(port, SCxRDR);
870 if (uart_handle_sysrq_char(port, c))
871 count = 0;
872 else
873 tty_insert_flip_char(tport, c, TTY_NORMAL);
874 } else {
875 for (i = 0; i < count; i++) {
876 char c = serial_port_in(port, SCxRDR);
877
878 status = serial_port_in(port, SCxSR);
879 if (uart_handle_sysrq_char(port, c)) {
880 count--; i--;
881 continue;
882 }
883
884 /* Store data and status */
885 if (status & SCxSR_FER(port)) {
886 flag = TTY_FRAME;
887 port->icount.frame++;
888 dev_notice(port->dev, "frame error\n");
889 } else if (status & SCxSR_PER(port)) {
890 flag = TTY_PARITY;
891 port->icount.parity++;
892 dev_notice(port->dev, "parity error\n");
893 } else
894 flag = TTY_NORMAL;
895
896 tty_insert_flip_char(tport, c, flag);
897 }
898 }
899
900 serial_port_in(port, SCxSR); /* dummy read */
901 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
902
903 copied += count;
904 port->icount.rx += count;
905 }
906
907 if (copied) {
908 /* Tell the rest of the system the news. New characters! */
909 tty_flip_buffer_push(tport);
910 } else {
911 /* TTY buffers full; read from RX reg to prevent lockup */
912 serial_port_in(port, SCxRDR);
913 serial_port_in(port, SCxSR); /* dummy read */
914 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
915 }
916}
917
918static int sci_handle_errors(struct uart_port *port)
919{
920 int copied = 0;
921 unsigned short status = serial_port_in(port, SCxSR);
922 struct tty_port *tport = &port->state->port;
923 struct sci_port *s = to_sci_port(port);
924
925 /* Handle overruns */
926 if (status & s->params->overrun_mask) {
927 port->icount.overrun++;
928
929 /* overrun error */
930 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
931 copied++;
932
933 dev_notice(port->dev, "overrun error\n");
934 }
935
936 if (status & SCxSR_FER(port)) {
937 /* frame error */
938 port->icount.frame++;
939
940 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
941 copied++;
942
943 dev_notice(port->dev, "frame error\n");
944 }
945
946 if (status & SCxSR_PER(port)) {
947 /* parity error */
948 port->icount.parity++;
949
950 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
951 copied++;
952
953 dev_notice(port->dev, "parity error\n");
954 }
955
956 if (copied)
957 tty_flip_buffer_push(tport);
958
959 return copied;
960}
961
962static int sci_handle_fifo_overrun(struct uart_port *port)
963{
964 struct tty_port *tport = &port->state->port;
965 struct sci_port *s = to_sci_port(port);
966 const struct plat_sci_reg *reg;
967 int copied = 0;
968 u16 status;
969
970 reg = sci_getreg(port, s->params->overrun_reg);
971 if (!reg->size)
972 return 0;
973
974 status = serial_port_in(port, s->params->overrun_reg);
975 if (status & s->params->overrun_mask) {
976 status &= ~s->params->overrun_mask;
977 serial_port_out(port, s->params->overrun_reg, status);
978
979 port->icount.overrun++;
980
981 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
982 tty_flip_buffer_push(tport);
983
984 dev_dbg(port->dev, "overrun error\n");
985 copied++;
986 }
987
988 return copied;
989}
990
991static int sci_handle_breaks(struct uart_port *port)
992{
993 int copied = 0;
994 unsigned short status = serial_port_in(port, SCxSR);
995 struct tty_port *tport = &port->state->port;
996
997 if (uart_handle_break(port))
998 return 0;
999
1000 if (status & SCxSR_BRK(port)) {
1001 port->icount.brk++;
1002
1003 /* Notify of BREAK */
1004 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1005 copied++;
1006
1007 dev_dbg(port->dev, "BREAK detected\n");
1008 }
1009
1010 if (copied)
1011 tty_flip_buffer_push(tport);
1012
1013 copied += sci_handle_fifo_overrun(port);
1014
1015 return copied;
1016}
1017
1018static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1019{
1020 unsigned int bits;
1021
1022 if (rx_trig < 1)
1023 rx_trig = 1;
1024 if (rx_trig >= port->fifosize)
1025 rx_trig = port->fifosize;
1026
1027 /* HSCIF can be set to an arbitrary level. */
1028 if (sci_getreg(port, HSRTRGR)->size) {
1029 serial_port_out(port, HSRTRGR, rx_trig);
1030 return rx_trig;
1031 }
1032
1033 switch (port->type) {
1034 case PORT_SCIF:
1035 if (rx_trig < 4) {
1036 bits = 0;
1037 rx_trig = 1;
1038 } else if (rx_trig < 8) {
1039 bits = SCFCR_RTRG0;
1040 rx_trig = 4;
1041 } else if (rx_trig < 14) {
1042 bits = SCFCR_RTRG1;
1043 rx_trig = 8;
1044 } else {
1045 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1046 rx_trig = 14;
1047 }
1048 break;
1049 case PORT_SCIFA:
1050 case PORT_SCIFB:
1051 if (rx_trig < 16) {
1052 bits = 0;
1053 rx_trig = 1;
1054 } else if (rx_trig < 32) {
1055 bits = SCFCR_RTRG0;
1056 rx_trig = 16;
1057 } else if (rx_trig < 48) {
1058 bits = SCFCR_RTRG1;
1059 rx_trig = 32;
1060 } else {
1061 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1062 rx_trig = 48;
1063 }
1064 break;
1065 default:
1066 WARN(1, "unknown FIFO configuration");
1067 return 1;
1068 }
1069
1070 serial_port_out(port, SCFCR,
1071 (serial_port_in(port, SCFCR) &
1072 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1073
1074 return rx_trig;
1075}
1076
1077static int scif_rtrg_enabled(struct uart_port *port)
1078{
1079 if (sci_getreg(port, HSRTRGR)->size)
1080 return serial_port_in(port, HSRTRGR) != 0;
1081 else
1082 return (serial_port_in(port, SCFCR) &
1083 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1084}
1085
1086static void rx_fifo_timer_fn(struct timer_list *t)
1087{
1088 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1089 struct uart_port *port = &s->port;
1090
1091 dev_dbg(port->dev, "Rx timed out\n");
1092 scif_set_rtrg(port, 1);
1093}
1094
1095static ssize_t rx_fifo_trigger_show(struct device *dev,
1096 struct device_attribute *attr, char *buf)
1097{
1098 struct uart_port *port = dev_get_drvdata(dev);
1099 struct sci_port *sci = to_sci_port(port);
1100
1101 return sprintf(buf, "%d\n", sci->rx_trigger);
1102}
1103
1104static ssize_t rx_fifo_trigger_store(struct device *dev,
1105 struct device_attribute *attr,
1106 const char *buf, size_t count)
1107{
1108 struct uart_port *port = dev_get_drvdata(dev);
1109 struct sci_port *sci = to_sci_port(port);
1110 int ret;
1111 long r;
1112
1113 ret = kstrtol(buf, 0, &r);
1114 if (ret)
1115 return ret;
1116
1117 sci->rx_trigger = scif_set_rtrg(port, r);
1118 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1119 scif_set_rtrg(port, 1);
1120
1121 return count;
1122}
1123
1124static DEVICE_ATTR_RW(rx_fifo_trigger);
1125
1126static ssize_t rx_fifo_timeout_show(struct device *dev,
1127 struct device_attribute *attr,
1128 char *buf)
1129{
1130 struct uart_port *port = dev_get_drvdata(dev);
1131 struct sci_port *sci = to_sci_port(port);
1132 int v;
1133
1134 if (port->type == PORT_HSCIF)
1135 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1136 else
1137 v = sci->rx_fifo_timeout;
1138
1139 return sprintf(buf, "%d\n", v);
1140}
1141
1142static ssize_t rx_fifo_timeout_store(struct device *dev,
1143 struct device_attribute *attr,
1144 const char *buf,
1145 size_t count)
1146{
1147 struct uart_port *port = dev_get_drvdata(dev);
1148 struct sci_port *sci = to_sci_port(port);
1149 int ret;
1150 long r;
1151
1152 ret = kstrtol(buf, 0, &r);
1153 if (ret)
1154 return ret;
1155
1156 if (port->type == PORT_HSCIF) {
1157 if (r < 0 || r > 3)
1158 return -EINVAL;
1159 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1160 } else {
1161 sci->rx_fifo_timeout = r;
1162 scif_set_rtrg(port, 1);
1163 if (r > 0)
1164 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1165 }
1166
1167 return count;
1168}
1169
1170static DEVICE_ATTR_RW(rx_fifo_timeout);
1171
1172
1173#ifdef CONFIG_SERIAL_SH_SCI_DMA
1174static void sci_dma_tx_complete(void *arg)
1175{
1176 struct sci_port *s = arg;
1177 struct uart_port *port = &s->port;
1178 struct circ_buf *xmit = &port->state->xmit;
1179 unsigned long flags;
1180
1181 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1182
1183 spin_lock_irqsave(&port->lock, flags);
1184
1185 xmit->tail += s->tx_dma_len;
1186 xmit->tail &= UART_XMIT_SIZE - 1;
1187
1188 port->icount.tx += s->tx_dma_len;
1189
1190 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1191 uart_write_wakeup(port);
1192
1193 if (!uart_circ_empty(xmit)) {
1194 s->cookie_tx = 0;
1195 schedule_work(&s->work_tx);
1196 } else {
1197 s->cookie_tx = -EINVAL;
1198 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1199 u16 ctrl = serial_port_in(port, SCSCR);
1200 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1201 }
1202 }
1203
1204 spin_unlock_irqrestore(&port->lock, flags);
1205}
1206
1207/* Locking: called with port lock held */
1208static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1209{
1210 struct uart_port *port = &s->port;
1211 struct tty_port *tport = &port->state->port;
1212 int copied;
1213
1214 copied = tty_insert_flip_string(tport, buf, count);
1215 if (copied < count)
1216 port->icount.buf_overrun++;
1217
1218 port->icount.rx += copied;
1219
1220 return copied;
1221}
1222
1223static int sci_dma_rx_find_active(struct sci_port *s)
1224{
1225 unsigned int i;
1226
1227 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1228 if (s->active_rx == s->cookie_rx[i])
1229 return i;
1230
1231 return -1;
1232}
1233
1234static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1235{
1236 unsigned int i;
1237
1238 s->chan_rx = NULL;
1239 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1240 s->cookie_rx[i] = -EINVAL;
1241 s->active_rx = 0;
1242}
1243
1244static void sci_dma_rx_release(struct sci_port *s)
1245{
1246 struct dma_chan *chan = s->chan_rx_saved;
1247
1248 s->chan_rx_saved = NULL;
1249 sci_dma_rx_chan_invalidate(s);
1250 dmaengine_terminate_sync(chan);
1251 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1252 sg_dma_address(&s->sg_rx[0]));
1253 dma_release_channel(chan);
1254}
1255
1256static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1257{
1258 long sec = usec / 1000000;
1259 long nsec = (usec % 1000000) * 1000;
1260 ktime_t t = ktime_set(sec, nsec);
1261
1262 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1263}
1264
1265static void sci_dma_rx_reenable_irq(struct sci_port *s)
1266{
1267 struct uart_port *port = &s->port;
1268 u16 scr;
1269
1270 /* Direct new serial port interrupts back to CPU */
1271 scr = serial_port_in(port, SCSCR);
1272 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1273 scr &= ~SCSCR_RDRQE;
1274 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1275 }
1276 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1277}
1278
1279static void sci_dma_rx_complete(void *arg)
1280{
1281 struct sci_port *s = arg;
1282 struct dma_chan *chan = s->chan_rx;
1283 struct uart_port *port = &s->port;
1284 struct dma_async_tx_descriptor *desc;
1285 unsigned long flags;
1286 int active, count = 0;
1287
1288 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1289 s->active_rx);
1290
1291 spin_lock_irqsave(&port->lock, flags);
1292
1293 active = sci_dma_rx_find_active(s);
1294 if (active >= 0)
1295 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1296
1297 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1298
1299 if (count)
1300 tty_flip_buffer_push(&port->state->port);
1301
1302 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1303 DMA_DEV_TO_MEM,
1304 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1305 if (!desc)
1306 goto fail;
1307
1308 desc->callback = sci_dma_rx_complete;
1309 desc->callback_param = s;
1310 s->cookie_rx[active] = dmaengine_submit(desc);
1311 if (dma_submit_error(s->cookie_rx[active]))
1312 goto fail;
1313
1314 s->active_rx = s->cookie_rx[!active];
1315
1316 dma_async_issue_pending(chan);
1317
1318 spin_unlock_irqrestore(&port->lock, flags);
1319 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1320 __func__, s->cookie_rx[active], active, s->active_rx);
1321 return;
1322
1323fail:
1324 spin_unlock_irqrestore(&port->lock, flags);
1325 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1326 /* Switch to PIO */
1327 spin_lock_irqsave(&port->lock, flags);
1328 dmaengine_terminate_async(chan);
1329 sci_dma_rx_chan_invalidate(s);
1330 sci_dma_rx_reenable_irq(s);
1331 spin_unlock_irqrestore(&port->lock, flags);
1332}
1333
1334static void sci_dma_tx_release(struct sci_port *s)
1335{
1336 struct dma_chan *chan = s->chan_tx_saved;
1337
1338 cancel_work_sync(&s->work_tx);
1339 s->chan_tx_saved = s->chan_tx = NULL;
1340 s->cookie_tx = -EINVAL;
1341 dmaengine_terminate_sync(chan);
1342 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1343 DMA_TO_DEVICE);
1344 dma_release_channel(chan);
1345}
1346
1347static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1348{
1349 struct dma_chan *chan = s->chan_rx;
1350 struct uart_port *port = &s->port;
1351 unsigned long flags;
1352 int i;
1353
1354 for (i = 0; i < 2; i++) {
1355 struct scatterlist *sg = &s->sg_rx[i];
1356 struct dma_async_tx_descriptor *desc;
1357
1358 desc = dmaengine_prep_slave_sg(chan,
1359 sg, 1, DMA_DEV_TO_MEM,
1360 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1361 if (!desc)
1362 goto fail;
1363
1364 desc->callback = sci_dma_rx_complete;
1365 desc->callback_param = s;
1366 s->cookie_rx[i] = dmaengine_submit(desc);
1367 if (dma_submit_error(s->cookie_rx[i]))
1368 goto fail;
1369
1370 }
1371
1372 s->active_rx = s->cookie_rx[0];
1373
1374 dma_async_issue_pending(chan);
1375 return 0;
1376
1377fail:
1378 /* Switch to PIO */
1379 if (!port_lock_held)
1380 spin_lock_irqsave(&port->lock, flags);
1381 if (i)
1382 dmaengine_terminate_async(chan);
1383 sci_dma_rx_chan_invalidate(s);
1384 sci_start_rx(port);
1385 if (!port_lock_held)
1386 spin_unlock_irqrestore(&port->lock, flags);
1387 return -EAGAIN;
1388}
1389
1390static void sci_dma_tx_work_fn(struct work_struct *work)
1391{
1392 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1393 struct dma_async_tx_descriptor *desc;
1394 struct dma_chan *chan = s->chan_tx;
1395 struct uart_port *port = &s->port;
1396 struct circ_buf *xmit = &port->state->xmit;
1397 unsigned long flags;
1398 dma_addr_t buf;
1399 int head, tail;
1400
1401 /*
1402 * DMA is idle now.
1403 * Port xmit buffer is already mapped, and it is one page... Just adjust
1404 * offsets and lengths. Since it is a circular buffer, we have to
1405 * transmit till the end, and then the rest. Take the port lock to get a
1406 * consistent xmit buffer state.
1407 */
1408 spin_lock_irq(&port->lock);
1409 head = xmit->head;
1410 tail = xmit->tail;
1411 buf = s->tx_dma_addr + (tail & (UART_XMIT_SIZE - 1));
1412 s->tx_dma_len = min_t(unsigned int,
1413 CIRC_CNT(head, tail, UART_XMIT_SIZE),
1414 CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE));
1415 if (!s->tx_dma_len) {
1416 /* Transmit buffer has been flushed */
1417 spin_unlock_irq(&port->lock);
1418 return;
1419 }
1420
1421 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1422 DMA_MEM_TO_DEV,
1423 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1424 if (!desc) {
1425 spin_unlock_irq(&port->lock);
1426 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1427 goto switch_to_pio;
1428 }
1429
1430 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1431 DMA_TO_DEVICE);
1432
1433 desc->callback = sci_dma_tx_complete;
1434 desc->callback_param = s;
1435 s->cookie_tx = dmaengine_submit(desc);
1436 if (dma_submit_error(s->cookie_tx)) {
1437 spin_unlock_irq(&port->lock);
1438 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1439 goto switch_to_pio;
1440 }
1441
1442 spin_unlock_irq(&port->lock);
1443 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1444 __func__, xmit->buf, tail, head, s->cookie_tx);
1445
1446 dma_async_issue_pending(chan);
1447 return;
1448
1449switch_to_pio:
1450 spin_lock_irqsave(&port->lock, flags);
1451 s->chan_tx = NULL;
1452 sci_start_tx(port);
1453 spin_unlock_irqrestore(&port->lock, flags);
1454 return;
1455}
1456
1457static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1458{
1459 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1460 struct dma_chan *chan = s->chan_rx;
1461 struct uart_port *port = &s->port;
1462 struct dma_tx_state state;
1463 enum dma_status status;
1464 unsigned long flags;
1465 unsigned int read;
1466 int active, count;
1467
1468 dev_dbg(port->dev, "DMA Rx timed out\n");
1469
1470 spin_lock_irqsave(&port->lock, flags);
1471
1472 active = sci_dma_rx_find_active(s);
1473 if (active < 0) {
1474 spin_unlock_irqrestore(&port->lock, flags);
1475 return HRTIMER_NORESTART;
1476 }
1477
1478 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1479 if (status == DMA_COMPLETE) {
1480 spin_unlock_irqrestore(&port->lock, flags);
1481 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1482 s->active_rx, active);
1483
1484 /* Let packet complete handler take care of the packet */
1485 return HRTIMER_NORESTART;
1486 }
1487
1488 dmaengine_pause(chan);
1489
1490 /*
1491 * sometimes DMA transfer doesn't stop even if it is stopped and
1492 * data keeps on coming until transaction is complete so check
1493 * for DMA_COMPLETE again
1494 * Let packet complete handler take care of the packet
1495 */
1496 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1497 if (status == DMA_COMPLETE) {
1498 spin_unlock_irqrestore(&port->lock, flags);
1499 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1500 return HRTIMER_NORESTART;
1501 }
1502
1503 /* Handle incomplete DMA receive */
1504 dmaengine_terminate_async(s->chan_rx);
1505 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1506
1507 if (read) {
1508 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1509 if (count)
1510 tty_flip_buffer_push(&port->state->port);
1511 }
1512
1513 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1514 sci_dma_rx_submit(s, true);
1515
1516 sci_dma_rx_reenable_irq(s);
1517
1518 spin_unlock_irqrestore(&port->lock, flags);
1519
1520 return HRTIMER_NORESTART;
1521}
1522
1523static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1524 enum dma_transfer_direction dir)
1525{
1526 struct dma_chan *chan;
1527 struct dma_slave_config cfg;
1528 int ret;
1529
1530 chan = dma_request_slave_channel(port->dev,
1531 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1532 if (!chan) {
1533 dev_dbg(port->dev, "dma_request_slave_channel failed\n");
1534 return NULL;
1535 }
1536
1537 memset(&cfg, 0, sizeof(cfg));
1538 cfg.direction = dir;
1539 if (dir == DMA_MEM_TO_DEV) {
1540 cfg.dst_addr = port->mapbase +
1541 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1542 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1543 } else {
1544 cfg.src_addr = port->mapbase +
1545 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1546 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1547 }
1548
1549 ret = dmaengine_slave_config(chan, &cfg);
1550 if (ret) {
1551 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1552 dma_release_channel(chan);
1553 return NULL;
1554 }
1555
1556 return chan;
1557}
1558
1559static void sci_request_dma(struct uart_port *port)
1560{
1561 struct sci_port *s = to_sci_port(port);
1562 struct dma_chan *chan;
1563
1564 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1565
1566 /*
1567 * DMA on console may interfere with Kernel log messages which use
1568 * plain putchar(). So, simply don't use it with a console.
1569 */
1570 if (uart_console(port))
1571 return;
1572
1573 if (!port->dev->of_node)
1574 return;
1575
1576 s->cookie_tx = -EINVAL;
1577
1578 /*
1579 * Don't request a dma channel if no channel was specified
1580 * in the device tree.
1581 */
1582 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1583 return;
1584
1585 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1586 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1587 if (chan) {
1588 /* UART circular tx buffer is an aligned page. */
1589 s->tx_dma_addr = dma_map_single(chan->device->dev,
1590 port->state->xmit.buf,
1591 UART_XMIT_SIZE,
1592 DMA_TO_DEVICE);
1593 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1594 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1595 dma_release_channel(chan);
1596 } else {
1597 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1598 __func__, UART_XMIT_SIZE,
1599 port->state->xmit.buf, &s->tx_dma_addr);
1600
1601 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1602 s->chan_tx_saved = s->chan_tx = chan;
1603 }
1604 }
1605
1606 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1607 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1608 if (chan) {
1609 unsigned int i;
1610 dma_addr_t dma;
1611 void *buf;
1612
1613 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1614 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1615 &dma, GFP_KERNEL);
1616 if (!buf) {
1617 dev_warn(port->dev,
1618 "Failed to allocate Rx dma buffer, using PIO\n");
1619 dma_release_channel(chan);
1620 return;
1621 }
1622
1623 for (i = 0; i < 2; i++) {
1624 struct scatterlist *sg = &s->sg_rx[i];
1625
1626 sg_init_table(sg, 1);
1627 s->rx_buf[i] = buf;
1628 sg_dma_address(sg) = dma;
1629 sg_dma_len(sg) = s->buf_len_rx;
1630
1631 buf += s->buf_len_rx;
1632 dma += s->buf_len_rx;
1633 }
1634
1635 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1636 s->rx_timer.function = sci_dma_rx_timer_fn;
1637
1638 s->chan_rx_saved = s->chan_rx = chan;
1639
1640 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1641 sci_dma_rx_submit(s, false);
1642 }
1643}
1644
1645static void sci_free_dma(struct uart_port *port)
1646{
1647 struct sci_port *s = to_sci_port(port);
1648
1649 if (s->chan_tx_saved)
1650 sci_dma_tx_release(s);
1651 if (s->chan_rx_saved)
1652 sci_dma_rx_release(s);
1653}
1654
1655static void sci_flush_buffer(struct uart_port *port)
1656{
1657 struct sci_port *s = to_sci_port(port);
1658
1659 /*
1660 * In uart_flush_buffer(), the xmit circular buffer has just been
1661 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1662 * pending transfers
1663 */
1664 s->tx_dma_len = 0;
1665 if (s->chan_tx) {
1666 dmaengine_terminate_async(s->chan_tx);
1667 s->cookie_tx = -EINVAL;
1668 }
1669}
1670#else /* !CONFIG_SERIAL_SH_SCI_DMA */
1671static inline void sci_request_dma(struct uart_port *port)
1672{
1673}
1674
1675static inline void sci_free_dma(struct uart_port *port)
1676{
1677}
1678
1679#define sci_flush_buffer NULL
1680#endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1681
1682static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1683{
1684 struct uart_port *port = ptr;
1685 struct sci_port *s = to_sci_port(port);
1686
1687#ifdef CONFIG_SERIAL_SH_SCI_DMA
1688 if (s->chan_rx) {
1689 u16 scr = serial_port_in(port, SCSCR);
1690 u16 ssr = serial_port_in(port, SCxSR);
1691
1692 /* Disable future Rx interrupts */
1693 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1694 disable_irq_nosync(irq);
1695 scr |= SCSCR_RDRQE;
1696 } else {
1697 if (sci_dma_rx_submit(s, false) < 0)
1698 goto handle_pio;
1699
1700 scr &= ~SCSCR_RIE;
1701 }
1702 serial_port_out(port, SCSCR, scr);
1703 /* Clear current interrupt */
1704 serial_port_out(port, SCxSR,
1705 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1706 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1707 jiffies, s->rx_timeout);
1708 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1709
1710 return IRQ_HANDLED;
1711 }
1712
1713handle_pio:
1714#endif
1715
1716 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1717 if (!scif_rtrg_enabled(port))
1718 scif_set_rtrg(port, s->rx_trigger);
1719
1720 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1721 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1722 }
1723
1724 /* I think sci_receive_chars has to be called irrespective
1725 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1726 * to be disabled?
1727 */
1728 sci_receive_chars(port);
1729
1730 return IRQ_HANDLED;
1731}
1732
1733static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1734{
1735 struct uart_port *port = ptr;
1736 unsigned long flags;
1737
1738 spin_lock_irqsave(&port->lock, flags);
1739 sci_transmit_chars(port);
1740 spin_unlock_irqrestore(&port->lock, flags);
1741
1742 return IRQ_HANDLED;
1743}
1744
1745static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1746{
1747 struct uart_port *port = ptr;
1748
1749 /* Handle BREAKs */
1750 sci_handle_breaks(port);
1751 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1752
1753 return IRQ_HANDLED;
1754}
1755
1756static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1757{
1758 struct uart_port *port = ptr;
1759 struct sci_port *s = to_sci_port(port);
1760
1761 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1762 /* Break and Error interrupts are muxed */
1763 unsigned short ssr_status = serial_port_in(port, SCxSR);
1764
1765 /* Break Interrupt */
1766 if (ssr_status & SCxSR_BRK(port))
1767 sci_br_interrupt(irq, ptr);
1768
1769 /* Break only? */
1770 if (!(ssr_status & SCxSR_ERRORS(port)))
1771 return IRQ_HANDLED;
1772 }
1773
1774 /* Handle errors */
1775 if (port->type == PORT_SCI) {
1776 if (sci_handle_errors(port)) {
1777 /* discard character in rx buffer */
1778 serial_port_in(port, SCxSR);
1779 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1780 }
1781 } else {
1782 sci_handle_fifo_overrun(port);
1783 if (!s->chan_rx)
1784 sci_receive_chars(port);
1785 }
1786
1787 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1788
1789 /* Kick the transmission */
1790 if (!s->chan_tx)
1791 sci_tx_interrupt(irq, ptr);
1792
1793 return IRQ_HANDLED;
1794}
1795
1796static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1797{
1798 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1799 struct uart_port *port = ptr;
1800 struct sci_port *s = to_sci_port(port);
1801 irqreturn_t ret = IRQ_NONE;
1802
1803 ssr_status = serial_port_in(port, SCxSR);
1804 scr_status = serial_port_in(port, SCSCR);
1805 if (s->params->overrun_reg == SCxSR)
1806 orer_status = ssr_status;
1807 else if (sci_getreg(port, s->params->overrun_reg)->size)
1808 orer_status = serial_port_in(port, s->params->overrun_reg);
1809
1810 err_enabled = scr_status & port_rx_irq_mask(port);
1811
1812 /* Tx Interrupt */
1813 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1814 !s->chan_tx)
1815 ret = sci_tx_interrupt(irq, ptr);
1816
1817 /*
1818 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1819 * DR flags
1820 */
1821 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1822 (scr_status & SCSCR_RIE))
1823 ret = sci_rx_interrupt(irq, ptr);
1824
1825 /* Error Interrupt */
1826 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1827 ret = sci_er_interrupt(irq, ptr);
1828
1829 /* Break Interrupt */
1830 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1831 ret = sci_br_interrupt(irq, ptr);
1832
1833 /* Overrun Interrupt */
1834 if (orer_status & s->params->overrun_mask) {
1835 sci_handle_fifo_overrun(port);
1836 ret = IRQ_HANDLED;
1837 }
1838
1839 return ret;
1840}
1841
1842static const struct sci_irq_desc {
1843 const char *desc;
1844 irq_handler_t handler;
1845} sci_irq_desc[] = {
1846 /*
1847 * Split out handlers, the default case.
1848 */
1849 [SCIx_ERI_IRQ] = {
1850 .desc = "rx err",
1851 .handler = sci_er_interrupt,
1852 },
1853
1854 [SCIx_RXI_IRQ] = {
1855 .desc = "rx full",
1856 .handler = sci_rx_interrupt,
1857 },
1858
1859 [SCIx_TXI_IRQ] = {
1860 .desc = "tx empty",
1861 .handler = sci_tx_interrupt,
1862 },
1863
1864 [SCIx_BRI_IRQ] = {
1865 .desc = "break",
1866 .handler = sci_br_interrupt,
1867 },
1868
1869 [SCIx_DRI_IRQ] = {
1870 .desc = "rx ready",
1871 .handler = sci_rx_interrupt,
1872 },
1873
1874 [SCIx_TEI_IRQ] = {
1875 .desc = "tx end",
1876 .handler = sci_tx_interrupt,
1877 },
1878
1879 /*
1880 * Special muxed handler.
1881 */
1882 [SCIx_MUX_IRQ] = {
1883 .desc = "mux",
1884 .handler = sci_mpxed_interrupt,
1885 },
1886};
1887
1888static int sci_request_irq(struct sci_port *port)
1889{
1890 struct uart_port *up = &port->port;
1891 int i, j, w, ret = 0;
1892
1893 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1894 const struct sci_irq_desc *desc;
1895 int irq;
1896
1897 /* Check if already registered (muxed) */
1898 for (w = 0; w < i; w++)
1899 if (port->irqs[w] == port->irqs[i])
1900 w = i + 1;
1901 if (w > i)
1902 continue;
1903
1904 if (SCIx_IRQ_IS_MUXED(port)) {
1905 i = SCIx_MUX_IRQ;
1906 irq = up->irq;
1907 } else {
1908 irq = port->irqs[i];
1909
1910 /*
1911 * Certain port types won't support all of the
1912 * available interrupt sources.
1913 */
1914 if (unlikely(irq < 0))
1915 continue;
1916 }
1917
1918 desc = sci_irq_desc + i;
1919 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1920 dev_name(up->dev), desc->desc);
1921 if (!port->irqstr[j]) {
1922 ret = -ENOMEM;
1923 goto out_nomem;
1924 }
1925
1926 ret = request_irq(irq, desc->handler, up->irqflags,
1927 port->irqstr[j], port);
1928 if (unlikely(ret)) {
1929 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1930 goto out_noirq;
1931 }
1932 }
1933
1934 return 0;
1935
1936out_noirq:
1937 while (--i >= 0)
1938 free_irq(port->irqs[i], port);
1939
1940out_nomem:
1941 while (--j >= 0)
1942 kfree(port->irqstr[j]);
1943
1944 return ret;
1945}
1946
1947static void sci_free_irq(struct sci_port *port)
1948{
1949 int i, j;
1950
1951 /*
1952 * Intentionally in reverse order so we iterate over the muxed
1953 * IRQ first.
1954 */
1955 for (i = 0; i < SCIx_NR_IRQS; i++) {
1956 int irq = port->irqs[i];
1957
1958 /*
1959 * Certain port types won't support all of the available
1960 * interrupt sources.
1961 */
1962 if (unlikely(irq < 0))
1963 continue;
1964
1965 /* Check if already freed (irq was muxed) */
1966 for (j = 0; j < i; j++)
1967 if (port->irqs[j] == irq)
1968 j = i + 1;
1969 if (j > i)
1970 continue;
1971
1972 free_irq(port->irqs[i], port);
1973 kfree(port->irqstr[i]);
1974
1975 if (SCIx_IRQ_IS_MUXED(port)) {
1976 /* If there's only one IRQ, we're done. */
1977 return;
1978 }
1979 }
1980}
1981
1982static unsigned int sci_tx_empty(struct uart_port *port)
1983{
1984 unsigned short status = serial_port_in(port, SCxSR);
1985 unsigned short in_tx_fifo = sci_txfill(port);
1986
1987 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1988}
1989
1990static void sci_set_rts(struct uart_port *port, bool state)
1991{
1992 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1993 u16 data = serial_port_in(port, SCPDR);
1994
1995 /* Active low */
1996 if (state)
1997 data &= ~SCPDR_RTSD;
1998 else
1999 data |= SCPDR_RTSD;
2000 serial_port_out(port, SCPDR, data);
2001
2002 /* RTS# is output */
2003 serial_port_out(port, SCPCR,
2004 serial_port_in(port, SCPCR) | SCPCR_RTSC);
2005 } else if (sci_getreg(port, SCSPTR)->size) {
2006 u16 ctrl = serial_port_in(port, SCSPTR);
2007
2008 /* Active low */
2009 if (state)
2010 ctrl &= ~SCSPTR_RTSDT;
2011 else
2012 ctrl |= SCSPTR_RTSDT;
2013 serial_port_out(port, SCSPTR, ctrl);
2014 }
2015}
2016
2017static bool sci_get_cts(struct uart_port *port)
2018{
2019 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2020 /* Active low */
2021 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
2022 } else if (sci_getreg(port, SCSPTR)->size) {
2023 /* Active low */
2024 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
2025 }
2026
2027 return true;
2028}
2029
2030/*
2031 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2032 * CTS/RTS is supported in hardware by at least one port and controlled
2033 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2034 * handled via the ->init_pins() op, which is a bit of a one-way street,
2035 * lacking any ability to defer pin control -- this will later be
2036 * converted over to the GPIO framework).
2037 *
2038 * Other modes (such as loopback) are supported generically on certain
2039 * port types, but not others. For these it's sufficient to test for the
2040 * existence of the support register and simply ignore the port type.
2041 */
2042static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2043{
2044 struct sci_port *s = to_sci_port(port);
2045
2046 if (mctrl & TIOCM_LOOP) {
2047 const struct plat_sci_reg *reg;
2048
2049 /*
2050 * Standard loopback mode for SCFCR ports.
2051 */
2052 reg = sci_getreg(port, SCFCR);
2053 if (reg->size)
2054 serial_port_out(port, SCFCR,
2055 serial_port_in(port, SCFCR) |
2056 SCFCR_LOOP);
2057 }
2058
2059 mctrl_gpio_set(s->gpios, mctrl);
2060
2061 if (!s->has_rtscts)
2062 return;
2063
2064 if (!(mctrl & TIOCM_RTS)) {
2065 /* Disable Auto RTS */
2066 serial_port_out(port, SCFCR,
2067 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2068
2069 /* Clear RTS */
2070 sci_set_rts(port, 0);
2071 } else if (s->autorts) {
2072 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2073 /* Enable RTS# pin function */
2074 serial_port_out(port, SCPCR,
2075 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2076 }
2077
2078 /* Enable Auto RTS */
2079 serial_port_out(port, SCFCR,
2080 serial_port_in(port, SCFCR) | SCFCR_MCE);
2081 } else {
2082 /* Set RTS */
2083 sci_set_rts(port, 1);
2084 }
2085}
2086
2087static unsigned int sci_get_mctrl(struct uart_port *port)
2088{
2089 struct sci_port *s = to_sci_port(port);
2090 struct mctrl_gpios *gpios = s->gpios;
2091 unsigned int mctrl = 0;
2092
2093 mctrl_gpio_get(gpios, &mctrl);
2094
2095 /*
2096 * CTS/RTS is handled in hardware when supported, while nothing
2097 * else is wired up.
2098 */
2099 if (s->autorts) {
2100 if (sci_get_cts(port))
2101 mctrl |= TIOCM_CTS;
2102 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
2103 mctrl |= TIOCM_CTS;
2104 }
2105 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
2106 mctrl |= TIOCM_DSR;
2107 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
2108 mctrl |= TIOCM_CAR;
2109
2110 return mctrl;
2111}
2112
2113static void sci_enable_ms(struct uart_port *port)
2114{
2115 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2116}
2117
2118static void sci_break_ctl(struct uart_port *port, int break_state)
2119{
2120 unsigned short scscr, scsptr;
2121 unsigned long flags;
2122
2123 /* check wheter the port has SCSPTR */
2124 if (!sci_getreg(port, SCSPTR)->size) {
2125 /*
2126 * Not supported by hardware. Most parts couple break and rx
2127 * interrupts together, with break detection always enabled.
2128 */
2129 return;
2130 }
2131
2132 spin_lock_irqsave(&port->lock, flags);
2133 scsptr = serial_port_in(port, SCSPTR);
2134 scscr = serial_port_in(port, SCSCR);
2135
2136 if (break_state == -1) {
2137 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2138 scscr &= ~SCSCR_TE;
2139 } else {
2140 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2141 scscr |= SCSCR_TE;
2142 }
2143
2144 serial_port_out(port, SCSPTR, scsptr);
2145 serial_port_out(port, SCSCR, scscr);
2146 spin_unlock_irqrestore(&port->lock, flags);
2147}
2148
2149static int sci_startup(struct uart_port *port)
2150{
2151 struct sci_port *s = to_sci_port(port);
2152 int ret;
2153
2154 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2155
2156 sci_request_dma(port);
2157
2158 ret = sci_request_irq(s);
2159 if (unlikely(ret < 0)) {
2160 sci_free_dma(port);
2161 return ret;
2162 }
2163
2164 return 0;
2165}
2166
2167static void sci_shutdown(struct uart_port *port)
2168{
2169 struct sci_port *s = to_sci_port(port);
2170 unsigned long flags;
2171 u16 scr;
2172
2173 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2174
2175 s->autorts = false;
2176 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2177
2178 spin_lock_irqsave(&port->lock, flags);
2179 sci_stop_rx(port);
2180 sci_stop_tx(port);
2181 /*
2182 * Stop RX and TX, disable related interrupts, keep clock source
2183 * and HSCIF TOT bits
2184 */
2185 scr = serial_port_in(port, SCSCR);
2186 serial_port_out(port, SCSCR, scr &
2187 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2188 spin_unlock_irqrestore(&port->lock, flags);
2189
2190#ifdef CONFIG_SERIAL_SH_SCI_DMA
2191 if (s->chan_rx_saved) {
2192 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2193 port->line);
2194 hrtimer_cancel(&s->rx_timer);
2195 }
2196#endif
2197
2198 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2199 del_timer_sync(&s->rx_fifo_timer);
2200 sci_free_irq(s);
2201 sci_free_dma(port);
2202}
2203
2204static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2205 unsigned int *srr)
2206{
2207 unsigned long freq = s->clk_rates[SCI_SCK];
2208 int err, min_err = INT_MAX;
2209 unsigned int sr;
2210
2211 if (s->port.type != PORT_HSCIF)
2212 freq *= 2;
2213
2214 for_each_sr(sr, s) {
2215 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2216 if (abs(err) >= abs(min_err))
2217 continue;
2218
2219 min_err = err;
2220 *srr = sr - 1;
2221
2222 if (!err)
2223 break;
2224 }
2225
2226 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2227 *srr + 1);
2228 return min_err;
2229}
2230
2231static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2232 unsigned long freq, unsigned int *dlr,
2233 unsigned int *srr)
2234{
2235 int err, min_err = INT_MAX;
2236 unsigned int sr, dl;
2237
2238 if (s->port.type != PORT_HSCIF)
2239 freq *= 2;
2240
2241 for_each_sr(sr, s) {
2242 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2243 dl = clamp(dl, 1U, 65535U);
2244
2245 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2246 if (abs(err) >= abs(min_err))
2247 continue;
2248
2249 min_err = err;
2250 *dlr = dl;
2251 *srr = sr - 1;
2252
2253 if (!err)
2254 break;
2255 }
2256
2257 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2258 min_err, *dlr, *srr + 1);
2259 return min_err;
2260}
2261
2262/* calculate sample rate, BRR, and clock select */
2263static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2264 unsigned int *brr, unsigned int *srr,
2265 unsigned int *cks)
2266{
2267 unsigned long freq = s->clk_rates[SCI_FCK];
2268 unsigned int sr, br, prediv, scrate, c;
2269 int err, min_err = INT_MAX;
2270
2271 if (s->port.type != PORT_HSCIF)
2272 freq *= 2;
2273
2274 /*
2275 * Find the combination of sample rate and clock select with the
2276 * smallest deviation from the desired baud rate.
2277 * Prefer high sample rates to maximise the receive margin.
2278 *
2279 * M: Receive margin (%)
2280 * N: Ratio of bit rate to clock (N = sampling rate)
2281 * D: Clock duty (D = 0 to 1.0)
2282 * L: Frame length (L = 9 to 12)
2283 * F: Absolute value of clock frequency deviation
2284 *
2285 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2286 * (|D - 0.5| / N * (1 + F))|
2287 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2288 */
2289 for_each_sr(sr, s) {
2290 for (c = 0; c <= 3; c++) {
2291 /* integerized formulas from HSCIF documentation */
2292 prediv = sr * (1 << (2 * c + 1));
2293
2294 /*
2295 * We need to calculate:
2296 *
2297 * br = freq / (prediv * bps) clamped to [1..256]
2298 * err = freq / (br * prediv) - bps
2299 *
2300 * Watch out for overflow when calculating the desired
2301 * sampling clock rate!
2302 */
2303 if (bps > UINT_MAX / prediv)
2304 break;
2305
2306 scrate = prediv * bps;
2307 br = DIV_ROUND_CLOSEST(freq, scrate);
2308 br = clamp(br, 1U, 256U);
2309
2310 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2311 if (abs(err) >= abs(min_err))
2312 continue;
2313
2314 min_err = err;
2315 *brr = br - 1;
2316 *srr = sr - 1;
2317 *cks = c;
2318
2319 if (!err)
2320 goto found;
2321 }
2322 }
2323
2324found:
2325 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2326 min_err, *brr, *srr + 1, *cks);
2327 return min_err;
2328}
2329
2330static void sci_reset(struct uart_port *port)
2331{
2332 const struct plat_sci_reg *reg;
2333 unsigned int status;
2334 struct sci_port *s = to_sci_port(port);
2335
2336 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2337
2338 reg = sci_getreg(port, SCFCR);
2339 if (reg->size)
2340 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2341
2342 sci_clear_SCxSR(port,
2343 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2344 SCxSR_BREAK_CLEAR(port));
2345 if (sci_getreg(port, SCLSR)->size) {
2346 status = serial_port_in(port, SCLSR);
2347 status &= ~(SCLSR_TO | SCLSR_ORER);
2348 serial_port_out(port, SCLSR, status);
2349 }
2350
2351 if (s->rx_trigger > 1) {
2352 if (s->rx_fifo_timeout) {
2353 scif_set_rtrg(port, 1);
2354 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2355 } else {
2356 if (port->type == PORT_SCIFA ||
2357 port->type == PORT_SCIFB)
2358 scif_set_rtrg(port, 1);
2359 else
2360 scif_set_rtrg(port, s->rx_trigger);
2361 }
2362 }
2363}
2364
2365static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2366 struct ktermios *old)
2367{
2368 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2369 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2370 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2371 struct sci_port *s = to_sci_port(port);
2372 const struct plat_sci_reg *reg;
2373 int min_err = INT_MAX, err;
2374 unsigned long max_freq = 0;
2375 int best_clk = -1;
2376 unsigned long flags;
2377
2378 if ((termios->c_cflag & CSIZE) == CS7)
2379 smr_val |= SCSMR_CHR;
2380 if (termios->c_cflag & PARENB)
2381 smr_val |= SCSMR_PE;
2382 if (termios->c_cflag & PARODD)
2383 smr_val |= SCSMR_PE | SCSMR_ODD;
2384 if (termios->c_cflag & CSTOPB)
2385 smr_val |= SCSMR_STOP;
2386
2387 /*
2388 * earlyprintk comes here early on with port->uartclk set to zero.
2389 * the clock framework is not up and running at this point so here
2390 * we assume that 115200 is the maximum baud rate. please note that
2391 * the baud rate is not programmed during earlyprintk - it is assumed
2392 * that the previous boot loader has enabled required clocks and
2393 * setup the baud rate generator hardware for us already.
2394 */
2395 if (!port->uartclk) {
2396 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2397 goto done;
2398 }
2399
2400 for (i = 0; i < SCI_NUM_CLKS; i++)
2401 max_freq = max(max_freq, s->clk_rates[i]);
2402
2403 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2404 if (!baud)
2405 goto done;
2406
2407 /*
2408 * There can be multiple sources for the sampling clock. Find the one
2409 * that gives us the smallest deviation from the desired baud rate.
2410 */
2411
2412 /* Optional Undivided External Clock */
2413 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2414 port->type != PORT_SCIFB) {
2415 err = sci_sck_calc(s, baud, &srr1);
2416 if (abs(err) < abs(min_err)) {
2417 best_clk = SCI_SCK;
2418 scr_val = SCSCR_CKE1;
2419 sccks = SCCKS_CKS;
2420 min_err = err;
2421 srr = srr1;
2422 if (!err)
2423 goto done;
2424 }
2425 }
2426
2427 /* Optional BRG Frequency Divided External Clock */
2428 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2429 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2430 &srr1);
2431 if (abs(err) < abs(min_err)) {
2432 best_clk = SCI_SCIF_CLK;
2433 scr_val = SCSCR_CKE1;
2434 sccks = 0;
2435 min_err = err;
2436 dl = dl1;
2437 srr = srr1;
2438 if (!err)
2439 goto done;
2440 }
2441 }
2442
2443 /* Optional BRG Frequency Divided Internal Clock */
2444 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2445 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2446 &srr1);
2447 if (abs(err) < abs(min_err)) {
2448 best_clk = SCI_BRG_INT;
2449 scr_val = SCSCR_CKE1;
2450 sccks = SCCKS_XIN;
2451 min_err = err;
2452 dl = dl1;
2453 srr = srr1;
2454 if (!min_err)
2455 goto done;
2456 }
2457 }
2458
2459 /* Divided Functional Clock using standard Bit Rate Register */
2460 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2461 if (abs(err) < abs(min_err)) {
2462 best_clk = SCI_FCK;
2463 scr_val = 0;
2464 min_err = err;
2465 brr = brr1;
2466 srr = srr1;
2467 cks = cks1;
2468 }
2469
2470done:
2471 if (best_clk >= 0)
2472 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2473 s->clks[best_clk], baud, min_err);
2474
2475 sci_port_enable(s);
2476
2477 /*
2478 * Program the optional External Baud Rate Generator (BRG) first.
2479 * It controls the mux to select (H)SCK or frequency divided clock.
2480 */
2481 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2482 serial_port_out(port, SCDL, dl);
2483 serial_port_out(port, SCCKS, sccks);
2484 }
2485
2486 spin_lock_irqsave(&port->lock, flags);
2487
2488 sci_reset(port);
2489
2490 uart_update_timeout(port, termios->c_cflag, baud);
2491
2492 /* byte size and parity */
2493 switch (termios->c_cflag & CSIZE) {
2494 case CS5:
2495 bits = 7;
2496 break;
2497 case CS6:
2498 bits = 8;
2499 break;
2500 case CS7:
2501 bits = 9;
2502 break;
2503 default:
2504 bits = 10;
2505 break;
2506 }
2507
2508 if (termios->c_cflag & CSTOPB)
2509 bits++;
2510 if (termios->c_cflag & PARENB)
2511 bits++;
2512
2513 if (best_clk >= 0) {
2514 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2515 switch (srr + 1) {
2516 case 5: smr_val |= SCSMR_SRC_5; break;
2517 case 7: smr_val |= SCSMR_SRC_7; break;
2518 case 11: smr_val |= SCSMR_SRC_11; break;
2519 case 13: smr_val |= SCSMR_SRC_13; break;
2520 case 16: smr_val |= SCSMR_SRC_16; break;
2521 case 17: smr_val |= SCSMR_SRC_17; break;
2522 case 19: smr_val |= SCSMR_SRC_19; break;
2523 case 27: smr_val |= SCSMR_SRC_27; break;
2524 }
2525 smr_val |= cks;
2526 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2527 serial_port_out(port, SCSMR, smr_val);
2528 serial_port_out(port, SCBRR, brr);
2529 if (sci_getreg(port, HSSRR)->size) {
2530 unsigned int hssrr = srr | HSCIF_SRE;
2531 /* Calculate deviation from intended rate at the
2532 * center of the last stop bit in sampling clocks.
2533 */
2534 int last_stop = bits * 2 - 1;
2535 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2536 (int)(srr + 1),
2537 2 * (int)baud);
2538
2539 if (abs(deviation) >= 2) {
2540 /* At least two sampling clocks off at the
2541 * last stop bit; we can increase the error
2542 * margin by shifting the sampling point.
2543 */
2544 int shift = clamp(deviation / 2, -8, 7);
2545
2546 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2547 HSCIF_SRHP_MASK;
2548 hssrr |= HSCIF_SRDE;
2549 }
2550 serial_port_out(port, HSSRR, hssrr);
2551 }
2552
2553 /* Wait one bit interval */
2554 udelay((1000000 + (baud - 1)) / baud);
2555 } else {
2556 /* Don't touch the bit rate configuration */
2557 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2558 smr_val |= serial_port_in(port, SCSMR) &
2559 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2560 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2561 serial_port_out(port, SCSMR, smr_val);
2562 }
2563
2564 sci_init_pins(port, termios->c_cflag);
2565
2566 port->status &= ~UPSTAT_AUTOCTS;
2567 s->autorts = false;
2568 reg = sci_getreg(port, SCFCR);
2569 if (reg->size) {
2570 unsigned short ctrl = serial_port_in(port, SCFCR);
2571
2572 if ((port->flags & UPF_HARD_FLOW) &&
2573 (termios->c_cflag & CRTSCTS)) {
2574 /* There is no CTS interrupt to restart the hardware */
2575 port->status |= UPSTAT_AUTOCTS;
2576 /* MCE is enabled when RTS is raised */
2577 s->autorts = true;
2578 }
2579
2580 /*
2581 * As we've done a sci_reset() above, ensure we don't
2582 * interfere with the FIFOs while toggling MCE. As the
2583 * reset values could still be set, simply mask them out.
2584 */
2585 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2586
2587 serial_port_out(port, SCFCR, ctrl);
2588 }
2589 if (port->flags & UPF_HARD_FLOW) {
2590 /* Refresh (Auto) RTS */
2591 sci_set_mctrl(port, port->mctrl);
2592 }
2593
2594 scr_val |= SCSCR_RE | SCSCR_TE |
2595 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2596 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2597 if ((srr + 1 == 5) &&
2598 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2599 /*
2600 * In asynchronous mode, when the sampling rate is 1/5, first
2601 * received data may become invalid on some SCIFA and SCIFB.
2602 * To avoid this problem wait more than 1 serial data time (1
2603 * bit time x serial data number) after setting SCSCR.RE = 1.
2604 */
2605 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2606 }
2607
2608 /*
2609 * Calculate delay for 2 DMA buffers (4 FIFO).
2610 * See serial_core.c::uart_update_timeout().
2611 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2612 * function calculates 1 jiffie for the data plus 5 jiffies for the
2613 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2614 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2615 * value obtained by this formula is too small. Therefore, if the value
2616 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2617 */
2618 s->rx_frame = (10000 * bits) / (baud / 100);
2619#ifdef CONFIG_SERIAL_SH_SCI_DMA
2620 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2621 if (s->rx_timeout < 20)
2622 s->rx_timeout = 20;
2623#endif
2624
2625 if ((termios->c_cflag & CREAD) != 0)
2626 sci_start_rx(port);
2627
2628 spin_unlock_irqrestore(&port->lock, flags);
2629
2630 sci_port_disable(s);
2631
2632 if (UART_ENABLE_MS(port, termios->c_cflag))
2633 sci_enable_ms(port);
2634}
2635
2636static void sci_pm(struct uart_port *port, unsigned int state,
2637 unsigned int oldstate)
2638{
2639 struct sci_port *sci_port = to_sci_port(port);
2640
2641 switch (state) {
2642 case UART_PM_STATE_OFF:
2643 sci_port_disable(sci_port);
2644 break;
2645 default:
2646 sci_port_enable(sci_port);
2647 break;
2648 }
2649}
2650
2651static const char *sci_type(struct uart_port *port)
2652{
2653 switch (port->type) {
2654 case PORT_IRDA:
2655 return "irda";
2656 case PORT_SCI:
2657 return "sci";
2658 case PORT_SCIF:
2659 return "scif";
2660 case PORT_SCIFA:
2661 return "scifa";
2662 case PORT_SCIFB:
2663 return "scifb";
2664 case PORT_HSCIF:
2665 return "hscif";
2666 }
2667
2668 return NULL;
2669}
2670
2671static int sci_remap_port(struct uart_port *port)
2672{
2673 struct sci_port *sport = to_sci_port(port);
2674
2675 /*
2676 * Nothing to do if there's already an established membase.
2677 */
2678 if (port->membase)
2679 return 0;
2680
2681 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2682 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2683 if (unlikely(!port->membase)) {
2684 dev_err(port->dev, "can't remap port#%d\n", port->line);
2685 return -ENXIO;
2686 }
2687 } else {
2688 /*
2689 * For the simple (and majority of) cases where we don't
2690 * need to do any remapping, just cast the cookie
2691 * directly.
2692 */
2693 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2694 }
2695
2696 return 0;
2697}
2698
2699static void sci_release_port(struct uart_port *port)
2700{
2701 struct sci_port *sport = to_sci_port(port);
2702
2703 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2704 iounmap(port->membase);
2705 port->membase = NULL;
2706 }
2707
2708 release_mem_region(port->mapbase, sport->reg_size);
2709}
2710
2711static int sci_request_port(struct uart_port *port)
2712{
2713 struct resource *res;
2714 struct sci_port *sport = to_sci_port(port);
2715 int ret;
2716
2717 res = request_mem_region(port->mapbase, sport->reg_size,
2718 dev_name(port->dev));
2719 if (unlikely(res == NULL)) {
2720 dev_err(port->dev, "request_mem_region failed.");
2721 return -EBUSY;
2722 }
2723
2724 ret = sci_remap_port(port);
2725 if (unlikely(ret != 0)) {
2726 release_resource(res);
2727 return ret;
2728 }
2729
2730 return 0;
2731}
2732
2733static void sci_config_port(struct uart_port *port, int flags)
2734{
2735 if (flags & UART_CONFIG_TYPE) {
2736 struct sci_port *sport = to_sci_port(port);
2737
2738 port->type = sport->cfg->type;
2739 sci_request_port(port);
2740 }
2741}
2742
2743static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2744{
2745 if (ser->baud_base < 2400)
2746 /* No paper tape reader for Mitch.. */
2747 return -EINVAL;
2748
2749 return 0;
2750}
2751
2752static const struct uart_ops sci_uart_ops = {
2753 .tx_empty = sci_tx_empty,
2754 .set_mctrl = sci_set_mctrl,
2755 .get_mctrl = sci_get_mctrl,
2756 .start_tx = sci_start_tx,
2757 .stop_tx = sci_stop_tx,
2758 .stop_rx = sci_stop_rx,
2759 .enable_ms = sci_enable_ms,
2760 .break_ctl = sci_break_ctl,
2761 .startup = sci_startup,
2762 .shutdown = sci_shutdown,
2763 .flush_buffer = sci_flush_buffer,
2764 .set_termios = sci_set_termios,
2765 .pm = sci_pm,
2766 .type = sci_type,
2767 .release_port = sci_release_port,
2768 .request_port = sci_request_port,
2769 .config_port = sci_config_port,
2770 .verify_port = sci_verify_port,
2771#ifdef CONFIG_CONSOLE_POLL
2772 .poll_get_char = sci_poll_get_char,
2773 .poll_put_char = sci_poll_put_char,
2774#endif
2775};
2776
2777static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2778{
2779 const char *clk_names[] = {
2780 [SCI_FCK] = "fck",
2781 [SCI_SCK] = "sck",
2782 [SCI_BRG_INT] = "brg_int",
2783 [SCI_SCIF_CLK] = "scif_clk",
2784 };
2785 struct clk *clk;
2786 unsigned int i;
2787
2788 if (sci_port->cfg->type == PORT_HSCIF)
2789 clk_names[SCI_SCK] = "hsck";
2790
2791 for (i = 0; i < SCI_NUM_CLKS; i++) {
2792 clk = devm_clk_get(dev, clk_names[i]);
2793 if (PTR_ERR(clk) == -EPROBE_DEFER)
2794 return -EPROBE_DEFER;
2795
2796 if (IS_ERR(clk) && i == SCI_FCK) {
2797 /*
2798 * "fck" used to be called "sci_ick", and we need to
2799 * maintain DT backward compatibility.
2800 */
2801 clk = devm_clk_get(dev, "sci_ick");
2802 if (PTR_ERR(clk) == -EPROBE_DEFER)
2803 return -EPROBE_DEFER;
2804
2805 if (!IS_ERR(clk))
2806 goto found;
2807
2808 /*
2809 * Not all SH platforms declare a clock lookup entry
2810 * for SCI devices, in which case we need to get the
2811 * global "peripheral_clk" clock.
2812 */
2813 clk = devm_clk_get(dev, "peripheral_clk");
2814 if (!IS_ERR(clk))
2815 goto found;
2816
2817 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2818 PTR_ERR(clk));
2819 return PTR_ERR(clk);
2820 }
2821
2822found:
2823 if (IS_ERR(clk))
2824 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2825 PTR_ERR(clk));
2826 else
2827 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2828 clk, clk_get_rate(clk));
2829 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2830 }
2831 return 0;
2832}
2833
2834static const struct sci_port_params *
2835sci_probe_regmap(const struct plat_sci_port *cfg)
2836{
2837 unsigned int regtype;
2838
2839 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2840 return &sci_port_params[cfg->regtype];
2841
2842 switch (cfg->type) {
2843 case PORT_SCI:
2844 regtype = SCIx_SCI_REGTYPE;
2845 break;
2846 case PORT_IRDA:
2847 regtype = SCIx_IRDA_REGTYPE;
2848 break;
2849 case PORT_SCIFA:
2850 regtype = SCIx_SCIFA_REGTYPE;
2851 break;
2852 case PORT_SCIFB:
2853 regtype = SCIx_SCIFB_REGTYPE;
2854 break;
2855 case PORT_SCIF:
2856 /*
2857 * The SH-4 is a bit of a misnomer here, although that's
2858 * where this particular port layout originated. This
2859 * configuration (or some slight variation thereof)
2860 * remains the dominant model for all SCIFs.
2861 */
2862 regtype = SCIx_SH4_SCIF_REGTYPE;
2863 break;
2864 case PORT_HSCIF:
2865 regtype = SCIx_HSCIF_REGTYPE;
2866 break;
2867 default:
2868 pr_err("Can't probe register map for given port\n");
2869 return NULL;
2870 }
2871
2872 return &sci_port_params[regtype];
2873}
2874
2875static int sci_init_single(struct platform_device *dev,
2876 struct sci_port *sci_port, unsigned int index,
2877 const struct plat_sci_port *p, bool early)
2878{
2879 struct uart_port *port = &sci_port->port;
2880 const struct resource *res;
2881 unsigned int i;
2882 int ret;
2883
2884 sci_port->cfg = p;
2885
2886 port->ops = &sci_uart_ops;
2887 port->iotype = UPIO_MEM;
2888 port->line = index;
2889
2890 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2891 if (res == NULL)
2892 return -ENOMEM;
2893
2894 port->mapbase = res->start;
2895 sci_port->reg_size = resource_size(res);
2896
2897 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
2898 if (i)
2899 sci_port->irqs[i] = platform_get_irq_optional(dev, i);
2900 else
2901 sci_port->irqs[i] = platform_get_irq(dev, i);
2902 }
2903
2904 /* The SCI generates several interrupts. They can be muxed together or
2905 * connected to different interrupt lines. In the muxed case only one
2906 * interrupt resource is specified as there is only one interrupt ID.
2907 * In the non-muxed case, up to 6 interrupt signals might be generated
2908 * from the SCI, however those signals might have their own individual
2909 * interrupt ID numbers, or muxed together with another interrupt.
2910 */
2911 if (sci_port->irqs[0] < 0)
2912 return -ENXIO;
2913
2914 if (sci_port->irqs[1] < 0)
2915 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
2916 sci_port->irqs[i] = sci_port->irqs[0];
2917
2918 sci_port->params = sci_probe_regmap(p);
2919 if (unlikely(sci_port->params == NULL))
2920 return -EINVAL;
2921
2922 switch (p->type) {
2923 case PORT_SCIFB:
2924 sci_port->rx_trigger = 48;
2925 break;
2926 case PORT_HSCIF:
2927 sci_port->rx_trigger = 64;
2928 break;
2929 case PORT_SCIFA:
2930 sci_port->rx_trigger = 32;
2931 break;
2932 case PORT_SCIF:
2933 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2934 /* RX triggering not implemented for this IP */
2935 sci_port->rx_trigger = 1;
2936 else
2937 sci_port->rx_trigger = 8;
2938 break;
2939 default:
2940 sci_port->rx_trigger = 1;
2941 break;
2942 }
2943
2944 sci_port->rx_fifo_timeout = 0;
2945 sci_port->hscif_tot = 0;
2946
2947 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2948 * match the SoC datasheet, this should be investigated. Let platform
2949 * data override the sampling rate for now.
2950 */
2951 sci_port->sampling_rate_mask = p->sampling_rate
2952 ? SCI_SR(p->sampling_rate)
2953 : sci_port->params->sampling_rate_mask;
2954
2955 if (!early) {
2956 ret = sci_init_clocks(sci_port, &dev->dev);
2957 if (ret < 0)
2958 return ret;
2959
2960 port->dev = &dev->dev;
2961
2962 pm_runtime_enable(&dev->dev);
2963 }
2964
2965 port->type = p->type;
2966 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2967 port->fifosize = sci_port->params->fifosize;
2968
2969 if (port->type == PORT_SCI) {
2970 if (sci_port->reg_size >= 0x20)
2971 port->regshift = 2;
2972 else
2973 port->regshift = 1;
2974 }
2975
2976 /*
2977 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2978 * for the multi-IRQ ports, which is where we are primarily
2979 * concerned with the shutdown path synchronization.
2980 *
2981 * For the muxed case there's nothing more to do.
2982 */
2983 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2984 port->irqflags = 0;
2985
2986 port->serial_in = sci_serial_in;
2987 port->serial_out = sci_serial_out;
2988
2989 return 0;
2990}
2991
2992static void sci_cleanup_single(struct sci_port *port)
2993{
2994 pm_runtime_disable(port->port.dev);
2995}
2996
2997#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2998 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2999static void serial_console_putchar(struct uart_port *port, int ch)
3000{
3001 sci_poll_put_char(port, ch);
3002}
3003
3004/*
3005 * Print a string to the serial port trying not to disturb
3006 * any possible real use of the port...
3007 */
3008static void serial_console_write(struct console *co, const char *s,
3009 unsigned count)
3010{
3011 struct sci_port *sci_port = &sci_ports[co->index];
3012 struct uart_port *port = &sci_port->port;
3013 unsigned short bits, ctrl, ctrl_temp;
3014 unsigned long flags;
3015 int locked = 1;
3016
3017#if defined(SUPPORT_SYSRQ)
3018 if (port->sysrq)
3019 locked = 0;
3020 else
3021#endif
3022 if (oops_in_progress)
3023 locked = spin_trylock_irqsave(&port->lock, flags);
3024 else
3025 spin_lock_irqsave(&port->lock, flags);
3026
3027 /* first save SCSCR then disable interrupts, keep clock source */
3028 ctrl = serial_port_in(port, SCSCR);
3029 ctrl_temp = SCSCR_RE | SCSCR_TE |
3030 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
3031 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
3032 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
3033
3034 uart_console_write(port, s, count, serial_console_putchar);
3035
3036 /* wait until fifo is empty and last bit has been transmitted */
3037 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3038 while ((serial_port_in(port, SCxSR) & bits) != bits)
3039 cpu_relax();
3040
3041 /* restore the SCSCR */
3042 serial_port_out(port, SCSCR, ctrl);
3043
3044 if (locked)
3045 spin_unlock_irqrestore(&port->lock, flags);
3046}
3047
3048static int serial_console_setup(struct console *co, char *options)
3049{
3050 struct sci_port *sci_port;
3051 struct uart_port *port;
3052 int baud = 115200;
3053 int bits = 8;
3054 int parity = 'n';
3055 int flow = 'n';
3056 int ret;
3057
3058 /*
3059 * Refuse to handle any bogus ports.
3060 */
3061 if (co->index < 0 || co->index >= SCI_NPORTS)
3062 return -ENODEV;
3063
3064 sci_port = &sci_ports[co->index];
3065 port = &sci_port->port;
3066
3067 /*
3068 * Refuse to handle uninitialized ports.
3069 */
3070 if (!port->ops)
3071 return -ENODEV;
3072
3073 ret = sci_remap_port(port);
3074 if (unlikely(ret != 0))
3075 return ret;
3076
3077 if (options)
3078 uart_parse_options(options, &baud, &parity, &bits, &flow);
3079
3080 return uart_set_options(port, co, baud, parity, bits, flow);
3081}
3082
3083static struct console serial_console = {
3084 .name = "ttySC",
3085 .device = uart_console_device,
3086 .write = serial_console_write,
3087 .setup = serial_console_setup,
3088 .flags = CON_PRINTBUFFER,
3089 .index = -1,
3090 .data = &sci_uart_driver,
3091};
3092
3093static struct console early_serial_console = {
3094 .name = "early_ttySC",
3095 .write = serial_console_write,
3096 .flags = CON_PRINTBUFFER,
3097 .index = -1,
3098};
3099
3100static char early_serial_buf[32];
3101
3102static int sci_probe_earlyprintk(struct platform_device *pdev)
3103{
3104 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3105
3106 if (early_serial_console.data)
3107 return -EEXIST;
3108
3109 early_serial_console.index = pdev->id;
3110
3111 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3112
3113 serial_console_setup(&early_serial_console, early_serial_buf);
3114
3115 if (!strstr(early_serial_buf, "keep"))
3116 early_serial_console.flags |= CON_BOOT;
3117
3118 register_console(&early_serial_console);
3119 return 0;
3120}
3121
3122#define SCI_CONSOLE (&serial_console)
3123
3124#else
3125static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3126{
3127 return -EINVAL;
3128}
3129
3130#define SCI_CONSOLE NULL
3131
3132#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3133
3134static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3135
3136static DEFINE_MUTEX(sci_uart_registration_lock);
3137static struct uart_driver sci_uart_driver = {
3138 .owner = THIS_MODULE,
3139 .driver_name = "sci",
3140 .dev_name = "ttySC",
3141 .major = SCI_MAJOR,
3142 .minor = SCI_MINOR_START,
3143 .nr = SCI_NPORTS,
3144 .cons = SCI_CONSOLE,
3145};
3146
3147static int sci_remove(struct platform_device *dev)
3148{
3149 struct sci_port *port = platform_get_drvdata(dev);
3150 unsigned int type = port->port.type; /* uart_remove_... clears it */
3151
3152 sci_ports_in_use &= ~BIT(port->port.line);
3153 uart_remove_one_port(&sci_uart_driver, &port->port);
3154
3155 sci_cleanup_single(port);
3156
3157 if (port->port.fifosize > 1)
3158 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3159 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
3160 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3161
3162 return 0;
3163}
3164
3165
3166#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3167#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3168#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3169
3170static const struct of_device_id of_sci_match[] = {
3171 /* SoC-specific types */
3172 {
3173 .compatible = "renesas,scif-r7s72100",
3174 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3175 },
3176 {
3177 .compatible = "renesas,scif-r7s9210",
3178 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3179 },
3180 /* Family-specific types */
3181 {
3182 .compatible = "renesas,rcar-gen1-scif",
3183 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3184 }, {
3185 .compatible = "renesas,rcar-gen2-scif",
3186 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3187 }, {
3188 .compatible = "renesas,rcar-gen3-scif",
3189 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3190 },
3191 /* Generic types */
3192 {
3193 .compatible = "renesas,scif",
3194 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3195 }, {
3196 .compatible = "renesas,scifa",
3197 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3198 }, {
3199 .compatible = "renesas,scifb",
3200 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3201 }, {
3202 .compatible = "renesas,hscif",
3203 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3204 }, {
3205 .compatible = "renesas,sci",
3206 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3207 }, {
3208 /* Terminator */
3209 },
3210};
3211MODULE_DEVICE_TABLE(of, of_sci_match);
3212
3213static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3214 unsigned int *dev_id)
3215{
3216 struct device_node *np = pdev->dev.of_node;
3217 struct plat_sci_port *p;
3218 struct sci_port *sp;
3219 const void *data;
3220 int id;
3221
3222 if (!IS_ENABLED(CONFIG_OF) || !np)
3223 return NULL;
3224
3225 data = of_device_get_match_data(&pdev->dev);
3226
3227 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3228 if (!p)
3229 return NULL;
3230
3231 /* Get the line number from the aliases node. */
3232 id = of_alias_get_id(np, "serial");
3233 if (id < 0 && ~sci_ports_in_use)
3234 id = ffz(sci_ports_in_use);
3235 if (id < 0) {
3236 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3237 return NULL;
3238 }
3239 if (id >= ARRAY_SIZE(sci_ports)) {
3240 dev_err(&pdev->dev, "serial%d out of range\n", id);
3241 return NULL;
3242 }
3243
3244 sp = &sci_ports[id];
3245 *dev_id = id;
3246
3247 p->type = SCI_OF_TYPE(data);
3248 p->regtype = SCI_OF_REGTYPE(data);
3249
3250 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3251
3252 return p;
3253}
3254
3255static int sci_probe_single(struct platform_device *dev,
3256 unsigned int index,
3257 struct plat_sci_port *p,
3258 struct sci_port *sciport)
3259{
3260 int ret;
3261
3262 /* Sanity check */
3263 if (unlikely(index >= SCI_NPORTS)) {
3264 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3265 index+1, SCI_NPORTS);
3266 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3267 return -EINVAL;
3268 }
3269 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3270 if (sci_ports_in_use & BIT(index))
3271 return -EBUSY;
3272
3273 mutex_lock(&sci_uart_registration_lock);
3274 if (!sci_uart_driver.state) {
3275 ret = uart_register_driver(&sci_uart_driver);
3276 if (ret) {
3277 mutex_unlock(&sci_uart_registration_lock);
3278 return ret;
3279 }
3280 }
3281 mutex_unlock(&sci_uart_registration_lock);
3282
3283 ret = sci_init_single(dev, sciport, index, p, false);
3284 if (ret)
3285 return ret;
3286
3287 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3288 if (IS_ERR(sciport->gpios))
3289 return PTR_ERR(sciport->gpios);
3290
3291 if (sciport->has_rtscts) {
3292 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
3293 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
3294 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3295 return -EINVAL;
3296 }
3297 sciport->port.flags |= UPF_HARD_FLOW;
3298 }
3299
3300 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3301 if (ret) {
3302 sci_cleanup_single(sciport);
3303 return ret;
3304 }
3305
3306 return 0;
3307}
3308
3309static int sci_probe(struct platform_device *dev)
3310{
3311 struct plat_sci_port *p;
3312 struct sci_port *sp;
3313 unsigned int dev_id;
3314 int ret;
3315
3316 /*
3317 * If we've come here via earlyprintk initialization, head off to
3318 * the special early probe. We don't have sufficient device state
3319 * to make it beyond this yet.
3320 */
3321 if (is_early_platform_device(dev))
3322 return sci_probe_earlyprintk(dev);
3323
3324 if (dev->dev.of_node) {
3325 p = sci_parse_dt(dev, &dev_id);
3326 if (p == NULL)
3327 return -EINVAL;
3328 } else {
3329 p = dev->dev.platform_data;
3330 if (p == NULL) {
3331 dev_err(&dev->dev, "no platform data supplied\n");
3332 return -EINVAL;
3333 }
3334
3335 dev_id = dev->id;
3336 }
3337
3338 sp = &sci_ports[dev_id];
3339 platform_set_drvdata(dev, sp);
3340
3341 ret = sci_probe_single(dev, dev_id, p, sp);
3342 if (ret)
3343 return ret;
3344
3345 if (sp->port.fifosize > 1) {
3346 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3347 if (ret)
3348 return ret;
3349 }
3350 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3351 sp->port.type == PORT_HSCIF) {
3352 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3353 if (ret) {
3354 if (sp->port.fifosize > 1) {
3355 device_remove_file(&dev->dev,
3356 &dev_attr_rx_fifo_trigger);
3357 }
3358 return ret;
3359 }
3360 }
3361
3362#ifdef CONFIG_SH_STANDARD_BIOS
3363 sh_bios_gdb_detach();
3364#endif
3365
3366 sci_ports_in_use |= BIT(dev_id);
3367 return 0;
3368}
3369
3370static __maybe_unused int sci_suspend(struct device *dev)
3371{
3372 struct sci_port *sport = dev_get_drvdata(dev);
3373
3374 if (sport)
3375 uart_suspend_port(&sci_uart_driver, &sport->port);
3376
3377 return 0;
3378}
3379
3380static __maybe_unused int sci_resume(struct device *dev)
3381{
3382 struct sci_port *sport = dev_get_drvdata(dev);
3383
3384 if (sport)
3385 uart_resume_port(&sci_uart_driver, &sport->port);
3386
3387 return 0;
3388}
3389
3390static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3391
3392static struct platform_driver sci_driver = {
3393 .probe = sci_probe,
3394 .remove = sci_remove,
3395 .driver = {
3396 .name = "sh-sci",
3397 .pm = &sci_dev_pm_ops,
3398 .of_match_table = of_match_ptr(of_sci_match),
3399 },
3400};
3401
3402static int __init sci_init(void)
3403{
3404 pr_info("%s\n", banner);
3405
3406 return platform_driver_register(&sci_driver);
3407}
3408
3409static void __exit sci_exit(void)
3410{
3411 platform_driver_unregister(&sci_driver);
3412
3413 if (sci_uart_driver.state)
3414 uart_unregister_driver(&sci_uart_driver);
3415}
3416
3417#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3418early_platform_init_buffer("earlyprintk", &sci_driver,
3419 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3420#endif
3421#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3422static struct plat_sci_port port_cfg __initdata;
3423
3424static int __init early_console_setup(struct earlycon_device *device,
3425 int type)
3426{
3427 if (!device->port.membase)
3428 return -ENODEV;
3429
3430 device->port.serial_in = sci_serial_in;
3431 device->port.serial_out = sci_serial_out;
3432 device->port.type = type;
3433 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3434 port_cfg.type = type;
3435 sci_ports[0].cfg = &port_cfg;
3436 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3437 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3438 sci_serial_out(&sci_ports[0].port, SCSCR,
3439 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3440
3441 device->con->write = serial_console_write;
3442 return 0;
3443}
3444static int __init sci_early_console_setup(struct earlycon_device *device,
3445 const char *opt)
3446{
3447 return early_console_setup(device, PORT_SCI);
3448}
3449static int __init scif_early_console_setup(struct earlycon_device *device,
3450 const char *opt)
3451{
3452 return early_console_setup(device, PORT_SCIF);
3453}
3454static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3455 const char *opt)
3456{
3457 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3458 return early_console_setup(device, PORT_SCIF);
3459}
3460static int __init scifa_early_console_setup(struct earlycon_device *device,
3461 const char *opt)
3462{
3463 return early_console_setup(device, PORT_SCIFA);
3464}
3465static int __init scifb_early_console_setup(struct earlycon_device *device,
3466 const char *opt)
3467{
3468 return early_console_setup(device, PORT_SCIFB);
3469}
3470static int __init hscif_early_console_setup(struct earlycon_device *device,
3471 const char *opt)
3472{
3473 return early_console_setup(device, PORT_HSCIF);
3474}
3475
3476OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3477OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3478OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3479OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3480OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3481OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3482#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3483
3484module_init(sci_init);
3485module_exit(sci_exit);
3486
3487MODULE_LICENSE("GPL");
3488MODULE_ALIAS("platform:sh-sci");
3489MODULE_AUTHOR("Paul Mundt");
3490MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 */
18#undef DEBUG
19
20#include <linux/clk.h>
21#include <linux/console.h>
22#include <linux/ctype.h>
23#include <linux/cpufreq.h>
24#include <linux/delay.h>
25#include <linux/dmaengine.h>
26#include <linux/dma-mapping.h>
27#include <linux/err.h>
28#include <linux/errno.h>
29#include <linux/init.h>
30#include <linux/interrupt.h>
31#include <linux/ioport.h>
32#include <linux/ktime.h>
33#include <linux/major.h>
34#include <linux/minmax.h>
35#include <linux/module.h>
36#include <linux/mm.h>
37#include <linux/of.h>
38#include <linux/platform_device.h>
39#include <linux/pm_runtime.h>
40#include <linux/reset.h>
41#include <linux/scatterlist.h>
42#include <linux/serial.h>
43#include <linux/serial_sci.h>
44#include <linux/sh_dma.h>
45#include <linux/slab.h>
46#include <linux/string.h>
47#include <linux/sysrq.h>
48#include <linux/timer.h>
49#include <linux/tty.h>
50#include <linux/tty_flip.h>
51
52#ifdef CONFIG_SUPERH
53#include <asm/sh_bios.h>
54#include <asm/platform_early.h>
55#endif
56
57#include "serial_mctrl_gpio.h"
58#include "sh-sci.h"
59
60/* Offsets into the sci_port->irqs array */
61enum {
62 SCIx_ERI_IRQ,
63 SCIx_RXI_IRQ,
64 SCIx_TXI_IRQ,
65 SCIx_BRI_IRQ,
66 SCIx_DRI_IRQ,
67 SCIx_TEI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
79enum SCI_CLKS {
80 SCI_FCK, /* Functional Clock */
81 SCI_SCK, /* Optional External Clock */
82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
84 SCI_NUM_CLKS
85};
86
87/* Bit x set means sampling rate x + 1 is supported */
88#define SCI_SR(x) BIT((x) - 1)
89#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
90
91#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
93 SCI_SR(19) | SCI_SR(27)
94
95#define min_sr(_port) ffs((_port)->sampling_rate_mask)
96#define max_sr(_port) fls((_port)->sampling_rate_mask)
97
98/* Iterate over all supported sampling rates, from high to low */
99#define for_each_sr(_sr, _port) \
100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
101 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
102
103struct plat_sci_reg {
104 u8 offset, size;
105};
106
107struct sci_port_params {
108 const struct plat_sci_reg regs[SCIx_NR_REGS];
109 unsigned int fifosize;
110 unsigned int overrun_reg;
111 unsigned int overrun_mask;
112 unsigned int sampling_rate_mask;
113 unsigned int error_mask;
114 unsigned int error_clear;
115};
116
117struct sci_port {
118 struct uart_port port;
119
120 /* Platform configuration */
121 const struct sci_port_params *params;
122 const struct plat_sci_port *cfg;
123 unsigned int sampling_rate_mask;
124 resource_size_t reg_size;
125 struct mctrl_gpios *gpios;
126
127 /* Clocks */
128 struct clk *clks[SCI_NUM_CLKS];
129 unsigned long clk_rates[SCI_NUM_CLKS];
130
131 int irqs[SCIx_NR_IRQS];
132 char *irqstr[SCIx_NR_IRQS];
133
134 struct dma_chan *chan_tx;
135 struct dma_chan *chan_rx;
136
137#ifdef CONFIG_SERIAL_SH_SCI_DMA
138 struct dma_chan *chan_tx_saved;
139 struct dma_chan *chan_rx_saved;
140 dma_cookie_t cookie_tx;
141 dma_cookie_t cookie_rx[2];
142 dma_cookie_t active_rx;
143 dma_addr_t tx_dma_addr;
144 unsigned int tx_dma_len;
145 struct scatterlist sg_rx[2];
146 void *rx_buf[2];
147 size_t buf_len_rx;
148 struct work_struct work_tx;
149 struct hrtimer rx_timer;
150 unsigned int rx_timeout; /* microseconds */
151#endif
152 unsigned int rx_frame;
153 int rx_trigger;
154 struct timer_list rx_fifo_timer;
155 int rx_fifo_timeout;
156 u16 hscif_tot;
157
158 bool has_rtscts;
159 bool autorts;
160};
161
162#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
163
164static struct sci_port sci_ports[SCI_NPORTS];
165static unsigned long sci_ports_in_use;
166static struct uart_driver sci_uart_driver;
167
168static inline struct sci_port *
169to_sci_port(struct uart_port *uart)
170{
171 return container_of(uart, struct sci_port, port);
172}
173
174static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
175 /*
176 * Common SCI definitions, dependent on the port's regshift
177 * value.
178 */
179 [SCIx_SCI_REGTYPE] = {
180 .regs = {
181 [SCSMR] = { 0x00, 8 },
182 [SCBRR] = { 0x01, 8 },
183 [SCSCR] = { 0x02, 8 },
184 [SCxTDR] = { 0x03, 8 },
185 [SCxSR] = { 0x04, 8 },
186 [SCxRDR] = { 0x05, 8 },
187 },
188 .fifosize = 1,
189 .overrun_reg = SCxSR,
190 .overrun_mask = SCI_ORER,
191 .sampling_rate_mask = SCI_SR(32),
192 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
193 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
194 },
195
196 /*
197 * Common definitions for legacy IrDA ports.
198 */
199 [SCIx_IRDA_REGTYPE] = {
200 .regs = {
201 [SCSMR] = { 0x00, 8 },
202 [SCBRR] = { 0x02, 8 },
203 [SCSCR] = { 0x04, 8 },
204 [SCxTDR] = { 0x06, 8 },
205 [SCxSR] = { 0x08, 16 },
206 [SCxRDR] = { 0x0a, 8 },
207 [SCFCR] = { 0x0c, 8 },
208 [SCFDR] = { 0x0e, 16 },
209 },
210 .fifosize = 1,
211 .overrun_reg = SCxSR,
212 .overrun_mask = SCI_ORER,
213 .sampling_rate_mask = SCI_SR(32),
214 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
215 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
216 },
217
218 /*
219 * Common SCIFA definitions.
220 */
221 [SCIx_SCIFA_REGTYPE] = {
222 .regs = {
223 [SCSMR] = { 0x00, 16 },
224 [SCBRR] = { 0x04, 8 },
225 [SCSCR] = { 0x08, 16 },
226 [SCxTDR] = { 0x20, 8 },
227 [SCxSR] = { 0x14, 16 },
228 [SCxRDR] = { 0x24, 8 },
229 [SCFCR] = { 0x18, 16 },
230 [SCFDR] = { 0x1c, 16 },
231 [SCPCR] = { 0x30, 16 },
232 [SCPDR] = { 0x34, 16 },
233 },
234 .fifosize = 64,
235 .overrun_reg = SCxSR,
236 .overrun_mask = SCIFA_ORER,
237 .sampling_rate_mask = SCI_SR_SCIFAB,
238 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
239 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
240 },
241
242 /*
243 * Common SCIFB definitions.
244 */
245 [SCIx_SCIFB_REGTYPE] = {
246 .regs = {
247 [SCSMR] = { 0x00, 16 },
248 [SCBRR] = { 0x04, 8 },
249 [SCSCR] = { 0x08, 16 },
250 [SCxTDR] = { 0x40, 8 },
251 [SCxSR] = { 0x14, 16 },
252 [SCxRDR] = { 0x60, 8 },
253 [SCFCR] = { 0x18, 16 },
254 [SCTFDR] = { 0x38, 16 },
255 [SCRFDR] = { 0x3c, 16 },
256 [SCPCR] = { 0x30, 16 },
257 [SCPDR] = { 0x34, 16 },
258 },
259 .fifosize = 256,
260 .overrun_reg = SCxSR,
261 .overrun_mask = SCIFA_ORER,
262 .sampling_rate_mask = SCI_SR_SCIFAB,
263 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
264 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
265 },
266
267 /*
268 * Common SH-2(A) SCIF definitions for ports with FIFO data
269 * count registers.
270 */
271 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
272 .regs = {
273 [SCSMR] = { 0x00, 16 },
274 [SCBRR] = { 0x04, 8 },
275 [SCSCR] = { 0x08, 16 },
276 [SCxTDR] = { 0x0c, 8 },
277 [SCxSR] = { 0x10, 16 },
278 [SCxRDR] = { 0x14, 8 },
279 [SCFCR] = { 0x18, 16 },
280 [SCFDR] = { 0x1c, 16 },
281 [SCSPTR] = { 0x20, 16 },
282 [SCLSR] = { 0x24, 16 },
283 },
284 .fifosize = 16,
285 .overrun_reg = SCLSR,
286 .overrun_mask = SCLSR_ORER,
287 .sampling_rate_mask = SCI_SR(32),
288 .error_mask = SCIF_DEFAULT_ERROR_MASK,
289 .error_clear = SCIF_ERROR_CLEAR,
290 },
291
292 /*
293 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T.
294 * It looks like a normal SCIF with FIFO data, but with a
295 * compressed address space. Also, the break out of interrupts
296 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
297 */
298 [SCIx_RZ_SCIFA_REGTYPE] = {
299 .regs = {
300 [SCSMR] = { 0x00, 16 },
301 [SCBRR] = { 0x02, 8 },
302 [SCSCR] = { 0x04, 16 },
303 [SCxTDR] = { 0x06, 8 },
304 [SCxSR] = { 0x08, 16 },
305 [SCxRDR] = { 0x0A, 8 },
306 [SCFCR] = { 0x0C, 16 },
307 [SCFDR] = { 0x0E, 16 },
308 [SCSPTR] = { 0x10, 16 },
309 [SCLSR] = { 0x12, 16 },
310 [SEMR] = { 0x14, 8 },
311 },
312 .fifosize = 16,
313 .overrun_reg = SCLSR,
314 .overrun_mask = SCLSR_ORER,
315 .sampling_rate_mask = SCI_SR(32),
316 .error_mask = SCIF_DEFAULT_ERROR_MASK,
317 .error_clear = SCIF_ERROR_CLEAR,
318 },
319
320 /*
321 * Common SH-3 SCIF definitions.
322 */
323 [SCIx_SH3_SCIF_REGTYPE] = {
324 .regs = {
325 [SCSMR] = { 0x00, 8 },
326 [SCBRR] = { 0x02, 8 },
327 [SCSCR] = { 0x04, 8 },
328 [SCxTDR] = { 0x06, 8 },
329 [SCxSR] = { 0x08, 16 },
330 [SCxRDR] = { 0x0a, 8 },
331 [SCFCR] = { 0x0c, 8 },
332 [SCFDR] = { 0x0e, 16 },
333 },
334 .fifosize = 16,
335 .overrun_reg = SCLSR,
336 .overrun_mask = SCLSR_ORER,
337 .sampling_rate_mask = SCI_SR(32),
338 .error_mask = SCIF_DEFAULT_ERROR_MASK,
339 .error_clear = SCIF_ERROR_CLEAR,
340 },
341
342 /*
343 * Common SH-4(A) SCIF(B) definitions.
344 */
345 [SCIx_SH4_SCIF_REGTYPE] = {
346 .regs = {
347 [SCSMR] = { 0x00, 16 },
348 [SCBRR] = { 0x04, 8 },
349 [SCSCR] = { 0x08, 16 },
350 [SCxTDR] = { 0x0c, 8 },
351 [SCxSR] = { 0x10, 16 },
352 [SCxRDR] = { 0x14, 8 },
353 [SCFCR] = { 0x18, 16 },
354 [SCFDR] = { 0x1c, 16 },
355 [SCSPTR] = { 0x20, 16 },
356 [SCLSR] = { 0x24, 16 },
357 },
358 .fifosize = 16,
359 .overrun_reg = SCLSR,
360 .overrun_mask = SCLSR_ORER,
361 .sampling_rate_mask = SCI_SR(32),
362 .error_mask = SCIF_DEFAULT_ERROR_MASK,
363 .error_clear = SCIF_ERROR_CLEAR,
364 },
365
366 /*
367 * Common SCIF definitions for ports with a Baud Rate Generator for
368 * External Clock (BRG).
369 */
370 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
371 .regs = {
372 [SCSMR] = { 0x00, 16 },
373 [SCBRR] = { 0x04, 8 },
374 [SCSCR] = { 0x08, 16 },
375 [SCxTDR] = { 0x0c, 8 },
376 [SCxSR] = { 0x10, 16 },
377 [SCxRDR] = { 0x14, 8 },
378 [SCFCR] = { 0x18, 16 },
379 [SCFDR] = { 0x1c, 16 },
380 [SCSPTR] = { 0x20, 16 },
381 [SCLSR] = { 0x24, 16 },
382 [SCDL] = { 0x30, 16 },
383 [SCCKS] = { 0x34, 16 },
384 },
385 .fifosize = 16,
386 .overrun_reg = SCLSR,
387 .overrun_mask = SCLSR_ORER,
388 .sampling_rate_mask = SCI_SR(32),
389 .error_mask = SCIF_DEFAULT_ERROR_MASK,
390 .error_clear = SCIF_ERROR_CLEAR,
391 },
392
393 /*
394 * Common HSCIF definitions.
395 */
396 [SCIx_HSCIF_REGTYPE] = {
397 .regs = {
398 [SCSMR] = { 0x00, 16 },
399 [SCBRR] = { 0x04, 8 },
400 [SCSCR] = { 0x08, 16 },
401 [SCxTDR] = { 0x0c, 8 },
402 [SCxSR] = { 0x10, 16 },
403 [SCxRDR] = { 0x14, 8 },
404 [SCFCR] = { 0x18, 16 },
405 [SCFDR] = { 0x1c, 16 },
406 [SCSPTR] = { 0x20, 16 },
407 [SCLSR] = { 0x24, 16 },
408 [HSSRR] = { 0x40, 16 },
409 [SCDL] = { 0x30, 16 },
410 [SCCKS] = { 0x34, 16 },
411 [HSRTRGR] = { 0x54, 16 },
412 [HSTTRGR] = { 0x58, 16 },
413 },
414 .fifosize = 128,
415 .overrun_reg = SCLSR,
416 .overrun_mask = SCLSR_ORER,
417 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
418 .error_mask = SCIF_DEFAULT_ERROR_MASK,
419 .error_clear = SCIF_ERROR_CLEAR,
420 },
421
422 /*
423 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
424 * register.
425 */
426 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
427 .regs = {
428 [SCSMR] = { 0x00, 16 },
429 [SCBRR] = { 0x04, 8 },
430 [SCSCR] = { 0x08, 16 },
431 [SCxTDR] = { 0x0c, 8 },
432 [SCxSR] = { 0x10, 16 },
433 [SCxRDR] = { 0x14, 8 },
434 [SCFCR] = { 0x18, 16 },
435 [SCFDR] = { 0x1c, 16 },
436 [SCLSR] = { 0x24, 16 },
437 },
438 .fifosize = 16,
439 .overrun_reg = SCLSR,
440 .overrun_mask = SCLSR_ORER,
441 .sampling_rate_mask = SCI_SR(32),
442 .error_mask = SCIF_DEFAULT_ERROR_MASK,
443 .error_clear = SCIF_ERROR_CLEAR,
444 },
445
446 /*
447 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
448 * count registers.
449 */
450 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
451 .regs = {
452 [SCSMR] = { 0x00, 16 },
453 [SCBRR] = { 0x04, 8 },
454 [SCSCR] = { 0x08, 16 },
455 [SCxTDR] = { 0x0c, 8 },
456 [SCxSR] = { 0x10, 16 },
457 [SCxRDR] = { 0x14, 8 },
458 [SCFCR] = { 0x18, 16 },
459 [SCFDR] = { 0x1c, 16 },
460 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
461 [SCRFDR] = { 0x20, 16 },
462 [SCSPTR] = { 0x24, 16 },
463 [SCLSR] = { 0x28, 16 },
464 },
465 .fifosize = 16,
466 .overrun_reg = SCLSR,
467 .overrun_mask = SCLSR_ORER,
468 .sampling_rate_mask = SCI_SR(32),
469 .error_mask = SCIF_DEFAULT_ERROR_MASK,
470 .error_clear = SCIF_ERROR_CLEAR,
471 },
472
473 /*
474 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
475 * registers.
476 */
477 [SCIx_SH7705_SCIF_REGTYPE] = {
478 .regs = {
479 [SCSMR] = { 0x00, 16 },
480 [SCBRR] = { 0x04, 8 },
481 [SCSCR] = { 0x08, 16 },
482 [SCxTDR] = { 0x20, 8 },
483 [SCxSR] = { 0x14, 16 },
484 [SCxRDR] = { 0x24, 8 },
485 [SCFCR] = { 0x18, 16 },
486 [SCFDR] = { 0x1c, 16 },
487 },
488 .fifosize = 64,
489 .overrun_reg = SCxSR,
490 .overrun_mask = SCIFA_ORER,
491 .sampling_rate_mask = SCI_SR(16),
492 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
493 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
494 },
495};
496
497#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
498
499/*
500 * The "offset" here is rather misleading, in that it refers to an enum
501 * value relative to the port mapping rather than the fixed offset
502 * itself, which needs to be manually retrieved from the platform's
503 * register map for the given port.
504 */
505static unsigned int sci_serial_in(struct uart_port *p, int offset)
506{
507 const struct plat_sci_reg *reg = sci_getreg(p, offset);
508
509 if (reg->size == 8)
510 return ioread8(p->membase + (reg->offset << p->regshift));
511 else if (reg->size == 16)
512 return ioread16(p->membase + (reg->offset << p->regshift));
513 else
514 WARN(1, "Invalid register access\n");
515
516 return 0;
517}
518
519static void sci_serial_out(struct uart_port *p, int offset, int value)
520{
521 const struct plat_sci_reg *reg = sci_getreg(p, offset);
522
523 if (reg->size == 8)
524 iowrite8(value, p->membase + (reg->offset << p->regshift));
525 else if (reg->size == 16)
526 iowrite16(value, p->membase + (reg->offset << p->regshift));
527 else
528 WARN(1, "Invalid register access\n");
529}
530
531static void sci_port_enable(struct sci_port *sci_port)
532{
533 unsigned int i;
534
535 if (!sci_port->port.dev)
536 return;
537
538 pm_runtime_get_sync(sci_port->port.dev);
539
540 for (i = 0; i < SCI_NUM_CLKS; i++) {
541 clk_prepare_enable(sci_port->clks[i]);
542 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
543 }
544 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
545}
546
547static void sci_port_disable(struct sci_port *sci_port)
548{
549 unsigned int i;
550
551 if (!sci_port->port.dev)
552 return;
553
554 for (i = SCI_NUM_CLKS; i-- > 0; )
555 clk_disable_unprepare(sci_port->clks[i]);
556
557 pm_runtime_put_sync(sci_port->port.dev);
558}
559
560static inline unsigned long port_rx_irq_mask(struct uart_port *port)
561{
562 /*
563 * Not all ports (such as SCIFA) will support REIE. Rather than
564 * special-casing the port type, we check the port initialization
565 * IRQ enable mask to see whether the IRQ is desired at all. If
566 * it's unset, it's logically inferred that there's no point in
567 * testing for it.
568 */
569 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
570}
571
572static void sci_start_tx(struct uart_port *port)
573{
574 struct sci_port *s = to_sci_port(port);
575 unsigned short ctrl;
576
577#ifdef CONFIG_SERIAL_SH_SCI_DMA
578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
579 u16 new, scr = sci_serial_in(port, SCSCR);
580 if (s->chan_tx)
581 new = scr | SCSCR_TDRQE;
582 else
583 new = scr & ~SCSCR_TDRQE;
584 if (new != scr)
585 sci_serial_out(port, SCSCR, new);
586 }
587
588 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
589 dma_submit_error(s->cookie_tx)) {
590 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
591 /* Switch irq from SCIF to DMA */
592 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]);
593
594 s->cookie_tx = 0;
595 schedule_work(&s->work_tx);
596 }
597#endif
598
599 if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE ||
600 port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
601 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
602 ctrl = sci_serial_in(port, SCSCR);
603
604 /*
605 * For SCI, TE (transmit enable) must be set after setting TIE
606 * (transmit interrupt enable) or in the same instruction to start
607 * the transmit process.
608 */
609 if (port->type == PORT_SCI)
610 ctrl |= SCSCR_TE;
611
612 sci_serial_out(port, SCSCR, ctrl | SCSCR_TIE);
613 }
614}
615
616static void sci_stop_tx(struct uart_port *port)
617{
618 unsigned short ctrl;
619
620 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
621 ctrl = sci_serial_in(port, SCSCR);
622
623 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
624 ctrl &= ~SCSCR_TDRQE;
625
626 ctrl &= ~SCSCR_TIE;
627
628 sci_serial_out(port, SCSCR, ctrl);
629
630#ifdef CONFIG_SERIAL_SH_SCI_DMA
631 if (to_sci_port(port)->chan_tx &&
632 !dma_submit_error(to_sci_port(port)->cookie_tx)) {
633 dmaengine_terminate_async(to_sci_port(port)->chan_tx);
634 to_sci_port(port)->cookie_tx = -EINVAL;
635 }
636#endif
637}
638
639static void sci_start_rx(struct uart_port *port)
640{
641 unsigned short ctrl;
642
643 ctrl = sci_serial_in(port, SCSCR) | port_rx_irq_mask(port);
644
645 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
646 ctrl &= ~SCSCR_RDRQE;
647
648 sci_serial_out(port, SCSCR, ctrl);
649}
650
651static void sci_stop_rx(struct uart_port *port)
652{
653 unsigned short ctrl;
654
655 ctrl = sci_serial_in(port, SCSCR);
656
657 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
658 ctrl &= ~SCSCR_RDRQE;
659
660 ctrl &= ~port_rx_irq_mask(port);
661
662 sci_serial_out(port, SCSCR, ctrl);
663}
664
665static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
666{
667 if (port->type == PORT_SCI) {
668 /* Just store the mask */
669 sci_serial_out(port, SCxSR, mask);
670 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
671 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
672 /* Only clear the status bits we want to clear */
673 sci_serial_out(port, SCxSR, sci_serial_in(port, SCxSR) & mask);
674 } else {
675 /* Store the mask, clear parity/framing errors */
676 sci_serial_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
677 }
678}
679
680#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
681 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
682
683#ifdef CONFIG_CONSOLE_POLL
684static int sci_poll_get_char(struct uart_port *port)
685{
686 unsigned short status;
687 int c;
688
689 do {
690 status = sci_serial_in(port, SCxSR);
691 if (status & SCxSR_ERRORS(port)) {
692 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
693 continue;
694 }
695 break;
696 } while (1);
697
698 if (!(status & SCxSR_RDxF(port)))
699 return NO_POLL_CHAR;
700
701 c = sci_serial_in(port, SCxRDR);
702
703 /* Dummy read */
704 sci_serial_in(port, SCxSR);
705 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
706
707 return c;
708}
709#endif
710
711static void sci_poll_put_char(struct uart_port *port, unsigned char c)
712{
713 unsigned short status;
714
715 do {
716 status = sci_serial_in(port, SCxSR);
717 } while (!(status & SCxSR_TDxE(port)));
718
719 sci_serial_out(port, SCxTDR, c);
720 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
721}
722#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
723 CONFIG_SERIAL_SH_SCI_EARLYCON */
724
725static void sci_init_pins(struct uart_port *port, unsigned int cflag)
726{
727 struct sci_port *s = to_sci_port(port);
728
729 /*
730 * Use port-specific handler if provided.
731 */
732 if (s->cfg->ops && s->cfg->ops->init_pins) {
733 s->cfg->ops->init_pins(port, cflag);
734 return;
735 }
736
737 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
738 u16 data = sci_serial_in(port, SCPDR);
739 u16 ctrl = sci_serial_in(port, SCPCR);
740
741 /* Enable RXD and TXD pin functions */
742 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
743 if (to_sci_port(port)->has_rtscts) {
744 /* RTS# is output, active low, unless autorts */
745 if (!(port->mctrl & TIOCM_RTS)) {
746 ctrl |= SCPCR_RTSC;
747 data |= SCPDR_RTSD;
748 } else if (!s->autorts) {
749 ctrl |= SCPCR_RTSC;
750 data &= ~SCPDR_RTSD;
751 } else {
752 /* Enable RTS# pin function */
753 ctrl &= ~SCPCR_RTSC;
754 }
755 /* Enable CTS# pin function */
756 ctrl &= ~SCPCR_CTSC;
757 }
758 sci_serial_out(port, SCPDR, data);
759 sci_serial_out(port, SCPCR, ctrl);
760 } else if (sci_getreg(port, SCSPTR)->size) {
761 u16 status = sci_serial_in(port, SCSPTR);
762
763 /* RTS# is always output; and active low, unless autorts */
764 status |= SCSPTR_RTSIO;
765 if (!(port->mctrl & TIOCM_RTS))
766 status |= SCSPTR_RTSDT;
767 else if (!s->autorts)
768 status &= ~SCSPTR_RTSDT;
769 /* CTS# and SCK are inputs */
770 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
771 sci_serial_out(port, SCSPTR, status);
772 }
773}
774
775static int sci_txfill(struct uart_port *port)
776{
777 struct sci_port *s = to_sci_port(port);
778 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
779 const struct plat_sci_reg *reg;
780
781 reg = sci_getreg(port, SCTFDR);
782 if (reg->size)
783 return sci_serial_in(port, SCTFDR) & fifo_mask;
784
785 reg = sci_getreg(port, SCFDR);
786 if (reg->size)
787 return sci_serial_in(port, SCFDR) >> 8;
788
789 return !(sci_serial_in(port, SCxSR) & SCI_TDRE);
790}
791
792static int sci_txroom(struct uart_port *port)
793{
794 return port->fifosize - sci_txfill(port);
795}
796
797static int sci_rxfill(struct uart_port *port)
798{
799 struct sci_port *s = to_sci_port(port);
800 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
801 const struct plat_sci_reg *reg;
802
803 reg = sci_getreg(port, SCRFDR);
804 if (reg->size)
805 return sci_serial_in(port, SCRFDR) & fifo_mask;
806
807 reg = sci_getreg(port, SCFDR);
808 if (reg->size)
809 return sci_serial_in(port, SCFDR) & fifo_mask;
810
811 return (sci_serial_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
812}
813
814/* ********************************************************************** *
815 * the interrupt related routines *
816 * ********************************************************************** */
817
818static void sci_transmit_chars(struct uart_port *port)
819{
820 struct circ_buf *xmit = &port->state->xmit;
821 unsigned int stopped = uart_tx_stopped(port);
822 unsigned short status;
823 unsigned short ctrl;
824 int count;
825
826 status = sci_serial_in(port, SCxSR);
827 if (!(status & SCxSR_TDxE(port))) {
828 ctrl = sci_serial_in(port, SCSCR);
829 if (uart_circ_empty(xmit))
830 ctrl &= ~SCSCR_TIE;
831 else
832 ctrl |= SCSCR_TIE;
833 sci_serial_out(port, SCSCR, ctrl);
834 return;
835 }
836
837 count = sci_txroom(port);
838
839 do {
840 unsigned char c;
841
842 if (port->x_char) {
843 c = port->x_char;
844 port->x_char = 0;
845 } else if (!uart_circ_empty(xmit) && !stopped) {
846 c = xmit->buf[xmit->tail];
847 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
848 } else if (port->type == PORT_SCI && uart_circ_empty(xmit)) {
849 ctrl = sci_serial_in(port, SCSCR);
850 ctrl &= ~SCSCR_TE;
851 sci_serial_out(port, SCSCR, ctrl);
852 return;
853 } else {
854 break;
855 }
856
857 sci_serial_out(port, SCxTDR, c);
858
859 port->icount.tx++;
860 } while (--count > 0);
861
862 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
863
864 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
865 uart_write_wakeup(port);
866 if (uart_circ_empty(xmit)) {
867 if (port->type == PORT_SCI) {
868 ctrl = sci_serial_in(port, SCSCR);
869 ctrl &= ~SCSCR_TIE;
870 ctrl |= SCSCR_TEIE;
871 sci_serial_out(port, SCSCR, ctrl);
872 }
873
874 sci_stop_tx(port);
875 }
876}
877
878static void sci_receive_chars(struct uart_port *port)
879{
880 struct tty_port *tport = &port->state->port;
881 int i, count, copied = 0;
882 unsigned short status;
883 unsigned char flag;
884
885 status = sci_serial_in(port, SCxSR);
886 if (!(status & SCxSR_RDxF(port)))
887 return;
888
889 while (1) {
890 /* Don't copy more bytes than there is room for in the buffer */
891 count = tty_buffer_request_room(tport, sci_rxfill(port));
892
893 /* If for any reason we can't copy more data, we're done! */
894 if (count == 0)
895 break;
896
897 if (port->type == PORT_SCI) {
898 char c = sci_serial_in(port, SCxRDR);
899 if (uart_handle_sysrq_char(port, c))
900 count = 0;
901 else
902 tty_insert_flip_char(tport, c, TTY_NORMAL);
903 } else {
904 for (i = 0; i < count; i++) {
905 char c;
906
907 if (port->type == PORT_SCIF ||
908 port->type == PORT_HSCIF) {
909 status = sci_serial_in(port, SCxSR);
910 c = sci_serial_in(port, SCxRDR);
911 } else {
912 c = sci_serial_in(port, SCxRDR);
913 status = sci_serial_in(port, SCxSR);
914 }
915 if (uart_handle_sysrq_char(port, c)) {
916 count--; i--;
917 continue;
918 }
919
920 /* Store data and status */
921 if (status & SCxSR_FER(port)) {
922 flag = TTY_FRAME;
923 port->icount.frame++;
924 } else if (status & SCxSR_PER(port)) {
925 flag = TTY_PARITY;
926 port->icount.parity++;
927 } else
928 flag = TTY_NORMAL;
929
930 tty_insert_flip_char(tport, c, flag);
931 }
932 }
933
934 sci_serial_in(port, SCxSR); /* dummy read */
935 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
936
937 copied += count;
938 port->icount.rx += count;
939 }
940
941 if (copied) {
942 /* Tell the rest of the system the news. New characters! */
943 tty_flip_buffer_push(tport);
944 } else {
945 /* TTY buffers full; read from RX reg to prevent lockup */
946 sci_serial_in(port, SCxRDR);
947 sci_serial_in(port, SCxSR); /* dummy read */
948 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
949 }
950}
951
952static int sci_handle_errors(struct uart_port *port)
953{
954 int copied = 0;
955 unsigned short status = sci_serial_in(port, SCxSR);
956 struct tty_port *tport = &port->state->port;
957 struct sci_port *s = to_sci_port(port);
958
959 /* Handle overruns */
960 if (status & s->params->overrun_mask) {
961 port->icount.overrun++;
962
963 /* overrun error */
964 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
965 copied++;
966 }
967
968 if (status & SCxSR_FER(port)) {
969 /* frame error */
970 port->icount.frame++;
971
972 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
973 copied++;
974 }
975
976 if (status & SCxSR_PER(port)) {
977 /* parity error */
978 port->icount.parity++;
979
980 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
981 copied++;
982 }
983
984 if (copied)
985 tty_flip_buffer_push(tport);
986
987 return copied;
988}
989
990static int sci_handle_fifo_overrun(struct uart_port *port)
991{
992 struct tty_port *tport = &port->state->port;
993 struct sci_port *s = to_sci_port(port);
994 const struct plat_sci_reg *reg;
995 int copied = 0;
996 u16 status;
997
998 reg = sci_getreg(port, s->params->overrun_reg);
999 if (!reg->size)
1000 return 0;
1001
1002 status = sci_serial_in(port, s->params->overrun_reg);
1003 if (status & s->params->overrun_mask) {
1004 status &= ~s->params->overrun_mask;
1005 sci_serial_out(port, s->params->overrun_reg, status);
1006
1007 port->icount.overrun++;
1008
1009 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1010 tty_flip_buffer_push(tport);
1011 copied++;
1012 }
1013
1014 return copied;
1015}
1016
1017static int sci_handle_breaks(struct uart_port *port)
1018{
1019 int copied = 0;
1020 unsigned short status = sci_serial_in(port, SCxSR);
1021 struct tty_port *tport = &port->state->port;
1022
1023 if (uart_handle_break(port))
1024 return 0;
1025
1026 if (status & SCxSR_BRK(port)) {
1027 port->icount.brk++;
1028
1029 /* Notify of BREAK */
1030 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1031 copied++;
1032 }
1033
1034 if (copied)
1035 tty_flip_buffer_push(tport);
1036
1037 copied += sci_handle_fifo_overrun(port);
1038
1039 return copied;
1040}
1041
1042static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1043{
1044 unsigned int bits;
1045
1046 if (rx_trig >= port->fifosize)
1047 rx_trig = port->fifosize - 1;
1048 if (rx_trig < 1)
1049 rx_trig = 1;
1050
1051 /* HSCIF can be set to an arbitrary level. */
1052 if (sci_getreg(port, HSRTRGR)->size) {
1053 sci_serial_out(port, HSRTRGR, rx_trig);
1054 return rx_trig;
1055 }
1056
1057 switch (port->type) {
1058 case PORT_SCIF:
1059 if (rx_trig < 4) {
1060 bits = 0;
1061 rx_trig = 1;
1062 } else if (rx_trig < 8) {
1063 bits = SCFCR_RTRG0;
1064 rx_trig = 4;
1065 } else if (rx_trig < 14) {
1066 bits = SCFCR_RTRG1;
1067 rx_trig = 8;
1068 } else {
1069 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1070 rx_trig = 14;
1071 }
1072 break;
1073 case PORT_SCIFA:
1074 case PORT_SCIFB:
1075 if (rx_trig < 16) {
1076 bits = 0;
1077 rx_trig = 1;
1078 } else if (rx_trig < 32) {
1079 bits = SCFCR_RTRG0;
1080 rx_trig = 16;
1081 } else if (rx_trig < 48) {
1082 bits = SCFCR_RTRG1;
1083 rx_trig = 32;
1084 } else {
1085 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1086 rx_trig = 48;
1087 }
1088 break;
1089 default:
1090 WARN(1, "unknown FIFO configuration");
1091 return 1;
1092 }
1093
1094 sci_serial_out(port, SCFCR,
1095 (sci_serial_in(port, SCFCR) &
1096 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1097
1098 return rx_trig;
1099}
1100
1101static int scif_rtrg_enabled(struct uart_port *port)
1102{
1103 if (sci_getreg(port, HSRTRGR)->size)
1104 return sci_serial_in(port, HSRTRGR) != 0;
1105 else
1106 return (sci_serial_in(port, SCFCR) &
1107 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1108}
1109
1110static void rx_fifo_timer_fn(struct timer_list *t)
1111{
1112 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1113 struct uart_port *port = &s->port;
1114
1115 dev_dbg(port->dev, "Rx timed out\n");
1116 scif_set_rtrg(port, 1);
1117}
1118
1119static ssize_t rx_fifo_trigger_show(struct device *dev,
1120 struct device_attribute *attr, char *buf)
1121{
1122 struct uart_port *port = dev_get_drvdata(dev);
1123 struct sci_port *sci = to_sci_port(port);
1124
1125 return sprintf(buf, "%d\n", sci->rx_trigger);
1126}
1127
1128static ssize_t rx_fifo_trigger_store(struct device *dev,
1129 struct device_attribute *attr,
1130 const char *buf, size_t count)
1131{
1132 struct uart_port *port = dev_get_drvdata(dev);
1133 struct sci_port *sci = to_sci_port(port);
1134 int ret;
1135 long r;
1136
1137 ret = kstrtol(buf, 0, &r);
1138 if (ret)
1139 return ret;
1140
1141 sci->rx_trigger = scif_set_rtrg(port, r);
1142 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1143 scif_set_rtrg(port, 1);
1144
1145 return count;
1146}
1147
1148static DEVICE_ATTR_RW(rx_fifo_trigger);
1149
1150static ssize_t rx_fifo_timeout_show(struct device *dev,
1151 struct device_attribute *attr,
1152 char *buf)
1153{
1154 struct uart_port *port = dev_get_drvdata(dev);
1155 struct sci_port *sci = to_sci_port(port);
1156 int v;
1157
1158 if (port->type == PORT_HSCIF)
1159 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1160 else
1161 v = sci->rx_fifo_timeout;
1162
1163 return sprintf(buf, "%d\n", v);
1164}
1165
1166static ssize_t rx_fifo_timeout_store(struct device *dev,
1167 struct device_attribute *attr,
1168 const char *buf,
1169 size_t count)
1170{
1171 struct uart_port *port = dev_get_drvdata(dev);
1172 struct sci_port *sci = to_sci_port(port);
1173 int ret;
1174 long r;
1175
1176 ret = kstrtol(buf, 0, &r);
1177 if (ret)
1178 return ret;
1179
1180 if (port->type == PORT_HSCIF) {
1181 if (r < 0 || r > 3)
1182 return -EINVAL;
1183 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1184 } else {
1185 sci->rx_fifo_timeout = r;
1186 scif_set_rtrg(port, 1);
1187 if (r > 0)
1188 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1189 }
1190
1191 return count;
1192}
1193
1194static DEVICE_ATTR_RW(rx_fifo_timeout);
1195
1196
1197#ifdef CONFIG_SERIAL_SH_SCI_DMA
1198static void sci_dma_tx_complete(void *arg)
1199{
1200 struct sci_port *s = arg;
1201 struct uart_port *port = &s->port;
1202 struct circ_buf *xmit = &port->state->xmit;
1203 unsigned long flags;
1204
1205 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1206
1207 uart_port_lock_irqsave(port, &flags);
1208
1209 uart_xmit_advance(port, s->tx_dma_len);
1210
1211 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1212 uart_write_wakeup(port);
1213
1214 if (!uart_circ_empty(xmit)) {
1215 s->cookie_tx = 0;
1216 schedule_work(&s->work_tx);
1217 } else {
1218 s->cookie_tx = -EINVAL;
1219 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1220 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1221 u16 ctrl = sci_serial_in(port, SCSCR);
1222 sci_serial_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1223 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1224 /* Switch irq from DMA to SCIF */
1225 dmaengine_pause(s->chan_tx_saved);
1226 enable_irq(s->irqs[SCIx_TXI_IRQ]);
1227 }
1228 }
1229 }
1230
1231 uart_port_unlock_irqrestore(port, flags);
1232}
1233
1234/* Locking: called with port lock held */
1235static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1236{
1237 struct uart_port *port = &s->port;
1238 struct tty_port *tport = &port->state->port;
1239 int copied;
1240
1241 copied = tty_insert_flip_string(tport, buf, count);
1242 if (copied < count)
1243 port->icount.buf_overrun++;
1244
1245 port->icount.rx += copied;
1246
1247 return copied;
1248}
1249
1250static int sci_dma_rx_find_active(struct sci_port *s)
1251{
1252 unsigned int i;
1253
1254 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1255 if (s->active_rx == s->cookie_rx[i])
1256 return i;
1257
1258 return -1;
1259}
1260
1261static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1262{
1263 unsigned int i;
1264
1265 s->chan_rx = NULL;
1266 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1267 s->cookie_rx[i] = -EINVAL;
1268 s->active_rx = 0;
1269}
1270
1271static void sci_dma_rx_release(struct sci_port *s)
1272{
1273 struct dma_chan *chan = s->chan_rx_saved;
1274 struct uart_port *port = &s->port;
1275 unsigned long flags;
1276
1277 uart_port_lock_irqsave(port, &flags);
1278 s->chan_rx_saved = NULL;
1279 sci_dma_rx_chan_invalidate(s);
1280 uart_port_unlock_irqrestore(port, flags);
1281
1282 dmaengine_terminate_sync(chan);
1283 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1284 sg_dma_address(&s->sg_rx[0]));
1285 dma_release_channel(chan);
1286}
1287
1288static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1289{
1290 long sec = usec / 1000000;
1291 long nsec = (usec % 1000000) * 1000;
1292 ktime_t t = ktime_set(sec, nsec);
1293
1294 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1295}
1296
1297static void sci_dma_rx_reenable_irq(struct sci_port *s)
1298{
1299 struct uart_port *port = &s->port;
1300 u16 scr;
1301
1302 /* Direct new serial port interrupts back to CPU */
1303 scr = sci_serial_in(port, SCSCR);
1304 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1305 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1306 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1307 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1308 scif_set_rtrg(port, s->rx_trigger);
1309 else
1310 scr &= ~SCSCR_RDRQE;
1311 }
1312 sci_serial_out(port, SCSCR, scr | SCSCR_RIE);
1313}
1314
1315static void sci_dma_rx_complete(void *arg)
1316{
1317 struct sci_port *s = arg;
1318 struct dma_chan *chan = s->chan_rx;
1319 struct uart_port *port = &s->port;
1320 struct dma_async_tx_descriptor *desc;
1321 unsigned long flags;
1322 int active, count = 0;
1323
1324 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1325 s->active_rx);
1326
1327 uart_port_lock_irqsave(port, &flags);
1328
1329 active = sci_dma_rx_find_active(s);
1330 if (active >= 0)
1331 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1332
1333 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1334
1335 if (count)
1336 tty_flip_buffer_push(&port->state->port);
1337
1338 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1339 DMA_DEV_TO_MEM,
1340 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1341 if (!desc)
1342 goto fail;
1343
1344 desc->callback = sci_dma_rx_complete;
1345 desc->callback_param = s;
1346 s->cookie_rx[active] = dmaengine_submit(desc);
1347 if (dma_submit_error(s->cookie_rx[active]))
1348 goto fail;
1349
1350 s->active_rx = s->cookie_rx[!active];
1351
1352 dma_async_issue_pending(chan);
1353
1354 uart_port_unlock_irqrestore(port, flags);
1355 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1356 __func__, s->cookie_rx[active], active, s->active_rx);
1357 return;
1358
1359fail:
1360 uart_port_unlock_irqrestore(port, flags);
1361 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1362 /* Switch to PIO */
1363 uart_port_lock_irqsave(port, &flags);
1364 dmaengine_terminate_async(chan);
1365 sci_dma_rx_chan_invalidate(s);
1366 sci_dma_rx_reenable_irq(s);
1367 uart_port_unlock_irqrestore(port, flags);
1368}
1369
1370static void sci_dma_tx_release(struct sci_port *s)
1371{
1372 struct dma_chan *chan = s->chan_tx_saved;
1373
1374 cancel_work_sync(&s->work_tx);
1375 s->chan_tx_saved = s->chan_tx = NULL;
1376 s->cookie_tx = -EINVAL;
1377 dmaengine_terminate_sync(chan);
1378 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1379 DMA_TO_DEVICE);
1380 dma_release_channel(chan);
1381}
1382
1383static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1384{
1385 struct dma_chan *chan = s->chan_rx;
1386 struct uart_port *port = &s->port;
1387 unsigned long flags;
1388 int i;
1389
1390 for (i = 0; i < 2; i++) {
1391 struct scatterlist *sg = &s->sg_rx[i];
1392 struct dma_async_tx_descriptor *desc;
1393
1394 desc = dmaengine_prep_slave_sg(chan,
1395 sg, 1, DMA_DEV_TO_MEM,
1396 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1397 if (!desc)
1398 goto fail;
1399
1400 desc->callback = sci_dma_rx_complete;
1401 desc->callback_param = s;
1402 s->cookie_rx[i] = dmaengine_submit(desc);
1403 if (dma_submit_error(s->cookie_rx[i]))
1404 goto fail;
1405
1406 }
1407
1408 s->active_rx = s->cookie_rx[0];
1409
1410 dma_async_issue_pending(chan);
1411 return 0;
1412
1413fail:
1414 /* Switch to PIO */
1415 if (!port_lock_held)
1416 uart_port_lock_irqsave(port, &flags);
1417 if (i)
1418 dmaengine_terminate_async(chan);
1419 sci_dma_rx_chan_invalidate(s);
1420 sci_start_rx(port);
1421 if (!port_lock_held)
1422 uart_port_unlock_irqrestore(port, flags);
1423 return -EAGAIN;
1424}
1425
1426static void sci_dma_tx_work_fn(struct work_struct *work)
1427{
1428 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1429 struct dma_async_tx_descriptor *desc;
1430 struct dma_chan *chan = s->chan_tx;
1431 struct uart_port *port = &s->port;
1432 struct circ_buf *xmit = &port->state->xmit;
1433 unsigned long flags;
1434 dma_addr_t buf;
1435 int head, tail;
1436
1437 /*
1438 * DMA is idle now.
1439 * Port xmit buffer is already mapped, and it is one page... Just adjust
1440 * offsets and lengths. Since it is a circular buffer, we have to
1441 * transmit till the end, and then the rest. Take the port lock to get a
1442 * consistent xmit buffer state.
1443 */
1444 uart_port_lock_irq(port);
1445 head = xmit->head;
1446 tail = xmit->tail;
1447 buf = s->tx_dma_addr + tail;
1448 s->tx_dma_len = CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE);
1449 if (!s->tx_dma_len) {
1450 /* Transmit buffer has been flushed */
1451 uart_port_unlock_irq(port);
1452 return;
1453 }
1454
1455 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1456 DMA_MEM_TO_DEV,
1457 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1458 if (!desc) {
1459 uart_port_unlock_irq(port);
1460 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1461 goto switch_to_pio;
1462 }
1463
1464 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1465 DMA_TO_DEVICE);
1466
1467 desc->callback = sci_dma_tx_complete;
1468 desc->callback_param = s;
1469 s->cookie_tx = dmaengine_submit(desc);
1470 if (dma_submit_error(s->cookie_tx)) {
1471 uart_port_unlock_irq(port);
1472 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1473 goto switch_to_pio;
1474 }
1475
1476 uart_port_unlock_irq(port);
1477 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1478 __func__, xmit->buf, tail, head, s->cookie_tx);
1479
1480 dma_async_issue_pending(chan);
1481 return;
1482
1483switch_to_pio:
1484 uart_port_lock_irqsave(port, &flags);
1485 s->chan_tx = NULL;
1486 sci_start_tx(port);
1487 uart_port_unlock_irqrestore(port, flags);
1488 return;
1489}
1490
1491static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1492{
1493 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1494 struct dma_chan *chan = s->chan_rx;
1495 struct uart_port *port = &s->port;
1496 struct dma_tx_state state;
1497 enum dma_status status;
1498 unsigned long flags;
1499 unsigned int read;
1500 int active, count;
1501
1502 dev_dbg(port->dev, "DMA Rx timed out\n");
1503
1504 uart_port_lock_irqsave(port, &flags);
1505
1506 active = sci_dma_rx_find_active(s);
1507 if (active < 0) {
1508 uart_port_unlock_irqrestore(port, flags);
1509 return HRTIMER_NORESTART;
1510 }
1511
1512 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1513 if (status == DMA_COMPLETE) {
1514 uart_port_unlock_irqrestore(port, flags);
1515 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1516 s->active_rx, active);
1517
1518 /* Let packet complete handler take care of the packet */
1519 return HRTIMER_NORESTART;
1520 }
1521
1522 dmaengine_pause(chan);
1523
1524 /*
1525 * sometimes DMA transfer doesn't stop even if it is stopped and
1526 * data keeps on coming until transaction is complete so check
1527 * for DMA_COMPLETE again
1528 * Let packet complete handler take care of the packet
1529 */
1530 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1531 if (status == DMA_COMPLETE) {
1532 uart_port_unlock_irqrestore(port, flags);
1533 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1534 return HRTIMER_NORESTART;
1535 }
1536
1537 /* Handle incomplete DMA receive */
1538 dmaengine_terminate_async(s->chan_rx);
1539 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1540
1541 if (read) {
1542 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1543 if (count)
1544 tty_flip_buffer_push(&port->state->port);
1545 }
1546
1547 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1548 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1549 sci_dma_rx_submit(s, true);
1550
1551 sci_dma_rx_reenable_irq(s);
1552
1553 uart_port_unlock_irqrestore(port, flags);
1554
1555 return HRTIMER_NORESTART;
1556}
1557
1558static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1559 enum dma_transfer_direction dir)
1560{
1561 struct dma_chan *chan;
1562 struct dma_slave_config cfg;
1563 int ret;
1564
1565 chan = dma_request_chan(port->dev, dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1566 if (IS_ERR(chan)) {
1567 dev_dbg(port->dev, "dma_request_chan failed\n");
1568 return NULL;
1569 }
1570
1571 memset(&cfg, 0, sizeof(cfg));
1572 cfg.direction = dir;
1573 cfg.dst_addr = port->mapbase +
1574 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1575 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1576 cfg.src_addr = port->mapbase +
1577 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1578 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1579
1580 ret = dmaengine_slave_config(chan, &cfg);
1581 if (ret) {
1582 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1583 dma_release_channel(chan);
1584 return NULL;
1585 }
1586
1587 return chan;
1588}
1589
1590static void sci_request_dma(struct uart_port *port)
1591{
1592 struct sci_port *s = to_sci_port(port);
1593 struct dma_chan *chan;
1594
1595 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1596
1597 /*
1598 * DMA on console may interfere with Kernel log messages which use
1599 * plain putchar(). So, simply don't use it with a console.
1600 */
1601 if (uart_console(port))
1602 return;
1603
1604 if (!port->dev->of_node)
1605 return;
1606
1607 s->cookie_tx = -EINVAL;
1608
1609 /*
1610 * Don't request a dma channel if no channel was specified
1611 * in the device tree.
1612 */
1613 if (!of_property_present(port->dev->of_node, "dmas"))
1614 return;
1615
1616 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1617 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1618 if (chan) {
1619 /* UART circular tx buffer is an aligned page. */
1620 s->tx_dma_addr = dma_map_single(chan->device->dev,
1621 port->state->xmit.buf,
1622 UART_XMIT_SIZE,
1623 DMA_TO_DEVICE);
1624 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1625 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1626 dma_release_channel(chan);
1627 } else {
1628 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1629 __func__, UART_XMIT_SIZE,
1630 port->state->xmit.buf, &s->tx_dma_addr);
1631
1632 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1633 s->chan_tx_saved = s->chan_tx = chan;
1634 }
1635 }
1636
1637 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1638 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1639 if (chan) {
1640 unsigned int i;
1641 dma_addr_t dma;
1642 void *buf;
1643
1644 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1645 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1646 &dma, GFP_KERNEL);
1647 if (!buf) {
1648 dev_warn(port->dev,
1649 "Failed to allocate Rx dma buffer, using PIO\n");
1650 dma_release_channel(chan);
1651 return;
1652 }
1653
1654 for (i = 0; i < 2; i++) {
1655 struct scatterlist *sg = &s->sg_rx[i];
1656
1657 sg_init_table(sg, 1);
1658 s->rx_buf[i] = buf;
1659 sg_dma_address(sg) = dma;
1660 sg_dma_len(sg) = s->buf_len_rx;
1661
1662 buf += s->buf_len_rx;
1663 dma += s->buf_len_rx;
1664 }
1665
1666 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1667 s->rx_timer.function = sci_dma_rx_timer_fn;
1668
1669 s->chan_rx_saved = s->chan_rx = chan;
1670
1671 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1672 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1673 sci_dma_rx_submit(s, false);
1674 }
1675}
1676
1677static void sci_free_dma(struct uart_port *port)
1678{
1679 struct sci_port *s = to_sci_port(port);
1680
1681 if (s->chan_tx_saved)
1682 sci_dma_tx_release(s);
1683 if (s->chan_rx_saved)
1684 sci_dma_rx_release(s);
1685}
1686
1687static void sci_flush_buffer(struct uart_port *port)
1688{
1689 struct sci_port *s = to_sci_port(port);
1690
1691 /*
1692 * In uart_flush_buffer(), the xmit circular buffer has just been
1693 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1694 * pending transfers
1695 */
1696 s->tx_dma_len = 0;
1697 if (s->chan_tx) {
1698 dmaengine_terminate_async(s->chan_tx);
1699 s->cookie_tx = -EINVAL;
1700 }
1701}
1702#else /* !CONFIG_SERIAL_SH_SCI_DMA */
1703static inline void sci_request_dma(struct uart_port *port)
1704{
1705}
1706
1707static inline void sci_free_dma(struct uart_port *port)
1708{
1709}
1710
1711#define sci_flush_buffer NULL
1712#endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1713
1714static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1715{
1716 struct uart_port *port = ptr;
1717 struct sci_port *s = to_sci_port(port);
1718
1719#ifdef CONFIG_SERIAL_SH_SCI_DMA
1720 if (s->chan_rx) {
1721 u16 scr = sci_serial_in(port, SCSCR);
1722 u16 ssr = sci_serial_in(port, SCxSR);
1723
1724 /* Disable future Rx interrupts */
1725 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1726 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1727 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]);
1728 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1729 scif_set_rtrg(port, 1);
1730 scr |= SCSCR_RIE;
1731 } else {
1732 scr |= SCSCR_RDRQE;
1733 }
1734 } else {
1735 if (sci_dma_rx_submit(s, false) < 0)
1736 goto handle_pio;
1737
1738 scr &= ~SCSCR_RIE;
1739 }
1740 sci_serial_out(port, SCSCR, scr);
1741 /* Clear current interrupt */
1742 sci_serial_out(port, SCxSR,
1743 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1744 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1745 jiffies, s->rx_timeout);
1746 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1747
1748 return IRQ_HANDLED;
1749 }
1750
1751handle_pio:
1752#endif
1753
1754 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1755 if (!scif_rtrg_enabled(port))
1756 scif_set_rtrg(port, s->rx_trigger);
1757
1758 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1759 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1760 }
1761
1762 /* I think sci_receive_chars has to be called irrespective
1763 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1764 * to be disabled?
1765 */
1766 sci_receive_chars(port);
1767
1768 return IRQ_HANDLED;
1769}
1770
1771static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1772{
1773 struct uart_port *port = ptr;
1774 unsigned long flags;
1775
1776 uart_port_lock_irqsave(port, &flags);
1777 sci_transmit_chars(port);
1778 uart_port_unlock_irqrestore(port, flags);
1779
1780 return IRQ_HANDLED;
1781}
1782
1783static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
1784{
1785 struct uart_port *port = ptr;
1786 unsigned long flags;
1787 unsigned short ctrl;
1788
1789 if (port->type != PORT_SCI)
1790 return sci_tx_interrupt(irq, ptr);
1791
1792 uart_port_lock_irqsave(port, &flags);
1793 ctrl = sci_serial_in(port, SCSCR);
1794 ctrl &= ~(SCSCR_TE | SCSCR_TEIE);
1795 sci_serial_out(port, SCSCR, ctrl);
1796 uart_port_unlock_irqrestore(port, flags);
1797
1798 return IRQ_HANDLED;
1799}
1800
1801static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1802{
1803 struct uart_port *port = ptr;
1804
1805 /* Handle BREAKs */
1806 sci_handle_breaks(port);
1807
1808 /* drop invalid character received before break was detected */
1809 sci_serial_in(port, SCxRDR);
1810
1811 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1812
1813 return IRQ_HANDLED;
1814}
1815
1816static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1817{
1818 struct uart_port *port = ptr;
1819 struct sci_port *s = to_sci_port(port);
1820
1821 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1822 /* Break and Error interrupts are muxed */
1823 unsigned short ssr_status = sci_serial_in(port, SCxSR);
1824
1825 /* Break Interrupt */
1826 if (ssr_status & SCxSR_BRK(port))
1827 sci_br_interrupt(irq, ptr);
1828
1829 /* Break only? */
1830 if (!(ssr_status & SCxSR_ERRORS(port)))
1831 return IRQ_HANDLED;
1832 }
1833
1834 /* Handle errors */
1835 if (port->type == PORT_SCI) {
1836 if (sci_handle_errors(port)) {
1837 /* discard character in rx buffer */
1838 sci_serial_in(port, SCxSR);
1839 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1840 }
1841 } else {
1842 sci_handle_fifo_overrun(port);
1843 if (!s->chan_rx)
1844 sci_receive_chars(port);
1845 }
1846
1847 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1848
1849 /* Kick the transmission */
1850 if (!s->chan_tx)
1851 sci_tx_interrupt(irq, ptr);
1852
1853 return IRQ_HANDLED;
1854}
1855
1856static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1857{
1858 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1859 struct uart_port *port = ptr;
1860 struct sci_port *s = to_sci_port(port);
1861 irqreturn_t ret = IRQ_NONE;
1862
1863 ssr_status = sci_serial_in(port, SCxSR);
1864 scr_status = sci_serial_in(port, SCSCR);
1865 if (s->params->overrun_reg == SCxSR)
1866 orer_status = ssr_status;
1867 else if (sci_getreg(port, s->params->overrun_reg)->size)
1868 orer_status = sci_serial_in(port, s->params->overrun_reg);
1869
1870 err_enabled = scr_status & port_rx_irq_mask(port);
1871
1872 /* Tx Interrupt */
1873 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1874 !s->chan_tx)
1875 ret = sci_tx_interrupt(irq, ptr);
1876
1877 /*
1878 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1879 * DR flags
1880 */
1881 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1882 (scr_status & SCSCR_RIE))
1883 ret = sci_rx_interrupt(irq, ptr);
1884
1885 /* Error Interrupt */
1886 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1887 ret = sci_er_interrupt(irq, ptr);
1888
1889 /* Break Interrupt */
1890 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] &&
1891 (ssr_status & SCxSR_BRK(port)) && err_enabled)
1892 ret = sci_br_interrupt(irq, ptr);
1893
1894 /* Overrun Interrupt */
1895 if (orer_status & s->params->overrun_mask) {
1896 sci_handle_fifo_overrun(port);
1897 ret = IRQ_HANDLED;
1898 }
1899
1900 return ret;
1901}
1902
1903static const struct sci_irq_desc {
1904 const char *desc;
1905 irq_handler_t handler;
1906} sci_irq_desc[] = {
1907 /*
1908 * Split out handlers, the default case.
1909 */
1910 [SCIx_ERI_IRQ] = {
1911 .desc = "rx err",
1912 .handler = sci_er_interrupt,
1913 },
1914
1915 [SCIx_RXI_IRQ] = {
1916 .desc = "rx full",
1917 .handler = sci_rx_interrupt,
1918 },
1919
1920 [SCIx_TXI_IRQ] = {
1921 .desc = "tx empty",
1922 .handler = sci_tx_interrupt,
1923 },
1924
1925 [SCIx_BRI_IRQ] = {
1926 .desc = "break",
1927 .handler = sci_br_interrupt,
1928 },
1929
1930 [SCIx_DRI_IRQ] = {
1931 .desc = "rx ready",
1932 .handler = sci_rx_interrupt,
1933 },
1934
1935 [SCIx_TEI_IRQ] = {
1936 .desc = "tx end",
1937 .handler = sci_tx_end_interrupt,
1938 },
1939
1940 /*
1941 * Special muxed handler.
1942 */
1943 [SCIx_MUX_IRQ] = {
1944 .desc = "mux",
1945 .handler = sci_mpxed_interrupt,
1946 },
1947};
1948
1949static int sci_request_irq(struct sci_port *port)
1950{
1951 struct uart_port *up = &port->port;
1952 int i, j, w, ret = 0;
1953
1954 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1955 const struct sci_irq_desc *desc;
1956 int irq;
1957
1958 /* Check if already registered (muxed) */
1959 for (w = 0; w < i; w++)
1960 if (port->irqs[w] == port->irqs[i])
1961 w = i + 1;
1962 if (w > i)
1963 continue;
1964
1965 if (SCIx_IRQ_IS_MUXED(port)) {
1966 i = SCIx_MUX_IRQ;
1967 irq = up->irq;
1968 } else {
1969 irq = port->irqs[i];
1970
1971 /*
1972 * Certain port types won't support all of the
1973 * available interrupt sources.
1974 */
1975 if (unlikely(irq < 0))
1976 continue;
1977 }
1978
1979 desc = sci_irq_desc + i;
1980 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1981 dev_name(up->dev), desc->desc);
1982 if (!port->irqstr[j]) {
1983 ret = -ENOMEM;
1984 goto out_nomem;
1985 }
1986
1987 ret = request_irq(irq, desc->handler, up->irqflags,
1988 port->irqstr[j], port);
1989 if (unlikely(ret)) {
1990 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1991 goto out_noirq;
1992 }
1993 }
1994
1995 return 0;
1996
1997out_noirq:
1998 while (--i >= 0)
1999 free_irq(port->irqs[i], port);
2000
2001out_nomem:
2002 while (--j >= 0)
2003 kfree(port->irqstr[j]);
2004
2005 return ret;
2006}
2007
2008static void sci_free_irq(struct sci_port *port)
2009{
2010 int i, j;
2011
2012 /*
2013 * Intentionally in reverse order so we iterate over the muxed
2014 * IRQ first.
2015 */
2016 for (i = 0; i < SCIx_NR_IRQS; i++) {
2017 int irq = port->irqs[i];
2018
2019 /*
2020 * Certain port types won't support all of the available
2021 * interrupt sources.
2022 */
2023 if (unlikely(irq < 0))
2024 continue;
2025
2026 /* Check if already freed (irq was muxed) */
2027 for (j = 0; j < i; j++)
2028 if (port->irqs[j] == irq)
2029 j = i + 1;
2030 if (j > i)
2031 continue;
2032
2033 free_irq(port->irqs[i], port);
2034 kfree(port->irqstr[i]);
2035
2036 if (SCIx_IRQ_IS_MUXED(port)) {
2037 /* If there's only one IRQ, we're done. */
2038 return;
2039 }
2040 }
2041}
2042
2043static unsigned int sci_tx_empty(struct uart_port *port)
2044{
2045 unsigned short status = sci_serial_in(port, SCxSR);
2046 unsigned short in_tx_fifo = sci_txfill(port);
2047
2048 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
2049}
2050
2051static void sci_set_rts(struct uart_port *port, bool state)
2052{
2053 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2054 u16 data = sci_serial_in(port, SCPDR);
2055
2056 /* Active low */
2057 if (state)
2058 data &= ~SCPDR_RTSD;
2059 else
2060 data |= SCPDR_RTSD;
2061 sci_serial_out(port, SCPDR, data);
2062
2063 /* RTS# is output */
2064 sci_serial_out(port, SCPCR,
2065 sci_serial_in(port, SCPCR) | SCPCR_RTSC);
2066 } else if (sci_getreg(port, SCSPTR)->size) {
2067 u16 ctrl = sci_serial_in(port, SCSPTR);
2068
2069 /* Active low */
2070 if (state)
2071 ctrl &= ~SCSPTR_RTSDT;
2072 else
2073 ctrl |= SCSPTR_RTSDT;
2074 sci_serial_out(port, SCSPTR, ctrl);
2075 }
2076}
2077
2078static bool sci_get_cts(struct uart_port *port)
2079{
2080 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2081 /* Active low */
2082 return !(sci_serial_in(port, SCPDR) & SCPDR_CTSD);
2083 } else if (sci_getreg(port, SCSPTR)->size) {
2084 /* Active low */
2085 return !(sci_serial_in(port, SCSPTR) & SCSPTR_CTSDT);
2086 }
2087
2088 return true;
2089}
2090
2091/*
2092 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2093 * CTS/RTS is supported in hardware by at least one port and controlled
2094 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2095 * handled via the ->init_pins() op, which is a bit of a one-way street,
2096 * lacking any ability to defer pin control -- this will later be
2097 * converted over to the GPIO framework).
2098 *
2099 * Other modes (such as loopback) are supported generically on certain
2100 * port types, but not others. For these it's sufficient to test for the
2101 * existence of the support register and simply ignore the port type.
2102 */
2103static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2104{
2105 struct sci_port *s = to_sci_port(port);
2106
2107 if (mctrl & TIOCM_LOOP) {
2108 const struct plat_sci_reg *reg;
2109
2110 /*
2111 * Standard loopback mode for SCFCR ports.
2112 */
2113 reg = sci_getreg(port, SCFCR);
2114 if (reg->size)
2115 sci_serial_out(port, SCFCR,
2116 sci_serial_in(port, SCFCR) | SCFCR_LOOP);
2117 }
2118
2119 mctrl_gpio_set(s->gpios, mctrl);
2120
2121 if (!s->has_rtscts)
2122 return;
2123
2124 if (!(mctrl & TIOCM_RTS)) {
2125 /* Disable Auto RTS */
2126 sci_serial_out(port, SCFCR,
2127 sci_serial_in(port, SCFCR) & ~SCFCR_MCE);
2128
2129 /* Clear RTS */
2130 sci_set_rts(port, 0);
2131 } else if (s->autorts) {
2132 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2133 /* Enable RTS# pin function */
2134 sci_serial_out(port, SCPCR,
2135 sci_serial_in(port, SCPCR) & ~SCPCR_RTSC);
2136 }
2137
2138 /* Enable Auto RTS */
2139 sci_serial_out(port, SCFCR,
2140 sci_serial_in(port, SCFCR) | SCFCR_MCE);
2141 } else {
2142 /* Set RTS */
2143 sci_set_rts(port, 1);
2144 }
2145}
2146
2147static unsigned int sci_get_mctrl(struct uart_port *port)
2148{
2149 struct sci_port *s = to_sci_port(port);
2150 struct mctrl_gpios *gpios = s->gpios;
2151 unsigned int mctrl = 0;
2152
2153 mctrl_gpio_get(gpios, &mctrl);
2154
2155 /*
2156 * CTS/RTS is handled in hardware when supported, while nothing
2157 * else is wired up.
2158 */
2159 if (s->autorts) {
2160 if (sci_get_cts(port))
2161 mctrl |= TIOCM_CTS;
2162 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
2163 mctrl |= TIOCM_CTS;
2164 }
2165 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
2166 mctrl |= TIOCM_DSR;
2167 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
2168 mctrl |= TIOCM_CAR;
2169
2170 return mctrl;
2171}
2172
2173static void sci_enable_ms(struct uart_port *port)
2174{
2175 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2176}
2177
2178static void sci_break_ctl(struct uart_port *port, int break_state)
2179{
2180 unsigned short scscr, scsptr;
2181 unsigned long flags;
2182
2183 /* check whether the port has SCSPTR */
2184 if (!sci_getreg(port, SCSPTR)->size) {
2185 /*
2186 * Not supported by hardware. Most parts couple break and rx
2187 * interrupts together, with break detection always enabled.
2188 */
2189 return;
2190 }
2191
2192 uart_port_lock_irqsave(port, &flags);
2193 scsptr = sci_serial_in(port, SCSPTR);
2194 scscr = sci_serial_in(port, SCSCR);
2195
2196 if (break_state == -1) {
2197 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2198 scscr &= ~SCSCR_TE;
2199 } else {
2200 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2201 scscr |= SCSCR_TE;
2202 }
2203
2204 sci_serial_out(port, SCSPTR, scsptr);
2205 sci_serial_out(port, SCSCR, scscr);
2206 uart_port_unlock_irqrestore(port, flags);
2207}
2208
2209static int sci_startup(struct uart_port *port)
2210{
2211 struct sci_port *s = to_sci_port(port);
2212 int ret;
2213
2214 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2215
2216 sci_request_dma(port);
2217
2218 ret = sci_request_irq(s);
2219 if (unlikely(ret < 0)) {
2220 sci_free_dma(port);
2221 return ret;
2222 }
2223
2224 return 0;
2225}
2226
2227static void sci_shutdown(struct uart_port *port)
2228{
2229 struct sci_port *s = to_sci_port(port);
2230 unsigned long flags;
2231 u16 scr;
2232
2233 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2234
2235 s->autorts = false;
2236 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2237
2238 uart_port_lock_irqsave(port, &flags);
2239 sci_stop_rx(port);
2240 sci_stop_tx(port);
2241 /*
2242 * Stop RX and TX, disable related interrupts, keep clock source
2243 * and HSCIF TOT bits
2244 */
2245 scr = sci_serial_in(port, SCSCR);
2246 sci_serial_out(port, SCSCR,
2247 scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2248 uart_port_unlock_irqrestore(port, flags);
2249
2250#ifdef CONFIG_SERIAL_SH_SCI_DMA
2251 if (s->chan_rx_saved) {
2252 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2253 port->line);
2254 hrtimer_cancel(&s->rx_timer);
2255 }
2256#endif
2257
2258 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2259 del_timer_sync(&s->rx_fifo_timer);
2260 sci_free_irq(s);
2261 sci_free_dma(port);
2262}
2263
2264static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2265 unsigned int *srr)
2266{
2267 unsigned long freq = s->clk_rates[SCI_SCK];
2268 int err, min_err = INT_MAX;
2269 unsigned int sr;
2270
2271 if (s->port.type != PORT_HSCIF)
2272 freq *= 2;
2273
2274 for_each_sr(sr, s) {
2275 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2276 if (abs(err) >= abs(min_err))
2277 continue;
2278
2279 min_err = err;
2280 *srr = sr - 1;
2281
2282 if (!err)
2283 break;
2284 }
2285
2286 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2287 *srr + 1);
2288 return min_err;
2289}
2290
2291static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2292 unsigned long freq, unsigned int *dlr,
2293 unsigned int *srr)
2294{
2295 int err, min_err = INT_MAX;
2296 unsigned int sr, dl;
2297
2298 if (s->port.type != PORT_HSCIF)
2299 freq *= 2;
2300
2301 for_each_sr(sr, s) {
2302 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2303 dl = clamp(dl, 1U, 65535U);
2304
2305 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2306 if (abs(err) >= abs(min_err))
2307 continue;
2308
2309 min_err = err;
2310 *dlr = dl;
2311 *srr = sr - 1;
2312
2313 if (!err)
2314 break;
2315 }
2316
2317 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2318 min_err, *dlr, *srr + 1);
2319 return min_err;
2320}
2321
2322/* calculate sample rate, BRR, and clock select */
2323static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2324 unsigned int *brr, unsigned int *srr,
2325 unsigned int *cks)
2326{
2327 unsigned long freq = s->clk_rates[SCI_FCK];
2328 unsigned int sr, br, prediv, scrate, c;
2329 int err, min_err = INT_MAX;
2330
2331 if (s->port.type != PORT_HSCIF)
2332 freq *= 2;
2333
2334 /*
2335 * Find the combination of sample rate and clock select with the
2336 * smallest deviation from the desired baud rate.
2337 * Prefer high sample rates to maximise the receive margin.
2338 *
2339 * M: Receive margin (%)
2340 * N: Ratio of bit rate to clock (N = sampling rate)
2341 * D: Clock duty (D = 0 to 1.0)
2342 * L: Frame length (L = 9 to 12)
2343 * F: Absolute value of clock frequency deviation
2344 *
2345 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2346 * (|D - 0.5| / N * (1 + F))|
2347 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2348 */
2349 for_each_sr(sr, s) {
2350 for (c = 0; c <= 3; c++) {
2351 /* integerized formulas from HSCIF documentation */
2352 prediv = sr << (2 * c + 1);
2353
2354 /*
2355 * We need to calculate:
2356 *
2357 * br = freq / (prediv * bps) clamped to [1..256]
2358 * err = freq / (br * prediv) - bps
2359 *
2360 * Watch out for overflow when calculating the desired
2361 * sampling clock rate!
2362 */
2363 if (bps > UINT_MAX / prediv)
2364 break;
2365
2366 scrate = prediv * bps;
2367 br = DIV_ROUND_CLOSEST(freq, scrate);
2368 br = clamp(br, 1U, 256U);
2369
2370 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2371 if (abs(err) >= abs(min_err))
2372 continue;
2373
2374 min_err = err;
2375 *brr = br - 1;
2376 *srr = sr - 1;
2377 *cks = c;
2378
2379 if (!err)
2380 goto found;
2381 }
2382 }
2383
2384found:
2385 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2386 min_err, *brr, *srr + 1, *cks);
2387 return min_err;
2388}
2389
2390static void sci_reset(struct uart_port *port)
2391{
2392 const struct plat_sci_reg *reg;
2393 unsigned int status;
2394 struct sci_port *s = to_sci_port(port);
2395
2396 sci_serial_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2397
2398 reg = sci_getreg(port, SCFCR);
2399 if (reg->size)
2400 sci_serial_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2401
2402 sci_clear_SCxSR(port,
2403 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2404 SCxSR_BREAK_CLEAR(port));
2405 if (sci_getreg(port, SCLSR)->size) {
2406 status = sci_serial_in(port, SCLSR);
2407 status &= ~(SCLSR_TO | SCLSR_ORER);
2408 sci_serial_out(port, SCLSR, status);
2409 }
2410
2411 if (s->rx_trigger > 1) {
2412 if (s->rx_fifo_timeout) {
2413 scif_set_rtrg(port, 1);
2414 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2415 } else {
2416 if (port->type == PORT_SCIFA ||
2417 port->type == PORT_SCIFB)
2418 scif_set_rtrg(port, 1);
2419 else
2420 scif_set_rtrg(port, s->rx_trigger);
2421 }
2422 }
2423}
2424
2425static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2426 const struct ktermios *old)
2427{
2428 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2429 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2430 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2431 struct sci_port *s = to_sci_port(port);
2432 const struct plat_sci_reg *reg;
2433 int min_err = INT_MAX, err;
2434 unsigned long max_freq = 0;
2435 int best_clk = -1;
2436 unsigned long flags;
2437
2438 if ((termios->c_cflag & CSIZE) == CS7) {
2439 smr_val |= SCSMR_CHR;
2440 } else {
2441 termios->c_cflag &= ~CSIZE;
2442 termios->c_cflag |= CS8;
2443 }
2444 if (termios->c_cflag & PARENB)
2445 smr_val |= SCSMR_PE;
2446 if (termios->c_cflag & PARODD)
2447 smr_val |= SCSMR_PE | SCSMR_ODD;
2448 if (termios->c_cflag & CSTOPB)
2449 smr_val |= SCSMR_STOP;
2450
2451 /*
2452 * earlyprintk comes here early on with port->uartclk set to zero.
2453 * the clock framework is not up and running at this point so here
2454 * we assume that 115200 is the maximum baud rate. please note that
2455 * the baud rate is not programmed during earlyprintk - it is assumed
2456 * that the previous boot loader has enabled required clocks and
2457 * setup the baud rate generator hardware for us already.
2458 */
2459 if (!port->uartclk) {
2460 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2461 goto done;
2462 }
2463
2464 for (i = 0; i < SCI_NUM_CLKS; i++)
2465 max_freq = max(max_freq, s->clk_rates[i]);
2466
2467 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2468 if (!baud)
2469 goto done;
2470
2471 /*
2472 * There can be multiple sources for the sampling clock. Find the one
2473 * that gives us the smallest deviation from the desired baud rate.
2474 */
2475
2476 /* Optional Undivided External Clock */
2477 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2478 port->type != PORT_SCIFB) {
2479 err = sci_sck_calc(s, baud, &srr1);
2480 if (abs(err) < abs(min_err)) {
2481 best_clk = SCI_SCK;
2482 scr_val = SCSCR_CKE1;
2483 sccks = SCCKS_CKS;
2484 min_err = err;
2485 srr = srr1;
2486 if (!err)
2487 goto done;
2488 }
2489 }
2490
2491 /* Optional BRG Frequency Divided External Clock */
2492 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2493 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2494 &srr1);
2495 if (abs(err) < abs(min_err)) {
2496 best_clk = SCI_SCIF_CLK;
2497 scr_val = SCSCR_CKE1;
2498 sccks = 0;
2499 min_err = err;
2500 dl = dl1;
2501 srr = srr1;
2502 if (!err)
2503 goto done;
2504 }
2505 }
2506
2507 /* Optional BRG Frequency Divided Internal Clock */
2508 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2509 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2510 &srr1);
2511 if (abs(err) < abs(min_err)) {
2512 best_clk = SCI_BRG_INT;
2513 scr_val = SCSCR_CKE1;
2514 sccks = SCCKS_XIN;
2515 min_err = err;
2516 dl = dl1;
2517 srr = srr1;
2518 if (!min_err)
2519 goto done;
2520 }
2521 }
2522
2523 /* Divided Functional Clock using standard Bit Rate Register */
2524 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2525 if (abs(err) < abs(min_err)) {
2526 best_clk = SCI_FCK;
2527 scr_val = 0;
2528 min_err = err;
2529 brr = brr1;
2530 srr = srr1;
2531 cks = cks1;
2532 }
2533
2534done:
2535 if (best_clk >= 0)
2536 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2537 s->clks[best_clk], baud, min_err);
2538
2539 sci_port_enable(s);
2540
2541 /*
2542 * Program the optional External Baud Rate Generator (BRG) first.
2543 * It controls the mux to select (H)SCK or frequency divided clock.
2544 */
2545 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2546 sci_serial_out(port, SCDL, dl);
2547 sci_serial_out(port, SCCKS, sccks);
2548 }
2549
2550 uart_port_lock_irqsave(port, &flags);
2551
2552 sci_reset(port);
2553
2554 uart_update_timeout(port, termios->c_cflag, baud);
2555
2556 /* byte size and parity */
2557 bits = tty_get_frame_size(termios->c_cflag);
2558
2559 if (sci_getreg(port, SEMR)->size)
2560 sci_serial_out(port, SEMR, 0);
2561
2562 if (best_clk >= 0) {
2563 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2564 switch (srr + 1) {
2565 case 5: smr_val |= SCSMR_SRC_5; break;
2566 case 7: smr_val |= SCSMR_SRC_7; break;
2567 case 11: smr_val |= SCSMR_SRC_11; break;
2568 case 13: smr_val |= SCSMR_SRC_13; break;
2569 case 16: smr_val |= SCSMR_SRC_16; break;
2570 case 17: smr_val |= SCSMR_SRC_17; break;
2571 case 19: smr_val |= SCSMR_SRC_19; break;
2572 case 27: smr_val |= SCSMR_SRC_27; break;
2573 }
2574 smr_val |= cks;
2575 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2576 sci_serial_out(port, SCSMR, smr_val);
2577 sci_serial_out(port, SCBRR, brr);
2578 if (sci_getreg(port, HSSRR)->size) {
2579 unsigned int hssrr = srr | HSCIF_SRE;
2580 /* Calculate deviation from intended rate at the
2581 * center of the last stop bit in sampling clocks.
2582 */
2583 int last_stop = bits * 2 - 1;
2584 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2585 (int)(srr + 1),
2586 2 * (int)baud);
2587
2588 if (abs(deviation) >= 2) {
2589 /* At least two sampling clocks off at the
2590 * last stop bit; we can increase the error
2591 * margin by shifting the sampling point.
2592 */
2593 int shift = clamp(deviation / 2, -8, 7);
2594
2595 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2596 HSCIF_SRHP_MASK;
2597 hssrr |= HSCIF_SRDE;
2598 }
2599 sci_serial_out(port, HSSRR, hssrr);
2600 }
2601
2602 /* Wait one bit interval */
2603 udelay((1000000 + (baud - 1)) / baud);
2604 } else {
2605 /* Don't touch the bit rate configuration */
2606 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2607 smr_val |= sci_serial_in(port, SCSMR) &
2608 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2609 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2610 sci_serial_out(port, SCSMR, smr_val);
2611 }
2612
2613 sci_init_pins(port, termios->c_cflag);
2614
2615 port->status &= ~UPSTAT_AUTOCTS;
2616 s->autorts = false;
2617 reg = sci_getreg(port, SCFCR);
2618 if (reg->size) {
2619 unsigned short ctrl = sci_serial_in(port, SCFCR);
2620
2621 if ((port->flags & UPF_HARD_FLOW) &&
2622 (termios->c_cflag & CRTSCTS)) {
2623 /* There is no CTS interrupt to restart the hardware */
2624 port->status |= UPSTAT_AUTOCTS;
2625 /* MCE is enabled when RTS is raised */
2626 s->autorts = true;
2627 }
2628
2629 /*
2630 * As we've done a sci_reset() above, ensure we don't
2631 * interfere with the FIFOs while toggling MCE. As the
2632 * reset values could still be set, simply mask them out.
2633 */
2634 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2635
2636 sci_serial_out(port, SCFCR, ctrl);
2637 }
2638 if (port->flags & UPF_HARD_FLOW) {
2639 /* Refresh (Auto) RTS */
2640 sci_set_mctrl(port, port->mctrl);
2641 }
2642
2643 /*
2644 * For SCI, TE (transmit enable) must be set after setting TIE
2645 * (transmit interrupt enable) or in the same instruction to
2646 * start the transmitting process. So skip setting TE here for SCI.
2647 */
2648 if (port->type != PORT_SCI)
2649 scr_val |= SCSCR_TE;
2650 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2651 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2652 if ((srr + 1 == 5) &&
2653 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2654 /*
2655 * In asynchronous mode, when the sampling rate is 1/5, first
2656 * received data may become invalid on some SCIFA and SCIFB.
2657 * To avoid this problem wait more than 1 serial data time (1
2658 * bit time x serial data number) after setting SCSCR.RE = 1.
2659 */
2660 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2661 }
2662
2663 /* Calculate delay for 2 DMA buffers (4 FIFO). */
2664 s->rx_frame = (10000 * bits) / (baud / 100);
2665#ifdef CONFIG_SERIAL_SH_SCI_DMA
2666 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2667#endif
2668
2669 if ((termios->c_cflag & CREAD) != 0)
2670 sci_start_rx(port);
2671
2672 uart_port_unlock_irqrestore(port, flags);
2673
2674 sci_port_disable(s);
2675
2676 if (UART_ENABLE_MS(port, termios->c_cflag))
2677 sci_enable_ms(port);
2678}
2679
2680static void sci_pm(struct uart_port *port, unsigned int state,
2681 unsigned int oldstate)
2682{
2683 struct sci_port *sci_port = to_sci_port(port);
2684
2685 switch (state) {
2686 case UART_PM_STATE_OFF:
2687 sci_port_disable(sci_port);
2688 break;
2689 default:
2690 sci_port_enable(sci_port);
2691 break;
2692 }
2693}
2694
2695static const char *sci_type(struct uart_port *port)
2696{
2697 switch (port->type) {
2698 case PORT_IRDA:
2699 return "irda";
2700 case PORT_SCI:
2701 return "sci";
2702 case PORT_SCIF:
2703 return "scif";
2704 case PORT_SCIFA:
2705 return "scifa";
2706 case PORT_SCIFB:
2707 return "scifb";
2708 case PORT_HSCIF:
2709 return "hscif";
2710 }
2711
2712 return NULL;
2713}
2714
2715static int sci_remap_port(struct uart_port *port)
2716{
2717 struct sci_port *sport = to_sci_port(port);
2718
2719 /*
2720 * Nothing to do if there's already an established membase.
2721 */
2722 if (port->membase)
2723 return 0;
2724
2725 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2726 port->membase = ioremap(port->mapbase, sport->reg_size);
2727 if (unlikely(!port->membase)) {
2728 dev_err(port->dev, "can't remap port#%d\n", port->line);
2729 return -ENXIO;
2730 }
2731 } else {
2732 /*
2733 * For the simple (and majority of) cases where we don't
2734 * need to do any remapping, just cast the cookie
2735 * directly.
2736 */
2737 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2738 }
2739
2740 return 0;
2741}
2742
2743static void sci_release_port(struct uart_port *port)
2744{
2745 struct sci_port *sport = to_sci_port(port);
2746
2747 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2748 iounmap(port->membase);
2749 port->membase = NULL;
2750 }
2751
2752 release_mem_region(port->mapbase, sport->reg_size);
2753}
2754
2755static int sci_request_port(struct uart_port *port)
2756{
2757 struct resource *res;
2758 struct sci_port *sport = to_sci_port(port);
2759 int ret;
2760
2761 res = request_mem_region(port->mapbase, sport->reg_size,
2762 dev_name(port->dev));
2763 if (unlikely(res == NULL)) {
2764 dev_err(port->dev, "request_mem_region failed.");
2765 return -EBUSY;
2766 }
2767
2768 ret = sci_remap_port(port);
2769 if (unlikely(ret != 0)) {
2770 release_resource(res);
2771 return ret;
2772 }
2773
2774 return 0;
2775}
2776
2777static void sci_config_port(struct uart_port *port, int flags)
2778{
2779 if (flags & UART_CONFIG_TYPE) {
2780 struct sci_port *sport = to_sci_port(port);
2781
2782 port->type = sport->cfg->type;
2783 sci_request_port(port);
2784 }
2785}
2786
2787static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2788{
2789 if (ser->baud_base < 2400)
2790 /* No paper tape reader for Mitch.. */
2791 return -EINVAL;
2792
2793 return 0;
2794}
2795
2796static const struct uart_ops sci_uart_ops = {
2797 .tx_empty = sci_tx_empty,
2798 .set_mctrl = sci_set_mctrl,
2799 .get_mctrl = sci_get_mctrl,
2800 .start_tx = sci_start_tx,
2801 .stop_tx = sci_stop_tx,
2802 .stop_rx = sci_stop_rx,
2803 .enable_ms = sci_enable_ms,
2804 .break_ctl = sci_break_ctl,
2805 .startup = sci_startup,
2806 .shutdown = sci_shutdown,
2807 .flush_buffer = sci_flush_buffer,
2808 .set_termios = sci_set_termios,
2809 .pm = sci_pm,
2810 .type = sci_type,
2811 .release_port = sci_release_port,
2812 .request_port = sci_request_port,
2813 .config_port = sci_config_port,
2814 .verify_port = sci_verify_port,
2815#ifdef CONFIG_CONSOLE_POLL
2816 .poll_get_char = sci_poll_get_char,
2817 .poll_put_char = sci_poll_put_char,
2818#endif
2819};
2820
2821static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2822{
2823 const char *clk_names[] = {
2824 [SCI_FCK] = "fck",
2825 [SCI_SCK] = "sck",
2826 [SCI_BRG_INT] = "brg_int",
2827 [SCI_SCIF_CLK] = "scif_clk",
2828 };
2829 struct clk *clk;
2830 unsigned int i;
2831
2832 if (sci_port->cfg->type == PORT_HSCIF)
2833 clk_names[SCI_SCK] = "hsck";
2834
2835 for (i = 0; i < SCI_NUM_CLKS; i++) {
2836 clk = devm_clk_get_optional(dev, clk_names[i]);
2837 if (IS_ERR(clk))
2838 return PTR_ERR(clk);
2839
2840 if (!clk && i == SCI_FCK) {
2841 /*
2842 * Not all SH platforms declare a clock lookup entry
2843 * for SCI devices, in which case we need to get the
2844 * global "peripheral_clk" clock.
2845 */
2846 clk = devm_clk_get(dev, "peripheral_clk");
2847 if (IS_ERR(clk))
2848 return dev_err_probe(dev, PTR_ERR(clk),
2849 "failed to get %s\n",
2850 clk_names[i]);
2851 }
2852
2853 if (!clk)
2854 dev_dbg(dev, "failed to get %s\n", clk_names[i]);
2855 else
2856 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2857 clk, clk_get_rate(clk));
2858 sci_port->clks[i] = clk;
2859 }
2860 return 0;
2861}
2862
2863static const struct sci_port_params *
2864sci_probe_regmap(const struct plat_sci_port *cfg)
2865{
2866 unsigned int regtype;
2867
2868 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2869 return &sci_port_params[cfg->regtype];
2870
2871 switch (cfg->type) {
2872 case PORT_SCI:
2873 regtype = SCIx_SCI_REGTYPE;
2874 break;
2875 case PORT_IRDA:
2876 regtype = SCIx_IRDA_REGTYPE;
2877 break;
2878 case PORT_SCIFA:
2879 regtype = SCIx_SCIFA_REGTYPE;
2880 break;
2881 case PORT_SCIFB:
2882 regtype = SCIx_SCIFB_REGTYPE;
2883 break;
2884 case PORT_SCIF:
2885 /*
2886 * The SH-4 is a bit of a misnomer here, although that's
2887 * where this particular port layout originated. This
2888 * configuration (or some slight variation thereof)
2889 * remains the dominant model for all SCIFs.
2890 */
2891 regtype = SCIx_SH4_SCIF_REGTYPE;
2892 break;
2893 case PORT_HSCIF:
2894 regtype = SCIx_HSCIF_REGTYPE;
2895 break;
2896 default:
2897 pr_err("Can't probe register map for given port\n");
2898 return NULL;
2899 }
2900
2901 return &sci_port_params[regtype];
2902}
2903
2904static int sci_init_single(struct platform_device *dev,
2905 struct sci_port *sci_port, unsigned int index,
2906 const struct plat_sci_port *p, bool early)
2907{
2908 struct uart_port *port = &sci_port->port;
2909 const struct resource *res;
2910 unsigned int i;
2911 int ret;
2912
2913 sci_port->cfg = p;
2914
2915 port->ops = &sci_uart_ops;
2916 port->iotype = UPIO_MEM;
2917 port->line = index;
2918 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
2919
2920 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2921 if (res == NULL)
2922 return -ENOMEM;
2923
2924 port->mapbase = res->start;
2925 sci_port->reg_size = resource_size(res);
2926
2927 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
2928 if (i)
2929 sci_port->irqs[i] = platform_get_irq_optional(dev, i);
2930 else
2931 sci_port->irqs[i] = platform_get_irq(dev, i);
2932 }
2933
2934 /*
2935 * The fourth interrupt on SCI port is transmit end interrupt, so
2936 * shuffle the interrupts.
2937 */
2938 if (p->type == PORT_SCI)
2939 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]);
2940
2941 /* The SCI generates several interrupts. They can be muxed together or
2942 * connected to different interrupt lines. In the muxed case only one
2943 * interrupt resource is specified as there is only one interrupt ID.
2944 * In the non-muxed case, up to 6 interrupt signals might be generated
2945 * from the SCI, however those signals might have their own individual
2946 * interrupt ID numbers, or muxed together with another interrupt.
2947 */
2948 if (sci_port->irqs[0] < 0)
2949 return -ENXIO;
2950
2951 if (sci_port->irqs[1] < 0)
2952 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
2953 sci_port->irqs[i] = sci_port->irqs[0];
2954
2955 sci_port->params = sci_probe_regmap(p);
2956 if (unlikely(sci_port->params == NULL))
2957 return -EINVAL;
2958
2959 switch (p->type) {
2960 case PORT_SCIFB:
2961 sci_port->rx_trigger = 48;
2962 break;
2963 case PORT_HSCIF:
2964 sci_port->rx_trigger = 64;
2965 break;
2966 case PORT_SCIFA:
2967 sci_port->rx_trigger = 32;
2968 break;
2969 case PORT_SCIF:
2970 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2971 /* RX triggering not implemented for this IP */
2972 sci_port->rx_trigger = 1;
2973 else
2974 sci_port->rx_trigger = 8;
2975 break;
2976 default:
2977 sci_port->rx_trigger = 1;
2978 break;
2979 }
2980
2981 sci_port->rx_fifo_timeout = 0;
2982 sci_port->hscif_tot = 0;
2983
2984 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2985 * match the SoC datasheet, this should be investigated. Let platform
2986 * data override the sampling rate for now.
2987 */
2988 sci_port->sampling_rate_mask = p->sampling_rate
2989 ? SCI_SR(p->sampling_rate)
2990 : sci_port->params->sampling_rate_mask;
2991
2992 if (!early) {
2993 ret = sci_init_clocks(sci_port, &dev->dev);
2994 if (ret < 0)
2995 return ret;
2996
2997 port->dev = &dev->dev;
2998
2999 pm_runtime_enable(&dev->dev);
3000 }
3001
3002 port->type = p->type;
3003 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
3004 port->fifosize = sci_port->params->fifosize;
3005
3006 if (port->type == PORT_SCI && !dev->dev.of_node) {
3007 if (sci_port->reg_size >= 0x20)
3008 port->regshift = 2;
3009 else
3010 port->regshift = 1;
3011 }
3012
3013 /*
3014 * The UART port needs an IRQ value, so we peg this to the RX IRQ
3015 * for the multi-IRQ ports, which is where we are primarily
3016 * concerned with the shutdown path synchronization.
3017 *
3018 * For the muxed case there's nothing more to do.
3019 */
3020 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
3021 port->irqflags = 0;
3022
3023 return 0;
3024}
3025
3026static void sci_cleanup_single(struct sci_port *port)
3027{
3028 pm_runtime_disable(port->port.dev);
3029}
3030
3031#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
3032 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
3033static void serial_console_putchar(struct uart_port *port, unsigned char ch)
3034{
3035 sci_poll_put_char(port, ch);
3036}
3037
3038/*
3039 * Print a string to the serial port trying not to disturb
3040 * any possible real use of the port...
3041 */
3042static void serial_console_write(struct console *co, const char *s,
3043 unsigned count)
3044{
3045 struct sci_port *sci_port = &sci_ports[co->index];
3046 struct uart_port *port = &sci_port->port;
3047 unsigned short bits, ctrl, ctrl_temp;
3048 unsigned long flags;
3049 int locked = 1;
3050
3051 if (port->sysrq)
3052 locked = 0;
3053 else if (oops_in_progress)
3054 locked = uart_port_trylock_irqsave(port, &flags);
3055 else
3056 uart_port_lock_irqsave(port, &flags);
3057
3058 /* first save SCSCR then disable interrupts, keep clock source */
3059 ctrl = sci_serial_in(port, SCSCR);
3060 ctrl_temp = SCSCR_RE | SCSCR_TE |
3061 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
3062 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
3063 sci_serial_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
3064
3065 uart_console_write(port, s, count, serial_console_putchar);
3066
3067 /* wait until fifo is empty and last bit has been transmitted */
3068 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3069 while ((sci_serial_in(port, SCxSR) & bits) != bits)
3070 cpu_relax();
3071
3072 /* restore the SCSCR */
3073 sci_serial_out(port, SCSCR, ctrl);
3074
3075 if (locked)
3076 uart_port_unlock_irqrestore(port, flags);
3077}
3078
3079static int serial_console_setup(struct console *co, char *options)
3080{
3081 struct sci_port *sci_port;
3082 struct uart_port *port;
3083 int baud = 115200;
3084 int bits = 8;
3085 int parity = 'n';
3086 int flow = 'n';
3087 int ret;
3088
3089 /*
3090 * Refuse to handle any bogus ports.
3091 */
3092 if (co->index < 0 || co->index >= SCI_NPORTS)
3093 return -ENODEV;
3094
3095 sci_port = &sci_ports[co->index];
3096 port = &sci_port->port;
3097
3098 /*
3099 * Refuse to handle uninitialized ports.
3100 */
3101 if (!port->ops)
3102 return -ENODEV;
3103
3104 ret = sci_remap_port(port);
3105 if (unlikely(ret != 0))
3106 return ret;
3107
3108 if (options)
3109 uart_parse_options(options, &baud, &parity, &bits, &flow);
3110
3111 return uart_set_options(port, co, baud, parity, bits, flow);
3112}
3113
3114static struct console serial_console = {
3115 .name = "ttySC",
3116 .device = uart_console_device,
3117 .write = serial_console_write,
3118 .setup = serial_console_setup,
3119 .flags = CON_PRINTBUFFER,
3120 .index = -1,
3121 .data = &sci_uart_driver,
3122};
3123
3124#ifdef CONFIG_SUPERH
3125static char early_serial_buf[32];
3126
3127static int early_serial_console_setup(struct console *co, char *options)
3128{
3129 /*
3130 * This early console is always registered using the earlyprintk=
3131 * parameter, which does not call add_preferred_console(). Thus
3132 * @options is always NULL and the options for this early console
3133 * are passed using a custom buffer.
3134 */
3135 WARN_ON(options);
3136
3137 return serial_console_setup(co, early_serial_buf);
3138}
3139
3140static struct console early_serial_console = {
3141 .name = "early_ttySC",
3142 .write = serial_console_write,
3143 .setup = early_serial_console_setup,
3144 .flags = CON_PRINTBUFFER,
3145 .index = -1,
3146};
3147
3148static int sci_probe_earlyprintk(struct platform_device *pdev)
3149{
3150 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3151
3152 if (early_serial_console.data)
3153 return -EEXIST;
3154
3155 early_serial_console.index = pdev->id;
3156
3157 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3158
3159 if (!strstr(early_serial_buf, "keep"))
3160 early_serial_console.flags |= CON_BOOT;
3161
3162 register_console(&early_serial_console);
3163 return 0;
3164}
3165#endif
3166
3167#define SCI_CONSOLE (&serial_console)
3168
3169#else
3170static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3171{
3172 return -EINVAL;
3173}
3174
3175#define SCI_CONSOLE NULL
3176
3177#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3178
3179static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3180
3181static DEFINE_MUTEX(sci_uart_registration_lock);
3182static struct uart_driver sci_uart_driver = {
3183 .owner = THIS_MODULE,
3184 .driver_name = "sci",
3185 .dev_name = "ttySC",
3186 .major = SCI_MAJOR,
3187 .minor = SCI_MINOR_START,
3188 .nr = SCI_NPORTS,
3189 .cons = SCI_CONSOLE,
3190};
3191
3192static void sci_remove(struct platform_device *dev)
3193{
3194 struct sci_port *port = platform_get_drvdata(dev);
3195 unsigned int type = port->port.type; /* uart_remove_... clears it */
3196
3197 sci_ports_in_use &= ~BIT(port->port.line);
3198 uart_remove_one_port(&sci_uart_driver, &port->port);
3199
3200 sci_cleanup_single(port);
3201
3202 if (port->port.fifosize > 1)
3203 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3204 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
3205 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3206}
3207
3208
3209#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3210#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3211#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3212
3213static const struct of_device_id of_sci_match[] __maybe_unused = {
3214 /* SoC-specific types */
3215 {
3216 .compatible = "renesas,scif-r7s72100",
3217 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3218 },
3219 {
3220 .compatible = "renesas,scif-r7s9210",
3221 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3222 },
3223 {
3224 .compatible = "renesas,scif-r9a07g044",
3225 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3226 },
3227 /* Family-specific types */
3228 {
3229 .compatible = "renesas,rcar-gen1-scif",
3230 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3231 }, {
3232 .compatible = "renesas,rcar-gen2-scif",
3233 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3234 }, {
3235 .compatible = "renesas,rcar-gen3-scif",
3236 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3237 }, {
3238 .compatible = "renesas,rcar-gen4-scif",
3239 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3240 },
3241 /* Generic types */
3242 {
3243 .compatible = "renesas,scif",
3244 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3245 }, {
3246 .compatible = "renesas,scifa",
3247 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3248 }, {
3249 .compatible = "renesas,scifb",
3250 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3251 }, {
3252 .compatible = "renesas,hscif",
3253 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3254 }, {
3255 .compatible = "renesas,sci",
3256 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3257 }, {
3258 /* Terminator */
3259 },
3260};
3261MODULE_DEVICE_TABLE(of, of_sci_match);
3262
3263static void sci_reset_control_assert(void *data)
3264{
3265 reset_control_assert(data);
3266}
3267
3268static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3269 unsigned int *dev_id)
3270{
3271 struct device_node *np = pdev->dev.of_node;
3272 struct reset_control *rstc;
3273 struct plat_sci_port *p;
3274 struct sci_port *sp;
3275 const void *data;
3276 int id, ret;
3277
3278 if (!IS_ENABLED(CONFIG_OF) || !np)
3279 return ERR_PTR(-EINVAL);
3280
3281 data = of_device_get_match_data(&pdev->dev);
3282
3283 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
3284 if (IS_ERR(rstc))
3285 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc),
3286 "failed to get reset ctrl\n"));
3287
3288 ret = reset_control_deassert(rstc);
3289 if (ret) {
3290 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret);
3291 return ERR_PTR(ret);
3292 }
3293
3294 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc);
3295 if (ret) {
3296 dev_err(&pdev->dev, "failed to register assert devm action, %d\n",
3297 ret);
3298 return ERR_PTR(ret);
3299 }
3300
3301 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3302 if (!p)
3303 return ERR_PTR(-ENOMEM);
3304
3305 /* Get the line number from the aliases node. */
3306 id = of_alias_get_id(np, "serial");
3307 if (id < 0 && ~sci_ports_in_use)
3308 id = ffz(sci_ports_in_use);
3309 if (id < 0) {
3310 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3311 return ERR_PTR(-EINVAL);
3312 }
3313 if (id >= ARRAY_SIZE(sci_ports)) {
3314 dev_err(&pdev->dev, "serial%d out of range\n", id);
3315 return ERR_PTR(-EINVAL);
3316 }
3317
3318 sp = &sci_ports[id];
3319 *dev_id = id;
3320
3321 p->type = SCI_OF_TYPE(data);
3322 p->regtype = SCI_OF_REGTYPE(data);
3323
3324 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3325
3326 return p;
3327}
3328
3329static int sci_probe_single(struct platform_device *dev,
3330 unsigned int index,
3331 struct plat_sci_port *p,
3332 struct sci_port *sciport)
3333{
3334 int ret;
3335
3336 /* Sanity check */
3337 if (unlikely(index >= SCI_NPORTS)) {
3338 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3339 index+1, SCI_NPORTS);
3340 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3341 return -EINVAL;
3342 }
3343 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3344 if (sci_ports_in_use & BIT(index))
3345 return -EBUSY;
3346
3347 mutex_lock(&sci_uart_registration_lock);
3348 if (!sci_uart_driver.state) {
3349 ret = uart_register_driver(&sci_uart_driver);
3350 if (ret) {
3351 mutex_unlock(&sci_uart_registration_lock);
3352 return ret;
3353 }
3354 }
3355 mutex_unlock(&sci_uart_registration_lock);
3356
3357 ret = sci_init_single(dev, sciport, index, p, false);
3358 if (ret)
3359 return ret;
3360
3361 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3362 if (IS_ERR(sciport->gpios))
3363 return PTR_ERR(sciport->gpios);
3364
3365 if (sciport->has_rtscts) {
3366 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
3367 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
3368 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3369 return -EINVAL;
3370 }
3371 sciport->port.flags |= UPF_HARD_FLOW;
3372 }
3373
3374 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3375 if (ret) {
3376 sci_cleanup_single(sciport);
3377 return ret;
3378 }
3379
3380 return 0;
3381}
3382
3383static int sci_probe(struct platform_device *dev)
3384{
3385 struct plat_sci_port *p;
3386 struct sci_port *sp;
3387 unsigned int dev_id;
3388 int ret;
3389
3390 /*
3391 * If we've come here via earlyprintk initialization, head off to
3392 * the special early probe. We don't have sufficient device state
3393 * to make it beyond this yet.
3394 */
3395#ifdef CONFIG_SUPERH
3396 if (is_sh_early_platform_device(dev))
3397 return sci_probe_earlyprintk(dev);
3398#endif
3399
3400 if (dev->dev.of_node) {
3401 p = sci_parse_dt(dev, &dev_id);
3402 if (IS_ERR(p))
3403 return PTR_ERR(p);
3404 } else {
3405 p = dev->dev.platform_data;
3406 if (p == NULL) {
3407 dev_err(&dev->dev, "no platform data supplied\n");
3408 return -EINVAL;
3409 }
3410
3411 dev_id = dev->id;
3412 }
3413
3414 sp = &sci_ports[dev_id];
3415 platform_set_drvdata(dev, sp);
3416
3417 ret = sci_probe_single(dev, dev_id, p, sp);
3418 if (ret)
3419 return ret;
3420
3421 if (sp->port.fifosize > 1) {
3422 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3423 if (ret)
3424 return ret;
3425 }
3426 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3427 sp->port.type == PORT_HSCIF) {
3428 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3429 if (ret) {
3430 if (sp->port.fifosize > 1) {
3431 device_remove_file(&dev->dev,
3432 &dev_attr_rx_fifo_trigger);
3433 }
3434 return ret;
3435 }
3436 }
3437
3438#ifdef CONFIG_SH_STANDARD_BIOS
3439 sh_bios_gdb_detach();
3440#endif
3441
3442 sci_ports_in_use |= BIT(dev_id);
3443 return 0;
3444}
3445
3446static __maybe_unused int sci_suspend(struct device *dev)
3447{
3448 struct sci_port *sport = dev_get_drvdata(dev);
3449
3450 if (sport)
3451 uart_suspend_port(&sci_uart_driver, &sport->port);
3452
3453 return 0;
3454}
3455
3456static __maybe_unused int sci_resume(struct device *dev)
3457{
3458 struct sci_port *sport = dev_get_drvdata(dev);
3459
3460 if (sport)
3461 uart_resume_port(&sci_uart_driver, &sport->port);
3462
3463 return 0;
3464}
3465
3466static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3467
3468static struct platform_driver sci_driver = {
3469 .probe = sci_probe,
3470 .remove_new = sci_remove,
3471 .driver = {
3472 .name = "sh-sci",
3473 .pm = &sci_dev_pm_ops,
3474 .of_match_table = of_match_ptr(of_sci_match),
3475 },
3476};
3477
3478static int __init sci_init(void)
3479{
3480 pr_info("%s\n", banner);
3481
3482 return platform_driver_register(&sci_driver);
3483}
3484
3485static void __exit sci_exit(void)
3486{
3487 platform_driver_unregister(&sci_driver);
3488
3489 if (sci_uart_driver.state)
3490 uart_unregister_driver(&sci_uart_driver);
3491}
3492
3493#if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
3494sh_early_platform_init_buffer("earlyprintk", &sci_driver,
3495 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3496#endif
3497#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3498static struct plat_sci_port port_cfg __initdata;
3499
3500static int __init early_console_setup(struct earlycon_device *device,
3501 int type)
3502{
3503 if (!device->port.membase)
3504 return -ENODEV;
3505
3506 device->port.type = type;
3507 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3508 port_cfg.type = type;
3509 sci_ports[0].cfg = &port_cfg;
3510 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3511 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3512 sci_serial_out(&sci_ports[0].port, SCSCR,
3513 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3514
3515 device->con->write = serial_console_write;
3516 return 0;
3517}
3518static int __init sci_early_console_setup(struct earlycon_device *device,
3519 const char *opt)
3520{
3521 return early_console_setup(device, PORT_SCI);
3522}
3523static int __init scif_early_console_setup(struct earlycon_device *device,
3524 const char *opt)
3525{
3526 return early_console_setup(device, PORT_SCIF);
3527}
3528static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3529 const char *opt)
3530{
3531 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3532 return early_console_setup(device, PORT_SCIF);
3533}
3534
3535static int __init scifa_early_console_setup(struct earlycon_device *device,
3536 const char *opt)
3537{
3538 return early_console_setup(device, PORT_SCIFA);
3539}
3540static int __init scifb_early_console_setup(struct earlycon_device *device,
3541 const char *opt)
3542{
3543 return early_console_setup(device, PORT_SCIFB);
3544}
3545static int __init hscif_early_console_setup(struct earlycon_device *device,
3546 const char *opt)
3547{
3548 return early_console_setup(device, PORT_HSCIF);
3549}
3550
3551OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3552OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3553OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3554OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
3555OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3556OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3557OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3558#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3559
3560module_init(sci_init);
3561module_exit(sci_exit);
3562
3563MODULE_LICENSE("GPL");
3564MODULE_ALIAS("platform:sh-sci");
3565MODULE_AUTHOR("Paul Mundt");
3566MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");