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1// SPDX-License-Identifier: GPL-2.0
2#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3
4#include <linux/errno.h>
5#include <linux/kernel.h>
6#include <linux/mm.h>
7#include <linux/smp.h>
8#include <linux/prctl.h>
9#include <linux/slab.h>
10#include <linux/sched.h>
11#include <linux/sched/idle.h>
12#include <linux/sched/debug.h>
13#include <linux/sched/task.h>
14#include <linux/sched/task_stack.h>
15#include <linux/init.h>
16#include <linux/export.h>
17#include <linux/pm.h>
18#include <linux/tick.h>
19#include <linux/random.h>
20#include <linux/user-return-notifier.h>
21#include <linux/dmi.h>
22#include <linux/utsname.h>
23#include <linux/stackprotector.h>
24#include <linux/cpuidle.h>
25#include <linux/acpi.h>
26#include <linux/elf-randomize.h>
27#include <trace/events/power.h>
28#include <linux/hw_breakpoint.h>
29#include <asm/cpu.h>
30#include <asm/apic.h>
31#include <asm/syscalls.h>
32#include <linux/uaccess.h>
33#include <asm/mwait.h>
34#include <asm/fpu/internal.h>
35#include <asm/debugreg.h>
36#include <asm/nmi.h>
37#include <asm/tlbflush.h>
38#include <asm/mce.h>
39#include <asm/vm86.h>
40#include <asm/switch_to.h>
41#include <asm/desc.h>
42#include <asm/prctl.h>
43#include <asm/spec-ctrl.h>
44#include <asm/proto.h>
45
46#include "process.h"
47
48/*
49 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
50 * no more per-task TSS's. The TSS size is kept cacheline-aligned
51 * so they are allowed to end up in the .data..cacheline_aligned
52 * section. Since TSS's are completely CPU-local, we want them
53 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
54 */
55__visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
56 .x86_tss = {
57 /*
58 * .sp0 is only used when entering ring 0 from a lower
59 * privilege level. Since the init task never runs anything
60 * but ring 0 code, there is no need for a valid value here.
61 * Poison it.
62 */
63 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
64
65 /*
66 * .sp1 is cpu_current_top_of_stack. The init task never
67 * runs user code, but cpu_current_top_of_stack should still
68 * be well defined before the first context switch.
69 */
70 .sp1 = TOP_OF_INIT_STACK,
71
72#ifdef CONFIG_X86_32
73 .ss0 = __KERNEL_DS,
74 .ss1 = __KERNEL_CS,
75 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
76#endif
77 },
78#ifdef CONFIG_X86_32
79 /*
80 * Note that the .io_bitmap member must be extra-big. This is because
81 * the CPU will access an additional byte beyond the end of the IO
82 * permission bitmap. The extra byte must be all 1 bits, and must
83 * be within the limit.
84 */
85 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 },
86#endif
87};
88EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
89
90DEFINE_PER_CPU(bool, __tss_limit_invalid);
91EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
92
93/*
94 * this gets called so that we can store lazy state into memory and copy the
95 * current task into the new thread.
96 */
97int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
98{
99 memcpy(dst, src, arch_task_struct_size);
100#ifdef CONFIG_VM86
101 dst->thread.vm86 = NULL;
102#endif
103
104 return fpu__copy(dst, src);
105}
106
107/*
108 * Free current thread data structures etc..
109 */
110void exit_thread(struct task_struct *tsk)
111{
112 struct thread_struct *t = &tsk->thread;
113 unsigned long *bp = t->io_bitmap_ptr;
114 struct fpu *fpu = &t->fpu;
115
116 if (bp) {
117 struct tss_struct *tss = &per_cpu(cpu_tss_rw, get_cpu());
118
119 t->io_bitmap_ptr = NULL;
120 clear_thread_flag(TIF_IO_BITMAP);
121 /*
122 * Careful, clear this in the TSS too:
123 */
124 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
125 t->io_bitmap_max = 0;
126 put_cpu();
127 kfree(bp);
128 }
129
130 free_vm86(t);
131
132 fpu__drop(fpu);
133}
134
135void flush_thread(void)
136{
137 struct task_struct *tsk = current;
138
139 flush_ptrace_hw_breakpoint(tsk);
140 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
141
142 fpu__clear(&tsk->thread.fpu);
143}
144
145void disable_TSC(void)
146{
147 preempt_disable();
148 if (!test_and_set_thread_flag(TIF_NOTSC))
149 /*
150 * Must flip the CPU state synchronously with
151 * TIF_NOTSC in the current running context.
152 */
153 cr4_set_bits(X86_CR4_TSD);
154 preempt_enable();
155}
156
157static void enable_TSC(void)
158{
159 preempt_disable();
160 if (test_and_clear_thread_flag(TIF_NOTSC))
161 /*
162 * Must flip the CPU state synchronously with
163 * TIF_NOTSC in the current running context.
164 */
165 cr4_clear_bits(X86_CR4_TSD);
166 preempt_enable();
167}
168
169int get_tsc_mode(unsigned long adr)
170{
171 unsigned int val;
172
173 if (test_thread_flag(TIF_NOTSC))
174 val = PR_TSC_SIGSEGV;
175 else
176 val = PR_TSC_ENABLE;
177
178 return put_user(val, (unsigned int __user *)adr);
179}
180
181int set_tsc_mode(unsigned int val)
182{
183 if (val == PR_TSC_SIGSEGV)
184 disable_TSC();
185 else if (val == PR_TSC_ENABLE)
186 enable_TSC();
187 else
188 return -EINVAL;
189
190 return 0;
191}
192
193DEFINE_PER_CPU(u64, msr_misc_features_shadow);
194
195static void set_cpuid_faulting(bool on)
196{
197 u64 msrval;
198
199 msrval = this_cpu_read(msr_misc_features_shadow);
200 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
201 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
202 this_cpu_write(msr_misc_features_shadow, msrval);
203 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
204}
205
206static void disable_cpuid(void)
207{
208 preempt_disable();
209 if (!test_and_set_thread_flag(TIF_NOCPUID)) {
210 /*
211 * Must flip the CPU state synchronously with
212 * TIF_NOCPUID in the current running context.
213 */
214 set_cpuid_faulting(true);
215 }
216 preempt_enable();
217}
218
219static void enable_cpuid(void)
220{
221 preempt_disable();
222 if (test_and_clear_thread_flag(TIF_NOCPUID)) {
223 /*
224 * Must flip the CPU state synchronously with
225 * TIF_NOCPUID in the current running context.
226 */
227 set_cpuid_faulting(false);
228 }
229 preempt_enable();
230}
231
232static int get_cpuid_mode(void)
233{
234 return !test_thread_flag(TIF_NOCPUID);
235}
236
237static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
238{
239 if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT))
240 return -ENODEV;
241
242 if (cpuid_enabled)
243 enable_cpuid();
244 else
245 disable_cpuid();
246
247 return 0;
248}
249
250/*
251 * Called immediately after a successful exec.
252 */
253void arch_setup_new_exec(void)
254{
255 /* If cpuid was previously disabled for this task, re-enable it. */
256 if (test_thread_flag(TIF_NOCPUID))
257 enable_cpuid();
258
259 /*
260 * Don't inherit TIF_SSBD across exec boundary when
261 * PR_SPEC_DISABLE_NOEXEC is used.
262 */
263 if (test_thread_flag(TIF_SSBD) &&
264 task_spec_ssb_noexec(current)) {
265 clear_thread_flag(TIF_SSBD);
266 task_clear_spec_ssb_disable(current);
267 task_clear_spec_ssb_noexec(current);
268 speculation_ctrl_update(task_thread_info(current)->flags);
269 }
270}
271
272static inline void switch_to_bitmap(struct thread_struct *prev,
273 struct thread_struct *next,
274 unsigned long tifp, unsigned long tifn)
275{
276 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
277
278 if (tifn & _TIF_IO_BITMAP) {
279 /*
280 * Copy the relevant range of the IO bitmap.
281 * Normally this is 128 bytes or less:
282 */
283 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
284 max(prev->io_bitmap_max, next->io_bitmap_max));
285 /*
286 * Make sure that the TSS limit is correct for the CPU
287 * to notice the IO bitmap.
288 */
289 refresh_tss_limit();
290 } else if (tifp & _TIF_IO_BITMAP) {
291 /*
292 * Clear any possible leftover bits:
293 */
294 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
295 }
296}
297
298#ifdef CONFIG_SMP
299
300struct ssb_state {
301 struct ssb_state *shared_state;
302 raw_spinlock_t lock;
303 unsigned int disable_state;
304 unsigned long local_state;
305};
306
307#define LSTATE_SSB 0
308
309static DEFINE_PER_CPU(struct ssb_state, ssb_state);
310
311void speculative_store_bypass_ht_init(void)
312{
313 struct ssb_state *st = this_cpu_ptr(&ssb_state);
314 unsigned int this_cpu = smp_processor_id();
315 unsigned int cpu;
316
317 st->local_state = 0;
318
319 /*
320 * Shared state setup happens once on the first bringup
321 * of the CPU. It's not destroyed on CPU hotunplug.
322 */
323 if (st->shared_state)
324 return;
325
326 raw_spin_lock_init(&st->lock);
327
328 /*
329 * Go over HT siblings and check whether one of them has set up the
330 * shared state pointer already.
331 */
332 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
333 if (cpu == this_cpu)
334 continue;
335
336 if (!per_cpu(ssb_state, cpu).shared_state)
337 continue;
338
339 /* Link it to the state of the sibling: */
340 st->shared_state = per_cpu(ssb_state, cpu).shared_state;
341 return;
342 }
343
344 /*
345 * First HT sibling to come up on the core. Link shared state of
346 * the first HT sibling to itself. The siblings on the same core
347 * which come up later will see the shared state pointer and link
348 * themself to the state of this CPU.
349 */
350 st->shared_state = st;
351}
352
353/*
354 * Logic is: First HT sibling enables SSBD for both siblings in the core
355 * and last sibling to disable it, disables it for the whole core. This how
356 * MSR_SPEC_CTRL works in "hardware":
357 *
358 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
359 */
360static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
361{
362 struct ssb_state *st = this_cpu_ptr(&ssb_state);
363 u64 msr = x86_amd_ls_cfg_base;
364
365 if (!static_cpu_has(X86_FEATURE_ZEN)) {
366 msr |= ssbd_tif_to_amd_ls_cfg(tifn);
367 wrmsrl(MSR_AMD64_LS_CFG, msr);
368 return;
369 }
370
371 if (tifn & _TIF_SSBD) {
372 /*
373 * Since this can race with prctl(), block reentry on the
374 * same CPU.
375 */
376 if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
377 return;
378
379 msr |= x86_amd_ls_cfg_ssbd_mask;
380
381 raw_spin_lock(&st->shared_state->lock);
382 /* First sibling enables SSBD: */
383 if (!st->shared_state->disable_state)
384 wrmsrl(MSR_AMD64_LS_CFG, msr);
385 st->shared_state->disable_state++;
386 raw_spin_unlock(&st->shared_state->lock);
387 } else {
388 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
389 return;
390
391 raw_spin_lock(&st->shared_state->lock);
392 st->shared_state->disable_state--;
393 if (!st->shared_state->disable_state)
394 wrmsrl(MSR_AMD64_LS_CFG, msr);
395 raw_spin_unlock(&st->shared_state->lock);
396 }
397}
398#else
399static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
400{
401 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
402
403 wrmsrl(MSR_AMD64_LS_CFG, msr);
404}
405#endif
406
407static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
408{
409 /*
410 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
411 * so ssbd_tif_to_spec_ctrl() just works.
412 */
413 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
414}
415
416/*
417 * Update the MSRs managing speculation control, during context switch.
418 *
419 * tifp: Previous task's thread flags
420 * tifn: Next task's thread flags
421 */
422static __always_inline void __speculation_ctrl_update(unsigned long tifp,
423 unsigned long tifn)
424{
425 unsigned long tif_diff = tifp ^ tifn;
426 u64 msr = x86_spec_ctrl_base;
427 bool updmsr = false;
428
429 lockdep_assert_irqs_disabled();
430
431 /*
432 * If TIF_SSBD is different, select the proper mitigation
433 * method. Note that if SSBD mitigation is disabled or permanentely
434 * enabled this branch can't be taken because nothing can set
435 * TIF_SSBD.
436 */
437 if (tif_diff & _TIF_SSBD) {
438 if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) {
439 amd_set_ssb_virt_state(tifn);
440 } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) {
441 amd_set_core_ssb_state(tifn);
442 } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
443 static_cpu_has(X86_FEATURE_AMD_SSBD)) {
444 msr |= ssbd_tif_to_spec_ctrl(tifn);
445 updmsr = true;
446 }
447 }
448
449 /*
450 * Only evaluate TIF_SPEC_IB if conditional STIBP is enabled,
451 * otherwise avoid the MSR write.
452 */
453 if (IS_ENABLED(CONFIG_SMP) &&
454 static_branch_unlikely(&switch_to_cond_stibp)) {
455 updmsr |= !!(tif_diff & _TIF_SPEC_IB);
456 msr |= stibp_tif_to_spec_ctrl(tifn);
457 }
458
459 if (updmsr)
460 wrmsrl(MSR_IA32_SPEC_CTRL, msr);
461}
462
463static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
464{
465 if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) {
466 if (task_spec_ssb_disable(tsk))
467 set_tsk_thread_flag(tsk, TIF_SSBD);
468 else
469 clear_tsk_thread_flag(tsk, TIF_SSBD);
470
471 if (task_spec_ib_disable(tsk))
472 set_tsk_thread_flag(tsk, TIF_SPEC_IB);
473 else
474 clear_tsk_thread_flag(tsk, TIF_SPEC_IB);
475 }
476 /* Return the updated threadinfo flags*/
477 return task_thread_info(tsk)->flags;
478}
479
480void speculation_ctrl_update(unsigned long tif)
481{
482 unsigned long flags;
483
484 /* Forced update. Make sure all relevant TIF flags are different */
485 local_irq_save(flags);
486 __speculation_ctrl_update(~tif, tif);
487 local_irq_restore(flags);
488}
489
490/* Called from seccomp/prctl update */
491void speculation_ctrl_update_current(void)
492{
493 preempt_disable();
494 speculation_ctrl_update(speculation_ctrl_update_tif(current));
495 preempt_enable();
496}
497
498void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p)
499{
500 struct thread_struct *prev, *next;
501 unsigned long tifp, tifn;
502
503 prev = &prev_p->thread;
504 next = &next_p->thread;
505
506 tifn = READ_ONCE(task_thread_info(next_p)->flags);
507 tifp = READ_ONCE(task_thread_info(prev_p)->flags);
508 switch_to_bitmap(prev, next, tifp, tifn);
509
510 propagate_user_return_notify(prev_p, next_p);
511
512 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
513 arch_has_block_step()) {
514 unsigned long debugctl, msk;
515
516 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
517 debugctl &= ~DEBUGCTLMSR_BTF;
518 msk = tifn & _TIF_BLOCKSTEP;
519 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
520 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
521 }
522
523 if ((tifp ^ tifn) & _TIF_NOTSC)
524 cr4_toggle_bits_irqsoff(X86_CR4_TSD);
525
526 if ((tifp ^ tifn) & _TIF_NOCPUID)
527 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
528
529 if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) {
530 __speculation_ctrl_update(tifp, tifn);
531 } else {
532 speculation_ctrl_update_tif(prev_p);
533 tifn = speculation_ctrl_update_tif(next_p);
534
535 /* Enforce MSR update to ensure consistent state */
536 __speculation_ctrl_update(~tifn, tifn);
537 }
538}
539
540/*
541 * Idle related variables and functions
542 */
543unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
544EXPORT_SYMBOL(boot_option_idle_override);
545
546static void (*x86_idle)(void);
547
548#ifndef CONFIG_SMP
549static inline void play_dead(void)
550{
551 BUG();
552}
553#endif
554
555void arch_cpu_idle_enter(void)
556{
557 tsc_verify_tsc_adjust(false);
558 local_touch_nmi();
559}
560
561void arch_cpu_idle_dead(void)
562{
563 play_dead();
564}
565
566/*
567 * Called from the generic idle code.
568 */
569void arch_cpu_idle(void)
570{
571 x86_idle();
572}
573
574/*
575 * We use this if we don't have any better idle routine..
576 */
577void __cpuidle default_idle(void)
578{
579 trace_cpu_idle_rcuidle(1, smp_processor_id());
580 safe_halt();
581 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
582}
583#if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE)
584EXPORT_SYMBOL(default_idle);
585#endif
586
587#ifdef CONFIG_XEN
588bool xen_set_default_idle(void)
589{
590 bool ret = !!x86_idle;
591
592 x86_idle = default_idle;
593
594 return ret;
595}
596#endif
597
598void stop_this_cpu(void *dummy)
599{
600 local_irq_disable();
601 /*
602 * Remove this CPU:
603 */
604 set_cpu_online(smp_processor_id(), false);
605 disable_local_APIC();
606 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
607
608 /*
609 * Use wbinvd on processors that support SME. This provides support
610 * for performing a successful kexec when going from SME inactive
611 * to SME active (or vice-versa). The cache must be cleared so that
612 * if there are entries with the same physical address, both with and
613 * without the encryption bit, they don't race each other when flushed
614 * and potentially end up with the wrong entry being committed to
615 * memory.
616 */
617 if (boot_cpu_has(X86_FEATURE_SME))
618 native_wbinvd();
619 for (;;) {
620 /*
621 * Use native_halt() so that memory contents don't change
622 * (stack usage and variables) after possibly issuing the
623 * native_wbinvd() above.
624 */
625 native_halt();
626 }
627}
628
629/*
630 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
631 * states (local apic timer and TSC stop).
632 */
633static void amd_e400_idle(void)
634{
635 /*
636 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
637 * gets set after static_cpu_has() places have been converted via
638 * alternatives.
639 */
640 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
641 default_idle();
642 return;
643 }
644
645 tick_broadcast_enter();
646
647 default_idle();
648
649 /*
650 * The switch back from broadcast mode needs to be called with
651 * interrupts disabled.
652 */
653 local_irq_disable();
654 tick_broadcast_exit();
655 local_irq_enable();
656}
657
658/*
659 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
660 * We can't rely on cpuidle installing MWAIT, because it will not load
661 * on systems that support only C1 -- so the boot default must be MWAIT.
662 *
663 * Some AMD machines are the opposite, they depend on using HALT.
664 *
665 * So for default C1, which is used during boot until cpuidle loads,
666 * use MWAIT-C1 on Intel HW that has it, else use HALT.
667 */
668static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
669{
670 if (c->x86_vendor != X86_VENDOR_INTEL)
671 return 0;
672
673 if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR))
674 return 0;
675
676 return 1;
677}
678
679/*
680 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
681 * with interrupts enabled and no flags, which is backwards compatible with the
682 * original MWAIT implementation.
683 */
684static __cpuidle void mwait_idle(void)
685{
686 if (!current_set_polling_and_test()) {
687 trace_cpu_idle_rcuidle(1, smp_processor_id());
688 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
689 mb(); /* quirk */
690 clflush((void *)¤t_thread_info()->flags);
691 mb(); /* quirk */
692 }
693
694 __monitor((void *)¤t_thread_info()->flags, 0, 0);
695 if (!need_resched())
696 __sti_mwait(0, 0);
697 else
698 local_irq_enable();
699 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
700 } else {
701 local_irq_enable();
702 }
703 __current_clr_polling();
704}
705
706void select_idle_routine(const struct cpuinfo_x86 *c)
707{
708#ifdef CONFIG_SMP
709 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
710 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
711#endif
712 if (x86_idle || boot_option_idle_override == IDLE_POLL)
713 return;
714
715 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
716 pr_info("using AMD E400 aware idle routine\n");
717 x86_idle = amd_e400_idle;
718 } else if (prefer_mwait_c1_over_halt(c)) {
719 pr_info("using mwait in idle threads\n");
720 x86_idle = mwait_idle;
721 } else
722 x86_idle = default_idle;
723}
724
725void amd_e400_c1e_apic_setup(void)
726{
727 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
728 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
729 local_irq_disable();
730 tick_broadcast_force();
731 local_irq_enable();
732 }
733}
734
735void __init arch_post_acpi_subsys_init(void)
736{
737 u32 lo, hi;
738
739 if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
740 return;
741
742 /*
743 * AMD E400 detection needs to happen after ACPI has been enabled. If
744 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
745 * MSR_K8_INT_PENDING_MSG.
746 */
747 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
748 if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
749 return;
750
751 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
752
753 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
754 mark_tsc_unstable("TSC halt in AMD C1E");
755 pr_info("System has AMD C1E enabled\n");
756}
757
758static int __init idle_setup(char *str)
759{
760 if (!str)
761 return -EINVAL;
762
763 if (!strcmp(str, "poll")) {
764 pr_info("using polling idle threads\n");
765 boot_option_idle_override = IDLE_POLL;
766 cpu_idle_poll_ctrl(true);
767 } else if (!strcmp(str, "halt")) {
768 /*
769 * When the boot option of idle=halt is added, halt is
770 * forced to be used for CPU idle. In such case CPU C2/C3
771 * won't be used again.
772 * To continue to load the CPU idle driver, don't touch
773 * the boot_option_idle_override.
774 */
775 x86_idle = default_idle;
776 boot_option_idle_override = IDLE_HALT;
777 } else if (!strcmp(str, "nomwait")) {
778 /*
779 * If the boot option of "idle=nomwait" is added,
780 * it means that mwait will be disabled for CPU C2/C3
781 * states. In such case it won't touch the variable
782 * of boot_option_idle_override.
783 */
784 boot_option_idle_override = IDLE_NOMWAIT;
785 } else
786 return -1;
787
788 return 0;
789}
790early_param("idle", idle_setup);
791
792unsigned long arch_align_stack(unsigned long sp)
793{
794 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
795 sp -= get_random_int() % 8192;
796 return sp & ~0xf;
797}
798
799unsigned long arch_randomize_brk(struct mm_struct *mm)
800{
801 return randomize_page(mm->brk, 0x02000000);
802}
803
804/*
805 * Called from fs/proc with a reference on @p to find the function
806 * which called into schedule(). This needs to be done carefully
807 * because the task might wake up and we might look at a stack
808 * changing under us.
809 */
810unsigned long get_wchan(struct task_struct *p)
811{
812 unsigned long start, bottom, top, sp, fp, ip, ret = 0;
813 int count = 0;
814
815 if (p == current || p->state == TASK_RUNNING)
816 return 0;
817
818 if (!try_get_task_stack(p))
819 return 0;
820
821 start = (unsigned long)task_stack_page(p);
822 if (!start)
823 goto out;
824
825 /*
826 * Layout of the stack page:
827 *
828 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
829 * PADDING
830 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
831 * stack
832 * ----------- bottom = start
833 *
834 * The tasks stack pointer points at the location where the
835 * framepointer is stored. The data on the stack is:
836 * ... IP FP ... IP FP
837 *
838 * We need to read FP and IP, so we need to adjust the upper
839 * bound by another unsigned long.
840 */
841 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
842 top -= 2 * sizeof(unsigned long);
843 bottom = start;
844
845 sp = READ_ONCE(p->thread.sp);
846 if (sp < bottom || sp > top)
847 goto out;
848
849 fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
850 do {
851 if (fp < bottom || fp > top)
852 goto out;
853 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
854 if (!in_sched_functions(ip)) {
855 ret = ip;
856 goto out;
857 }
858 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
859 } while (count++ < 16 && p->state != TASK_RUNNING);
860
861out:
862 put_task_stack(p);
863 return ret;
864}
865
866long do_arch_prctl_common(struct task_struct *task, int option,
867 unsigned long cpuid_enabled)
868{
869 switch (option) {
870 case ARCH_GET_CPUID:
871 return get_cpuid_mode();
872 case ARCH_SET_CPUID:
873 return set_cpuid_mode(task, cpuid_enabled);
874 }
875
876 return -EINVAL;
877}
1// SPDX-License-Identifier: GPL-2.0
2#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3
4#include <linux/errno.h>
5#include <linux/kernel.h>
6#include <linux/mm.h>
7#include <linux/smp.h>
8#include <linux/cpu.h>
9#include <linux/prctl.h>
10#include <linux/slab.h>
11#include <linux/sched.h>
12#include <linux/sched/idle.h>
13#include <linux/sched/debug.h>
14#include <linux/sched/task.h>
15#include <linux/sched/task_stack.h>
16#include <linux/init.h>
17#include <linux/export.h>
18#include <linux/pm.h>
19#include <linux/tick.h>
20#include <linux/random.h>
21#include <linux/user-return-notifier.h>
22#include <linux/dmi.h>
23#include <linux/utsname.h>
24#include <linux/stackprotector.h>
25#include <linux/cpuidle.h>
26#include <linux/acpi.h>
27#include <linux/elf-randomize.h>
28#include <linux/static_call.h>
29#include <trace/events/power.h>
30#include <linux/hw_breakpoint.h>
31#include <linux/entry-common.h>
32#include <asm/cpu.h>
33#include <asm/apic.h>
34#include <linux/uaccess.h>
35#include <asm/mwait.h>
36#include <asm/fpu/api.h>
37#include <asm/fpu/sched.h>
38#include <asm/fpu/xstate.h>
39#include <asm/debugreg.h>
40#include <asm/nmi.h>
41#include <asm/tlbflush.h>
42#include <asm/mce.h>
43#include <asm/vm86.h>
44#include <asm/switch_to.h>
45#include <asm/desc.h>
46#include <asm/prctl.h>
47#include <asm/spec-ctrl.h>
48#include <asm/io_bitmap.h>
49#include <asm/proto.h>
50#include <asm/frame.h>
51#include <asm/unwind.h>
52#include <asm/tdx.h>
53#include <asm/mmu_context.h>
54#include <asm/shstk.h>
55
56#include "process.h"
57
58/*
59 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
60 * no more per-task TSS's. The TSS size is kept cacheline-aligned
61 * so they are allowed to end up in the .data..cacheline_aligned
62 * section. Since TSS's are completely CPU-local, we want them
63 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
64 */
65__visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
66 .x86_tss = {
67 /*
68 * .sp0 is only used when entering ring 0 from a lower
69 * privilege level. Since the init task never runs anything
70 * but ring 0 code, there is no need for a valid value here.
71 * Poison it.
72 */
73 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
74
75#ifdef CONFIG_X86_32
76 .sp1 = TOP_OF_INIT_STACK,
77
78 .ss0 = __KERNEL_DS,
79 .ss1 = __KERNEL_CS,
80#endif
81 .io_bitmap_base = IO_BITMAP_OFFSET_INVALID,
82 },
83};
84EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
85
86DEFINE_PER_CPU(bool, __tss_limit_invalid);
87EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
88
89/*
90 * this gets called so that we can store lazy state into memory and copy the
91 * current task into the new thread.
92 */
93int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
94{
95 memcpy(dst, src, arch_task_struct_size);
96#ifdef CONFIG_VM86
97 dst->thread.vm86 = NULL;
98#endif
99 /* Drop the copied pointer to current's fpstate */
100 dst->thread.fpu.fpstate = NULL;
101
102 return 0;
103}
104
105#ifdef CONFIG_X86_64
106void arch_release_task_struct(struct task_struct *tsk)
107{
108 if (fpu_state_size_dynamic())
109 fpstate_free(&tsk->thread.fpu);
110}
111#endif
112
113/*
114 * Free thread data structures etc..
115 */
116void exit_thread(struct task_struct *tsk)
117{
118 struct thread_struct *t = &tsk->thread;
119 struct fpu *fpu = &t->fpu;
120
121 if (test_thread_flag(TIF_IO_BITMAP))
122 io_bitmap_exit(tsk);
123
124 free_vm86(t);
125
126 shstk_free(tsk);
127 fpu__drop(fpu);
128}
129
130static int set_new_tls(struct task_struct *p, unsigned long tls)
131{
132 struct user_desc __user *utls = (struct user_desc __user *)tls;
133
134 if (in_ia32_syscall())
135 return do_set_thread_area(p, -1, utls, 0);
136 else
137 return do_set_thread_area_64(p, ARCH_SET_FS, tls);
138}
139
140__visible void ret_from_fork(struct task_struct *prev, struct pt_regs *regs,
141 int (*fn)(void *), void *fn_arg)
142{
143 schedule_tail(prev);
144
145 /* Is this a kernel thread? */
146 if (unlikely(fn)) {
147 fn(fn_arg);
148 /*
149 * A kernel thread is allowed to return here after successfully
150 * calling kernel_execve(). Exit to userspace to complete the
151 * execve() syscall.
152 */
153 regs->ax = 0;
154 }
155
156 syscall_exit_to_user_mode(regs);
157}
158
159int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
160{
161 unsigned long clone_flags = args->flags;
162 unsigned long sp = args->stack;
163 unsigned long tls = args->tls;
164 struct inactive_task_frame *frame;
165 struct fork_frame *fork_frame;
166 struct pt_regs *childregs;
167 unsigned long new_ssp;
168 int ret = 0;
169
170 childregs = task_pt_regs(p);
171 fork_frame = container_of(childregs, struct fork_frame, regs);
172 frame = &fork_frame->frame;
173
174 frame->bp = encode_frame_pointer(childregs);
175 frame->ret_addr = (unsigned long) ret_from_fork_asm;
176 p->thread.sp = (unsigned long) fork_frame;
177 p->thread.io_bitmap = NULL;
178 p->thread.iopl_warn = 0;
179 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
180
181#ifdef CONFIG_X86_64
182 current_save_fsgs();
183 p->thread.fsindex = current->thread.fsindex;
184 p->thread.fsbase = current->thread.fsbase;
185 p->thread.gsindex = current->thread.gsindex;
186 p->thread.gsbase = current->thread.gsbase;
187
188 savesegment(es, p->thread.es);
189 savesegment(ds, p->thread.ds);
190
191 if (p->mm && (clone_flags & (CLONE_VM | CLONE_VFORK)) == CLONE_VM)
192 set_bit(MM_CONTEXT_LOCK_LAM, &p->mm->context.flags);
193#else
194 p->thread.sp0 = (unsigned long) (childregs + 1);
195 savesegment(gs, p->thread.gs);
196 /*
197 * Clear all status flags including IF and set fixed bit. 64bit
198 * does not have this initialization as the frame does not contain
199 * flags. The flags consistency (especially vs. AC) is there
200 * ensured via objtool, which lacks 32bit support.
201 */
202 frame->flags = X86_EFLAGS_FIXED;
203#endif
204
205 /*
206 * Allocate a new shadow stack for thread if needed. If shadow stack,
207 * is disabled, new_ssp will remain 0, and fpu_clone() will know not to
208 * update it.
209 */
210 new_ssp = shstk_alloc_thread_stack(p, clone_flags, args->stack_size);
211 if (IS_ERR_VALUE(new_ssp))
212 return PTR_ERR((void *)new_ssp);
213
214 fpu_clone(p, clone_flags, args->fn, new_ssp);
215
216 /* Kernel thread ? */
217 if (unlikely(p->flags & PF_KTHREAD)) {
218 p->thread.pkru = pkru_get_init_value();
219 memset(childregs, 0, sizeof(struct pt_regs));
220 kthread_frame_init(frame, args->fn, args->fn_arg);
221 return 0;
222 }
223
224 /*
225 * Clone current's PKRU value from hardware. tsk->thread.pkru
226 * is only valid when scheduled out.
227 */
228 p->thread.pkru = read_pkru();
229
230 frame->bx = 0;
231 *childregs = *current_pt_regs();
232 childregs->ax = 0;
233 if (sp)
234 childregs->sp = sp;
235
236 if (unlikely(args->fn)) {
237 /*
238 * A user space thread, but it doesn't return to
239 * ret_after_fork().
240 *
241 * In order to indicate that to tools like gdb,
242 * we reset the stack and instruction pointers.
243 *
244 * It does the same kernel frame setup to return to a kernel
245 * function that a kernel thread does.
246 */
247 childregs->sp = 0;
248 childregs->ip = 0;
249 kthread_frame_init(frame, args->fn, args->fn_arg);
250 return 0;
251 }
252
253 /* Set a new TLS for the child thread? */
254 if (clone_flags & CLONE_SETTLS)
255 ret = set_new_tls(p, tls);
256
257 if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP)))
258 io_bitmap_share(p);
259
260 return ret;
261}
262
263static void pkru_flush_thread(void)
264{
265 /*
266 * If PKRU is enabled the default PKRU value has to be loaded into
267 * the hardware right here (similar to context switch).
268 */
269 pkru_write_default();
270}
271
272void flush_thread(void)
273{
274 struct task_struct *tsk = current;
275
276 flush_ptrace_hw_breakpoint(tsk);
277 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
278
279 fpu_flush_thread();
280 pkru_flush_thread();
281}
282
283void disable_TSC(void)
284{
285 preempt_disable();
286 if (!test_and_set_thread_flag(TIF_NOTSC))
287 /*
288 * Must flip the CPU state synchronously with
289 * TIF_NOTSC in the current running context.
290 */
291 cr4_set_bits(X86_CR4_TSD);
292 preempt_enable();
293}
294
295static void enable_TSC(void)
296{
297 preempt_disable();
298 if (test_and_clear_thread_flag(TIF_NOTSC))
299 /*
300 * Must flip the CPU state synchronously with
301 * TIF_NOTSC in the current running context.
302 */
303 cr4_clear_bits(X86_CR4_TSD);
304 preempt_enable();
305}
306
307int get_tsc_mode(unsigned long adr)
308{
309 unsigned int val;
310
311 if (test_thread_flag(TIF_NOTSC))
312 val = PR_TSC_SIGSEGV;
313 else
314 val = PR_TSC_ENABLE;
315
316 return put_user(val, (unsigned int __user *)adr);
317}
318
319int set_tsc_mode(unsigned int val)
320{
321 if (val == PR_TSC_SIGSEGV)
322 disable_TSC();
323 else if (val == PR_TSC_ENABLE)
324 enable_TSC();
325 else
326 return -EINVAL;
327
328 return 0;
329}
330
331DEFINE_PER_CPU(u64, msr_misc_features_shadow);
332
333static void set_cpuid_faulting(bool on)
334{
335 u64 msrval;
336
337 msrval = this_cpu_read(msr_misc_features_shadow);
338 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
339 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
340 this_cpu_write(msr_misc_features_shadow, msrval);
341 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
342}
343
344static void disable_cpuid(void)
345{
346 preempt_disable();
347 if (!test_and_set_thread_flag(TIF_NOCPUID)) {
348 /*
349 * Must flip the CPU state synchronously with
350 * TIF_NOCPUID in the current running context.
351 */
352 set_cpuid_faulting(true);
353 }
354 preempt_enable();
355}
356
357static void enable_cpuid(void)
358{
359 preempt_disable();
360 if (test_and_clear_thread_flag(TIF_NOCPUID)) {
361 /*
362 * Must flip the CPU state synchronously with
363 * TIF_NOCPUID in the current running context.
364 */
365 set_cpuid_faulting(false);
366 }
367 preempt_enable();
368}
369
370static int get_cpuid_mode(void)
371{
372 return !test_thread_flag(TIF_NOCPUID);
373}
374
375static int set_cpuid_mode(unsigned long cpuid_enabled)
376{
377 if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT))
378 return -ENODEV;
379
380 if (cpuid_enabled)
381 enable_cpuid();
382 else
383 disable_cpuid();
384
385 return 0;
386}
387
388/*
389 * Called immediately after a successful exec.
390 */
391void arch_setup_new_exec(void)
392{
393 /* If cpuid was previously disabled for this task, re-enable it. */
394 if (test_thread_flag(TIF_NOCPUID))
395 enable_cpuid();
396
397 /*
398 * Don't inherit TIF_SSBD across exec boundary when
399 * PR_SPEC_DISABLE_NOEXEC is used.
400 */
401 if (test_thread_flag(TIF_SSBD) &&
402 task_spec_ssb_noexec(current)) {
403 clear_thread_flag(TIF_SSBD);
404 task_clear_spec_ssb_disable(current);
405 task_clear_spec_ssb_noexec(current);
406 speculation_ctrl_update(read_thread_flags());
407 }
408
409 mm_reset_untag_mask(current->mm);
410}
411
412#ifdef CONFIG_X86_IOPL_IOPERM
413static inline void switch_to_bitmap(unsigned long tifp)
414{
415 /*
416 * Invalidate I/O bitmap if the previous task used it. This prevents
417 * any possible leakage of an active I/O bitmap.
418 *
419 * If the next task has an I/O bitmap it will handle it on exit to
420 * user mode.
421 */
422 if (tifp & _TIF_IO_BITMAP)
423 tss_invalidate_io_bitmap();
424}
425
426static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm)
427{
428 /*
429 * Copy at least the byte range of the incoming tasks bitmap which
430 * covers the permitted I/O ports.
431 *
432 * If the previous task which used an I/O bitmap had more bits
433 * permitted, then the copy needs to cover those as well so they
434 * get turned off.
435 */
436 memcpy(tss->io_bitmap.bitmap, iobm->bitmap,
437 max(tss->io_bitmap.prev_max, iobm->max));
438
439 /*
440 * Store the new max and the sequence number of this bitmap
441 * and a pointer to the bitmap itself.
442 */
443 tss->io_bitmap.prev_max = iobm->max;
444 tss->io_bitmap.prev_sequence = iobm->sequence;
445}
446
447/**
448 * native_tss_update_io_bitmap - Update I/O bitmap before exiting to user mode
449 */
450void native_tss_update_io_bitmap(void)
451{
452 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
453 struct thread_struct *t = ¤t->thread;
454 u16 *base = &tss->x86_tss.io_bitmap_base;
455
456 if (!test_thread_flag(TIF_IO_BITMAP)) {
457 native_tss_invalidate_io_bitmap();
458 return;
459 }
460
461 if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) {
462 *base = IO_BITMAP_OFFSET_VALID_ALL;
463 } else {
464 struct io_bitmap *iobm = t->io_bitmap;
465
466 /*
467 * Only copy bitmap data when the sequence number differs. The
468 * update time is accounted to the incoming task.
469 */
470 if (tss->io_bitmap.prev_sequence != iobm->sequence)
471 tss_copy_io_bitmap(tss, iobm);
472
473 /* Enable the bitmap */
474 *base = IO_BITMAP_OFFSET_VALID_MAP;
475 }
476
477 /*
478 * Make sure that the TSS limit is covering the IO bitmap. It might have
479 * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O
480 * access from user space to trigger a #GP because the bitmap is outside
481 * the TSS limit.
482 */
483 refresh_tss_limit();
484}
485#else /* CONFIG_X86_IOPL_IOPERM */
486static inline void switch_to_bitmap(unsigned long tifp) { }
487#endif
488
489#ifdef CONFIG_SMP
490
491struct ssb_state {
492 struct ssb_state *shared_state;
493 raw_spinlock_t lock;
494 unsigned int disable_state;
495 unsigned long local_state;
496};
497
498#define LSTATE_SSB 0
499
500static DEFINE_PER_CPU(struct ssb_state, ssb_state);
501
502void speculative_store_bypass_ht_init(void)
503{
504 struct ssb_state *st = this_cpu_ptr(&ssb_state);
505 unsigned int this_cpu = smp_processor_id();
506 unsigned int cpu;
507
508 st->local_state = 0;
509
510 /*
511 * Shared state setup happens once on the first bringup
512 * of the CPU. It's not destroyed on CPU hotunplug.
513 */
514 if (st->shared_state)
515 return;
516
517 raw_spin_lock_init(&st->lock);
518
519 /*
520 * Go over HT siblings and check whether one of them has set up the
521 * shared state pointer already.
522 */
523 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
524 if (cpu == this_cpu)
525 continue;
526
527 if (!per_cpu(ssb_state, cpu).shared_state)
528 continue;
529
530 /* Link it to the state of the sibling: */
531 st->shared_state = per_cpu(ssb_state, cpu).shared_state;
532 return;
533 }
534
535 /*
536 * First HT sibling to come up on the core. Link shared state of
537 * the first HT sibling to itself. The siblings on the same core
538 * which come up later will see the shared state pointer and link
539 * themselves to the state of this CPU.
540 */
541 st->shared_state = st;
542}
543
544/*
545 * Logic is: First HT sibling enables SSBD for both siblings in the core
546 * and last sibling to disable it, disables it for the whole core. This how
547 * MSR_SPEC_CTRL works in "hardware":
548 *
549 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
550 */
551static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
552{
553 struct ssb_state *st = this_cpu_ptr(&ssb_state);
554 u64 msr = x86_amd_ls_cfg_base;
555
556 if (!static_cpu_has(X86_FEATURE_ZEN)) {
557 msr |= ssbd_tif_to_amd_ls_cfg(tifn);
558 wrmsrl(MSR_AMD64_LS_CFG, msr);
559 return;
560 }
561
562 if (tifn & _TIF_SSBD) {
563 /*
564 * Since this can race with prctl(), block reentry on the
565 * same CPU.
566 */
567 if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
568 return;
569
570 msr |= x86_amd_ls_cfg_ssbd_mask;
571
572 raw_spin_lock(&st->shared_state->lock);
573 /* First sibling enables SSBD: */
574 if (!st->shared_state->disable_state)
575 wrmsrl(MSR_AMD64_LS_CFG, msr);
576 st->shared_state->disable_state++;
577 raw_spin_unlock(&st->shared_state->lock);
578 } else {
579 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
580 return;
581
582 raw_spin_lock(&st->shared_state->lock);
583 st->shared_state->disable_state--;
584 if (!st->shared_state->disable_state)
585 wrmsrl(MSR_AMD64_LS_CFG, msr);
586 raw_spin_unlock(&st->shared_state->lock);
587 }
588}
589#else
590static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
591{
592 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
593
594 wrmsrl(MSR_AMD64_LS_CFG, msr);
595}
596#endif
597
598static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
599{
600 /*
601 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
602 * so ssbd_tif_to_spec_ctrl() just works.
603 */
604 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
605}
606
607/*
608 * Update the MSRs managing speculation control, during context switch.
609 *
610 * tifp: Previous task's thread flags
611 * tifn: Next task's thread flags
612 */
613static __always_inline void __speculation_ctrl_update(unsigned long tifp,
614 unsigned long tifn)
615{
616 unsigned long tif_diff = tifp ^ tifn;
617 u64 msr = x86_spec_ctrl_base;
618 bool updmsr = false;
619
620 lockdep_assert_irqs_disabled();
621
622 /* Handle change of TIF_SSBD depending on the mitigation method. */
623 if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) {
624 if (tif_diff & _TIF_SSBD)
625 amd_set_ssb_virt_state(tifn);
626 } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) {
627 if (tif_diff & _TIF_SSBD)
628 amd_set_core_ssb_state(tifn);
629 } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
630 static_cpu_has(X86_FEATURE_AMD_SSBD)) {
631 updmsr |= !!(tif_diff & _TIF_SSBD);
632 msr |= ssbd_tif_to_spec_ctrl(tifn);
633 }
634
635 /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */
636 if (IS_ENABLED(CONFIG_SMP) &&
637 static_branch_unlikely(&switch_to_cond_stibp)) {
638 updmsr |= !!(tif_diff & _TIF_SPEC_IB);
639 msr |= stibp_tif_to_spec_ctrl(tifn);
640 }
641
642 if (updmsr)
643 update_spec_ctrl_cond(msr);
644}
645
646static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
647{
648 if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) {
649 if (task_spec_ssb_disable(tsk))
650 set_tsk_thread_flag(tsk, TIF_SSBD);
651 else
652 clear_tsk_thread_flag(tsk, TIF_SSBD);
653
654 if (task_spec_ib_disable(tsk))
655 set_tsk_thread_flag(tsk, TIF_SPEC_IB);
656 else
657 clear_tsk_thread_flag(tsk, TIF_SPEC_IB);
658 }
659 /* Return the updated threadinfo flags*/
660 return read_task_thread_flags(tsk);
661}
662
663void speculation_ctrl_update(unsigned long tif)
664{
665 unsigned long flags;
666
667 /* Forced update. Make sure all relevant TIF flags are different */
668 local_irq_save(flags);
669 __speculation_ctrl_update(~tif, tif);
670 local_irq_restore(flags);
671}
672
673/* Called from seccomp/prctl update */
674void speculation_ctrl_update_current(void)
675{
676 preempt_disable();
677 speculation_ctrl_update(speculation_ctrl_update_tif(current));
678 preempt_enable();
679}
680
681static inline void cr4_toggle_bits_irqsoff(unsigned long mask)
682{
683 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
684
685 newval = cr4 ^ mask;
686 if (newval != cr4) {
687 this_cpu_write(cpu_tlbstate.cr4, newval);
688 __write_cr4(newval);
689 }
690}
691
692void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p)
693{
694 unsigned long tifp, tifn;
695
696 tifn = read_task_thread_flags(next_p);
697 tifp = read_task_thread_flags(prev_p);
698
699 switch_to_bitmap(tifp);
700
701 propagate_user_return_notify(prev_p, next_p);
702
703 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
704 arch_has_block_step()) {
705 unsigned long debugctl, msk;
706
707 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
708 debugctl &= ~DEBUGCTLMSR_BTF;
709 msk = tifn & _TIF_BLOCKSTEP;
710 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
711 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
712 }
713
714 if ((tifp ^ tifn) & _TIF_NOTSC)
715 cr4_toggle_bits_irqsoff(X86_CR4_TSD);
716
717 if ((tifp ^ tifn) & _TIF_NOCPUID)
718 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
719
720 if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) {
721 __speculation_ctrl_update(tifp, tifn);
722 } else {
723 speculation_ctrl_update_tif(prev_p);
724 tifn = speculation_ctrl_update_tif(next_p);
725
726 /* Enforce MSR update to ensure consistent state */
727 __speculation_ctrl_update(~tifn, tifn);
728 }
729}
730
731/*
732 * Idle related variables and functions
733 */
734unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
735EXPORT_SYMBOL(boot_option_idle_override);
736
737/*
738 * We use this if we don't have any better idle routine..
739 */
740void __cpuidle default_idle(void)
741{
742 raw_safe_halt();
743 raw_local_irq_disable();
744}
745#if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE)
746EXPORT_SYMBOL(default_idle);
747#endif
748
749DEFINE_STATIC_CALL_NULL(x86_idle, default_idle);
750
751static bool x86_idle_set(void)
752{
753 return !!static_call_query(x86_idle);
754}
755
756#ifndef CONFIG_SMP
757static inline void __noreturn play_dead(void)
758{
759 BUG();
760}
761#endif
762
763void arch_cpu_idle_enter(void)
764{
765 tsc_verify_tsc_adjust(false);
766 local_touch_nmi();
767}
768
769void __noreturn arch_cpu_idle_dead(void)
770{
771 play_dead();
772}
773
774/*
775 * Called from the generic idle code.
776 */
777void __cpuidle arch_cpu_idle(void)
778{
779 static_call(x86_idle)();
780}
781EXPORT_SYMBOL_GPL(arch_cpu_idle);
782
783#ifdef CONFIG_XEN
784bool xen_set_default_idle(void)
785{
786 bool ret = x86_idle_set();
787
788 static_call_update(x86_idle, default_idle);
789
790 return ret;
791}
792#endif
793
794struct cpumask cpus_stop_mask;
795
796void __noreturn stop_this_cpu(void *dummy)
797{
798 struct cpuinfo_x86 *c = this_cpu_ptr(&cpu_info);
799 unsigned int cpu = smp_processor_id();
800
801 local_irq_disable();
802
803 /*
804 * Remove this CPU from the online mask and disable it
805 * unconditionally. This might be redundant in case that the reboot
806 * vector was handled late and stop_other_cpus() sent an NMI.
807 *
808 * According to SDM and APM NMIs can be accepted even after soft
809 * disabling the local APIC.
810 */
811 set_cpu_online(cpu, false);
812 disable_local_APIC();
813 mcheck_cpu_clear(c);
814
815 /*
816 * Use wbinvd on processors that support SME. This provides support
817 * for performing a successful kexec when going from SME inactive
818 * to SME active (or vice-versa). The cache must be cleared so that
819 * if there are entries with the same physical address, both with and
820 * without the encryption bit, they don't race each other when flushed
821 * and potentially end up with the wrong entry being committed to
822 * memory.
823 *
824 * Test the CPUID bit directly because the machine might've cleared
825 * X86_FEATURE_SME due to cmdline options.
826 */
827 if (c->extended_cpuid_level >= 0x8000001f && (cpuid_eax(0x8000001f) & BIT(0)))
828 native_wbinvd();
829
830 /*
831 * This brings a cache line back and dirties it, but
832 * native_stop_other_cpus() will overwrite cpus_stop_mask after it
833 * observed that all CPUs reported stop. This write will invalidate
834 * the related cache line on this CPU.
835 */
836 cpumask_clear_cpu(cpu, &cpus_stop_mask);
837
838#ifdef CONFIG_SMP
839 if (smp_ops.stop_this_cpu) {
840 smp_ops.stop_this_cpu();
841 BUG();
842 }
843#endif
844
845 for (;;) {
846 /*
847 * Use native_halt() so that memory contents don't change
848 * (stack usage and variables) after possibly issuing the
849 * native_wbinvd() above.
850 */
851 native_halt();
852 }
853}
854
855/*
856 * Prefer MWAIT over HALT if MWAIT is supported, MWAIT_CPUID leaf
857 * exists and whenever MONITOR/MWAIT extensions are present there is at
858 * least one C1 substate.
859 *
860 * Do not prefer MWAIT if MONITOR instruction has a bug or idle=nomwait
861 * is passed to kernel commandline parameter.
862 */
863static __init bool prefer_mwait_c1_over_halt(void)
864{
865 const struct cpuinfo_x86 *c = &boot_cpu_data;
866 u32 eax, ebx, ecx, edx;
867
868 /* If override is enforced on the command line, fall back to HALT. */
869 if (boot_option_idle_override != IDLE_NO_OVERRIDE)
870 return false;
871
872 /* MWAIT is not supported on this platform. Fallback to HALT */
873 if (!cpu_has(c, X86_FEATURE_MWAIT))
874 return false;
875
876 /* Monitor has a bug or APIC stops in C1E. Fallback to HALT */
877 if (boot_cpu_has_bug(X86_BUG_MONITOR) || boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E))
878 return false;
879
880 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
881
882 /*
883 * If MWAIT extensions are not available, it is safe to use MWAIT
884 * with EAX=0, ECX=0.
885 */
886 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED))
887 return true;
888
889 /*
890 * If MWAIT extensions are available, there should be at least one
891 * MWAIT C1 substate present.
892 */
893 return !!(edx & MWAIT_C1_SUBSTATE_MASK);
894}
895
896/*
897 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
898 * with interrupts enabled and no flags, which is backwards compatible with the
899 * original MWAIT implementation.
900 */
901static __cpuidle void mwait_idle(void)
902{
903 if (!current_set_polling_and_test()) {
904 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
905 mb(); /* quirk */
906 clflush((void *)¤t_thread_info()->flags);
907 mb(); /* quirk */
908 }
909
910 __monitor((void *)¤t_thread_info()->flags, 0, 0);
911 if (!need_resched()) {
912 __sti_mwait(0, 0);
913 raw_local_irq_disable();
914 }
915 }
916 __current_clr_polling();
917}
918
919void __init select_idle_routine(void)
920{
921 if (boot_option_idle_override == IDLE_POLL) {
922 if (IS_ENABLED(CONFIG_SMP) && __max_threads_per_core > 1)
923 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
924 return;
925 }
926
927 /* Required to guard against xen_set_default_idle() */
928 if (x86_idle_set())
929 return;
930
931 if (prefer_mwait_c1_over_halt()) {
932 pr_info("using mwait in idle threads\n");
933 static_call_update(x86_idle, mwait_idle);
934 } else if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) {
935 pr_info("using TDX aware idle routine\n");
936 static_call_update(x86_idle, tdx_safe_halt);
937 } else {
938 static_call_update(x86_idle, default_idle);
939 }
940}
941
942void amd_e400_c1e_apic_setup(void)
943{
944 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
945 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
946 local_irq_disable();
947 tick_broadcast_force();
948 local_irq_enable();
949 }
950}
951
952void __init arch_post_acpi_subsys_init(void)
953{
954 u32 lo, hi;
955
956 if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
957 return;
958
959 /*
960 * AMD E400 detection needs to happen after ACPI has been enabled. If
961 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
962 * MSR_K8_INT_PENDING_MSG.
963 */
964 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
965 if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
966 return;
967
968 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
969
970 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
971 mark_tsc_unstable("TSC halt in AMD C1E");
972
973 if (IS_ENABLED(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST_IDLE))
974 static_branch_enable(&arch_needs_tick_broadcast);
975 pr_info("System has AMD C1E erratum E400. Workaround enabled.\n");
976}
977
978static int __init idle_setup(char *str)
979{
980 if (!str)
981 return -EINVAL;
982
983 if (!strcmp(str, "poll")) {
984 pr_info("using polling idle threads\n");
985 boot_option_idle_override = IDLE_POLL;
986 cpu_idle_poll_ctrl(true);
987 } else if (!strcmp(str, "halt")) {
988 /* 'idle=halt' HALT for idle. C-states are disabled. */
989 boot_option_idle_override = IDLE_HALT;
990 } else if (!strcmp(str, "nomwait")) {
991 /* 'idle=nomwait' disables MWAIT for idle */
992 boot_option_idle_override = IDLE_NOMWAIT;
993 } else {
994 return -EINVAL;
995 }
996
997 return 0;
998}
999early_param("idle", idle_setup);
1000
1001unsigned long arch_align_stack(unsigned long sp)
1002{
1003 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1004 sp -= get_random_u32_below(8192);
1005 return sp & ~0xf;
1006}
1007
1008unsigned long arch_randomize_brk(struct mm_struct *mm)
1009{
1010 if (mmap_is_ia32())
1011 return randomize_page(mm->brk, SZ_32M);
1012
1013 return randomize_page(mm->brk, SZ_1G);
1014}
1015
1016/*
1017 * Called from fs/proc with a reference on @p to find the function
1018 * which called into schedule(). This needs to be done carefully
1019 * because the task might wake up and we might look at a stack
1020 * changing under us.
1021 */
1022unsigned long __get_wchan(struct task_struct *p)
1023{
1024 struct unwind_state state;
1025 unsigned long addr = 0;
1026
1027 if (!try_get_task_stack(p))
1028 return 0;
1029
1030 for (unwind_start(&state, p, NULL, NULL); !unwind_done(&state);
1031 unwind_next_frame(&state)) {
1032 addr = unwind_get_return_address(&state);
1033 if (!addr)
1034 break;
1035 if (in_sched_functions(addr))
1036 continue;
1037 break;
1038 }
1039
1040 put_task_stack(p);
1041
1042 return addr;
1043}
1044
1045long do_arch_prctl_common(int option, unsigned long arg2)
1046{
1047 switch (option) {
1048 case ARCH_GET_CPUID:
1049 return get_cpuid_mode();
1050 case ARCH_SET_CPUID:
1051 return set_cpuid_mode(arg2);
1052 case ARCH_GET_XCOMP_SUPP:
1053 case ARCH_GET_XCOMP_PERM:
1054 case ARCH_REQ_XCOMP_PERM:
1055 case ARCH_GET_XCOMP_GUEST_PERM:
1056 case ARCH_REQ_XCOMP_GUEST_PERM:
1057 return fpu_xstate_prctl(option, arg2);
1058 }
1059
1060 return -EINVAL;
1061}