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1// SPDX-License-Identifier: GPL-2.0
2#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3
4#include <linux/errno.h>
5#include <linux/kernel.h>
6#include <linux/mm.h>
7#include <linux/smp.h>
8#include <linux/prctl.h>
9#include <linux/slab.h>
10#include <linux/sched.h>
11#include <linux/sched/idle.h>
12#include <linux/sched/debug.h>
13#include <linux/sched/task.h>
14#include <linux/sched/task_stack.h>
15#include <linux/init.h>
16#include <linux/export.h>
17#include <linux/pm.h>
18#include <linux/tick.h>
19#include <linux/random.h>
20#include <linux/user-return-notifier.h>
21#include <linux/dmi.h>
22#include <linux/utsname.h>
23#include <linux/stackprotector.h>
24#include <linux/cpuidle.h>
25#include <linux/acpi.h>
26#include <linux/elf-randomize.h>
27#include <trace/events/power.h>
28#include <linux/hw_breakpoint.h>
29#include <asm/cpu.h>
30#include <asm/apic.h>
31#include <asm/syscalls.h>
32#include <linux/uaccess.h>
33#include <asm/mwait.h>
34#include <asm/fpu/internal.h>
35#include <asm/debugreg.h>
36#include <asm/nmi.h>
37#include <asm/tlbflush.h>
38#include <asm/mce.h>
39#include <asm/vm86.h>
40#include <asm/switch_to.h>
41#include <asm/desc.h>
42#include <asm/prctl.h>
43#include <asm/spec-ctrl.h>
44#include <asm/proto.h>
45
46#include "process.h"
47
48/*
49 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
50 * no more per-task TSS's. The TSS size is kept cacheline-aligned
51 * so they are allowed to end up in the .data..cacheline_aligned
52 * section. Since TSS's are completely CPU-local, we want them
53 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
54 */
55__visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
56 .x86_tss = {
57 /*
58 * .sp0 is only used when entering ring 0 from a lower
59 * privilege level. Since the init task never runs anything
60 * but ring 0 code, there is no need for a valid value here.
61 * Poison it.
62 */
63 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
64
65 /*
66 * .sp1 is cpu_current_top_of_stack. The init task never
67 * runs user code, but cpu_current_top_of_stack should still
68 * be well defined before the first context switch.
69 */
70 .sp1 = TOP_OF_INIT_STACK,
71
72#ifdef CONFIG_X86_32
73 .ss0 = __KERNEL_DS,
74 .ss1 = __KERNEL_CS,
75 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
76#endif
77 },
78#ifdef CONFIG_X86_32
79 /*
80 * Note that the .io_bitmap member must be extra-big. This is because
81 * the CPU will access an additional byte beyond the end of the IO
82 * permission bitmap. The extra byte must be all 1 bits, and must
83 * be within the limit.
84 */
85 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 },
86#endif
87};
88EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
89
90DEFINE_PER_CPU(bool, __tss_limit_invalid);
91EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
92
93/*
94 * this gets called so that we can store lazy state into memory and copy the
95 * current task into the new thread.
96 */
97int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
98{
99 memcpy(dst, src, arch_task_struct_size);
100#ifdef CONFIG_VM86
101 dst->thread.vm86 = NULL;
102#endif
103
104 return fpu__copy(dst, src);
105}
106
107/*
108 * Free current thread data structures etc..
109 */
110void exit_thread(struct task_struct *tsk)
111{
112 struct thread_struct *t = &tsk->thread;
113 unsigned long *bp = t->io_bitmap_ptr;
114 struct fpu *fpu = &t->fpu;
115
116 if (bp) {
117 struct tss_struct *tss = &per_cpu(cpu_tss_rw, get_cpu());
118
119 t->io_bitmap_ptr = NULL;
120 clear_thread_flag(TIF_IO_BITMAP);
121 /*
122 * Careful, clear this in the TSS too:
123 */
124 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
125 t->io_bitmap_max = 0;
126 put_cpu();
127 kfree(bp);
128 }
129
130 free_vm86(t);
131
132 fpu__drop(fpu);
133}
134
135void flush_thread(void)
136{
137 struct task_struct *tsk = current;
138
139 flush_ptrace_hw_breakpoint(tsk);
140 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
141
142 fpu__clear(&tsk->thread.fpu);
143}
144
145void disable_TSC(void)
146{
147 preempt_disable();
148 if (!test_and_set_thread_flag(TIF_NOTSC))
149 /*
150 * Must flip the CPU state synchronously with
151 * TIF_NOTSC in the current running context.
152 */
153 cr4_set_bits(X86_CR4_TSD);
154 preempt_enable();
155}
156
157static void enable_TSC(void)
158{
159 preempt_disable();
160 if (test_and_clear_thread_flag(TIF_NOTSC))
161 /*
162 * Must flip the CPU state synchronously with
163 * TIF_NOTSC in the current running context.
164 */
165 cr4_clear_bits(X86_CR4_TSD);
166 preempt_enable();
167}
168
169int get_tsc_mode(unsigned long adr)
170{
171 unsigned int val;
172
173 if (test_thread_flag(TIF_NOTSC))
174 val = PR_TSC_SIGSEGV;
175 else
176 val = PR_TSC_ENABLE;
177
178 return put_user(val, (unsigned int __user *)adr);
179}
180
181int set_tsc_mode(unsigned int val)
182{
183 if (val == PR_TSC_SIGSEGV)
184 disable_TSC();
185 else if (val == PR_TSC_ENABLE)
186 enable_TSC();
187 else
188 return -EINVAL;
189
190 return 0;
191}
192
193DEFINE_PER_CPU(u64, msr_misc_features_shadow);
194
195static void set_cpuid_faulting(bool on)
196{
197 u64 msrval;
198
199 msrval = this_cpu_read(msr_misc_features_shadow);
200 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
201 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
202 this_cpu_write(msr_misc_features_shadow, msrval);
203 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
204}
205
206static void disable_cpuid(void)
207{
208 preempt_disable();
209 if (!test_and_set_thread_flag(TIF_NOCPUID)) {
210 /*
211 * Must flip the CPU state synchronously with
212 * TIF_NOCPUID in the current running context.
213 */
214 set_cpuid_faulting(true);
215 }
216 preempt_enable();
217}
218
219static void enable_cpuid(void)
220{
221 preempt_disable();
222 if (test_and_clear_thread_flag(TIF_NOCPUID)) {
223 /*
224 * Must flip the CPU state synchronously with
225 * TIF_NOCPUID in the current running context.
226 */
227 set_cpuid_faulting(false);
228 }
229 preempt_enable();
230}
231
232static int get_cpuid_mode(void)
233{
234 return !test_thread_flag(TIF_NOCPUID);
235}
236
237static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
238{
239 if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT))
240 return -ENODEV;
241
242 if (cpuid_enabled)
243 enable_cpuid();
244 else
245 disable_cpuid();
246
247 return 0;
248}
249
250/*
251 * Called immediately after a successful exec.
252 */
253void arch_setup_new_exec(void)
254{
255 /* If cpuid was previously disabled for this task, re-enable it. */
256 if (test_thread_flag(TIF_NOCPUID))
257 enable_cpuid();
258
259 /*
260 * Don't inherit TIF_SSBD across exec boundary when
261 * PR_SPEC_DISABLE_NOEXEC is used.
262 */
263 if (test_thread_flag(TIF_SSBD) &&
264 task_spec_ssb_noexec(current)) {
265 clear_thread_flag(TIF_SSBD);
266 task_clear_spec_ssb_disable(current);
267 task_clear_spec_ssb_noexec(current);
268 speculation_ctrl_update(task_thread_info(current)->flags);
269 }
270}
271
272static inline void switch_to_bitmap(struct thread_struct *prev,
273 struct thread_struct *next,
274 unsigned long tifp, unsigned long tifn)
275{
276 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
277
278 if (tifn & _TIF_IO_BITMAP) {
279 /*
280 * Copy the relevant range of the IO bitmap.
281 * Normally this is 128 bytes or less:
282 */
283 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
284 max(prev->io_bitmap_max, next->io_bitmap_max));
285 /*
286 * Make sure that the TSS limit is correct for the CPU
287 * to notice the IO bitmap.
288 */
289 refresh_tss_limit();
290 } else if (tifp & _TIF_IO_BITMAP) {
291 /*
292 * Clear any possible leftover bits:
293 */
294 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
295 }
296}
297
298#ifdef CONFIG_SMP
299
300struct ssb_state {
301 struct ssb_state *shared_state;
302 raw_spinlock_t lock;
303 unsigned int disable_state;
304 unsigned long local_state;
305};
306
307#define LSTATE_SSB 0
308
309static DEFINE_PER_CPU(struct ssb_state, ssb_state);
310
311void speculative_store_bypass_ht_init(void)
312{
313 struct ssb_state *st = this_cpu_ptr(&ssb_state);
314 unsigned int this_cpu = smp_processor_id();
315 unsigned int cpu;
316
317 st->local_state = 0;
318
319 /*
320 * Shared state setup happens once on the first bringup
321 * of the CPU. It's not destroyed on CPU hotunplug.
322 */
323 if (st->shared_state)
324 return;
325
326 raw_spin_lock_init(&st->lock);
327
328 /*
329 * Go over HT siblings and check whether one of them has set up the
330 * shared state pointer already.
331 */
332 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
333 if (cpu == this_cpu)
334 continue;
335
336 if (!per_cpu(ssb_state, cpu).shared_state)
337 continue;
338
339 /* Link it to the state of the sibling: */
340 st->shared_state = per_cpu(ssb_state, cpu).shared_state;
341 return;
342 }
343
344 /*
345 * First HT sibling to come up on the core. Link shared state of
346 * the first HT sibling to itself. The siblings on the same core
347 * which come up later will see the shared state pointer and link
348 * themself to the state of this CPU.
349 */
350 st->shared_state = st;
351}
352
353/*
354 * Logic is: First HT sibling enables SSBD for both siblings in the core
355 * and last sibling to disable it, disables it for the whole core. This how
356 * MSR_SPEC_CTRL works in "hardware":
357 *
358 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
359 */
360static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
361{
362 struct ssb_state *st = this_cpu_ptr(&ssb_state);
363 u64 msr = x86_amd_ls_cfg_base;
364
365 if (!static_cpu_has(X86_FEATURE_ZEN)) {
366 msr |= ssbd_tif_to_amd_ls_cfg(tifn);
367 wrmsrl(MSR_AMD64_LS_CFG, msr);
368 return;
369 }
370
371 if (tifn & _TIF_SSBD) {
372 /*
373 * Since this can race with prctl(), block reentry on the
374 * same CPU.
375 */
376 if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
377 return;
378
379 msr |= x86_amd_ls_cfg_ssbd_mask;
380
381 raw_spin_lock(&st->shared_state->lock);
382 /* First sibling enables SSBD: */
383 if (!st->shared_state->disable_state)
384 wrmsrl(MSR_AMD64_LS_CFG, msr);
385 st->shared_state->disable_state++;
386 raw_spin_unlock(&st->shared_state->lock);
387 } else {
388 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
389 return;
390
391 raw_spin_lock(&st->shared_state->lock);
392 st->shared_state->disable_state--;
393 if (!st->shared_state->disable_state)
394 wrmsrl(MSR_AMD64_LS_CFG, msr);
395 raw_spin_unlock(&st->shared_state->lock);
396 }
397}
398#else
399static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
400{
401 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
402
403 wrmsrl(MSR_AMD64_LS_CFG, msr);
404}
405#endif
406
407static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
408{
409 /*
410 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
411 * so ssbd_tif_to_spec_ctrl() just works.
412 */
413 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
414}
415
416/*
417 * Update the MSRs managing speculation control, during context switch.
418 *
419 * tifp: Previous task's thread flags
420 * tifn: Next task's thread flags
421 */
422static __always_inline void __speculation_ctrl_update(unsigned long tifp,
423 unsigned long tifn)
424{
425 unsigned long tif_diff = tifp ^ tifn;
426 u64 msr = x86_spec_ctrl_base;
427 bool updmsr = false;
428
429 lockdep_assert_irqs_disabled();
430
431 /*
432 * If TIF_SSBD is different, select the proper mitigation
433 * method. Note that if SSBD mitigation is disabled or permanentely
434 * enabled this branch can't be taken because nothing can set
435 * TIF_SSBD.
436 */
437 if (tif_diff & _TIF_SSBD) {
438 if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) {
439 amd_set_ssb_virt_state(tifn);
440 } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) {
441 amd_set_core_ssb_state(tifn);
442 } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
443 static_cpu_has(X86_FEATURE_AMD_SSBD)) {
444 msr |= ssbd_tif_to_spec_ctrl(tifn);
445 updmsr = true;
446 }
447 }
448
449 /*
450 * Only evaluate TIF_SPEC_IB if conditional STIBP is enabled,
451 * otherwise avoid the MSR write.
452 */
453 if (IS_ENABLED(CONFIG_SMP) &&
454 static_branch_unlikely(&switch_to_cond_stibp)) {
455 updmsr |= !!(tif_diff & _TIF_SPEC_IB);
456 msr |= stibp_tif_to_spec_ctrl(tifn);
457 }
458
459 if (updmsr)
460 wrmsrl(MSR_IA32_SPEC_CTRL, msr);
461}
462
463static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
464{
465 if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) {
466 if (task_spec_ssb_disable(tsk))
467 set_tsk_thread_flag(tsk, TIF_SSBD);
468 else
469 clear_tsk_thread_flag(tsk, TIF_SSBD);
470
471 if (task_spec_ib_disable(tsk))
472 set_tsk_thread_flag(tsk, TIF_SPEC_IB);
473 else
474 clear_tsk_thread_flag(tsk, TIF_SPEC_IB);
475 }
476 /* Return the updated threadinfo flags*/
477 return task_thread_info(tsk)->flags;
478}
479
480void speculation_ctrl_update(unsigned long tif)
481{
482 unsigned long flags;
483
484 /* Forced update. Make sure all relevant TIF flags are different */
485 local_irq_save(flags);
486 __speculation_ctrl_update(~tif, tif);
487 local_irq_restore(flags);
488}
489
490/* Called from seccomp/prctl update */
491void speculation_ctrl_update_current(void)
492{
493 preempt_disable();
494 speculation_ctrl_update(speculation_ctrl_update_tif(current));
495 preempt_enable();
496}
497
498void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p)
499{
500 struct thread_struct *prev, *next;
501 unsigned long tifp, tifn;
502
503 prev = &prev_p->thread;
504 next = &next_p->thread;
505
506 tifn = READ_ONCE(task_thread_info(next_p)->flags);
507 tifp = READ_ONCE(task_thread_info(prev_p)->flags);
508 switch_to_bitmap(prev, next, tifp, tifn);
509
510 propagate_user_return_notify(prev_p, next_p);
511
512 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
513 arch_has_block_step()) {
514 unsigned long debugctl, msk;
515
516 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
517 debugctl &= ~DEBUGCTLMSR_BTF;
518 msk = tifn & _TIF_BLOCKSTEP;
519 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
520 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
521 }
522
523 if ((tifp ^ tifn) & _TIF_NOTSC)
524 cr4_toggle_bits_irqsoff(X86_CR4_TSD);
525
526 if ((tifp ^ tifn) & _TIF_NOCPUID)
527 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
528
529 if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) {
530 __speculation_ctrl_update(tifp, tifn);
531 } else {
532 speculation_ctrl_update_tif(prev_p);
533 tifn = speculation_ctrl_update_tif(next_p);
534
535 /* Enforce MSR update to ensure consistent state */
536 __speculation_ctrl_update(~tifn, tifn);
537 }
538}
539
540/*
541 * Idle related variables and functions
542 */
543unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
544EXPORT_SYMBOL(boot_option_idle_override);
545
546static void (*x86_idle)(void);
547
548#ifndef CONFIG_SMP
549static inline void play_dead(void)
550{
551 BUG();
552}
553#endif
554
555void arch_cpu_idle_enter(void)
556{
557 tsc_verify_tsc_adjust(false);
558 local_touch_nmi();
559}
560
561void arch_cpu_idle_dead(void)
562{
563 play_dead();
564}
565
566/*
567 * Called from the generic idle code.
568 */
569void arch_cpu_idle(void)
570{
571 x86_idle();
572}
573
574/*
575 * We use this if we don't have any better idle routine..
576 */
577void __cpuidle default_idle(void)
578{
579 trace_cpu_idle_rcuidle(1, smp_processor_id());
580 safe_halt();
581 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
582}
583#if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE)
584EXPORT_SYMBOL(default_idle);
585#endif
586
587#ifdef CONFIG_XEN
588bool xen_set_default_idle(void)
589{
590 bool ret = !!x86_idle;
591
592 x86_idle = default_idle;
593
594 return ret;
595}
596#endif
597
598void stop_this_cpu(void *dummy)
599{
600 local_irq_disable();
601 /*
602 * Remove this CPU:
603 */
604 set_cpu_online(smp_processor_id(), false);
605 disable_local_APIC();
606 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
607
608 /*
609 * Use wbinvd on processors that support SME. This provides support
610 * for performing a successful kexec when going from SME inactive
611 * to SME active (or vice-versa). The cache must be cleared so that
612 * if there are entries with the same physical address, both with and
613 * without the encryption bit, they don't race each other when flushed
614 * and potentially end up with the wrong entry being committed to
615 * memory.
616 */
617 if (boot_cpu_has(X86_FEATURE_SME))
618 native_wbinvd();
619 for (;;) {
620 /*
621 * Use native_halt() so that memory contents don't change
622 * (stack usage and variables) after possibly issuing the
623 * native_wbinvd() above.
624 */
625 native_halt();
626 }
627}
628
629/*
630 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
631 * states (local apic timer and TSC stop).
632 */
633static void amd_e400_idle(void)
634{
635 /*
636 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
637 * gets set after static_cpu_has() places have been converted via
638 * alternatives.
639 */
640 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
641 default_idle();
642 return;
643 }
644
645 tick_broadcast_enter();
646
647 default_idle();
648
649 /*
650 * The switch back from broadcast mode needs to be called with
651 * interrupts disabled.
652 */
653 local_irq_disable();
654 tick_broadcast_exit();
655 local_irq_enable();
656}
657
658/*
659 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
660 * We can't rely on cpuidle installing MWAIT, because it will not load
661 * on systems that support only C1 -- so the boot default must be MWAIT.
662 *
663 * Some AMD machines are the opposite, they depend on using HALT.
664 *
665 * So for default C1, which is used during boot until cpuidle loads,
666 * use MWAIT-C1 on Intel HW that has it, else use HALT.
667 */
668static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
669{
670 if (c->x86_vendor != X86_VENDOR_INTEL)
671 return 0;
672
673 if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR))
674 return 0;
675
676 return 1;
677}
678
679/*
680 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
681 * with interrupts enabled and no flags, which is backwards compatible with the
682 * original MWAIT implementation.
683 */
684static __cpuidle void mwait_idle(void)
685{
686 if (!current_set_polling_and_test()) {
687 trace_cpu_idle_rcuidle(1, smp_processor_id());
688 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
689 mb(); /* quirk */
690 clflush((void *)¤t_thread_info()->flags);
691 mb(); /* quirk */
692 }
693
694 __monitor((void *)¤t_thread_info()->flags, 0, 0);
695 if (!need_resched())
696 __sti_mwait(0, 0);
697 else
698 local_irq_enable();
699 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
700 } else {
701 local_irq_enable();
702 }
703 __current_clr_polling();
704}
705
706void select_idle_routine(const struct cpuinfo_x86 *c)
707{
708#ifdef CONFIG_SMP
709 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
710 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
711#endif
712 if (x86_idle || boot_option_idle_override == IDLE_POLL)
713 return;
714
715 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
716 pr_info("using AMD E400 aware idle routine\n");
717 x86_idle = amd_e400_idle;
718 } else if (prefer_mwait_c1_over_halt(c)) {
719 pr_info("using mwait in idle threads\n");
720 x86_idle = mwait_idle;
721 } else
722 x86_idle = default_idle;
723}
724
725void amd_e400_c1e_apic_setup(void)
726{
727 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
728 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
729 local_irq_disable();
730 tick_broadcast_force();
731 local_irq_enable();
732 }
733}
734
735void __init arch_post_acpi_subsys_init(void)
736{
737 u32 lo, hi;
738
739 if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
740 return;
741
742 /*
743 * AMD E400 detection needs to happen after ACPI has been enabled. If
744 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
745 * MSR_K8_INT_PENDING_MSG.
746 */
747 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
748 if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
749 return;
750
751 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
752
753 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
754 mark_tsc_unstable("TSC halt in AMD C1E");
755 pr_info("System has AMD C1E enabled\n");
756}
757
758static int __init idle_setup(char *str)
759{
760 if (!str)
761 return -EINVAL;
762
763 if (!strcmp(str, "poll")) {
764 pr_info("using polling idle threads\n");
765 boot_option_idle_override = IDLE_POLL;
766 cpu_idle_poll_ctrl(true);
767 } else if (!strcmp(str, "halt")) {
768 /*
769 * When the boot option of idle=halt is added, halt is
770 * forced to be used for CPU idle. In such case CPU C2/C3
771 * won't be used again.
772 * To continue to load the CPU idle driver, don't touch
773 * the boot_option_idle_override.
774 */
775 x86_idle = default_idle;
776 boot_option_idle_override = IDLE_HALT;
777 } else if (!strcmp(str, "nomwait")) {
778 /*
779 * If the boot option of "idle=nomwait" is added,
780 * it means that mwait will be disabled for CPU C2/C3
781 * states. In such case it won't touch the variable
782 * of boot_option_idle_override.
783 */
784 boot_option_idle_override = IDLE_NOMWAIT;
785 } else
786 return -1;
787
788 return 0;
789}
790early_param("idle", idle_setup);
791
792unsigned long arch_align_stack(unsigned long sp)
793{
794 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
795 sp -= get_random_int() % 8192;
796 return sp & ~0xf;
797}
798
799unsigned long arch_randomize_brk(struct mm_struct *mm)
800{
801 return randomize_page(mm->brk, 0x02000000);
802}
803
804/*
805 * Called from fs/proc with a reference on @p to find the function
806 * which called into schedule(). This needs to be done carefully
807 * because the task might wake up and we might look at a stack
808 * changing under us.
809 */
810unsigned long get_wchan(struct task_struct *p)
811{
812 unsigned long start, bottom, top, sp, fp, ip, ret = 0;
813 int count = 0;
814
815 if (p == current || p->state == TASK_RUNNING)
816 return 0;
817
818 if (!try_get_task_stack(p))
819 return 0;
820
821 start = (unsigned long)task_stack_page(p);
822 if (!start)
823 goto out;
824
825 /*
826 * Layout of the stack page:
827 *
828 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
829 * PADDING
830 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
831 * stack
832 * ----------- bottom = start
833 *
834 * The tasks stack pointer points at the location where the
835 * framepointer is stored. The data on the stack is:
836 * ... IP FP ... IP FP
837 *
838 * We need to read FP and IP, so we need to adjust the upper
839 * bound by another unsigned long.
840 */
841 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
842 top -= 2 * sizeof(unsigned long);
843 bottom = start;
844
845 sp = READ_ONCE(p->thread.sp);
846 if (sp < bottom || sp > top)
847 goto out;
848
849 fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
850 do {
851 if (fp < bottom || fp > top)
852 goto out;
853 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
854 if (!in_sched_functions(ip)) {
855 ret = ip;
856 goto out;
857 }
858 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
859 } while (count++ < 16 && p->state != TASK_RUNNING);
860
861out:
862 put_task_stack(p);
863 return ret;
864}
865
866long do_arch_prctl_common(struct task_struct *task, int option,
867 unsigned long cpuid_enabled)
868{
869 switch (option) {
870 case ARCH_GET_CPUID:
871 return get_cpuid_mode();
872 case ARCH_SET_CPUID:
873 return set_cpuid_mode(task, cpuid_enabled);
874 }
875
876 return -EINVAL;
877}
1#include <linux/errno.h>
2#include <linux/kernel.h>
3#include <linux/mm.h>
4#include <linux/smp.h>
5#include <linux/prctl.h>
6#include <linux/slab.h>
7#include <linux/sched.h>
8#include <linux/module.h>
9#include <linux/pm.h>
10#include <linux/clockchips.h>
11#include <linux/random.h>
12#include <linux/user-return-notifier.h>
13#include <linux/dmi.h>
14#include <linux/utsname.h>
15#include <trace/events/power.h>
16#include <linux/hw_breakpoint.h>
17#include <asm/cpu.h>
18#include <asm/system.h>
19#include <asm/apic.h>
20#include <asm/syscalls.h>
21#include <asm/idle.h>
22#include <asm/uaccess.h>
23#include <asm/i387.h>
24#include <asm/debugreg.h>
25
26struct kmem_cache *task_xstate_cachep;
27EXPORT_SYMBOL_GPL(task_xstate_cachep);
28
29int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
30{
31 int ret;
32
33 *dst = *src;
34 if (fpu_allocated(&src->thread.fpu)) {
35 memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu));
36 ret = fpu_alloc(&dst->thread.fpu);
37 if (ret)
38 return ret;
39 fpu_copy(&dst->thread.fpu, &src->thread.fpu);
40 }
41 return 0;
42}
43
44void free_thread_xstate(struct task_struct *tsk)
45{
46 fpu_free(&tsk->thread.fpu);
47}
48
49void free_thread_info(struct thread_info *ti)
50{
51 free_thread_xstate(ti->task);
52 free_pages((unsigned long)ti, get_order(THREAD_SIZE));
53}
54
55void arch_task_cache_init(void)
56{
57 task_xstate_cachep =
58 kmem_cache_create("task_xstate", xstate_size,
59 __alignof__(union thread_xstate),
60 SLAB_PANIC | SLAB_NOTRACK, NULL);
61}
62
63/*
64 * Free current thread data structures etc..
65 */
66void exit_thread(void)
67{
68 struct task_struct *me = current;
69 struct thread_struct *t = &me->thread;
70 unsigned long *bp = t->io_bitmap_ptr;
71
72 if (bp) {
73 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
74
75 t->io_bitmap_ptr = NULL;
76 clear_thread_flag(TIF_IO_BITMAP);
77 /*
78 * Careful, clear this in the TSS too:
79 */
80 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
81 t->io_bitmap_max = 0;
82 put_cpu();
83 kfree(bp);
84 }
85}
86
87void show_regs(struct pt_regs *regs)
88{
89 show_registers(regs);
90 show_trace(NULL, regs, (unsigned long *)kernel_stack_pointer(regs), 0);
91}
92
93void show_regs_common(void)
94{
95 const char *vendor, *product, *board;
96
97 vendor = dmi_get_system_info(DMI_SYS_VENDOR);
98 if (!vendor)
99 vendor = "";
100 product = dmi_get_system_info(DMI_PRODUCT_NAME);
101 if (!product)
102 product = "";
103
104 /* Board Name is optional */
105 board = dmi_get_system_info(DMI_BOARD_NAME);
106
107 printk(KERN_CONT "\n");
108 printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s",
109 current->pid, current->comm, print_tainted(),
110 init_utsname()->release,
111 (int)strcspn(init_utsname()->version, " "),
112 init_utsname()->version);
113 printk(KERN_CONT " %s %s", vendor, product);
114 if (board)
115 printk(KERN_CONT "/%s", board);
116 printk(KERN_CONT "\n");
117}
118
119void flush_thread(void)
120{
121 struct task_struct *tsk = current;
122
123 flush_ptrace_hw_breakpoint(tsk);
124 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
125 /*
126 * Forget coprocessor state..
127 */
128 tsk->fpu_counter = 0;
129 clear_fpu(tsk);
130 clear_used_math();
131}
132
133static void hard_disable_TSC(void)
134{
135 write_cr4(read_cr4() | X86_CR4_TSD);
136}
137
138void disable_TSC(void)
139{
140 preempt_disable();
141 if (!test_and_set_thread_flag(TIF_NOTSC))
142 /*
143 * Must flip the CPU state synchronously with
144 * TIF_NOTSC in the current running context.
145 */
146 hard_disable_TSC();
147 preempt_enable();
148}
149
150static void hard_enable_TSC(void)
151{
152 write_cr4(read_cr4() & ~X86_CR4_TSD);
153}
154
155static void enable_TSC(void)
156{
157 preempt_disable();
158 if (test_and_clear_thread_flag(TIF_NOTSC))
159 /*
160 * Must flip the CPU state synchronously with
161 * TIF_NOTSC in the current running context.
162 */
163 hard_enable_TSC();
164 preempt_enable();
165}
166
167int get_tsc_mode(unsigned long adr)
168{
169 unsigned int val;
170
171 if (test_thread_flag(TIF_NOTSC))
172 val = PR_TSC_SIGSEGV;
173 else
174 val = PR_TSC_ENABLE;
175
176 return put_user(val, (unsigned int __user *)adr);
177}
178
179int set_tsc_mode(unsigned int val)
180{
181 if (val == PR_TSC_SIGSEGV)
182 disable_TSC();
183 else if (val == PR_TSC_ENABLE)
184 enable_TSC();
185 else
186 return -EINVAL;
187
188 return 0;
189}
190
191void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
192 struct tss_struct *tss)
193{
194 struct thread_struct *prev, *next;
195
196 prev = &prev_p->thread;
197 next = &next_p->thread;
198
199 if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
200 test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
201 unsigned long debugctl = get_debugctlmsr();
202
203 debugctl &= ~DEBUGCTLMSR_BTF;
204 if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
205 debugctl |= DEBUGCTLMSR_BTF;
206
207 update_debugctlmsr(debugctl);
208 }
209
210 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
211 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
212 /* prev and next are different */
213 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
214 hard_disable_TSC();
215 else
216 hard_enable_TSC();
217 }
218
219 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
220 /*
221 * Copy the relevant range of the IO bitmap.
222 * Normally this is 128 bytes or less:
223 */
224 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
225 max(prev->io_bitmap_max, next->io_bitmap_max));
226 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
227 /*
228 * Clear any possible leftover bits:
229 */
230 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
231 }
232 propagate_user_return_notify(prev_p, next_p);
233}
234
235int sys_fork(struct pt_regs *regs)
236{
237 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
238}
239
240/*
241 * This is trivial, and on the face of it looks like it
242 * could equally well be done in user mode.
243 *
244 * Not so, for quite unobvious reasons - register pressure.
245 * In user mode vfork() cannot have a stack frame, and if
246 * done by calling the "clone()" system call directly, you
247 * do not have enough call-clobbered registers to hold all
248 * the information you need.
249 */
250int sys_vfork(struct pt_regs *regs)
251{
252 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
253 NULL, NULL);
254}
255
256long
257sys_clone(unsigned long clone_flags, unsigned long newsp,
258 void __user *parent_tid, void __user *child_tid, struct pt_regs *regs)
259{
260 if (!newsp)
261 newsp = regs->sp;
262 return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid);
263}
264
265/*
266 * This gets run with %si containing the
267 * function to call, and %di containing
268 * the "args".
269 */
270extern void kernel_thread_helper(void);
271
272/*
273 * Create a kernel thread
274 */
275int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
276{
277 struct pt_regs regs;
278
279 memset(®s, 0, sizeof(regs));
280
281 regs.si = (unsigned long) fn;
282 regs.di = (unsigned long) arg;
283
284#ifdef CONFIG_X86_32
285 regs.ds = __USER_DS;
286 regs.es = __USER_DS;
287 regs.fs = __KERNEL_PERCPU;
288 regs.gs = __KERNEL_STACK_CANARY;
289#else
290 regs.ss = __KERNEL_DS;
291#endif
292
293 regs.orig_ax = -1;
294 regs.ip = (unsigned long) kernel_thread_helper;
295 regs.cs = __KERNEL_CS | get_kernel_rpl();
296 regs.flags = X86_EFLAGS_IF | 0x2;
297
298 /* Ok, create the new process.. */
299 return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL);
300}
301EXPORT_SYMBOL(kernel_thread);
302
303/*
304 * sys_execve() executes a new program.
305 */
306long sys_execve(const char __user *name,
307 const char __user *const __user *argv,
308 const char __user *const __user *envp, struct pt_regs *regs)
309{
310 long error;
311 char *filename;
312
313 filename = getname(name);
314 error = PTR_ERR(filename);
315 if (IS_ERR(filename))
316 return error;
317 error = do_execve(filename, argv, envp, regs);
318
319#ifdef CONFIG_X86_32
320 if (error == 0) {
321 /* Make sure we don't return using sysenter.. */
322 set_thread_flag(TIF_IRET);
323 }
324#endif
325
326 putname(filename);
327 return error;
328}
329
330/*
331 * Idle related variables and functions
332 */
333unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
334EXPORT_SYMBOL(boot_option_idle_override);
335
336/*
337 * Powermanagement idle function, if any..
338 */
339void (*pm_idle)(void);
340#ifdef CONFIG_APM_MODULE
341EXPORT_SYMBOL(pm_idle);
342#endif
343
344#ifdef CONFIG_X86_32
345/*
346 * This halt magic was a workaround for ancient floppy DMA
347 * wreckage. It should be safe to remove.
348 */
349static int hlt_counter;
350void disable_hlt(void)
351{
352 hlt_counter++;
353}
354EXPORT_SYMBOL(disable_hlt);
355
356void enable_hlt(void)
357{
358 hlt_counter--;
359}
360EXPORT_SYMBOL(enable_hlt);
361
362static inline int hlt_use_halt(void)
363{
364 return (!hlt_counter && boot_cpu_data.hlt_works_ok);
365}
366#else
367static inline int hlt_use_halt(void)
368{
369 return 1;
370}
371#endif
372
373/*
374 * We use this if we don't have any better
375 * idle routine..
376 */
377void default_idle(void)
378{
379 if (hlt_use_halt()) {
380 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
381 trace_cpu_idle(1, smp_processor_id());
382 current_thread_info()->status &= ~TS_POLLING;
383 /*
384 * TS_POLLING-cleared state must be visible before we
385 * test NEED_RESCHED:
386 */
387 smp_mb();
388
389 if (!need_resched())
390 safe_halt(); /* enables interrupts racelessly */
391 else
392 local_irq_enable();
393 current_thread_info()->status |= TS_POLLING;
394 trace_power_end(smp_processor_id());
395 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
396 } else {
397 local_irq_enable();
398 /* loop is done by the caller */
399 cpu_relax();
400 }
401}
402#ifdef CONFIG_APM_MODULE
403EXPORT_SYMBOL(default_idle);
404#endif
405
406void stop_this_cpu(void *dummy)
407{
408 local_irq_disable();
409 /*
410 * Remove this CPU:
411 */
412 set_cpu_online(smp_processor_id(), false);
413 disable_local_APIC();
414
415 for (;;) {
416 if (hlt_works(smp_processor_id()))
417 halt();
418 }
419}
420
421static void do_nothing(void *unused)
422{
423}
424
425/*
426 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
427 * pm_idle and update to new pm_idle value. Required while changing pm_idle
428 * handler on SMP systems.
429 *
430 * Caller must have changed pm_idle to the new value before the call. Old
431 * pm_idle value will not be used by any CPU after the return of this function.
432 */
433void cpu_idle_wait(void)
434{
435 smp_mb();
436 /* kick all the CPUs so that they exit out of pm_idle */
437 smp_call_function(do_nothing, NULL, 1);
438}
439EXPORT_SYMBOL_GPL(cpu_idle_wait);
440
441/* Default MONITOR/MWAIT with no hints, used for default C1 state */
442static void mwait_idle(void)
443{
444 if (!need_resched()) {
445 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
446 trace_cpu_idle(1, smp_processor_id());
447 if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR))
448 clflush((void *)¤t_thread_info()->flags);
449
450 __monitor((void *)¤t_thread_info()->flags, 0, 0);
451 smp_mb();
452 if (!need_resched())
453 __sti_mwait(0, 0);
454 else
455 local_irq_enable();
456 trace_power_end(smp_processor_id());
457 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
458 } else
459 local_irq_enable();
460}
461
462/*
463 * On SMP it's slightly faster (but much more power-consuming!)
464 * to poll the ->work.need_resched flag instead of waiting for the
465 * cross-CPU IPI to arrive. Use this option with caution.
466 */
467static void poll_idle(void)
468{
469 trace_power_start(POWER_CSTATE, 0, smp_processor_id());
470 trace_cpu_idle(0, smp_processor_id());
471 local_irq_enable();
472 while (!need_resched())
473 cpu_relax();
474 trace_power_end(smp_processor_id());
475 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
476}
477
478/*
479 * mwait selection logic:
480 *
481 * It depends on the CPU. For AMD CPUs that support MWAIT this is
482 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
483 * then depend on a clock divisor and current Pstate of the core. If
484 * all cores of a processor are in halt state (C1) the processor can
485 * enter the C1E (C1 enhanced) state. If mwait is used this will never
486 * happen.
487 *
488 * idle=mwait overrides this decision and forces the usage of mwait.
489 */
490
491#define MWAIT_INFO 0x05
492#define MWAIT_ECX_EXTENDED_INFO 0x01
493#define MWAIT_EDX_C1 0xf0
494
495int mwait_usable(const struct cpuinfo_x86 *c)
496{
497 u32 eax, ebx, ecx, edx;
498
499 if (boot_option_idle_override == IDLE_FORCE_MWAIT)
500 return 1;
501
502 if (c->cpuid_level < MWAIT_INFO)
503 return 0;
504
505 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
506 /* Check, whether EDX has extended info about MWAIT */
507 if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
508 return 1;
509
510 /*
511 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
512 * C1 supports MWAIT
513 */
514 return (edx & MWAIT_EDX_C1);
515}
516
517bool amd_e400_c1e_detected;
518EXPORT_SYMBOL(amd_e400_c1e_detected);
519
520static cpumask_var_t amd_e400_c1e_mask;
521
522void amd_e400_remove_cpu(int cpu)
523{
524 if (amd_e400_c1e_mask != NULL)
525 cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
526}
527
528/*
529 * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
530 * pending message MSR. If we detect C1E, then we handle it the same
531 * way as C3 power states (local apic timer and TSC stop)
532 */
533static void amd_e400_idle(void)
534{
535 if (need_resched())
536 return;
537
538 if (!amd_e400_c1e_detected) {
539 u32 lo, hi;
540
541 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
542
543 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
544 amd_e400_c1e_detected = true;
545 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
546 mark_tsc_unstable("TSC halt in AMD C1E");
547 printk(KERN_INFO "System has AMD C1E enabled\n");
548 }
549 }
550
551 if (amd_e400_c1e_detected) {
552 int cpu = smp_processor_id();
553
554 if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
555 cpumask_set_cpu(cpu, amd_e400_c1e_mask);
556 /*
557 * Force broadcast so ACPI can not interfere.
558 */
559 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
560 &cpu);
561 printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
562 cpu);
563 }
564 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
565
566 default_idle();
567
568 /*
569 * The switch back from broadcast mode needs to be
570 * called with interrupts disabled.
571 */
572 local_irq_disable();
573 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
574 local_irq_enable();
575 } else
576 default_idle();
577}
578
579void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
580{
581#ifdef CONFIG_SMP
582 if (pm_idle == poll_idle && smp_num_siblings > 1) {
583 printk_once(KERN_WARNING "WARNING: polling idle and HT enabled,"
584 " performance may degrade.\n");
585 }
586#endif
587 if (pm_idle)
588 return;
589
590 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
591 /*
592 * One CPU supports mwait => All CPUs supports mwait
593 */
594 printk(KERN_INFO "using mwait in idle threads.\n");
595 pm_idle = mwait_idle;
596 } else if (cpu_has_amd_erratum(amd_erratum_400)) {
597 /* E400: APIC timer interrupt does not wake up CPU from C1e */
598 printk(KERN_INFO "using AMD E400 aware idle routine\n");
599 pm_idle = amd_e400_idle;
600 } else
601 pm_idle = default_idle;
602}
603
604void __init init_amd_e400_c1e_mask(void)
605{
606 /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
607 if (pm_idle == amd_e400_idle)
608 zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
609}
610
611static int __init idle_setup(char *str)
612{
613 if (!str)
614 return -EINVAL;
615
616 if (!strcmp(str, "poll")) {
617 printk("using polling idle threads.\n");
618 pm_idle = poll_idle;
619 boot_option_idle_override = IDLE_POLL;
620 } else if (!strcmp(str, "mwait")) {
621 boot_option_idle_override = IDLE_FORCE_MWAIT;
622 WARN_ONCE(1, "\"idle=mwait\" will be removed in 2012\n");
623 } else if (!strcmp(str, "halt")) {
624 /*
625 * When the boot option of idle=halt is added, halt is
626 * forced to be used for CPU idle. In such case CPU C2/C3
627 * won't be used again.
628 * To continue to load the CPU idle driver, don't touch
629 * the boot_option_idle_override.
630 */
631 pm_idle = default_idle;
632 boot_option_idle_override = IDLE_HALT;
633 } else if (!strcmp(str, "nomwait")) {
634 /*
635 * If the boot option of "idle=nomwait" is added,
636 * it means that mwait will be disabled for CPU C2/C3
637 * states. In such case it won't touch the variable
638 * of boot_option_idle_override.
639 */
640 boot_option_idle_override = IDLE_NOMWAIT;
641 } else
642 return -1;
643
644 return 0;
645}
646early_param("idle", idle_setup);
647
648unsigned long arch_align_stack(unsigned long sp)
649{
650 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
651 sp -= get_random_int() % 8192;
652 return sp & ~0xf;
653}
654
655unsigned long arch_randomize_brk(struct mm_struct *mm)
656{
657 unsigned long range_end = mm->brk + 0x02000000;
658 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
659}
660