Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * TLB Management (flush/create/diagnostics) for ARC700
4 *
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 *
7 * vineetg: Aug 2011
8 * -Reintroduce duplicate PD fixup - some customer chips still have the issue
9 *
10 * vineetg: May 2011
11 * -No need to flush_cache_page( ) for each call to update_mmu_cache()
12 * some of the LMBench tests improved amazingly
13 * = page-fault thrice as fast (75 usec to 28 usec)
14 * = mmap twice as fast (9.6 msec to 4.6 msec),
15 * = fork (5.3 msec to 3.7 msec)
16 *
17 * vineetg: April 2011 :
18 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
19 * helps avoid a shift when preparing PD0 from PTE
20 *
21 * vineetg: April 2011 : Preparing for MMU V3
22 * -MMU v2/v3 BCRs decoded differently
23 * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
24 * -tlb_entry_erase( ) can be void
25 * -local_flush_tlb_range( ):
26 * = need not "ceil" @end
27 * = walks MMU only if range spans < 32 entries, as opposed to 256
28 *
29 * Vineetg: Sept 10th 2008
30 * -Changes related to MMU v2 (Rel 4.8)
31 *
32 * Vineetg: Aug 29th 2008
33 * -In TLB Flush operations (Metal Fix MMU) there is a explict command to
34 * flush Micro-TLBS. If TLB Index Reg is invalid prior to TLBIVUTLB cmd,
35 * it fails. Thus need to load it with ANY valid value before invoking
36 * TLBIVUTLB cmd
37 *
38 * Vineetg: Aug 21th 2008:
39 * -Reduced the duration of IRQ lockouts in TLB Flush routines
40 * -Multiple copies of TLB erase code seperated into a "single" function
41 * -In TLB Flush routines, interrupt disabling moved UP to retrieve ASID
42 * in interrupt-safe region.
43 *
44 * Vineetg: April 23rd Bug #93131
45 * Problem: tlb_flush_kernel_range() doesn't do anything if the range to
46 * flush is more than the size of TLB itself.
47 *
48 * Rahul Trivedi : Codito Technologies 2004
49 */
50
51#include <linux/module.h>
52#include <linux/bug.h>
53#include <linux/mm_types.h>
54
55#include <asm/arcregs.h>
56#include <asm/setup.h>
57#include <asm/mmu_context.h>
58#include <asm/mmu.h>
59
60/* Need for ARC MMU v2
61 *
62 * ARC700 MMU-v1 had a Joint-TLB for Code and Data and is 2 way set-assoc.
63 * For a memcpy operation with 3 players (src/dst/code) such that all 3 pages
64 * map into same set, there would be contention for the 2 ways causing severe
65 * Thrashing.
66 *
67 * Although J-TLB is 2 way set assoc, ARC700 caches J-TLB into uTLBS which has
68 * much higher associativity. u-D-TLB is 8 ways, u-I-TLB is 4 ways.
69 * Given this, the thrasing problem should never happen because once the 3
70 * J-TLB entries are created (even though 3rd will knock out one of the prev
71 * two), the u-D-TLB and u-I-TLB will have what is required to accomplish memcpy
72 *
73 * Yet we still see the Thrashing because a J-TLB Write cause flush of u-TLBs.
74 * This is a simple design for keeping them in sync. So what do we do?
75 * The solution which James came up was pretty neat. It utilised the assoc
76 * of uTLBs by not invalidating always but only when absolutely necessary.
77 *
78 * - Existing TLB commands work as before
79 * - New command (TLBWriteNI) for TLB write without clearing uTLBs
80 * - New command (TLBIVUTLB) to invalidate uTLBs.
81 *
82 * The uTLBs need only be invalidated when pages are being removed from the
83 * OS page table. If a 'victim' TLB entry is being overwritten in the main TLB
84 * as a result of a miss, the removed entry is still allowed to exist in the
85 * uTLBs as it is still valid and present in the OS page table. This allows the
86 * full associativity of the uTLBs to hide the limited associativity of the main
87 * TLB.
88 *
89 * During a miss handler, the new "TLBWriteNI" command is used to load
90 * entries without clearing the uTLBs.
91 *
92 * When the OS page table is updated, TLB entries that may be associated with a
93 * removed page are removed (flushed) from the TLB using TLBWrite. In this
94 * circumstance, the uTLBs must also be cleared. This is done by using the
95 * existing TLBWrite command. An explicit IVUTLB is also required for those
96 * corner cases when TLBWrite was not executed at all because the corresp
97 * J-TLB entry got evicted/replaced.
98 */
99
100
101/* A copy of the ASID from the PID reg is kept in asid_cache */
102DEFINE_PER_CPU(unsigned int, asid_cache) = MM_CTXT_FIRST_CYCLE;
103
104static int __read_mostly pae_exists;
105
106/*
107 * Utility Routine to erase a J-TLB entry
108 * Caller needs to setup Index Reg (manually or via getIndex)
109 */
110static inline void __tlb_entry_erase(void)
111{
112 write_aux_reg(ARC_REG_TLBPD1, 0);
113
114 if (is_pae40_enabled())
115 write_aux_reg(ARC_REG_TLBPD1HI, 0);
116
117 write_aux_reg(ARC_REG_TLBPD0, 0);
118 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
119}
120
121#if (CONFIG_ARC_MMU_VER < 4)
122
123static inline unsigned int tlb_entry_lkup(unsigned long vaddr_n_asid)
124{
125 unsigned int idx;
126
127 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid);
128
129 write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe);
130 idx = read_aux_reg(ARC_REG_TLBINDEX);
131
132 return idx;
133}
134
135static void tlb_entry_erase(unsigned int vaddr_n_asid)
136{
137 unsigned int idx;
138
139 /* Locate the TLB entry for this vaddr + ASID */
140 idx = tlb_entry_lkup(vaddr_n_asid);
141
142 /* No error means entry found, zero it out */
143 if (likely(!(idx & TLB_LKUP_ERR))) {
144 __tlb_entry_erase();
145 } else {
146 /* Duplicate entry error */
147 WARN(idx == TLB_DUP_ERR, "Probe returned Dup PD for %x\n",
148 vaddr_n_asid);
149 }
150}
151
152/****************************************************************************
153 * ARC700 MMU caches recently used J-TLB entries (RAM) as uTLBs (FLOPs)
154 *
155 * New IVUTLB cmd in MMU v2 explictly invalidates the uTLB
156 *
157 * utlb_invalidate ( )
158 * -For v2 MMU calls Flush uTLB Cmd
159 * -For v1 MMU does nothing (except for Metal Fix v1 MMU)
160 * This is because in v1 TLBWrite itself invalidate uTLBs
161 ***************************************************************************/
162
163static void utlb_invalidate(void)
164{
165#if (CONFIG_ARC_MMU_VER >= 2)
166
167#if (CONFIG_ARC_MMU_VER == 2)
168 /* MMU v2 introduced the uTLB Flush command.
169 * There was however an obscure hardware bug, where uTLB flush would
170 * fail when a prior probe for J-TLB (both totally unrelated) would
171 * return lkup err - because the entry didn't exist in MMU.
172 * The Workround was to set Index reg with some valid value, prior to
173 * flush. This was fixed in MMU v3 hence not needed any more
174 */
175 unsigned int idx;
176
177 /* make sure INDEX Reg is valid */
178 idx = read_aux_reg(ARC_REG_TLBINDEX);
179
180 /* If not write some dummy val */
181 if (unlikely(idx & TLB_LKUP_ERR))
182 write_aux_reg(ARC_REG_TLBINDEX, 0xa);
183#endif
184
185 write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB);
186#endif
187
188}
189
190static void tlb_entry_insert(unsigned int pd0, pte_t pd1)
191{
192 unsigned int idx;
193
194 /*
195 * First verify if entry for this vaddr+ASID already exists
196 * This also sets up PD0 (vaddr, ASID..) for final commit
197 */
198 idx = tlb_entry_lkup(pd0);
199
200 /*
201 * If Not already present get a free slot from MMU.
202 * Otherwise, Probe would have located the entry and set INDEX Reg
203 * with existing location. This will cause Write CMD to over-write
204 * existing entry with new PD0 and PD1
205 */
206 if (likely(idx & TLB_LKUP_ERR))
207 write_aux_reg(ARC_REG_TLBCOMMAND, TLBGetIndex);
208
209 /* setup the other half of TLB entry (pfn, rwx..) */
210 write_aux_reg(ARC_REG_TLBPD1, pd1);
211
212 /*
213 * Commit the Entry to MMU
214 * It doesn't sound safe to use the TLBWriteNI cmd here
215 * which doesn't flush uTLBs. I'd rather be safe than sorry.
216 */
217 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
218}
219
220#else /* CONFIG_ARC_MMU_VER >= 4) */
221
222static void utlb_invalidate(void)
223{
224 /* No need since uTLB is always in sync with JTLB */
225}
226
227static void tlb_entry_erase(unsigned int vaddr_n_asid)
228{
229 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid | _PAGE_PRESENT);
230 write_aux_reg(ARC_REG_TLBCOMMAND, TLBDeleteEntry);
231}
232
233static void tlb_entry_insert(unsigned int pd0, pte_t pd1)
234{
235 write_aux_reg(ARC_REG_TLBPD0, pd0);
236 write_aux_reg(ARC_REG_TLBPD1, pd1);
237
238 if (is_pae40_enabled())
239 write_aux_reg(ARC_REG_TLBPD1HI, (u64)pd1 >> 32);
240
241 write_aux_reg(ARC_REG_TLBCOMMAND, TLBInsertEntry);
242}
243
244#endif
245
246/*
247 * Un-conditionally (without lookup) erase the entire MMU contents
248 */
249
250noinline void local_flush_tlb_all(void)
251{
252 struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
253 unsigned long flags;
254 unsigned int entry;
255 int num_tlb = mmu->sets * mmu->ways;
256
257 local_irq_save(flags);
258
259 /* Load PD0 and PD1 with template for a Blank Entry */
260 write_aux_reg(ARC_REG_TLBPD1, 0);
261
262 if (is_pae40_enabled())
263 write_aux_reg(ARC_REG_TLBPD1HI, 0);
264
265 write_aux_reg(ARC_REG_TLBPD0, 0);
266
267 for (entry = 0; entry < num_tlb; entry++) {
268 /* write this entry to the TLB */
269 write_aux_reg(ARC_REG_TLBINDEX, entry);
270 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
271 }
272
273 if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE)) {
274 const int stlb_idx = 0x800;
275
276 /* Blank sTLB entry */
277 write_aux_reg(ARC_REG_TLBPD0, _PAGE_HW_SZ);
278
279 for (entry = stlb_idx; entry < stlb_idx + 16; entry++) {
280 write_aux_reg(ARC_REG_TLBINDEX, entry);
281 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
282 }
283 }
284
285 utlb_invalidate();
286
287 local_irq_restore(flags);
288}
289
290/*
291 * Flush the entrie MM for userland. The fastest way is to move to Next ASID
292 */
293noinline void local_flush_tlb_mm(struct mm_struct *mm)
294{
295 /*
296 * Small optimisation courtesy IA64
297 * flush_mm called during fork,exit,munmap etc, multiple times as well.
298 * Only for fork( ) do we need to move parent to a new MMU ctxt,
299 * all other cases are NOPs, hence this check.
300 */
301 if (atomic_read(&mm->mm_users) == 0)
302 return;
303
304 /*
305 * - Move to a new ASID, but only if the mm is still wired in
306 * (Android Binder ended up calling this for vma->mm != tsk->mm,
307 * causing h/w - s/w ASID to get out of sync)
308 * - Also get_new_mmu_context() new implementation allocates a new
309 * ASID only if it is not allocated already - so unallocate first
310 */
311 destroy_context(mm);
312 if (current->mm == mm)
313 get_new_mmu_context(mm);
314}
315
316/*
317 * Flush a Range of TLB entries for userland.
318 * @start is inclusive, while @end is exclusive
319 * Difference between this and Kernel Range Flush is
320 * -Here the fastest way (if range is too large) is to move to next ASID
321 * without doing any explicit Shootdown
322 * -In case of kernel Flush, entry has to be shot down explictly
323 */
324void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
325 unsigned long end)
326{
327 const unsigned int cpu = smp_processor_id();
328 unsigned long flags;
329
330 /* If range @start to @end is more than 32 TLB entries deep,
331 * its better to move to a new ASID rather than searching for
332 * individual entries and then shooting them down
333 *
334 * The calc above is rough, doesn't account for unaligned parts,
335 * since this is heuristics based anyways
336 */
337 if (unlikely((end - start) >= PAGE_SIZE * 32)) {
338 local_flush_tlb_mm(vma->vm_mm);
339 return;
340 }
341
342 /*
343 * @start moved to page start: this alone suffices for checking
344 * loop end condition below, w/o need for aligning @end to end
345 * e.g. 2000 to 4001 will anyhow loop twice
346 */
347 start &= PAGE_MASK;
348
349 local_irq_save(flags);
350
351 if (asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID) {
352 while (start < end) {
353 tlb_entry_erase(start | hw_pid(vma->vm_mm, cpu));
354 start += PAGE_SIZE;
355 }
356 }
357
358 utlb_invalidate();
359
360 local_irq_restore(flags);
361}
362
363/* Flush the kernel TLB entries - vmalloc/modules (Global from MMU perspective)
364 * @start, @end interpreted as kvaddr
365 * Interestingly, shared TLB entries can also be flushed using just
366 * @start,@end alone (interpreted as user vaddr), although technically SASID
367 * is also needed. However our smart TLbProbe lookup takes care of that.
368 */
369void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
370{
371 unsigned long flags;
372
373 /* exactly same as above, except for TLB entry not taking ASID */
374
375 if (unlikely((end - start) >= PAGE_SIZE * 32)) {
376 local_flush_tlb_all();
377 return;
378 }
379
380 start &= PAGE_MASK;
381
382 local_irq_save(flags);
383 while (start < end) {
384 tlb_entry_erase(start);
385 start += PAGE_SIZE;
386 }
387
388 utlb_invalidate();
389
390 local_irq_restore(flags);
391}
392
393/*
394 * Delete TLB entry in MMU for a given page (??? address)
395 * NOTE One TLB entry contains translation for single PAGE
396 */
397
398void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
399{
400 const unsigned int cpu = smp_processor_id();
401 unsigned long flags;
402
403 /* Note that it is critical that interrupts are DISABLED between
404 * checking the ASID and using it flush the TLB entry
405 */
406 local_irq_save(flags);
407
408 if (asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID) {
409 tlb_entry_erase((page & PAGE_MASK) | hw_pid(vma->vm_mm, cpu));
410 utlb_invalidate();
411 }
412
413 local_irq_restore(flags);
414}
415
416#ifdef CONFIG_SMP
417
418struct tlb_args {
419 struct vm_area_struct *ta_vma;
420 unsigned long ta_start;
421 unsigned long ta_end;
422};
423
424static inline void ipi_flush_tlb_page(void *arg)
425{
426 struct tlb_args *ta = arg;
427
428 local_flush_tlb_page(ta->ta_vma, ta->ta_start);
429}
430
431static inline void ipi_flush_tlb_range(void *arg)
432{
433 struct tlb_args *ta = arg;
434
435 local_flush_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
436}
437
438#ifdef CONFIG_TRANSPARENT_HUGEPAGE
439static inline void ipi_flush_pmd_tlb_range(void *arg)
440{
441 struct tlb_args *ta = arg;
442
443 local_flush_pmd_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
444}
445#endif
446
447static inline void ipi_flush_tlb_kernel_range(void *arg)
448{
449 struct tlb_args *ta = (struct tlb_args *)arg;
450
451 local_flush_tlb_kernel_range(ta->ta_start, ta->ta_end);
452}
453
454void flush_tlb_all(void)
455{
456 on_each_cpu((smp_call_func_t)local_flush_tlb_all, NULL, 1);
457}
458
459void flush_tlb_mm(struct mm_struct *mm)
460{
461 on_each_cpu_mask(mm_cpumask(mm), (smp_call_func_t)local_flush_tlb_mm,
462 mm, 1);
463}
464
465void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
466{
467 struct tlb_args ta = {
468 .ta_vma = vma,
469 .ta_start = uaddr
470 };
471
472 on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_page, &ta, 1);
473}
474
475void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
476 unsigned long end)
477{
478 struct tlb_args ta = {
479 .ta_vma = vma,
480 .ta_start = start,
481 .ta_end = end
482 };
483
484 on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_range, &ta, 1);
485}
486
487#ifdef CONFIG_TRANSPARENT_HUGEPAGE
488void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
489 unsigned long end)
490{
491 struct tlb_args ta = {
492 .ta_vma = vma,
493 .ta_start = start,
494 .ta_end = end
495 };
496
497 on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_pmd_tlb_range, &ta, 1);
498}
499#endif
500
501void flush_tlb_kernel_range(unsigned long start, unsigned long end)
502{
503 struct tlb_args ta = {
504 .ta_start = start,
505 .ta_end = end
506 };
507
508 on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
509}
510#endif
511
512/*
513 * Routine to create a TLB entry
514 */
515void create_tlb(struct vm_area_struct *vma, unsigned long vaddr, pte_t *ptep)
516{
517 unsigned long flags;
518 unsigned int asid_or_sasid, rwx;
519 unsigned long pd0;
520 pte_t pd1;
521
522 /*
523 * create_tlb() assumes that current->mm == vma->mm, since
524 * -it ASID for TLB entry is fetched from MMU ASID reg (valid for curr)
525 * -completes the lazy write to SASID reg (again valid for curr tsk)
526 *
527 * Removing the assumption involves
528 * -Using vma->mm->context{ASID,SASID}, as opposed to MMU reg.
529 * -Fix the TLB paranoid debug code to not trigger false negatives.
530 * -More importantly it makes this handler inconsistent with fast-path
531 * TLB Refill handler which always deals with "current"
532 *
533 * Lets see the use cases when current->mm != vma->mm and we land here
534 * 1. execve->copy_strings()->__get_user_pages->handle_mm_fault
535 * Here VM wants to pre-install a TLB entry for user stack while
536 * current->mm still points to pre-execve mm (hence the condition).
537 * However the stack vaddr is soon relocated (randomization) and
538 * move_page_tables() tries to undo that TLB entry.
539 * Thus not creating TLB entry is not any worse.
540 *
541 * 2. ptrace(POKETEXT) causes a CoW - debugger(current) inserting a
542 * breakpoint in debugged task. Not creating a TLB now is not
543 * performance critical.
544 *
545 * Both the cases above are not good enough for code churn.
546 */
547 if (current->active_mm != vma->vm_mm)
548 return;
549
550 local_irq_save(flags);
551
552 tlb_paranoid_check(asid_mm(vma->vm_mm, smp_processor_id()), vaddr);
553
554 vaddr &= PAGE_MASK;
555
556 /* update this PTE credentials */
557 pte_val(*ptep) |= (_PAGE_PRESENT | _PAGE_ACCESSED);
558
559 /* Create HW TLB(PD0,PD1) from PTE */
560
561 /* ASID for this task */
562 asid_or_sasid = read_aux_reg(ARC_REG_PID) & 0xff;
563
564 pd0 = vaddr | asid_or_sasid | (pte_val(*ptep) & PTE_BITS_IN_PD0);
565
566 /*
567 * ARC MMU provides fully orthogonal access bits for K/U mode,
568 * however Linux only saves 1 set to save PTE real-estate
569 * Here we convert 3 PTE bits into 6 MMU bits:
570 * -Kernel only entries have Kr Kw Kx 0 0 0
571 * -User entries have mirrored K and U bits
572 */
573 rwx = pte_val(*ptep) & PTE_BITS_RWX;
574
575 if (pte_val(*ptep) & _PAGE_GLOBAL)
576 rwx <<= 3; /* r w x => Kr Kw Kx 0 0 0 */
577 else
578 rwx |= (rwx << 3); /* r w x => Kr Kw Kx Ur Uw Ux */
579
580 pd1 = rwx | (pte_val(*ptep) & PTE_BITS_NON_RWX_IN_PD1);
581
582 tlb_entry_insert(pd0, pd1);
583
584 local_irq_restore(flags);
585}
586
587/*
588 * Called at the end of pagefault, for a userspace mapped page
589 * -pre-install the corresponding TLB entry into MMU
590 * -Finalize the delayed D-cache flush of kernel mapping of page due to
591 * flush_dcache_page(), copy_user_page()
592 *
593 * Note that flush (when done) involves both WBACK - so physical page is
594 * in sync as well as INV - so any non-congruent aliases don't remain
595 */
596void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
597 pte_t *ptep)
598{
599 unsigned long vaddr = vaddr_unaligned & PAGE_MASK;
600 phys_addr_t paddr = pte_val(*ptep) & PAGE_MASK;
601 struct page *page = pfn_to_page(pte_pfn(*ptep));
602
603 create_tlb(vma, vaddr, ptep);
604
605 if (page == ZERO_PAGE(0)) {
606 return;
607 }
608
609 /*
610 * Exec page : Independent of aliasing/page-color considerations,
611 * since icache doesn't snoop dcache on ARC, any dirty
612 * K-mapping of a code page needs to be wback+inv so that
613 * icache fetch by userspace sees code correctly.
614 * !EXEC page: If K-mapping is NOT congruent to U-mapping, flush it
615 * so userspace sees the right data.
616 * (Avoids the flush for Non-exec + congruent mapping case)
617 */
618 if ((vma->vm_flags & VM_EXEC) ||
619 addr_not_cache_congruent(paddr, vaddr)) {
620
621 int dirty = !test_and_set_bit(PG_dc_clean, &page->flags);
622 if (dirty) {
623 /* wback + inv dcache lines (K-mapping) */
624 __flush_dcache_page(paddr, paddr);
625
626 /* invalidate any existing icache lines (U-mapping) */
627 if (vma->vm_flags & VM_EXEC)
628 __inv_icache_page(paddr, vaddr);
629 }
630 }
631}
632
633#ifdef CONFIG_TRANSPARENT_HUGEPAGE
634
635/*
636 * MMUv4 in HS38x cores supports Super Pages which are basis for Linux THP
637 * support.
638 *
639 * Normal and Super pages can co-exist (ofcourse not overlap) in TLB with a
640 * new bit "SZ" in TLB page descriptor to distinguish between them.
641 * Super Page size is configurable in hardware (4K to 16M), but fixed once
642 * RTL builds.
643 *
644 * The exact THP size a Linx configuration will support is a function of:
645 * - MMU page size (typical 8K, RTL fixed)
646 * - software page walker address split between PGD:PTE:PFN (typical
647 * 11:8:13, but can be changed with 1 line)
648 * So for above default, THP size supported is 8K * (2^8) = 2M
649 *
650 * Default Page Walker is 2 levels, PGD:PTE:PFN, which in THP regime
651 * reduces to 1 level (as PTE is folded into PGD and canonically referred
652 * to as PMD).
653 * Thus THP PMD accessors are implemented in terms of PTE (just like sparc)
654 */
655
656void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
657 pmd_t *pmd)
658{
659 pte_t pte = __pte(pmd_val(*pmd));
660 update_mmu_cache(vma, addr, &pte);
661}
662
663void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
664 pgtable_t pgtable)
665{
666 struct list_head *lh = (struct list_head *) pgtable;
667
668 assert_spin_locked(&mm->page_table_lock);
669
670 /* FIFO */
671 if (!pmd_huge_pte(mm, pmdp))
672 INIT_LIST_HEAD(lh);
673 else
674 list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
675 pmd_huge_pte(mm, pmdp) = pgtable;
676}
677
678pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
679{
680 struct list_head *lh;
681 pgtable_t pgtable;
682
683 assert_spin_locked(&mm->page_table_lock);
684
685 pgtable = pmd_huge_pte(mm, pmdp);
686 lh = (struct list_head *) pgtable;
687 if (list_empty(lh))
688 pmd_huge_pte(mm, pmdp) = NULL;
689 else {
690 pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
691 list_del(lh);
692 }
693
694 pte_val(pgtable[0]) = 0;
695 pte_val(pgtable[1]) = 0;
696
697 return pgtable;
698}
699
700void local_flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
701 unsigned long end)
702{
703 unsigned int cpu;
704 unsigned long flags;
705
706 local_irq_save(flags);
707
708 cpu = smp_processor_id();
709
710 if (likely(asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID)) {
711 unsigned int asid = hw_pid(vma->vm_mm, cpu);
712
713 /* No need to loop here: this will always be for 1 Huge Page */
714 tlb_entry_erase(start | _PAGE_HW_SZ | asid);
715 }
716
717 local_irq_restore(flags);
718}
719
720#endif
721
722/* Read the Cache Build Confuration Registers, Decode them and save into
723 * the cpuinfo structure for later use.
724 * No Validation is done here, simply read/convert the BCRs
725 */
726void read_decode_mmu_bcr(void)
727{
728 struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
729 unsigned int tmp;
730 struct bcr_mmu_1_2 {
731#ifdef CONFIG_CPU_BIG_ENDIAN
732 unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8;
733#else
734 unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8;
735#endif
736 } *mmu2;
737
738 struct bcr_mmu_3 {
739#ifdef CONFIG_CPU_BIG_ENDIAN
740 unsigned int ver:8, ways:4, sets:4, res:3, sasid:1, pg_sz:4,
741 u_itlb:4, u_dtlb:4;
742#else
743 unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, sasid:1, res:3, sets:4,
744 ways:4, ver:8;
745#endif
746 } *mmu3;
747
748 struct bcr_mmu_4 {
749#ifdef CONFIG_CPU_BIG_ENDIAN
750 unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
751 n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
752#else
753 /* DTLB ITLB JES JE JA */
754 unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
755 pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
756#endif
757 } *mmu4;
758
759 tmp = read_aux_reg(ARC_REG_MMU_BCR);
760 mmu->ver = (tmp >> 24);
761
762 if (is_isa_arcompact()) {
763 if (mmu->ver <= 2) {
764 mmu2 = (struct bcr_mmu_1_2 *)&tmp;
765 mmu->pg_sz_k = TO_KB(0x2000);
766 mmu->sets = 1 << mmu2->sets;
767 mmu->ways = 1 << mmu2->ways;
768 mmu->u_dtlb = mmu2->u_dtlb;
769 mmu->u_itlb = mmu2->u_itlb;
770 } else {
771 mmu3 = (struct bcr_mmu_3 *)&tmp;
772 mmu->pg_sz_k = 1 << (mmu3->pg_sz - 1);
773 mmu->sets = 1 << mmu3->sets;
774 mmu->ways = 1 << mmu3->ways;
775 mmu->u_dtlb = mmu3->u_dtlb;
776 mmu->u_itlb = mmu3->u_itlb;
777 mmu->sasid = mmu3->sasid;
778 }
779 } else {
780 mmu4 = (struct bcr_mmu_4 *)&tmp;
781 mmu->pg_sz_k = 1 << (mmu4->sz0 - 1);
782 mmu->s_pg_sz_m = 1 << (mmu4->sz1 - 11);
783 mmu->sets = 64 << mmu4->n_entry;
784 mmu->ways = mmu4->n_ways * 2;
785 mmu->u_dtlb = mmu4->u_dtlb * 4;
786 mmu->u_itlb = mmu4->u_itlb * 4;
787 mmu->sasid = mmu4->sasid;
788 pae_exists = mmu->pae = mmu4->pae;
789 }
790}
791
792char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
793{
794 int n = 0;
795 struct cpuinfo_arc_mmu *p_mmu = &cpuinfo_arc700[cpu_id].mmu;
796 char super_pg[64] = "";
797
798 if (p_mmu->s_pg_sz_m)
799 scnprintf(super_pg, 64, "%dM Super Page %s",
800 p_mmu->s_pg_sz_m,
801 IS_USED_CFG(CONFIG_TRANSPARENT_HUGEPAGE));
802
803 n += scnprintf(buf + n, len - n,
804 "MMU [v%x]\t: %dk PAGE, %sJTLB %d (%dx%d), uDTLB %d, uITLB %d%s%s\n",
805 p_mmu->ver, p_mmu->pg_sz_k, super_pg,
806 p_mmu->sets * p_mmu->ways, p_mmu->sets, p_mmu->ways,
807 p_mmu->u_dtlb, p_mmu->u_itlb,
808 IS_AVAIL2(p_mmu->pae, ", PAE40 ", CONFIG_ARC_HAS_PAE40));
809
810 return buf;
811}
812
813int pae40_exist_but_not_enab(void)
814{
815 return pae_exists && !is_pae40_enabled();
816}
817
818void arc_mmu_init(void)
819{
820 struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
821 char str[256];
822 int compat = 0;
823
824 pr_info("%s", arc_mmu_mumbojumbo(0, str, sizeof(str)));
825
826 /*
827 * Can't be done in processor.h due to header include depenedencies
828 */
829 BUILD_BUG_ON(!IS_ALIGNED((CONFIG_ARC_KVADDR_SIZE << 20), PMD_SIZE));
830
831 /*
832 * stack top size sanity check,
833 * Can't be done in processor.h due to header include depenedencies
834 */
835 BUILD_BUG_ON(!IS_ALIGNED(STACK_TOP, PMD_SIZE));
836
837 /*
838 * Ensure that MMU features assumed by kernel exist in hardware.
839 * For older ARC700 cpus, it has to be exact match, since the MMU
840 * revisions were not backwards compatible (MMUv3 TLB layout changed
841 * so even if kernel for v2 didn't use any new cmds of v3, it would
842 * still not work.
843 * For HS cpus, MMUv4 was baseline and v5 is backwards compatible
844 * (will run older software).
845 */
846 if (is_isa_arcompact() && mmu->ver == CONFIG_ARC_MMU_VER)
847 compat = 1;
848 else if (is_isa_arcv2() && mmu->ver >= CONFIG_ARC_MMU_VER)
849 compat = 1;
850
851 if (!compat) {
852 panic("MMU ver %d doesn't match kernel built for %d...\n",
853 mmu->ver, CONFIG_ARC_MMU_VER);
854 }
855
856 if (mmu->pg_sz_k != TO_KB(PAGE_SIZE))
857 panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE));
858
859 if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE) &&
860 mmu->s_pg_sz_m != TO_MB(HPAGE_PMD_SIZE))
861 panic("MMU Super pg size != Linux HPAGE_PMD_SIZE (%luM)\n",
862 (unsigned long)TO_MB(HPAGE_PMD_SIZE));
863
864 if (IS_ENABLED(CONFIG_ARC_HAS_PAE40) && !mmu->pae)
865 panic("Hardware doesn't support PAE40\n");
866
867 /* Enable the MMU */
868 write_aux_reg(ARC_REG_PID, MMU_ENABLE);
869
870 /* In smp we use this reg for interrupt 1 scratch */
871#ifndef CONFIG_SMP
872 /* swapper_pg_dir is the pgd for the kernel, used by vmalloc */
873 write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir);
874#endif
875
876 if (pae40_exist_but_not_enab())
877 write_aux_reg(ARC_REG_TLBPD1HI, 0);
878}
879
880/*
881 * TLB Programmer's Model uses Linear Indexes: 0 to {255, 511} for 128 x {2,4}
882 * The mapping is Column-first.
883 * --------------------- -----------
884 * |way0|way1|way2|way3| |way0|way1|
885 * --------------------- -----------
886 * [set0] | 0 | 1 | 2 | 3 | | 0 | 1 |
887 * [set1] | 4 | 5 | 6 | 7 | | 2 | 3 |
888 * ~ ~ ~ ~
889 * [set127] | 508| 509| 510| 511| | 254| 255|
890 * --------------------- -----------
891 * For normal operations we don't(must not) care how above works since
892 * MMU cmd getIndex(vaddr) abstracts that out.
893 * However for walking WAYS of a SET, we need to know this
894 */
895#define SET_WAY_TO_IDX(mmu, set, way) ((set) * mmu->ways + (way))
896
897/* Handling of Duplicate PD (TLB entry) in MMU.
898 * -Could be due to buggy customer tapeouts or obscure kernel bugs
899 * -MMU complaints not at the time of duplicate PD installation, but at the
900 * time of lookup matching multiple ways.
901 * -Ideally these should never happen - but if they do - workaround by deleting
902 * the duplicate one.
903 * -Knob to be verbose abt it.(TODO: hook them up to debugfs)
904 */
905volatile int dup_pd_silent; /* Be slient abt it or complain (default) */
906
907void do_tlb_overlap_fault(unsigned long cause, unsigned long address,
908 struct pt_regs *regs)
909{
910 struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
911 unsigned long flags;
912 int set, n_ways = mmu->ways;
913
914 n_ways = min(n_ways, 4);
915 BUG_ON(mmu->ways > 4);
916
917 local_irq_save(flags);
918
919 /* loop thru all sets of TLB */
920 for (set = 0; set < mmu->sets; set++) {
921
922 int is_valid, way;
923 unsigned int pd0[4];
924
925 /* read out all the ways of current set */
926 for (way = 0, is_valid = 0; way < n_ways; way++) {
927 write_aux_reg(ARC_REG_TLBINDEX,
928 SET_WAY_TO_IDX(mmu, set, way));
929 write_aux_reg(ARC_REG_TLBCOMMAND, TLBRead);
930 pd0[way] = read_aux_reg(ARC_REG_TLBPD0);
931 is_valid |= pd0[way] & _PAGE_PRESENT;
932 pd0[way] &= PAGE_MASK;
933 }
934
935 /* If all the WAYS in SET are empty, skip to next SET */
936 if (!is_valid)
937 continue;
938
939 /* Scan the set for duplicate ways: needs a nested loop */
940 for (way = 0; way < n_ways - 1; way++) {
941
942 int n;
943
944 if (!pd0[way])
945 continue;
946
947 for (n = way + 1; n < n_ways; n++) {
948 if (pd0[way] != pd0[n])
949 continue;
950
951 if (!dup_pd_silent)
952 pr_info("Dup TLB PD0 %08x @ set %d ways %d,%d\n",
953 pd0[way], set, way, n);
954
955 /*
956 * clear entry @way and not @n.
957 * This is critical to our optimised loop
958 */
959 pd0[way] = 0;
960 write_aux_reg(ARC_REG_TLBINDEX,
961 SET_WAY_TO_IDX(mmu, set, way));
962 __tlb_entry_erase();
963 }
964 }
965 }
966
967 local_irq_restore(flags);
968}
969
970/***********************************************************************
971 * Diagnostic Routines
972 * -Called from Low Level TLB Hanlders if things don;t look good
973 **********************************************************************/
974
975#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
976
977/*
978 * Low Level ASM TLB handler calls this if it finds that HW and SW ASIDS
979 * don't match
980 */
981void print_asid_mismatch(int mm_asid, int mmu_asid, int is_fast_path)
982{
983 pr_emerg("ASID Mismatch in %s Path Handler: sw-pid=0x%x hw-pid=0x%x\n",
984 is_fast_path ? "Fast" : "Slow", mm_asid, mmu_asid);
985
986 __asm__ __volatile__("flag 1");
987}
988
989void tlb_paranoid_check(unsigned int mm_asid, unsigned long addr)
990{
991 unsigned int mmu_asid;
992
993 mmu_asid = read_aux_reg(ARC_REG_PID) & 0xff;
994
995 /*
996 * At the time of a TLB miss/installation
997 * - HW version needs to match SW version
998 * - SW needs to have a valid ASID
999 */
1000 if (addr < 0x70000000 &&
1001 ((mm_asid == MM_CTXT_NO_ASID) ||
1002 (mmu_asid != (mm_asid & MM_CTXT_ASID_MASK))))
1003 print_asid_mismatch(mm_asid, mmu_asid, 0);
1004}
1005#endif
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * TLB Management (flush/create/diagnostics) for MMUv3 and MMUv4
4 *
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 *
7 */
8
9#include <linux/module.h>
10#include <linux/bug.h>
11#include <linux/mm_types.h>
12
13#include <asm/arcregs.h>
14#include <asm/setup.h>
15#include <asm/mmu_context.h>
16#include <asm/mmu.h>
17
18/* A copy of the ASID from the PID reg is kept in asid_cache */
19DEFINE_PER_CPU(unsigned int, asid_cache) = MM_CTXT_FIRST_CYCLE;
20
21static struct cpuinfo_arc_mmu {
22 unsigned int ver, pg_sz_k, s_pg_sz_m, pae, sets, ways;
23} mmuinfo;
24
25/*
26 * Utility Routine to erase a J-TLB entry
27 * Caller needs to setup Index Reg (manually or via getIndex)
28 */
29static inline void __tlb_entry_erase(void)
30{
31 write_aux_reg(ARC_REG_TLBPD1, 0);
32
33 if (is_pae40_enabled())
34 write_aux_reg(ARC_REG_TLBPD1HI, 0);
35
36 write_aux_reg(ARC_REG_TLBPD0, 0);
37 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
38}
39
40static void utlb_invalidate(void)
41{
42 write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB);
43}
44
45#ifdef CONFIG_ARC_MMU_V3
46
47static inline unsigned int tlb_entry_lkup(unsigned long vaddr_n_asid)
48{
49 unsigned int idx;
50
51 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid);
52
53 write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe);
54 idx = read_aux_reg(ARC_REG_TLBINDEX);
55
56 return idx;
57}
58
59static void tlb_entry_erase(unsigned int vaddr_n_asid)
60{
61 unsigned int idx;
62
63 /* Locate the TLB entry for this vaddr + ASID */
64 idx = tlb_entry_lkup(vaddr_n_asid);
65
66 /* No error means entry found, zero it out */
67 if (likely(!(idx & TLB_LKUP_ERR))) {
68 __tlb_entry_erase();
69 } else {
70 /* Duplicate entry error */
71 WARN(idx == TLB_DUP_ERR, "Probe returned Dup PD for %x\n",
72 vaddr_n_asid);
73 }
74}
75
76static void tlb_entry_insert(unsigned int pd0, phys_addr_t pd1)
77{
78 unsigned int idx;
79
80 /*
81 * First verify if entry for this vaddr+ASID already exists
82 * This also sets up PD0 (vaddr, ASID..) for final commit
83 */
84 idx = tlb_entry_lkup(pd0);
85
86 /*
87 * If Not already present get a free slot from MMU.
88 * Otherwise, Probe would have located the entry and set INDEX Reg
89 * with existing location. This will cause Write CMD to over-write
90 * existing entry with new PD0 and PD1
91 */
92 if (likely(idx & TLB_LKUP_ERR))
93 write_aux_reg(ARC_REG_TLBCOMMAND, TLBGetIndex);
94
95 /* setup the other half of TLB entry (pfn, rwx..) */
96 write_aux_reg(ARC_REG_TLBPD1, pd1);
97
98 /*
99 * Commit the Entry to MMU
100 * It doesn't sound safe to use the TLBWriteNI cmd here
101 * which doesn't flush uTLBs. I'd rather be safe than sorry.
102 */
103 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
104}
105
106#else /* MMUv4 */
107
108static void tlb_entry_erase(unsigned int vaddr_n_asid)
109{
110 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid | _PAGE_PRESENT);
111 write_aux_reg(ARC_REG_TLBCOMMAND, TLBDeleteEntry);
112}
113
114static void tlb_entry_insert(unsigned int pd0, phys_addr_t pd1)
115{
116 write_aux_reg(ARC_REG_TLBPD0, pd0);
117
118 if (!is_pae40_enabled()) {
119 write_aux_reg(ARC_REG_TLBPD1, pd1);
120 } else {
121 write_aux_reg(ARC_REG_TLBPD1, pd1 & 0xFFFFFFFF);
122 write_aux_reg(ARC_REG_TLBPD1HI, (u64)pd1 >> 32);
123 }
124
125 write_aux_reg(ARC_REG_TLBCOMMAND, TLBInsertEntry);
126}
127
128#endif
129
130/*
131 * Un-conditionally (without lookup) erase the entire MMU contents
132 */
133
134noinline void local_flush_tlb_all(void)
135{
136 struct cpuinfo_arc_mmu *mmu = &mmuinfo;
137 unsigned long flags;
138 unsigned int entry;
139 int num_tlb = mmu->sets * mmu->ways;
140
141 local_irq_save(flags);
142
143 /* Load PD0 and PD1 with template for a Blank Entry */
144 write_aux_reg(ARC_REG_TLBPD1, 0);
145
146 if (is_pae40_enabled())
147 write_aux_reg(ARC_REG_TLBPD1HI, 0);
148
149 write_aux_reg(ARC_REG_TLBPD0, 0);
150
151 for (entry = 0; entry < num_tlb; entry++) {
152 /* write this entry to the TLB */
153 write_aux_reg(ARC_REG_TLBINDEX, entry);
154 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWriteNI);
155 }
156
157 if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE)) {
158 const int stlb_idx = 0x800;
159
160 /* Blank sTLB entry */
161 write_aux_reg(ARC_REG_TLBPD0, _PAGE_HW_SZ);
162
163 for (entry = stlb_idx; entry < stlb_idx + 16; entry++) {
164 write_aux_reg(ARC_REG_TLBINDEX, entry);
165 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWriteNI);
166 }
167 }
168
169 utlb_invalidate();
170
171 local_irq_restore(flags);
172}
173
174/*
175 * Flush the entire MM for userland. The fastest way is to move to Next ASID
176 */
177noinline void local_flush_tlb_mm(struct mm_struct *mm)
178{
179 /*
180 * Small optimisation courtesy IA64
181 * flush_mm called during fork,exit,munmap etc, multiple times as well.
182 * Only for fork( ) do we need to move parent to a new MMU ctxt,
183 * all other cases are NOPs, hence this check.
184 */
185 if (atomic_read(&mm->mm_users) == 0)
186 return;
187
188 /*
189 * - Move to a new ASID, but only if the mm is still wired in
190 * (Android Binder ended up calling this for vma->mm != tsk->mm,
191 * causing h/w - s/w ASID to get out of sync)
192 * - Also get_new_mmu_context() new implementation allocates a new
193 * ASID only if it is not allocated already - so unallocate first
194 */
195 destroy_context(mm);
196 if (current->mm == mm)
197 get_new_mmu_context(mm);
198}
199
200/*
201 * Flush a Range of TLB entries for userland.
202 * @start is inclusive, while @end is exclusive
203 * Difference between this and Kernel Range Flush is
204 * -Here the fastest way (if range is too large) is to move to next ASID
205 * without doing any explicit Shootdown
206 * -In case of kernel Flush, entry has to be shot down explicitly
207 */
208void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
209 unsigned long end)
210{
211 const unsigned int cpu = smp_processor_id();
212 unsigned long flags;
213
214 /* If range @start to @end is more than 32 TLB entries deep,
215 * it's better to move to a new ASID rather than searching for
216 * individual entries and then shooting them down
217 *
218 * The calc above is rough, doesn't account for unaligned parts,
219 * since this is heuristics based anyways
220 */
221 if (unlikely((end - start) >= PAGE_SIZE * 32)) {
222 local_flush_tlb_mm(vma->vm_mm);
223 return;
224 }
225
226 /*
227 * @start moved to page start: this alone suffices for checking
228 * loop end condition below, w/o need for aligning @end to end
229 * e.g. 2000 to 4001 will anyhow loop twice
230 */
231 start &= PAGE_MASK;
232
233 local_irq_save(flags);
234
235 if (asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID) {
236 while (start < end) {
237 tlb_entry_erase(start | hw_pid(vma->vm_mm, cpu));
238 start += PAGE_SIZE;
239 }
240 }
241
242 local_irq_restore(flags);
243}
244
245/* Flush the kernel TLB entries - vmalloc/modules (Global from MMU perspective)
246 * @start, @end interpreted as kvaddr
247 * Interestingly, shared TLB entries can also be flushed using just
248 * @start,@end alone (interpreted as user vaddr), although technically SASID
249 * is also needed. However our smart TLbProbe lookup takes care of that.
250 */
251void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
252{
253 unsigned long flags;
254
255 /* exactly same as above, except for TLB entry not taking ASID */
256
257 if (unlikely((end - start) >= PAGE_SIZE * 32)) {
258 local_flush_tlb_all();
259 return;
260 }
261
262 start &= PAGE_MASK;
263
264 local_irq_save(flags);
265 while (start < end) {
266 tlb_entry_erase(start);
267 start += PAGE_SIZE;
268 }
269
270 local_irq_restore(flags);
271}
272
273/*
274 * Delete TLB entry in MMU for a given page (??? address)
275 * NOTE One TLB entry contains translation for single PAGE
276 */
277
278void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
279{
280 const unsigned int cpu = smp_processor_id();
281 unsigned long flags;
282
283 /* Note that it is critical that interrupts are DISABLED between
284 * checking the ASID and using it flush the TLB entry
285 */
286 local_irq_save(flags);
287
288 if (asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID) {
289 tlb_entry_erase((page & PAGE_MASK) | hw_pid(vma->vm_mm, cpu));
290 }
291
292 local_irq_restore(flags);
293}
294
295#ifdef CONFIG_SMP
296
297struct tlb_args {
298 struct vm_area_struct *ta_vma;
299 unsigned long ta_start;
300 unsigned long ta_end;
301};
302
303static inline void ipi_flush_tlb_page(void *arg)
304{
305 struct tlb_args *ta = arg;
306
307 local_flush_tlb_page(ta->ta_vma, ta->ta_start);
308}
309
310static inline void ipi_flush_tlb_range(void *arg)
311{
312 struct tlb_args *ta = arg;
313
314 local_flush_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
315}
316
317#ifdef CONFIG_TRANSPARENT_HUGEPAGE
318static inline void ipi_flush_pmd_tlb_range(void *arg)
319{
320 struct tlb_args *ta = arg;
321
322 local_flush_pmd_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
323}
324#endif
325
326static inline void ipi_flush_tlb_kernel_range(void *arg)
327{
328 struct tlb_args *ta = (struct tlb_args *)arg;
329
330 local_flush_tlb_kernel_range(ta->ta_start, ta->ta_end);
331}
332
333void flush_tlb_all(void)
334{
335 on_each_cpu((smp_call_func_t)local_flush_tlb_all, NULL, 1);
336}
337
338void flush_tlb_mm(struct mm_struct *mm)
339{
340 on_each_cpu_mask(mm_cpumask(mm), (smp_call_func_t)local_flush_tlb_mm,
341 mm, 1);
342}
343
344void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
345{
346 struct tlb_args ta = {
347 .ta_vma = vma,
348 .ta_start = uaddr
349 };
350
351 on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_page, &ta, 1);
352}
353
354void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
355 unsigned long end)
356{
357 struct tlb_args ta = {
358 .ta_vma = vma,
359 .ta_start = start,
360 .ta_end = end
361 };
362
363 on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_range, &ta, 1);
364}
365
366#ifdef CONFIG_TRANSPARENT_HUGEPAGE
367void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
368 unsigned long end)
369{
370 struct tlb_args ta = {
371 .ta_vma = vma,
372 .ta_start = start,
373 .ta_end = end
374 };
375
376 on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_pmd_tlb_range, &ta, 1);
377}
378#endif
379
380void flush_tlb_kernel_range(unsigned long start, unsigned long end)
381{
382 struct tlb_args ta = {
383 .ta_start = start,
384 .ta_end = end
385 };
386
387 on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
388}
389#endif
390
391/*
392 * Routine to create a TLB entry
393 */
394static void create_tlb(struct vm_area_struct *vma, unsigned long vaddr, pte_t *ptep)
395{
396 unsigned long flags;
397 unsigned int asid_or_sasid, rwx;
398 unsigned long pd0;
399 phys_addr_t pd1;
400
401 /*
402 * create_tlb() assumes that current->mm == vma->mm, since
403 * -it ASID for TLB entry is fetched from MMU ASID reg (valid for curr)
404 * -completes the lazy write to SASID reg (again valid for curr tsk)
405 *
406 * Removing the assumption involves
407 * -Using vma->mm->context{ASID,SASID}, as opposed to MMU reg.
408 * -More importantly it makes this handler inconsistent with fast-path
409 * TLB Refill handler which always deals with "current"
410 *
411 * Let's see the use cases when current->mm != vma->mm and we land here
412 * 1. execve->copy_strings()->__get_user_pages->handle_mm_fault
413 * Here VM wants to pre-install a TLB entry for user stack while
414 * current->mm still points to pre-execve mm (hence the condition).
415 * However the stack vaddr is soon relocated (randomization) and
416 * move_page_tables() tries to undo that TLB entry.
417 * Thus not creating TLB entry is not any worse.
418 *
419 * 2. ptrace(POKETEXT) causes a CoW - debugger(current) inserting a
420 * breakpoint in debugged task. Not creating a TLB now is not
421 * performance critical.
422 *
423 * Both the cases above are not good enough for code churn.
424 */
425 if (current->active_mm != vma->vm_mm)
426 return;
427
428 local_irq_save(flags);
429
430 vaddr &= PAGE_MASK;
431
432 /* update this PTE credentials */
433 pte_val(*ptep) |= (_PAGE_PRESENT | _PAGE_ACCESSED);
434
435 /* Create HW TLB(PD0,PD1) from PTE */
436
437 /* ASID for this task */
438 asid_or_sasid = read_aux_reg(ARC_REG_PID) & 0xff;
439
440 pd0 = vaddr | asid_or_sasid | (pte_val(*ptep) & PTE_BITS_IN_PD0);
441
442 /*
443 * ARC MMU provides fully orthogonal access bits for K/U mode,
444 * however Linux only saves 1 set to save PTE real-estate
445 * Here we convert 3 PTE bits into 6 MMU bits:
446 * -Kernel only entries have Kr Kw Kx 0 0 0
447 * -User entries have mirrored K and U bits
448 */
449 rwx = pte_val(*ptep) & PTE_BITS_RWX;
450
451 if (pte_val(*ptep) & _PAGE_GLOBAL)
452 rwx <<= 3; /* r w x => Kr Kw Kx 0 0 0 */
453 else
454 rwx |= (rwx << 3); /* r w x => Kr Kw Kx Ur Uw Ux */
455
456 pd1 = rwx | (pte_val(*ptep) & PTE_BITS_NON_RWX_IN_PD1);
457
458 tlb_entry_insert(pd0, pd1);
459
460 local_irq_restore(flags);
461}
462
463/*
464 * Called at the end of pagefault, for a userspace mapped page
465 * -pre-install the corresponding TLB entry into MMU
466 * -Finalize the delayed D-cache flush of kernel mapping of page due to
467 * flush_dcache_page(), copy_user_page()
468 *
469 * Note that flush (when done) involves both WBACK - so physical page is
470 * in sync as well as INV - so any non-congruent aliases don't remain
471 */
472void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma,
473 unsigned long vaddr_unaligned, pte_t *ptep, unsigned int nr)
474{
475 unsigned long vaddr = vaddr_unaligned & PAGE_MASK;
476 phys_addr_t paddr = pte_val(*ptep) & PAGE_MASK_PHYS;
477 struct page *page = pfn_to_page(pte_pfn(*ptep));
478
479 create_tlb(vma, vaddr, ptep);
480
481 if (page == ZERO_PAGE(0))
482 return;
483
484 /*
485 * For executable pages, since icache doesn't snoop dcache, any
486 * dirty K-mapping of a code page needs to be wback+inv so that
487 * icache fetch by userspace sees code correctly.
488 */
489 if (vma->vm_flags & VM_EXEC) {
490 struct folio *folio = page_folio(page);
491 int dirty = !test_and_set_bit(PG_dc_clean, &folio->flags);
492 if (dirty) {
493 unsigned long offset = offset_in_folio(folio, paddr);
494 nr = folio_nr_pages(folio);
495 paddr -= offset;
496 vaddr -= offset;
497 /* wback + inv dcache lines (K-mapping) */
498 __flush_dcache_pages(paddr, paddr, nr);
499
500 /* invalidate any existing icache lines (U-mapping) */
501 if (vma->vm_flags & VM_EXEC)
502 __inv_icache_pages(paddr, vaddr, nr);
503 }
504 }
505}
506
507#ifdef CONFIG_TRANSPARENT_HUGEPAGE
508
509/*
510 * MMUv4 in HS38x cores supports Super Pages which are basis for Linux THP
511 * support.
512 *
513 * Normal and Super pages can co-exist (ofcourse not overlap) in TLB with a
514 * new bit "SZ" in TLB page descriptor to distinguish between them.
515 * Super Page size is configurable in hardware (4K to 16M), but fixed once
516 * RTL builds.
517 *
518 * The exact THP size a Linux configuration will support is a function of:
519 * - MMU page size (typical 8K, RTL fixed)
520 * - software page walker address split between PGD:PTE:PFN (typical
521 * 11:8:13, but can be changed with 1 line)
522 * So for above default, THP size supported is 8K * (2^8) = 2M
523 *
524 * Default Page Walker is 2 levels, PGD:PTE:PFN, which in THP regime
525 * reduces to 1 level (as PTE is folded into PGD and canonically referred
526 * to as PMD).
527 * Thus THP PMD accessors are implemented in terms of PTE (just like sparc)
528 */
529
530void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
531 pmd_t *pmd)
532{
533 pte_t pte = __pte(pmd_val(*pmd));
534 update_mmu_cache_range(NULL, vma, addr, &pte, HPAGE_PMD_NR);
535}
536
537void local_flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
538 unsigned long end)
539{
540 unsigned int cpu;
541 unsigned long flags;
542
543 local_irq_save(flags);
544
545 cpu = smp_processor_id();
546
547 if (likely(asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID)) {
548 unsigned int asid = hw_pid(vma->vm_mm, cpu);
549
550 /* No need to loop here: this will always be for 1 Huge Page */
551 tlb_entry_erase(start | _PAGE_HW_SZ | asid);
552 }
553
554 local_irq_restore(flags);
555}
556
557#endif
558
559/* Read the Cache Build Configuration Registers, Decode them and save into
560 * the cpuinfo structure for later use.
561 * No Validation is done here, simply read/convert the BCRs
562 */
563int arc_mmu_mumbojumbo(int c, char *buf, int len)
564{
565 struct cpuinfo_arc_mmu *mmu = &mmuinfo;
566 unsigned int bcr, u_dtlb, u_itlb, sasid;
567 struct bcr_mmu_3 *mmu3;
568 struct bcr_mmu_4 *mmu4;
569 char super_pg[64] = "";
570 int n = 0;
571
572 bcr = read_aux_reg(ARC_REG_MMU_BCR);
573 mmu->ver = (bcr >> 24);
574
575 if (is_isa_arcompact() && mmu->ver == 3) {
576 mmu3 = (struct bcr_mmu_3 *)&bcr;
577 mmu->pg_sz_k = 1 << (mmu3->pg_sz - 1);
578 mmu->sets = 1 << mmu3->sets;
579 mmu->ways = 1 << mmu3->ways;
580 u_dtlb = mmu3->u_dtlb;
581 u_itlb = mmu3->u_itlb;
582 sasid = mmu3->sasid;
583 } else {
584 mmu4 = (struct bcr_mmu_4 *)&bcr;
585 mmu->pg_sz_k = 1 << (mmu4->sz0 - 1);
586 mmu->s_pg_sz_m = 1 << (mmu4->sz1 - 11);
587 mmu->sets = 64 << mmu4->n_entry;
588 mmu->ways = mmu4->n_ways * 2;
589 u_dtlb = mmu4->u_dtlb * 4;
590 u_itlb = mmu4->u_itlb * 4;
591 sasid = mmu4->sasid;
592 mmu->pae = mmu4->pae;
593 }
594
595 if (mmu->s_pg_sz_m)
596 scnprintf(super_pg, 64, "/%dM%s",
597 mmu->s_pg_sz_m,
598 IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE) ? " (THP enabled)":"");
599
600 n += scnprintf(buf + n, len - n,
601 "MMU [v%x]\t: %dk%s, swalk %d lvl, JTLB %dx%d, uDTLB %d, uITLB %d%s%s%s\n",
602 mmu->ver, mmu->pg_sz_k, super_pg, CONFIG_PGTABLE_LEVELS,
603 mmu->sets, mmu->ways,
604 u_dtlb, u_itlb,
605 IS_AVAIL1(sasid, ", SASID"),
606 IS_AVAIL2(mmu->pae, ", PAE40 ", CONFIG_ARC_HAS_PAE40));
607
608 return n;
609}
610
611int pae40_exist_but_not_enab(void)
612{
613 return mmuinfo.pae && !is_pae40_enabled();
614}
615
616void arc_mmu_init(void)
617{
618 struct cpuinfo_arc_mmu *mmu = &mmuinfo;
619 int compat = 0;
620
621 /*
622 * Can't be done in processor.h due to header include dependencies
623 */
624 BUILD_BUG_ON(!IS_ALIGNED((CONFIG_ARC_KVADDR_SIZE << 20), PMD_SIZE));
625
626 /*
627 * stack top size sanity check,
628 * Can't be done in processor.h due to header include dependencies
629 */
630 BUILD_BUG_ON(!IS_ALIGNED(STACK_TOP, PMD_SIZE));
631
632 /*
633 * Ensure that MMU features assumed by kernel exist in hardware.
634 * - For older ARC700 cpus, only v3 supported
635 * - For HS cpus, v4 was baseline and v5 is backwards compatible
636 * (will run older software).
637 */
638 if (is_isa_arcompact() && mmu->ver == 3)
639 compat = 1;
640 else if (is_isa_arcv2() && mmu->ver >= 4)
641 compat = 1;
642
643 if (!compat)
644 panic("MMU ver %d doesn't match kernel built for\n", mmu->ver);
645
646 if (mmu->pg_sz_k != TO_KB(PAGE_SIZE))
647 panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE));
648
649 if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE) &&
650 mmu->s_pg_sz_m != TO_MB(HPAGE_PMD_SIZE))
651 panic("MMU Super pg size != Linux HPAGE_PMD_SIZE (%luM)\n",
652 (unsigned long)TO_MB(HPAGE_PMD_SIZE));
653
654 if (IS_ENABLED(CONFIG_ARC_HAS_PAE40) && !mmu->pae)
655 panic("Hardware doesn't support PAE40\n");
656
657 /* Enable the MMU with ASID 0 */
658 mmu_setup_asid(NULL, 0);
659
660 /* cache the pgd pointer in MMU SCRATCH reg (ARCv2 only) */
661 mmu_setup_pgd(NULL, swapper_pg_dir);
662
663 if (pae40_exist_but_not_enab())
664 write_aux_reg(ARC_REG_TLBPD1HI, 0);
665}
666
667/*
668 * TLB Programmer's Model uses Linear Indexes: 0 to {255, 511} for 128 x {2,4}
669 * The mapping is Column-first.
670 * --------------------- -----------
671 * |way0|way1|way2|way3| |way0|way1|
672 * --------------------- -----------
673 * [set0] | 0 | 1 | 2 | 3 | | 0 | 1 |
674 * [set1] | 4 | 5 | 6 | 7 | | 2 | 3 |
675 * ~ ~ ~ ~
676 * [set127] | 508| 509| 510| 511| | 254| 255|
677 * --------------------- -----------
678 * For normal operations we don't(must not) care how above works since
679 * MMU cmd getIndex(vaddr) abstracts that out.
680 * However for walking WAYS of a SET, we need to know this
681 */
682#define SET_WAY_TO_IDX(mmu, set, way) ((set) * mmu->ways + (way))
683
684/* Handling of Duplicate PD (TLB entry) in MMU.
685 * -Could be due to buggy customer tapeouts or obscure kernel bugs
686 * -MMU complaints not at the time of duplicate PD installation, but at the
687 * time of lookup matching multiple ways.
688 * -Ideally these should never happen - but if they do - workaround by deleting
689 * the duplicate one.
690 * -Knob to be verbose abt it.(TODO: hook them up to debugfs)
691 */
692volatile int dup_pd_silent; /* Be silent abt it or complain (default) */
693
694void do_tlb_overlap_fault(unsigned long cause, unsigned long address,
695 struct pt_regs *regs)
696{
697 struct cpuinfo_arc_mmu *mmu = &mmuinfo;
698 unsigned long flags;
699 int set, n_ways = mmu->ways;
700
701 n_ways = min(n_ways, 4);
702 BUG_ON(mmu->ways > 4);
703
704 local_irq_save(flags);
705
706 /* loop thru all sets of TLB */
707 for (set = 0; set < mmu->sets; set++) {
708
709 int is_valid, way;
710 unsigned int pd0[4];
711
712 /* read out all the ways of current set */
713 for (way = 0, is_valid = 0; way < n_ways; way++) {
714 write_aux_reg(ARC_REG_TLBINDEX,
715 SET_WAY_TO_IDX(mmu, set, way));
716 write_aux_reg(ARC_REG_TLBCOMMAND, TLBRead);
717 pd0[way] = read_aux_reg(ARC_REG_TLBPD0);
718 is_valid |= pd0[way] & _PAGE_PRESENT;
719 pd0[way] &= PAGE_MASK;
720 }
721
722 /* If all the WAYS in SET are empty, skip to next SET */
723 if (!is_valid)
724 continue;
725
726 /* Scan the set for duplicate ways: needs a nested loop */
727 for (way = 0; way < n_ways - 1; way++) {
728
729 int n;
730
731 if (!pd0[way])
732 continue;
733
734 for (n = way + 1; n < n_ways; n++) {
735 if (pd0[way] != pd0[n])
736 continue;
737
738 if (!dup_pd_silent)
739 pr_info("Dup TLB PD0 %08x @ set %d ways %d,%d\n",
740 pd0[way], set, way, n);
741
742 /*
743 * clear entry @way and not @n.
744 * This is critical to our optimised loop
745 */
746 pd0[way] = 0;
747 write_aux_reg(ARC_REG_TLBINDEX,
748 SET_WAY_TO_IDX(mmu, set, way));
749 __tlb_entry_erase();
750 }
751 }
752 }
753
754 local_irq_restore(flags);
755}