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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 Broadcom
4 */
5
6/**
7 * DOC: VC4 CRTC module
8 *
9 * In VC4, the Pixel Valve is what most closely corresponds to the
10 * DRM's concept of a CRTC. The PV generates video timings from the
11 * encoder's clock plus its configuration. It pulls scaled pixels from
12 * the HVS at that timing, and feeds it to the encoder.
13 *
14 * However, the DRM CRTC also collects the configuration of all the
15 * DRM planes attached to it. As a result, the CRTC is also
16 * responsible for writing the display list for the HVS channel that
17 * the CRTC will use.
18 *
19 * The 2835 has 3 different pixel valves. pv0 in the audio power
20 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
21 * image domain can feed either HDMI or the SDTV controller. The
22 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
23 * SDTV, etc.) according to which output type is chosen in the mux.
24 *
25 * For power management, the pixel valve's registers are all clocked
26 * by the AXI clock, while the timings and FIFOs make use of the
27 * output-specific clock. Since the encoders also directly consume
28 * the CPRMAN clocks, and know what timings they need, they are the
29 * ones that set the clock.
30 */
31
32#include <linux/clk.h>
33#include <linux/component.h>
34#include <linux/of_device.h>
35
36#include <drm/drm_atomic.h>
37#include <drm/drm_atomic_helper.h>
38#include <drm/drm_atomic_uapi.h>
39#include <drm/drm_fb_cma_helper.h>
40#include <drm/drm_print.h>
41#include <drm/drm_probe_helper.h>
42#include <drm/drm_vblank.h>
43
44#include "vc4_drv.h"
45#include "vc4_regs.h"
46
47struct vc4_crtc_state {
48 struct drm_crtc_state base;
49 /* Dlist area for this CRTC configuration. */
50 struct drm_mm_node mm;
51 bool feed_txp;
52 bool txp_armed;
53
54 struct {
55 unsigned int left;
56 unsigned int right;
57 unsigned int top;
58 unsigned int bottom;
59 } margins;
60};
61
62static inline struct vc4_crtc_state *
63to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
64{
65 return (struct vc4_crtc_state *)crtc_state;
66}
67
68#define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
69#define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
70
71static const struct debugfs_reg32 crtc_regs[] = {
72 VC4_REG32(PV_CONTROL),
73 VC4_REG32(PV_V_CONTROL),
74 VC4_REG32(PV_VSYNCD_EVEN),
75 VC4_REG32(PV_HORZA),
76 VC4_REG32(PV_HORZB),
77 VC4_REG32(PV_VERTA),
78 VC4_REG32(PV_VERTB),
79 VC4_REG32(PV_VERTA_EVEN),
80 VC4_REG32(PV_VERTB_EVEN),
81 VC4_REG32(PV_INTEN),
82 VC4_REG32(PV_INTSTAT),
83 VC4_REG32(PV_STAT),
84 VC4_REG32(PV_HACT_ACT),
85};
86
87bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
88 bool in_vblank_irq, int *vpos, int *hpos,
89 ktime_t *stime, ktime_t *etime,
90 const struct drm_display_mode *mode)
91{
92 struct vc4_dev *vc4 = to_vc4_dev(dev);
93 struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
94 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
95 u32 val;
96 int fifo_lines;
97 int vblank_lines;
98 bool ret = false;
99
100 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
101
102 /* Get optional system timestamp before query. */
103 if (stime)
104 *stime = ktime_get();
105
106 /*
107 * Read vertical scanline which is currently composed for our
108 * pixelvalve by the HVS, and also the scaler status.
109 */
110 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
111
112 /* Get optional system timestamp after query. */
113 if (etime)
114 *etime = ktime_get();
115
116 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
117
118 /* Vertical position of hvs composed scanline. */
119 *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
120 *hpos = 0;
121
122 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
123 *vpos /= 2;
124
125 /* Use hpos to correct for field offset in interlaced mode. */
126 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
127 *hpos += mode->crtc_htotal / 2;
128 }
129
130 /* This is the offset we need for translating hvs -> pv scanout pos. */
131 fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
132
133 if (fifo_lines > 0)
134 ret = true;
135
136 /* HVS more than fifo_lines into frame for compositing? */
137 if (*vpos > fifo_lines) {
138 /*
139 * We are in active scanout and can get some meaningful results
140 * from HVS. The actual PV scanout can not trail behind more
141 * than fifo_lines as that is the fifo's capacity. Assume that
142 * in active scanout the HVS and PV work in lockstep wrt. HVS
143 * refilling the fifo and PV consuming from the fifo, ie.
144 * whenever the PV consumes and frees up a scanline in the
145 * fifo, the HVS will immediately refill it, therefore
146 * incrementing vpos. Therefore we choose HVS read position -
147 * fifo size in scanlines as a estimate of the real scanout
148 * position of the PV.
149 */
150 *vpos -= fifo_lines + 1;
151
152 return ret;
153 }
154
155 /*
156 * Less: This happens when we are in vblank and the HVS, after getting
157 * the VSTART restart signal from the PV, just started refilling its
158 * fifo with new lines from the top-most lines of the new framebuffers.
159 * The PV does not scan out in vblank, so does not remove lines from
160 * the fifo, so the fifo will be full quickly and the HVS has to pause.
161 * We can't get meaningful readings wrt. scanline position of the PV
162 * and need to make things up in a approximative but consistent way.
163 */
164 vblank_lines = mode->vtotal - mode->vdisplay;
165
166 if (in_vblank_irq) {
167 /*
168 * Assume the irq handler got called close to first
169 * line of vblank, so PV has about a full vblank
170 * scanlines to go, and as a base timestamp use the
171 * one taken at entry into vblank irq handler, so it
172 * is not affected by random delays due to lock
173 * contention on event_lock or vblank_time lock in
174 * the core.
175 */
176 *vpos = -vblank_lines;
177
178 if (stime)
179 *stime = vc4_crtc->t_vblank;
180 if (etime)
181 *etime = vc4_crtc->t_vblank;
182
183 /*
184 * If the HVS fifo is not yet full then we know for certain
185 * we are at the very beginning of vblank, as the hvs just
186 * started refilling, and the stime and etime timestamps
187 * truly correspond to start of vblank.
188 *
189 * Unfortunately there's no way to report this to upper levels
190 * and make it more useful.
191 */
192 } else {
193 /*
194 * No clue where we are inside vblank. Return a vpos of zero,
195 * which will cause calling code to just return the etime
196 * timestamp uncorrected. At least this is no worse than the
197 * standard fallback.
198 */
199 *vpos = 0;
200 }
201
202 return ret;
203}
204
205static void vc4_crtc_destroy(struct drm_crtc *crtc)
206{
207 drm_crtc_cleanup(crtc);
208}
209
210static void
211vc4_crtc_lut_load(struct drm_crtc *crtc)
212{
213 struct drm_device *dev = crtc->dev;
214 struct vc4_dev *vc4 = to_vc4_dev(dev);
215 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
216 u32 i;
217
218 /* The LUT memory is laid out with each HVS channel in order,
219 * each of which takes 256 writes for R, 256 for G, then 256
220 * for B.
221 */
222 HVS_WRITE(SCALER_GAMADDR,
223 SCALER_GAMADDR_AUTOINC |
224 (vc4_crtc->channel * 3 * crtc->gamma_size));
225
226 for (i = 0; i < crtc->gamma_size; i++)
227 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
228 for (i = 0; i < crtc->gamma_size; i++)
229 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
230 for (i = 0; i < crtc->gamma_size; i++)
231 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
232}
233
234static void
235vc4_crtc_update_gamma_lut(struct drm_crtc *crtc)
236{
237 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
238 struct drm_color_lut *lut = crtc->state->gamma_lut->data;
239 u32 length = drm_color_lut_size(crtc->state->gamma_lut);
240 u32 i;
241
242 for (i = 0; i < length; i++) {
243 vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8);
244 vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8);
245 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8);
246 }
247
248 vc4_crtc_lut_load(crtc);
249}
250
251static u32 vc4_get_fifo_full_level(u32 format)
252{
253 static const u32 fifo_len_bytes = 64;
254 static const u32 hvs_latency_pix = 6;
255
256 switch (format) {
257 case PV_CONTROL_FORMAT_DSIV_16:
258 case PV_CONTROL_FORMAT_DSIC_16:
259 return fifo_len_bytes - 2 * hvs_latency_pix;
260 case PV_CONTROL_FORMAT_DSIV_18:
261 return fifo_len_bytes - 14;
262 case PV_CONTROL_FORMAT_24:
263 case PV_CONTROL_FORMAT_DSIV_24:
264 default:
265 return fifo_len_bytes - 3 * hvs_latency_pix;
266 }
267}
268
269/*
270 * Returns the encoder attached to the CRTC.
271 *
272 * VC4 can only scan out to one encoder at a time, while the DRM core
273 * allows drivers to push pixels to more than one encoder from the
274 * same CRTC.
275 */
276static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
277{
278 struct drm_connector *connector;
279 struct drm_connector_list_iter conn_iter;
280
281 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
282 drm_for_each_connector_iter(connector, &conn_iter) {
283 if (connector->state->crtc == crtc) {
284 drm_connector_list_iter_end(&conn_iter);
285 return connector->encoder;
286 }
287 }
288 drm_connector_list_iter_end(&conn_iter);
289
290 return NULL;
291}
292
293static void vc4_crtc_config_pv(struct drm_crtc *crtc)
294{
295 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
296 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
297 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
298 struct drm_crtc_state *state = crtc->state;
299 struct drm_display_mode *mode = &state->adjusted_mode;
300 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
301 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
302 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
303 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
304 u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
305
306 /* Reset the PV fifo. */
307 CRTC_WRITE(PV_CONTROL, 0);
308 CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
309 CRTC_WRITE(PV_CONTROL, 0);
310
311 CRTC_WRITE(PV_HORZA,
312 VC4_SET_FIELD((mode->htotal -
313 mode->hsync_end) * pixel_rep,
314 PV_HORZA_HBP) |
315 VC4_SET_FIELD((mode->hsync_end -
316 mode->hsync_start) * pixel_rep,
317 PV_HORZA_HSYNC));
318 CRTC_WRITE(PV_HORZB,
319 VC4_SET_FIELD((mode->hsync_start -
320 mode->hdisplay) * pixel_rep,
321 PV_HORZB_HFP) |
322 VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
323
324 CRTC_WRITE(PV_VERTA,
325 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
326 PV_VERTA_VBP) |
327 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
328 PV_VERTA_VSYNC));
329 CRTC_WRITE(PV_VERTB,
330 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
331 PV_VERTB_VFP) |
332 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
333
334 if (interlace) {
335 CRTC_WRITE(PV_VERTA_EVEN,
336 VC4_SET_FIELD(mode->crtc_vtotal -
337 mode->crtc_vsync_end - 1,
338 PV_VERTA_VBP) |
339 VC4_SET_FIELD(mode->crtc_vsync_end -
340 mode->crtc_vsync_start,
341 PV_VERTA_VSYNC));
342 CRTC_WRITE(PV_VERTB_EVEN,
343 VC4_SET_FIELD(mode->crtc_vsync_start -
344 mode->crtc_vdisplay,
345 PV_VERTB_VFP) |
346 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
347
348 /* We set up first field even mode for HDMI. VEC's
349 * NTSC mode would want first field odd instead, once
350 * we support it (to do so, set ODD_FIRST and put the
351 * delay in VSYNCD_EVEN instead).
352 */
353 CRTC_WRITE(PV_V_CONTROL,
354 PV_VCONTROL_CONTINUOUS |
355 (is_dsi ? PV_VCONTROL_DSI : 0) |
356 PV_VCONTROL_INTERLACE |
357 VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
358 PV_VCONTROL_ODD_DELAY));
359 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
360 } else {
361 CRTC_WRITE(PV_V_CONTROL,
362 PV_VCONTROL_CONTINUOUS |
363 (is_dsi ? PV_VCONTROL_DSI : 0));
364 }
365
366 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
367
368 CRTC_WRITE(PV_CONTROL,
369 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
370 VC4_SET_FIELD(vc4_get_fifo_full_level(format),
371 PV_CONTROL_FIFO_LEVEL) |
372 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
373 PV_CONTROL_CLR_AT_START |
374 PV_CONTROL_TRIGGER_UNDERFLOW |
375 PV_CONTROL_WAIT_HSTART |
376 VC4_SET_FIELD(vc4_encoder->clock_select,
377 PV_CONTROL_CLK_SELECT) |
378 PV_CONTROL_FIFO_CLR |
379 PV_CONTROL_EN);
380}
381
382static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
383{
384 struct drm_device *dev = crtc->dev;
385 struct vc4_dev *vc4 = to_vc4_dev(dev);
386 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
387 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
388 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
389 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
390 bool debug_dump_regs = false;
391
392 if (debug_dump_regs) {
393 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
394 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",
395 drm_crtc_index(crtc));
396 drm_print_regset32(&p, &vc4_crtc->regset);
397 }
398
399 if (vc4_crtc->channel == 2) {
400 u32 dispctrl;
401 u32 dsp3_mux;
402
403 /*
404 * SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
405 * FIFO X'.
406 * SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
407 *
408 * DSP3 is connected to FIFO2 unless the transposer is
409 * enabled. In this case, FIFO 2 is directly accessed by the
410 * TXP IP, and we need to disable the FIFO2 -> pixelvalve1
411 * route.
412 */
413 if (vc4_state->feed_txp)
414 dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
415 else
416 dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
417
418 dispctrl = HVS_READ(SCALER_DISPCTRL) &
419 ~SCALER_DISPCTRL_DSP3_MUX_MASK;
420 HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
421 }
422
423 if (!vc4_state->feed_txp)
424 vc4_crtc_config_pv(crtc);
425
426 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
427 SCALER_DISPBKGND_AUTOHS |
428 SCALER_DISPBKGND_GAMMA |
429 (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
430
431 /* Reload the LUT, since the SRAMs would have been disabled if
432 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
433 */
434 vc4_crtc_lut_load(crtc);
435
436 if (debug_dump_regs) {
437 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
438 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",
439 drm_crtc_index(crtc));
440 drm_print_regset32(&p, &vc4_crtc->regset);
441 }
442}
443
444static void require_hvs_enabled(struct drm_device *dev)
445{
446 struct vc4_dev *vc4 = to_vc4_dev(dev);
447
448 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
449 SCALER_DISPCTRL_ENABLE);
450}
451
452static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
453 struct drm_crtc_state *old_state)
454{
455 struct drm_device *dev = crtc->dev;
456 struct vc4_dev *vc4 = to_vc4_dev(dev);
457 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
458 u32 chan = vc4_crtc->channel;
459 int ret;
460 require_hvs_enabled(dev);
461
462 /* Disable vblank irq handling before crtc is disabled. */
463 drm_crtc_vblank_off(crtc);
464
465 CRTC_WRITE(PV_V_CONTROL,
466 CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
467 ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
468 WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
469
470 if (HVS_READ(SCALER_DISPCTRLX(chan)) &
471 SCALER_DISPCTRLX_ENABLE) {
472 HVS_WRITE(SCALER_DISPCTRLX(chan),
473 SCALER_DISPCTRLX_RESET);
474
475 /* While the docs say that reset is self-clearing, it
476 * seems it doesn't actually.
477 */
478 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
479 }
480
481 /* Once we leave, the scaler should be disabled and its fifo empty. */
482
483 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
484
485 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
486 SCALER_DISPSTATX_MODE) !=
487 SCALER_DISPSTATX_MODE_DISABLED);
488
489 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
490 (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
491 SCALER_DISPSTATX_EMPTY);
492
493 /*
494 * Make sure we issue a vblank event after disabling the CRTC if
495 * someone was waiting it.
496 */
497 if (crtc->state->event) {
498 unsigned long flags;
499
500 spin_lock_irqsave(&dev->event_lock, flags);
501 drm_crtc_send_vblank_event(crtc, crtc->state->event);
502 crtc->state->event = NULL;
503 spin_unlock_irqrestore(&dev->event_lock, flags);
504 }
505}
506
507void vc4_crtc_txp_armed(struct drm_crtc_state *state)
508{
509 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
510
511 vc4_state->txp_armed = true;
512}
513
514static void vc4_crtc_update_dlist(struct drm_crtc *crtc)
515{
516 struct drm_device *dev = crtc->dev;
517 struct vc4_dev *vc4 = to_vc4_dev(dev);
518 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
519 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
520
521 if (crtc->state->event) {
522 unsigned long flags;
523
524 crtc->state->event->pipe = drm_crtc_index(crtc);
525
526 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
527
528 spin_lock_irqsave(&dev->event_lock, flags);
529
530 if (!vc4_state->feed_txp || vc4_state->txp_armed) {
531 vc4_crtc->event = crtc->state->event;
532 crtc->state->event = NULL;
533 }
534
535 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
536 vc4_state->mm.start);
537
538 spin_unlock_irqrestore(&dev->event_lock, flags);
539 } else {
540 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
541 vc4_state->mm.start);
542 }
543}
544
545static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
546 struct drm_crtc_state *old_state)
547{
548 struct drm_device *dev = crtc->dev;
549 struct vc4_dev *vc4 = to_vc4_dev(dev);
550 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
551 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
552 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
553
554 require_hvs_enabled(dev);
555
556 /* Enable vblank irq handling before crtc is started otherwise
557 * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
558 */
559 drm_crtc_vblank_on(crtc);
560 vc4_crtc_update_dlist(crtc);
561
562 /* Turn on the scaler, which will wait for vstart to start
563 * compositing.
564 * When feeding the transposer, we should operate in oneshot
565 * mode.
566 */
567 HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
568 VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
569 VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
570 SCALER_DISPCTRLX_ENABLE |
571 (vc4_state->feed_txp ? SCALER_DISPCTRLX_ONESHOT : 0));
572
573 /* When feeding the transposer block the pixelvalve is unneeded and
574 * should not be enabled.
575 */
576 if (!vc4_state->feed_txp)
577 CRTC_WRITE(PV_V_CONTROL,
578 CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
579}
580
581static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
582 const struct drm_display_mode *mode)
583{
584 /* Do not allow doublescan modes from user space */
585 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
586 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
587 crtc->base.id);
588 return MODE_NO_DBLESCAN;
589 }
590
591 return MODE_OK;
592}
593
594void vc4_crtc_get_margins(struct drm_crtc_state *state,
595 unsigned int *left, unsigned int *right,
596 unsigned int *top, unsigned int *bottom)
597{
598 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
599 struct drm_connector_state *conn_state;
600 struct drm_connector *conn;
601 int i;
602
603 *left = vc4_state->margins.left;
604 *right = vc4_state->margins.right;
605 *top = vc4_state->margins.top;
606 *bottom = vc4_state->margins.bottom;
607
608 /* We have to interate over all new connector states because
609 * vc4_crtc_get_margins() might be called before
610 * vc4_crtc_atomic_check() which means margins info in vc4_crtc_state
611 * might be outdated.
612 */
613 for_each_new_connector_in_state(state->state, conn, conn_state, i) {
614 if (conn_state->crtc != state->crtc)
615 continue;
616
617 *left = conn_state->tv.margins.left;
618 *right = conn_state->tv.margins.right;
619 *top = conn_state->tv.margins.top;
620 *bottom = conn_state->tv.margins.bottom;
621 break;
622 }
623}
624
625static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
626 struct drm_crtc_state *state)
627{
628 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
629 struct drm_device *dev = crtc->dev;
630 struct vc4_dev *vc4 = to_vc4_dev(dev);
631 struct drm_plane *plane;
632 unsigned long flags;
633 const struct drm_plane_state *plane_state;
634 struct drm_connector *conn;
635 struct drm_connector_state *conn_state;
636 u32 dlist_count = 0;
637 int ret, i;
638
639 /* The pixelvalve can only feed one encoder (and encoders are
640 * 1:1 with connectors.)
641 */
642 if (hweight32(state->connector_mask) > 1)
643 return -EINVAL;
644
645 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
646 dlist_count += vc4_plane_dlist_size(plane_state);
647
648 dlist_count++; /* Account for SCALER_CTL0_END. */
649
650 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
651 ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
652 dlist_count);
653 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
654 if (ret)
655 return ret;
656
657 for_each_new_connector_in_state(state->state, conn, conn_state, i) {
658 if (conn_state->crtc != crtc)
659 continue;
660
661 /* The writeback connector is implemented using the transposer
662 * block which is directly taking its data from the HVS FIFO.
663 */
664 if (conn->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) {
665 state->no_vblank = true;
666 vc4_state->feed_txp = true;
667 } else {
668 state->no_vblank = false;
669 vc4_state->feed_txp = false;
670 }
671
672 vc4_state->margins.left = conn_state->tv.margins.left;
673 vc4_state->margins.right = conn_state->tv.margins.right;
674 vc4_state->margins.top = conn_state->tv.margins.top;
675 vc4_state->margins.bottom = conn_state->tv.margins.bottom;
676 break;
677 }
678
679 return 0;
680}
681
682static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
683 struct drm_crtc_state *old_state)
684{
685 struct drm_device *dev = crtc->dev;
686 struct vc4_dev *vc4 = to_vc4_dev(dev);
687 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
688 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
689 struct drm_plane *plane;
690 struct vc4_plane_state *vc4_plane_state;
691 bool debug_dump_regs = false;
692 bool enable_bg_fill = false;
693 u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
694 u32 __iomem *dlist_next = dlist_start;
695
696 if (debug_dump_regs) {
697 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
698 vc4_hvs_dump_state(dev);
699 }
700
701 /* Copy all the active planes' dlist contents to the hardware dlist. */
702 drm_atomic_crtc_for_each_plane(plane, crtc) {
703 /* Is this the first active plane? */
704 if (dlist_next == dlist_start) {
705 /* We need to enable background fill when a plane
706 * could be alpha blending from the background, i.e.
707 * where no other plane is underneath. It suffices to
708 * consider the first active plane here since we set
709 * needs_bg_fill such that either the first plane
710 * already needs it or all planes on top blend from
711 * the first or a lower plane.
712 */
713 vc4_plane_state = to_vc4_plane_state(plane->state);
714 enable_bg_fill = vc4_plane_state->needs_bg_fill;
715 }
716
717 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
718 }
719
720 writel(SCALER_CTL0_END, dlist_next);
721 dlist_next++;
722
723 WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
724
725 if (enable_bg_fill)
726 /* This sets a black background color fill, as is the case
727 * with other DRM drivers.
728 */
729 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
730 HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) |
731 SCALER_DISPBKGND_FILL);
732
733 /* Only update DISPLIST if the CRTC was already running and is not
734 * being disabled.
735 * vc4_crtc_enable() takes care of updating the dlist just after
736 * re-enabling VBLANK interrupts and before enabling the engine.
737 * If the CRTC is being disabled, there's no point in updating this
738 * information.
739 */
740 if (crtc->state->active && old_state->active)
741 vc4_crtc_update_dlist(crtc);
742
743 if (crtc->state->color_mgmt_changed) {
744 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel));
745
746 if (crtc->state->gamma_lut) {
747 vc4_crtc_update_gamma_lut(crtc);
748 dispbkgndx |= SCALER_DISPBKGND_GAMMA;
749 } else {
750 /* Unsetting DISPBKGND_GAMMA skips the gamma lut step
751 * in hardware, which is the same as a linear lut that
752 * DRM expects us to use in absence of a user lut.
753 */
754 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
755 }
756 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), dispbkgndx);
757 }
758
759 if (debug_dump_regs) {
760 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
761 vc4_hvs_dump_state(dev);
762 }
763}
764
765static int vc4_enable_vblank(struct drm_crtc *crtc)
766{
767 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
768
769 CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
770
771 return 0;
772}
773
774static void vc4_disable_vblank(struct drm_crtc *crtc)
775{
776 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
777
778 CRTC_WRITE(PV_INTEN, 0);
779}
780
781static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
782{
783 struct drm_crtc *crtc = &vc4_crtc->base;
784 struct drm_device *dev = crtc->dev;
785 struct vc4_dev *vc4 = to_vc4_dev(dev);
786 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
787 u32 chan = vc4_crtc->channel;
788 unsigned long flags;
789
790 spin_lock_irqsave(&dev->event_lock, flags);
791 if (vc4_crtc->event &&
792 (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)) ||
793 vc4_state->feed_txp)) {
794 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
795 vc4_crtc->event = NULL;
796 drm_crtc_vblank_put(crtc);
797
798 /* Wait for the page flip to unmask the underrun to ensure that
799 * the display list was updated by the hardware. Before that
800 * happens, the HVS will be using the previous display list with
801 * the CRTC and encoder already reconfigured, leading to
802 * underruns. This can be seen when reconfiguring the CRTC.
803 */
804 vc4_hvs_unmask_underrun(dev, vc4_crtc->channel);
805 }
806 spin_unlock_irqrestore(&dev->event_lock, flags);
807}
808
809void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
810{
811 crtc->t_vblank = ktime_get();
812 drm_crtc_handle_vblank(&crtc->base);
813 vc4_crtc_handle_page_flip(crtc);
814}
815
816static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
817{
818 struct vc4_crtc *vc4_crtc = data;
819 u32 stat = CRTC_READ(PV_INTSTAT);
820 irqreturn_t ret = IRQ_NONE;
821
822 if (stat & PV_INT_VFP_START) {
823 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
824 vc4_crtc_handle_vblank(vc4_crtc);
825 ret = IRQ_HANDLED;
826 }
827
828 return ret;
829}
830
831struct vc4_async_flip_state {
832 struct drm_crtc *crtc;
833 struct drm_framebuffer *fb;
834 struct drm_framebuffer *old_fb;
835 struct drm_pending_vblank_event *event;
836
837 struct vc4_seqno_cb cb;
838};
839
840/* Called when the V3D execution for the BO being flipped to is done, so that
841 * we can actually update the plane's address to point to it.
842 */
843static void
844vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
845{
846 struct vc4_async_flip_state *flip_state =
847 container_of(cb, struct vc4_async_flip_state, cb);
848 struct drm_crtc *crtc = flip_state->crtc;
849 struct drm_device *dev = crtc->dev;
850 struct vc4_dev *vc4 = to_vc4_dev(dev);
851 struct drm_plane *plane = crtc->primary;
852
853 vc4_plane_async_set_fb(plane, flip_state->fb);
854 if (flip_state->event) {
855 unsigned long flags;
856
857 spin_lock_irqsave(&dev->event_lock, flags);
858 drm_crtc_send_vblank_event(crtc, flip_state->event);
859 spin_unlock_irqrestore(&dev->event_lock, flags);
860 }
861
862 drm_crtc_vblank_put(crtc);
863 drm_framebuffer_put(flip_state->fb);
864
865 /* Decrement the BO usecnt in order to keep the inc/dec calls balanced
866 * when the planes are updated through the async update path.
867 * FIXME: we should move to generic async-page-flip when it's
868 * available, so that we can get rid of this hand-made cleanup_fb()
869 * logic.
870 */
871 if (flip_state->old_fb) {
872 struct drm_gem_cma_object *cma_bo;
873 struct vc4_bo *bo;
874
875 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
876 bo = to_vc4_bo(&cma_bo->base);
877 vc4_bo_dec_usecnt(bo);
878 drm_framebuffer_put(flip_state->old_fb);
879 }
880
881 kfree(flip_state);
882
883 up(&vc4->async_modeset);
884}
885
886/* Implements async (non-vblank-synced) page flips.
887 *
888 * The page flip ioctl needs to return immediately, so we grab the
889 * modeset semaphore on the pipe, and queue the address update for
890 * when V3D is done with the BO being flipped to.
891 */
892static int vc4_async_page_flip(struct drm_crtc *crtc,
893 struct drm_framebuffer *fb,
894 struct drm_pending_vblank_event *event,
895 uint32_t flags)
896{
897 struct drm_device *dev = crtc->dev;
898 struct vc4_dev *vc4 = to_vc4_dev(dev);
899 struct drm_plane *plane = crtc->primary;
900 int ret = 0;
901 struct vc4_async_flip_state *flip_state;
902 struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
903 struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
904
905 /* Increment the BO usecnt here, so that we never end up with an
906 * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
907 * plane is later updated through the non-async path.
908 * FIXME: we should move to generic async-page-flip when it's
909 * available, so that we can get rid of this hand-made prepare_fb()
910 * logic.
911 */
912 ret = vc4_bo_inc_usecnt(bo);
913 if (ret)
914 return ret;
915
916 flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
917 if (!flip_state) {
918 vc4_bo_dec_usecnt(bo);
919 return -ENOMEM;
920 }
921
922 drm_framebuffer_get(fb);
923 flip_state->fb = fb;
924 flip_state->crtc = crtc;
925 flip_state->event = event;
926
927 /* Make sure all other async modesetes have landed. */
928 ret = down_interruptible(&vc4->async_modeset);
929 if (ret) {
930 drm_framebuffer_put(fb);
931 vc4_bo_dec_usecnt(bo);
932 kfree(flip_state);
933 return ret;
934 }
935
936 /* Save the current FB before it's replaced by the new one in
937 * drm_atomic_set_fb_for_plane(). We'll need the old FB in
938 * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
939 * it consistent.
940 * FIXME: we should move to generic async-page-flip when it's
941 * available, so that we can get rid of this hand-made cleanup_fb()
942 * logic.
943 */
944 flip_state->old_fb = plane->state->fb;
945 if (flip_state->old_fb)
946 drm_framebuffer_get(flip_state->old_fb);
947
948 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
949
950 /* Immediately update the plane's legacy fb pointer, so that later
951 * modeset prep sees the state that will be present when the semaphore
952 * is released.
953 */
954 drm_atomic_set_fb_for_plane(plane->state, fb);
955
956 vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
957 vc4_async_page_flip_complete);
958
959 /* Driver takes ownership of state on successful async commit. */
960 return 0;
961}
962
963static int vc4_page_flip(struct drm_crtc *crtc,
964 struct drm_framebuffer *fb,
965 struct drm_pending_vblank_event *event,
966 uint32_t flags,
967 struct drm_modeset_acquire_ctx *ctx)
968{
969 if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
970 return vc4_async_page_flip(crtc, fb, event, flags);
971 else
972 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
973}
974
975static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
976{
977 struct vc4_crtc_state *vc4_state, *old_vc4_state;
978
979 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
980 if (!vc4_state)
981 return NULL;
982
983 old_vc4_state = to_vc4_crtc_state(crtc->state);
984 vc4_state->feed_txp = old_vc4_state->feed_txp;
985 vc4_state->margins = old_vc4_state->margins;
986
987 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
988 return &vc4_state->base;
989}
990
991static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
992 struct drm_crtc_state *state)
993{
994 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
995 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
996
997 if (vc4_state->mm.allocated) {
998 unsigned long flags;
999
1000 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
1001 drm_mm_remove_node(&vc4_state->mm);
1002 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
1003
1004 }
1005
1006 drm_atomic_helper_crtc_destroy_state(crtc, state);
1007}
1008
1009static void
1010vc4_crtc_reset(struct drm_crtc *crtc)
1011{
1012 if (crtc->state)
1013 vc4_crtc_destroy_state(crtc, crtc->state);
1014
1015 crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL);
1016 if (crtc->state)
1017 crtc->state->crtc = crtc;
1018}
1019
1020static const struct drm_crtc_funcs vc4_crtc_funcs = {
1021 .set_config = drm_atomic_helper_set_config,
1022 .destroy = vc4_crtc_destroy,
1023 .page_flip = vc4_page_flip,
1024 .set_property = NULL,
1025 .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
1026 .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
1027 .reset = vc4_crtc_reset,
1028 .atomic_duplicate_state = vc4_crtc_duplicate_state,
1029 .atomic_destroy_state = vc4_crtc_destroy_state,
1030 .gamma_set = drm_atomic_helper_legacy_gamma_set,
1031 .enable_vblank = vc4_enable_vblank,
1032 .disable_vblank = vc4_disable_vblank,
1033};
1034
1035static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
1036 .mode_set_nofb = vc4_crtc_mode_set_nofb,
1037 .mode_valid = vc4_crtc_mode_valid,
1038 .atomic_check = vc4_crtc_atomic_check,
1039 .atomic_flush = vc4_crtc_atomic_flush,
1040 .atomic_enable = vc4_crtc_atomic_enable,
1041 .atomic_disable = vc4_crtc_atomic_disable,
1042};
1043
1044static const struct vc4_crtc_data pv0_data = {
1045 .hvs_channel = 0,
1046 .debugfs_name = "crtc0_regs",
1047 .encoder_types = {
1048 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
1049 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
1050 },
1051};
1052
1053static const struct vc4_crtc_data pv1_data = {
1054 .hvs_channel = 2,
1055 .debugfs_name = "crtc1_regs",
1056 .encoder_types = {
1057 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
1058 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
1059 },
1060};
1061
1062static const struct vc4_crtc_data pv2_data = {
1063 .hvs_channel = 1,
1064 .debugfs_name = "crtc2_regs",
1065 .encoder_types = {
1066 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
1067 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1068 },
1069};
1070
1071static const struct of_device_id vc4_crtc_dt_match[] = {
1072 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
1073 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
1074 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
1075 {}
1076};
1077
1078static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1079 struct drm_crtc *crtc)
1080{
1081 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1082 const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
1083 const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
1084 struct drm_encoder *encoder;
1085
1086 drm_for_each_encoder(encoder, drm) {
1087 struct vc4_encoder *vc4_encoder;
1088 int i;
1089
1090 /* HVS FIFO2 can feed the TXP IP. */
1091 if (crtc_data->hvs_channel == 2 &&
1092 encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) {
1093 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1094 continue;
1095 }
1096
1097 vc4_encoder = to_vc4_encoder(encoder);
1098 for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
1099 if (vc4_encoder->type == encoder_types[i]) {
1100 vc4_encoder->clock_select = i;
1101 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1102 break;
1103 }
1104 }
1105 }
1106}
1107
1108static void
1109vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
1110{
1111 struct drm_device *drm = vc4_crtc->base.dev;
1112 struct vc4_dev *vc4 = to_vc4_dev(drm);
1113 u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
1114 /* Top/base are supposed to be 4-pixel aligned, but the
1115 * Raspberry Pi firmware fills the low bits (which are
1116 * presumably ignored).
1117 */
1118 u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
1119 u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
1120
1121 vc4_crtc->cob_size = top - base + 4;
1122}
1123
1124static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1125{
1126 struct platform_device *pdev = to_platform_device(dev);
1127 struct drm_device *drm = dev_get_drvdata(master);
1128 struct vc4_crtc *vc4_crtc;
1129 struct drm_crtc *crtc;
1130 struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
1131 const struct of_device_id *match;
1132 int ret, i;
1133
1134 vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
1135 if (!vc4_crtc)
1136 return -ENOMEM;
1137 crtc = &vc4_crtc->base;
1138
1139 match = of_match_device(vc4_crtc_dt_match, dev);
1140 if (!match)
1141 return -ENODEV;
1142 vc4_crtc->data = match->data;
1143 vc4_crtc->pdev = pdev;
1144
1145 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1146 if (IS_ERR(vc4_crtc->regs))
1147 return PTR_ERR(vc4_crtc->regs);
1148
1149 vc4_crtc->regset.base = vc4_crtc->regs;
1150 vc4_crtc->regset.regs = crtc_regs;
1151 vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);
1152
1153 /* For now, we create just the primary and the legacy cursor
1154 * planes. We should be able to stack more planes on easily,
1155 * but to do that we would need to compute the bandwidth
1156 * requirement of the plane configuration, and reject ones
1157 * that will take too much.
1158 */
1159 primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
1160 if (IS_ERR(primary_plane)) {
1161 dev_err(dev, "failed to construct primary plane\n");
1162 ret = PTR_ERR(primary_plane);
1163 goto err;
1164 }
1165
1166 drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1167 &vc4_crtc_funcs, NULL);
1168 drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
1169 vc4_crtc->channel = vc4_crtc->data->hvs_channel;
1170 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1171 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
1172
1173 /* We support CTM, but only for one CRTC at a time. It's therefore
1174 * implemented as private driver state in vc4_kms, not here.
1175 */
1176 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
1177
1178 /* Set up some arbitrary number of planes. We're not limited
1179 * by a set number of physical registers, just the space in
1180 * the HVS (16k) and how small an plane can be (28 bytes).
1181 * However, each plane we set up takes up some memory, and
1182 * increases the cost of looping over planes, which atomic
1183 * modesetting does quite a bit. As a result, we pick a
1184 * modest number of planes to expose, that should hopefully
1185 * still cover any sane usecase.
1186 */
1187 for (i = 0; i < 8; i++) {
1188 struct drm_plane *plane =
1189 vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
1190
1191 if (IS_ERR(plane))
1192 continue;
1193
1194 plane->possible_crtcs = drm_crtc_mask(crtc);
1195 }
1196
1197 /* Set up the legacy cursor after overlay initialization,
1198 * since we overlay planes on the CRTC in the order they were
1199 * initialized.
1200 */
1201 cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1202 if (!IS_ERR(cursor_plane)) {
1203 cursor_plane->possible_crtcs = drm_crtc_mask(crtc);
1204 crtc->cursor = cursor_plane;
1205 }
1206
1207 vc4_crtc_get_cob_allocation(vc4_crtc);
1208
1209 CRTC_WRITE(PV_INTEN, 0);
1210 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1211 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1212 vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
1213 if (ret)
1214 goto err_destroy_planes;
1215
1216 vc4_set_crtc_possible_masks(drm, crtc);
1217
1218 for (i = 0; i < crtc->gamma_size; i++) {
1219 vc4_crtc->lut_r[i] = i;
1220 vc4_crtc->lut_g[i] = i;
1221 vc4_crtc->lut_b[i] = i;
1222 }
1223
1224 platform_set_drvdata(pdev, vc4_crtc);
1225
1226 vc4_debugfs_add_regset32(drm, vc4_crtc->data->debugfs_name,
1227 &vc4_crtc->regset);
1228
1229 return 0;
1230
1231err_destroy_planes:
1232 list_for_each_entry_safe(destroy_plane, temp,
1233 &drm->mode_config.plane_list, head) {
1234 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc))
1235 destroy_plane->funcs->destroy(destroy_plane);
1236 }
1237err:
1238 return ret;
1239}
1240
1241static void vc4_crtc_unbind(struct device *dev, struct device *master,
1242 void *data)
1243{
1244 struct platform_device *pdev = to_platform_device(dev);
1245 struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1246
1247 vc4_crtc_destroy(&vc4_crtc->base);
1248
1249 CRTC_WRITE(PV_INTEN, 0);
1250
1251 platform_set_drvdata(pdev, NULL);
1252}
1253
1254static const struct component_ops vc4_crtc_ops = {
1255 .bind = vc4_crtc_bind,
1256 .unbind = vc4_crtc_unbind,
1257};
1258
1259static int vc4_crtc_dev_probe(struct platform_device *pdev)
1260{
1261 return component_add(&pdev->dev, &vc4_crtc_ops);
1262}
1263
1264static int vc4_crtc_dev_remove(struct platform_device *pdev)
1265{
1266 component_del(&pdev->dev, &vc4_crtc_ops);
1267 return 0;
1268}
1269
1270struct platform_driver vc4_crtc_driver = {
1271 .probe = vc4_crtc_dev_probe,
1272 .remove = vc4_crtc_dev_remove,
1273 .driver = {
1274 .name = "vc4_crtc",
1275 .of_match_table = vc4_crtc_dt_match,
1276 },
1277};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 Broadcom
4 */
5
6/**
7 * DOC: VC4 CRTC module
8 *
9 * In VC4, the Pixel Valve is what most closely corresponds to the
10 * DRM's concept of a CRTC. The PV generates video timings from the
11 * encoder's clock plus its configuration. It pulls scaled pixels from
12 * the HVS at that timing, and feeds it to the encoder.
13 *
14 * However, the DRM CRTC also collects the configuration of all the
15 * DRM planes attached to it. As a result, the CRTC is also
16 * responsible for writing the display list for the HVS channel that
17 * the CRTC will use.
18 *
19 * The 2835 has 3 different pixel valves. pv0 in the audio power
20 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
21 * image domain can feed either HDMI or the SDTV controller. The
22 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
23 * SDTV, etc.) according to which output type is chosen in the mux.
24 *
25 * For power management, the pixel valve's registers are all clocked
26 * by the AXI clock, while the timings and FIFOs make use of the
27 * output-specific clock. Since the encoders also directly consume
28 * the CPRMAN clocks, and know what timings they need, they are the
29 * ones that set the clock.
30 */
31
32#include <linux/clk.h>
33#include <linux/component.h>
34#include <linux/of_device.h>
35
36#include <drm/drm_atomic.h>
37#include <drm/drm_atomic_helper.h>
38#include <drm/drm_atomic_uapi.h>
39#include <drm/drm_fb_cma_helper.h>
40#include <drm/drm_print.h>
41#include <drm/drm_probe_helper.h>
42#include <drm/drm_vblank.h>
43
44#include "vc4_drv.h"
45#include "vc4_regs.h"
46
47#define HVS_FIFO_LATENCY_PIX 6
48
49#define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
50#define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
51
52static const struct debugfs_reg32 crtc_regs[] = {
53 VC4_REG32(PV_CONTROL),
54 VC4_REG32(PV_V_CONTROL),
55 VC4_REG32(PV_VSYNCD_EVEN),
56 VC4_REG32(PV_HORZA),
57 VC4_REG32(PV_HORZB),
58 VC4_REG32(PV_VERTA),
59 VC4_REG32(PV_VERTB),
60 VC4_REG32(PV_VERTA_EVEN),
61 VC4_REG32(PV_VERTB_EVEN),
62 VC4_REG32(PV_INTEN),
63 VC4_REG32(PV_INTSTAT),
64 VC4_REG32(PV_STAT),
65 VC4_REG32(PV_HACT_ACT),
66};
67
68static unsigned int
69vc4_crtc_get_cob_allocation(struct vc4_dev *vc4, unsigned int channel)
70{
71 u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel));
72 /* Top/base are supposed to be 4-pixel aligned, but the
73 * Raspberry Pi firmware fills the low bits (which are
74 * presumably ignored).
75 */
76 u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
77 u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
78
79 return top - base + 4;
80}
81
82static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
83 bool in_vblank_irq,
84 int *vpos, int *hpos,
85 ktime_t *stime, ktime_t *etime,
86 const struct drm_display_mode *mode)
87{
88 struct drm_device *dev = crtc->dev;
89 struct vc4_dev *vc4 = to_vc4_dev(dev);
90 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
91 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
92 unsigned int cob_size;
93 u32 val;
94 int fifo_lines;
95 int vblank_lines;
96 bool ret = false;
97
98 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
99
100 /* Get optional system timestamp before query. */
101 if (stime)
102 *stime = ktime_get();
103
104 /*
105 * Read vertical scanline which is currently composed for our
106 * pixelvalve by the HVS, and also the scaler status.
107 */
108 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel));
109
110 /* Get optional system timestamp after query. */
111 if (etime)
112 *etime = ktime_get();
113
114 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
115
116 /* Vertical position of hvs composed scanline. */
117 *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
118 *hpos = 0;
119
120 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
121 *vpos /= 2;
122
123 /* Use hpos to correct for field offset in interlaced mode. */
124 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
125 *hpos += mode->crtc_htotal / 2;
126 }
127
128 cob_size = vc4_crtc_get_cob_allocation(vc4, vc4_crtc_state->assigned_channel);
129 /* This is the offset we need for translating hvs -> pv scanout pos. */
130 fifo_lines = cob_size / mode->crtc_hdisplay;
131
132 if (fifo_lines > 0)
133 ret = true;
134
135 /* HVS more than fifo_lines into frame for compositing? */
136 if (*vpos > fifo_lines) {
137 /*
138 * We are in active scanout and can get some meaningful results
139 * from HVS. The actual PV scanout can not trail behind more
140 * than fifo_lines as that is the fifo's capacity. Assume that
141 * in active scanout the HVS and PV work in lockstep wrt. HVS
142 * refilling the fifo and PV consuming from the fifo, ie.
143 * whenever the PV consumes and frees up a scanline in the
144 * fifo, the HVS will immediately refill it, therefore
145 * incrementing vpos. Therefore we choose HVS read position -
146 * fifo size in scanlines as a estimate of the real scanout
147 * position of the PV.
148 */
149 *vpos -= fifo_lines + 1;
150
151 return ret;
152 }
153
154 /*
155 * Less: This happens when we are in vblank and the HVS, after getting
156 * the VSTART restart signal from the PV, just started refilling its
157 * fifo with new lines from the top-most lines of the new framebuffers.
158 * The PV does not scan out in vblank, so does not remove lines from
159 * the fifo, so the fifo will be full quickly and the HVS has to pause.
160 * We can't get meaningful readings wrt. scanline position of the PV
161 * and need to make things up in a approximative but consistent way.
162 */
163 vblank_lines = mode->vtotal - mode->vdisplay;
164
165 if (in_vblank_irq) {
166 /*
167 * Assume the irq handler got called close to first
168 * line of vblank, so PV has about a full vblank
169 * scanlines to go, and as a base timestamp use the
170 * one taken at entry into vblank irq handler, so it
171 * is not affected by random delays due to lock
172 * contention on event_lock or vblank_time lock in
173 * the core.
174 */
175 *vpos = -vblank_lines;
176
177 if (stime)
178 *stime = vc4_crtc->t_vblank;
179 if (etime)
180 *etime = vc4_crtc->t_vblank;
181
182 /*
183 * If the HVS fifo is not yet full then we know for certain
184 * we are at the very beginning of vblank, as the hvs just
185 * started refilling, and the stime and etime timestamps
186 * truly correspond to start of vblank.
187 *
188 * Unfortunately there's no way to report this to upper levels
189 * and make it more useful.
190 */
191 } else {
192 /*
193 * No clue where we are inside vblank. Return a vpos of zero,
194 * which will cause calling code to just return the etime
195 * timestamp uncorrected. At least this is no worse than the
196 * standard fallback.
197 */
198 *vpos = 0;
199 }
200
201 return ret;
202}
203
204void vc4_crtc_destroy(struct drm_crtc *crtc)
205{
206 drm_crtc_cleanup(crtc);
207}
208
209static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
210{
211 const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);
212 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
213 struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev);
214 u32 fifo_len_bytes = pv_data->fifo_depth;
215
216 /*
217 * Pixels are pulled from the HVS if the number of bytes is
218 * lower than the FIFO full level.
219 *
220 * The latency of the pixel fetch mechanism is 6 pixels, so we
221 * need to convert those 6 pixels in bytes, depending on the
222 * format, and then subtract that from the length of the FIFO
223 * to make sure we never end up in a situation where the FIFO
224 * is full.
225 */
226 switch (format) {
227 case PV_CONTROL_FORMAT_DSIV_16:
228 case PV_CONTROL_FORMAT_DSIC_16:
229 return fifo_len_bytes - 2 * HVS_FIFO_LATENCY_PIX;
230 case PV_CONTROL_FORMAT_DSIV_18:
231 return fifo_len_bytes - 14;
232 case PV_CONTROL_FORMAT_24:
233 case PV_CONTROL_FORMAT_DSIV_24:
234 default:
235 /*
236 * For some reason, the pixelvalve4 doesn't work with
237 * the usual formula and will only work with 32.
238 */
239 if (crtc_data->hvs_output == 5)
240 return 32;
241
242 /*
243 * It looks like in some situations, we will overflow
244 * the PixelValve FIFO (with the bit 10 of PV stat being
245 * set) and stall the HVS / PV, eventually resulting in
246 * a page flip timeout.
247 *
248 * Displaying the video overlay during a playback with
249 * Kodi on an RPi3 seems to be a great solution with a
250 * failure rate around 50%.
251 *
252 * Removing 1 from the FIFO full level however
253 * seems to completely remove that issue.
254 */
255 if (!vc4->hvs->hvs5)
256 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1;
257
258 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
259 }
260}
261
262static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc,
263 u32 format)
264{
265 u32 level = vc4_get_fifo_full_level(vc4_crtc, format);
266 u32 ret = 0;
267
268 ret |= VC4_SET_FIELD((level >> 6),
269 PV5_CONTROL_FIFO_LEVEL_HIGH);
270
271 return ret | VC4_SET_FIELD(level & 0x3f,
272 PV_CONTROL_FIFO_LEVEL);
273}
274
275/*
276 * Returns the encoder attached to the CRTC.
277 *
278 * VC4 can only scan out to one encoder at a time, while the DRM core
279 * allows drivers to push pixels to more than one encoder from the
280 * same CRTC.
281 */
282static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc,
283 struct drm_atomic_state *state,
284 struct drm_connector_state *(*get_state)(struct drm_atomic_state *state,
285 struct drm_connector *connector))
286{
287 struct drm_connector *connector;
288 struct drm_connector_list_iter conn_iter;
289
290 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
291 drm_for_each_connector_iter(connector, &conn_iter) {
292 struct drm_connector_state *conn_state = get_state(state, connector);
293
294 if (!conn_state)
295 continue;
296
297 if (conn_state->crtc == crtc) {
298 drm_connector_list_iter_end(&conn_iter);
299 return connector->encoder;
300 }
301 }
302 drm_connector_list_iter_end(&conn_iter);
303
304 return NULL;
305}
306
307static void vc4_crtc_pixelvalve_reset(struct drm_crtc *crtc)
308{
309 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
310
311 /* The PV needs to be disabled before it can be flushed */
312 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);
313 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR);
314}
315
316static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_atomic_state *state)
317{
318 struct drm_device *dev = crtc->dev;
319 struct vc4_dev *vc4 = to_vc4_dev(dev);
320 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, state,
321 drm_atomic_get_new_connector_state);
322 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
323 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
324 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
325 struct drm_crtc_state *crtc_state = crtc->state;
326 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
327 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
328 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
329 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
330 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
331 u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
332 u8 ppc = pv_data->pixels_per_clock;
333 bool debug_dump_regs = false;
334
335 if (debug_dump_regs) {
336 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
337 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",
338 drm_crtc_index(crtc));
339 drm_print_regset32(&p, &vc4_crtc->regset);
340 }
341
342 vc4_crtc_pixelvalve_reset(crtc);
343
344 CRTC_WRITE(PV_HORZA,
345 VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
346 PV_HORZA_HBP) |
347 VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc,
348 PV_HORZA_HSYNC));
349
350 CRTC_WRITE(PV_HORZB,
351 VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc,
352 PV_HORZB_HFP) |
353 VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,
354 PV_HORZB_HACTIVE));
355
356 CRTC_WRITE(PV_VERTA,
357 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
358 PV_VERTA_VBP) |
359 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
360 PV_VERTA_VSYNC));
361 CRTC_WRITE(PV_VERTB,
362 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
363 PV_VERTB_VFP) |
364 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
365
366 if (interlace) {
367 CRTC_WRITE(PV_VERTA_EVEN,
368 VC4_SET_FIELD(mode->crtc_vtotal -
369 mode->crtc_vsync_end - 1,
370 PV_VERTA_VBP) |
371 VC4_SET_FIELD(mode->crtc_vsync_end -
372 mode->crtc_vsync_start,
373 PV_VERTA_VSYNC));
374 CRTC_WRITE(PV_VERTB_EVEN,
375 VC4_SET_FIELD(mode->crtc_vsync_start -
376 mode->crtc_vdisplay,
377 PV_VERTB_VFP) |
378 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
379
380 /* We set up first field even mode for HDMI. VEC's
381 * NTSC mode would want first field odd instead, once
382 * we support it (to do so, set ODD_FIRST and put the
383 * delay in VSYNCD_EVEN instead).
384 */
385 CRTC_WRITE(PV_V_CONTROL,
386 PV_VCONTROL_CONTINUOUS |
387 (is_dsi ? PV_VCONTROL_DSI : 0) |
388 PV_VCONTROL_INTERLACE |
389 VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
390 PV_VCONTROL_ODD_DELAY));
391 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
392 } else {
393 CRTC_WRITE(PV_V_CONTROL,
394 PV_VCONTROL_CONTINUOUS |
395 (is_dsi ? PV_VCONTROL_DSI : 0));
396 }
397
398 if (is_dsi)
399 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
400
401 if (vc4->hvs->hvs5)
402 CRTC_WRITE(PV_MUX_CFG,
403 VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP,
404 PV_MUX_CFG_RGB_PIXEL_MUX_MODE));
405
406 CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR |
407 vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |
408 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
409 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
410 PV_CONTROL_CLR_AT_START |
411 PV_CONTROL_TRIGGER_UNDERFLOW |
412 PV_CONTROL_WAIT_HSTART |
413 VC4_SET_FIELD(vc4_encoder->clock_select,
414 PV_CONTROL_CLK_SELECT));
415
416 if (debug_dump_regs) {
417 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
418 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",
419 drm_crtc_index(crtc));
420 drm_print_regset32(&p, &vc4_crtc->regset);
421 }
422}
423
424static void require_hvs_enabled(struct drm_device *dev)
425{
426 struct vc4_dev *vc4 = to_vc4_dev(dev);
427
428 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
429 SCALER_DISPCTRL_ENABLE);
430}
431
432static int vc4_crtc_disable(struct drm_crtc *crtc,
433 struct drm_encoder *encoder,
434 struct drm_atomic_state *state,
435 unsigned int channel)
436{
437 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
438 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
439 struct drm_device *dev = crtc->dev;
440 int ret;
441
442 CRTC_WRITE(PV_V_CONTROL,
443 CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
444 ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
445 WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
446
447 /*
448 * This delay is needed to avoid to get a pixel stuck in an
449 * unflushable FIFO between the pixelvalve and the HDMI
450 * controllers on the BCM2711.
451 *
452 * Timing is fairly sensitive here, so mdelay is the safest
453 * approach.
454 *
455 * If it was to be reworked, the stuck pixel happens on a
456 * BCM2711 when changing mode with a good probability, so a
457 * script that changes mode on a regular basis should trigger
458 * the bug after less than 10 attempts. It manifests itself with
459 * every pixels being shifted by one to the right, and thus the
460 * last pixel of a line actually being displayed as the first
461 * pixel on the next line.
462 */
463 mdelay(20);
464
465 if (vc4_encoder && vc4_encoder->post_crtc_disable)
466 vc4_encoder->post_crtc_disable(encoder, state);
467
468 vc4_crtc_pixelvalve_reset(crtc);
469 vc4_hvs_stop_channel(dev, channel);
470
471 if (vc4_encoder && vc4_encoder->post_crtc_powerdown)
472 vc4_encoder->post_crtc_powerdown(encoder, state);
473
474 return 0;
475}
476
477static struct drm_encoder *vc4_crtc_get_encoder_by_type(struct drm_crtc *crtc,
478 enum vc4_encoder_type type)
479{
480 struct drm_encoder *encoder;
481
482 drm_for_each_encoder(encoder, crtc->dev) {
483 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
484
485 if (vc4_encoder->type == type)
486 return encoder;
487 }
488
489 return NULL;
490}
491
492int vc4_crtc_disable_at_boot(struct drm_crtc *crtc)
493{
494 struct drm_device *drm = crtc->dev;
495 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
496 enum vc4_encoder_type encoder_type;
497 const struct vc4_pv_data *pv_data;
498 struct drm_encoder *encoder;
499 unsigned encoder_sel;
500 int channel;
501
502 if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
503 "brcm,bcm2711-pixelvalve2") ||
504 of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
505 "brcm,bcm2711-pixelvalve4")))
506 return 0;
507
508 if (!(CRTC_READ(PV_CONTROL) & PV_CONTROL_EN))
509 return 0;
510
511 if (!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN))
512 return 0;
513
514 channel = vc4_hvs_get_fifo_from_output(drm, vc4_crtc->data->hvs_output);
515 if (channel < 0)
516 return 0;
517
518 encoder_sel = VC4_GET_FIELD(CRTC_READ(PV_CONTROL), PV_CONTROL_CLK_SELECT);
519 if (WARN_ON(encoder_sel != 0))
520 return 0;
521
522 pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
523 encoder_type = pv_data->encoder_types[encoder_sel];
524 encoder = vc4_crtc_get_encoder_by_type(crtc, encoder_type);
525 if (WARN_ON(!encoder))
526 return 0;
527
528 return vc4_crtc_disable(crtc, encoder, NULL, channel);
529}
530
531static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
532 struct drm_atomic_state *state)
533{
534 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
535 crtc);
536 struct vc4_crtc_state *old_vc4_state = to_vc4_crtc_state(old_state);
537 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, state,
538 drm_atomic_get_old_connector_state);
539 struct drm_device *dev = crtc->dev;
540
541 require_hvs_enabled(dev);
542
543 /* Disable vblank irq handling before crtc is disabled. */
544 drm_crtc_vblank_off(crtc);
545
546 vc4_crtc_disable(crtc, encoder, state, old_vc4_state->assigned_channel);
547
548 /*
549 * Make sure we issue a vblank event after disabling the CRTC if
550 * someone was waiting it.
551 */
552 if (crtc->state->event) {
553 unsigned long flags;
554
555 spin_lock_irqsave(&dev->event_lock, flags);
556 drm_crtc_send_vblank_event(crtc, crtc->state->event);
557 crtc->state->event = NULL;
558 spin_unlock_irqrestore(&dev->event_lock, flags);
559 }
560}
561
562static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
563 struct drm_atomic_state *state)
564{
565 struct drm_device *dev = crtc->dev;
566 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
567 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, state,
568 drm_atomic_get_new_connector_state);
569 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
570
571 require_hvs_enabled(dev);
572
573 /* Enable vblank irq handling before crtc is started otherwise
574 * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
575 */
576 drm_crtc_vblank_on(crtc);
577
578 vc4_hvs_atomic_enable(crtc, state);
579
580 if (vc4_encoder->pre_crtc_configure)
581 vc4_encoder->pre_crtc_configure(encoder, state);
582
583 vc4_crtc_config_pv(crtc, state);
584
585 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);
586
587 if (vc4_encoder->pre_crtc_enable)
588 vc4_encoder->pre_crtc_enable(encoder, state);
589
590 /* When feeding the transposer block the pixelvalve is unneeded and
591 * should not be enabled.
592 */
593 CRTC_WRITE(PV_V_CONTROL,
594 CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
595
596 if (vc4_encoder->post_crtc_enable)
597 vc4_encoder->post_crtc_enable(encoder, state);
598}
599
600static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
601 const struct drm_display_mode *mode)
602{
603 /* Do not allow doublescan modes from user space */
604 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
605 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
606 crtc->base.id);
607 return MODE_NO_DBLESCAN;
608 }
609
610 return MODE_OK;
611}
612
613void vc4_crtc_get_margins(struct drm_crtc_state *state,
614 unsigned int *left, unsigned int *right,
615 unsigned int *top, unsigned int *bottom)
616{
617 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
618 struct drm_connector_state *conn_state;
619 struct drm_connector *conn;
620 int i;
621
622 *left = vc4_state->margins.left;
623 *right = vc4_state->margins.right;
624 *top = vc4_state->margins.top;
625 *bottom = vc4_state->margins.bottom;
626
627 /* We have to interate over all new connector states because
628 * vc4_crtc_get_margins() might be called before
629 * vc4_crtc_atomic_check() which means margins info in vc4_crtc_state
630 * might be outdated.
631 */
632 for_each_new_connector_in_state(state->state, conn, conn_state, i) {
633 if (conn_state->crtc != state->crtc)
634 continue;
635
636 *left = conn_state->tv.margins.left;
637 *right = conn_state->tv.margins.right;
638 *top = conn_state->tv.margins.top;
639 *bottom = conn_state->tv.margins.bottom;
640 break;
641 }
642}
643
644static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
645 struct drm_atomic_state *state)
646{
647 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
648 crtc);
649 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
650 struct drm_connector *conn;
651 struct drm_connector_state *conn_state;
652 int ret, i;
653
654 ret = vc4_hvs_atomic_check(crtc, state);
655 if (ret)
656 return ret;
657
658 for_each_new_connector_in_state(state, conn, conn_state,
659 i) {
660 if (conn_state->crtc != crtc)
661 continue;
662
663 vc4_state->margins.left = conn_state->tv.margins.left;
664 vc4_state->margins.right = conn_state->tv.margins.right;
665 vc4_state->margins.top = conn_state->tv.margins.top;
666 vc4_state->margins.bottom = conn_state->tv.margins.bottom;
667 break;
668 }
669
670 return 0;
671}
672
673static int vc4_enable_vblank(struct drm_crtc *crtc)
674{
675 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
676
677 CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
678
679 return 0;
680}
681
682static void vc4_disable_vblank(struct drm_crtc *crtc)
683{
684 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
685
686 CRTC_WRITE(PV_INTEN, 0);
687}
688
689static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
690{
691 struct drm_crtc *crtc = &vc4_crtc->base;
692 struct drm_device *dev = crtc->dev;
693 struct vc4_dev *vc4 = to_vc4_dev(dev);
694 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
695 u32 chan = vc4_state->assigned_channel;
696 unsigned long flags;
697
698 spin_lock_irqsave(&dev->event_lock, flags);
699 if (vc4_crtc->event &&
700 (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)) ||
701 vc4_state->feed_txp)) {
702 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
703 vc4_crtc->event = NULL;
704 drm_crtc_vblank_put(crtc);
705
706 /* Wait for the page flip to unmask the underrun to ensure that
707 * the display list was updated by the hardware. Before that
708 * happens, the HVS will be using the previous display list with
709 * the CRTC and encoder already reconfigured, leading to
710 * underruns. This can be seen when reconfiguring the CRTC.
711 */
712 vc4_hvs_unmask_underrun(dev, chan);
713 }
714 spin_unlock_irqrestore(&dev->event_lock, flags);
715}
716
717void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
718{
719 crtc->t_vblank = ktime_get();
720 drm_crtc_handle_vblank(&crtc->base);
721 vc4_crtc_handle_page_flip(crtc);
722}
723
724static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
725{
726 struct vc4_crtc *vc4_crtc = data;
727 u32 stat = CRTC_READ(PV_INTSTAT);
728 irqreturn_t ret = IRQ_NONE;
729
730 if (stat & PV_INT_VFP_START) {
731 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
732 vc4_crtc_handle_vblank(vc4_crtc);
733 ret = IRQ_HANDLED;
734 }
735
736 return ret;
737}
738
739struct vc4_async_flip_state {
740 struct drm_crtc *crtc;
741 struct drm_framebuffer *fb;
742 struct drm_framebuffer *old_fb;
743 struct drm_pending_vblank_event *event;
744
745 struct vc4_seqno_cb cb;
746};
747
748/* Called when the V3D execution for the BO being flipped to is done, so that
749 * we can actually update the plane's address to point to it.
750 */
751static void
752vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
753{
754 struct vc4_async_flip_state *flip_state =
755 container_of(cb, struct vc4_async_flip_state, cb);
756 struct drm_crtc *crtc = flip_state->crtc;
757 struct drm_device *dev = crtc->dev;
758 struct drm_plane *plane = crtc->primary;
759
760 vc4_plane_async_set_fb(plane, flip_state->fb);
761 if (flip_state->event) {
762 unsigned long flags;
763
764 spin_lock_irqsave(&dev->event_lock, flags);
765 drm_crtc_send_vblank_event(crtc, flip_state->event);
766 spin_unlock_irqrestore(&dev->event_lock, flags);
767 }
768
769 drm_crtc_vblank_put(crtc);
770 drm_framebuffer_put(flip_state->fb);
771
772 /* Decrement the BO usecnt in order to keep the inc/dec calls balanced
773 * when the planes are updated through the async update path.
774 * FIXME: we should move to generic async-page-flip when it's
775 * available, so that we can get rid of this hand-made cleanup_fb()
776 * logic.
777 */
778 if (flip_state->old_fb) {
779 struct drm_gem_cma_object *cma_bo;
780 struct vc4_bo *bo;
781
782 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
783 bo = to_vc4_bo(&cma_bo->base);
784 vc4_bo_dec_usecnt(bo);
785 drm_framebuffer_put(flip_state->old_fb);
786 }
787
788 kfree(flip_state);
789}
790
791/* Implements async (non-vblank-synced) page flips.
792 *
793 * The page flip ioctl needs to return immediately, so we grab the
794 * modeset semaphore on the pipe, and queue the address update for
795 * when V3D is done with the BO being flipped to.
796 */
797static int vc4_async_page_flip(struct drm_crtc *crtc,
798 struct drm_framebuffer *fb,
799 struct drm_pending_vblank_event *event,
800 uint32_t flags)
801{
802 struct drm_device *dev = crtc->dev;
803 struct drm_plane *plane = crtc->primary;
804 int ret = 0;
805 struct vc4_async_flip_state *flip_state;
806 struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
807 struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
808
809 /* Increment the BO usecnt here, so that we never end up with an
810 * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
811 * plane is later updated through the non-async path.
812 * FIXME: we should move to generic async-page-flip when it's
813 * available, so that we can get rid of this hand-made prepare_fb()
814 * logic.
815 */
816 ret = vc4_bo_inc_usecnt(bo);
817 if (ret)
818 return ret;
819
820 flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
821 if (!flip_state) {
822 vc4_bo_dec_usecnt(bo);
823 return -ENOMEM;
824 }
825
826 drm_framebuffer_get(fb);
827 flip_state->fb = fb;
828 flip_state->crtc = crtc;
829 flip_state->event = event;
830
831 /* Save the current FB before it's replaced by the new one in
832 * drm_atomic_set_fb_for_plane(). We'll need the old FB in
833 * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
834 * it consistent.
835 * FIXME: we should move to generic async-page-flip when it's
836 * available, so that we can get rid of this hand-made cleanup_fb()
837 * logic.
838 */
839 flip_state->old_fb = plane->state->fb;
840 if (flip_state->old_fb)
841 drm_framebuffer_get(flip_state->old_fb);
842
843 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
844
845 /* Immediately update the plane's legacy fb pointer, so that later
846 * modeset prep sees the state that will be present when the semaphore
847 * is released.
848 */
849 drm_atomic_set_fb_for_plane(plane->state, fb);
850
851 vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
852 vc4_async_page_flip_complete);
853
854 /* Driver takes ownership of state on successful async commit. */
855 return 0;
856}
857
858int vc4_page_flip(struct drm_crtc *crtc,
859 struct drm_framebuffer *fb,
860 struct drm_pending_vblank_event *event,
861 uint32_t flags,
862 struct drm_modeset_acquire_ctx *ctx)
863{
864 if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
865 return vc4_async_page_flip(crtc, fb, event, flags);
866 else
867 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
868}
869
870struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
871{
872 struct vc4_crtc_state *vc4_state, *old_vc4_state;
873
874 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
875 if (!vc4_state)
876 return NULL;
877
878 old_vc4_state = to_vc4_crtc_state(crtc->state);
879 vc4_state->feed_txp = old_vc4_state->feed_txp;
880 vc4_state->margins = old_vc4_state->margins;
881 vc4_state->assigned_channel = old_vc4_state->assigned_channel;
882
883 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
884 return &vc4_state->base;
885}
886
887void vc4_crtc_destroy_state(struct drm_crtc *crtc,
888 struct drm_crtc_state *state)
889{
890 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
891 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
892
893 if (drm_mm_node_allocated(&vc4_state->mm)) {
894 unsigned long flags;
895
896 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
897 drm_mm_remove_node(&vc4_state->mm);
898 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
899
900 }
901
902 drm_atomic_helper_crtc_destroy_state(crtc, state);
903}
904
905void vc4_crtc_reset(struct drm_crtc *crtc)
906{
907 struct vc4_crtc_state *vc4_crtc_state;
908
909 if (crtc->state)
910 vc4_crtc_destroy_state(crtc, crtc->state);
911
912 vc4_crtc_state = kzalloc(sizeof(*vc4_crtc_state), GFP_KERNEL);
913 if (!vc4_crtc_state) {
914 crtc->state = NULL;
915 return;
916 }
917
918 vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;
919 __drm_atomic_helper_crtc_reset(crtc, &vc4_crtc_state->base);
920}
921
922static const struct drm_crtc_funcs vc4_crtc_funcs = {
923 .set_config = drm_atomic_helper_set_config,
924 .destroy = vc4_crtc_destroy,
925 .page_flip = vc4_page_flip,
926 .set_property = NULL,
927 .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
928 .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
929 .reset = vc4_crtc_reset,
930 .atomic_duplicate_state = vc4_crtc_duplicate_state,
931 .atomic_destroy_state = vc4_crtc_destroy_state,
932 .enable_vblank = vc4_enable_vblank,
933 .disable_vblank = vc4_disable_vblank,
934 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
935};
936
937static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
938 .mode_valid = vc4_crtc_mode_valid,
939 .atomic_check = vc4_crtc_atomic_check,
940 .atomic_flush = vc4_hvs_atomic_flush,
941 .atomic_enable = vc4_crtc_atomic_enable,
942 .atomic_disable = vc4_crtc_atomic_disable,
943 .get_scanout_position = vc4_crtc_get_scanout_position,
944};
945
946static const struct vc4_pv_data bcm2835_pv0_data = {
947 .base = {
948 .hvs_available_channels = BIT(0),
949 .hvs_output = 0,
950 },
951 .debugfs_name = "crtc0_regs",
952 .fifo_depth = 64,
953 .pixels_per_clock = 1,
954 .encoder_types = {
955 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
956 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
957 },
958};
959
960static const struct vc4_pv_data bcm2835_pv1_data = {
961 .base = {
962 .hvs_available_channels = BIT(2),
963 .hvs_output = 2,
964 },
965 .debugfs_name = "crtc1_regs",
966 .fifo_depth = 64,
967 .pixels_per_clock = 1,
968 .encoder_types = {
969 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
970 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
971 },
972};
973
974static const struct vc4_pv_data bcm2835_pv2_data = {
975 .base = {
976 .hvs_available_channels = BIT(1),
977 .hvs_output = 1,
978 },
979 .debugfs_name = "crtc2_regs",
980 .fifo_depth = 64,
981 .pixels_per_clock = 1,
982 .encoder_types = {
983 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI0,
984 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
985 },
986};
987
988static const struct vc4_pv_data bcm2711_pv0_data = {
989 .base = {
990 .hvs_available_channels = BIT(0),
991 .hvs_output = 0,
992 },
993 .debugfs_name = "crtc0_regs",
994 .fifo_depth = 64,
995 .pixels_per_clock = 1,
996 .encoder_types = {
997 [0] = VC4_ENCODER_TYPE_DSI0,
998 [1] = VC4_ENCODER_TYPE_DPI,
999 },
1000};
1001
1002static const struct vc4_pv_data bcm2711_pv1_data = {
1003 .base = {
1004 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1005 .hvs_output = 3,
1006 },
1007 .debugfs_name = "crtc1_regs",
1008 .fifo_depth = 64,
1009 .pixels_per_clock = 1,
1010 .encoder_types = {
1011 [0] = VC4_ENCODER_TYPE_DSI1,
1012 [1] = VC4_ENCODER_TYPE_SMI,
1013 },
1014};
1015
1016static const struct vc4_pv_data bcm2711_pv2_data = {
1017 .base = {
1018 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1019 .hvs_output = 4,
1020 },
1021 .debugfs_name = "crtc2_regs",
1022 .fifo_depth = 256,
1023 .pixels_per_clock = 2,
1024 .encoder_types = {
1025 [0] = VC4_ENCODER_TYPE_HDMI0,
1026 },
1027};
1028
1029static const struct vc4_pv_data bcm2711_pv3_data = {
1030 .base = {
1031 .hvs_available_channels = BIT(1),
1032 .hvs_output = 1,
1033 },
1034 .debugfs_name = "crtc3_regs",
1035 .fifo_depth = 64,
1036 .pixels_per_clock = 1,
1037 .encoder_types = {
1038 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1039 },
1040};
1041
1042static const struct vc4_pv_data bcm2711_pv4_data = {
1043 .base = {
1044 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1045 .hvs_output = 5,
1046 },
1047 .debugfs_name = "crtc4_regs",
1048 .fifo_depth = 64,
1049 .pixels_per_clock = 2,
1050 .encoder_types = {
1051 [0] = VC4_ENCODER_TYPE_HDMI1,
1052 },
1053};
1054
1055static const struct of_device_id vc4_crtc_dt_match[] = {
1056 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
1057 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
1058 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data },
1059 { .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data },
1060 { .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data },
1061 { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },
1062 { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },
1063 { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },
1064 {}
1065};
1066
1067static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1068 struct drm_crtc *crtc)
1069{
1070 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1071 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
1072 const enum vc4_encoder_type *encoder_types = pv_data->encoder_types;
1073 struct drm_encoder *encoder;
1074
1075 drm_for_each_encoder(encoder, drm) {
1076 struct vc4_encoder *vc4_encoder;
1077 int i;
1078
1079 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
1080 continue;
1081
1082 vc4_encoder = to_vc4_encoder(encoder);
1083 for (i = 0; i < ARRAY_SIZE(pv_data->encoder_types); i++) {
1084 if (vc4_encoder->type == encoder_types[i]) {
1085 vc4_encoder->clock_select = i;
1086 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1087 break;
1088 }
1089 }
1090 }
1091}
1092
1093int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
1094 const struct drm_crtc_funcs *crtc_funcs,
1095 const struct drm_crtc_helper_funcs *crtc_helper_funcs)
1096{
1097 struct vc4_dev *vc4 = to_vc4_dev(drm);
1098 struct drm_crtc *crtc = &vc4_crtc->base;
1099 struct drm_plane *primary_plane;
1100 unsigned int i;
1101
1102 /* For now, we create just the primary and the legacy cursor
1103 * planes. We should be able to stack more planes on easily,
1104 * but to do that we would need to compute the bandwidth
1105 * requirement of the plane configuration, and reject ones
1106 * that will take too much.
1107 */
1108 primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
1109 if (IS_ERR(primary_plane)) {
1110 dev_err(drm->dev, "failed to construct primary plane\n");
1111 return PTR_ERR(primary_plane);
1112 }
1113
1114 drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1115 crtc_funcs, NULL);
1116 drm_crtc_helper_add(crtc, crtc_helper_funcs);
1117
1118 if (!vc4->hvs->hvs5) {
1119 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1120
1121 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
1122
1123 /* We support CTM, but only for one CRTC at a time. It's therefore
1124 * implemented as private driver state in vc4_kms, not here.
1125 */
1126 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
1127 }
1128
1129 for (i = 0; i < crtc->gamma_size; i++) {
1130 vc4_crtc->lut_r[i] = i;
1131 vc4_crtc->lut_g[i] = i;
1132 vc4_crtc->lut_b[i] = i;
1133 }
1134
1135 return 0;
1136}
1137
1138static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1139{
1140 struct platform_device *pdev = to_platform_device(dev);
1141 struct drm_device *drm = dev_get_drvdata(master);
1142 const struct vc4_pv_data *pv_data;
1143 struct vc4_crtc *vc4_crtc;
1144 struct drm_crtc *crtc;
1145 struct drm_plane *destroy_plane, *temp;
1146 int ret;
1147
1148 vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
1149 if (!vc4_crtc)
1150 return -ENOMEM;
1151 crtc = &vc4_crtc->base;
1152
1153 pv_data = of_device_get_match_data(dev);
1154 if (!pv_data)
1155 return -ENODEV;
1156 vc4_crtc->data = &pv_data->base;
1157 vc4_crtc->pdev = pdev;
1158
1159 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1160 if (IS_ERR(vc4_crtc->regs))
1161 return PTR_ERR(vc4_crtc->regs);
1162
1163 vc4_crtc->regset.base = vc4_crtc->regs;
1164 vc4_crtc->regset.regs = crtc_regs;
1165 vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);
1166
1167 ret = vc4_crtc_init(drm, vc4_crtc,
1168 &vc4_crtc_funcs, &vc4_crtc_helper_funcs);
1169 if (ret)
1170 return ret;
1171 vc4_set_crtc_possible_masks(drm, crtc);
1172
1173 CRTC_WRITE(PV_INTEN, 0);
1174 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1175 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1176 vc4_crtc_irq_handler,
1177 IRQF_SHARED,
1178 "vc4 crtc", vc4_crtc);
1179 if (ret)
1180 goto err_destroy_planes;
1181
1182 platform_set_drvdata(pdev, vc4_crtc);
1183
1184 vc4_debugfs_add_regset32(drm, pv_data->debugfs_name,
1185 &vc4_crtc->regset);
1186
1187 return 0;
1188
1189err_destroy_planes:
1190 list_for_each_entry_safe(destroy_plane, temp,
1191 &drm->mode_config.plane_list, head) {
1192 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc))
1193 destroy_plane->funcs->destroy(destroy_plane);
1194 }
1195
1196 return ret;
1197}
1198
1199static void vc4_crtc_unbind(struct device *dev, struct device *master,
1200 void *data)
1201{
1202 struct platform_device *pdev = to_platform_device(dev);
1203 struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1204
1205 vc4_crtc_destroy(&vc4_crtc->base);
1206
1207 CRTC_WRITE(PV_INTEN, 0);
1208
1209 platform_set_drvdata(pdev, NULL);
1210}
1211
1212static const struct component_ops vc4_crtc_ops = {
1213 .bind = vc4_crtc_bind,
1214 .unbind = vc4_crtc_unbind,
1215};
1216
1217static int vc4_crtc_dev_probe(struct platform_device *pdev)
1218{
1219 return component_add(&pdev->dev, &vc4_crtc_ops);
1220}
1221
1222static int vc4_crtc_dev_remove(struct platform_device *pdev)
1223{
1224 component_del(&pdev->dev, &vc4_crtc_ops);
1225 return 0;
1226}
1227
1228struct platform_driver vc4_crtc_driver = {
1229 .probe = vc4_crtc_dev_probe,
1230 .remove = vc4_crtc_dev_remove,
1231 .driver = {
1232 .name = "vc4_crtc",
1233 .of_match_table = vc4_crtc_dt_match,
1234 },
1235};