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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 Broadcom
4 */
5
6/**
7 * DOC: VC4 CRTC module
8 *
9 * In VC4, the Pixel Valve is what most closely corresponds to the
10 * DRM's concept of a CRTC. The PV generates video timings from the
11 * encoder's clock plus its configuration. It pulls scaled pixels from
12 * the HVS at that timing, and feeds it to the encoder.
13 *
14 * However, the DRM CRTC also collects the configuration of all the
15 * DRM planes attached to it. As a result, the CRTC is also
16 * responsible for writing the display list for the HVS channel that
17 * the CRTC will use.
18 *
19 * The 2835 has 3 different pixel valves. pv0 in the audio power
20 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
21 * image domain can feed either HDMI or the SDTV controller. The
22 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
23 * SDTV, etc.) according to which output type is chosen in the mux.
24 *
25 * For power management, the pixel valve's registers are all clocked
26 * by the AXI clock, while the timings and FIFOs make use of the
27 * output-specific clock. Since the encoders also directly consume
28 * the CPRMAN clocks, and know what timings they need, they are the
29 * ones that set the clock.
30 */
31
32#include <linux/clk.h>
33#include <linux/component.h>
34#include <linux/of_device.h>
35
36#include <drm/drm_atomic.h>
37#include <drm/drm_atomic_helper.h>
38#include <drm/drm_atomic_uapi.h>
39#include <drm/drm_fb_cma_helper.h>
40#include <drm/drm_print.h>
41#include <drm/drm_probe_helper.h>
42#include <drm/drm_vblank.h>
43
44#include "vc4_drv.h"
45#include "vc4_regs.h"
46
47struct vc4_crtc_state {
48 struct drm_crtc_state base;
49 /* Dlist area for this CRTC configuration. */
50 struct drm_mm_node mm;
51 bool feed_txp;
52 bool txp_armed;
53
54 struct {
55 unsigned int left;
56 unsigned int right;
57 unsigned int top;
58 unsigned int bottom;
59 } margins;
60};
61
62static inline struct vc4_crtc_state *
63to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
64{
65 return (struct vc4_crtc_state *)crtc_state;
66}
67
68#define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
69#define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
70
71static const struct debugfs_reg32 crtc_regs[] = {
72 VC4_REG32(PV_CONTROL),
73 VC4_REG32(PV_V_CONTROL),
74 VC4_REG32(PV_VSYNCD_EVEN),
75 VC4_REG32(PV_HORZA),
76 VC4_REG32(PV_HORZB),
77 VC4_REG32(PV_VERTA),
78 VC4_REG32(PV_VERTB),
79 VC4_REG32(PV_VERTA_EVEN),
80 VC4_REG32(PV_VERTB_EVEN),
81 VC4_REG32(PV_INTEN),
82 VC4_REG32(PV_INTSTAT),
83 VC4_REG32(PV_STAT),
84 VC4_REG32(PV_HACT_ACT),
85};
86
87bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
88 bool in_vblank_irq, int *vpos, int *hpos,
89 ktime_t *stime, ktime_t *etime,
90 const struct drm_display_mode *mode)
91{
92 struct vc4_dev *vc4 = to_vc4_dev(dev);
93 struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
94 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
95 u32 val;
96 int fifo_lines;
97 int vblank_lines;
98 bool ret = false;
99
100 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
101
102 /* Get optional system timestamp before query. */
103 if (stime)
104 *stime = ktime_get();
105
106 /*
107 * Read vertical scanline which is currently composed for our
108 * pixelvalve by the HVS, and also the scaler status.
109 */
110 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
111
112 /* Get optional system timestamp after query. */
113 if (etime)
114 *etime = ktime_get();
115
116 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
117
118 /* Vertical position of hvs composed scanline. */
119 *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
120 *hpos = 0;
121
122 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
123 *vpos /= 2;
124
125 /* Use hpos to correct for field offset in interlaced mode. */
126 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
127 *hpos += mode->crtc_htotal / 2;
128 }
129
130 /* This is the offset we need for translating hvs -> pv scanout pos. */
131 fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
132
133 if (fifo_lines > 0)
134 ret = true;
135
136 /* HVS more than fifo_lines into frame for compositing? */
137 if (*vpos > fifo_lines) {
138 /*
139 * We are in active scanout and can get some meaningful results
140 * from HVS. The actual PV scanout can not trail behind more
141 * than fifo_lines as that is the fifo's capacity. Assume that
142 * in active scanout the HVS and PV work in lockstep wrt. HVS
143 * refilling the fifo and PV consuming from the fifo, ie.
144 * whenever the PV consumes and frees up a scanline in the
145 * fifo, the HVS will immediately refill it, therefore
146 * incrementing vpos. Therefore we choose HVS read position -
147 * fifo size in scanlines as a estimate of the real scanout
148 * position of the PV.
149 */
150 *vpos -= fifo_lines + 1;
151
152 return ret;
153 }
154
155 /*
156 * Less: This happens when we are in vblank and the HVS, after getting
157 * the VSTART restart signal from the PV, just started refilling its
158 * fifo with new lines from the top-most lines of the new framebuffers.
159 * The PV does not scan out in vblank, so does not remove lines from
160 * the fifo, so the fifo will be full quickly and the HVS has to pause.
161 * We can't get meaningful readings wrt. scanline position of the PV
162 * and need to make things up in a approximative but consistent way.
163 */
164 vblank_lines = mode->vtotal - mode->vdisplay;
165
166 if (in_vblank_irq) {
167 /*
168 * Assume the irq handler got called close to first
169 * line of vblank, so PV has about a full vblank
170 * scanlines to go, and as a base timestamp use the
171 * one taken at entry into vblank irq handler, so it
172 * is not affected by random delays due to lock
173 * contention on event_lock or vblank_time lock in
174 * the core.
175 */
176 *vpos = -vblank_lines;
177
178 if (stime)
179 *stime = vc4_crtc->t_vblank;
180 if (etime)
181 *etime = vc4_crtc->t_vblank;
182
183 /*
184 * If the HVS fifo is not yet full then we know for certain
185 * we are at the very beginning of vblank, as the hvs just
186 * started refilling, and the stime and etime timestamps
187 * truly correspond to start of vblank.
188 *
189 * Unfortunately there's no way to report this to upper levels
190 * and make it more useful.
191 */
192 } else {
193 /*
194 * No clue where we are inside vblank. Return a vpos of zero,
195 * which will cause calling code to just return the etime
196 * timestamp uncorrected. At least this is no worse than the
197 * standard fallback.
198 */
199 *vpos = 0;
200 }
201
202 return ret;
203}
204
205static void vc4_crtc_destroy(struct drm_crtc *crtc)
206{
207 drm_crtc_cleanup(crtc);
208}
209
210static void
211vc4_crtc_lut_load(struct drm_crtc *crtc)
212{
213 struct drm_device *dev = crtc->dev;
214 struct vc4_dev *vc4 = to_vc4_dev(dev);
215 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
216 u32 i;
217
218 /* The LUT memory is laid out with each HVS channel in order,
219 * each of which takes 256 writes for R, 256 for G, then 256
220 * for B.
221 */
222 HVS_WRITE(SCALER_GAMADDR,
223 SCALER_GAMADDR_AUTOINC |
224 (vc4_crtc->channel * 3 * crtc->gamma_size));
225
226 for (i = 0; i < crtc->gamma_size; i++)
227 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
228 for (i = 0; i < crtc->gamma_size; i++)
229 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
230 for (i = 0; i < crtc->gamma_size; i++)
231 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
232}
233
234static void
235vc4_crtc_update_gamma_lut(struct drm_crtc *crtc)
236{
237 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
238 struct drm_color_lut *lut = crtc->state->gamma_lut->data;
239 u32 length = drm_color_lut_size(crtc->state->gamma_lut);
240 u32 i;
241
242 for (i = 0; i < length; i++) {
243 vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8);
244 vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8);
245 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8);
246 }
247
248 vc4_crtc_lut_load(crtc);
249}
250
251static u32 vc4_get_fifo_full_level(u32 format)
252{
253 static const u32 fifo_len_bytes = 64;
254 static const u32 hvs_latency_pix = 6;
255
256 switch (format) {
257 case PV_CONTROL_FORMAT_DSIV_16:
258 case PV_CONTROL_FORMAT_DSIC_16:
259 return fifo_len_bytes - 2 * hvs_latency_pix;
260 case PV_CONTROL_FORMAT_DSIV_18:
261 return fifo_len_bytes - 14;
262 case PV_CONTROL_FORMAT_24:
263 case PV_CONTROL_FORMAT_DSIV_24:
264 default:
265 return fifo_len_bytes - 3 * hvs_latency_pix;
266 }
267}
268
269/*
270 * Returns the encoder attached to the CRTC.
271 *
272 * VC4 can only scan out to one encoder at a time, while the DRM core
273 * allows drivers to push pixels to more than one encoder from the
274 * same CRTC.
275 */
276static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
277{
278 struct drm_connector *connector;
279 struct drm_connector_list_iter conn_iter;
280
281 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
282 drm_for_each_connector_iter(connector, &conn_iter) {
283 if (connector->state->crtc == crtc) {
284 drm_connector_list_iter_end(&conn_iter);
285 return connector->encoder;
286 }
287 }
288 drm_connector_list_iter_end(&conn_iter);
289
290 return NULL;
291}
292
293static void vc4_crtc_config_pv(struct drm_crtc *crtc)
294{
295 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
296 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
297 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
298 struct drm_crtc_state *state = crtc->state;
299 struct drm_display_mode *mode = &state->adjusted_mode;
300 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
301 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
302 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
303 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
304 u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
305
306 /* Reset the PV fifo. */
307 CRTC_WRITE(PV_CONTROL, 0);
308 CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
309 CRTC_WRITE(PV_CONTROL, 0);
310
311 CRTC_WRITE(PV_HORZA,
312 VC4_SET_FIELD((mode->htotal -
313 mode->hsync_end) * pixel_rep,
314 PV_HORZA_HBP) |
315 VC4_SET_FIELD((mode->hsync_end -
316 mode->hsync_start) * pixel_rep,
317 PV_HORZA_HSYNC));
318 CRTC_WRITE(PV_HORZB,
319 VC4_SET_FIELD((mode->hsync_start -
320 mode->hdisplay) * pixel_rep,
321 PV_HORZB_HFP) |
322 VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
323
324 CRTC_WRITE(PV_VERTA,
325 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
326 PV_VERTA_VBP) |
327 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
328 PV_VERTA_VSYNC));
329 CRTC_WRITE(PV_VERTB,
330 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
331 PV_VERTB_VFP) |
332 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
333
334 if (interlace) {
335 CRTC_WRITE(PV_VERTA_EVEN,
336 VC4_SET_FIELD(mode->crtc_vtotal -
337 mode->crtc_vsync_end - 1,
338 PV_VERTA_VBP) |
339 VC4_SET_FIELD(mode->crtc_vsync_end -
340 mode->crtc_vsync_start,
341 PV_VERTA_VSYNC));
342 CRTC_WRITE(PV_VERTB_EVEN,
343 VC4_SET_FIELD(mode->crtc_vsync_start -
344 mode->crtc_vdisplay,
345 PV_VERTB_VFP) |
346 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
347
348 /* We set up first field even mode for HDMI. VEC's
349 * NTSC mode would want first field odd instead, once
350 * we support it (to do so, set ODD_FIRST and put the
351 * delay in VSYNCD_EVEN instead).
352 */
353 CRTC_WRITE(PV_V_CONTROL,
354 PV_VCONTROL_CONTINUOUS |
355 (is_dsi ? PV_VCONTROL_DSI : 0) |
356 PV_VCONTROL_INTERLACE |
357 VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
358 PV_VCONTROL_ODD_DELAY));
359 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
360 } else {
361 CRTC_WRITE(PV_V_CONTROL,
362 PV_VCONTROL_CONTINUOUS |
363 (is_dsi ? PV_VCONTROL_DSI : 0));
364 }
365
366 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
367
368 CRTC_WRITE(PV_CONTROL,
369 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
370 VC4_SET_FIELD(vc4_get_fifo_full_level(format),
371 PV_CONTROL_FIFO_LEVEL) |
372 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
373 PV_CONTROL_CLR_AT_START |
374 PV_CONTROL_TRIGGER_UNDERFLOW |
375 PV_CONTROL_WAIT_HSTART |
376 VC4_SET_FIELD(vc4_encoder->clock_select,
377 PV_CONTROL_CLK_SELECT) |
378 PV_CONTROL_FIFO_CLR |
379 PV_CONTROL_EN);
380}
381
382static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
383{
384 struct drm_device *dev = crtc->dev;
385 struct vc4_dev *vc4 = to_vc4_dev(dev);
386 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
387 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
388 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
389 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
390 bool debug_dump_regs = false;
391
392 if (debug_dump_regs) {
393 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
394 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",
395 drm_crtc_index(crtc));
396 drm_print_regset32(&p, &vc4_crtc->regset);
397 }
398
399 if (vc4_crtc->channel == 2) {
400 u32 dispctrl;
401 u32 dsp3_mux;
402
403 /*
404 * SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
405 * FIFO X'.
406 * SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
407 *
408 * DSP3 is connected to FIFO2 unless the transposer is
409 * enabled. In this case, FIFO 2 is directly accessed by the
410 * TXP IP, and we need to disable the FIFO2 -> pixelvalve1
411 * route.
412 */
413 if (vc4_state->feed_txp)
414 dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
415 else
416 dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
417
418 dispctrl = HVS_READ(SCALER_DISPCTRL) &
419 ~SCALER_DISPCTRL_DSP3_MUX_MASK;
420 HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
421 }
422
423 if (!vc4_state->feed_txp)
424 vc4_crtc_config_pv(crtc);
425
426 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
427 SCALER_DISPBKGND_AUTOHS |
428 SCALER_DISPBKGND_GAMMA |
429 (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
430
431 /* Reload the LUT, since the SRAMs would have been disabled if
432 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
433 */
434 vc4_crtc_lut_load(crtc);
435
436 if (debug_dump_regs) {
437 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
438 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",
439 drm_crtc_index(crtc));
440 drm_print_regset32(&p, &vc4_crtc->regset);
441 }
442}
443
444static void require_hvs_enabled(struct drm_device *dev)
445{
446 struct vc4_dev *vc4 = to_vc4_dev(dev);
447
448 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
449 SCALER_DISPCTRL_ENABLE);
450}
451
452static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
453 struct drm_crtc_state *old_state)
454{
455 struct drm_device *dev = crtc->dev;
456 struct vc4_dev *vc4 = to_vc4_dev(dev);
457 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
458 u32 chan = vc4_crtc->channel;
459 int ret;
460 require_hvs_enabled(dev);
461
462 /* Disable vblank irq handling before crtc is disabled. */
463 drm_crtc_vblank_off(crtc);
464
465 CRTC_WRITE(PV_V_CONTROL,
466 CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
467 ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
468 WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
469
470 if (HVS_READ(SCALER_DISPCTRLX(chan)) &
471 SCALER_DISPCTRLX_ENABLE) {
472 HVS_WRITE(SCALER_DISPCTRLX(chan),
473 SCALER_DISPCTRLX_RESET);
474
475 /* While the docs say that reset is self-clearing, it
476 * seems it doesn't actually.
477 */
478 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
479 }
480
481 /* Once we leave, the scaler should be disabled and its fifo empty. */
482
483 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
484
485 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
486 SCALER_DISPSTATX_MODE) !=
487 SCALER_DISPSTATX_MODE_DISABLED);
488
489 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
490 (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
491 SCALER_DISPSTATX_EMPTY);
492
493 /*
494 * Make sure we issue a vblank event after disabling the CRTC if
495 * someone was waiting it.
496 */
497 if (crtc->state->event) {
498 unsigned long flags;
499
500 spin_lock_irqsave(&dev->event_lock, flags);
501 drm_crtc_send_vblank_event(crtc, crtc->state->event);
502 crtc->state->event = NULL;
503 spin_unlock_irqrestore(&dev->event_lock, flags);
504 }
505}
506
507void vc4_crtc_txp_armed(struct drm_crtc_state *state)
508{
509 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
510
511 vc4_state->txp_armed = true;
512}
513
514static void vc4_crtc_update_dlist(struct drm_crtc *crtc)
515{
516 struct drm_device *dev = crtc->dev;
517 struct vc4_dev *vc4 = to_vc4_dev(dev);
518 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
519 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
520
521 if (crtc->state->event) {
522 unsigned long flags;
523
524 crtc->state->event->pipe = drm_crtc_index(crtc);
525
526 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
527
528 spin_lock_irqsave(&dev->event_lock, flags);
529
530 if (!vc4_state->feed_txp || vc4_state->txp_armed) {
531 vc4_crtc->event = crtc->state->event;
532 crtc->state->event = NULL;
533 }
534
535 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
536 vc4_state->mm.start);
537
538 spin_unlock_irqrestore(&dev->event_lock, flags);
539 } else {
540 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
541 vc4_state->mm.start);
542 }
543}
544
545static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
546 struct drm_crtc_state *old_state)
547{
548 struct drm_device *dev = crtc->dev;
549 struct vc4_dev *vc4 = to_vc4_dev(dev);
550 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
551 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
552 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
553
554 require_hvs_enabled(dev);
555
556 /* Enable vblank irq handling before crtc is started otherwise
557 * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
558 */
559 drm_crtc_vblank_on(crtc);
560 vc4_crtc_update_dlist(crtc);
561
562 /* Turn on the scaler, which will wait for vstart to start
563 * compositing.
564 * When feeding the transposer, we should operate in oneshot
565 * mode.
566 */
567 HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
568 VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
569 VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
570 SCALER_DISPCTRLX_ENABLE |
571 (vc4_state->feed_txp ? SCALER_DISPCTRLX_ONESHOT : 0));
572
573 /* When feeding the transposer block the pixelvalve is unneeded and
574 * should not be enabled.
575 */
576 if (!vc4_state->feed_txp)
577 CRTC_WRITE(PV_V_CONTROL,
578 CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
579}
580
581static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
582 const struct drm_display_mode *mode)
583{
584 /* Do not allow doublescan modes from user space */
585 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
586 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
587 crtc->base.id);
588 return MODE_NO_DBLESCAN;
589 }
590
591 return MODE_OK;
592}
593
594void vc4_crtc_get_margins(struct drm_crtc_state *state,
595 unsigned int *left, unsigned int *right,
596 unsigned int *top, unsigned int *bottom)
597{
598 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
599 struct drm_connector_state *conn_state;
600 struct drm_connector *conn;
601 int i;
602
603 *left = vc4_state->margins.left;
604 *right = vc4_state->margins.right;
605 *top = vc4_state->margins.top;
606 *bottom = vc4_state->margins.bottom;
607
608 /* We have to interate over all new connector states because
609 * vc4_crtc_get_margins() might be called before
610 * vc4_crtc_atomic_check() which means margins info in vc4_crtc_state
611 * might be outdated.
612 */
613 for_each_new_connector_in_state(state->state, conn, conn_state, i) {
614 if (conn_state->crtc != state->crtc)
615 continue;
616
617 *left = conn_state->tv.margins.left;
618 *right = conn_state->tv.margins.right;
619 *top = conn_state->tv.margins.top;
620 *bottom = conn_state->tv.margins.bottom;
621 break;
622 }
623}
624
625static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
626 struct drm_crtc_state *state)
627{
628 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
629 struct drm_device *dev = crtc->dev;
630 struct vc4_dev *vc4 = to_vc4_dev(dev);
631 struct drm_plane *plane;
632 unsigned long flags;
633 const struct drm_plane_state *plane_state;
634 struct drm_connector *conn;
635 struct drm_connector_state *conn_state;
636 u32 dlist_count = 0;
637 int ret, i;
638
639 /* The pixelvalve can only feed one encoder (and encoders are
640 * 1:1 with connectors.)
641 */
642 if (hweight32(state->connector_mask) > 1)
643 return -EINVAL;
644
645 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
646 dlist_count += vc4_plane_dlist_size(plane_state);
647
648 dlist_count++; /* Account for SCALER_CTL0_END. */
649
650 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
651 ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
652 dlist_count);
653 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
654 if (ret)
655 return ret;
656
657 for_each_new_connector_in_state(state->state, conn, conn_state, i) {
658 if (conn_state->crtc != crtc)
659 continue;
660
661 /* The writeback connector is implemented using the transposer
662 * block which is directly taking its data from the HVS FIFO.
663 */
664 if (conn->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) {
665 state->no_vblank = true;
666 vc4_state->feed_txp = true;
667 } else {
668 state->no_vblank = false;
669 vc4_state->feed_txp = false;
670 }
671
672 vc4_state->margins.left = conn_state->tv.margins.left;
673 vc4_state->margins.right = conn_state->tv.margins.right;
674 vc4_state->margins.top = conn_state->tv.margins.top;
675 vc4_state->margins.bottom = conn_state->tv.margins.bottom;
676 break;
677 }
678
679 return 0;
680}
681
682static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
683 struct drm_crtc_state *old_state)
684{
685 struct drm_device *dev = crtc->dev;
686 struct vc4_dev *vc4 = to_vc4_dev(dev);
687 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
688 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
689 struct drm_plane *plane;
690 struct vc4_plane_state *vc4_plane_state;
691 bool debug_dump_regs = false;
692 bool enable_bg_fill = false;
693 u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
694 u32 __iomem *dlist_next = dlist_start;
695
696 if (debug_dump_regs) {
697 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
698 vc4_hvs_dump_state(dev);
699 }
700
701 /* Copy all the active planes' dlist contents to the hardware dlist. */
702 drm_atomic_crtc_for_each_plane(plane, crtc) {
703 /* Is this the first active plane? */
704 if (dlist_next == dlist_start) {
705 /* We need to enable background fill when a plane
706 * could be alpha blending from the background, i.e.
707 * where no other plane is underneath. It suffices to
708 * consider the first active plane here since we set
709 * needs_bg_fill such that either the first plane
710 * already needs it or all planes on top blend from
711 * the first or a lower plane.
712 */
713 vc4_plane_state = to_vc4_plane_state(plane->state);
714 enable_bg_fill = vc4_plane_state->needs_bg_fill;
715 }
716
717 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
718 }
719
720 writel(SCALER_CTL0_END, dlist_next);
721 dlist_next++;
722
723 WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
724
725 if (enable_bg_fill)
726 /* This sets a black background color fill, as is the case
727 * with other DRM drivers.
728 */
729 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
730 HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) |
731 SCALER_DISPBKGND_FILL);
732
733 /* Only update DISPLIST if the CRTC was already running and is not
734 * being disabled.
735 * vc4_crtc_enable() takes care of updating the dlist just after
736 * re-enabling VBLANK interrupts and before enabling the engine.
737 * If the CRTC is being disabled, there's no point in updating this
738 * information.
739 */
740 if (crtc->state->active && old_state->active)
741 vc4_crtc_update_dlist(crtc);
742
743 if (crtc->state->color_mgmt_changed) {
744 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel));
745
746 if (crtc->state->gamma_lut) {
747 vc4_crtc_update_gamma_lut(crtc);
748 dispbkgndx |= SCALER_DISPBKGND_GAMMA;
749 } else {
750 /* Unsetting DISPBKGND_GAMMA skips the gamma lut step
751 * in hardware, which is the same as a linear lut that
752 * DRM expects us to use in absence of a user lut.
753 */
754 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
755 }
756 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), dispbkgndx);
757 }
758
759 if (debug_dump_regs) {
760 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
761 vc4_hvs_dump_state(dev);
762 }
763}
764
765static int vc4_enable_vblank(struct drm_crtc *crtc)
766{
767 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
768
769 CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
770
771 return 0;
772}
773
774static void vc4_disable_vblank(struct drm_crtc *crtc)
775{
776 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
777
778 CRTC_WRITE(PV_INTEN, 0);
779}
780
781static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
782{
783 struct drm_crtc *crtc = &vc4_crtc->base;
784 struct drm_device *dev = crtc->dev;
785 struct vc4_dev *vc4 = to_vc4_dev(dev);
786 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
787 u32 chan = vc4_crtc->channel;
788 unsigned long flags;
789
790 spin_lock_irqsave(&dev->event_lock, flags);
791 if (vc4_crtc->event &&
792 (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)) ||
793 vc4_state->feed_txp)) {
794 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
795 vc4_crtc->event = NULL;
796 drm_crtc_vblank_put(crtc);
797
798 /* Wait for the page flip to unmask the underrun to ensure that
799 * the display list was updated by the hardware. Before that
800 * happens, the HVS will be using the previous display list with
801 * the CRTC and encoder already reconfigured, leading to
802 * underruns. This can be seen when reconfiguring the CRTC.
803 */
804 vc4_hvs_unmask_underrun(dev, vc4_crtc->channel);
805 }
806 spin_unlock_irqrestore(&dev->event_lock, flags);
807}
808
809void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
810{
811 crtc->t_vblank = ktime_get();
812 drm_crtc_handle_vblank(&crtc->base);
813 vc4_crtc_handle_page_flip(crtc);
814}
815
816static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
817{
818 struct vc4_crtc *vc4_crtc = data;
819 u32 stat = CRTC_READ(PV_INTSTAT);
820 irqreturn_t ret = IRQ_NONE;
821
822 if (stat & PV_INT_VFP_START) {
823 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
824 vc4_crtc_handle_vblank(vc4_crtc);
825 ret = IRQ_HANDLED;
826 }
827
828 return ret;
829}
830
831struct vc4_async_flip_state {
832 struct drm_crtc *crtc;
833 struct drm_framebuffer *fb;
834 struct drm_framebuffer *old_fb;
835 struct drm_pending_vblank_event *event;
836
837 struct vc4_seqno_cb cb;
838};
839
840/* Called when the V3D execution for the BO being flipped to is done, so that
841 * we can actually update the plane's address to point to it.
842 */
843static void
844vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
845{
846 struct vc4_async_flip_state *flip_state =
847 container_of(cb, struct vc4_async_flip_state, cb);
848 struct drm_crtc *crtc = flip_state->crtc;
849 struct drm_device *dev = crtc->dev;
850 struct vc4_dev *vc4 = to_vc4_dev(dev);
851 struct drm_plane *plane = crtc->primary;
852
853 vc4_plane_async_set_fb(plane, flip_state->fb);
854 if (flip_state->event) {
855 unsigned long flags;
856
857 spin_lock_irqsave(&dev->event_lock, flags);
858 drm_crtc_send_vblank_event(crtc, flip_state->event);
859 spin_unlock_irqrestore(&dev->event_lock, flags);
860 }
861
862 drm_crtc_vblank_put(crtc);
863 drm_framebuffer_put(flip_state->fb);
864
865 /* Decrement the BO usecnt in order to keep the inc/dec calls balanced
866 * when the planes are updated through the async update path.
867 * FIXME: we should move to generic async-page-flip when it's
868 * available, so that we can get rid of this hand-made cleanup_fb()
869 * logic.
870 */
871 if (flip_state->old_fb) {
872 struct drm_gem_cma_object *cma_bo;
873 struct vc4_bo *bo;
874
875 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
876 bo = to_vc4_bo(&cma_bo->base);
877 vc4_bo_dec_usecnt(bo);
878 drm_framebuffer_put(flip_state->old_fb);
879 }
880
881 kfree(flip_state);
882
883 up(&vc4->async_modeset);
884}
885
886/* Implements async (non-vblank-synced) page flips.
887 *
888 * The page flip ioctl needs to return immediately, so we grab the
889 * modeset semaphore on the pipe, and queue the address update for
890 * when V3D is done with the BO being flipped to.
891 */
892static int vc4_async_page_flip(struct drm_crtc *crtc,
893 struct drm_framebuffer *fb,
894 struct drm_pending_vblank_event *event,
895 uint32_t flags)
896{
897 struct drm_device *dev = crtc->dev;
898 struct vc4_dev *vc4 = to_vc4_dev(dev);
899 struct drm_plane *plane = crtc->primary;
900 int ret = 0;
901 struct vc4_async_flip_state *flip_state;
902 struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
903 struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
904
905 /* Increment the BO usecnt here, so that we never end up with an
906 * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
907 * plane is later updated through the non-async path.
908 * FIXME: we should move to generic async-page-flip when it's
909 * available, so that we can get rid of this hand-made prepare_fb()
910 * logic.
911 */
912 ret = vc4_bo_inc_usecnt(bo);
913 if (ret)
914 return ret;
915
916 flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
917 if (!flip_state) {
918 vc4_bo_dec_usecnt(bo);
919 return -ENOMEM;
920 }
921
922 drm_framebuffer_get(fb);
923 flip_state->fb = fb;
924 flip_state->crtc = crtc;
925 flip_state->event = event;
926
927 /* Make sure all other async modesetes have landed. */
928 ret = down_interruptible(&vc4->async_modeset);
929 if (ret) {
930 drm_framebuffer_put(fb);
931 vc4_bo_dec_usecnt(bo);
932 kfree(flip_state);
933 return ret;
934 }
935
936 /* Save the current FB before it's replaced by the new one in
937 * drm_atomic_set_fb_for_plane(). We'll need the old FB in
938 * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
939 * it consistent.
940 * FIXME: we should move to generic async-page-flip when it's
941 * available, so that we can get rid of this hand-made cleanup_fb()
942 * logic.
943 */
944 flip_state->old_fb = plane->state->fb;
945 if (flip_state->old_fb)
946 drm_framebuffer_get(flip_state->old_fb);
947
948 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
949
950 /* Immediately update the plane's legacy fb pointer, so that later
951 * modeset prep sees the state that will be present when the semaphore
952 * is released.
953 */
954 drm_atomic_set_fb_for_plane(plane->state, fb);
955
956 vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
957 vc4_async_page_flip_complete);
958
959 /* Driver takes ownership of state on successful async commit. */
960 return 0;
961}
962
963static int vc4_page_flip(struct drm_crtc *crtc,
964 struct drm_framebuffer *fb,
965 struct drm_pending_vblank_event *event,
966 uint32_t flags,
967 struct drm_modeset_acquire_ctx *ctx)
968{
969 if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
970 return vc4_async_page_flip(crtc, fb, event, flags);
971 else
972 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
973}
974
975static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
976{
977 struct vc4_crtc_state *vc4_state, *old_vc4_state;
978
979 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
980 if (!vc4_state)
981 return NULL;
982
983 old_vc4_state = to_vc4_crtc_state(crtc->state);
984 vc4_state->feed_txp = old_vc4_state->feed_txp;
985 vc4_state->margins = old_vc4_state->margins;
986
987 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
988 return &vc4_state->base;
989}
990
991static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
992 struct drm_crtc_state *state)
993{
994 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
995 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
996
997 if (vc4_state->mm.allocated) {
998 unsigned long flags;
999
1000 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
1001 drm_mm_remove_node(&vc4_state->mm);
1002 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
1003
1004 }
1005
1006 drm_atomic_helper_crtc_destroy_state(crtc, state);
1007}
1008
1009static void
1010vc4_crtc_reset(struct drm_crtc *crtc)
1011{
1012 if (crtc->state)
1013 vc4_crtc_destroy_state(crtc, crtc->state);
1014
1015 crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL);
1016 if (crtc->state)
1017 crtc->state->crtc = crtc;
1018}
1019
1020static const struct drm_crtc_funcs vc4_crtc_funcs = {
1021 .set_config = drm_atomic_helper_set_config,
1022 .destroy = vc4_crtc_destroy,
1023 .page_flip = vc4_page_flip,
1024 .set_property = NULL,
1025 .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
1026 .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
1027 .reset = vc4_crtc_reset,
1028 .atomic_duplicate_state = vc4_crtc_duplicate_state,
1029 .atomic_destroy_state = vc4_crtc_destroy_state,
1030 .gamma_set = drm_atomic_helper_legacy_gamma_set,
1031 .enable_vblank = vc4_enable_vblank,
1032 .disable_vblank = vc4_disable_vblank,
1033};
1034
1035static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
1036 .mode_set_nofb = vc4_crtc_mode_set_nofb,
1037 .mode_valid = vc4_crtc_mode_valid,
1038 .atomic_check = vc4_crtc_atomic_check,
1039 .atomic_flush = vc4_crtc_atomic_flush,
1040 .atomic_enable = vc4_crtc_atomic_enable,
1041 .atomic_disable = vc4_crtc_atomic_disable,
1042};
1043
1044static const struct vc4_crtc_data pv0_data = {
1045 .hvs_channel = 0,
1046 .debugfs_name = "crtc0_regs",
1047 .encoder_types = {
1048 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
1049 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
1050 },
1051};
1052
1053static const struct vc4_crtc_data pv1_data = {
1054 .hvs_channel = 2,
1055 .debugfs_name = "crtc1_regs",
1056 .encoder_types = {
1057 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
1058 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
1059 },
1060};
1061
1062static const struct vc4_crtc_data pv2_data = {
1063 .hvs_channel = 1,
1064 .debugfs_name = "crtc2_regs",
1065 .encoder_types = {
1066 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
1067 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1068 },
1069};
1070
1071static const struct of_device_id vc4_crtc_dt_match[] = {
1072 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
1073 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
1074 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
1075 {}
1076};
1077
1078static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1079 struct drm_crtc *crtc)
1080{
1081 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1082 const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
1083 const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
1084 struct drm_encoder *encoder;
1085
1086 drm_for_each_encoder(encoder, drm) {
1087 struct vc4_encoder *vc4_encoder;
1088 int i;
1089
1090 /* HVS FIFO2 can feed the TXP IP. */
1091 if (crtc_data->hvs_channel == 2 &&
1092 encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) {
1093 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1094 continue;
1095 }
1096
1097 vc4_encoder = to_vc4_encoder(encoder);
1098 for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
1099 if (vc4_encoder->type == encoder_types[i]) {
1100 vc4_encoder->clock_select = i;
1101 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1102 break;
1103 }
1104 }
1105 }
1106}
1107
1108static void
1109vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
1110{
1111 struct drm_device *drm = vc4_crtc->base.dev;
1112 struct vc4_dev *vc4 = to_vc4_dev(drm);
1113 u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
1114 /* Top/base are supposed to be 4-pixel aligned, but the
1115 * Raspberry Pi firmware fills the low bits (which are
1116 * presumably ignored).
1117 */
1118 u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
1119 u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
1120
1121 vc4_crtc->cob_size = top - base + 4;
1122}
1123
1124static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1125{
1126 struct platform_device *pdev = to_platform_device(dev);
1127 struct drm_device *drm = dev_get_drvdata(master);
1128 struct vc4_crtc *vc4_crtc;
1129 struct drm_crtc *crtc;
1130 struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
1131 const struct of_device_id *match;
1132 int ret, i;
1133
1134 vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
1135 if (!vc4_crtc)
1136 return -ENOMEM;
1137 crtc = &vc4_crtc->base;
1138
1139 match = of_match_device(vc4_crtc_dt_match, dev);
1140 if (!match)
1141 return -ENODEV;
1142 vc4_crtc->data = match->data;
1143 vc4_crtc->pdev = pdev;
1144
1145 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1146 if (IS_ERR(vc4_crtc->regs))
1147 return PTR_ERR(vc4_crtc->regs);
1148
1149 vc4_crtc->regset.base = vc4_crtc->regs;
1150 vc4_crtc->regset.regs = crtc_regs;
1151 vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);
1152
1153 /* For now, we create just the primary and the legacy cursor
1154 * planes. We should be able to stack more planes on easily,
1155 * but to do that we would need to compute the bandwidth
1156 * requirement of the plane configuration, and reject ones
1157 * that will take too much.
1158 */
1159 primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
1160 if (IS_ERR(primary_plane)) {
1161 dev_err(dev, "failed to construct primary plane\n");
1162 ret = PTR_ERR(primary_plane);
1163 goto err;
1164 }
1165
1166 drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1167 &vc4_crtc_funcs, NULL);
1168 drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
1169 vc4_crtc->channel = vc4_crtc->data->hvs_channel;
1170 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1171 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
1172
1173 /* We support CTM, but only for one CRTC at a time. It's therefore
1174 * implemented as private driver state in vc4_kms, not here.
1175 */
1176 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
1177
1178 /* Set up some arbitrary number of planes. We're not limited
1179 * by a set number of physical registers, just the space in
1180 * the HVS (16k) and how small an plane can be (28 bytes).
1181 * However, each plane we set up takes up some memory, and
1182 * increases the cost of looping over planes, which atomic
1183 * modesetting does quite a bit. As a result, we pick a
1184 * modest number of planes to expose, that should hopefully
1185 * still cover any sane usecase.
1186 */
1187 for (i = 0; i < 8; i++) {
1188 struct drm_plane *plane =
1189 vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
1190
1191 if (IS_ERR(plane))
1192 continue;
1193
1194 plane->possible_crtcs = drm_crtc_mask(crtc);
1195 }
1196
1197 /* Set up the legacy cursor after overlay initialization,
1198 * since we overlay planes on the CRTC in the order they were
1199 * initialized.
1200 */
1201 cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1202 if (!IS_ERR(cursor_plane)) {
1203 cursor_plane->possible_crtcs = drm_crtc_mask(crtc);
1204 crtc->cursor = cursor_plane;
1205 }
1206
1207 vc4_crtc_get_cob_allocation(vc4_crtc);
1208
1209 CRTC_WRITE(PV_INTEN, 0);
1210 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1211 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1212 vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
1213 if (ret)
1214 goto err_destroy_planes;
1215
1216 vc4_set_crtc_possible_masks(drm, crtc);
1217
1218 for (i = 0; i < crtc->gamma_size; i++) {
1219 vc4_crtc->lut_r[i] = i;
1220 vc4_crtc->lut_g[i] = i;
1221 vc4_crtc->lut_b[i] = i;
1222 }
1223
1224 platform_set_drvdata(pdev, vc4_crtc);
1225
1226 vc4_debugfs_add_regset32(drm, vc4_crtc->data->debugfs_name,
1227 &vc4_crtc->regset);
1228
1229 return 0;
1230
1231err_destroy_planes:
1232 list_for_each_entry_safe(destroy_plane, temp,
1233 &drm->mode_config.plane_list, head) {
1234 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc))
1235 destroy_plane->funcs->destroy(destroy_plane);
1236 }
1237err:
1238 return ret;
1239}
1240
1241static void vc4_crtc_unbind(struct device *dev, struct device *master,
1242 void *data)
1243{
1244 struct platform_device *pdev = to_platform_device(dev);
1245 struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1246
1247 vc4_crtc_destroy(&vc4_crtc->base);
1248
1249 CRTC_WRITE(PV_INTEN, 0);
1250
1251 platform_set_drvdata(pdev, NULL);
1252}
1253
1254static const struct component_ops vc4_crtc_ops = {
1255 .bind = vc4_crtc_bind,
1256 .unbind = vc4_crtc_unbind,
1257};
1258
1259static int vc4_crtc_dev_probe(struct platform_device *pdev)
1260{
1261 return component_add(&pdev->dev, &vc4_crtc_ops);
1262}
1263
1264static int vc4_crtc_dev_remove(struct platform_device *pdev)
1265{
1266 component_del(&pdev->dev, &vc4_crtc_ops);
1267 return 0;
1268}
1269
1270struct platform_driver vc4_crtc_driver = {
1271 .probe = vc4_crtc_dev_probe,
1272 .remove = vc4_crtc_dev_remove,
1273 .driver = {
1274 .name = "vc4_crtc",
1275 .of_match_table = vc4_crtc_dt_match,
1276 },
1277};
1/*
2 * Copyright (C) 2015 Broadcom
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/**
10 * DOC: VC4 CRTC module
11 *
12 * In VC4, the Pixel Valve is what most closely corresponds to the
13 * DRM's concept of a CRTC. The PV generates video timings from the
14 * encoder's clock plus its configuration. It pulls scaled pixels from
15 * the HVS at that timing, and feeds it to the encoder.
16 *
17 * However, the DRM CRTC also collects the configuration of all the
18 * DRM planes attached to it. As a result, the CRTC is also
19 * responsible for writing the display list for the HVS channel that
20 * the CRTC will use.
21 *
22 * The 2835 has 3 different pixel valves. pv0 in the audio power
23 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
24 * image domain can feed either HDMI or the SDTV controller. The
25 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
26 * SDTV, etc.) according to which output type is chosen in the mux.
27 *
28 * For power management, the pixel valve's registers are all clocked
29 * by the AXI clock, while the timings and FIFOs make use of the
30 * output-specific clock. Since the encoders also directly consume
31 * the CPRMAN clocks, and know what timings they need, they are the
32 * ones that set the clock.
33 */
34
35#include <drm/drm_atomic.h>
36#include <drm/drm_atomic_helper.h>
37#include <drm/drm_crtc_helper.h>
38#include <linux/clk.h>
39#include <drm/drm_fb_cma_helper.h>
40#include <linux/component.h>
41#include <linux/of_device.h>
42#include "vc4_drv.h"
43#include "vc4_regs.h"
44
45struct vc4_crtc {
46 struct drm_crtc base;
47 const struct vc4_crtc_data *data;
48 void __iomem *regs;
49
50 /* Timestamp at start of vblank irq - unaffected by lock delays. */
51 ktime_t t_vblank;
52
53 /* Which HVS channel we're using for our CRTC. */
54 int channel;
55
56 u8 lut_r[256];
57 u8 lut_g[256];
58 u8 lut_b[256];
59 /* Size in pixels of the COB memory allocated to this CRTC. */
60 u32 cob_size;
61
62 struct drm_pending_vblank_event *event;
63};
64
65struct vc4_crtc_state {
66 struct drm_crtc_state base;
67 /* Dlist area for this CRTC configuration. */
68 struct drm_mm_node mm;
69};
70
71static inline struct vc4_crtc *
72to_vc4_crtc(struct drm_crtc *crtc)
73{
74 return (struct vc4_crtc *)crtc;
75}
76
77static inline struct vc4_crtc_state *
78to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
79{
80 return (struct vc4_crtc_state *)crtc_state;
81}
82
83struct vc4_crtc_data {
84 /* Which channel of the HVS this pixelvalve sources from. */
85 int hvs_channel;
86
87 enum vc4_encoder_type encoder_types[4];
88};
89
90#define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
91#define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
92
93#define CRTC_REG(reg) { reg, #reg }
94static const struct {
95 u32 reg;
96 const char *name;
97} crtc_regs[] = {
98 CRTC_REG(PV_CONTROL),
99 CRTC_REG(PV_V_CONTROL),
100 CRTC_REG(PV_VSYNCD_EVEN),
101 CRTC_REG(PV_HORZA),
102 CRTC_REG(PV_HORZB),
103 CRTC_REG(PV_VERTA),
104 CRTC_REG(PV_VERTB),
105 CRTC_REG(PV_VERTA_EVEN),
106 CRTC_REG(PV_VERTB_EVEN),
107 CRTC_REG(PV_INTEN),
108 CRTC_REG(PV_INTSTAT),
109 CRTC_REG(PV_STAT),
110 CRTC_REG(PV_HACT_ACT),
111};
112
113static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
114{
115 int i;
116
117 for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
118 DRM_INFO("0x%04x (%s): 0x%08x\n",
119 crtc_regs[i].reg, crtc_regs[i].name,
120 CRTC_READ(crtc_regs[i].reg));
121 }
122}
123
124#ifdef CONFIG_DEBUG_FS
125int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
126{
127 struct drm_info_node *node = (struct drm_info_node *)m->private;
128 struct drm_device *dev = node->minor->dev;
129 int crtc_index = (uintptr_t)node->info_ent->data;
130 struct drm_crtc *crtc;
131 struct vc4_crtc *vc4_crtc;
132 int i;
133
134 i = 0;
135 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
136 if (i == crtc_index)
137 break;
138 i++;
139 }
140 if (!crtc)
141 return 0;
142 vc4_crtc = to_vc4_crtc(crtc);
143
144 for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
145 seq_printf(m, "%s (0x%04x): 0x%08x\n",
146 crtc_regs[i].name, crtc_regs[i].reg,
147 CRTC_READ(crtc_regs[i].reg));
148 }
149
150 return 0;
151}
152#endif
153
154bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
155 bool in_vblank_irq, int *vpos, int *hpos,
156 ktime_t *stime, ktime_t *etime,
157 const struct drm_display_mode *mode)
158{
159 struct vc4_dev *vc4 = to_vc4_dev(dev);
160 struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
161 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
162 u32 val;
163 int fifo_lines;
164 int vblank_lines;
165 bool ret = false;
166
167 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
168
169 /* Get optional system timestamp before query. */
170 if (stime)
171 *stime = ktime_get();
172
173 /*
174 * Read vertical scanline which is currently composed for our
175 * pixelvalve by the HVS, and also the scaler status.
176 */
177 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
178
179 /* Get optional system timestamp after query. */
180 if (etime)
181 *etime = ktime_get();
182
183 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
184
185 /* Vertical position of hvs composed scanline. */
186 *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
187 *hpos = 0;
188
189 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
190 *vpos /= 2;
191
192 /* Use hpos to correct for field offset in interlaced mode. */
193 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
194 *hpos += mode->crtc_htotal / 2;
195 }
196
197 /* This is the offset we need for translating hvs -> pv scanout pos. */
198 fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
199
200 if (fifo_lines > 0)
201 ret = true;
202
203 /* HVS more than fifo_lines into frame for compositing? */
204 if (*vpos > fifo_lines) {
205 /*
206 * We are in active scanout and can get some meaningful results
207 * from HVS. The actual PV scanout can not trail behind more
208 * than fifo_lines as that is the fifo's capacity. Assume that
209 * in active scanout the HVS and PV work in lockstep wrt. HVS
210 * refilling the fifo and PV consuming from the fifo, ie.
211 * whenever the PV consumes and frees up a scanline in the
212 * fifo, the HVS will immediately refill it, therefore
213 * incrementing vpos. Therefore we choose HVS read position -
214 * fifo size in scanlines as a estimate of the real scanout
215 * position of the PV.
216 */
217 *vpos -= fifo_lines + 1;
218
219 return ret;
220 }
221
222 /*
223 * Less: This happens when we are in vblank and the HVS, after getting
224 * the VSTART restart signal from the PV, just started refilling its
225 * fifo with new lines from the top-most lines of the new framebuffers.
226 * The PV does not scan out in vblank, so does not remove lines from
227 * the fifo, so the fifo will be full quickly and the HVS has to pause.
228 * We can't get meaningful readings wrt. scanline position of the PV
229 * and need to make things up in a approximative but consistent way.
230 */
231 vblank_lines = mode->vtotal - mode->vdisplay;
232
233 if (in_vblank_irq) {
234 /*
235 * Assume the irq handler got called close to first
236 * line of vblank, so PV has about a full vblank
237 * scanlines to go, and as a base timestamp use the
238 * one taken at entry into vblank irq handler, so it
239 * is not affected by random delays due to lock
240 * contention on event_lock or vblank_time lock in
241 * the core.
242 */
243 *vpos = -vblank_lines;
244
245 if (stime)
246 *stime = vc4_crtc->t_vblank;
247 if (etime)
248 *etime = vc4_crtc->t_vblank;
249
250 /*
251 * If the HVS fifo is not yet full then we know for certain
252 * we are at the very beginning of vblank, as the hvs just
253 * started refilling, and the stime and etime timestamps
254 * truly correspond to start of vblank.
255 *
256 * Unfortunately there's no way to report this to upper levels
257 * and make it more useful.
258 */
259 } else {
260 /*
261 * No clue where we are inside vblank. Return a vpos of zero,
262 * which will cause calling code to just return the etime
263 * timestamp uncorrected. At least this is no worse than the
264 * standard fallback.
265 */
266 *vpos = 0;
267 }
268
269 return ret;
270}
271
272static void vc4_crtc_destroy(struct drm_crtc *crtc)
273{
274 drm_crtc_cleanup(crtc);
275}
276
277static void
278vc4_crtc_lut_load(struct drm_crtc *crtc)
279{
280 struct drm_device *dev = crtc->dev;
281 struct vc4_dev *vc4 = to_vc4_dev(dev);
282 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
283 u32 i;
284
285 /* The LUT memory is laid out with each HVS channel in order,
286 * each of which takes 256 writes for R, 256 for G, then 256
287 * for B.
288 */
289 HVS_WRITE(SCALER_GAMADDR,
290 SCALER_GAMADDR_AUTOINC |
291 (vc4_crtc->channel * 3 * crtc->gamma_size));
292
293 for (i = 0; i < crtc->gamma_size; i++)
294 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
295 for (i = 0; i < crtc->gamma_size; i++)
296 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
297 for (i = 0; i < crtc->gamma_size; i++)
298 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
299}
300
301static int
302vc4_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
303 uint32_t size,
304 struct drm_modeset_acquire_ctx *ctx)
305{
306 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
307 u32 i;
308
309 for (i = 0; i < size; i++) {
310 vc4_crtc->lut_r[i] = r[i] >> 8;
311 vc4_crtc->lut_g[i] = g[i] >> 8;
312 vc4_crtc->lut_b[i] = b[i] >> 8;
313 }
314
315 vc4_crtc_lut_load(crtc);
316
317 return 0;
318}
319
320static u32 vc4_get_fifo_full_level(u32 format)
321{
322 static const u32 fifo_len_bytes = 64;
323 static const u32 hvs_latency_pix = 6;
324
325 switch (format) {
326 case PV_CONTROL_FORMAT_DSIV_16:
327 case PV_CONTROL_FORMAT_DSIC_16:
328 return fifo_len_bytes - 2 * hvs_latency_pix;
329 case PV_CONTROL_FORMAT_DSIV_18:
330 return fifo_len_bytes - 14;
331 case PV_CONTROL_FORMAT_24:
332 case PV_CONTROL_FORMAT_DSIV_24:
333 default:
334 return fifo_len_bytes - 3 * hvs_latency_pix;
335 }
336}
337
338/*
339 * Returns the encoder attached to the CRTC.
340 *
341 * VC4 can only scan out to one encoder at a time, while the DRM core
342 * allows drivers to push pixels to more than one encoder from the
343 * same CRTC.
344 */
345static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
346{
347 struct drm_connector *connector;
348 struct drm_connector_list_iter conn_iter;
349
350 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
351 drm_for_each_connector_iter(connector, &conn_iter) {
352 if (connector->state->crtc == crtc) {
353 drm_connector_list_iter_end(&conn_iter);
354 return connector->encoder;
355 }
356 }
357 drm_connector_list_iter_end(&conn_iter);
358
359 return NULL;
360}
361
362static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
363{
364 struct drm_device *dev = crtc->dev;
365 struct vc4_dev *vc4 = to_vc4_dev(dev);
366 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
367 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
368 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
369 struct drm_crtc_state *state = crtc->state;
370 struct drm_display_mode *mode = &state->adjusted_mode;
371 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
372 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
373 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
374 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
375 u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
376 bool debug_dump_regs = false;
377
378 if (debug_dump_regs) {
379 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
380 vc4_crtc_dump_regs(vc4_crtc);
381 }
382
383 /* Reset the PV fifo. */
384 CRTC_WRITE(PV_CONTROL, 0);
385 CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
386 CRTC_WRITE(PV_CONTROL, 0);
387
388 CRTC_WRITE(PV_HORZA,
389 VC4_SET_FIELD((mode->htotal -
390 mode->hsync_end) * pixel_rep,
391 PV_HORZA_HBP) |
392 VC4_SET_FIELD((mode->hsync_end -
393 mode->hsync_start) * pixel_rep,
394 PV_HORZA_HSYNC));
395 CRTC_WRITE(PV_HORZB,
396 VC4_SET_FIELD((mode->hsync_start -
397 mode->hdisplay) * pixel_rep,
398 PV_HORZB_HFP) |
399 VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
400
401 CRTC_WRITE(PV_VERTA,
402 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
403 PV_VERTA_VBP) |
404 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
405 PV_VERTA_VSYNC));
406 CRTC_WRITE(PV_VERTB,
407 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
408 PV_VERTB_VFP) |
409 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
410
411 if (interlace) {
412 CRTC_WRITE(PV_VERTA_EVEN,
413 VC4_SET_FIELD(mode->crtc_vtotal -
414 mode->crtc_vsync_end - 1,
415 PV_VERTA_VBP) |
416 VC4_SET_FIELD(mode->crtc_vsync_end -
417 mode->crtc_vsync_start,
418 PV_VERTA_VSYNC));
419 CRTC_WRITE(PV_VERTB_EVEN,
420 VC4_SET_FIELD(mode->crtc_vsync_start -
421 mode->crtc_vdisplay,
422 PV_VERTB_VFP) |
423 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
424
425 /* We set up first field even mode for HDMI. VEC's
426 * NTSC mode would want first field odd instead, once
427 * we support it (to do so, set ODD_FIRST and put the
428 * delay in VSYNCD_EVEN instead).
429 */
430 CRTC_WRITE(PV_V_CONTROL,
431 PV_VCONTROL_CONTINUOUS |
432 (is_dsi ? PV_VCONTROL_DSI : 0) |
433 PV_VCONTROL_INTERLACE |
434 VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
435 PV_VCONTROL_ODD_DELAY));
436 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
437 } else {
438 CRTC_WRITE(PV_V_CONTROL,
439 PV_VCONTROL_CONTINUOUS |
440 (is_dsi ? PV_VCONTROL_DSI : 0));
441 }
442
443 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
444
445 CRTC_WRITE(PV_CONTROL,
446 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
447 VC4_SET_FIELD(vc4_get_fifo_full_level(format),
448 PV_CONTROL_FIFO_LEVEL) |
449 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
450 PV_CONTROL_CLR_AT_START |
451 PV_CONTROL_TRIGGER_UNDERFLOW |
452 PV_CONTROL_WAIT_HSTART |
453 VC4_SET_FIELD(vc4_encoder->clock_select,
454 PV_CONTROL_CLK_SELECT) |
455 PV_CONTROL_FIFO_CLR |
456 PV_CONTROL_EN);
457
458 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
459 SCALER_DISPBKGND_AUTOHS |
460 SCALER_DISPBKGND_GAMMA |
461 (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
462
463 /* Reload the LUT, since the SRAMs would have been disabled if
464 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
465 */
466 vc4_crtc_lut_load(crtc);
467
468 if (debug_dump_regs) {
469 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
470 vc4_crtc_dump_regs(vc4_crtc);
471 }
472}
473
474static void require_hvs_enabled(struct drm_device *dev)
475{
476 struct vc4_dev *vc4 = to_vc4_dev(dev);
477
478 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
479 SCALER_DISPCTRL_ENABLE);
480}
481
482static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
483 struct drm_crtc_state *old_state)
484{
485 struct drm_device *dev = crtc->dev;
486 struct vc4_dev *vc4 = to_vc4_dev(dev);
487 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
488 u32 chan = vc4_crtc->channel;
489 int ret;
490 require_hvs_enabled(dev);
491
492 /* Disable vblank irq handling before crtc is disabled. */
493 drm_crtc_vblank_off(crtc);
494
495 CRTC_WRITE(PV_V_CONTROL,
496 CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
497 ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
498 WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
499
500 if (HVS_READ(SCALER_DISPCTRLX(chan)) &
501 SCALER_DISPCTRLX_ENABLE) {
502 HVS_WRITE(SCALER_DISPCTRLX(chan),
503 SCALER_DISPCTRLX_RESET);
504
505 /* While the docs say that reset is self-clearing, it
506 * seems it doesn't actually.
507 */
508 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
509 }
510
511 /* Once we leave, the scaler should be disabled and its fifo empty. */
512
513 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
514
515 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
516 SCALER_DISPSTATX_MODE) !=
517 SCALER_DISPSTATX_MODE_DISABLED);
518
519 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
520 (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
521 SCALER_DISPSTATX_EMPTY);
522
523 /*
524 * Make sure we issue a vblank event after disabling the CRTC if
525 * someone was waiting it.
526 */
527 if (crtc->state->event) {
528 unsigned long flags;
529
530 spin_lock_irqsave(&dev->event_lock, flags);
531 drm_crtc_send_vblank_event(crtc, crtc->state->event);
532 crtc->state->event = NULL;
533 spin_unlock_irqrestore(&dev->event_lock, flags);
534 }
535}
536
537static void vc4_crtc_update_dlist(struct drm_crtc *crtc)
538{
539 struct drm_device *dev = crtc->dev;
540 struct vc4_dev *vc4 = to_vc4_dev(dev);
541 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
542 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
543
544 if (crtc->state->event) {
545 unsigned long flags;
546
547 crtc->state->event->pipe = drm_crtc_index(crtc);
548
549 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
550
551 spin_lock_irqsave(&dev->event_lock, flags);
552 vc4_crtc->event = crtc->state->event;
553 crtc->state->event = NULL;
554
555 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
556 vc4_state->mm.start);
557
558 spin_unlock_irqrestore(&dev->event_lock, flags);
559 } else {
560 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
561 vc4_state->mm.start);
562 }
563}
564
565static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
566 struct drm_crtc_state *old_state)
567{
568 struct drm_device *dev = crtc->dev;
569 struct vc4_dev *vc4 = to_vc4_dev(dev);
570 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
571 struct drm_crtc_state *state = crtc->state;
572 struct drm_display_mode *mode = &state->adjusted_mode;
573
574 require_hvs_enabled(dev);
575
576 /* Enable vblank irq handling before crtc is started otherwise
577 * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
578 */
579 drm_crtc_vblank_on(crtc);
580 vc4_crtc_update_dlist(crtc);
581
582 /* Turn on the scaler, which will wait for vstart to start
583 * compositing.
584 */
585 HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
586 VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
587 VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
588 SCALER_DISPCTRLX_ENABLE);
589
590 /* Turn on the pixel valve, which will emit the vstart signal. */
591 CRTC_WRITE(PV_V_CONTROL,
592 CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
593}
594
595static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
596 const struct drm_display_mode *mode)
597{
598 /* Do not allow doublescan modes from user space */
599 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
600 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
601 crtc->base.id);
602 return MODE_NO_DBLESCAN;
603 }
604
605 return MODE_OK;
606}
607
608static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
609 struct drm_crtc_state *state)
610{
611 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
612 struct drm_device *dev = crtc->dev;
613 struct vc4_dev *vc4 = to_vc4_dev(dev);
614 struct drm_plane *plane;
615 unsigned long flags;
616 const struct drm_plane_state *plane_state;
617 u32 dlist_count = 0;
618 int ret;
619
620 /* The pixelvalve can only feed one encoder (and encoders are
621 * 1:1 with connectors.)
622 */
623 if (hweight32(state->connector_mask) > 1)
624 return -EINVAL;
625
626 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
627 dlist_count += vc4_plane_dlist_size(plane_state);
628
629 dlist_count++; /* Account for SCALER_CTL0_END. */
630
631 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
632 ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
633 dlist_count);
634 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
635 if (ret)
636 return ret;
637
638 return 0;
639}
640
641static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
642 struct drm_crtc_state *old_state)
643{
644 struct drm_device *dev = crtc->dev;
645 struct vc4_dev *vc4 = to_vc4_dev(dev);
646 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
647 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
648 struct drm_plane *plane;
649 struct vc4_plane_state *vc4_plane_state;
650 bool debug_dump_regs = false;
651 bool enable_bg_fill = false;
652 u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
653 u32 __iomem *dlist_next = dlist_start;
654
655 if (debug_dump_regs) {
656 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
657 vc4_hvs_dump_state(dev);
658 }
659
660 /* Copy all the active planes' dlist contents to the hardware dlist. */
661 drm_atomic_crtc_for_each_plane(plane, crtc) {
662 /* Is this the first active plane? */
663 if (dlist_next == dlist_start) {
664 /* We need to enable background fill when a plane
665 * could be alpha blending from the background, i.e.
666 * where no other plane is underneath. It suffices to
667 * consider the first active plane here since we set
668 * needs_bg_fill such that either the first plane
669 * already needs it or all planes on top blend from
670 * the first or a lower plane.
671 */
672 vc4_plane_state = to_vc4_plane_state(plane->state);
673 enable_bg_fill = vc4_plane_state->needs_bg_fill;
674 }
675
676 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
677 }
678
679 writel(SCALER_CTL0_END, dlist_next);
680 dlist_next++;
681
682 WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
683
684 if (enable_bg_fill)
685 /* This sets a black background color fill, as is the case
686 * with other DRM drivers.
687 */
688 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
689 HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) |
690 SCALER_DISPBKGND_FILL);
691
692 /* Only update DISPLIST if the CRTC was already running and is not
693 * being disabled.
694 * vc4_crtc_enable() takes care of updating the dlist just after
695 * re-enabling VBLANK interrupts and before enabling the engine.
696 * If the CRTC is being disabled, there's no point in updating this
697 * information.
698 */
699 if (crtc->state->active && old_state->active)
700 vc4_crtc_update_dlist(crtc);
701
702 if (debug_dump_regs) {
703 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
704 vc4_hvs_dump_state(dev);
705 }
706}
707
708static int vc4_enable_vblank(struct drm_crtc *crtc)
709{
710 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
711
712 CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
713
714 return 0;
715}
716
717static void vc4_disable_vblank(struct drm_crtc *crtc)
718{
719 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
720
721 CRTC_WRITE(PV_INTEN, 0);
722}
723
724static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
725{
726 struct drm_crtc *crtc = &vc4_crtc->base;
727 struct drm_device *dev = crtc->dev;
728 struct vc4_dev *vc4 = to_vc4_dev(dev);
729 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
730 u32 chan = vc4_crtc->channel;
731 unsigned long flags;
732
733 spin_lock_irqsave(&dev->event_lock, flags);
734 if (vc4_crtc->event &&
735 (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) {
736 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
737 vc4_crtc->event = NULL;
738 drm_crtc_vblank_put(crtc);
739 }
740 spin_unlock_irqrestore(&dev->event_lock, flags);
741}
742
743static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
744{
745 struct vc4_crtc *vc4_crtc = data;
746 u32 stat = CRTC_READ(PV_INTSTAT);
747 irqreturn_t ret = IRQ_NONE;
748
749 if (stat & PV_INT_VFP_START) {
750 vc4_crtc->t_vblank = ktime_get();
751 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
752 drm_crtc_handle_vblank(&vc4_crtc->base);
753 vc4_crtc_handle_page_flip(vc4_crtc);
754 ret = IRQ_HANDLED;
755 }
756
757 return ret;
758}
759
760struct vc4_async_flip_state {
761 struct drm_crtc *crtc;
762 struct drm_framebuffer *fb;
763 struct drm_framebuffer *old_fb;
764 struct drm_pending_vblank_event *event;
765
766 struct vc4_seqno_cb cb;
767};
768
769/* Called when the V3D execution for the BO being flipped to is done, so that
770 * we can actually update the plane's address to point to it.
771 */
772static void
773vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
774{
775 struct vc4_async_flip_state *flip_state =
776 container_of(cb, struct vc4_async_flip_state, cb);
777 struct drm_crtc *crtc = flip_state->crtc;
778 struct drm_device *dev = crtc->dev;
779 struct vc4_dev *vc4 = to_vc4_dev(dev);
780 struct drm_plane *plane = crtc->primary;
781
782 vc4_plane_async_set_fb(plane, flip_state->fb);
783 if (flip_state->event) {
784 unsigned long flags;
785
786 spin_lock_irqsave(&dev->event_lock, flags);
787 drm_crtc_send_vblank_event(crtc, flip_state->event);
788 spin_unlock_irqrestore(&dev->event_lock, flags);
789 }
790
791 drm_crtc_vblank_put(crtc);
792 drm_framebuffer_put(flip_state->fb);
793
794 /* Decrement the BO usecnt in order to keep the inc/dec calls balanced
795 * when the planes are updated through the async update path.
796 * FIXME: we should move to generic async-page-flip when it's
797 * available, so that we can get rid of this hand-made cleanup_fb()
798 * logic.
799 */
800 if (flip_state->old_fb) {
801 struct drm_gem_cma_object *cma_bo;
802 struct vc4_bo *bo;
803
804 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
805 bo = to_vc4_bo(&cma_bo->base);
806 vc4_bo_dec_usecnt(bo);
807 drm_framebuffer_put(flip_state->old_fb);
808 }
809
810 kfree(flip_state);
811
812 up(&vc4->async_modeset);
813}
814
815/* Implements async (non-vblank-synced) page flips.
816 *
817 * The page flip ioctl needs to return immediately, so we grab the
818 * modeset semaphore on the pipe, and queue the address update for
819 * when V3D is done with the BO being flipped to.
820 */
821static int vc4_async_page_flip(struct drm_crtc *crtc,
822 struct drm_framebuffer *fb,
823 struct drm_pending_vblank_event *event,
824 uint32_t flags)
825{
826 struct drm_device *dev = crtc->dev;
827 struct vc4_dev *vc4 = to_vc4_dev(dev);
828 struct drm_plane *plane = crtc->primary;
829 int ret = 0;
830 struct vc4_async_flip_state *flip_state;
831 struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
832 struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
833
834 /* Increment the BO usecnt here, so that we never end up with an
835 * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
836 * plane is later updated through the non-async path.
837 * FIXME: we should move to generic async-page-flip when it's
838 * available, so that we can get rid of this hand-made prepare_fb()
839 * logic.
840 */
841 ret = vc4_bo_inc_usecnt(bo);
842 if (ret)
843 return ret;
844
845 flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
846 if (!flip_state) {
847 vc4_bo_dec_usecnt(bo);
848 return -ENOMEM;
849 }
850
851 drm_framebuffer_get(fb);
852 flip_state->fb = fb;
853 flip_state->crtc = crtc;
854 flip_state->event = event;
855
856 /* Make sure all other async modesetes have landed. */
857 ret = down_interruptible(&vc4->async_modeset);
858 if (ret) {
859 drm_framebuffer_put(fb);
860 vc4_bo_dec_usecnt(bo);
861 kfree(flip_state);
862 return ret;
863 }
864
865 /* Save the current FB before it's replaced by the new one in
866 * drm_atomic_set_fb_for_plane(). We'll need the old FB in
867 * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
868 * it consistent.
869 * FIXME: we should move to generic async-page-flip when it's
870 * available, so that we can get rid of this hand-made cleanup_fb()
871 * logic.
872 */
873 flip_state->old_fb = plane->state->fb;
874 if (flip_state->old_fb)
875 drm_framebuffer_get(flip_state->old_fb);
876
877 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
878
879 /* Immediately update the plane's legacy fb pointer, so that later
880 * modeset prep sees the state that will be present when the semaphore
881 * is released.
882 */
883 drm_atomic_set_fb_for_plane(plane->state, fb);
884 plane->fb = fb;
885
886 vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
887 vc4_async_page_flip_complete);
888
889 /* Driver takes ownership of state on successful async commit. */
890 return 0;
891}
892
893static int vc4_page_flip(struct drm_crtc *crtc,
894 struct drm_framebuffer *fb,
895 struct drm_pending_vblank_event *event,
896 uint32_t flags,
897 struct drm_modeset_acquire_ctx *ctx)
898{
899 if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
900 return vc4_async_page_flip(crtc, fb, event, flags);
901 else
902 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
903}
904
905static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
906{
907 struct vc4_crtc_state *vc4_state;
908
909 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
910 if (!vc4_state)
911 return NULL;
912
913 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
914 return &vc4_state->base;
915}
916
917static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
918 struct drm_crtc_state *state)
919{
920 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
921 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
922
923 if (vc4_state->mm.allocated) {
924 unsigned long flags;
925
926 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
927 drm_mm_remove_node(&vc4_state->mm);
928 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
929
930 }
931
932 drm_atomic_helper_crtc_destroy_state(crtc, state);
933}
934
935static void
936vc4_crtc_reset(struct drm_crtc *crtc)
937{
938 if (crtc->state)
939 __drm_atomic_helper_crtc_destroy_state(crtc->state);
940
941 crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL);
942 if (crtc->state)
943 crtc->state->crtc = crtc;
944}
945
946static const struct drm_crtc_funcs vc4_crtc_funcs = {
947 .set_config = drm_atomic_helper_set_config,
948 .destroy = vc4_crtc_destroy,
949 .page_flip = vc4_page_flip,
950 .set_property = NULL,
951 .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
952 .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
953 .reset = vc4_crtc_reset,
954 .atomic_duplicate_state = vc4_crtc_duplicate_state,
955 .atomic_destroy_state = vc4_crtc_destroy_state,
956 .gamma_set = vc4_crtc_gamma_set,
957 .enable_vblank = vc4_enable_vblank,
958 .disable_vblank = vc4_disable_vblank,
959};
960
961static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
962 .mode_set_nofb = vc4_crtc_mode_set_nofb,
963 .mode_valid = vc4_crtc_mode_valid,
964 .atomic_check = vc4_crtc_atomic_check,
965 .atomic_flush = vc4_crtc_atomic_flush,
966 .atomic_enable = vc4_crtc_atomic_enable,
967 .atomic_disable = vc4_crtc_atomic_disable,
968};
969
970static const struct vc4_crtc_data pv0_data = {
971 .hvs_channel = 0,
972 .encoder_types = {
973 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
974 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
975 },
976};
977
978static const struct vc4_crtc_data pv1_data = {
979 .hvs_channel = 2,
980 .encoder_types = {
981 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
982 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
983 },
984};
985
986static const struct vc4_crtc_data pv2_data = {
987 .hvs_channel = 1,
988 .encoder_types = {
989 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
990 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
991 },
992};
993
994static const struct of_device_id vc4_crtc_dt_match[] = {
995 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
996 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
997 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
998 {}
999};
1000
1001static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1002 struct drm_crtc *crtc)
1003{
1004 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1005 const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
1006 const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
1007 struct drm_encoder *encoder;
1008
1009 drm_for_each_encoder(encoder, drm) {
1010 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
1011 int i;
1012
1013 for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
1014 if (vc4_encoder->type == encoder_types[i]) {
1015 vc4_encoder->clock_select = i;
1016 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1017 break;
1018 }
1019 }
1020 }
1021}
1022
1023static void
1024vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
1025{
1026 struct drm_device *drm = vc4_crtc->base.dev;
1027 struct vc4_dev *vc4 = to_vc4_dev(drm);
1028 u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
1029 /* Top/base are supposed to be 4-pixel aligned, but the
1030 * Raspberry Pi firmware fills the low bits (which are
1031 * presumably ignored).
1032 */
1033 u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
1034 u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
1035
1036 vc4_crtc->cob_size = top - base + 4;
1037}
1038
1039static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1040{
1041 struct platform_device *pdev = to_platform_device(dev);
1042 struct drm_device *drm = dev_get_drvdata(master);
1043 struct vc4_crtc *vc4_crtc;
1044 struct drm_crtc *crtc;
1045 struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
1046 const struct of_device_id *match;
1047 int ret, i;
1048
1049 vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
1050 if (!vc4_crtc)
1051 return -ENOMEM;
1052 crtc = &vc4_crtc->base;
1053
1054 match = of_match_device(vc4_crtc_dt_match, dev);
1055 if (!match)
1056 return -ENODEV;
1057 vc4_crtc->data = match->data;
1058
1059 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1060 if (IS_ERR(vc4_crtc->regs))
1061 return PTR_ERR(vc4_crtc->regs);
1062
1063 /* For now, we create just the primary and the legacy cursor
1064 * planes. We should be able to stack more planes on easily,
1065 * but to do that we would need to compute the bandwidth
1066 * requirement of the plane configuration, and reject ones
1067 * that will take too much.
1068 */
1069 primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
1070 if (IS_ERR(primary_plane)) {
1071 dev_err(dev, "failed to construct primary plane\n");
1072 ret = PTR_ERR(primary_plane);
1073 goto err;
1074 }
1075
1076 drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1077 &vc4_crtc_funcs, NULL);
1078 drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
1079 primary_plane->crtc = crtc;
1080 vc4_crtc->channel = vc4_crtc->data->hvs_channel;
1081 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1082
1083 /* Set up some arbitrary number of planes. We're not limited
1084 * by a set number of physical registers, just the space in
1085 * the HVS (16k) and how small an plane can be (28 bytes).
1086 * However, each plane we set up takes up some memory, and
1087 * increases the cost of looping over planes, which atomic
1088 * modesetting does quite a bit. As a result, we pick a
1089 * modest number of planes to expose, that should hopefully
1090 * still cover any sane usecase.
1091 */
1092 for (i = 0; i < 8; i++) {
1093 struct drm_plane *plane =
1094 vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
1095
1096 if (IS_ERR(plane))
1097 continue;
1098
1099 plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1100 }
1101
1102 /* Set up the legacy cursor after overlay initialization,
1103 * since we overlay planes on the CRTC in the order they were
1104 * initialized.
1105 */
1106 cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1107 if (!IS_ERR(cursor_plane)) {
1108 cursor_plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1109 cursor_plane->crtc = crtc;
1110 crtc->cursor = cursor_plane;
1111 }
1112
1113 vc4_crtc_get_cob_allocation(vc4_crtc);
1114
1115 CRTC_WRITE(PV_INTEN, 0);
1116 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1117 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1118 vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
1119 if (ret)
1120 goto err_destroy_planes;
1121
1122 vc4_set_crtc_possible_masks(drm, crtc);
1123
1124 for (i = 0; i < crtc->gamma_size; i++) {
1125 vc4_crtc->lut_r[i] = i;
1126 vc4_crtc->lut_g[i] = i;
1127 vc4_crtc->lut_b[i] = i;
1128 }
1129
1130 platform_set_drvdata(pdev, vc4_crtc);
1131
1132 return 0;
1133
1134err_destroy_planes:
1135 list_for_each_entry_safe(destroy_plane, temp,
1136 &drm->mode_config.plane_list, head) {
1137 if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc))
1138 destroy_plane->funcs->destroy(destroy_plane);
1139 }
1140err:
1141 return ret;
1142}
1143
1144static void vc4_crtc_unbind(struct device *dev, struct device *master,
1145 void *data)
1146{
1147 struct platform_device *pdev = to_platform_device(dev);
1148 struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1149
1150 vc4_crtc_destroy(&vc4_crtc->base);
1151
1152 CRTC_WRITE(PV_INTEN, 0);
1153
1154 platform_set_drvdata(pdev, NULL);
1155}
1156
1157static const struct component_ops vc4_crtc_ops = {
1158 .bind = vc4_crtc_bind,
1159 .unbind = vc4_crtc_unbind,
1160};
1161
1162static int vc4_crtc_dev_probe(struct platform_device *pdev)
1163{
1164 return component_add(&pdev->dev, &vc4_crtc_ops);
1165}
1166
1167static int vc4_crtc_dev_remove(struct platform_device *pdev)
1168{
1169 component_del(&pdev->dev, &vc4_crtc_ops);
1170 return 0;
1171}
1172
1173struct platform_driver vc4_crtc_driver = {
1174 .probe = vc4_crtc_dev_probe,
1175 .remove = vc4_crtc_dev_remove,
1176 .driver = {
1177 .name = "vc4_crtc",
1178 .of_match_table = vc4_crtc_dt_match,
1179 },
1180};