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1/*
2 * Copyright (C) 2013-2015 ARM Limited
3 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive
7 * for more details.
8 *
9 * ARM HDLCD Driver
10 */
11
12#include <linux/module.h>
13#include <linux/spinlock.h>
14#include <linux/clk.h>
15#include <linux/component.h>
16#include <linux/console.h>
17#include <linux/dma-mapping.h>
18#include <linux/list.h>
19#include <linux/of_graph.h>
20#include <linux/of_reserved_mem.h>
21#include <linux/platform_device.h>
22#include <linux/pm_runtime.h>
23
24#include <drm/drm_atomic_helper.h>
25#include <drm/drm_crtc.h>
26#include <drm/drm_debugfs.h>
27#include <drm/drm_drv.h>
28#include <drm/drm_fb_cma_helper.h>
29#include <drm/drm_fb_helper.h>
30#include <drm/drm_gem_cma_helper.h>
31#include <drm/drm_gem_framebuffer_helper.h>
32#include <drm/drm_irq.h>
33#include <drm/drm_modeset_helper.h>
34#include <drm/drm_of.h>
35#include <drm/drm_probe_helper.h>
36#include <drm/drm_vblank.h>
37
38#include "hdlcd_drv.h"
39#include "hdlcd_regs.h"
40
41static int hdlcd_load(struct drm_device *drm, unsigned long flags)
42{
43 struct hdlcd_drm_private *hdlcd = drm->dev_private;
44 struct platform_device *pdev = to_platform_device(drm->dev);
45 struct resource *res;
46 u32 version;
47 int ret;
48
49 hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
50 if (IS_ERR(hdlcd->clk))
51 return PTR_ERR(hdlcd->clk);
52
53#ifdef CONFIG_DEBUG_FS
54 atomic_set(&hdlcd->buffer_underrun_count, 0);
55 atomic_set(&hdlcd->bus_error_count, 0);
56 atomic_set(&hdlcd->vsync_count, 0);
57 atomic_set(&hdlcd->dma_end_count, 0);
58#endif
59
60 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
61 hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
62 if (IS_ERR(hdlcd->mmio)) {
63 DRM_ERROR("failed to map control registers area\n");
64 ret = PTR_ERR(hdlcd->mmio);
65 hdlcd->mmio = NULL;
66 return ret;
67 }
68
69 version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
70 if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
71 DRM_ERROR("unknown product id: 0x%x\n", version);
72 return -EINVAL;
73 }
74 DRM_INFO("found ARM HDLCD version r%dp%d\n",
75 (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
76 version & HDLCD_VERSION_MINOR_MASK);
77
78 /* Get the optional framebuffer memory resource */
79 ret = of_reserved_mem_device_init(drm->dev);
80 if (ret && ret != -ENODEV)
81 return ret;
82
83 ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
84 if (ret)
85 goto setup_fail;
86
87 ret = hdlcd_setup_crtc(drm);
88 if (ret < 0) {
89 DRM_ERROR("failed to create crtc\n");
90 goto setup_fail;
91 }
92
93 ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
94 if (ret < 0) {
95 DRM_ERROR("failed to install IRQ handler\n");
96 goto irq_fail;
97 }
98
99 return 0;
100
101irq_fail:
102 drm_crtc_cleanup(&hdlcd->crtc);
103setup_fail:
104 of_reserved_mem_device_release(drm->dev);
105
106 return ret;
107}
108
109static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
110 .fb_create = drm_gem_fb_create,
111 .atomic_check = drm_atomic_helper_check,
112 .atomic_commit = drm_atomic_helper_commit,
113};
114
115static void hdlcd_setup_mode_config(struct drm_device *drm)
116{
117 drm_mode_config_init(drm);
118 drm->mode_config.min_width = 0;
119 drm->mode_config.min_height = 0;
120 drm->mode_config.max_width = HDLCD_MAX_XRES;
121 drm->mode_config.max_height = HDLCD_MAX_YRES;
122 drm->mode_config.funcs = &hdlcd_mode_config_funcs;
123}
124
125static irqreturn_t hdlcd_irq(int irq, void *arg)
126{
127 struct drm_device *drm = arg;
128 struct hdlcd_drm_private *hdlcd = drm->dev_private;
129 unsigned long irq_status;
130
131 irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
132
133#ifdef CONFIG_DEBUG_FS
134 if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
135 atomic_inc(&hdlcd->buffer_underrun_count);
136
137 if (irq_status & HDLCD_INTERRUPT_DMA_END)
138 atomic_inc(&hdlcd->dma_end_count);
139
140 if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
141 atomic_inc(&hdlcd->bus_error_count);
142
143 if (irq_status & HDLCD_INTERRUPT_VSYNC)
144 atomic_inc(&hdlcd->vsync_count);
145
146#endif
147 if (irq_status & HDLCD_INTERRUPT_VSYNC)
148 drm_crtc_handle_vblank(&hdlcd->crtc);
149
150 /* acknowledge interrupt(s) */
151 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
152
153 return IRQ_HANDLED;
154}
155
156static void hdlcd_irq_preinstall(struct drm_device *drm)
157{
158 struct hdlcd_drm_private *hdlcd = drm->dev_private;
159 /* Ensure interrupts are disabled */
160 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
161 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
162}
163
164static int hdlcd_irq_postinstall(struct drm_device *drm)
165{
166#ifdef CONFIG_DEBUG_FS
167 struct hdlcd_drm_private *hdlcd = drm->dev_private;
168 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
169
170 /* enable debug interrupts */
171 irq_mask |= HDLCD_DEBUG_INT_MASK;
172
173 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
174#endif
175 return 0;
176}
177
178static void hdlcd_irq_uninstall(struct drm_device *drm)
179{
180 struct hdlcd_drm_private *hdlcd = drm->dev_private;
181 /* disable all the interrupts that we might have enabled */
182 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
183
184#ifdef CONFIG_DEBUG_FS
185 /* disable debug interrupts */
186 irq_mask &= ~HDLCD_DEBUG_INT_MASK;
187#endif
188
189 /* disable vsync interrupts */
190 irq_mask &= ~HDLCD_INTERRUPT_VSYNC;
191
192 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
193}
194
195#ifdef CONFIG_DEBUG_FS
196static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
197{
198 struct drm_info_node *node = (struct drm_info_node *)m->private;
199 struct drm_device *drm = node->minor->dev;
200 struct hdlcd_drm_private *hdlcd = drm->dev_private;
201
202 seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
203 seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count));
204 seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
205 seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count));
206 return 0;
207}
208
209static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
210{
211 struct drm_info_node *node = (struct drm_info_node *)m->private;
212 struct drm_device *drm = node->minor->dev;
213 struct hdlcd_drm_private *hdlcd = drm->dev_private;
214 unsigned long clkrate = clk_get_rate(hdlcd->clk);
215 unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
216
217 seq_printf(m, "hw : %lu\n", clkrate);
218 seq_printf(m, "mode: %lu\n", mode_clock);
219 return 0;
220}
221
222static struct drm_info_list hdlcd_debugfs_list[] = {
223 { "interrupt_count", hdlcd_show_underrun_count, 0 },
224 { "clocks", hdlcd_show_pxlclock, 0 },
225};
226
227static int hdlcd_debugfs_init(struct drm_minor *minor)
228{
229 return drm_debugfs_create_files(hdlcd_debugfs_list,
230 ARRAY_SIZE(hdlcd_debugfs_list), minor->debugfs_root, minor);
231}
232#endif
233
234DEFINE_DRM_GEM_CMA_FOPS(fops);
235
236static struct drm_driver hdlcd_driver = {
237 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
238 .irq_handler = hdlcd_irq,
239 .irq_preinstall = hdlcd_irq_preinstall,
240 .irq_postinstall = hdlcd_irq_postinstall,
241 .irq_uninstall = hdlcd_irq_uninstall,
242 .gem_free_object_unlocked = drm_gem_cma_free_object,
243 .gem_print_info = drm_gem_cma_print_info,
244 .gem_vm_ops = &drm_gem_cma_vm_ops,
245 .dumb_create = drm_gem_cma_dumb_create,
246 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
247 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
248 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
249 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
250 .gem_prime_vmap = drm_gem_cma_prime_vmap,
251 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
252 .gem_prime_mmap = drm_gem_cma_prime_mmap,
253#ifdef CONFIG_DEBUG_FS
254 .debugfs_init = hdlcd_debugfs_init,
255#endif
256 .fops = &fops,
257 .name = "hdlcd",
258 .desc = "ARM HDLCD Controller DRM",
259 .date = "20151021",
260 .major = 1,
261 .minor = 0,
262};
263
264static int hdlcd_drm_bind(struct device *dev)
265{
266 struct drm_device *drm;
267 struct hdlcd_drm_private *hdlcd;
268 int ret;
269
270 hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL);
271 if (!hdlcd)
272 return -ENOMEM;
273
274 drm = drm_dev_alloc(&hdlcd_driver, dev);
275 if (IS_ERR(drm))
276 return PTR_ERR(drm);
277
278 drm->dev_private = hdlcd;
279 dev_set_drvdata(dev, drm);
280
281 hdlcd_setup_mode_config(drm);
282 ret = hdlcd_load(drm, 0);
283 if (ret)
284 goto err_free;
285
286 /* Set the CRTC's port so that the encoder component can find it */
287 hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
288
289 ret = component_bind_all(dev, drm);
290 if (ret) {
291 DRM_ERROR("Failed to bind all components\n");
292 goto err_unload;
293 }
294
295 ret = pm_runtime_set_active(dev);
296 if (ret)
297 goto err_pm_active;
298
299 pm_runtime_enable(dev);
300
301 ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
302 if (ret < 0) {
303 DRM_ERROR("failed to initialise vblank\n");
304 goto err_vblank;
305 }
306
307 drm_mode_config_reset(drm);
308 drm_kms_helper_poll_init(drm);
309
310 ret = drm_dev_register(drm, 0);
311 if (ret)
312 goto err_register;
313
314 drm_fbdev_generic_setup(drm, 32);
315
316 return 0;
317
318err_register:
319 drm_kms_helper_poll_fini(drm);
320err_vblank:
321 pm_runtime_disable(drm->dev);
322err_pm_active:
323 drm_atomic_helper_shutdown(drm);
324 component_unbind_all(dev, drm);
325err_unload:
326 of_node_put(hdlcd->crtc.port);
327 hdlcd->crtc.port = NULL;
328 drm_irq_uninstall(drm);
329 of_reserved_mem_device_release(drm->dev);
330err_free:
331 drm_mode_config_cleanup(drm);
332 dev_set_drvdata(dev, NULL);
333 drm_dev_put(drm);
334
335 return ret;
336}
337
338static void hdlcd_drm_unbind(struct device *dev)
339{
340 struct drm_device *drm = dev_get_drvdata(dev);
341 struct hdlcd_drm_private *hdlcd = drm->dev_private;
342
343 drm_dev_unregister(drm);
344 drm_kms_helper_poll_fini(drm);
345 component_unbind_all(dev, drm);
346 of_node_put(hdlcd->crtc.port);
347 hdlcd->crtc.port = NULL;
348 pm_runtime_get_sync(dev);
349 drm_crtc_vblank_off(&hdlcd->crtc);
350 drm_irq_uninstall(drm);
351 drm_atomic_helper_shutdown(drm);
352 pm_runtime_put(dev);
353 if (pm_runtime_enabled(dev))
354 pm_runtime_disable(dev);
355 of_reserved_mem_device_release(dev);
356 drm_mode_config_cleanup(drm);
357 drm->dev_private = NULL;
358 dev_set_drvdata(dev, NULL);
359 drm_dev_put(drm);
360}
361
362static const struct component_master_ops hdlcd_master_ops = {
363 .bind = hdlcd_drm_bind,
364 .unbind = hdlcd_drm_unbind,
365};
366
367static int compare_dev(struct device *dev, void *data)
368{
369 return dev->of_node == data;
370}
371
372static int hdlcd_probe(struct platform_device *pdev)
373{
374 struct device_node *port;
375 struct component_match *match = NULL;
376
377 /* there is only one output port inside each device, find it */
378 port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
379 if (!port)
380 return -ENODEV;
381
382 drm_of_component_match_add(&pdev->dev, &match, compare_dev, port);
383 of_node_put(port);
384
385 return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
386 match);
387}
388
389static int hdlcd_remove(struct platform_device *pdev)
390{
391 component_master_del(&pdev->dev, &hdlcd_master_ops);
392 return 0;
393}
394
395static const struct of_device_id hdlcd_of_match[] = {
396 { .compatible = "arm,hdlcd" },
397 {},
398};
399MODULE_DEVICE_TABLE(of, hdlcd_of_match);
400
401static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
402{
403 struct drm_device *drm = dev_get_drvdata(dev);
404
405 return drm_mode_config_helper_suspend(drm);
406}
407
408static int __maybe_unused hdlcd_pm_resume(struct device *dev)
409{
410 struct drm_device *drm = dev_get_drvdata(dev);
411
412 drm_mode_config_helper_resume(drm);
413
414 return 0;
415}
416
417static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
418
419static struct platform_driver hdlcd_platform_driver = {
420 .probe = hdlcd_probe,
421 .remove = hdlcd_remove,
422 .driver = {
423 .name = "hdlcd",
424 .pm = &hdlcd_pm_ops,
425 .of_match_table = hdlcd_of_match,
426 },
427};
428
429module_platform_driver(hdlcd_platform_driver);
430
431MODULE_AUTHOR("Liviu Dudau");
432MODULE_DESCRIPTION("ARM HDLCD DRM driver");
433MODULE_LICENSE("GPL v2");
1/*
2 * Copyright (C) 2013-2015 ARM Limited
3 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive
7 * for more details.
8 *
9 * ARM HDLCD Driver
10 */
11
12#include <linux/module.h>
13#include <linux/spinlock.h>
14#include <linux/clk.h>
15#include <linux/component.h>
16#include <linux/list.h>
17#include <linux/of_graph.h>
18#include <linux/of_reserved_mem.h>
19#include <linux/pm_runtime.h>
20
21#include <drm/drmP.h>
22#include <drm/drm_atomic_helper.h>
23#include <drm/drm_crtc.h>
24#include <drm/drm_crtc_helper.h>
25#include <drm/drm_fb_helper.h>
26#include <drm/drm_fb_cma_helper.h>
27#include <drm/drm_gem_cma_helper.h>
28#include <drm/drm_of.h>
29
30#include "hdlcd_drv.h"
31#include "hdlcd_regs.h"
32
33static int hdlcd_load(struct drm_device *drm, unsigned long flags)
34{
35 struct hdlcd_drm_private *hdlcd = drm->dev_private;
36 struct platform_device *pdev = to_platform_device(drm->dev);
37 struct resource *res;
38 u32 version;
39 int ret;
40
41 hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
42 if (IS_ERR(hdlcd->clk))
43 return PTR_ERR(hdlcd->clk);
44
45#ifdef CONFIG_DEBUG_FS
46 atomic_set(&hdlcd->buffer_underrun_count, 0);
47 atomic_set(&hdlcd->bus_error_count, 0);
48 atomic_set(&hdlcd->vsync_count, 0);
49 atomic_set(&hdlcd->dma_end_count, 0);
50#endif
51
52 INIT_LIST_HEAD(&hdlcd->event_list);
53
54 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
55 hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
56 if (IS_ERR(hdlcd->mmio)) {
57 DRM_ERROR("failed to map control registers area\n");
58 ret = PTR_ERR(hdlcd->mmio);
59 hdlcd->mmio = NULL;
60 return ret;
61 }
62
63 version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
64 if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
65 DRM_ERROR("unknown product id: 0x%x\n", version);
66 return -EINVAL;
67 }
68 DRM_INFO("found ARM HDLCD version r%dp%d\n",
69 (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
70 version & HDLCD_VERSION_MINOR_MASK);
71
72 /* Get the optional framebuffer memory resource */
73 ret = of_reserved_mem_device_init(drm->dev);
74 if (ret && ret != -ENODEV)
75 return ret;
76
77 ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
78 if (ret)
79 goto setup_fail;
80
81 ret = hdlcd_setup_crtc(drm);
82 if (ret < 0) {
83 DRM_ERROR("failed to create crtc\n");
84 goto setup_fail;
85 }
86
87 pm_runtime_enable(drm->dev);
88
89 pm_runtime_get_sync(drm->dev);
90 ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
91 pm_runtime_put_sync(drm->dev);
92 if (ret < 0) {
93 DRM_ERROR("failed to install IRQ handler\n");
94 goto irq_fail;
95 }
96
97 return 0;
98
99irq_fail:
100 drm_crtc_cleanup(&hdlcd->crtc);
101setup_fail:
102 of_reserved_mem_device_release(drm->dev);
103
104 return ret;
105}
106
107static void hdlcd_fb_output_poll_changed(struct drm_device *drm)
108{
109 struct hdlcd_drm_private *hdlcd = drm->dev_private;
110
111 if (hdlcd->fbdev)
112 drm_fbdev_cma_hotplug_event(hdlcd->fbdev);
113}
114
115static int hdlcd_atomic_commit(struct drm_device *dev,
116 struct drm_atomic_state *state, bool async)
117{
118 return drm_atomic_helper_commit(dev, state, false);
119}
120
121static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
122 .fb_create = drm_fb_cma_create,
123 .output_poll_changed = hdlcd_fb_output_poll_changed,
124 .atomic_check = drm_atomic_helper_check,
125 .atomic_commit = hdlcd_atomic_commit,
126};
127
128static void hdlcd_setup_mode_config(struct drm_device *drm)
129{
130 drm_mode_config_init(drm);
131 drm->mode_config.min_width = 0;
132 drm->mode_config.min_height = 0;
133 drm->mode_config.max_width = HDLCD_MAX_XRES;
134 drm->mode_config.max_height = HDLCD_MAX_YRES;
135 drm->mode_config.funcs = &hdlcd_mode_config_funcs;
136}
137
138static void hdlcd_lastclose(struct drm_device *drm)
139{
140 struct hdlcd_drm_private *hdlcd = drm->dev_private;
141
142 drm_fbdev_cma_restore_mode(hdlcd->fbdev);
143}
144
145static irqreturn_t hdlcd_irq(int irq, void *arg)
146{
147 struct drm_device *drm = arg;
148 struct hdlcd_drm_private *hdlcd = drm->dev_private;
149 unsigned long irq_status;
150
151 irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
152
153#ifdef CONFIG_DEBUG_FS
154 if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
155 atomic_inc(&hdlcd->buffer_underrun_count);
156
157 if (irq_status & HDLCD_INTERRUPT_DMA_END)
158 atomic_inc(&hdlcd->dma_end_count);
159
160 if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
161 atomic_inc(&hdlcd->bus_error_count);
162
163 if (irq_status & HDLCD_INTERRUPT_VSYNC)
164 atomic_inc(&hdlcd->vsync_count);
165
166#endif
167 if (irq_status & HDLCD_INTERRUPT_VSYNC) {
168 bool events_sent = false;
169 unsigned long flags;
170 struct drm_pending_vblank_event *e, *t;
171
172 drm_crtc_handle_vblank(&hdlcd->crtc);
173
174 spin_lock_irqsave(&drm->event_lock, flags);
175 list_for_each_entry_safe(e, t, &hdlcd->event_list, base.link) {
176 list_del(&e->base.link);
177 drm_crtc_send_vblank_event(&hdlcd->crtc, e);
178 events_sent = true;
179 }
180 if (events_sent)
181 drm_crtc_vblank_put(&hdlcd->crtc);
182 spin_unlock_irqrestore(&drm->event_lock, flags);
183 }
184
185 /* acknowledge interrupt(s) */
186 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
187
188 return IRQ_HANDLED;
189}
190
191static void hdlcd_irq_preinstall(struct drm_device *drm)
192{
193 struct hdlcd_drm_private *hdlcd = drm->dev_private;
194 /* Ensure interrupts are disabled */
195 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
196 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
197}
198
199static int hdlcd_irq_postinstall(struct drm_device *drm)
200{
201#ifdef CONFIG_DEBUG_FS
202 struct hdlcd_drm_private *hdlcd = drm->dev_private;
203 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
204
205 /* enable debug interrupts */
206 irq_mask |= HDLCD_DEBUG_INT_MASK;
207
208 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
209#endif
210 return 0;
211}
212
213static void hdlcd_irq_uninstall(struct drm_device *drm)
214{
215 struct hdlcd_drm_private *hdlcd = drm->dev_private;
216 /* disable all the interrupts that we might have enabled */
217 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
218
219#ifdef CONFIG_DEBUG_FS
220 /* disable debug interrupts */
221 irq_mask &= ~HDLCD_DEBUG_INT_MASK;
222#endif
223
224 /* disable vsync interrupts */
225 irq_mask &= ~HDLCD_INTERRUPT_VSYNC;
226
227 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
228}
229
230static int hdlcd_enable_vblank(struct drm_device *drm, unsigned int crtc)
231{
232 struct hdlcd_drm_private *hdlcd = drm->dev_private;
233 unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
234
235 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC);
236
237 return 0;
238}
239
240static void hdlcd_disable_vblank(struct drm_device *drm, unsigned int crtc)
241{
242 struct hdlcd_drm_private *hdlcd = drm->dev_private;
243 unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
244
245 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC);
246}
247
248#ifdef CONFIG_DEBUG_FS
249static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
250{
251 struct drm_info_node *node = (struct drm_info_node *)m->private;
252 struct drm_device *drm = node->minor->dev;
253 struct hdlcd_drm_private *hdlcd = drm->dev_private;
254
255 seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
256 seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count));
257 seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
258 seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count));
259 return 0;
260}
261
262static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
263{
264 struct drm_info_node *node = (struct drm_info_node *)m->private;
265 struct drm_device *drm = node->minor->dev;
266 struct hdlcd_drm_private *hdlcd = drm->dev_private;
267 unsigned long clkrate = clk_get_rate(hdlcd->clk);
268 unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
269
270 seq_printf(m, "hw : %lu\n", clkrate);
271 seq_printf(m, "mode: %lu\n", mode_clock);
272 return 0;
273}
274
275static struct drm_info_list hdlcd_debugfs_list[] = {
276 { "interrupt_count", hdlcd_show_underrun_count, 0 },
277 { "clocks", hdlcd_show_pxlclock, 0 },
278};
279
280static int hdlcd_debugfs_init(struct drm_minor *minor)
281{
282 return drm_debugfs_create_files(hdlcd_debugfs_list,
283 ARRAY_SIZE(hdlcd_debugfs_list), minor->debugfs_root, minor);
284}
285
286static void hdlcd_debugfs_cleanup(struct drm_minor *minor)
287{
288 drm_debugfs_remove_files(hdlcd_debugfs_list,
289 ARRAY_SIZE(hdlcd_debugfs_list), minor);
290}
291#endif
292
293static const struct file_operations fops = {
294 .owner = THIS_MODULE,
295 .open = drm_open,
296 .release = drm_release,
297 .unlocked_ioctl = drm_ioctl,
298#ifdef CONFIG_COMPAT
299 .compat_ioctl = drm_compat_ioctl,
300#endif
301 .poll = drm_poll,
302 .read = drm_read,
303 .llseek = noop_llseek,
304 .mmap = drm_gem_cma_mmap,
305};
306
307static struct drm_driver hdlcd_driver = {
308 .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
309 DRIVER_MODESET | DRIVER_PRIME |
310 DRIVER_ATOMIC,
311 .lastclose = hdlcd_lastclose,
312 .irq_handler = hdlcd_irq,
313 .irq_preinstall = hdlcd_irq_preinstall,
314 .irq_postinstall = hdlcd_irq_postinstall,
315 .irq_uninstall = hdlcd_irq_uninstall,
316 .get_vblank_counter = drm_vblank_no_hw_counter,
317 .enable_vblank = hdlcd_enable_vblank,
318 .disable_vblank = hdlcd_disable_vblank,
319 .gem_free_object = drm_gem_cma_free_object,
320 .gem_vm_ops = &drm_gem_cma_vm_ops,
321 .dumb_create = drm_gem_cma_dumb_create,
322 .dumb_map_offset = drm_gem_cma_dumb_map_offset,
323 .dumb_destroy = drm_gem_dumb_destroy,
324 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
325 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
326 .gem_prime_export = drm_gem_prime_export,
327 .gem_prime_import = drm_gem_prime_import,
328 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
329 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
330 .gem_prime_vmap = drm_gem_cma_prime_vmap,
331 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
332 .gem_prime_mmap = drm_gem_cma_prime_mmap,
333#ifdef CONFIG_DEBUG_FS
334 .debugfs_init = hdlcd_debugfs_init,
335 .debugfs_cleanup = hdlcd_debugfs_cleanup,
336#endif
337 .fops = &fops,
338 .name = "hdlcd",
339 .desc = "ARM HDLCD Controller DRM",
340 .date = "20151021",
341 .major = 1,
342 .minor = 0,
343};
344
345static int hdlcd_drm_bind(struct device *dev)
346{
347 struct drm_device *drm;
348 struct hdlcd_drm_private *hdlcd;
349 int ret;
350
351 hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL);
352 if (!hdlcd)
353 return -ENOMEM;
354
355 drm = drm_dev_alloc(&hdlcd_driver, dev);
356 if (!drm)
357 return -ENOMEM;
358
359 drm->dev_private = hdlcd;
360 hdlcd_setup_mode_config(drm);
361 ret = hdlcd_load(drm, 0);
362 if (ret)
363 goto err_free;
364
365 ret = drm_dev_register(drm, 0);
366 if (ret)
367 goto err_unload;
368
369 dev_set_drvdata(dev, drm);
370
371 ret = component_bind_all(dev, drm);
372 if (ret) {
373 DRM_ERROR("Failed to bind all components\n");
374 goto err_unregister;
375 }
376
377 ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
378 if (ret < 0) {
379 DRM_ERROR("failed to initialise vblank\n");
380 goto err_vblank;
381 }
382 drm->vblank_disable_allowed = true;
383
384 drm_mode_config_reset(drm);
385 drm_kms_helper_poll_init(drm);
386
387 hdlcd->fbdev = drm_fbdev_cma_init(drm, 32, drm->mode_config.num_crtc,
388 drm->mode_config.num_connector);
389
390 if (IS_ERR(hdlcd->fbdev)) {
391 ret = PTR_ERR(hdlcd->fbdev);
392 hdlcd->fbdev = NULL;
393 goto err_fbdev;
394 }
395
396 return 0;
397
398err_fbdev:
399 drm_kms_helper_poll_fini(drm);
400 drm_mode_config_cleanup(drm);
401 drm_vblank_cleanup(drm);
402err_vblank:
403 component_unbind_all(dev, drm);
404err_unregister:
405 drm_dev_unregister(drm);
406err_unload:
407 pm_runtime_get_sync(drm->dev);
408 drm_irq_uninstall(drm);
409 pm_runtime_put_sync(drm->dev);
410 pm_runtime_disable(drm->dev);
411 of_reserved_mem_device_release(drm->dev);
412err_free:
413 drm_dev_unref(drm);
414
415 return ret;
416}
417
418static void hdlcd_drm_unbind(struct device *dev)
419{
420 struct drm_device *drm = dev_get_drvdata(dev);
421 struct hdlcd_drm_private *hdlcd = drm->dev_private;
422
423 if (hdlcd->fbdev) {
424 drm_fbdev_cma_fini(hdlcd->fbdev);
425 hdlcd->fbdev = NULL;
426 }
427 drm_kms_helper_poll_fini(drm);
428 component_unbind_all(dev, drm);
429 drm_vblank_cleanup(drm);
430 pm_runtime_get_sync(drm->dev);
431 drm_irq_uninstall(drm);
432 pm_runtime_put_sync(drm->dev);
433 pm_runtime_disable(drm->dev);
434 of_reserved_mem_device_release(drm->dev);
435 drm_mode_config_cleanup(drm);
436 drm_dev_unregister(drm);
437 drm_dev_unref(drm);
438 drm->dev_private = NULL;
439 dev_set_drvdata(dev, NULL);
440}
441
442static const struct component_master_ops hdlcd_master_ops = {
443 .bind = hdlcd_drm_bind,
444 .unbind = hdlcd_drm_unbind,
445};
446
447static int compare_dev(struct device *dev, void *data)
448{
449 return dev->of_node == data;
450}
451
452static int hdlcd_probe(struct platform_device *pdev)
453{
454 struct device_node *port, *ep;
455 struct component_match *match = NULL;
456
457 if (!pdev->dev.of_node)
458 return -ENODEV;
459
460 /* there is only one output port inside each device, find it */
461 ep = of_graph_get_next_endpoint(pdev->dev.of_node, NULL);
462 if (!ep)
463 return -ENODEV;
464
465 if (!of_device_is_available(ep)) {
466 of_node_put(ep);
467 return -ENODEV;
468 }
469
470 /* add the remote encoder port as component */
471 port = of_graph_get_remote_port_parent(ep);
472 of_node_put(ep);
473 if (!port || !of_device_is_available(port)) {
474 of_node_put(port);
475 return -EAGAIN;
476 }
477
478 component_match_add(&pdev->dev, &match, compare_dev, port);
479
480 return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
481 match);
482}
483
484static int hdlcd_remove(struct platform_device *pdev)
485{
486 component_master_del(&pdev->dev, &hdlcd_master_ops);
487 return 0;
488}
489
490static const struct of_device_id hdlcd_of_match[] = {
491 { .compatible = "arm,hdlcd" },
492 {},
493};
494MODULE_DEVICE_TABLE(of, hdlcd_of_match);
495
496static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
497{
498 struct drm_device *drm = dev_get_drvdata(dev);
499 struct drm_crtc *crtc;
500
501 if (pm_runtime_suspended(dev))
502 return 0;
503
504 drm_modeset_lock_all(drm);
505 list_for_each_entry(crtc, &drm->mode_config.crtc_list, head)
506 hdlcd_crtc_suspend(crtc);
507 drm_modeset_unlock_all(drm);
508 return 0;
509}
510
511static int __maybe_unused hdlcd_pm_resume(struct device *dev)
512{
513 struct drm_device *drm = dev_get_drvdata(dev);
514 struct drm_crtc *crtc;
515
516 if (!pm_runtime_suspended(dev))
517 return 0;
518
519 drm_modeset_lock_all(drm);
520 list_for_each_entry(crtc, &drm->mode_config.crtc_list, head)
521 hdlcd_crtc_resume(crtc);
522 drm_modeset_unlock_all(drm);
523 return 0;
524}
525
526static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
527
528static struct platform_driver hdlcd_platform_driver = {
529 .probe = hdlcd_probe,
530 .remove = hdlcd_remove,
531 .driver = {
532 .name = "hdlcd",
533 .pm = &hdlcd_pm_ops,
534 .of_match_table = hdlcd_of_match,
535 },
536};
537
538module_platform_driver(hdlcd_platform_driver);
539
540MODULE_AUTHOR("Liviu Dudau");
541MODULE_DESCRIPTION("ARM HDLCD DRM driver");
542MODULE_LICENSE("GPL v2");