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1/*
2 * Copyright (C) 2013-2015 ARM Limited
3 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive
7 * for more details.
8 *
9 * ARM HDLCD Driver
10 */
11
12#include <linux/module.h>
13#include <linux/spinlock.h>
14#include <linux/clk.h>
15#include <linux/component.h>
16#include <linux/console.h>
17#include <linux/dma-mapping.h>
18#include <linux/list.h>
19#include <linux/of_graph.h>
20#include <linux/of_reserved_mem.h>
21#include <linux/platform_device.h>
22#include <linux/pm_runtime.h>
23
24#include <drm/drm_atomic_helper.h>
25#include <drm/drm_crtc.h>
26#include <drm/drm_debugfs.h>
27#include <drm/drm_drv.h>
28#include <drm/drm_fb_cma_helper.h>
29#include <drm/drm_fb_helper.h>
30#include <drm/drm_gem_cma_helper.h>
31#include <drm/drm_gem_framebuffer_helper.h>
32#include <drm/drm_irq.h>
33#include <drm/drm_modeset_helper.h>
34#include <drm/drm_of.h>
35#include <drm/drm_probe_helper.h>
36#include <drm/drm_vblank.h>
37
38#include "hdlcd_drv.h"
39#include "hdlcd_regs.h"
40
41static int hdlcd_load(struct drm_device *drm, unsigned long flags)
42{
43 struct hdlcd_drm_private *hdlcd = drm->dev_private;
44 struct platform_device *pdev = to_platform_device(drm->dev);
45 struct resource *res;
46 u32 version;
47 int ret;
48
49 hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
50 if (IS_ERR(hdlcd->clk))
51 return PTR_ERR(hdlcd->clk);
52
53#ifdef CONFIG_DEBUG_FS
54 atomic_set(&hdlcd->buffer_underrun_count, 0);
55 atomic_set(&hdlcd->bus_error_count, 0);
56 atomic_set(&hdlcd->vsync_count, 0);
57 atomic_set(&hdlcd->dma_end_count, 0);
58#endif
59
60 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
61 hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
62 if (IS_ERR(hdlcd->mmio)) {
63 DRM_ERROR("failed to map control registers area\n");
64 ret = PTR_ERR(hdlcd->mmio);
65 hdlcd->mmio = NULL;
66 return ret;
67 }
68
69 version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
70 if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
71 DRM_ERROR("unknown product id: 0x%x\n", version);
72 return -EINVAL;
73 }
74 DRM_INFO("found ARM HDLCD version r%dp%d\n",
75 (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
76 version & HDLCD_VERSION_MINOR_MASK);
77
78 /* Get the optional framebuffer memory resource */
79 ret = of_reserved_mem_device_init(drm->dev);
80 if (ret && ret != -ENODEV)
81 return ret;
82
83 ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
84 if (ret)
85 goto setup_fail;
86
87 ret = hdlcd_setup_crtc(drm);
88 if (ret < 0) {
89 DRM_ERROR("failed to create crtc\n");
90 goto setup_fail;
91 }
92
93 ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
94 if (ret < 0) {
95 DRM_ERROR("failed to install IRQ handler\n");
96 goto irq_fail;
97 }
98
99 return 0;
100
101irq_fail:
102 drm_crtc_cleanup(&hdlcd->crtc);
103setup_fail:
104 of_reserved_mem_device_release(drm->dev);
105
106 return ret;
107}
108
109static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
110 .fb_create = drm_gem_fb_create,
111 .atomic_check = drm_atomic_helper_check,
112 .atomic_commit = drm_atomic_helper_commit,
113};
114
115static void hdlcd_setup_mode_config(struct drm_device *drm)
116{
117 drm_mode_config_init(drm);
118 drm->mode_config.min_width = 0;
119 drm->mode_config.min_height = 0;
120 drm->mode_config.max_width = HDLCD_MAX_XRES;
121 drm->mode_config.max_height = HDLCD_MAX_YRES;
122 drm->mode_config.funcs = &hdlcd_mode_config_funcs;
123}
124
125static irqreturn_t hdlcd_irq(int irq, void *arg)
126{
127 struct drm_device *drm = arg;
128 struct hdlcd_drm_private *hdlcd = drm->dev_private;
129 unsigned long irq_status;
130
131 irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
132
133#ifdef CONFIG_DEBUG_FS
134 if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
135 atomic_inc(&hdlcd->buffer_underrun_count);
136
137 if (irq_status & HDLCD_INTERRUPT_DMA_END)
138 atomic_inc(&hdlcd->dma_end_count);
139
140 if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
141 atomic_inc(&hdlcd->bus_error_count);
142
143 if (irq_status & HDLCD_INTERRUPT_VSYNC)
144 atomic_inc(&hdlcd->vsync_count);
145
146#endif
147 if (irq_status & HDLCD_INTERRUPT_VSYNC)
148 drm_crtc_handle_vblank(&hdlcd->crtc);
149
150 /* acknowledge interrupt(s) */
151 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
152
153 return IRQ_HANDLED;
154}
155
156static void hdlcd_irq_preinstall(struct drm_device *drm)
157{
158 struct hdlcd_drm_private *hdlcd = drm->dev_private;
159 /* Ensure interrupts are disabled */
160 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
161 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
162}
163
164static int hdlcd_irq_postinstall(struct drm_device *drm)
165{
166#ifdef CONFIG_DEBUG_FS
167 struct hdlcd_drm_private *hdlcd = drm->dev_private;
168 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
169
170 /* enable debug interrupts */
171 irq_mask |= HDLCD_DEBUG_INT_MASK;
172
173 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
174#endif
175 return 0;
176}
177
178static void hdlcd_irq_uninstall(struct drm_device *drm)
179{
180 struct hdlcd_drm_private *hdlcd = drm->dev_private;
181 /* disable all the interrupts that we might have enabled */
182 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
183
184#ifdef CONFIG_DEBUG_FS
185 /* disable debug interrupts */
186 irq_mask &= ~HDLCD_DEBUG_INT_MASK;
187#endif
188
189 /* disable vsync interrupts */
190 irq_mask &= ~HDLCD_INTERRUPT_VSYNC;
191
192 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
193}
194
195#ifdef CONFIG_DEBUG_FS
196static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
197{
198 struct drm_info_node *node = (struct drm_info_node *)m->private;
199 struct drm_device *drm = node->minor->dev;
200 struct hdlcd_drm_private *hdlcd = drm->dev_private;
201
202 seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
203 seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count));
204 seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
205 seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count));
206 return 0;
207}
208
209static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
210{
211 struct drm_info_node *node = (struct drm_info_node *)m->private;
212 struct drm_device *drm = node->minor->dev;
213 struct hdlcd_drm_private *hdlcd = drm->dev_private;
214 unsigned long clkrate = clk_get_rate(hdlcd->clk);
215 unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
216
217 seq_printf(m, "hw : %lu\n", clkrate);
218 seq_printf(m, "mode: %lu\n", mode_clock);
219 return 0;
220}
221
222static struct drm_info_list hdlcd_debugfs_list[] = {
223 { "interrupt_count", hdlcd_show_underrun_count, 0 },
224 { "clocks", hdlcd_show_pxlclock, 0 },
225};
226
227static int hdlcd_debugfs_init(struct drm_minor *minor)
228{
229 return drm_debugfs_create_files(hdlcd_debugfs_list,
230 ARRAY_SIZE(hdlcd_debugfs_list), minor->debugfs_root, minor);
231}
232#endif
233
234DEFINE_DRM_GEM_CMA_FOPS(fops);
235
236static struct drm_driver hdlcd_driver = {
237 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
238 .irq_handler = hdlcd_irq,
239 .irq_preinstall = hdlcd_irq_preinstall,
240 .irq_postinstall = hdlcd_irq_postinstall,
241 .irq_uninstall = hdlcd_irq_uninstall,
242 .gem_free_object_unlocked = drm_gem_cma_free_object,
243 .gem_print_info = drm_gem_cma_print_info,
244 .gem_vm_ops = &drm_gem_cma_vm_ops,
245 .dumb_create = drm_gem_cma_dumb_create,
246 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
247 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
248 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
249 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
250 .gem_prime_vmap = drm_gem_cma_prime_vmap,
251 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
252 .gem_prime_mmap = drm_gem_cma_prime_mmap,
253#ifdef CONFIG_DEBUG_FS
254 .debugfs_init = hdlcd_debugfs_init,
255#endif
256 .fops = &fops,
257 .name = "hdlcd",
258 .desc = "ARM HDLCD Controller DRM",
259 .date = "20151021",
260 .major = 1,
261 .minor = 0,
262};
263
264static int hdlcd_drm_bind(struct device *dev)
265{
266 struct drm_device *drm;
267 struct hdlcd_drm_private *hdlcd;
268 int ret;
269
270 hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL);
271 if (!hdlcd)
272 return -ENOMEM;
273
274 drm = drm_dev_alloc(&hdlcd_driver, dev);
275 if (IS_ERR(drm))
276 return PTR_ERR(drm);
277
278 drm->dev_private = hdlcd;
279 dev_set_drvdata(dev, drm);
280
281 hdlcd_setup_mode_config(drm);
282 ret = hdlcd_load(drm, 0);
283 if (ret)
284 goto err_free;
285
286 /* Set the CRTC's port so that the encoder component can find it */
287 hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
288
289 ret = component_bind_all(dev, drm);
290 if (ret) {
291 DRM_ERROR("Failed to bind all components\n");
292 goto err_unload;
293 }
294
295 ret = pm_runtime_set_active(dev);
296 if (ret)
297 goto err_pm_active;
298
299 pm_runtime_enable(dev);
300
301 ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
302 if (ret < 0) {
303 DRM_ERROR("failed to initialise vblank\n");
304 goto err_vblank;
305 }
306
307 drm_mode_config_reset(drm);
308 drm_kms_helper_poll_init(drm);
309
310 ret = drm_dev_register(drm, 0);
311 if (ret)
312 goto err_register;
313
314 drm_fbdev_generic_setup(drm, 32);
315
316 return 0;
317
318err_register:
319 drm_kms_helper_poll_fini(drm);
320err_vblank:
321 pm_runtime_disable(drm->dev);
322err_pm_active:
323 drm_atomic_helper_shutdown(drm);
324 component_unbind_all(dev, drm);
325err_unload:
326 of_node_put(hdlcd->crtc.port);
327 hdlcd->crtc.port = NULL;
328 drm_irq_uninstall(drm);
329 of_reserved_mem_device_release(drm->dev);
330err_free:
331 drm_mode_config_cleanup(drm);
332 dev_set_drvdata(dev, NULL);
333 drm_dev_put(drm);
334
335 return ret;
336}
337
338static void hdlcd_drm_unbind(struct device *dev)
339{
340 struct drm_device *drm = dev_get_drvdata(dev);
341 struct hdlcd_drm_private *hdlcd = drm->dev_private;
342
343 drm_dev_unregister(drm);
344 drm_kms_helper_poll_fini(drm);
345 component_unbind_all(dev, drm);
346 of_node_put(hdlcd->crtc.port);
347 hdlcd->crtc.port = NULL;
348 pm_runtime_get_sync(dev);
349 drm_crtc_vblank_off(&hdlcd->crtc);
350 drm_irq_uninstall(drm);
351 drm_atomic_helper_shutdown(drm);
352 pm_runtime_put(dev);
353 if (pm_runtime_enabled(dev))
354 pm_runtime_disable(dev);
355 of_reserved_mem_device_release(dev);
356 drm_mode_config_cleanup(drm);
357 drm->dev_private = NULL;
358 dev_set_drvdata(dev, NULL);
359 drm_dev_put(drm);
360}
361
362static const struct component_master_ops hdlcd_master_ops = {
363 .bind = hdlcd_drm_bind,
364 .unbind = hdlcd_drm_unbind,
365};
366
367static int compare_dev(struct device *dev, void *data)
368{
369 return dev->of_node == data;
370}
371
372static int hdlcd_probe(struct platform_device *pdev)
373{
374 struct device_node *port;
375 struct component_match *match = NULL;
376
377 /* there is only one output port inside each device, find it */
378 port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
379 if (!port)
380 return -ENODEV;
381
382 drm_of_component_match_add(&pdev->dev, &match, compare_dev, port);
383 of_node_put(port);
384
385 return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
386 match);
387}
388
389static int hdlcd_remove(struct platform_device *pdev)
390{
391 component_master_del(&pdev->dev, &hdlcd_master_ops);
392 return 0;
393}
394
395static const struct of_device_id hdlcd_of_match[] = {
396 { .compatible = "arm,hdlcd" },
397 {},
398};
399MODULE_DEVICE_TABLE(of, hdlcd_of_match);
400
401static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
402{
403 struct drm_device *drm = dev_get_drvdata(dev);
404
405 return drm_mode_config_helper_suspend(drm);
406}
407
408static int __maybe_unused hdlcd_pm_resume(struct device *dev)
409{
410 struct drm_device *drm = dev_get_drvdata(dev);
411
412 drm_mode_config_helper_resume(drm);
413
414 return 0;
415}
416
417static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
418
419static struct platform_driver hdlcd_platform_driver = {
420 .probe = hdlcd_probe,
421 .remove = hdlcd_remove,
422 .driver = {
423 .name = "hdlcd",
424 .pm = &hdlcd_pm_ops,
425 .of_match_table = hdlcd_of_match,
426 },
427};
428
429module_platform_driver(hdlcd_platform_driver);
430
431MODULE_AUTHOR("Liviu Dudau");
432MODULE_DESCRIPTION("ARM HDLCD DRM driver");
433MODULE_LICENSE("GPL v2");
1/*
2 * Copyright (C) 2013-2015 ARM Limited
3 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive
7 * for more details.
8 *
9 * ARM HDLCD Driver
10 */
11
12#include <linux/module.h>
13#include <linux/spinlock.h>
14#include <linux/clk.h>
15#include <linux/component.h>
16#include <linux/console.h>
17#include <linux/dma-mapping.h>
18#include <linux/list.h>
19#include <linux/of_graph.h>
20#include <linux/of_reserved_mem.h>
21#include <linux/platform_device.h>
22#include <linux/pm_runtime.h>
23
24#include <drm/drm_aperture.h>
25#include <drm/drm_atomic_helper.h>
26#include <drm/drm_crtc.h>
27#include <drm/drm_debugfs.h>
28#include <drm/drm_drv.h>
29#include <drm/drm_fbdev_dma.h>
30#include <drm/drm_gem_dma_helper.h>
31#include <drm/drm_gem_framebuffer_helper.h>
32#include <drm/drm_modeset_helper.h>
33#include <drm/drm_module.h>
34#include <drm/drm_of.h>
35#include <drm/drm_probe_helper.h>
36#include <drm/drm_vblank.h>
37
38#include "hdlcd_drv.h"
39#include "hdlcd_regs.h"
40
41static irqreturn_t hdlcd_irq(int irq, void *arg)
42{
43 struct hdlcd_drm_private *hdlcd = arg;
44 unsigned long irq_status;
45
46 irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
47
48#ifdef CONFIG_DEBUG_FS
49 if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
50 atomic_inc(&hdlcd->buffer_underrun_count);
51
52 if (irq_status & HDLCD_INTERRUPT_DMA_END)
53 atomic_inc(&hdlcd->dma_end_count);
54
55 if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
56 atomic_inc(&hdlcd->bus_error_count);
57
58 if (irq_status & HDLCD_INTERRUPT_VSYNC)
59 atomic_inc(&hdlcd->vsync_count);
60
61#endif
62 if (irq_status & HDLCD_INTERRUPT_VSYNC)
63 drm_crtc_handle_vblank(&hdlcd->crtc);
64
65 /* acknowledge interrupt(s) */
66 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
67
68 return IRQ_HANDLED;
69}
70
71static int hdlcd_irq_install(struct hdlcd_drm_private *hdlcd)
72{
73 int ret;
74
75 /* Ensure interrupts are disabled */
76 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
77 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
78
79 ret = request_irq(hdlcd->irq, hdlcd_irq, 0, "hdlcd", hdlcd);
80 if (ret)
81 return ret;
82
83#ifdef CONFIG_DEBUG_FS
84 /* enable debug interrupts */
85 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, HDLCD_DEBUG_INT_MASK);
86#endif
87
88 return 0;
89}
90
91static void hdlcd_irq_uninstall(struct hdlcd_drm_private *hdlcd)
92{
93 /* disable all the interrupts that we might have enabled */
94 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
95
96 free_irq(hdlcd->irq, hdlcd);
97}
98
99static int hdlcd_load(struct drm_device *drm, unsigned long flags)
100{
101 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
102 struct platform_device *pdev = to_platform_device(drm->dev);
103 u32 version;
104 int ret;
105
106 hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
107 if (IS_ERR(hdlcd->clk))
108 return PTR_ERR(hdlcd->clk);
109
110#ifdef CONFIG_DEBUG_FS
111 atomic_set(&hdlcd->buffer_underrun_count, 0);
112 atomic_set(&hdlcd->bus_error_count, 0);
113 atomic_set(&hdlcd->vsync_count, 0);
114 atomic_set(&hdlcd->dma_end_count, 0);
115#endif
116
117 hdlcd->mmio = devm_platform_ioremap_resource(pdev, 0);
118 if (IS_ERR(hdlcd->mmio)) {
119 DRM_ERROR("failed to map control registers area\n");
120 ret = PTR_ERR(hdlcd->mmio);
121 hdlcd->mmio = NULL;
122 return ret;
123 }
124
125 version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
126 if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
127 DRM_ERROR("unknown product id: 0x%x\n", version);
128 return -EINVAL;
129 }
130 DRM_INFO("found ARM HDLCD version r%dp%d\n",
131 (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
132 version & HDLCD_VERSION_MINOR_MASK);
133
134 /* Get the optional framebuffer memory resource */
135 ret = of_reserved_mem_device_init(drm->dev);
136 if (ret && ret != -ENODEV)
137 return ret;
138
139 ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
140 if (ret)
141 goto setup_fail;
142
143 ret = hdlcd_setup_crtc(drm);
144 if (ret < 0) {
145 DRM_ERROR("failed to create crtc\n");
146 goto setup_fail;
147 }
148
149 ret = platform_get_irq(pdev, 0);
150 if (ret < 0)
151 goto irq_fail;
152 hdlcd->irq = ret;
153
154 ret = hdlcd_irq_install(hdlcd);
155 if (ret < 0) {
156 DRM_ERROR("failed to install IRQ handler\n");
157 goto irq_fail;
158 }
159
160 return 0;
161
162irq_fail:
163 drm_crtc_cleanup(&hdlcd->crtc);
164setup_fail:
165 of_reserved_mem_device_release(drm->dev);
166
167 return ret;
168}
169
170static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
171 .fb_create = drm_gem_fb_create,
172 .atomic_check = drm_atomic_helper_check,
173 .atomic_commit = drm_atomic_helper_commit,
174};
175
176static int hdlcd_setup_mode_config(struct drm_device *drm)
177{
178 int ret;
179
180 ret = drmm_mode_config_init(drm);
181 if (ret)
182 return ret;
183
184 drm->mode_config.min_width = 0;
185 drm->mode_config.min_height = 0;
186 drm->mode_config.max_width = HDLCD_MAX_XRES;
187 drm->mode_config.max_height = HDLCD_MAX_YRES;
188 drm->mode_config.funcs = &hdlcd_mode_config_funcs;
189
190 return 0;
191}
192
193#ifdef CONFIG_DEBUG_FS
194static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
195{
196 struct drm_debugfs_entry *entry = m->private;
197 struct drm_device *drm = entry->dev;
198 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
199
200 seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
201 seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count));
202 seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
203 seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count));
204 return 0;
205}
206
207static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
208{
209 struct drm_debugfs_entry *entry = m->private;
210 struct drm_device *drm = entry->dev;
211 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
212 unsigned long clkrate = clk_get_rate(hdlcd->clk);
213 unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
214
215 seq_printf(m, "hw : %lu\n", clkrate);
216 seq_printf(m, "mode: %lu\n", mode_clock);
217 return 0;
218}
219
220static struct drm_debugfs_info hdlcd_debugfs_list[] = {
221 { "interrupt_count", hdlcd_show_underrun_count, 0 },
222 { "clocks", hdlcd_show_pxlclock, 0 },
223};
224#endif
225
226DEFINE_DRM_GEM_DMA_FOPS(fops);
227
228static const struct drm_driver hdlcd_driver = {
229 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
230 DRM_GEM_DMA_DRIVER_OPS,
231 .fops = &fops,
232 .name = "hdlcd",
233 .desc = "ARM HDLCD Controller DRM",
234 .date = "20151021",
235 .major = 1,
236 .minor = 0,
237};
238
239static int hdlcd_drm_bind(struct device *dev)
240{
241 struct drm_device *drm;
242 struct hdlcd_drm_private *hdlcd;
243 int ret;
244
245 hdlcd = devm_drm_dev_alloc(dev, &hdlcd_driver, typeof(*hdlcd), base);
246 if (IS_ERR(hdlcd))
247 return PTR_ERR(hdlcd);
248
249 drm = &hdlcd->base;
250
251 dev_set_drvdata(dev, drm);
252
253 ret = hdlcd_setup_mode_config(drm);
254 if (ret)
255 goto err_free;
256
257 ret = hdlcd_load(drm, 0);
258 if (ret)
259 goto err_free;
260
261 /* Set the CRTC's port so that the encoder component can find it */
262 hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
263
264 ret = component_bind_all(dev, drm);
265 if (ret) {
266 DRM_ERROR("Failed to bind all components\n");
267 goto err_unload;
268 }
269
270 ret = pm_runtime_set_active(dev);
271 if (ret)
272 goto err_pm_active;
273
274 pm_runtime_enable(dev);
275
276 ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
277 if (ret < 0) {
278 DRM_ERROR("failed to initialise vblank\n");
279 goto err_vblank;
280 }
281
282 /*
283 * If EFI left us running, take over from simple framebuffer
284 * drivers. Read HDLCD_REG_COMMAND to see if we are enabled.
285 */
286 if (hdlcd_read(hdlcd, HDLCD_REG_COMMAND)) {
287 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
288 drm_aperture_remove_framebuffers(&hdlcd_driver);
289 }
290
291 drm_mode_config_reset(drm);
292 drm_kms_helper_poll_init(drm);
293
294#ifdef CONFIG_DEBUG_FS
295 drm_debugfs_add_files(drm, hdlcd_debugfs_list, ARRAY_SIZE(hdlcd_debugfs_list));
296#endif
297
298 ret = drm_dev_register(drm, 0);
299 if (ret)
300 goto err_register;
301
302 drm_fbdev_dma_setup(drm, 32);
303
304 return 0;
305
306err_register:
307 drm_kms_helper_poll_fini(drm);
308err_vblank:
309 pm_runtime_disable(drm->dev);
310err_pm_active:
311 drm_atomic_helper_shutdown(drm);
312 component_unbind_all(dev, drm);
313err_unload:
314 of_node_put(hdlcd->crtc.port);
315 hdlcd->crtc.port = NULL;
316 hdlcd_irq_uninstall(hdlcd);
317 of_reserved_mem_device_release(drm->dev);
318err_free:
319 dev_set_drvdata(dev, NULL);
320 return ret;
321}
322
323static void hdlcd_drm_unbind(struct device *dev)
324{
325 struct drm_device *drm = dev_get_drvdata(dev);
326 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
327
328 drm_dev_unregister(drm);
329 drm_kms_helper_poll_fini(drm);
330 component_unbind_all(dev, drm);
331 of_node_put(hdlcd->crtc.port);
332 hdlcd->crtc.port = NULL;
333 pm_runtime_get_sync(dev);
334 drm_atomic_helper_shutdown(drm);
335 hdlcd_irq_uninstall(hdlcd);
336 pm_runtime_put(dev);
337 if (pm_runtime_enabled(dev))
338 pm_runtime_disable(dev);
339 of_reserved_mem_device_release(dev);
340 dev_set_drvdata(dev, NULL);
341}
342
343static const struct component_master_ops hdlcd_master_ops = {
344 .bind = hdlcd_drm_bind,
345 .unbind = hdlcd_drm_unbind,
346};
347
348static int compare_dev(struct device *dev, void *data)
349{
350 return dev->of_node == data;
351}
352
353static int hdlcd_probe(struct platform_device *pdev)
354{
355 struct device_node *port;
356 struct component_match *match = NULL;
357
358 /* there is only one output port inside each device, find it */
359 port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
360 if (!port)
361 return -ENODEV;
362
363 drm_of_component_match_add(&pdev->dev, &match, compare_dev, port);
364 of_node_put(port);
365
366 return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
367 match);
368}
369
370static void hdlcd_remove(struct platform_device *pdev)
371{
372 component_master_del(&pdev->dev, &hdlcd_master_ops);
373}
374
375static void hdlcd_shutdown(struct platform_device *pdev)
376{
377 drm_atomic_helper_shutdown(platform_get_drvdata(pdev));
378}
379
380static const struct of_device_id hdlcd_of_match[] = {
381 { .compatible = "arm,hdlcd" },
382 {},
383};
384MODULE_DEVICE_TABLE(of, hdlcd_of_match);
385
386static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
387{
388 struct drm_device *drm = dev_get_drvdata(dev);
389
390 return drm_mode_config_helper_suspend(drm);
391}
392
393static int __maybe_unused hdlcd_pm_resume(struct device *dev)
394{
395 struct drm_device *drm = dev_get_drvdata(dev);
396
397 drm_mode_config_helper_resume(drm);
398
399 return 0;
400}
401
402static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
403
404static struct platform_driver hdlcd_platform_driver = {
405 .probe = hdlcd_probe,
406 .remove_new = hdlcd_remove,
407 .shutdown = hdlcd_shutdown,
408 .driver = {
409 .name = "hdlcd",
410 .pm = &hdlcd_pm_ops,
411 .of_match_table = hdlcd_of_match,
412 },
413};
414
415drm_module_platform_driver(hdlcd_platform_driver);
416
417MODULE_AUTHOR("Liviu Dudau");
418MODULE_DESCRIPTION("ARM HDLCD DRM driver");
419MODULE_LICENSE("GPL v2");