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1/*
2 * Copyright (C) 2013-2015 ARM Limited
3 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive
7 * for more details.
8 *
9 * ARM HDLCD Driver
10 */
11
12#include <linux/module.h>
13#include <linux/spinlock.h>
14#include <linux/clk.h>
15#include <linux/component.h>
16#include <linux/console.h>
17#include <linux/dma-mapping.h>
18#include <linux/list.h>
19#include <linux/of_graph.h>
20#include <linux/of_reserved_mem.h>
21#include <linux/platform_device.h>
22#include <linux/pm_runtime.h>
23
24#include <drm/drm_atomic_helper.h>
25#include <drm/drm_crtc.h>
26#include <drm/drm_debugfs.h>
27#include <drm/drm_drv.h>
28#include <drm/drm_fb_cma_helper.h>
29#include <drm/drm_fb_helper.h>
30#include <drm/drm_gem_cma_helper.h>
31#include <drm/drm_gem_framebuffer_helper.h>
32#include <drm/drm_irq.h>
33#include <drm/drm_modeset_helper.h>
34#include <drm/drm_of.h>
35#include <drm/drm_probe_helper.h>
36#include <drm/drm_vblank.h>
37
38#include "hdlcd_drv.h"
39#include "hdlcd_regs.h"
40
41static int hdlcd_load(struct drm_device *drm, unsigned long flags)
42{
43 struct hdlcd_drm_private *hdlcd = drm->dev_private;
44 struct platform_device *pdev = to_platform_device(drm->dev);
45 struct resource *res;
46 u32 version;
47 int ret;
48
49 hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
50 if (IS_ERR(hdlcd->clk))
51 return PTR_ERR(hdlcd->clk);
52
53#ifdef CONFIG_DEBUG_FS
54 atomic_set(&hdlcd->buffer_underrun_count, 0);
55 atomic_set(&hdlcd->bus_error_count, 0);
56 atomic_set(&hdlcd->vsync_count, 0);
57 atomic_set(&hdlcd->dma_end_count, 0);
58#endif
59
60 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
61 hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
62 if (IS_ERR(hdlcd->mmio)) {
63 DRM_ERROR("failed to map control registers area\n");
64 ret = PTR_ERR(hdlcd->mmio);
65 hdlcd->mmio = NULL;
66 return ret;
67 }
68
69 version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
70 if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
71 DRM_ERROR("unknown product id: 0x%x\n", version);
72 return -EINVAL;
73 }
74 DRM_INFO("found ARM HDLCD version r%dp%d\n",
75 (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
76 version & HDLCD_VERSION_MINOR_MASK);
77
78 /* Get the optional framebuffer memory resource */
79 ret = of_reserved_mem_device_init(drm->dev);
80 if (ret && ret != -ENODEV)
81 return ret;
82
83 ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
84 if (ret)
85 goto setup_fail;
86
87 ret = hdlcd_setup_crtc(drm);
88 if (ret < 0) {
89 DRM_ERROR("failed to create crtc\n");
90 goto setup_fail;
91 }
92
93 ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
94 if (ret < 0) {
95 DRM_ERROR("failed to install IRQ handler\n");
96 goto irq_fail;
97 }
98
99 return 0;
100
101irq_fail:
102 drm_crtc_cleanup(&hdlcd->crtc);
103setup_fail:
104 of_reserved_mem_device_release(drm->dev);
105
106 return ret;
107}
108
109static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
110 .fb_create = drm_gem_fb_create,
111 .atomic_check = drm_atomic_helper_check,
112 .atomic_commit = drm_atomic_helper_commit,
113};
114
115static void hdlcd_setup_mode_config(struct drm_device *drm)
116{
117 drm_mode_config_init(drm);
118 drm->mode_config.min_width = 0;
119 drm->mode_config.min_height = 0;
120 drm->mode_config.max_width = HDLCD_MAX_XRES;
121 drm->mode_config.max_height = HDLCD_MAX_YRES;
122 drm->mode_config.funcs = &hdlcd_mode_config_funcs;
123}
124
125static irqreturn_t hdlcd_irq(int irq, void *arg)
126{
127 struct drm_device *drm = arg;
128 struct hdlcd_drm_private *hdlcd = drm->dev_private;
129 unsigned long irq_status;
130
131 irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
132
133#ifdef CONFIG_DEBUG_FS
134 if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
135 atomic_inc(&hdlcd->buffer_underrun_count);
136
137 if (irq_status & HDLCD_INTERRUPT_DMA_END)
138 atomic_inc(&hdlcd->dma_end_count);
139
140 if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
141 atomic_inc(&hdlcd->bus_error_count);
142
143 if (irq_status & HDLCD_INTERRUPT_VSYNC)
144 atomic_inc(&hdlcd->vsync_count);
145
146#endif
147 if (irq_status & HDLCD_INTERRUPT_VSYNC)
148 drm_crtc_handle_vblank(&hdlcd->crtc);
149
150 /* acknowledge interrupt(s) */
151 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
152
153 return IRQ_HANDLED;
154}
155
156static void hdlcd_irq_preinstall(struct drm_device *drm)
157{
158 struct hdlcd_drm_private *hdlcd = drm->dev_private;
159 /* Ensure interrupts are disabled */
160 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
161 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
162}
163
164static int hdlcd_irq_postinstall(struct drm_device *drm)
165{
166#ifdef CONFIG_DEBUG_FS
167 struct hdlcd_drm_private *hdlcd = drm->dev_private;
168 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
169
170 /* enable debug interrupts */
171 irq_mask |= HDLCD_DEBUG_INT_MASK;
172
173 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
174#endif
175 return 0;
176}
177
178static void hdlcd_irq_uninstall(struct drm_device *drm)
179{
180 struct hdlcd_drm_private *hdlcd = drm->dev_private;
181 /* disable all the interrupts that we might have enabled */
182 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
183
184#ifdef CONFIG_DEBUG_FS
185 /* disable debug interrupts */
186 irq_mask &= ~HDLCD_DEBUG_INT_MASK;
187#endif
188
189 /* disable vsync interrupts */
190 irq_mask &= ~HDLCD_INTERRUPT_VSYNC;
191
192 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
193}
194
195#ifdef CONFIG_DEBUG_FS
196static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
197{
198 struct drm_info_node *node = (struct drm_info_node *)m->private;
199 struct drm_device *drm = node->minor->dev;
200 struct hdlcd_drm_private *hdlcd = drm->dev_private;
201
202 seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
203 seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count));
204 seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
205 seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count));
206 return 0;
207}
208
209static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
210{
211 struct drm_info_node *node = (struct drm_info_node *)m->private;
212 struct drm_device *drm = node->minor->dev;
213 struct hdlcd_drm_private *hdlcd = drm->dev_private;
214 unsigned long clkrate = clk_get_rate(hdlcd->clk);
215 unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
216
217 seq_printf(m, "hw : %lu\n", clkrate);
218 seq_printf(m, "mode: %lu\n", mode_clock);
219 return 0;
220}
221
222static struct drm_info_list hdlcd_debugfs_list[] = {
223 { "interrupt_count", hdlcd_show_underrun_count, 0 },
224 { "clocks", hdlcd_show_pxlclock, 0 },
225};
226
227static int hdlcd_debugfs_init(struct drm_minor *minor)
228{
229 return drm_debugfs_create_files(hdlcd_debugfs_list,
230 ARRAY_SIZE(hdlcd_debugfs_list), minor->debugfs_root, minor);
231}
232#endif
233
234DEFINE_DRM_GEM_CMA_FOPS(fops);
235
236static struct drm_driver hdlcd_driver = {
237 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
238 .irq_handler = hdlcd_irq,
239 .irq_preinstall = hdlcd_irq_preinstall,
240 .irq_postinstall = hdlcd_irq_postinstall,
241 .irq_uninstall = hdlcd_irq_uninstall,
242 .gem_free_object_unlocked = drm_gem_cma_free_object,
243 .gem_print_info = drm_gem_cma_print_info,
244 .gem_vm_ops = &drm_gem_cma_vm_ops,
245 .dumb_create = drm_gem_cma_dumb_create,
246 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
247 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
248 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
249 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
250 .gem_prime_vmap = drm_gem_cma_prime_vmap,
251 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
252 .gem_prime_mmap = drm_gem_cma_prime_mmap,
253#ifdef CONFIG_DEBUG_FS
254 .debugfs_init = hdlcd_debugfs_init,
255#endif
256 .fops = &fops,
257 .name = "hdlcd",
258 .desc = "ARM HDLCD Controller DRM",
259 .date = "20151021",
260 .major = 1,
261 .minor = 0,
262};
263
264static int hdlcd_drm_bind(struct device *dev)
265{
266 struct drm_device *drm;
267 struct hdlcd_drm_private *hdlcd;
268 int ret;
269
270 hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL);
271 if (!hdlcd)
272 return -ENOMEM;
273
274 drm = drm_dev_alloc(&hdlcd_driver, dev);
275 if (IS_ERR(drm))
276 return PTR_ERR(drm);
277
278 drm->dev_private = hdlcd;
279 dev_set_drvdata(dev, drm);
280
281 hdlcd_setup_mode_config(drm);
282 ret = hdlcd_load(drm, 0);
283 if (ret)
284 goto err_free;
285
286 /* Set the CRTC's port so that the encoder component can find it */
287 hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
288
289 ret = component_bind_all(dev, drm);
290 if (ret) {
291 DRM_ERROR("Failed to bind all components\n");
292 goto err_unload;
293 }
294
295 ret = pm_runtime_set_active(dev);
296 if (ret)
297 goto err_pm_active;
298
299 pm_runtime_enable(dev);
300
301 ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
302 if (ret < 0) {
303 DRM_ERROR("failed to initialise vblank\n");
304 goto err_vblank;
305 }
306
307 drm_mode_config_reset(drm);
308 drm_kms_helper_poll_init(drm);
309
310 ret = drm_dev_register(drm, 0);
311 if (ret)
312 goto err_register;
313
314 drm_fbdev_generic_setup(drm, 32);
315
316 return 0;
317
318err_register:
319 drm_kms_helper_poll_fini(drm);
320err_vblank:
321 pm_runtime_disable(drm->dev);
322err_pm_active:
323 drm_atomic_helper_shutdown(drm);
324 component_unbind_all(dev, drm);
325err_unload:
326 of_node_put(hdlcd->crtc.port);
327 hdlcd->crtc.port = NULL;
328 drm_irq_uninstall(drm);
329 of_reserved_mem_device_release(drm->dev);
330err_free:
331 drm_mode_config_cleanup(drm);
332 dev_set_drvdata(dev, NULL);
333 drm_dev_put(drm);
334
335 return ret;
336}
337
338static void hdlcd_drm_unbind(struct device *dev)
339{
340 struct drm_device *drm = dev_get_drvdata(dev);
341 struct hdlcd_drm_private *hdlcd = drm->dev_private;
342
343 drm_dev_unregister(drm);
344 drm_kms_helper_poll_fini(drm);
345 component_unbind_all(dev, drm);
346 of_node_put(hdlcd->crtc.port);
347 hdlcd->crtc.port = NULL;
348 pm_runtime_get_sync(dev);
349 drm_crtc_vblank_off(&hdlcd->crtc);
350 drm_irq_uninstall(drm);
351 drm_atomic_helper_shutdown(drm);
352 pm_runtime_put(dev);
353 if (pm_runtime_enabled(dev))
354 pm_runtime_disable(dev);
355 of_reserved_mem_device_release(dev);
356 drm_mode_config_cleanup(drm);
357 drm->dev_private = NULL;
358 dev_set_drvdata(dev, NULL);
359 drm_dev_put(drm);
360}
361
362static const struct component_master_ops hdlcd_master_ops = {
363 .bind = hdlcd_drm_bind,
364 .unbind = hdlcd_drm_unbind,
365};
366
367static int compare_dev(struct device *dev, void *data)
368{
369 return dev->of_node == data;
370}
371
372static int hdlcd_probe(struct platform_device *pdev)
373{
374 struct device_node *port;
375 struct component_match *match = NULL;
376
377 /* there is only one output port inside each device, find it */
378 port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
379 if (!port)
380 return -ENODEV;
381
382 drm_of_component_match_add(&pdev->dev, &match, compare_dev, port);
383 of_node_put(port);
384
385 return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
386 match);
387}
388
389static int hdlcd_remove(struct platform_device *pdev)
390{
391 component_master_del(&pdev->dev, &hdlcd_master_ops);
392 return 0;
393}
394
395static const struct of_device_id hdlcd_of_match[] = {
396 { .compatible = "arm,hdlcd" },
397 {},
398};
399MODULE_DEVICE_TABLE(of, hdlcd_of_match);
400
401static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
402{
403 struct drm_device *drm = dev_get_drvdata(dev);
404
405 return drm_mode_config_helper_suspend(drm);
406}
407
408static int __maybe_unused hdlcd_pm_resume(struct device *dev)
409{
410 struct drm_device *drm = dev_get_drvdata(dev);
411
412 drm_mode_config_helper_resume(drm);
413
414 return 0;
415}
416
417static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
418
419static struct platform_driver hdlcd_platform_driver = {
420 .probe = hdlcd_probe,
421 .remove = hdlcd_remove,
422 .driver = {
423 .name = "hdlcd",
424 .pm = &hdlcd_pm_ops,
425 .of_match_table = hdlcd_of_match,
426 },
427};
428
429module_platform_driver(hdlcd_platform_driver);
430
431MODULE_AUTHOR("Liviu Dudau");
432MODULE_DESCRIPTION("ARM HDLCD DRM driver");
433MODULE_LICENSE("GPL v2");
1/*
2 * Copyright (C) 2013-2015 ARM Limited
3 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive
7 * for more details.
8 *
9 * ARM HDLCD Driver
10 */
11
12#include <linux/module.h>
13#include <linux/spinlock.h>
14#include <linux/clk.h>
15#include <linux/component.h>
16#include <linux/console.h>
17#include <linux/list.h>
18#include <linux/of_graph.h>
19#include <linux/of_reserved_mem.h>
20#include <linux/pm_runtime.h>
21
22#include <drm/drmP.h>
23#include <drm/drm_atomic_helper.h>
24#include <drm/drm_crtc.h>
25#include <drm/drm_crtc_helper.h>
26#include <drm/drm_fb_helper.h>
27#include <drm/drm_fb_cma_helper.h>
28#include <drm/drm_gem_cma_helper.h>
29#include <drm/drm_gem_framebuffer_helper.h>
30#include <drm/drm_of.h>
31
32#include "hdlcd_drv.h"
33#include "hdlcd_regs.h"
34
35static int hdlcd_load(struct drm_device *drm, unsigned long flags)
36{
37 struct hdlcd_drm_private *hdlcd = drm->dev_private;
38 struct platform_device *pdev = to_platform_device(drm->dev);
39 struct resource *res;
40 u32 version;
41 int ret;
42
43 hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
44 if (IS_ERR(hdlcd->clk))
45 return PTR_ERR(hdlcd->clk);
46
47#ifdef CONFIG_DEBUG_FS
48 atomic_set(&hdlcd->buffer_underrun_count, 0);
49 atomic_set(&hdlcd->bus_error_count, 0);
50 atomic_set(&hdlcd->vsync_count, 0);
51 atomic_set(&hdlcd->dma_end_count, 0);
52#endif
53
54 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
55 hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
56 if (IS_ERR(hdlcd->mmio)) {
57 DRM_ERROR("failed to map control registers area\n");
58 ret = PTR_ERR(hdlcd->mmio);
59 hdlcd->mmio = NULL;
60 return ret;
61 }
62
63 version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
64 if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
65 DRM_ERROR("unknown product id: 0x%x\n", version);
66 return -EINVAL;
67 }
68 DRM_INFO("found ARM HDLCD version r%dp%d\n",
69 (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
70 version & HDLCD_VERSION_MINOR_MASK);
71
72 /* Get the optional framebuffer memory resource */
73 ret = of_reserved_mem_device_init(drm->dev);
74 if (ret && ret != -ENODEV)
75 return ret;
76
77 ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
78 if (ret)
79 goto setup_fail;
80
81 ret = hdlcd_setup_crtc(drm);
82 if (ret < 0) {
83 DRM_ERROR("failed to create crtc\n");
84 goto setup_fail;
85 }
86
87 ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
88 if (ret < 0) {
89 DRM_ERROR("failed to install IRQ handler\n");
90 goto irq_fail;
91 }
92
93 return 0;
94
95irq_fail:
96 drm_crtc_cleanup(&hdlcd->crtc);
97setup_fail:
98 of_reserved_mem_device_release(drm->dev);
99
100 return ret;
101}
102
103static void hdlcd_fb_output_poll_changed(struct drm_device *drm)
104{
105 struct hdlcd_drm_private *hdlcd = drm->dev_private;
106
107 drm_fbdev_cma_hotplug_event(hdlcd->fbdev);
108}
109
110static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
111 .fb_create = drm_gem_fb_create,
112 .output_poll_changed = hdlcd_fb_output_poll_changed,
113 .atomic_check = drm_atomic_helper_check,
114 .atomic_commit = drm_atomic_helper_commit,
115};
116
117static void hdlcd_setup_mode_config(struct drm_device *drm)
118{
119 drm_mode_config_init(drm);
120 drm->mode_config.min_width = 0;
121 drm->mode_config.min_height = 0;
122 drm->mode_config.max_width = HDLCD_MAX_XRES;
123 drm->mode_config.max_height = HDLCD_MAX_YRES;
124 drm->mode_config.funcs = &hdlcd_mode_config_funcs;
125}
126
127static void hdlcd_lastclose(struct drm_device *drm)
128{
129 struct hdlcd_drm_private *hdlcd = drm->dev_private;
130
131 drm_fbdev_cma_restore_mode(hdlcd->fbdev);
132}
133
134static irqreturn_t hdlcd_irq(int irq, void *arg)
135{
136 struct drm_device *drm = arg;
137 struct hdlcd_drm_private *hdlcd = drm->dev_private;
138 unsigned long irq_status;
139
140 irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
141
142#ifdef CONFIG_DEBUG_FS
143 if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
144 atomic_inc(&hdlcd->buffer_underrun_count);
145
146 if (irq_status & HDLCD_INTERRUPT_DMA_END)
147 atomic_inc(&hdlcd->dma_end_count);
148
149 if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
150 atomic_inc(&hdlcd->bus_error_count);
151
152 if (irq_status & HDLCD_INTERRUPT_VSYNC)
153 atomic_inc(&hdlcd->vsync_count);
154
155#endif
156 if (irq_status & HDLCD_INTERRUPT_VSYNC)
157 drm_crtc_handle_vblank(&hdlcd->crtc);
158
159 /* acknowledge interrupt(s) */
160 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
161
162 return IRQ_HANDLED;
163}
164
165static void hdlcd_irq_preinstall(struct drm_device *drm)
166{
167 struct hdlcd_drm_private *hdlcd = drm->dev_private;
168 /* Ensure interrupts are disabled */
169 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
170 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
171}
172
173static int hdlcd_irq_postinstall(struct drm_device *drm)
174{
175#ifdef CONFIG_DEBUG_FS
176 struct hdlcd_drm_private *hdlcd = drm->dev_private;
177 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
178
179 /* enable debug interrupts */
180 irq_mask |= HDLCD_DEBUG_INT_MASK;
181
182 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
183#endif
184 return 0;
185}
186
187static void hdlcd_irq_uninstall(struct drm_device *drm)
188{
189 struct hdlcd_drm_private *hdlcd = drm->dev_private;
190 /* disable all the interrupts that we might have enabled */
191 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
192
193#ifdef CONFIG_DEBUG_FS
194 /* disable debug interrupts */
195 irq_mask &= ~HDLCD_DEBUG_INT_MASK;
196#endif
197
198 /* disable vsync interrupts */
199 irq_mask &= ~HDLCD_INTERRUPT_VSYNC;
200
201 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
202}
203
204#ifdef CONFIG_DEBUG_FS
205static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
206{
207 struct drm_info_node *node = (struct drm_info_node *)m->private;
208 struct drm_device *drm = node->minor->dev;
209 struct hdlcd_drm_private *hdlcd = drm->dev_private;
210
211 seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
212 seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count));
213 seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
214 seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count));
215 return 0;
216}
217
218static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
219{
220 struct drm_info_node *node = (struct drm_info_node *)m->private;
221 struct drm_device *drm = node->minor->dev;
222 struct hdlcd_drm_private *hdlcd = drm->dev_private;
223 unsigned long clkrate = clk_get_rate(hdlcd->clk);
224 unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
225
226 seq_printf(m, "hw : %lu\n", clkrate);
227 seq_printf(m, "mode: %lu\n", mode_clock);
228 return 0;
229}
230
231static struct drm_info_list hdlcd_debugfs_list[] = {
232 { "interrupt_count", hdlcd_show_underrun_count, 0 },
233 { "clocks", hdlcd_show_pxlclock, 0 },
234};
235
236static int hdlcd_debugfs_init(struct drm_minor *minor)
237{
238 return drm_debugfs_create_files(hdlcd_debugfs_list,
239 ARRAY_SIZE(hdlcd_debugfs_list), minor->debugfs_root, minor);
240}
241#endif
242
243DEFINE_DRM_GEM_CMA_FOPS(fops);
244
245static struct drm_driver hdlcd_driver = {
246 .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
247 DRIVER_MODESET | DRIVER_PRIME |
248 DRIVER_ATOMIC,
249 .lastclose = hdlcd_lastclose,
250 .irq_handler = hdlcd_irq,
251 .irq_preinstall = hdlcd_irq_preinstall,
252 .irq_postinstall = hdlcd_irq_postinstall,
253 .irq_uninstall = hdlcd_irq_uninstall,
254 .gem_free_object_unlocked = drm_gem_cma_free_object,
255 .gem_print_info = drm_gem_cma_print_info,
256 .gem_vm_ops = &drm_gem_cma_vm_ops,
257 .dumb_create = drm_gem_cma_dumb_create,
258 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
259 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
260 .gem_prime_export = drm_gem_prime_export,
261 .gem_prime_import = drm_gem_prime_import,
262 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
263 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
264 .gem_prime_vmap = drm_gem_cma_prime_vmap,
265 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
266 .gem_prime_mmap = drm_gem_cma_prime_mmap,
267#ifdef CONFIG_DEBUG_FS
268 .debugfs_init = hdlcd_debugfs_init,
269#endif
270 .fops = &fops,
271 .name = "hdlcd",
272 .desc = "ARM HDLCD Controller DRM",
273 .date = "20151021",
274 .major = 1,
275 .minor = 0,
276};
277
278static int hdlcd_drm_bind(struct device *dev)
279{
280 struct drm_device *drm;
281 struct hdlcd_drm_private *hdlcd;
282 int ret;
283
284 hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL);
285 if (!hdlcd)
286 return -ENOMEM;
287
288 drm = drm_dev_alloc(&hdlcd_driver, dev);
289 if (IS_ERR(drm))
290 return PTR_ERR(drm);
291
292 drm->dev_private = hdlcd;
293 dev_set_drvdata(dev, drm);
294
295 hdlcd_setup_mode_config(drm);
296 ret = hdlcd_load(drm, 0);
297 if (ret)
298 goto err_free;
299
300 /* Set the CRTC's port so that the encoder component can find it */
301 hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
302
303 ret = component_bind_all(dev, drm);
304 if (ret) {
305 DRM_ERROR("Failed to bind all components\n");
306 goto err_unload;
307 }
308
309 ret = pm_runtime_set_active(dev);
310 if (ret)
311 goto err_pm_active;
312
313 pm_runtime_enable(dev);
314
315 ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
316 if (ret < 0) {
317 DRM_ERROR("failed to initialise vblank\n");
318 goto err_vblank;
319 }
320
321 drm_mode_config_reset(drm);
322 drm_kms_helper_poll_init(drm);
323
324 hdlcd->fbdev = drm_fbdev_cma_init(drm, 32,
325 drm->mode_config.num_connector);
326
327 if (IS_ERR(hdlcd->fbdev)) {
328 ret = PTR_ERR(hdlcd->fbdev);
329 hdlcd->fbdev = NULL;
330 goto err_fbdev;
331 }
332
333 ret = drm_dev_register(drm, 0);
334 if (ret)
335 goto err_register;
336
337 return 0;
338
339err_register:
340 if (hdlcd->fbdev) {
341 drm_fbdev_cma_fini(hdlcd->fbdev);
342 hdlcd->fbdev = NULL;
343 }
344err_fbdev:
345 drm_kms_helper_poll_fini(drm);
346err_vblank:
347 pm_runtime_disable(drm->dev);
348err_pm_active:
349 component_unbind_all(dev, drm);
350err_unload:
351 of_node_put(hdlcd->crtc.port);
352 hdlcd->crtc.port = NULL;
353 drm_irq_uninstall(drm);
354 of_reserved_mem_device_release(drm->dev);
355err_free:
356 drm_mode_config_cleanup(drm);
357 dev_set_drvdata(dev, NULL);
358 drm_dev_put(drm);
359
360 return ret;
361}
362
363static void hdlcd_drm_unbind(struct device *dev)
364{
365 struct drm_device *drm = dev_get_drvdata(dev);
366 struct hdlcd_drm_private *hdlcd = drm->dev_private;
367
368 drm_dev_unregister(drm);
369 if (hdlcd->fbdev) {
370 drm_fbdev_cma_fini(hdlcd->fbdev);
371 hdlcd->fbdev = NULL;
372 }
373 drm_kms_helper_poll_fini(drm);
374 component_unbind_all(dev, drm);
375 of_node_put(hdlcd->crtc.port);
376 hdlcd->crtc.port = NULL;
377 pm_runtime_get_sync(drm->dev);
378 drm_irq_uninstall(drm);
379 pm_runtime_put_sync(drm->dev);
380 pm_runtime_disable(drm->dev);
381 of_reserved_mem_device_release(drm->dev);
382 drm_mode_config_cleanup(drm);
383 drm_dev_put(drm);
384 drm->dev_private = NULL;
385 dev_set_drvdata(dev, NULL);
386}
387
388static const struct component_master_ops hdlcd_master_ops = {
389 .bind = hdlcd_drm_bind,
390 .unbind = hdlcd_drm_unbind,
391};
392
393static int compare_dev(struct device *dev, void *data)
394{
395 return dev->of_node == data;
396}
397
398static int hdlcd_probe(struct platform_device *pdev)
399{
400 struct device_node *port;
401 struct component_match *match = NULL;
402
403 /* there is only one output port inside each device, find it */
404 port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
405 if (!port)
406 return -ENODEV;
407
408 drm_of_component_match_add(&pdev->dev, &match, compare_dev, port);
409 of_node_put(port);
410
411 return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
412 match);
413}
414
415static int hdlcd_remove(struct platform_device *pdev)
416{
417 component_master_del(&pdev->dev, &hdlcd_master_ops);
418 return 0;
419}
420
421static const struct of_device_id hdlcd_of_match[] = {
422 { .compatible = "arm,hdlcd" },
423 {},
424};
425MODULE_DEVICE_TABLE(of, hdlcd_of_match);
426
427static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
428{
429 struct drm_device *drm = dev_get_drvdata(dev);
430 struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL;
431
432 if (!hdlcd)
433 return 0;
434
435 drm_kms_helper_poll_disable(drm);
436 drm_fbdev_cma_set_suspend_unlocked(hdlcd->fbdev, 1);
437
438 hdlcd->state = drm_atomic_helper_suspend(drm);
439 if (IS_ERR(hdlcd->state)) {
440 drm_fbdev_cma_set_suspend_unlocked(hdlcd->fbdev, 0);
441 drm_kms_helper_poll_enable(drm);
442 return PTR_ERR(hdlcd->state);
443 }
444
445 return 0;
446}
447
448static int __maybe_unused hdlcd_pm_resume(struct device *dev)
449{
450 struct drm_device *drm = dev_get_drvdata(dev);
451 struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL;
452
453 if (!hdlcd)
454 return 0;
455
456 drm_atomic_helper_resume(drm, hdlcd->state);
457 drm_fbdev_cma_set_suspend_unlocked(hdlcd->fbdev, 0);
458 drm_kms_helper_poll_enable(drm);
459
460 return 0;
461}
462
463static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
464
465static struct platform_driver hdlcd_platform_driver = {
466 .probe = hdlcd_probe,
467 .remove = hdlcd_remove,
468 .driver = {
469 .name = "hdlcd",
470 .pm = &hdlcd_pm_ops,
471 .of_match_table = hdlcd_of_match,
472 },
473};
474
475module_platform_driver(hdlcd_platform_driver);
476
477MODULE_AUTHOR("Liviu Dudau");
478MODULE_DESCRIPTION("ARM HDLCD DRM driver");
479MODULE_LICENSE("GPL v2");