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1// SPDX-License-Identifier: GPL-2.0-only
2#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3
4#include <linux/kernel.h>
5#include <linux/sched.h>
6#include <linux/sched/clock.h>
7#include <linux/init.h>
8#include <linux/export.h>
9#include <linux/timer.h>
10#include <linux/acpi_pmtmr.h>
11#include <linux/cpufreq.h>
12#include <linux/delay.h>
13#include <linux/clocksource.h>
14#include <linux/percpu.h>
15#include <linux/timex.h>
16#include <linux/static_key.h>
17
18#include <asm/hpet.h>
19#include <asm/timer.h>
20#include <asm/vgtod.h>
21#include <asm/time.h>
22#include <asm/delay.h>
23#include <asm/hypervisor.h>
24#include <asm/nmi.h>
25#include <asm/x86_init.h>
26#include <asm/geode.h>
27#include <asm/apic.h>
28#include <asm/intel-family.h>
29#include <asm/i8259.h>
30#include <asm/uv/uv.h>
31
32unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
33EXPORT_SYMBOL(cpu_khz);
34
35unsigned int __read_mostly tsc_khz;
36EXPORT_SYMBOL(tsc_khz);
37
38#define KHZ 1000
39
40/*
41 * TSC can be unstable due to cpufreq or due to unsynced TSCs
42 */
43static int __read_mostly tsc_unstable;
44
45static DEFINE_STATIC_KEY_FALSE(__use_tsc);
46
47int tsc_clocksource_reliable;
48
49static u32 art_to_tsc_numerator;
50static u32 art_to_tsc_denominator;
51static u64 art_to_tsc_offset;
52struct clocksource *art_related_clocksource;
53
54struct cyc2ns {
55 struct cyc2ns_data data[2]; /* 0 + 2*16 = 32 */
56 seqcount_t seq; /* 32 + 4 = 36 */
57
58}; /* fits one cacheline */
59
60static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns);
61
62__always_inline void cyc2ns_read_begin(struct cyc2ns_data *data)
63{
64 int seq, idx;
65
66 preempt_disable_notrace();
67
68 do {
69 seq = this_cpu_read(cyc2ns.seq.sequence);
70 idx = seq & 1;
71
72 data->cyc2ns_offset = this_cpu_read(cyc2ns.data[idx].cyc2ns_offset);
73 data->cyc2ns_mul = this_cpu_read(cyc2ns.data[idx].cyc2ns_mul);
74 data->cyc2ns_shift = this_cpu_read(cyc2ns.data[idx].cyc2ns_shift);
75
76 } while (unlikely(seq != this_cpu_read(cyc2ns.seq.sequence)));
77}
78
79__always_inline void cyc2ns_read_end(void)
80{
81 preempt_enable_notrace();
82}
83
84/*
85 * Accelerators for sched_clock()
86 * convert from cycles(64bits) => nanoseconds (64bits)
87 * basic equation:
88 * ns = cycles / (freq / ns_per_sec)
89 * ns = cycles * (ns_per_sec / freq)
90 * ns = cycles * (10^9 / (cpu_khz * 10^3))
91 * ns = cycles * (10^6 / cpu_khz)
92 *
93 * Then we use scaling math (suggested by george@mvista.com) to get:
94 * ns = cycles * (10^6 * SC / cpu_khz) / SC
95 * ns = cycles * cyc2ns_scale / SC
96 *
97 * And since SC is a constant power of two, we can convert the div
98 * into a shift. The larger SC is, the more accurate the conversion, but
99 * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication
100 * (64-bit result) can be used.
101 *
102 * We can use khz divisor instead of mhz to keep a better precision.
103 * (mathieu.desnoyers@polymtl.ca)
104 *
105 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
106 */
107
108static __always_inline unsigned long long cycles_2_ns(unsigned long long cyc)
109{
110 struct cyc2ns_data data;
111 unsigned long long ns;
112
113 cyc2ns_read_begin(&data);
114
115 ns = data.cyc2ns_offset;
116 ns += mul_u64_u32_shr(cyc, data.cyc2ns_mul, data.cyc2ns_shift);
117
118 cyc2ns_read_end();
119
120 return ns;
121}
122
123static void __set_cyc2ns_scale(unsigned long khz, int cpu, unsigned long long tsc_now)
124{
125 unsigned long long ns_now;
126 struct cyc2ns_data data;
127 struct cyc2ns *c2n;
128
129 ns_now = cycles_2_ns(tsc_now);
130
131 /*
132 * Compute a new multiplier as per the above comment and ensure our
133 * time function is continuous; see the comment near struct
134 * cyc2ns_data.
135 */
136 clocks_calc_mult_shift(&data.cyc2ns_mul, &data.cyc2ns_shift, khz,
137 NSEC_PER_MSEC, 0);
138
139 /*
140 * cyc2ns_shift is exported via arch_perf_update_userpage() where it is
141 * not expected to be greater than 31 due to the original published
142 * conversion algorithm shifting a 32-bit value (now specifies a 64-bit
143 * value) - refer perf_event_mmap_page documentation in perf_event.h.
144 */
145 if (data.cyc2ns_shift == 32) {
146 data.cyc2ns_shift = 31;
147 data.cyc2ns_mul >>= 1;
148 }
149
150 data.cyc2ns_offset = ns_now -
151 mul_u64_u32_shr(tsc_now, data.cyc2ns_mul, data.cyc2ns_shift);
152
153 c2n = per_cpu_ptr(&cyc2ns, cpu);
154
155 raw_write_seqcount_latch(&c2n->seq);
156 c2n->data[0] = data;
157 raw_write_seqcount_latch(&c2n->seq);
158 c2n->data[1] = data;
159}
160
161static void set_cyc2ns_scale(unsigned long khz, int cpu, unsigned long long tsc_now)
162{
163 unsigned long flags;
164
165 local_irq_save(flags);
166 sched_clock_idle_sleep_event();
167
168 if (khz)
169 __set_cyc2ns_scale(khz, cpu, tsc_now);
170
171 sched_clock_idle_wakeup_event();
172 local_irq_restore(flags);
173}
174
175/*
176 * Initialize cyc2ns for boot cpu
177 */
178static void __init cyc2ns_init_boot_cpu(void)
179{
180 struct cyc2ns *c2n = this_cpu_ptr(&cyc2ns);
181
182 seqcount_init(&c2n->seq);
183 __set_cyc2ns_scale(tsc_khz, smp_processor_id(), rdtsc());
184}
185
186/*
187 * Secondary CPUs do not run through tsc_init(), so set up
188 * all the scale factors for all CPUs, assuming the same
189 * speed as the bootup CPU.
190 */
191static void __init cyc2ns_init_secondary_cpus(void)
192{
193 unsigned int cpu, this_cpu = smp_processor_id();
194 struct cyc2ns *c2n = this_cpu_ptr(&cyc2ns);
195 struct cyc2ns_data *data = c2n->data;
196
197 for_each_possible_cpu(cpu) {
198 if (cpu != this_cpu) {
199 seqcount_init(&c2n->seq);
200 c2n = per_cpu_ptr(&cyc2ns, cpu);
201 c2n->data[0] = data[0];
202 c2n->data[1] = data[1];
203 }
204 }
205}
206
207/*
208 * Scheduler clock - returns current time in nanosec units.
209 */
210u64 native_sched_clock(void)
211{
212 if (static_branch_likely(&__use_tsc)) {
213 u64 tsc_now = rdtsc();
214
215 /* return the value in ns */
216 return cycles_2_ns(tsc_now);
217 }
218
219 /*
220 * Fall back to jiffies if there's no TSC available:
221 * ( But note that we still use it if the TSC is marked
222 * unstable. We do this because unlike Time Of Day,
223 * the scheduler clock tolerates small errors and it's
224 * very important for it to be as fast as the platform
225 * can achieve it. )
226 */
227
228 /* No locking but a rare wrong value is not a big deal: */
229 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
230}
231
232/*
233 * Generate a sched_clock if you already have a TSC value.
234 */
235u64 native_sched_clock_from_tsc(u64 tsc)
236{
237 return cycles_2_ns(tsc);
238}
239
240/* We need to define a real function for sched_clock, to override the
241 weak default version */
242#ifdef CONFIG_PARAVIRT
243unsigned long long sched_clock(void)
244{
245 return paravirt_sched_clock();
246}
247
248bool using_native_sched_clock(void)
249{
250 return pv_ops.time.sched_clock == native_sched_clock;
251}
252#else
253unsigned long long
254sched_clock(void) __attribute__((alias("native_sched_clock")));
255
256bool using_native_sched_clock(void) { return true; }
257#endif
258
259int check_tsc_unstable(void)
260{
261 return tsc_unstable;
262}
263EXPORT_SYMBOL_GPL(check_tsc_unstable);
264
265#ifdef CONFIG_X86_TSC
266int __init notsc_setup(char *str)
267{
268 mark_tsc_unstable("boot parameter notsc");
269 return 1;
270}
271#else
272/*
273 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
274 * in cpu/common.c
275 */
276int __init notsc_setup(char *str)
277{
278 setup_clear_cpu_cap(X86_FEATURE_TSC);
279 return 1;
280}
281#endif
282
283__setup("notsc", notsc_setup);
284
285static int no_sched_irq_time;
286static int no_tsc_watchdog;
287
288static int __init tsc_setup(char *str)
289{
290 if (!strcmp(str, "reliable"))
291 tsc_clocksource_reliable = 1;
292 if (!strncmp(str, "noirqtime", 9))
293 no_sched_irq_time = 1;
294 if (!strcmp(str, "unstable"))
295 mark_tsc_unstable("boot parameter");
296 if (!strcmp(str, "nowatchdog"))
297 no_tsc_watchdog = 1;
298 return 1;
299}
300
301__setup("tsc=", tsc_setup);
302
303#define MAX_RETRIES 5
304#define TSC_DEFAULT_THRESHOLD 0x20000
305
306/*
307 * Read TSC and the reference counters. Take care of any disturbances
308 */
309static u64 tsc_read_refs(u64 *p, int hpet)
310{
311 u64 t1, t2;
312 u64 thresh = tsc_khz ? tsc_khz >> 5 : TSC_DEFAULT_THRESHOLD;
313 int i;
314
315 for (i = 0; i < MAX_RETRIES; i++) {
316 t1 = get_cycles();
317 if (hpet)
318 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
319 else
320 *p = acpi_pm_read_early();
321 t2 = get_cycles();
322 if ((t2 - t1) < thresh)
323 return t2;
324 }
325 return ULLONG_MAX;
326}
327
328/*
329 * Calculate the TSC frequency from HPET reference
330 */
331static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
332{
333 u64 tmp;
334
335 if (hpet2 < hpet1)
336 hpet2 += 0x100000000ULL;
337 hpet2 -= hpet1;
338 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
339 do_div(tmp, 1000000);
340 deltatsc = div64_u64(deltatsc, tmp);
341
342 return (unsigned long) deltatsc;
343}
344
345/*
346 * Calculate the TSC frequency from PMTimer reference
347 */
348static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
349{
350 u64 tmp;
351
352 if (!pm1 && !pm2)
353 return ULONG_MAX;
354
355 if (pm2 < pm1)
356 pm2 += (u64)ACPI_PM_OVRRUN;
357 pm2 -= pm1;
358 tmp = pm2 * 1000000000LL;
359 do_div(tmp, PMTMR_TICKS_PER_SEC);
360 do_div(deltatsc, tmp);
361
362 return (unsigned long) deltatsc;
363}
364
365#define CAL_MS 10
366#define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
367#define CAL_PIT_LOOPS 1000
368
369#define CAL2_MS 50
370#define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
371#define CAL2_PIT_LOOPS 5000
372
373
374/*
375 * Try to calibrate the TSC against the Programmable
376 * Interrupt Timer and return the frequency of the TSC
377 * in kHz.
378 *
379 * Return ULONG_MAX on failure to calibrate.
380 */
381static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
382{
383 u64 tsc, t1, t2, delta;
384 unsigned long tscmin, tscmax;
385 int pitcnt;
386
387 if (!has_legacy_pic()) {
388 /*
389 * Relies on tsc_early_delay_calibrate() to have given us semi
390 * usable udelay(), wait for the same 50ms we would have with
391 * the PIT loop below.
392 */
393 udelay(10 * USEC_PER_MSEC);
394 udelay(10 * USEC_PER_MSEC);
395 udelay(10 * USEC_PER_MSEC);
396 udelay(10 * USEC_PER_MSEC);
397 udelay(10 * USEC_PER_MSEC);
398 return ULONG_MAX;
399 }
400
401 /* Set the Gate high, disable speaker */
402 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
403
404 /*
405 * Setup CTC channel 2* for mode 0, (interrupt on terminal
406 * count mode), binary count. Set the latch register to 50ms
407 * (LSB then MSB) to begin countdown.
408 */
409 outb(0xb0, 0x43);
410 outb(latch & 0xff, 0x42);
411 outb(latch >> 8, 0x42);
412
413 tsc = t1 = t2 = get_cycles();
414
415 pitcnt = 0;
416 tscmax = 0;
417 tscmin = ULONG_MAX;
418 while ((inb(0x61) & 0x20) == 0) {
419 t2 = get_cycles();
420 delta = t2 - tsc;
421 tsc = t2;
422 if ((unsigned long) delta < tscmin)
423 tscmin = (unsigned int) delta;
424 if ((unsigned long) delta > tscmax)
425 tscmax = (unsigned int) delta;
426 pitcnt++;
427 }
428
429 /*
430 * Sanity checks:
431 *
432 * If we were not able to read the PIT more than loopmin
433 * times, then we have been hit by a massive SMI
434 *
435 * If the maximum is 10 times larger than the minimum,
436 * then we got hit by an SMI as well.
437 */
438 if (pitcnt < loopmin || tscmax > 10 * tscmin)
439 return ULONG_MAX;
440
441 /* Calculate the PIT value */
442 delta = t2 - t1;
443 do_div(delta, ms);
444 return delta;
445}
446
447/*
448 * This reads the current MSB of the PIT counter, and
449 * checks if we are running on sufficiently fast and
450 * non-virtualized hardware.
451 *
452 * Our expectations are:
453 *
454 * - the PIT is running at roughly 1.19MHz
455 *
456 * - each IO is going to take about 1us on real hardware,
457 * but we allow it to be much faster (by a factor of 10) or
458 * _slightly_ slower (ie we allow up to a 2us read+counter
459 * update - anything else implies a unacceptably slow CPU
460 * or PIT for the fast calibration to work.
461 *
462 * - with 256 PIT ticks to read the value, we have 214us to
463 * see the same MSB (and overhead like doing a single TSC
464 * read per MSB value etc).
465 *
466 * - We're doing 2 reads per loop (LSB, MSB), and we expect
467 * them each to take about a microsecond on real hardware.
468 * So we expect a count value of around 100. But we'll be
469 * generous, and accept anything over 50.
470 *
471 * - if the PIT is stuck, and we see *many* more reads, we
472 * return early (and the next caller of pit_expect_msb()
473 * then consider it a failure when they don't see the
474 * next expected value).
475 *
476 * These expectations mean that we know that we have seen the
477 * transition from one expected value to another with a fairly
478 * high accuracy, and we didn't miss any events. We can thus
479 * use the TSC value at the transitions to calculate a pretty
480 * good value for the TSC frequencty.
481 */
482static inline int pit_verify_msb(unsigned char val)
483{
484 /* Ignore LSB */
485 inb(0x42);
486 return inb(0x42) == val;
487}
488
489static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
490{
491 int count;
492 u64 tsc = 0, prev_tsc = 0;
493
494 for (count = 0; count < 50000; count++) {
495 if (!pit_verify_msb(val))
496 break;
497 prev_tsc = tsc;
498 tsc = get_cycles();
499 }
500 *deltap = get_cycles() - prev_tsc;
501 *tscp = tsc;
502
503 /*
504 * We require _some_ success, but the quality control
505 * will be based on the error terms on the TSC values.
506 */
507 return count > 5;
508}
509
510/*
511 * How many MSB values do we want to see? We aim for
512 * a maximum error rate of 500ppm (in practice the
513 * real error is much smaller), but refuse to spend
514 * more than 50ms on it.
515 */
516#define MAX_QUICK_PIT_MS 50
517#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
518
519static unsigned long quick_pit_calibrate(void)
520{
521 int i;
522 u64 tsc, delta;
523 unsigned long d1, d2;
524
525 if (!has_legacy_pic())
526 return 0;
527
528 /* Set the Gate high, disable speaker */
529 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
530
531 /*
532 * Counter 2, mode 0 (one-shot), binary count
533 *
534 * NOTE! Mode 2 decrements by two (and then the
535 * output is flipped each time, giving the same
536 * final output frequency as a decrement-by-one),
537 * so mode 0 is much better when looking at the
538 * individual counts.
539 */
540 outb(0xb0, 0x43);
541
542 /* Start at 0xffff */
543 outb(0xff, 0x42);
544 outb(0xff, 0x42);
545
546 /*
547 * The PIT starts counting at the next edge, so we
548 * need to delay for a microsecond. The easiest way
549 * to do that is to just read back the 16-bit counter
550 * once from the PIT.
551 */
552 pit_verify_msb(0);
553
554 if (pit_expect_msb(0xff, &tsc, &d1)) {
555 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
556 if (!pit_expect_msb(0xff-i, &delta, &d2))
557 break;
558
559 delta -= tsc;
560
561 /*
562 * Extrapolate the error and fail fast if the error will
563 * never be below 500 ppm.
564 */
565 if (i == 1 &&
566 d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11)
567 return 0;
568
569 /*
570 * Iterate until the error is less than 500 ppm
571 */
572 if (d1+d2 >= delta >> 11)
573 continue;
574
575 /*
576 * Check the PIT one more time to verify that
577 * all TSC reads were stable wrt the PIT.
578 *
579 * This also guarantees serialization of the
580 * last cycle read ('d2') in pit_expect_msb.
581 */
582 if (!pit_verify_msb(0xfe - i))
583 break;
584 goto success;
585 }
586 }
587 pr_info("Fast TSC calibration failed\n");
588 return 0;
589
590success:
591 /*
592 * Ok, if we get here, then we've seen the
593 * MSB of the PIT decrement 'i' times, and the
594 * error has shrunk to less than 500 ppm.
595 *
596 * As a result, we can depend on there not being
597 * any odd delays anywhere, and the TSC reads are
598 * reliable (within the error).
599 *
600 * kHz = ticks / time-in-seconds / 1000;
601 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
602 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
603 */
604 delta *= PIT_TICK_RATE;
605 do_div(delta, i*256*1000);
606 pr_info("Fast TSC calibration using PIT\n");
607 return delta;
608}
609
610/**
611 * native_calibrate_tsc
612 * Determine TSC frequency via CPUID, else return 0.
613 */
614unsigned long native_calibrate_tsc(void)
615{
616 unsigned int eax_denominator, ebx_numerator, ecx_hz, edx;
617 unsigned int crystal_khz;
618
619 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
620 return 0;
621
622 if (boot_cpu_data.cpuid_level < 0x15)
623 return 0;
624
625 eax_denominator = ebx_numerator = ecx_hz = edx = 0;
626
627 /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */
628 cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx);
629
630 if (ebx_numerator == 0 || eax_denominator == 0)
631 return 0;
632
633 crystal_khz = ecx_hz / 1000;
634
635 /*
636 * Denverton SoCs don't report crystal clock, and also don't support
637 * CPUID.0x16 for the calculation below, so hardcode the 25MHz crystal
638 * clock.
639 */
640 if (crystal_khz == 0 &&
641 boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT_D)
642 crystal_khz = 25000;
643
644 /*
645 * TSC frequency reported directly by CPUID is a "hardware reported"
646 * frequency and is the most accurate one so far we have. This
647 * is considered a known frequency.
648 */
649 if (crystal_khz != 0)
650 setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
651
652 /*
653 * Some Intel SoCs like Skylake and Kabylake don't report the crystal
654 * clock, but we can easily calculate it to a high degree of accuracy
655 * by considering the crystal ratio and the CPU speed.
656 */
657 if (crystal_khz == 0 && boot_cpu_data.cpuid_level >= 0x16) {
658 unsigned int eax_base_mhz, ebx, ecx, edx;
659
660 cpuid(0x16, &eax_base_mhz, &ebx, &ecx, &edx);
661 crystal_khz = eax_base_mhz * 1000 *
662 eax_denominator / ebx_numerator;
663 }
664
665 if (crystal_khz == 0)
666 return 0;
667
668 /*
669 * For Atom SoCs TSC is the only reliable clocksource.
670 * Mark TSC reliable so no watchdog on it.
671 */
672 if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
673 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
674
675#ifdef CONFIG_X86_LOCAL_APIC
676 /*
677 * The local APIC appears to be fed by the core crystal clock
678 * (which sounds entirely sensible). We can set the global
679 * lapic_timer_period here to avoid having to calibrate the APIC
680 * timer later.
681 */
682 lapic_timer_period = crystal_khz * 1000 / HZ;
683#endif
684
685 return crystal_khz * ebx_numerator / eax_denominator;
686}
687
688static unsigned long cpu_khz_from_cpuid(void)
689{
690 unsigned int eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx;
691
692 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
693 return 0;
694
695 if (boot_cpu_data.cpuid_level < 0x16)
696 return 0;
697
698 eax_base_mhz = ebx_max_mhz = ecx_bus_mhz = edx = 0;
699
700 cpuid(0x16, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx);
701
702 return eax_base_mhz * 1000;
703}
704
705/*
706 * calibrate cpu using pit, hpet, and ptimer methods. They are available
707 * later in boot after acpi is initialized.
708 */
709static unsigned long pit_hpet_ptimer_calibrate_cpu(void)
710{
711 u64 tsc1, tsc2, delta, ref1, ref2;
712 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
713 unsigned long flags, latch, ms;
714 int hpet = is_hpet_enabled(), i, loopmin;
715
716 /*
717 * Run 5 calibration loops to get the lowest frequency value
718 * (the best estimate). We use two different calibration modes
719 * here:
720 *
721 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
722 * load a timeout of 50ms. We read the time right after we
723 * started the timer and wait until the PIT count down reaches
724 * zero. In each wait loop iteration we read the TSC and check
725 * the delta to the previous read. We keep track of the min
726 * and max values of that delta. The delta is mostly defined
727 * by the IO time of the PIT access, so we can detect when
728 * any disturbance happened between the two reads. If the
729 * maximum time is significantly larger than the minimum time,
730 * then we discard the result and have another try.
731 *
732 * 2) Reference counter. If available we use the HPET or the
733 * PMTIMER as a reference to check the sanity of that value.
734 * We use separate TSC readouts and check inside of the
735 * reference read for any possible disturbance. We dicard
736 * disturbed values here as well. We do that around the PIT
737 * calibration delay loop as we have to wait for a certain
738 * amount of time anyway.
739 */
740
741 /* Preset PIT loop values */
742 latch = CAL_LATCH;
743 ms = CAL_MS;
744 loopmin = CAL_PIT_LOOPS;
745
746 for (i = 0; i < 3; i++) {
747 unsigned long tsc_pit_khz;
748
749 /*
750 * Read the start value and the reference count of
751 * hpet/pmtimer when available. Then do the PIT
752 * calibration, which will take at least 50ms, and
753 * read the end value.
754 */
755 local_irq_save(flags);
756 tsc1 = tsc_read_refs(&ref1, hpet);
757 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
758 tsc2 = tsc_read_refs(&ref2, hpet);
759 local_irq_restore(flags);
760
761 /* Pick the lowest PIT TSC calibration so far */
762 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
763
764 /* hpet or pmtimer available ? */
765 if (ref1 == ref2)
766 continue;
767
768 /* Check, whether the sampling was disturbed */
769 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
770 continue;
771
772 tsc2 = (tsc2 - tsc1) * 1000000LL;
773 if (hpet)
774 tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
775 else
776 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
777
778 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
779
780 /* Check the reference deviation */
781 delta = ((u64) tsc_pit_min) * 100;
782 do_div(delta, tsc_ref_min);
783
784 /*
785 * If both calibration results are inside a 10% window
786 * then we can be sure, that the calibration
787 * succeeded. We break out of the loop right away. We
788 * use the reference value, as it is more precise.
789 */
790 if (delta >= 90 && delta <= 110) {
791 pr_info("PIT calibration matches %s. %d loops\n",
792 hpet ? "HPET" : "PMTIMER", i + 1);
793 return tsc_ref_min;
794 }
795
796 /*
797 * Check whether PIT failed more than once. This
798 * happens in virtualized environments. We need to
799 * give the virtual PC a slightly longer timeframe for
800 * the HPET/PMTIMER to make the result precise.
801 */
802 if (i == 1 && tsc_pit_min == ULONG_MAX) {
803 latch = CAL2_LATCH;
804 ms = CAL2_MS;
805 loopmin = CAL2_PIT_LOOPS;
806 }
807 }
808
809 /*
810 * Now check the results.
811 */
812 if (tsc_pit_min == ULONG_MAX) {
813 /* PIT gave no useful value */
814 pr_warn("Unable to calibrate against PIT\n");
815
816 /* We don't have an alternative source, disable TSC */
817 if (!hpet && !ref1 && !ref2) {
818 pr_notice("No reference (HPET/PMTIMER) available\n");
819 return 0;
820 }
821
822 /* The alternative source failed as well, disable TSC */
823 if (tsc_ref_min == ULONG_MAX) {
824 pr_warn("HPET/PMTIMER calibration failed\n");
825 return 0;
826 }
827
828 /* Use the alternative source */
829 pr_info("using %s reference calibration\n",
830 hpet ? "HPET" : "PMTIMER");
831
832 return tsc_ref_min;
833 }
834
835 /* We don't have an alternative source, use the PIT calibration value */
836 if (!hpet && !ref1 && !ref2) {
837 pr_info("Using PIT calibration value\n");
838 return tsc_pit_min;
839 }
840
841 /* The alternative source failed, use the PIT calibration value */
842 if (tsc_ref_min == ULONG_MAX) {
843 pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n");
844 return tsc_pit_min;
845 }
846
847 /*
848 * The calibration values differ too much. In doubt, we use
849 * the PIT value as we know that there are PMTIMERs around
850 * running at double speed. At least we let the user know:
851 */
852 pr_warn("PIT calibration deviates from %s: %lu %lu\n",
853 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
854 pr_info("Using PIT calibration value\n");
855 return tsc_pit_min;
856}
857
858/**
859 * native_calibrate_cpu_early - can calibrate the cpu early in boot
860 */
861unsigned long native_calibrate_cpu_early(void)
862{
863 unsigned long flags, fast_calibrate = cpu_khz_from_cpuid();
864
865 if (!fast_calibrate)
866 fast_calibrate = cpu_khz_from_msr();
867 if (!fast_calibrate) {
868 local_irq_save(flags);
869 fast_calibrate = quick_pit_calibrate();
870 local_irq_restore(flags);
871 }
872 return fast_calibrate;
873}
874
875
876/**
877 * native_calibrate_cpu - calibrate the cpu
878 */
879static unsigned long native_calibrate_cpu(void)
880{
881 unsigned long tsc_freq = native_calibrate_cpu_early();
882
883 if (!tsc_freq)
884 tsc_freq = pit_hpet_ptimer_calibrate_cpu();
885
886 return tsc_freq;
887}
888
889void recalibrate_cpu_khz(void)
890{
891#ifndef CONFIG_SMP
892 unsigned long cpu_khz_old = cpu_khz;
893
894 if (!boot_cpu_has(X86_FEATURE_TSC))
895 return;
896
897 cpu_khz = x86_platform.calibrate_cpu();
898 tsc_khz = x86_platform.calibrate_tsc();
899 if (tsc_khz == 0)
900 tsc_khz = cpu_khz;
901 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
902 cpu_khz = tsc_khz;
903 cpu_data(0).loops_per_jiffy = cpufreq_scale(cpu_data(0).loops_per_jiffy,
904 cpu_khz_old, cpu_khz);
905#endif
906}
907
908EXPORT_SYMBOL(recalibrate_cpu_khz);
909
910
911static unsigned long long cyc2ns_suspend;
912
913void tsc_save_sched_clock_state(void)
914{
915 if (!sched_clock_stable())
916 return;
917
918 cyc2ns_suspend = sched_clock();
919}
920
921/*
922 * Even on processors with invariant TSC, TSC gets reset in some the
923 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
924 * arbitrary value (still sync'd across cpu's) during resume from such sleep
925 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
926 * that sched_clock() continues from the point where it was left off during
927 * suspend.
928 */
929void tsc_restore_sched_clock_state(void)
930{
931 unsigned long long offset;
932 unsigned long flags;
933 int cpu;
934
935 if (!sched_clock_stable())
936 return;
937
938 local_irq_save(flags);
939
940 /*
941 * We're coming out of suspend, there's no concurrency yet; don't
942 * bother being nice about the RCU stuff, just write to both
943 * data fields.
944 */
945
946 this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0);
947 this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0);
948
949 offset = cyc2ns_suspend - sched_clock();
950
951 for_each_possible_cpu(cpu) {
952 per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset;
953 per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset;
954 }
955
956 local_irq_restore(flags);
957}
958
959#ifdef CONFIG_CPU_FREQ
960/*
961 * Frequency scaling support. Adjust the TSC based timer when the CPU frequency
962 * changes.
963 *
964 * NOTE: On SMP the situation is not fixable in general, so simply mark the TSC
965 * as unstable and give up in those cases.
966 *
967 * Should fix up last_tsc too. Currently gettimeofday in the
968 * first tick after the change will be slightly wrong.
969 */
970
971static unsigned int ref_freq;
972static unsigned long loops_per_jiffy_ref;
973static unsigned long tsc_khz_ref;
974
975static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
976 void *data)
977{
978 struct cpufreq_freqs *freq = data;
979
980 if (num_online_cpus() > 1) {
981 mark_tsc_unstable("cpufreq changes on SMP");
982 return 0;
983 }
984
985 if (!ref_freq) {
986 ref_freq = freq->old;
987 loops_per_jiffy_ref = boot_cpu_data.loops_per_jiffy;
988 tsc_khz_ref = tsc_khz;
989 }
990
991 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
992 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
993 boot_cpu_data.loops_per_jiffy =
994 cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
995
996 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
997 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
998 mark_tsc_unstable("cpufreq changes");
999
1000 set_cyc2ns_scale(tsc_khz, freq->policy->cpu, rdtsc());
1001 }
1002
1003 return 0;
1004}
1005
1006static struct notifier_block time_cpufreq_notifier_block = {
1007 .notifier_call = time_cpufreq_notifier
1008};
1009
1010static int __init cpufreq_register_tsc_scaling(void)
1011{
1012 if (!boot_cpu_has(X86_FEATURE_TSC))
1013 return 0;
1014 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1015 return 0;
1016 cpufreq_register_notifier(&time_cpufreq_notifier_block,
1017 CPUFREQ_TRANSITION_NOTIFIER);
1018 return 0;
1019}
1020
1021core_initcall(cpufreq_register_tsc_scaling);
1022
1023#endif /* CONFIG_CPU_FREQ */
1024
1025#define ART_CPUID_LEAF (0x15)
1026#define ART_MIN_DENOMINATOR (1)
1027
1028
1029/*
1030 * If ART is present detect the numerator:denominator to convert to TSC
1031 */
1032static void __init detect_art(void)
1033{
1034 unsigned int unused[2];
1035
1036 if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF)
1037 return;
1038
1039 /*
1040 * Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required,
1041 * and the TSC counter resets must not occur asynchronously.
1042 */
1043 if (boot_cpu_has(X86_FEATURE_HYPERVISOR) ||
1044 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) ||
1045 !boot_cpu_has(X86_FEATURE_TSC_ADJUST) ||
1046 tsc_async_resets)
1047 return;
1048
1049 cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator,
1050 &art_to_tsc_numerator, unused, unused+1);
1051
1052 if (art_to_tsc_denominator < ART_MIN_DENOMINATOR)
1053 return;
1054
1055 rdmsrl(MSR_IA32_TSC_ADJUST, art_to_tsc_offset);
1056
1057 /* Make this sticky over multiple CPU init calls */
1058 setup_force_cpu_cap(X86_FEATURE_ART);
1059}
1060
1061
1062/* clocksource code */
1063
1064static void tsc_resume(struct clocksource *cs)
1065{
1066 tsc_verify_tsc_adjust(true);
1067}
1068
1069/*
1070 * We used to compare the TSC to the cycle_last value in the clocksource
1071 * structure to avoid a nasty time-warp. This can be observed in a
1072 * very small window right after one CPU updated cycle_last under
1073 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
1074 * is smaller than the cycle_last reference value due to a TSC which
1075 * is slighty behind. This delta is nowhere else observable, but in
1076 * that case it results in a forward time jump in the range of hours
1077 * due to the unsigned delta calculation of the time keeping core
1078 * code, which is necessary to support wrapping clocksources like pm
1079 * timer.
1080 *
1081 * This sanity check is now done in the core timekeeping code.
1082 * checking the result of read_tsc() - cycle_last for being negative.
1083 * That works because CLOCKSOURCE_MASK(64) does not mask out any bit.
1084 */
1085static u64 read_tsc(struct clocksource *cs)
1086{
1087 return (u64)rdtsc_ordered();
1088}
1089
1090static void tsc_cs_mark_unstable(struct clocksource *cs)
1091{
1092 if (tsc_unstable)
1093 return;
1094
1095 tsc_unstable = 1;
1096 if (using_native_sched_clock())
1097 clear_sched_clock_stable();
1098 disable_sched_clock_irqtime();
1099 pr_info("Marking TSC unstable due to clocksource watchdog\n");
1100}
1101
1102static void tsc_cs_tick_stable(struct clocksource *cs)
1103{
1104 if (tsc_unstable)
1105 return;
1106
1107 if (using_native_sched_clock())
1108 sched_clock_tick_stable();
1109}
1110
1111/*
1112 * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc()
1113 */
1114static struct clocksource clocksource_tsc_early = {
1115 .name = "tsc-early",
1116 .rating = 299,
1117 .read = read_tsc,
1118 .mask = CLOCKSOURCE_MASK(64),
1119 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
1120 CLOCK_SOURCE_MUST_VERIFY,
1121 .archdata = { .vclock_mode = VCLOCK_TSC },
1122 .resume = tsc_resume,
1123 .mark_unstable = tsc_cs_mark_unstable,
1124 .tick_stable = tsc_cs_tick_stable,
1125 .list = LIST_HEAD_INIT(clocksource_tsc_early.list),
1126};
1127
1128/*
1129 * Must mark VALID_FOR_HRES early such that when we unregister tsc_early
1130 * this one will immediately take over. We will only register if TSC has
1131 * been found good.
1132 */
1133static struct clocksource clocksource_tsc = {
1134 .name = "tsc",
1135 .rating = 300,
1136 .read = read_tsc,
1137 .mask = CLOCKSOURCE_MASK(64),
1138 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
1139 CLOCK_SOURCE_VALID_FOR_HRES |
1140 CLOCK_SOURCE_MUST_VERIFY,
1141 .archdata = { .vclock_mode = VCLOCK_TSC },
1142 .resume = tsc_resume,
1143 .mark_unstable = tsc_cs_mark_unstable,
1144 .tick_stable = tsc_cs_tick_stable,
1145 .list = LIST_HEAD_INIT(clocksource_tsc.list),
1146};
1147
1148void mark_tsc_unstable(char *reason)
1149{
1150 if (tsc_unstable)
1151 return;
1152
1153 tsc_unstable = 1;
1154 if (using_native_sched_clock())
1155 clear_sched_clock_stable();
1156 disable_sched_clock_irqtime();
1157 pr_info("Marking TSC unstable due to %s\n", reason);
1158
1159 clocksource_mark_unstable(&clocksource_tsc_early);
1160 clocksource_mark_unstable(&clocksource_tsc);
1161}
1162
1163EXPORT_SYMBOL_GPL(mark_tsc_unstable);
1164
1165static void __init check_system_tsc_reliable(void)
1166{
1167#if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC)
1168 if (is_geode_lx()) {
1169 /* RTSC counts during suspend */
1170#define RTSC_SUSP 0x100
1171 unsigned long res_low, res_high;
1172
1173 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
1174 /* Geode_LX - the OLPC CPU has a very reliable TSC */
1175 if (res_low & RTSC_SUSP)
1176 tsc_clocksource_reliable = 1;
1177 }
1178#endif
1179 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
1180 tsc_clocksource_reliable = 1;
1181}
1182
1183/*
1184 * Make an educated guess if the TSC is trustworthy and synchronized
1185 * over all CPUs.
1186 */
1187int unsynchronized_tsc(void)
1188{
1189 if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_unstable)
1190 return 1;
1191
1192#ifdef CONFIG_SMP
1193 if (apic_is_clustered_box())
1194 return 1;
1195#endif
1196
1197 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1198 return 0;
1199
1200 if (tsc_clocksource_reliable)
1201 return 0;
1202 /*
1203 * Intel systems are normally all synchronized.
1204 * Exceptions must mark TSC as unstable:
1205 */
1206 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1207 /* assume multi socket systems are not synchronized: */
1208 if (num_possible_cpus() > 1)
1209 return 1;
1210 }
1211
1212 return 0;
1213}
1214
1215/*
1216 * Convert ART to TSC given numerator/denominator found in detect_art()
1217 */
1218struct system_counterval_t convert_art_to_tsc(u64 art)
1219{
1220 u64 tmp, res, rem;
1221
1222 rem = do_div(art, art_to_tsc_denominator);
1223
1224 res = art * art_to_tsc_numerator;
1225 tmp = rem * art_to_tsc_numerator;
1226
1227 do_div(tmp, art_to_tsc_denominator);
1228 res += tmp + art_to_tsc_offset;
1229
1230 return (struct system_counterval_t) {.cs = art_related_clocksource,
1231 .cycles = res};
1232}
1233EXPORT_SYMBOL(convert_art_to_tsc);
1234
1235/**
1236 * convert_art_ns_to_tsc() - Convert ART in nanoseconds to TSC.
1237 * @art_ns: ART (Always Running Timer) in unit of nanoseconds
1238 *
1239 * PTM requires all timestamps to be in units of nanoseconds. When user
1240 * software requests a cross-timestamp, this function converts system timestamp
1241 * to TSC.
1242 *
1243 * This is valid when CPU feature flag X86_FEATURE_TSC_KNOWN_FREQ is set
1244 * indicating the tsc_khz is derived from CPUID[15H]. Drivers should check
1245 * that this flag is set before conversion to TSC is attempted.
1246 *
1247 * Return:
1248 * struct system_counterval_t - system counter value with the pointer to the
1249 * corresponding clocksource
1250 * @cycles: System counter value
1251 * @cs: Clocksource corresponding to system counter value. Used
1252 * by timekeeping code to verify comparibility of two cycle
1253 * values.
1254 */
1255
1256struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns)
1257{
1258 u64 tmp, res, rem;
1259
1260 rem = do_div(art_ns, USEC_PER_SEC);
1261
1262 res = art_ns * tsc_khz;
1263 tmp = rem * tsc_khz;
1264
1265 do_div(tmp, USEC_PER_SEC);
1266 res += tmp;
1267
1268 return (struct system_counterval_t) { .cs = art_related_clocksource,
1269 .cycles = res};
1270}
1271EXPORT_SYMBOL(convert_art_ns_to_tsc);
1272
1273
1274static void tsc_refine_calibration_work(struct work_struct *work);
1275static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
1276/**
1277 * tsc_refine_calibration_work - Further refine tsc freq calibration
1278 * @work - ignored.
1279 *
1280 * This functions uses delayed work over a period of a
1281 * second to further refine the TSC freq value. Since this is
1282 * timer based, instead of loop based, we don't block the boot
1283 * process while this longer calibration is done.
1284 *
1285 * If there are any calibration anomalies (too many SMIs, etc),
1286 * or the refined calibration is off by 1% of the fast early
1287 * calibration, we throw out the new calibration and use the
1288 * early calibration.
1289 */
1290static void tsc_refine_calibration_work(struct work_struct *work)
1291{
1292 static u64 tsc_start = ULLONG_MAX, ref_start;
1293 static int hpet;
1294 u64 tsc_stop, ref_stop, delta;
1295 unsigned long freq;
1296 int cpu;
1297
1298 /* Don't bother refining TSC on unstable systems */
1299 if (tsc_unstable)
1300 goto unreg;
1301
1302 /*
1303 * Since the work is started early in boot, we may be
1304 * delayed the first time we expire. So set the workqueue
1305 * again once we know timers are working.
1306 */
1307 if (tsc_start == ULLONG_MAX) {
1308restart:
1309 /*
1310 * Only set hpet once, to avoid mixing hardware
1311 * if the hpet becomes enabled later.
1312 */
1313 hpet = is_hpet_enabled();
1314 tsc_start = tsc_read_refs(&ref_start, hpet);
1315 schedule_delayed_work(&tsc_irqwork, HZ);
1316 return;
1317 }
1318
1319 tsc_stop = tsc_read_refs(&ref_stop, hpet);
1320
1321 /* hpet or pmtimer available ? */
1322 if (ref_start == ref_stop)
1323 goto out;
1324
1325 /* Check, whether the sampling was disturbed */
1326 if (tsc_stop == ULLONG_MAX)
1327 goto restart;
1328
1329 delta = tsc_stop - tsc_start;
1330 delta *= 1000000LL;
1331 if (hpet)
1332 freq = calc_hpet_ref(delta, ref_start, ref_stop);
1333 else
1334 freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
1335
1336 /* Make sure we're within 1% */
1337 if (abs(tsc_khz - freq) > tsc_khz/100)
1338 goto out;
1339
1340 tsc_khz = freq;
1341 pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",
1342 (unsigned long)tsc_khz / 1000,
1343 (unsigned long)tsc_khz % 1000);
1344
1345 /* Inform the TSC deadline clockevent devices about the recalibration */
1346 lapic_update_tsc_freq();
1347
1348 /* Update the sched_clock() rate to match the clocksource one */
1349 for_each_possible_cpu(cpu)
1350 set_cyc2ns_scale(tsc_khz, cpu, tsc_stop);
1351
1352out:
1353 if (tsc_unstable)
1354 goto unreg;
1355
1356 if (boot_cpu_has(X86_FEATURE_ART))
1357 art_related_clocksource = &clocksource_tsc;
1358 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1359unreg:
1360 clocksource_unregister(&clocksource_tsc_early);
1361}
1362
1363
1364static int __init init_tsc_clocksource(void)
1365{
1366 if (!boot_cpu_has(X86_FEATURE_TSC) || !tsc_khz)
1367 return 0;
1368
1369 if (tsc_unstable)
1370 goto unreg;
1371
1372 if (tsc_clocksource_reliable || no_tsc_watchdog)
1373 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
1374
1375 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3))
1376 clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1377
1378 /*
1379 * When TSC frequency is known (retrieved via MSR or CPUID), we skip
1380 * the refined calibration and directly register it as a clocksource.
1381 */
1382 if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) {
1383 if (boot_cpu_has(X86_FEATURE_ART))
1384 art_related_clocksource = &clocksource_tsc;
1385 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1386unreg:
1387 clocksource_unregister(&clocksource_tsc_early);
1388 return 0;
1389 }
1390
1391 schedule_delayed_work(&tsc_irqwork, 0);
1392 return 0;
1393}
1394/*
1395 * We use device_initcall here, to ensure we run after the hpet
1396 * is fully initialized, which may occur at fs_initcall time.
1397 */
1398device_initcall(init_tsc_clocksource);
1399
1400static bool __init determine_cpu_tsc_frequencies(bool early)
1401{
1402 /* Make sure that cpu and tsc are not already calibrated */
1403 WARN_ON(cpu_khz || tsc_khz);
1404
1405 if (early) {
1406 cpu_khz = x86_platform.calibrate_cpu();
1407 tsc_khz = x86_platform.calibrate_tsc();
1408 } else {
1409 /* We should not be here with non-native cpu calibration */
1410 WARN_ON(x86_platform.calibrate_cpu != native_calibrate_cpu);
1411 cpu_khz = pit_hpet_ptimer_calibrate_cpu();
1412 }
1413
1414 /*
1415 * Trust non-zero tsc_khz as authoritative,
1416 * and use it to sanity check cpu_khz,
1417 * which will be off if system timer is off.
1418 */
1419 if (tsc_khz == 0)
1420 tsc_khz = cpu_khz;
1421 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
1422 cpu_khz = tsc_khz;
1423
1424 if (tsc_khz == 0)
1425 return false;
1426
1427 pr_info("Detected %lu.%03lu MHz processor\n",
1428 (unsigned long)cpu_khz / KHZ,
1429 (unsigned long)cpu_khz % KHZ);
1430
1431 if (cpu_khz != tsc_khz) {
1432 pr_info("Detected %lu.%03lu MHz TSC",
1433 (unsigned long)tsc_khz / KHZ,
1434 (unsigned long)tsc_khz % KHZ);
1435 }
1436 return true;
1437}
1438
1439static unsigned long __init get_loops_per_jiffy(void)
1440{
1441 u64 lpj = (u64)tsc_khz * KHZ;
1442
1443 do_div(lpj, HZ);
1444 return lpj;
1445}
1446
1447static void __init tsc_enable_sched_clock(void)
1448{
1449 /* Sanitize TSC ADJUST before cyc2ns gets initialized */
1450 tsc_store_and_check_tsc_adjust(true);
1451 cyc2ns_init_boot_cpu();
1452 static_branch_enable(&__use_tsc);
1453}
1454
1455void __init tsc_early_init(void)
1456{
1457 if (!boot_cpu_has(X86_FEATURE_TSC))
1458 return;
1459 /* Don't change UV TSC multi-chassis synchronization */
1460 if (is_early_uv_system())
1461 return;
1462 if (!determine_cpu_tsc_frequencies(true))
1463 return;
1464 loops_per_jiffy = get_loops_per_jiffy();
1465
1466 tsc_enable_sched_clock();
1467}
1468
1469void __init tsc_init(void)
1470{
1471 /*
1472 * native_calibrate_cpu_early can only calibrate using methods that are
1473 * available early in boot.
1474 */
1475 if (x86_platform.calibrate_cpu == native_calibrate_cpu_early)
1476 x86_platform.calibrate_cpu = native_calibrate_cpu;
1477
1478 if (!boot_cpu_has(X86_FEATURE_TSC)) {
1479 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1480 return;
1481 }
1482
1483 if (!tsc_khz) {
1484 /* We failed to determine frequencies earlier, try again */
1485 if (!determine_cpu_tsc_frequencies(false)) {
1486 mark_tsc_unstable("could not calculate TSC khz");
1487 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1488 return;
1489 }
1490 tsc_enable_sched_clock();
1491 }
1492
1493 cyc2ns_init_secondary_cpus();
1494
1495 if (!no_sched_irq_time)
1496 enable_sched_clock_irqtime();
1497
1498 lpj_fine = get_loops_per_jiffy();
1499 use_tsc_delay();
1500
1501 check_system_tsc_reliable();
1502
1503 if (unsynchronized_tsc()) {
1504 mark_tsc_unstable("TSCs unsynchronized");
1505 return;
1506 }
1507
1508 if (tsc_clocksource_reliable || no_tsc_watchdog)
1509 clocksource_tsc_early.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
1510
1511 clocksource_register_khz(&clocksource_tsc_early, tsc_khz);
1512 detect_art();
1513}
1514
1515#ifdef CONFIG_SMP
1516/*
1517 * If we have a constant TSC and are using the TSC for the delay loop,
1518 * we can skip clock calibration if another cpu in the same socket has already
1519 * been calibrated. This assumes that CONSTANT_TSC applies to all
1520 * cpus in the socket - this should be a safe assumption.
1521 */
1522unsigned long calibrate_delay_is_known(void)
1523{
1524 int sibling, cpu = smp_processor_id();
1525 int constant_tsc = cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC);
1526 const struct cpumask *mask = topology_core_cpumask(cpu);
1527
1528 if (!constant_tsc || !mask)
1529 return 0;
1530
1531 sibling = cpumask_any_but(mask, cpu);
1532 if (sibling < nr_cpu_ids)
1533 return cpu_data(sibling).loops_per_jiffy;
1534 return 0;
1535}
1536#endif
1#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
2
3#include <linux/kernel.h>
4#include <linux/sched.h>
5#include <linux/init.h>
6#include <linux/export.h>
7#include <linux/timer.h>
8#include <linux/acpi_pmtmr.h>
9#include <linux/cpufreq.h>
10#include <linux/delay.h>
11#include <linux/clocksource.h>
12#include <linux/percpu.h>
13#include <linux/timex.h>
14#include <linux/static_key.h>
15
16#include <asm/hpet.h>
17#include <asm/timer.h>
18#include <asm/vgtod.h>
19#include <asm/time.h>
20#include <asm/delay.h>
21#include <asm/hypervisor.h>
22#include <asm/nmi.h>
23#include <asm/x86_init.h>
24#include <asm/geode.h>
25#include <asm/apic.h>
26#include <asm/intel-family.h>
27
28unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
29EXPORT_SYMBOL(cpu_khz);
30
31unsigned int __read_mostly tsc_khz;
32EXPORT_SYMBOL(tsc_khz);
33
34/*
35 * TSC can be unstable due to cpufreq or due to unsynced TSCs
36 */
37static int __read_mostly tsc_unstable;
38
39/* native_sched_clock() is called before tsc_init(), so
40 we must start with the TSC soft disabled to prevent
41 erroneous rdtsc usage on !boot_cpu_has(X86_FEATURE_TSC) processors */
42static int __read_mostly tsc_disabled = -1;
43
44static DEFINE_STATIC_KEY_FALSE(__use_tsc);
45
46int tsc_clocksource_reliable;
47
48static u32 art_to_tsc_numerator;
49static u32 art_to_tsc_denominator;
50static u64 art_to_tsc_offset;
51struct clocksource *art_related_clocksource;
52
53/*
54 * Use a ring-buffer like data structure, where a writer advances the head by
55 * writing a new data entry and a reader advances the tail when it observes a
56 * new entry.
57 *
58 * Writers are made to wait on readers until there's space to write a new
59 * entry.
60 *
61 * This means that we can always use an {offset, mul} pair to compute a ns
62 * value that is 'roughly' in the right direction, even if we're writing a new
63 * {offset, mul} pair during the clock read.
64 *
65 * The down-side is that we can no longer guarantee strict monotonicity anymore
66 * (assuming the TSC was that to begin with), because while we compute the
67 * intersection point of the two clock slopes and make sure the time is
68 * continuous at the point of switching; we can no longer guarantee a reader is
69 * strictly before or after the switch point.
70 *
71 * It does mean a reader no longer needs to disable IRQs in order to avoid
72 * CPU-Freq updates messing with his times, and similarly an NMI reader will
73 * no longer run the risk of hitting half-written state.
74 */
75
76struct cyc2ns {
77 struct cyc2ns_data data[2]; /* 0 + 2*24 = 48 */
78 struct cyc2ns_data *head; /* 48 + 8 = 56 */
79 struct cyc2ns_data *tail; /* 56 + 8 = 64 */
80}; /* exactly fits one cacheline */
81
82static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns);
83
84struct cyc2ns_data *cyc2ns_read_begin(void)
85{
86 struct cyc2ns_data *head;
87
88 preempt_disable();
89
90 head = this_cpu_read(cyc2ns.head);
91 /*
92 * Ensure we observe the entry when we observe the pointer to it.
93 * matches the wmb from cyc2ns_write_end().
94 */
95 smp_read_barrier_depends();
96 head->__count++;
97 barrier();
98
99 return head;
100}
101
102void cyc2ns_read_end(struct cyc2ns_data *head)
103{
104 barrier();
105 /*
106 * If we're the outer most nested read; update the tail pointer
107 * when we're done. This notifies possible pending writers
108 * that we've observed the head pointer and that the other
109 * entry is now free.
110 */
111 if (!--head->__count) {
112 /*
113 * x86-TSO does not reorder writes with older reads;
114 * therefore once this write becomes visible to another
115 * cpu, we must be finished reading the cyc2ns_data.
116 *
117 * matches with cyc2ns_write_begin().
118 */
119 this_cpu_write(cyc2ns.tail, head);
120 }
121 preempt_enable();
122}
123
124/*
125 * Begin writing a new @data entry for @cpu.
126 *
127 * Assumes some sort of write side lock; currently 'provided' by the assumption
128 * that cpufreq will call its notifiers sequentially.
129 */
130static struct cyc2ns_data *cyc2ns_write_begin(int cpu)
131{
132 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
133 struct cyc2ns_data *data = c2n->data;
134
135 if (data == c2n->head)
136 data++;
137
138 /* XXX send an IPI to @cpu in order to guarantee a read? */
139
140 /*
141 * When we observe the tail write from cyc2ns_read_end(),
142 * the cpu must be done with that entry and its safe
143 * to start writing to it.
144 */
145 while (c2n->tail == data)
146 cpu_relax();
147
148 return data;
149}
150
151static void cyc2ns_write_end(int cpu, struct cyc2ns_data *data)
152{
153 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
154
155 /*
156 * Ensure the @data writes are visible before we publish the
157 * entry. Matches the data-depencency in cyc2ns_read_begin().
158 */
159 smp_wmb();
160
161 ACCESS_ONCE(c2n->head) = data;
162}
163
164/*
165 * Accelerators for sched_clock()
166 * convert from cycles(64bits) => nanoseconds (64bits)
167 * basic equation:
168 * ns = cycles / (freq / ns_per_sec)
169 * ns = cycles * (ns_per_sec / freq)
170 * ns = cycles * (10^9 / (cpu_khz * 10^3))
171 * ns = cycles * (10^6 / cpu_khz)
172 *
173 * Then we use scaling math (suggested by george@mvista.com) to get:
174 * ns = cycles * (10^6 * SC / cpu_khz) / SC
175 * ns = cycles * cyc2ns_scale / SC
176 *
177 * And since SC is a constant power of two, we can convert the div
178 * into a shift. The larger SC is, the more accurate the conversion, but
179 * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication
180 * (64-bit result) can be used.
181 *
182 * We can use khz divisor instead of mhz to keep a better precision.
183 * (mathieu.desnoyers@polymtl.ca)
184 *
185 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
186 */
187
188static void cyc2ns_data_init(struct cyc2ns_data *data)
189{
190 data->cyc2ns_mul = 0;
191 data->cyc2ns_shift = 0;
192 data->cyc2ns_offset = 0;
193 data->__count = 0;
194}
195
196static void cyc2ns_init(int cpu)
197{
198 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
199
200 cyc2ns_data_init(&c2n->data[0]);
201 cyc2ns_data_init(&c2n->data[1]);
202
203 c2n->head = c2n->data;
204 c2n->tail = c2n->data;
205}
206
207static inline unsigned long long cycles_2_ns(unsigned long long cyc)
208{
209 struct cyc2ns_data *data, *tail;
210 unsigned long long ns;
211
212 /*
213 * See cyc2ns_read_*() for details; replicated in order to avoid
214 * an extra few instructions that came with the abstraction.
215 * Notable, it allows us to only do the __count and tail update
216 * dance when its actually needed.
217 */
218
219 preempt_disable_notrace();
220 data = this_cpu_read(cyc2ns.head);
221 tail = this_cpu_read(cyc2ns.tail);
222
223 if (likely(data == tail)) {
224 ns = data->cyc2ns_offset;
225 ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift);
226 } else {
227 data->__count++;
228
229 barrier();
230
231 ns = data->cyc2ns_offset;
232 ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift);
233
234 barrier();
235
236 if (!--data->__count)
237 this_cpu_write(cyc2ns.tail, data);
238 }
239 preempt_enable_notrace();
240
241 return ns;
242}
243
244static void set_cyc2ns_scale(unsigned long khz, int cpu)
245{
246 unsigned long long tsc_now, ns_now;
247 struct cyc2ns_data *data;
248 unsigned long flags;
249
250 local_irq_save(flags);
251 sched_clock_idle_sleep_event();
252
253 if (!khz)
254 goto done;
255
256 data = cyc2ns_write_begin(cpu);
257
258 tsc_now = rdtsc();
259 ns_now = cycles_2_ns(tsc_now);
260
261 /*
262 * Compute a new multiplier as per the above comment and ensure our
263 * time function is continuous; see the comment near struct
264 * cyc2ns_data.
265 */
266 clocks_calc_mult_shift(&data->cyc2ns_mul, &data->cyc2ns_shift, khz,
267 NSEC_PER_MSEC, 0);
268
269 /*
270 * cyc2ns_shift is exported via arch_perf_update_userpage() where it is
271 * not expected to be greater than 31 due to the original published
272 * conversion algorithm shifting a 32-bit value (now specifies a 64-bit
273 * value) - refer perf_event_mmap_page documentation in perf_event.h.
274 */
275 if (data->cyc2ns_shift == 32) {
276 data->cyc2ns_shift = 31;
277 data->cyc2ns_mul >>= 1;
278 }
279
280 data->cyc2ns_offset = ns_now -
281 mul_u64_u32_shr(tsc_now, data->cyc2ns_mul, data->cyc2ns_shift);
282
283 cyc2ns_write_end(cpu, data);
284
285done:
286 sched_clock_idle_wakeup_event(0);
287 local_irq_restore(flags);
288}
289/*
290 * Scheduler clock - returns current time in nanosec units.
291 */
292u64 native_sched_clock(void)
293{
294 if (static_branch_likely(&__use_tsc)) {
295 u64 tsc_now = rdtsc();
296
297 /* return the value in ns */
298 return cycles_2_ns(tsc_now);
299 }
300
301 /*
302 * Fall back to jiffies if there's no TSC available:
303 * ( But note that we still use it if the TSC is marked
304 * unstable. We do this because unlike Time Of Day,
305 * the scheduler clock tolerates small errors and it's
306 * very important for it to be as fast as the platform
307 * can achieve it. )
308 */
309
310 /* No locking but a rare wrong value is not a big deal: */
311 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
312}
313
314/*
315 * Generate a sched_clock if you already have a TSC value.
316 */
317u64 native_sched_clock_from_tsc(u64 tsc)
318{
319 return cycles_2_ns(tsc);
320}
321
322/* We need to define a real function for sched_clock, to override the
323 weak default version */
324#ifdef CONFIG_PARAVIRT
325unsigned long long sched_clock(void)
326{
327 return paravirt_sched_clock();
328}
329#else
330unsigned long long
331sched_clock(void) __attribute__((alias("native_sched_clock")));
332#endif
333
334int check_tsc_unstable(void)
335{
336 return tsc_unstable;
337}
338EXPORT_SYMBOL_GPL(check_tsc_unstable);
339
340#ifdef CONFIG_X86_TSC
341int __init notsc_setup(char *str)
342{
343 pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n");
344 tsc_disabled = 1;
345 return 1;
346}
347#else
348/*
349 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
350 * in cpu/common.c
351 */
352int __init notsc_setup(char *str)
353{
354 setup_clear_cpu_cap(X86_FEATURE_TSC);
355 return 1;
356}
357#endif
358
359__setup("notsc", notsc_setup);
360
361static int no_sched_irq_time;
362
363static int __init tsc_setup(char *str)
364{
365 if (!strcmp(str, "reliable"))
366 tsc_clocksource_reliable = 1;
367 if (!strncmp(str, "noirqtime", 9))
368 no_sched_irq_time = 1;
369 return 1;
370}
371
372__setup("tsc=", tsc_setup);
373
374#define MAX_RETRIES 5
375#define SMI_TRESHOLD 50000
376
377/*
378 * Read TSC and the reference counters. Take care of SMI disturbance
379 */
380static u64 tsc_read_refs(u64 *p, int hpet)
381{
382 u64 t1, t2;
383 int i;
384
385 for (i = 0; i < MAX_RETRIES; i++) {
386 t1 = get_cycles();
387 if (hpet)
388 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
389 else
390 *p = acpi_pm_read_early();
391 t2 = get_cycles();
392 if ((t2 - t1) < SMI_TRESHOLD)
393 return t2;
394 }
395 return ULLONG_MAX;
396}
397
398/*
399 * Calculate the TSC frequency from HPET reference
400 */
401static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
402{
403 u64 tmp;
404
405 if (hpet2 < hpet1)
406 hpet2 += 0x100000000ULL;
407 hpet2 -= hpet1;
408 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
409 do_div(tmp, 1000000);
410 do_div(deltatsc, tmp);
411
412 return (unsigned long) deltatsc;
413}
414
415/*
416 * Calculate the TSC frequency from PMTimer reference
417 */
418static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
419{
420 u64 tmp;
421
422 if (!pm1 && !pm2)
423 return ULONG_MAX;
424
425 if (pm2 < pm1)
426 pm2 += (u64)ACPI_PM_OVRRUN;
427 pm2 -= pm1;
428 tmp = pm2 * 1000000000LL;
429 do_div(tmp, PMTMR_TICKS_PER_SEC);
430 do_div(deltatsc, tmp);
431
432 return (unsigned long) deltatsc;
433}
434
435#define CAL_MS 10
436#define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
437#define CAL_PIT_LOOPS 1000
438
439#define CAL2_MS 50
440#define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
441#define CAL2_PIT_LOOPS 5000
442
443
444/*
445 * Try to calibrate the TSC against the Programmable
446 * Interrupt Timer and return the frequency of the TSC
447 * in kHz.
448 *
449 * Return ULONG_MAX on failure to calibrate.
450 */
451static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
452{
453 u64 tsc, t1, t2, delta;
454 unsigned long tscmin, tscmax;
455 int pitcnt;
456
457 /* Set the Gate high, disable speaker */
458 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
459
460 /*
461 * Setup CTC channel 2* for mode 0, (interrupt on terminal
462 * count mode), binary count. Set the latch register to 50ms
463 * (LSB then MSB) to begin countdown.
464 */
465 outb(0xb0, 0x43);
466 outb(latch & 0xff, 0x42);
467 outb(latch >> 8, 0x42);
468
469 tsc = t1 = t2 = get_cycles();
470
471 pitcnt = 0;
472 tscmax = 0;
473 tscmin = ULONG_MAX;
474 while ((inb(0x61) & 0x20) == 0) {
475 t2 = get_cycles();
476 delta = t2 - tsc;
477 tsc = t2;
478 if ((unsigned long) delta < tscmin)
479 tscmin = (unsigned int) delta;
480 if ((unsigned long) delta > tscmax)
481 tscmax = (unsigned int) delta;
482 pitcnt++;
483 }
484
485 /*
486 * Sanity checks:
487 *
488 * If we were not able to read the PIT more than loopmin
489 * times, then we have been hit by a massive SMI
490 *
491 * If the maximum is 10 times larger than the minimum,
492 * then we got hit by an SMI as well.
493 */
494 if (pitcnt < loopmin || tscmax > 10 * tscmin)
495 return ULONG_MAX;
496
497 /* Calculate the PIT value */
498 delta = t2 - t1;
499 do_div(delta, ms);
500 return delta;
501}
502
503/*
504 * This reads the current MSB of the PIT counter, and
505 * checks if we are running on sufficiently fast and
506 * non-virtualized hardware.
507 *
508 * Our expectations are:
509 *
510 * - the PIT is running at roughly 1.19MHz
511 *
512 * - each IO is going to take about 1us on real hardware,
513 * but we allow it to be much faster (by a factor of 10) or
514 * _slightly_ slower (ie we allow up to a 2us read+counter
515 * update - anything else implies a unacceptably slow CPU
516 * or PIT for the fast calibration to work.
517 *
518 * - with 256 PIT ticks to read the value, we have 214us to
519 * see the same MSB (and overhead like doing a single TSC
520 * read per MSB value etc).
521 *
522 * - We're doing 2 reads per loop (LSB, MSB), and we expect
523 * them each to take about a microsecond on real hardware.
524 * So we expect a count value of around 100. But we'll be
525 * generous, and accept anything over 50.
526 *
527 * - if the PIT is stuck, and we see *many* more reads, we
528 * return early (and the next caller of pit_expect_msb()
529 * then consider it a failure when they don't see the
530 * next expected value).
531 *
532 * These expectations mean that we know that we have seen the
533 * transition from one expected value to another with a fairly
534 * high accuracy, and we didn't miss any events. We can thus
535 * use the TSC value at the transitions to calculate a pretty
536 * good value for the TSC frequencty.
537 */
538static inline int pit_verify_msb(unsigned char val)
539{
540 /* Ignore LSB */
541 inb(0x42);
542 return inb(0x42) == val;
543}
544
545static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
546{
547 int count;
548 u64 tsc = 0, prev_tsc = 0;
549
550 for (count = 0; count < 50000; count++) {
551 if (!pit_verify_msb(val))
552 break;
553 prev_tsc = tsc;
554 tsc = get_cycles();
555 }
556 *deltap = get_cycles() - prev_tsc;
557 *tscp = tsc;
558
559 /*
560 * We require _some_ success, but the quality control
561 * will be based on the error terms on the TSC values.
562 */
563 return count > 5;
564}
565
566/*
567 * How many MSB values do we want to see? We aim for
568 * a maximum error rate of 500ppm (in practice the
569 * real error is much smaller), but refuse to spend
570 * more than 50ms on it.
571 */
572#define MAX_QUICK_PIT_MS 50
573#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
574
575static unsigned long quick_pit_calibrate(void)
576{
577 int i;
578 u64 tsc, delta;
579 unsigned long d1, d2;
580
581 /* Set the Gate high, disable speaker */
582 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
583
584 /*
585 * Counter 2, mode 0 (one-shot), binary count
586 *
587 * NOTE! Mode 2 decrements by two (and then the
588 * output is flipped each time, giving the same
589 * final output frequency as a decrement-by-one),
590 * so mode 0 is much better when looking at the
591 * individual counts.
592 */
593 outb(0xb0, 0x43);
594
595 /* Start at 0xffff */
596 outb(0xff, 0x42);
597 outb(0xff, 0x42);
598
599 /*
600 * The PIT starts counting at the next edge, so we
601 * need to delay for a microsecond. The easiest way
602 * to do that is to just read back the 16-bit counter
603 * once from the PIT.
604 */
605 pit_verify_msb(0);
606
607 if (pit_expect_msb(0xff, &tsc, &d1)) {
608 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
609 if (!pit_expect_msb(0xff-i, &delta, &d2))
610 break;
611
612 delta -= tsc;
613
614 /*
615 * Extrapolate the error and fail fast if the error will
616 * never be below 500 ppm.
617 */
618 if (i == 1 &&
619 d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11)
620 return 0;
621
622 /*
623 * Iterate until the error is less than 500 ppm
624 */
625 if (d1+d2 >= delta >> 11)
626 continue;
627
628 /*
629 * Check the PIT one more time to verify that
630 * all TSC reads were stable wrt the PIT.
631 *
632 * This also guarantees serialization of the
633 * last cycle read ('d2') in pit_expect_msb.
634 */
635 if (!pit_verify_msb(0xfe - i))
636 break;
637 goto success;
638 }
639 }
640 pr_info("Fast TSC calibration failed\n");
641 return 0;
642
643success:
644 /*
645 * Ok, if we get here, then we've seen the
646 * MSB of the PIT decrement 'i' times, and the
647 * error has shrunk to less than 500 ppm.
648 *
649 * As a result, we can depend on there not being
650 * any odd delays anywhere, and the TSC reads are
651 * reliable (within the error).
652 *
653 * kHz = ticks / time-in-seconds / 1000;
654 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
655 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
656 */
657 delta *= PIT_TICK_RATE;
658 do_div(delta, i*256*1000);
659 pr_info("Fast TSC calibration using PIT\n");
660 return delta;
661}
662
663/**
664 * native_calibrate_tsc
665 * Determine TSC frequency via CPUID, else return 0.
666 */
667unsigned long native_calibrate_tsc(void)
668{
669 unsigned int eax_denominator, ebx_numerator, ecx_hz, edx;
670 unsigned int crystal_khz;
671
672 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
673 return 0;
674
675 if (boot_cpu_data.cpuid_level < 0x15)
676 return 0;
677
678 eax_denominator = ebx_numerator = ecx_hz = edx = 0;
679
680 /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */
681 cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx);
682
683 if (ebx_numerator == 0 || eax_denominator == 0)
684 return 0;
685
686 crystal_khz = ecx_hz / 1000;
687
688 if (crystal_khz == 0) {
689 switch (boot_cpu_data.x86_model) {
690 case INTEL_FAM6_SKYLAKE_MOBILE:
691 case INTEL_FAM6_SKYLAKE_DESKTOP:
692 case INTEL_FAM6_KABYLAKE_MOBILE:
693 case INTEL_FAM6_KABYLAKE_DESKTOP:
694 crystal_khz = 24000; /* 24.0 MHz */
695 break;
696 case INTEL_FAM6_SKYLAKE_X:
697 case INTEL_FAM6_ATOM_DENVERTON:
698 crystal_khz = 25000; /* 25.0 MHz */
699 break;
700 case INTEL_FAM6_ATOM_GOLDMONT:
701 crystal_khz = 19200; /* 19.2 MHz */
702 break;
703 }
704 }
705
706 /*
707 * TSC frequency determined by CPUID is a "hardware reported"
708 * frequency and is the most accurate one so far we have. This
709 * is considered a known frequency.
710 */
711 setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
712
713 /*
714 * For Atom SoCs TSC is the only reliable clocksource.
715 * Mark TSC reliable so no watchdog on it.
716 */
717 if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
718 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
719
720 return crystal_khz * ebx_numerator / eax_denominator;
721}
722
723static unsigned long cpu_khz_from_cpuid(void)
724{
725 unsigned int eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx;
726
727 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
728 return 0;
729
730 if (boot_cpu_data.cpuid_level < 0x16)
731 return 0;
732
733 eax_base_mhz = ebx_max_mhz = ecx_bus_mhz = edx = 0;
734
735 cpuid(0x16, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx);
736
737 return eax_base_mhz * 1000;
738}
739
740/**
741 * native_calibrate_cpu - calibrate the cpu on boot
742 */
743unsigned long native_calibrate_cpu(void)
744{
745 u64 tsc1, tsc2, delta, ref1, ref2;
746 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
747 unsigned long flags, latch, ms, fast_calibrate;
748 int hpet = is_hpet_enabled(), i, loopmin;
749
750 fast_calibrate = cpu_khz_from_cpuid();
751 if (fast_calibrate)
752 return fast_calibrate;
753
754 fast_calibrate = cpu_khz_from_msr();
755 if (fast_calibrate)
756 return fast_calibrate;
757
758 local_irq_save(flags);
759 fast_calibrate = quick_pit_calibrate();
760 local_irq_restore(flags);
761 if (fast_calibrate)
762 return fast_calibrate;
763
764 /*
765 * Run 5 calibration loops to get the lowest frequency value
766 * (the best estimate). We use two different calibration modes
767 * here:
768 *
769 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
770 * load a timeout of 50ms. We read the time right after we
771 * started the timer and wait until the PIT count down reaches
772 * zero. In each wait loop iteration we read the TSC and check
773 * the delta to the previous read. We keep track of the min
774 * and max values of that delta. The delta is mostly defined
775 * by the IO time of the PIT access, so we can detect when a
776 * SMI/SMM disturbance happened between the two reads. If the
777 * maximum time is significantly larger than the minimum time,
778 * then we discard the result and have another try.
779 *
780 * 2) Reference counter. If available we use the HPET or the
781 * PMTIMER as a reference to check the sanity of that value.
782 * We use separate TSC readouts and check inside of the
783 * reference read for a SMI/SMM disturbance. We dicard
784 * disturbed values here as well. We do that around the PIT
785 * calibration delay loop as we have to wait for a certain
786 * amount of time anyway.
787 */
788
789 /* Preset PIT loop values */
790 latch = CAL_LATCH;
791 ms = CAL_MS;
792 loopmin = CAL_PIT_LOOPS;
793
794 for (i = 0; i < 3; i++) {
795 unsigned long tsc_pit_khz;
796
797 /*
798 * Read the start value and the reference count of
799 * hpet/pmtimer when available. Then do the PIT
800 * calibration, which will take at least 50ms, and
801 * read the end value.
802 */
803 local_irq_save(flags);
804 tsc1 = tsc_read_refs(&ref1, hpet);
805 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
806 tsc2 = tsc_read_refs(&ref2, hpet);
807 local_irq_restore(flags);
808
809 /* Pick the lowest PIT TSC calibration so far */
810 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
811
812 /* hpet or pmtimer available ? */
813 if (ref1 == ref2)
814 continue;
815
816 /* Check, whether the sampling was disturbed by an SMI */
817 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
818 continue;
819
820 tsc2 = (tsc2 - tsc1) * 1000000LL;
821 if (hpet)
822 tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
823 else
824 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
825
826 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
827
828 /* Check the reference deviation */
829 delta = ((u64) tsc_pit_min) * 100;
830 do_div(delta, tsc_ref_min);
831
832 /*
833 * If both calibration results are inside a 10% window
834 * then we can be sure, that the calibration
835 * succeeded. We break out of the loop right away. We
836 * use the reference value, as it is more precise.
837 */
838 if (delta >= 90 && delta <= 110) {
839 pr_info("PIT calibration matches %s. %d loops\n",
840 hpet ? "HPET" : "PMTIMER", i + 1);
841 return tsc_ref_min;
842 }
843
844 /*
845 * Check whether PIT failed more than once. This
846 * happens in virtualized environments. We need to
847 * give the virtual PC a slightly longer timeframe for
848 * the HPET/PMTIMER to make the result precise.
849 */
850 if (i == 1 && tsc_pit_min == ULONG_MAX) {
851 latch = CAL2_LATCH;
852 ms = CAL2_MS;
853 loopmin = CAL2_PIT_LOOPS;
854 }
855 }
856
857 /*
858 * Now check the results.
859 */
860 if (tsc_pit_min == ULONG_MAX) {
861 /* PIT gave no useful value */
862 pr_warn("Unable to calibrate against PIT\n");
863
864 /* We don't have an alternative source, disable TSC */
865 if (!hpet && !ref1 && !ref2) {
866 pr_notice("No reference (HPET/PMTIMER) available\n");
867 return 0;
868 }
869
870 /* The alternative source failed as well, disable TSC */
871 if (tsc_ref_min == ULONG_MAX) {
872 pr_warn("HPET/PMTIMER calibration failed\n");
873 return 0;
874 }
875
876 /* Use the alternative source */
877 pr_info("using %s reference calibration\n",
878 hpet ? "HPET" : "PMTIMER");
879
880 return tsc_ref_min;
881 }
882
883 /* We don't have an alternative source, use the PIT calibration value */
884 if (!hpet && !ref1 && !ref2) {
885 pr_info("Using PIT calibration value\n");
886 return tsc_pit_min;
887 }
888
889 /* The alternative source failed, use the PIT calibration value */
890 if (tsc_ref_min == ULONG_MAX) {
891 pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n");
892 return tsc_pit_min;
893 }
894
895 /*
896 * The calibration values differ too much. In doubt, we use
897 * the PIT value as we know that there are PMTIMERs around
898 * running at double speed. At least we let the user know:
899 */
900 pr_warn("PIT calibration deviates from %s: %lu %lu\n",
901 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
902 pr_info("Using PIT calibration value\n");
903 return tsc_pit_min;
904}
905
906int recalibrate_cpu_khz(void)
907{
908#ifndef CONFIG_SMP
909 unsigned long cpu_khz_old = cpu_khz;
910
911 if (!boot_cpu_has(X86_FEATURE_TSC))
912 return -ENODEV;
913
914 cpu_khz = x86_platform.calibrate_cpu();
915 tsc_khz = x86_platform.calibrate_tsc();
916 if (tsc_khz == 0)
917 tsc_khz = cpu_khz;
918 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
919 cpu_khz = tsc_khz;
920 cpu_data(0).loops_per_jiffy = cpufreq_scale(cpu_data(0).loops_per_jiffy,
921 cpu_khz_old, cpu_khz);
922
923 return 0;
924#else
925 return -ENODEV;
926#endif
927}
928
929EXPORT_SYMBOL(recalibrate_cpu_khz);
930
931
932static unsigned long long cyc2ns_suspend;
933
934void tsc_save_sched_clock_state(void)
935{
936 if (!sched_clock_stable())
937 return;
938
939 cyc2ns_suspend = sched_clock();
940}
941
942/*
943 * Even on processors with invariant TSC, TSC gets reset in some the
944 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
945 * arbitrary value (still sync'd across cpu's) during resume from such sleep
946 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
947 * that sched_clock() continues from the point where it was left off during
948 * suspend.
949 */
950void tsc_restore_sched_clock_state(void)
951{
952 unsigned long long offset;
953 unsigned long flags;
954 int cpu;
955
956 if (!sched_clock_stable())
957 return;
958
959 local_irq_save(flags);
960
961 /*
962 * We're coming out of suspend, there's no concurrency yet; don't
963 * bother being nice about the RCU stuff, just write to both
964 * data fields.
965 */
966
967 this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0);
968 this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0);
969
970 offset = cyc2ns_suspend - sched_clock();
971
972 for_each_possible_cpu(cpu) {
973 per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset;
974 per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset;
975 }
976
977 local_irq_restore(flags);
978}
979
980#ifdef CONFIG_CPU_FREQ
981
982/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
983 * changes.
984 *
985 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
986 * not that important because current Opteron setups do not support
987 * scaling on SMP anyroads.
988 *
989 * Should fix up last_tsc too. Currently gettimeofday in the
990 * first tick after the change will be slightly wrong.
991 */
992
993static unsigned int ref_freq;
994static unsigned long loops_per_jiffy_ref;
995static unsigned long tsc_khz_ref;
996
997static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
998 void *data)
999{
1000 struct cpufreq_freqs *freq = data;
1001 unsigned long *lpj;
1002
1003 lpj = &boot_cpu_data.loops_per_jiffy;
1004#ifdef CONFIG_SMP
1005 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
1006 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
1007#endif
1008
1009 if (!ref_freq) {
1010 ref_freq = freq->old;
1011 loops_per_jiffy_ref = *lpj;
1012 tsc_khz_ref = tsc_khz;
1013 }
1014 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
1015 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
1016 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
1017
1018 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
1019 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
1020 mark_tsc_unstable("cpufreq changes");
1021
1022 set_cyc2ns_scale(tsc_khz, freq->cpu);
1023 }
1024
1025 return 0;
1026}
1027
1028static struct notifier_block time_cpufreq_notifier_block = {
1029 .notifier_call = time_cpufreq_notifier
1030};
1031
1032static int __init cpufreq_register_tsc_scaling(void)
1033{
1034 if (!boot_cpu_has(X86_FEATURE_TSC))
1035 return 0;
1036 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1037 return 0;
1038 cpufreq_register_notifier(&time_cpufreq_notifier_block,
1039 CPUFREQ_TRANSITION_NOTIFIER);
1040 return 0;
1041}
1042
1043core_initcall(cpufreq_register_tsc_scaling);
1044
1045#endif /* CONFIG_CPU_FREQ */
1046
1047#define ART_CPUID_LEAF (0x15)
1048#define ART_MIN_DENOMINATOR (1)
1049
1050
1051/*
1052 * If ART is present detect the numerator:denominator to convert to TSC
1053 */
1054static void detect_art(void)
1055{
1056 unsigned int unused[2];
1057
1058 if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF)
1059 return;
1060
1061 /* Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required */
1062 if (boot_cpu_has(X86_FEATURE_HYPERVISOR) ||
1063 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) ||
1064 !boot_cpu_has(X86_FEATURE_TSC_ADJUST))
1065 return;
1066
1067 cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator,
1068 &art_to_tsc_numerator, unused, unused+1);
1069
1070 if (art_to_tsc_denominator < ART_MIN_DENOMINATOR)
1071 return;
1072
1073 rdmsrl(MSR_IA32_TSC_ADJUST, art_to_tsc_offset);
1074
1075 /* Make this sticky over multiple CPU init calls */
1076 setup_force_cpu_cap(X86_FEATURE_ART);
1077}
1078
1079
1080/* clocksource code */
1081
1082static struct clocksource clocksource_tsc;
1083
1084static void tsc_resume(struct clocksource *cs)
1085{
1086 tsc_verify_tsc_adjust(true);
1087}
1088
1089/*
1090 * We used to compare the TSC to the cycle_last value in the clocksource
1091 * structure to avoid a nasty time-warp. This can be observed in a
1092 * very small window right after one CPU updated cycle_last under
1093 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
1094 * is smaller than the cycle_last reference value due to a TSC which
1095 * is slighty behind. This delta is nowhere else observable, but in
1096 * that case it results in a forward time jump in the range of hours
1097 * due to the unsigned delta calculation of the time keeping core
1098 * code, which is necessary to support wrapping clocksources like pm
1099 * timer.
1100 *
1101 * This sanity check is now done in the core timekeeping code.
1102 * checking the result of read_tsc() - cycle_last for being negative.
1103 * That works because CLOCKSOURCE_MASK(64) does not mask out any bit.
1104 */
1105static u64 read_tsc(struct clocksource *cs)
1106{
1107 return (u64)rdtsc_ordered();
1108}
1109
1110/*
1111 * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc()
1112 */
1113static struct clocksource clocksource_tsc = {
1114 .name = "tsc",
1115 .rating = 300,
1116 .read = read_tsc,
1117 .mask = CLOCKSOURCE_MASK(64),
1118 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
1119 CLOCK_SOURCE_MUST_VERIFY,
1120 .archdata = { .vclock_mode = VCLOCK_TSC },
1121 .resume = tsc_resume,
1122};
1123
1124void mark_tsc_unstable(char *reason)
1125{
1126 if (!tsc_unstable) {
1127 tsc_unstable = 1;
1128 clear_sched_clock_stable();
1129 disable_sched_clock_irqtime();
1130 pr_info("Marking TSC unstable due to %s\n", reason);
1131 /* Change only the rating, when not registered */
1132 if (clocksource_tsc.mult)
1133 clocksource_mark_unstable(&clocksource_tsc);
1134 else {
1135 clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
1136 clocksource_tsc.rating = 0;
1137 }
1138 }
1139}
1140
1141EXPORT_SYMBOL_GPL(mark_tsc_unstable);
1142
1143static void __init check_system_tsc_reliable(void)
1144{
1145#if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC)
1146 if (is_geode_lx()) {
1147 /* RTSC counts during suspend */
1148#define RTSC_SUSP 0x100
1149 unsigned long res_low, res_high;
1150
1151 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
1152 /* Geode_LX - the OLPC CPU has a very reliable TSC */
1153 if (res_low & RTSC_SUSP)
1154 tsc_clocksource_reliable = 1;
1155 }
1156#endif
1157 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
1158 tsc_clocksource_reliable = 1;
1159}
1160
1161/*
1162 * Make an educated guess if the TSC is trustworthy and synchronized
1163 * over all CPUs.
1164 */
1165int unsynchronized_tsc(void)
1166{
1167 if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_unstable)
1168 return 1;
1169
1170#ifdef CONFIG_SMP
1171 if (apic_is_clustered_box())
1172 return 1;
1173#endif
1174
1175 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1176 return 0;
1177
1178 if (tsc_clocksource_reliable)
1179 return 0;
1180 /*
1181 * Intel systems are normally all synchronized.
1182 * Exceptions must mark TSC as unstable:
1183 */
1184 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1185 /* assume multi socket systems are not synchronized: */
1186 if (num_possible_cpus() > 1)
1187 return 1;
1188 }
1189
1190 return 0;
1191}
1192
1193/*
1194 * Convert ART to TSC given numerator/denominator found in detect_art()
1195 */
1196struct system_counterval_t convert_art_to_tsc(u64 art)
1197{
1198 u64 tmp, res, rem;
1199
1200 rem = do_div(art, art_to_tsc_denominator);
1201
1202 res = art * art_to_tsc_numerator;
1203 tmp = rem * art_to_tsc_numerator;
1204
1205 do_div(tmp, art_to_tsc_denominator);
1206 res += tmp + art_to_tsc_offset;
1207
1208 return (struct system_counterval_t) {.cs = art_related_clocksource,
1209 .cycles = res};
1210}
1211EXPORT_SYMBOL(convert_art_to_tsc);
1212
1213static void tsc_refine_calibration_work(struct work_struct *work);
1214static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
1215/**
1216 * tsc_refine_calibration_work - Further refine tsc freq calibration
1217 * @work - ignored.
1218 *
1219 * This functions uses delayed work over a period of a
1220 * second to further refine the TSC freq value. Since this is
1221 * timer based, instead of loop based, we don't block the boot
1222 * process while this longer calibration is done.
1223 *
1224 * If there are any calibration anomalies (too many SMIs, etc),
1225 * or the refined calibration is off by 1% of the fast early
1226 * calibration, we throw out the new calibration and use the
1227 * early calibration.
1228 */
1229static void tsc_refine_calibration_work(struct work_struct *work)
1230{
1231 static u64 tsc_start = -1, ref_start;
1232 static int hpet;
1233 u64 tsc_stop, ref_stop, delta;
1234 unsigned long freq;
1235
1236 /* Don't bother refining TSC on unstable systems */
1237 if (check_tsc_unstable())
1238 goto out;
1239
1240 /*
1241 * Since the work is started early in boot, we may be
1242 * delayed the first time we expire. So set the workqueue
1243 * again once we know timers are working.
1244 */
1245 if (tsc_start == -1) {
1246 /*
1247 * Only set hpet once, to avoid mixing hardware
1248 * if the hpet becomes enabled later.
1249 */
1250 hpet = is_hpet_enabled();
1251 schedule_delayed_work(&tsc_irqwork, HZ);
1252 tsc_start = tsc_read_refs(&ref_start, hpet);
1253 return;
1254 }
1255
1256 tsc_stop = tsc_read_refs(&ref_stop, hpet);
1257
1258 /* hpet or pmtimer available ? */
1259 if (ref_start == ref_stop)
1260 goto out;
1261
1262 /* Check, whether the sampling was disturbed by an SMI */
1263 if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
1264 goto out;
1265
1266 delta = tsc_stop - tsc_start;
1267 delta *= 1000000LL;
1268 if (hpet)
1269 freq = calc_hpet_ref(delta, ref_start, ref_stop);
1270 else
1271 freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
1272
1273 /* Make sure we're within 1% */
1274 if (abs(tsc_khz - freq) > tsc_khz/100)
1275 goto out;
1276
1277 tsc_khz = freq;
1278 pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",
1279 (unsigned long)tsc_khz / 1000,
1280 (unsigned long)tsc_khz % 1000);
1281
1282 /* Inform the TSC deadline clockevent devices about the recalibration */
1283 lapic_update_tsc_freq();
1284
1285out:
1286 if (boot_cpu_has(X86_FEATURE_ART))
1287 art_related_clocksource = &clocksource_tsc;
1288 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1289}
1290
1291
1292static int __init init_tsc_clocksource(void)
1293{
1294 if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_disabled > 0 || !tsc_khz)
1295 return 0;
1296
1297 if (tsc_clocksource_reliable)
1298 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
1299 /* lower the rating if we already know its unstable: */
1300 if (check_tsc_unstable()) {
1301 clocksource_tsc.rating = 0;
1302 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
1303 }
1304
1305 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3))
1306 clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1307
1308 /*
1309 * When TSC frequency is known (retrieved via MSR or CPUID), we skip
1310 * the refined calibration and directly register it as a clocksource.
1311 */
1312 if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) {
1313 if (boot_cpu_has(X86_FEATURE_ART))
1314 art_related_clocksource = &clocksource_tsc;
1315 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1316 return 0;
1317 }
1318
1319 schedule_delayed_work(&tsc_irqwork, 0);
1320 return 0;
1321}
1322/*
1323 * We use device_initcall here, to ensure we run after the hpet
1324 * is fully initialized, which may occur at fs_initcall time.
1325 */
1326device_initcall(init_tsc_clocksource);
1327
1328void __init tsc_init(void)
1329{
1330 u64 lpj;
1331 int cpu;
1332
1333 if (!boot_cpu_has(X86_FEATURE_TSC)) {
1334 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1335 return;
1336 }
1337
1338 cpu_khz = x86_platform.calibrate_cpu();
1339 tsc_khz = x86_platform.calibrate_tsc();
1340
1341 /*
1342 * Trust non-zero tsc_khz as authorative,
1343 * and use it to sanity check cpu_khz,
1344 * which will be off if system timer is off.
1345 */
1346 if (tsc_khz == 0)
1347 tsc_khz = cpu_khz;
1348 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
1349 cpu_khz = tsc_khz;
1350
1351 if (!tsc_khz) {
1352 mark_tsc_unstable("could not calculate TSC khz");
1353 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1354 return;
1355 }
1356
1357 pr_info("Detected %lu.%03lu MHz processor\n",
1358 (unsigned long)cpu_khz / 1000,
1359 (unsigned long)cpu_khz % 1000);
1360
1361 /* Sanitize TSC ADJUST before cyc2ns gets initialized */
1362 tsc_store_and_check_tsc_adjust(true);
1363
1364 /*
1365 * Secondary CPUs do not run through tsc_init(), so set up
1366 * all the scale factors for all CPUs, assuming the same
1367 * speed as the bootup CPU. (cpufreq notifiers will fix this
1368 * up if their speed diverges)
1369 */
1370 for_each_possible_cpu(cpu) {
1371 cyc2ns_init(cpu);
1372 set_cyc2ns_scale(tsc_khz, cpu);
1373 }
1374
1375 if (tsc_disabled > 0)
1376 return;
1377
1378 /* now allow native_sched_clock() to use rdtsc */
1379
1380 tsc_disabled = 0;
1381 static_branch_enable(&__use_tsc);
1382
1383 if (!no_sched_irq_time)
1384 enable_sched_clock_irqtime();
1385
1386 lpj = ((u64)tsc_khz * 1000);
1387 do_div(lpj, HZ);
1388 lpj_fine = lpj;
1389
1390 use_tsc_delay();
1391
1392 if (unsynchronized_tsc())
1393 mark_tsc_unstable("TSCs unsynchronized");
1394
1395 check_system_tsc_reliable();
1396
1397 detect_art();
1398}
1399
1400#ifdef CONFIG_SMP
1401/*
1402 * If we have a constant TSC and are using the TSC for the delay loop,
1403 * we can skip clock calibration if another cpu in the same socket has already
1404 * been calibrated. This assumes that CONSTANT_TSC applies to all
1405 * cpus in the socket - this should be a safe assumption.
1406 */
1407unsigned long calibrate_delay_is_known(void)
1408{
1409 int sibling, cpu = smp_processor_id();
1410 struct cpumask *mask = topology_core_cpumask(cpu);
1411
1412 if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC))
1413 return 0;
1414
1415 if (!mask)
1416 return 0;
1417
1418 sibling = cpumask_any_but(mask, cpu);
1419 if (sibling < nr_cpu_ids)
1420 return cpu_data(sibling).loops_per_jiffy;
1421 return 0;
1422}
1423#endif