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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11#include <linux/module.h>
12#include <linux/ioport.h>
13#include <linux/init.h>
14#include <linux/console.h>
15#include <linux/sysrq.h>
16#include <linux/platform_device.h>
17#include <linux/tty.h>
18#include <linux/tty_flip.h>
19#include <linux/serial_core.h>
20#include <linux/serial.h>
21#include <linux/clk.h>
22#include <linux/delay.h>
23#include <linux/ktime.h>
24#include <linux/pinctrl/consumer.h>
25#include <linux/rational.h>
26#include <linux/slab.h>
27#include <linux/of.h>
28#include <linux/of_device.h>
29#include <linux/io.h>
30#include <linux/dma-mapping.h>
31
32#include <asm/irq.h>
33#include <linux/platform_data/dma-imx.h>
34
35#include "serial_mctrl_gpio.h"
36
37/* Register definitions */
38#define URXD0 0x0 /* Receiver Register */
39#define URTX0 0x40 /* Transmitter Register */
40#define UCR1 0x80 /* Control Register 1 */
41#define UCR2 0x84 /* Control Register 2 */
42#define UCR3 0x88 /* Control Register 3 */
43#define UCR4 0x8c /* Control Register 4 */
44#define UFCR 0x90 /* FIFO Control Register */
45#define USR1 0x94 /* Status Register 1 */
46#define USR2 0x98 /* Status Register 2 */
47#define UESC 0x9c /* Escape Character Register */
48#define UTIM 0xa0 /* Escape Timer Register */
49#define UBIR 0xa4 /* BRM Incremental Register */
50#define UBMR 0xa8 /* BRM Modulator Register */
51#define UBRC 0xac /* Baud Rate Count Register */
52#define IMX21_ONEMS 0xb0 /* One Millisecond register */
53#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
54#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
55
56/* UART Control Register Bit Fields.*/
57#define URXD_DUMMY_READ (1<<16)
58#define URXD_CHARRDY (1<<15)
59#define URXD_ERR (1<<14)
60#define URXD_OVRRUN (1<<13)
61#define URXD_FRMERR (1<<12)
62#define URXD_BRK (1<<11)
63#define URXD_PRERR (1<<10)
64#define URXD_RX_DATA (0xFF<<0)
65#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
66#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
67#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
68#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
69#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
70#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
71#define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
72#define UCR1_IREN (1<<7) /* Infrared interface enable */
73#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
74#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
75#define UCR1_SNDBRK (1<<4) /* Send break */
76#define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
77#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
78#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
79#define UCR1_DOZE (1<<1) /* Doze */
80#define UCR1_UARTEN (1<<0) /* UART enabled */
81#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
82#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
83#define UCR2_CTSC (1<<13) /* CTS pin control */
84#define UCR2_CTS (1<<12) /* Clear to send */
85#define UCR2_ESCEN (1<<11) /* Escape enable */
86#define UCR2_PREN (1<<8) /* Parity enable */
87#define UCR2_PROE (1<<7) /* Parity odd/even */
88#define UCR2_STPB (1<<6) /* Stop */
89#define UCR2_WS (1<<5) /* Word size */
90#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
91#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
92#define UCR2_TXEN (1<<2) /* Transmitter enabled */
93#define UCR2_RXEN (1<<1) /* Receiver enabled */
94#define UCR2_SRST (1<<0) /* SW reset */
95#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
96#define UCR3_PARERREN (1<<12) /* Parity enable */
97#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
98#define UCR3_DSR (1<<10) /* Data set ready */
99#define UCR3_DCD (1<<9) /* Data carrier detect */
100#define UCR3_RI (1<<8) /* Ring indicator */
101#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
102#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
103#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
104#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
105#define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
106#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
107#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
108#define UCR3_BPEN (1<<0) /* Preset registers enable */
109#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
110#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
111#define UCR4_INVR (1<<9) /* Inverted infrared reception */
112#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
113#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
114#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
115#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
116#define UCR4_IRSC (1<<5) /* IR special case */
117#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
118#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
119#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
120#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
121#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
122#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
123#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
124#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
125#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
126#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
127#define USR1_RTSS (1<<14) /* RTS pin status */
128#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
129#define USR1_RTSD (1<<12) /* RTS delta */
130#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
131#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
132#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
133#define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
134#define USR1_DTRD (1<<7) /* DTR Delta */
135#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
136#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
137#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
138#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
139#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
140#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
141#define USR2_IDLE (1<<12) /* Idle condition */
142#define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
143#define USR2_RIIN (1<<9) /* Ring Indicator Input */
144#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
145#define USR2_WAKE (1<<7) /* Wake */
146#define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
147#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
148#define USR2_TXDC (1<<3) /* Transmitter complete */
149#define USR2_BRCD (1<<2) /* Break condition */
150#define USR2_ORE (1<<1) /* Overrun error */
151#define USR2_RDR (1<<0) /* Recv data ready */
152#define UTS_FRCPERR (1<<13) /* Force parity error */
153#define UTS_LOOP (1<<12) /* Loop tx and rx */
154#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
155#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
156#define UTS_TXFULL (1<<4) /* TxFIFO full */
157#define UTS_RXFULL (1<<3) /* RxFIFO full */
158#define UTS_SOFTRST (1<<0) /* Software reset */
159
160/* We've been assigned a range on the "Low-density serial ports" major */
161#define SERIAL_IMX_MAJOR 207
162#define MINOR_START 16
163#define DEV_NAME "ttymxc"
164
165/*
166 * This determines how often we check the modem status signals
167 * for any change. They generally aren't connected to an IRQ
168 * so we have to poll them. We also check immediately before
169 * filling the TX fifo incase CTS has been dropped.
170 */
171#define MCTRL_TIMEOUT (250*HZ/1000)
172
173#define DRIVER_NAME "IMX-uart"
174
175#define UART_NR 8
176
177/* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
178enum imx_uart_type {
179 IMX1_UART,
180 IMX21_UART,
181 IMX53_UART,
182 IMX6Q_UART,
183};
184
185/* device type dependent stuff */
186struct imx_uart_data {
187 unsigned uts_reg;
188 enum imx_uart_type devtype;
189};
190
191enum imx_tx_state {
192 OFF,
193 WAIT_AFTER_RTS,
194 SEND,
195 WAIT_AFTER_SEND,
196};
197
198struct imx_port {
199 struct uart_port port;
200 struct timer_list timer;
201 unsigned int old_status;
202 unsigned int have_rtscts:1;
203 unsigned int have_rtsgpio:1;
204 unsigned int dte_mode:1;
205 unsigned int inverted_tx:1;
206 unsigned int inverted_rx:1;
207 struct clk *clk_ipg;
208 struct clk *clk_per;
209 const struct imx_uart_data *devdata;
210
211 struct mctrl_gpios *gpios;
212
213 /* shadow registers */
214 unsigned int ucr1;
215 unsigned int ucr2;
216 unsigned int ucr3;
217 unsigned int ucr4;
218 unsigned int ufcr;
219
220 /* DMA fields */
221 unsigned int dma_is_enabled:1;
222 unsigned int dma_is_rxing:1;
223 unsigned int dma_is_txing:1;
224 struct dma_chan *dma_chan_rx, *dma_chan_tx;
225 struct scatterlist rx_sgl, tx_sgl[2];
226 void *rx_buf;
227 struct circ_buf rx_ring;
228 unsigned int rx_buf_size;
229 unsigned int rx_period_length;
230 unsigned int rx_periods;
231 dma_cookie_t rx_cookie;
232 unsigned int tx_bytes;
233 unsigned int dma_tx_nents;
234 unsigned int saved_reg[10];
235 bool context_saved;
236
237 enum imx_tx_state tx_state;
238 struct hrtimer trigger_start_tx;
239 struct hrtimer trigger_stop_tx;
240};
241
242struct imx_port_ucrs {
243 unsigned int ucr1;
244 unsigned int ucr2;
245 unsigned int ucr3;
246};
247
248static struct imx_uart_data imx_uart_devdata[] = {
249 [IMX1_UART] = {
250 .uts_reg = IMX1_UTS,
251 .devtype = IMX1_UART,
252 },
253 [IMX21_UART] = {
254 .uts_reg = IMX21_UTS,
255 .devtype = IMX21_UART,
256 },
257 [IMX53_UART] = {
258 .uts_reg = IMX21_UTS,
259 .devtype = IMX53_UART,
260 },
261 [IMX6Q_UART] = {
262 .uts_reg = IMX21_UTS,
263 .devtype = IMX6Q_UART,
264 },
265};
266
267static const struct of_device_id imx_uart_dt_ids[] = {
268 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
269 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
270 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
271 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
272 { /* sentinel */ }
273};
274MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
275
276static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
277{
278 switch (offset) {
279 case UCR1:
280 sport->ucr1 = val;
281 break;
282 case UCR2:
283 sport->ucr2 = val;
284 break;
285 case UCR3:
286 sport->ucr3 = val;
287 break;
288 case UCR4:
289 sport->ucr4 = val;
290 break;
291 case UFCR:
292 sport->ufcr = val;
293 break;
294 default:
295 break;
296 }
297 writel(val, sport->port.membase + offset);
298}
299
300static u32 imx_uart_readl(struct imx_port *sport, u32 offset)
301{
302 switch (offset) {
303 case UCR1:
304 return sport->ucr1;
305 break;
306 case UCR2:
307 /*
308 * UCR2_SRST is the only bit in the cached registers that might
309 * differ from the value that was last written. As it only
310 * automatically becomes one after being cleared, reread
311 * conditionally.
312 */
313 if (!(sport->ucr2 & UCR2_SRST))
314 sport->ucr2 = readl(sport->port.membase + offset);
315 return sport->ucr2;
316 break;
317 case UCR3:
318 return sport->ucr3;
319 break;
320 case UCR4:
321 return sport->ucr4;
322 break;
323 case UFCR:
324 return sport->ufcr;
325 break;
326 default:
327 return readl(sport->port.membase + offset);
328 }
329}
330
331static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
332{
333 return sport->devdata->uts_reg;
334}
335
336static inline int imx_uart_is_imx1(struct imx_port *sport)
337{
338 return sport->devdata->devtype == IMX1_UART;
339}
340
341static inline int imx_uart_is_imx21(struct imx_port *sport)
342{
343 return sport->devdata->devtype == IMX21_UART;
344}
345
346static inline int imx_uart_is_imx53(struct imx_port *sport)
347{
348 return sport->devdata->devtype == IMX53_UART;
349}
350
351static inline int imx_uart_is_imx6q(struct imx_port *sport)
352{
353 return sport->devdata->devtype == IMX6Q_UART;
354}
355/*
356 * Save and restore functions for UCR1, UCR2 and UCR3 registers
357 */
358#if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
359static void imx_uart_ucrs_save(struct imx_port *sport,
360 struct imx_port_ucrs *ucr)
361{
362 /* save control registers */
363 ucr->ucr1 = imx_uart_readl(sport, UCR1);
364 ucr->ucr2 = imx_uart_readl(sport, UCR2);
365 ucr->ucr3 = imx_uart_readl(sport, UCR3);
366}
367
368static void imx_uart_ucrs_restore(struct imx_port *sport,
369 struct imx_port_ucrs *ucr)
370{
371 /* restore control registers */
372 imx_uart_writel(sport, ucr->ucr1, UCR1);
373 imx_uart_writel(sport, ucr->ucr2, UCR2);
374 imx_uart_writel(sport, ucr->ucr3, UCR3);
375}
376#endif
377
378/* called with port.lock taken and irqs caller dependent */
379static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
380{
381 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
382
383 sport->port.mctrl |= TIOCM_RTS;
384 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
385}
386
387/* called with port.lock taken and irqs caller dependent */
388static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
389{
390 *ucr2 &= ~UCR2_CTSC;
391 *ucr2 |= UCR2_CTS;
392
393 sport->port.mctrl &= ~TIOCM_RTS;
394 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
395}
396
397static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
398{
399 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
400}
401
402/* called with port.lock taken and irqs off */
403static void imx_uart_start_rx(struct uart_port *port)
404{
405 struct imx_port *sport = (struct imx_port *)port;
406 unsigned int ucr1, ucr2;
407
408 ucr1 = imx_uart_readl(sport, UCR1);
409 ucr2 = imx_uart_readl(sport, UCR2);
410
411 ucr2 |= UCR2_RXEN;
412
413 if (sport->dma_is_enabled) {
414 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
415 } else {
416 ucr1 |= UCR1_RRDYEN;
417 ucr2 |= UCR2_ATEN;
418 }
419
420 /* Write UCR2 first as it includes RXEN */
421 imx_uart_writel(sport, ucr2, UCR2);
422 imx_uart_writel(sport, ucr1, UCR1);
423}
424
425/* called with port.lock taken and irqs off */
426static void imx_uart_stop_tx(struct uart_port *port)
427{
428 struct imx_port *sport = (struct imx_port *)port;
429 u32 ucr1, ucr4, usr2;
430
431 if (sport->tx_state == OFF)
432 return;
433
434 /*
435 * We are maybe in the SMP context, so if the DMA TX thread is running
436 * on other cpu, we have to wait for it to finish.
437 */
438 if (sport->dma_is_txing)
439 return;
440
441 ucr1 = imx_uart_readl(sport, UCR1);
442 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
443
444 usr2 = imx_uart_readl(sport, USR2);
445 if (!(usr2 & USR2_TXDC)) {
446 /* The shifter is still busy, so retry once TC triggers */
447 return;
448 }
449
450 ucr4 = imx_uart_readl(sport, UCR4);
451 ucr4 &= ~UCR4_TCEN;
452 imx_uart_writel(sport, ucr4, UCR4);
453
454 /* in rs485 mode disable transmitter */
455 if (port->rs485.flags & SER_RS485_ENABLED) {
456 if (sport->tx_state == SEND) {
457 sport->tx_state = WAIT_AFTER_SEND;
458 start_hrtimer_ms(&sport->trigger_stop_tx,
459 port->rs485.delay_rts_after_send);
460 return;
461 }
462
463 if (sport->tx_state == WAIT_AFTER_RTS ||
464 sport->tx_state == WAIT_AFTER_SEND) {
465 u32 ucr2;
466
467 hrtimer_try_to_cancel(&sport->trigger_start_tx);
468
469 ucr2 = imx_uart_readl(sport, UCR2);
470 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
471 imx_uart_rts_active(sport, &ucr2);
472 else
473 imx_uart_rts_inactive(sport, &ucr2);
474 imx_uart_writel(sport, ucr2, UCR2);
475
476 imx_uart_start_rx(port);
477
478 sport->tx_state = OFF;
479 }
480 } else {
481 sport->tx_state = OFF;
482 }
483}
484
485/* called with port.lock taken and irqs off */
486static void imx_uart_stop_rx(struct uart_port *port)
487{
488 struct imx_port *sport = (struct imx_port *)port;
489 u32 ucr1, ucr2;
490
491 ucr1 = imx_uart_readl(sport, UCR1);
492 ucr2 = imx_uart_readl(sport, UCR2);
493
494 if (sport->dma_is_enabled) {
495 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
496 } else {
497 ucr1 &= ~UCR1_RRDYEN;
498 ucr2 &= ~UCR2_ATEN;
499 }
500 imx_uart_writel(sport, ucr1, UCR1);
501
502 ucr2 &= ~UCR2_RXEN;
503 imx_uart_writel(sport, ucr2, UCR2);
504}
505
506/* called with port.lock taken and irqs off */
507static void imx_uart_enable_ms(struct uart_port *port)
508{
509 struct imx_port *sport = (struct imx_port *)port;
510
511 mod_timer(&sport->timer, jiffies);
512
513 mctrl_gpio_enable_ms(sport->gpios);
514}
515
516static void imx_uart_dma_tx(struct imx_port *sport);
517
518/* called with port.lock taken and irqs off */
519static inline void imx_uart_transmit_buffer(struct imx_port *sport)
520{
521 struct circ_buf *xmit = &sport->port.state->xmit;
522
523 if (sport->port.x_char) {
524 /* Send next char */
525 imx_uart_writel(sport, sport->port.x_char, URTX0);
526 sport->port.icount.tx++;
527 sport->port.x_char = 0;
528 return;
529 }
530
531 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
532 imx_uart_stop_tx(&sport->port);
533 return;
534 }
535
536 if (sport->dma_is_enabled) {
537 u32 ucr1;
538 /*
539 * We've just sent a X-char Ensure the TX DMA is enabled
540 * and the TX IRQ is disabled.
541 **/
542 ucr1 = imx_uart_readl(sport, UCR1);
543 ucr1 &= ~UCR1_TRDYEN;
544 if (sport->dma_is_txing) {
545 ucr1 |= UCR1_TXDMAEN;
546 imx_uart_writel(sport, ucr1, UCR1);
547 } else {
548 imx_uart_writel(sport, ucr1, UCR1);
549 imx_uart_dma_tx(sport);
550 }
551
552 return;
553 }
554
555 while (!uart_circ_empty(xmit) &&
556 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
557 /* send xmit->buf[xmit->tail]
558 * out the port here */
559 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
560 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
561 sport->port.icount.tx++;
562 }
563
564 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
565 uart_write_wakeup(&sport->port);
566
567 if (uart_circ_empty(xmit))
568 imx_uart_stop_tx(&sport->port);
569}
570
571static void imx_uart_dma_tx_callback(void *data)
572{
573 struct imx_port *sport = data;
574 struct scatterlist *sgl = &sport->tx_sgl[0];
575 struct circ_buf *xmit = &sport->port.state->xmit;
576 unsigned long flags;
577 u32 ucr1;
578
579 spin_lock_irqsave(&sport->port.lock, flags);
580
581 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
582
583 ucr1 = imx_uart_readl(sport, UCR1);
584 ucr1 &= ~UCR1_TXDMAEN;
585 imx_uart_writel(sport, ucr1, UCR1);
586
587 /* update the stat */
588 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
589 sport->port.icount.tx += sport->tx_bytes;
590
591 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
592
593 sport->dma_is_txing = 0;
594
595 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
596 uart_write_wakeup(&sport->port);
597
598 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
599 imx_uart_dma_tx(sport);
600 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
601 u32 ucr4 = imx_uart_readl(sport, UCR4);
602 ucr4 |= UCR4_TCEN;
603 imx_uart_writel(sport, ucr4, UCR4);
604 }
605
606 spin_unlock_irqrestore(&sport->port.lock, flags);
607}
608
609/* called with port.lock taken and irqs off */
610static void imx_uart_dma_tx(struct imx_port *sport)
611{
612 struct circ_buf *xmit = &sport->port.state->xmit;
613 struct scatterlist *sgl = sport->tx_sgl;
614 struct dma_async_tx_descriptor *desc;
615 struct dma_chan *chan = sport->dma_chan_tx;
616 struct device *dev = sport->port.dev;
617 u32 ucr1, ucr4;
618 int ret;
619
620 if (sport->dma_is_txing)
621 return;
622
623 ucr4 = imx_uart_readl(sport, UCR4);
624 ucr4 &= ~UCR4_TCEN;
625 imx_uart_writel(sport, ucr4, UCR4);
626
627 sport->tx_bytes = uart_circ_chars_pending(xmit);
628
629 if (xmit->tail < xmit->head || xmit->head == 0) {
630 sport->dma_tx_nents = 1;
631 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
632 } else {
633 sport->dma_tx_nents = 2;
634 sg_init_table(sgl, 2);
635 sg_set_buf(sgl, xmit->buf + xmit->tail,
636 UART_XMIT_SIZE - xmit->tail);
637 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
638 }
639
640 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
641 if (ret == 0) {
642 dev_err(dev, "DMA mapping error for TX.\n");
643 return;
644 }
645 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
646 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
647 if (!desc) {
648 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
649 DMA_TO_DEVICE);
650 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
651 return;
652 }
653 desc->callback = imx_uart_dma_tx_callback;
654 desc->callback_param = sport;
655
656 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
657 uart_circ_chars_pending(xmit));
658
659 ucr1 = imx_uart_readl(sport, UCR1);
660 ucr1 |= UCR1_TXDMAEN;
661 imx_uart_writel(sport, ucr1, UCR1);
662
663 /* fire it */
664 sport->dma_is_txing = 1;
665 dmaengine_submit(desc);
666 dma_async_issue_pending(chan);
667 return;
668}
669
670/* called with port.lock taken and irqs off */
671static void imx_uart_start_tx(struct uart_port *port)
672{
673 struct imx_port *sport = (struct imx_port *)port;
674 u32 ucr1;
675
676 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
677 return;
678
679 /*
680 * We cannot simply do nothing here if sport->tx_state == SEND already
681 * because UCR1_TXMPTYEN might already have been cleared in
682 * imx_uart_stop_tx(), but tx_state is still SEND.
683 */
684
685 if (port->rs485.flags & SER_RS485_ENABLED) {
686 if (sport->tx_state == OFF) {
687 u32 ucr2 = imx_uart_readl(sport, UCR2);
688 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
689 imx_uart_rts_active(sport, &ucr2);
690 else
691 imx_uart_rts_inactive(sport, &ucr2);
692 imx_uart_writel(sport, ucr2, UCR2);
693
694 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
695 imx_uart_stop_rx(port);
696
697 sport->tx_state = WAIT_AFTER_RTS;
698 start_hrtimer_ms(&sport->trigger_start_tx,
699 port->rs485.delay_rts_before_send);
700 return;
701 }
702
703 if (sport->tx_state == WAIT_AFTER_SEND
704 || sport->tx_state == WAIT_AFTER_RTS) {
705
706 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
707
708 /*
709 * Enable transmitter and shifter empty irq only if DMA
710 * is off. In the DMA case this is done in the
711 * tx-callback.
712 */
713 if (!sport->dma_is_enabled) {
714 u32 ucr4 = imx_uart_readl(sport, UCR4);
715 ucr4 |= UCR4_TCEN;
716 imx_uart_writel(sport, ucr4, UCR4);
717 }
718
719 sport->tx_state = SEND;
720 }
721 } else {
722 sport->tx_state = SEND;
723 }
724
725 if (!sport->dma_is_enabled) {
726 ucr1 = imx_uart_readl(sport, UCR1);
727 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
728 }
729
730 if (sport->dma_is_enabled) {
731 if (sport->port.x_char) {
732 /* We have X-char to send, so enable TX IRQ and
733 * disable TX DMA to let TX interrupt to send X-char */
734 ucr1 = imx_uart_readl(sport, UCR1);
735 ucr1 &= ~UCR1_TXDMAEN;
736 ucr1 |= UCR1_TRDYEN;
737 imx_uart_writel(sport, ucr1, UCR1);
738 return;
739 }
740
741 if (!uart_circ_empty(&port->state->xmit) &&
742 !uart_tx_stopped(port))
743 imx_uart_dma_tx(sport);
744 return;
745 }
746}
747
748static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
749{
750 struct imx_port *sport = dev_id;
751 u32 usr1;
752
753 imx_uart_writel(sport, USR1_RTSD, USR1);
754 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
755 uart_handle_cts_change(&sport->port, !!usr1);
756 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
757
758 return IRQ_HANDLED;
759}
760
761static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
762{
763 struct imx_port *sport = dev_id;
764 irqreturn_t ret;
765
766 spin_lock(&sport->port.lock);
767
768 ret = __imx_uart_rtsint(irq, dev_id);
769
770 spin_unlock(&sport->port.lock);
771
772 return ret;
773}
774
775static irqreturn_t imx_uart_txint(int irq, void *dev_id)
776{
777 struct imx_port *sport = dev_id;
778
779 spin_lock(&sport->port.lock);
780 imx_uart_transmit_buffer(sport);
781 spin_unlock(&sport->port.lock);
782 return IRQ_HANDLED;
783}
784
785static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
786{
787 struct imx_port *sport = dev_id;
788 unsigned int rx, flg, ignored = 0;
789 struct tty_port *port = &sport->port.state->port;
790
791 while (imx_uart_readl(sport, USR2) & USR2_RDR) {
792 u32 usr2;
793
794 flg = TTY_NORMAL;
795 sport->port.icount.rx++;
796
797 rx = imx_uart_readl(sport, URXD0);
798
799 usr2 = imx_uart_readl(sport, USR2);
800 if (usr2 & USR2_BRCD) {
801 imx_uart_writel(sport, USR2_BRCD, USR2);
802 if (uart_handle_break(&sport->port))
803 continue;
804 }
805
806 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
807 continue;
808
809 if (unlikely(rx & URXD_ERR)) {
810 if (rx & URXD_BRK)
811 sport->port.icount.brk++;
812 else if (rx & URXD_PRERR)
813 sport->port.icount.parity++;
814 else if (rx & URXD_FRMERR)
815 sport->port.icount.frame++;
816 if (rx & URXD_OVRRUN)
817 sport->port.icount.overrun++;
818
819 if (rx & sport->port.ignore_status_mask) {
820 if (++ignored > 100)
821 goto out;
822 continue;
823 }
824
825 rx &= (sport->port.read_status_mask | 0xFF);
826
827 if (rx & URXD_BRK)
828 flg = TTY_BREAK;
829 else if (rx & URXD_PRERR)
830 flg = TTY_PARITY;
831 else if (rx & URXD_FRMERR)
832 flg = TTY_FRAME;
833 if (rx & URXD_OVRRUN)
834 flg = TTY_OVERRUN;
835
836 sport->port.sysrq = 0;
837 }
838
839 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
840 goto out;
841
842 if (tty_insert_flip_char(port, rx, flg) == 0)
843 sport->port.icount.buf_overrun++;
844 }
845
846out:
847 tty_flip_buffer_push(port);
848
849 return IRQ_HANDLED;
850}
851
852static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
853{
854 struct imx_port *sport = dev_id;
855 irqreturn_t ret;
856
857 spin_lock(&sport->port.lock);
858
859 ret = __imx_uart_rxint(irq, dev_id);
860
861 spin_unlock(&sport->port.lock);
862
863 return ret;
864}
865
866static void imx_uart_clear_rx_errors(struct imx_port *sport);
867
868/*
869 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
870 */
871static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
872{
873 unsigned int tmp = TIOCM_DSR;
874 unsigned usr1 = imx_uart_readl(sport, USR1);
875 unsigned usr2 = imx_uart_readl(sport, USR2);
876
877 if (usr1 & USR1_RTSS)
878 tmp |= TIOCM_CTS;
879
880 /* in DCE mode DCDIN is always 0 */
881 if (!(usr2 & USR2_DCDIN))
882 tmp |= TIOCM_CAR;
883
884 if (sport->dte_mode)
885 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
886 tmp |= TIOCM_RI;
887
888 return tmp;
889}
890
891/*
892 * Handle any change of modem status signal since we were last called.
893 */
894static void imx_uart_mctrl_check(struct imx_port *sport)
895{
896 unsigned int status, changed;
897
898 status = imx_uart_get_hwmctrl(sport);
899 changed = status ^ sport->old_status;
900
901 if (changed == 0)
902 return;
903
904 sport->old_status = status;
905
906 if (changed & TIOCM_RI && status & TIOCM_RI)
907 sport->port.icount.rng++;
908 if (changed & TIOCM_DSR)
909 sport->port.icount.dsr++;
910 if (changed & TIOCM_CAR)
911 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
912 if (changed & TIOCM_CTS)
913 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
914
915 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
916}
917
918static irqreturn_t imx_uart_int(int irq, void *dev_id)
919{
920 struct imx_port *sport = dev_id;
921 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
922 irqreturn_t ret = IRQ_NONE;
923
924 spin_lock(&sport->port.lock);
925
926 usr1 = imx_uart_readl(sport, USR1);
927 usr2 = imx_uart_readl(sport, USR2);
928 ucr1 = imx_uart_readl(sport, UCR1);
929 ucr2 = imx_uart_readl(sport, UCR2);
930 ucr3 = imx_uart_readl(sport, UCR3);
931 ucr4 = imx_uart_readl(sport, UCR4);
932
933 /*
934 * Even if a condition is true that can trigger an irq only handle it if
935 * the respective irq source is enabled. This prevents some undesired
936 * actions, for example if a character that sits in the RX FIFO and that
937 * should be fetched via DMA is tried to be fetched using PIO. Or the
938 * receiver is currently off and so reading from URXD0 results in an
939 * exception. So just mask the (raw) status bits for disabled irqs.
940 */
941 if ((ucr1 & UCR1_RRDYEN) == 0)
942 usr1 &= ~USR1_RRDY;
943 if ((ucr2 & UCR2_ATEN) == 0)
944 usr1 &= ~USR1_AGTIM;
945 if ((ucr1 & UCR1_TRDYEN) == 0)
946 usr1 &= ~USR1_TRDY;
947 if ((ucr4 & UCR4_TCEN) == 0)
948 usr2 &= ~USR2_TXDC;
949 if ((ucr3 & UCR3_DTRDEN) == 0)
950 usr1 &= ~USR1_DTRD;
951 if ((ucr1 & UCR1_RTSDEN) == 0)
952 usr1 &= ~USR1_RTSD;
953 if ((ucr3 & UCR3_AWAKEN) == 0)
954 usr1 &= ~USR1_AWAKE;
955 if ((ucr4 & UCR4_OREN) == 0)
956 usr2 &= ~USR2_ORE;
957
958 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
959 imx_uart_writel(sport, USR1_AGTIM, USR1);
960
961 __imx_uart_rxint(irq, dev_id);
962 ret = IRQ_HANDLED;
963 }
964
965 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
966 imx_uart_transmit_buffer(sport);
967 ret = IRQ_HANDLED;
968 }
969
970 if (usr1 & USR1_DTRD) {
971 imx_uart_writel(sport, USR1_DTRD, USR1);
972
973 imx_uart_mctrl_check(sport);
974
975 ret = IRQ_HANDLED;
976 }
977
978 if (usr1 & USR1_RTSD) {
979 __imx_uart_rtsint(irq, dev_id);
980 ret = IRQ_HANDLED;
981 }
982
983 if (usr1 & USR1_AWAKE) {
984 imx_uart_writel(sport, USR1_AWAKE, USR1);
985 ret = IRQ_HANDLED;
986 }
987
988 if (usr2 & USR2_ORE) {
989 sport->port.icount.overrun++;
990 imx_uart_writel(sport, USR2_ORE, USR2);
991 ret = IRQ_HANDLED;
992 }
993
994 spin_unlock(&sport->port.lock);
995
996 return ret;
997}
998
999/*
1000 * Return TIOCSER_TEMT when transmitter is not busy.
1001 */
1002static unsigned int imx_uart_tx_empty(struct uart_port *port)
1003{
1004 struct imx_port *sport = (struct imx_port *)port;
1005 unsigned int ret;
1006
1007 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1008
1009 /* If the TX DMA is working, return 0. */
1010 if (sport->dma_is_txing)
1011 ret = 0;
1012
1013 return ret;
1014}
1015
1016/* called with port.lock taken and irqs off */
1017static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1018{
1019 struct imx_port *sport = (struct imx_port *)port;
1020 unsigned int ret = imx_uart_get_hwmctrl(sport);
1021
1022 mctrl_gpio_get(sport->gpios, &ret);
1023
1024 return ret;
1025}
1026
1027/* called with port.lock taken and irqs off */
1028static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1029{
1030 struct imx_port *sport = (struct imx_port *)port;
1031 u32 ucr3, uts;
1032
1033 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1034 u32 ucr2;
1035
1036 /*
1037 * Turn off autoRTS if RTS is lowered and restore autoRTS
1038 * setting if RTS is raised.
1039 */
1040 ucr2 = imx_uart_readl(sport, UCR2);
1041 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1042 if (mctrl & TIOCM_RTS) {
1043 ucr2 |= UCR2_CTS;
1044 /*
1045 * UCR2_IRTS is unset if and only if the port is
1046 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1047 * to get the state to restore to.
1048 */
1049 if (!(ucr2 & UCR2_IRTS))
1050 ucr2 |= UCR2_CTSC;
1051 }
1052 imx_uart_writel(sport, ucr2, UCR2);
1053 }
1054
1055 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1056 if (!(mctrl & TIOCM_DTR))
1057 ucr3 |= UCR3_DSR;
1058 imx_uart_writel(sport, ucr3, UCR3);
1059
1060 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1061 if (mctrl & TIOCM_LOOP)
1062 uts |= UTS_LOOP;
1063 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1064
1065 mctrl_gpio_set(sport->gpios, mctrl);
1066}
1067
1068/*
1069 * Interrupts always disabled.
1070 */
1071static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1072{
1073 struct imx_port *sport = (struct imx_port *)port;
1074 unsigned long flags;
1075 u32 ucr1;
1076
1077 spin_lock_irqsave(&sport->port.lock, flags);
1078
1079 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1080
1081 if (break_state != 0)
1082 ucr1 |= UCR1_SNDBRK;
1083
1084 imx_uart_writel(sport, ucr1, UCR1);
1085
1086 spin_unlock_irqrestore(&sport->port.lock, flags);
1087}
1088
1089/*
1090 * This is our per-port timeout handler, for checking the
1091 * modem status signals.
1092 */
1093static void imx_uart_timeout(struct timer_list *t)
1094{
1095 struct imx_port *sport = from_timer(sport, t, timer);
1096 unsigned long flags;
1097
1098 if (sport->port.state) {
1099 spin_lock_irqsave(&sport->port.lock, flags);
1100 imx_uart_mctrl_check(sport);
1101 spin_unlock_irqrestore(&sport->port.lock, flags);
1102
1103 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1104 }
1105}
1106
1107/*
1108 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1109 * [1] the RX DMA buffer is full.
1110 * [2] the aging timer expires
1111 *
1112 * Condition [2] is triggered when a character has been sitting in the FIFO
1113 * for at least 8 byte durations.
1114 */
1115static void imx_uart_dma_rx_callback(void *data)
1116{
1117 struct imx_port *sport = data;
1118 struct dma_chan *chan = sport->dma_chan_rx;
1119 struct scatterlist *sgl = &sport->rx_sgl;
1120 struct tty_port *port = &sport->port.state->port;
1121 struct dma_tx_state state;
1122 struct circ_buf *rx_ring = &sport->rx_ring;
1123 enum dma_status status;
1124 unsigned int w_bytes = 0;
1125 unsigned int r_bytes;
1126 unsigned int bd_size;
1127
1128 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1129
1130 if (status == DMA_ERROR) {
1131 imx_uart_clear_rx_errors(sport);
1132 return;
1133 }
1134
1135 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1136
1137 /*
1138 * The state-residue variable represents the empty space
1139 * relative to the entire buffer. Taking this in consideration
1140 * the head is always calculated base on the buffer total
1141 * length - DMA transaction residue. The UART script from the
1142 * SDMA firmware will jump to the next buffer descriptor,
1143 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1144 * Taking this in consideration the tail is always at the
1145 * beginning of the buffer descriptor that contains the head.
1146 */
1147
1148 /* Calculate the head */
1149 rx_ring->head = sg_dma_len(sgl) - state.residue;
1150
1151 /* Calculate the tail. */
1152 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1153 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1154
1155 if (rx_ring->head <= sg_dma_len(sgl) &&
1156 rx_ring->head > rx_ring->tail) {
1157
1158 /* Move data from tail to head */
1159 r_bytes = rx_ring->head - rx_ring->tail;
1160
1161 /* CPU claims ownership of RX DMA buffer */
1162 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1163 DMA_FROM_DEVICE);
1164
1165 w_bytes = tty_insert_flip_string(port,
1166 sport->rx_buf + rx_ring->tail, r_bytes);
1167
1168 /* UART retrieves ownership of RX DMA buffer */
1169 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1170 DMA_FROM_DEVICE);
1171
1172 if (w_bytes != r_bytes)
1173 sport->port.icount.buf_overrun++;
1174
1175 sport->port.icount.rx += w_bytes;
1176 } else {
1177 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1178 WARN_ON(rx_ring->head <= rx_ring->tail);
1179 }
1180 }
1181
1182 if (w_bytes) {
1183 tty_flip_buffer_push(port);
1184 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1185 }
1186}
1187
1188static int imx_uart_start_rx_dma(struct imx_port *sport)
1189{
1190 struct scatterlist *sgl = &sport->rx_sgl;
1191 struct dma_chan *chan = sport->dma_chan_rx;
1192 struct device *dev = sport->port.dev;
1193 struct dma_async_tx_descriptor *desc;
1194 int ret;
1195
1196 sport->rx_ring.head = 0;
1197 sport->rx_ring.tail = 0;
1198
1199 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size);
1200 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1201 if (ret == 0) {
1202 dev_err(dev, "DMA mapping error for RX.\n");
1203 return -EINVAL;
1204 }
1205
1206 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1207 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1208 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1209
1210 if (!desc) {
1211 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1212 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1213 return -EINVAL;
1214 }
1215 desc->callback = imx_uart_dma_rx_callback;
1216 desc->callback_param = sport;
1217
1218 dev_dbg(dev, "RX: prepare for the DMA.\n");
1219 sport->dma_is_rxing = 1;
1220 sport->rx_cookie = dmaengine_submit(desc);
1221 dma_async_issue_pending(chan);
1222 return 0;
1223}
1224
1225static void imx_uart_clear_rx_errors(struct imx_port *sport)
1226{
1227 struct tty_port *port = &sport->port.state->port;
1228 u32 usr1, usr2;
1229
1230 usr1 = imx_uart_readl(sport, USR1);
1231 usr2 = imx_uart_readl(sport, USR2);
1232
1233 if (usr2 & USR2_BRCD) {
1234 sport->port.icount.brk++;
1235 imx_uart_writel(sport, USR2_BRCD, USR2);
1236 uart_handle_break(&sport->port);
1237 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1238 sport->port.icount.buf_overrun++;
1239 tty_flip_buffer_push(port);
1240 } else {
1241 if (usr1 & USR1_FRAMERR) {
1242 sport->port.icount.frame++;
1243 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1244 } else if (usr1 & USR1_PARITYERR) {
1245 sport->port.icount.parity++;
1246 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1247 }
1248 }
1249
1250 if (usr2 & USR2_ORE) {
1251 sport->port.icount.overrun++;
1252 imx_uart_writel(sport, USR2_ORE, USR2);
1253 }
1254
1255}
1256
1257#define TXTL_DEFAULT 2 /* reset default */
1258#define RXTL_DEFAULT 1 /* reset default */
1259#define TXTL_DMA 8 /* DMA burst setting */
1260#define RXTL_DMA 9 /* DMA burst setting */
1261
1262static void imx_uart_setup_ufcr(struct imx_port *sport,
1263 unsigned char txwl, unsigned char rxwl)
1264{
1265 unsigned int val;
1266
1267 /* set receiver / transmitter trigger level */
1268 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1269 val |= txwl << UFCR_TXTL_SHF | rxwl;
1270 imx_uart_writel(sport, val, UFCR);
1271}
1272
1273static void imx_uart_dma_exit(struct imx_port *sport)
1274{
1275 if (sport->dma_chan_rx) {
1276 dmaengine_terminate_sync(sport->dma_chan_rx);
1277 dma_release_channel(sport->dma_chan_rx);
1278 sport->dma_chan_rx = NULL;
1279 sport->rx_cookie = -EINVAL;
1280 kfree(sport->rx_buf);
1281 sport->rx_buf = NULL;
1282 }
1283
1284 if (sport->dma_chan_tx) {
1285 dmaengine_terminate_sync(sport->dma_chan_tx);
1286 dma_release_channel(sport->dma_chan_tx);
1287 sport->dma_chan_tx = NULL;
1288 }
1289}
1290
1291static int imx_uart_dma_init(struct imx_port *sport)
1292{
1293 struct dma_slave_config slave_config = {};
1294 struct device *dev = sport->port.dev;
1295 int ret;
1296
1297 /* Prepare for RX : */
1298 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1299 if (!sport->dma_chan_rx) {
1300 dev_dbg(dev, "cannot get the DMA channel.\n");
1301 ret = -EINVAL;
1302 goto err;
1303 }
1304
1305 slave_config.direction = DMA_DEV_TO_MEM;
1306 slave_config.src_addr = sport->port.mapbase + URXD0;
1307 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1308 /* one byte less than the watermark level to enable the aging timer */
1309 slave_config.src_maxburst = RXTL_DMA - 1;
1310 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1311 if (ret) {
1312 dev_err(dev, "error in RX dma configuration.\n");
1313 goto err;
1314 }
1315
1316 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods;
1317 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL);
1318 if (!sport->rx_buf) {
1319 ret = -ENOMEM;
1320 goto err;
1321 }
1322 sport->rx_ring.buf = sport->rx_buf;
1323
1324 /* Prepare for TX : */
1325 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1326 if (!sport->dma_chan_tx) {
1327 dev_err(dev, "cannot get the TX DMA channel!\n");
1328 ret = -EINVAL;
1329 goto err;
1330 }
1331
1332 slave_config.direction = DMA_MEM_TO_DEV;
1333 slave_config.dst_addr = sport->port.mapbase + URTX0;
1334 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1335 slave_config.dst_maxburst = TXTL_DMA;
1336 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1337 if (ret) {
1338 dev_err(dev, "error in TX dma configuration.");
1339 goto err;
1340 }
1341
1342 return 0;
1343err:
1344 imx_uart_dma_exit(sport);
1345 return ret;
1346}
1347
1348static void imx_uart_enable_dma(struct imx_port *sport)
1349{
1350 u32 ucr1;
1351
1352 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1353
1354 /* set UCR1 */
1355 ucr1 = imx_uart_readl(sport, UCR1);
1356 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1357 imx_uart_writel(sport, ucr1, UCR1);
1358
1359 sport->dma_is_enabled = 1;
1360}
1361
1362static void imx_uart_disable_dma(struct imx_port *sport)
1363{
1364 u32 ucr1;
1365
1366 /* clear UCR1 */
1367 ucr1 = imx_uart_readl(sport, UCR1);
1368 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1369 imx_uart_writel(sport, ucr1, UCR1);
1370
1371 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1372
1373 sport->dma_is_enabled = 0;
1374}
1375
1376/* half the RX buffer size */
1377#define CTSTL 16
1378
1379static int imx_uart_startup(struct uart_port *port)
1380{
1381 struct imx_port *sport = (struct imx_port *)port;
1382 int retval, i;
1383 unsigned long flags;
1384 int dma_is_inited = 0;
1385 u32 ucr1, ucr2, ucr3, ucr4;
1386
1387 retval = clk_prepare_enable(sport->clk_per);
1388 if (retval)
1389 return retval;
1390 retval = clk_prepare_enable(sport->clk_ipg);
1391 if (retval) {
1392 clk_disable_unprepare(sport->clk_per);
1393 return retval;
1394 }
1395
1396 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1397
1398 /* disable the DREN bit (Data Ready interrupt enable) before
1399 * requesting IRQs
1400 */
1401 ucr4 = imx_uart_readl(sport, UCR4);
1402
1403 /* set the trigger level for CTS */
1404 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1405 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1406
1407 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1408
1409 /* Can we enable the DMA support? */
1410 if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1411 dma_is_inited = 1;
1412
1413 spin_lock_irqsave(&sport->port.lock, flags);
1414 /* Reset fifo's and state machines */
1415 i = 100;
1416
1417 ucr2 = imx_uart_readl(sport, UCR2);
1418 ucr2 &= ~UCR2_SRST;
1419 imx_uart_writel(sport, ucr2, UCR2);
1420
1421 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1422 udelay(1);
1423
1424 /*
1425 * Finally, clear and enable interrupts
1426 */
1427 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1428 imx_uart_writel(sport, USR2_ORE, USR2);
1429
1430 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1431 ucr1 |= UCR1_UARTEN;
1432 if (sport->have_rtscts)
1433 ucr1 |= UCR1_RTSDEN;
1434
1435 imx_uart_writel(sport, ucr1, UCR1);
1436
1437 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1438 if (!sport->dma_is_enabled)
1439 ucr4 |= UCR4_OREN;
1440 if (sport->inverted_rx)
1441 ucr4 |= UCR4_INVR;
1442 imx_uart_writel(sport, ucr4, UCR4);
1443
1444 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1445 /*
1446 * configure tx polarity before enabling tx
1447 */
1448 if (sport->inverted_tx)
1449 ucr3 |= UCR3_INVT;
1450
1451 if (!imx_uart_is_imx1(sport)) {
1452 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1453
1454 if (sport->dte_mode)
1455 /* disable broken interrupts */
1456 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1457 }
1458 imx_uart_writel(sport, ucr3, UCR3);
1459
1460 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1461 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1462 if (!sport->have_rtscts)
1463 ucr2 |= UCR2_IRTS;
1464 /*
1465 * make sure the edge sensitive RTS-irq is disabled,
1466 * we're using RTSD instead.
1467 */
1468 if (!imx_uart_is_imx1(sport))
1469 ucr2 &= ~UCR2_RTSEN;
1470 imx_uart_writel(sport, ucr2, UCR2);
1471
1472 /*
1473 * Enable modem status interrupts
1474 */
1475 imx_uart_enable_ms(&sport->port);
1476
1477 if (dma_is_inited) {
1478 imx_uart_enable_dma(sport);
1479 imx_uart_start_rx_dma(sport);
1480 } else {
1481 ucr1 = imx_uart_readl(sport, UCR1);
1482 ucr1 |= UCR1_RRDYEN;
1483 imx_uart_writel(sport, ucr1, UCR1);
1484
1485 ucr2 = imx_uart_readl(sport, UCR2);
1486 ucr2 |= UCR2_ATEN;
1487 imx_uart_writel(sport, ucr2, UCR2);
1488 }
1489
1490 spin_unlock_irqrestore(&sport->port.lock, flags);
1491
1492 return 0;
1493}
1494
1495static void imx_uart_shutdown(struct uart_port *port)
1496{
1497 struct imx_port *sport = (struct imx_port *)port;
1498 unsigned long flags;
1499 u32 ucr1, ucr2, ucr4;
1500
1501 if (sport->dma_is_enabled) {
1502 dmaengine_terminate_sync(sport->dma_chan_tx);
1503 if (sport->dma_is_txing) {
1504 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1505 sport->dma_tx_nents, DMA_TO_DEVICE);
1506 sport->dma_is_txing = 0;
1507 }
1508 dmaengine_terminate_sync(sport->dma_chan_rx);
1509 if (sport->dma_is_rxing) {
1510 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1511 1, DMA_FROM_DEVICE);
1512 sport->dma_is_rxing = 0;
1513 }
1514
1515 spin_lock_irqsave(&sport->port.lock, flags);
1516 imx_uart_stop_tx(port);
1517 imx_uart_stop_rx(port);
1518 imx_uart_disable_dma(sport);
1519 spin_unlock_irqrestore(&sport->port.lock, flags);
1520 imx_uart_dma_exit(sport);
1521 }
1522
1523 mctrl_gpio_disable_ms(sport->gpios);
1524
1525 spin_lock_irqsave(&sport->port.lock, flags);
1526 ucr2 = imx_uart_readl(sport, UCR2);
1527 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1528 imx_uart_writel(sport, ucr2, UCR2);
1529 spin_unlock_irqrestore(&sport->port.lock, flags);
1530
1531 /*
1532 * Stop our timer.
1533 */
1534 del_timer_sync(&sport->timer);
1535
1536 /*
1537 * Disable all interrupts, port and break condition.
1538 */
1539
1540 spin_lock_irqsave(&sport->port.lock, flags);
1541
1542 ucr1 = imx_uart_readl(sport, UCR1);
1543 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN);
1544 imx_uart_writel(sport, ucr1, UCR1);
1545
1546 ucr4 = imx_uart_readl(sport, UCR4);
1547 ucr4 &= ~(UCR4_OREN | UCR4_TCEN);
1548 imx_uart_writel(sport, ucr4, UCR4);
1549
1550 spin_unlock_irqrestore(&sport->port.lock, flags);
1551
1552 clk_disable_unprepare(sport->clk_per);
1553 clk_disable_unprepare(sport->clk_ipg);
1554}
1555
1556/* called with port.lock taken and irqs off */
1557static void imx_uart_flush_buffer(struct uart_port *port)
1558{
1559 struct imx_port *sport = (struct imx_port *)port;
1560 struct scatterlist *sgl = &sport->tx_sgl[0];
1561 u32 ucr2;
1562 int i = 100, ubir, ubmr, uts;
1563
1564 if (!sport->dma_chan_tx)
1565 return;
1566
1567 sport->tx_bytes = 0;
1568 dmaengine_terminate_all(sport->dma_chan_tx);
1569 if (sport->dma_is_txing) {
1570 u32 ucr1;
1571
1572 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1573 DMA_TO_DEVICE);
1574 ucr1 = imx_uart_readl(sport, UCR1);
1575 ucr1 &= ~UCR1_TXDMAEN;
1576 imx_uart_writel(sport, ucr1, UCR1);
1577 sport->dma_is_txing = 0;
1578 }
1579
1580 /*
1581 * According to the Reference Manual description of the UART SRST bit:
1582 *
1583 * "Reset the transmit and receive state machines,
1584 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1585 * and UTS[6-3]".
1586 *
1587 * We don't need to restore the old values from USR1, USR2, URXD and
1588 * UTXD. UBRC is read only, so only save/restore the other three
1589 * registers.
1590 */
1591 ubir = imx_uart_readl(sport, UBIR);
1592 ubmr = imx_uart_readl(sport, UBMR);
1593 uts = imx_uart_readl(sport, IMX21_UTS);
1594
1595 ucr2 = imx_uart_readl(sport, UCR2);
1596 ucr2 &= ~UCR2_SRST;
1597 imx_uart_writel(sport, ucr2, UCR2);
1598
1599 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1600 udelay(1);
1601
1602 /* Restore the registers */
1603 imx_uart_writel(sport, ubir, UBIR);
1604 imx_uart_writel(sport, ubmr, UBMR);
1605 imx_uart_writel(sport, uts, IMX21_UTS);
1606}
1607
1608static void
1609imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1610 struct ktermios *old)
1611{
1612 struct imx_port *sport = (struct imx_port *)port;
1613 unsigned long flags;
1614 u32 ucr2, old_ucr2, ufcr;
1615 unsigned int baud, quot;
1616 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1617 unsigned long div;
1618 unsigned long num, denom, old_ubir, old_ubmr;
1619 uint64_t tdiv64;
1620
1621 /*
1622 * We only support CS7 and CS8.
1623 */
1624 while ((termios->c_cflag & CSIZE) != CS7 &&
1625 (termios->c_cflag & CSIZE) != CS8) {
1626 termios->c_cflag &= ~CSIZE;
1627 termios->c_cflag |= old_csize;
1628 old_csize = CS8;
1629 }
1630
1631 del_timer_sync(&sport->timer);
1632
1633 /*
1634 * Ask the core to calculate the divisor for us.
1635 */
1636 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1637 quot = uart_get_divisor(port, baud);
1638
1639 spin_lock_irqsave(&sport->port.lock, flags);
1640
1641 /*
1642 * Read current UCR2 and save it for future use, then clear all the bits
1643 * except those we will or may need to preserve.
1644 */
1645 old_ucr2 = imx_uart_readl(sport, UCR2);
1646 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1647
1648 ucr2 |= UCR2_SRST | UCR2_IRTS;
1649 if ((termios->c_cflag & CSIZE) == CS8)
1650 ucr2 |= UCR2_WS;
1651
1652 if (!sport->have_rtscts)
1653 termios->c_cflag &= ~CRTSCTS;
1654
1655 if (port->rs485.flags & SER_RS485_ENABLED) {
1656 /*
1657 * RTS is mandatory for rs485 operation, so keep
1658 * it under manual control and keep transmitter
1659 * disabled.
1660 */
1661 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1662 imx_uart_rts_active(sport, &ucr2);
1663 else
1664 imx_uart_rts_inactive(sport, &ucr2);
1665
1666 } else if (termios->c_cflag & CRTSCTS) {
1667 /*
1668 * Only let receiver control RTS output if we were not requested
1669 * to have RTS inactive (which then should take precedence).
1670 */
1671 if (ucr2 & UCR2_CTS)
1672 ucr2 |= UCR2_CTSC;
1673 }
1674
1675 if (termios->c_cflag & CRTSCTS)
1676 ucr2 &= ~UCR2_IRTS;
1677 if (termios->c_cflag & CSTOPB)
1678 ucr2 |= UCR2_STPB;
1679 if (termios->c_cflag & PARENB) {
1680 ucr2 |= UCR2_PREN;
1681 if (termios->c_cflag & PARODD)
1682 ucr2 |= UCR2_PROE;
1683 }
1684
1685 sport->port.read_status_mask = 0;
1686 if (termios->c_iflag & INPCK)
1687 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1688 if (termios->c_iflag & (BRKINT | PARMRK))
1689 sport->port.read_status_mask |= URXD_BRK;
1690
1691 /*
1692 * Characters to ignore
1693 */
1694 sport->port.ignore_status_mask = 0;
1695 if (termios->c_iflag & IGNPAR)
1696 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1697 if (termios->c_iflag & IGNBRK) {
1698 sport->port.ignore_status_mask |= URXD_BRK;
1699 /*
1700 * If we're ignoring parity and break indicators,
1701 * ignore overruns too (for real raw support).
1702 */
1703 if (termios->c_iflag & IGNPAR)
1704 sport->port.ignore_status_mask |= URXD_OVRRUN;
1705 }
1706
1707 if ((termios->c_cflag & CREAD) == 0)
1708 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1709
1710 /*
1711 * Update the per-port timeout.
1712 */
1713 uart_update_timeout(port, termios->c_cflag, baud);
1714
1715 /* custom-baudrate handling */
1716 div = sport->port.uartclk / (baud * 16);
1717 if (baud == 38400 && quot != div)
1718 baud = sport->port.uartclk / (quot * 16);
1719
1720 div = sport->port.uartclk / (baud * 16);
1721 if (div > 7)
1722 div = 7;
1723 if (!div)
1724 div = 1;
1725
1726 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1727 1 << 16, 1 << 16, &num, &denom);
1728
1729 tdiv64 = sport->port.uartclk;
1730 tdiv64 *= num;
1731 do_div(tdiv64, denom * 16 * div);
1732 tty_termios_encode_baud_rate(termios,
1733 (speed_t)tdiv64, (speed_t)tdiv64);
1734
1735 num -= 1;
1736 denom -= 1;
1737
1738 ufcr = imx_uart_readl(sport, UFCR);
1739 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1740 imx_uart_writel(sport, ufcr, UFCR);
1741
1742 /*
1743 * Two registers below should always be written both and in this
1744 * particular order. One consequence is that we need to check if any of
1745 * them changes and then update both. We do need the check for change
1746 * as even writing the same values seem to "restart"
1747 * transmission/receiving logic in the hardware, that leads to data
1748 * breakage even when rate doesn't in fact change. E.g., user switches
1749 * RTS/CTS handshake and suddenly gets broken bytes.
1750 */
1751 old_ubir = imx_uart_readl(sport, UBIR);
1752 old_ubmr = imx_uart_readl(sport, UBMR);
1753 if (old_ubir != num || old_ubmr != denom) {
1754 imx_uart_writel(sport, num, UBIR);
1755 imx_uart_writel(sport, denom, UBMR);
1756 }
1757
1758 if (!imx_uart_is_imx1(sport))
1759 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1760 IMX21_ONEMS);
1761
1762 imx_uart_writel(sport, ucr2, UCR2);
1763
1764 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1765 imx_uart_enable_ms(&sport->port);
1766
1767 spin_unlock_irqrestore(&sport->port.lock, flags);
1768}
1769
1770static const char *imx_uart_type(struct uart_port *port)
1771{
1772 struct imx_port *sport = (struct imx_port *)port;
1773
1774 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1775}
1776
1777/*
1778 * Configure/autoconfigure the port.
1779 */
1780static void imx_uart_config_port(struct uart_port *port, int flags)
1781{
1782 struct imx_port *sport = (struct imx_port *)port;
1783
1784 if (flags & UART_CONFIG_TYPE)
1785 sport->port.type = PORT_IMX;
1786}
1787
1788/*
1789 * Verify the new serial_struct (for TIOCSSERIAL).
1790 * The only change we allow are to the flags and type, and
1791 * even then only between PORT_IMX and PORT_UNKNOWN
1792 */
1793static int
1794imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1795{
1796 struct imx_port *sport = (struct imx_port *)port;
1797 int ret = 0;
1798
1799 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1800 ret = -EINVAL;
1801 if (sport->port.irq != ser->irq)
1802 ret = -EINVAL;
1803 if (ser->io_type != UPIO_MEM)
1804 ret = -EINVAL;
1805 if (sport->port.uartclk / 16 != ser->baud_base)
1806 ret = -EINVAL;
1807 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1808 ret = -EINVAL;
1809 if (sport->port.iobase != ser->port)
1810 ret = -EINVAL;
1811 if (ser->hub6 != 0)
1812 ret = -EINVAL;
1813 return ret;
1814}
1815
1816#if defined(CONFIG_CONSOLE_POLL)
1817
1818static int imx_uart_poll_init(struct uart_port *port)
1819{
1820 struct imx_port *sport = (struct imx_port *)port;
1821 unsigned long flags;
1822 u32 ucr1, ucr2;
1823 int retval;
1824
1825 retval = clk_prepare_enable(sport->clk_ipg);
1826 if (retval)
1827 return retval;
1828 retval = clk_prepare_enable(sport->clk_per);
1829 if (retval)
1830 clk_disable_unprepare(sport->clk_ipg);
1831
1832 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1833
1834 spin_lock_irqsave(&sport->port.lock, flags);
1835
1836 /*
1837 * Be careful about the order of enabling bits here. First enable the
1838 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1839 * This prevents that a character that already sits in the RX fifo is
1840 * triggering an irq but the try to fetch it from there results in an
1841 * exception because UARTEN or RXEN is still off.
1842 */
1843 ucr1 = imx_uart_readl(sport, UCR1);
1844 ucr2 = imx_uart_readl(sport, UCR2);
1845
1846 if (imx_uart_is_imx1(sport))
1847 ucr1 |= IMX1_UCR1_UARTCLKEN;
1848
1849 ucr1 |= UCR1_UARTEN;
1850 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1851
1852 ucr2 |= UCR2_RXEN | UCR2_TXEN;
1853 ucr2 &= ~UCR2_ATEN;
1854
1855 imx_uart_writel(sport, ucr1, UCR1);
1856 imx_uart_writel(sport, ucr2, UCR2);
1857
1858 /* now enable irqs */
1859 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1860 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1861
1862 spin_unlock_irqrestore(&sport->port.lock, flags);
1863
1864 return 0;
1865}
1866
1867static int imx_uart_poll_get_char(struct uart_port *port)
1868{
1869 struct imx_port *sport = (struct imx_port *)port;
1870 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1871 return NO_POLL_CHAR;
1872
1873 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1874}
1875
1876static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1877{
1878 struct imx_port *sport = (struct imx_port *)port;
1879 unsigned int status;
1880
1881 /* drain */
1882 do {
1883 status = imx_uart_readl(sport, USR1);
1884 } while (~status & USR1_TRDY);
1885
1886 /* write */
1887 imx_uart_writel(sport, c, URTX0);
1888
1889 /* flush */
1890 do {
1891 status = imx_uart_readl(sport, USR2);
1892 } while (~status & USR2_TXDC);
1893}
1894#endif
1895
1896/* called with port.lock taken and irqs off or from .probe without locking */
1897static int imx_uart_rs485_config(struct uart_port *port,
1898 struct serial_rs485 *rs485conf)
1899{
1900 struct imx_port *sport = (struct imx_port *)port;
1901 u32 ucr2;
1902
1903 /* RTS is required to control the transmitter */
1904 if (!sport->have_rtscts && !sport->have_rtsgpio)
1905 rs485conf->flags &= ~SER_RS485_ENABLED;
1906
1907 if (rs485conf->flags & SER_RS485_ENABLED) {
1908 /* Enable receiver if low-active RTS signal is requested */
1909 if (sport->have_rtscts && !sport->have_rtsgpio &&
1910 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1911 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1912
1913 /* disable transmitter */
1914 ucr2 = imx_uart_readl(sport, UCR2);
1915 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1916 imx_uart_rts_active(sport, &ucr2);
1917 else
1918 imx_uart_rts_inactive(sport, &ucr2);
1919 imx_uart_writel(sport, ucr2, UCR2);
1920 }
1921
1922 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1923 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1924 rs485conf->flags & SER_RS485_RX_DURING_TX)
1925 imx_uart_start_rx(port);
1926
1927 port->rs485 = *rs485conf;
1928
1929 return 0;
1930}
1931
1932static const struct uart_ops imx_uart_pops = {
1933 .tx_empty = imx_uart_tx_empty,
1934 .set_mctrl = imx_uart_set_mctrl,
1935 .get_mctrl = imx_uart_get_mctrl,
1936 .stop_tx = imx_uart_stop_tx,
1937 .start_tx = imx_uart_start_tx,
1938 .stop_rx = imx_uart_stop_rx,
1939 .enable_ms = imx_uart_enable_ms,
1940 .break_ctl = imx_uart_break_ctl,
1941 .startup = imx_uart_startup,
1942 .shutdown = imx_uart_shutdown,
1943 .flush_buffer = imx_uart_flush_buffer,
1944 .set_termios = imx_uart_set_termios,
1945 .type = imx_uart_type,
1946 .config_port = imx_uart_config_port,
1947 .verify_port = imx_uart_verify_port,
1948#if defined(CONFIG_CONSOLE_POLL)
1949 .poll_init = imx_uart_poll_init,
1950 .poll_get_char = imx_uart_poll_get_char,
1951 .poll_put_char = imx_uart_poll_put_char,
1952#endif
1953};
1954
1955static struct imx_port *imx_uart_ports[UART_NR];
1956
1957#if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
1958static void imx_uart_console_putchar(struct uart_port *port, int ch)
1959{
1960 struct imx_port *sport = (struct imx_port *)port;
1961
1962 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1963 barrier();
1964
1965 imx_uart_writel(sport, ch, URTX0);
1966}
1967
1968/*
1969 * Interrupts are disabled on entering
1970 */
1971static void
1972imx_uart_console_write(struct console *co, const char *s, unsigned int count)
1973{
1974 struct imx_port *sport = imx_uart_ports[co->index];
1975 struct imx_port_ucrs old_ucr;
1976 unsigned long flags;
1977 unsigned int ucr1;
1978 int locked = 1;
1979
1980 if (sport->port.sysrq)
1981 locked = 0;
1982 else if (oops_in_progress)
1983 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1984 else
1985 spin_lock_irqsave(&sport->port.lock, flags);
1986
1987 /*
1988 * First, save UCR1/2/3 and then disable interrupts
1989 */
1990 imx_uart_ucrs_save(sport, &old_ucr);
1991 ucr1 = old_ucr.ucr1;
1992
1993 if (imx_uart_is_imx1(sport))
1994 ucr1 |= IMX1_UCR1_UARTCLKEN;
1995 ucr1 |= UCR1_UARTEN;
1996 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1997
1998 imx_uart_writel(sport, ucr1, UCR1);
1999
2000 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2001
2002 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
2003
2004 /*
2005 * Finally, wait for transmitter to become empty
2006 * and restore UCR1/2/3
2007 */
2008 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC));
2009
2010 imx_uart_ucrs_restore(sport, &old_ucr);
2011
2012 if (locked)
2013 spin_unlock_irqrestore(&sport->port.lock, flags);
2014}
2015
2016/*
2017 * If the port was already initialised (eg, by a boot loader),
2018 * try to determine the current setup.
2019 */
2020static void __init
2021imx_uart_console_get_options(struct imx_port *sport, int *baud,
2022 int *parity, int *bits)
2023{
2024
2025 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2026 /* ok, the port was enabled */
2027 unsigned int ucr2, ubir, ubmr, uartclk;
2028 unsigned int baud_raw;
2029 unsigned int ucfr_rfdiv;
2030
2031 ucr2 = imx_uart_readl(sport, UCR2);
2032
2033 *parity = 'n';
2034 if (ucr2 & UCR2_PREN) {
2035 if (ucr2 & UCR2_PROE)
2036 *parity = 'o';
2037 else
2038 *parity = 'e';
2039 }
2040
2041 if (ucr2 & UCR2_WS)
2042 *bits = 8;
2043 else
2044 *bits = 7;
2045
2046 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2047 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2048
2049 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2050 if (ucfr_rfdiv == 6)
2051 ucfr_rfdiv = 7;
2052 else
2053 ucfr_rfdiv = 6 - ucfr_rfdiv;
2054
2055 uartclk = clk_get_rate(sport->clk_per);
2056 uartclk /= ucfr_rfdiv;
2057
2058 { /*
2059 * The next code provides exact computation of
2060 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2061 * without need of float support or long long division,
2062 * which would be required to prevent 32bit arithmetic overflow
2063 */
2064 unsigned int mul = ubir + 1;
2065 unsigned int div = 16 * (ubmr + 1);
2066 unsigned int rem = uartclk % div;
2067
2068 baud_raw = (uartclk / div) * mul;
2069 baud_raw += (rem * mul + div / 2) / div;
2070 *baud = (baud_raw + 50) / 100 * 100;
2071 }
2072
2073 if (*baud != baud_raw)
2074 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2075 baud_raw, *baud);
2076 }
2077}
2078
2079static int __init
2080imx_uart_console_setup(struct console *co, char *options)
2081{
2082 struct imx_port *sport;
2083 int baud = 9600;
2084 int bits = 8;
2085 int parity = 'n';
2086 int flow = 'n';
2087 int retval;
2088
2089 /*
2090 * Check whether an invalid uart number has been specified, and
2091 * if so, search for the first available port that does have
2092 * console support.
2093 */
2094 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2095 co->index = 0;
2096 sport = imx_uart_ports[co->index];
2097 if (sport == NULL)
2098 return -ENODEV;
2099
2100 /* For setting the registers, we only need to enable the ipg clock. */
2101 retval = clk_prepare_enable(sport->clk_ipg);
2102 if (retval)
2103 goto error_console;
2104
2105 if (options)
2106 uart_parse_options(options, &baud, &parity, &bits, &flow);
2107 else
2108 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2109
2110 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2111
2112 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2113
2114 if (retval) {
2115 clk_disable_unprepare(sport->clk_ipg);
2116 goto error_console;
2117 }
2118
2119 retval = clk_prepare_enable(sport->clk_per);
2120 if (retval)
2121 clk_disable_unprepare(sport->clk_ipg);
2122
2123error_console:
2124 return retval;
2125}
2126
2127static struct uart_driver imx_uart_uart_driver;
2128static struct console imx_uart_console = {
2129 .name = DEV_NAME,
2130 .write = imx_uart_console_write,
2131 .device = uart_console_device,
2132 .setup = imx_uart_console_setup,
2133 .flags = CON_PRINTBUFFER,
2134 .index = -1,
2135 .data = &imx_uart_uart_driver,
2136};
2137
2138#define IMX_CONSOLE &imx_uart_console
2139
2140#else
2141#define IMX_CONSOLE NULL
2142#endif
2143
2144static struct uart_driver imx_uart_uart_driver = {
2145 .owner = THIS_MODULE,
2146 .driver_name = DRIVER_NAME,
2147 .dev_name = DEV_NAME,
2148 .major = SERIAL_IMX_MAJOR,
2149 .minor = MINOR_START,
2150 .nr = ARRAY_SIZE(imx_uart_ports),
2151 .cons = IMX_CONSOLE,
2152};
2153
2154static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2155{
2156 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2157 unsigned long flags;
2158
2159 spin_lock_irqsave(&sport->port.lock, flags);
2160 if (sport->tx_state == WAIT_AFTER_RTS)
2161 imx_uart_start_tx(&sport->port);
2162 spin_unlock_irqrestore(&sport->port.lock, flags);
2163
2164 return HRTIMER_NORESTART;
2165}
2166
2167static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2168{
2169 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2170 unsigned long flags;
2171
2172 spin_lock_irqsave(&sport->port.lock, flags);
2173 if (sport->tx_state == WAIT_AFTER_SEND)
2174 imx_uart_stop_tx(&sport->port);
2175 spin_unlock_irqrestore(&sport->port.lock, flags);
2176
2177 return HRTIMER_NORESTART;
2178}
2179
2180/* Default RX DMA buffer configuration */
2181#define RX_DMA_PERIODS 16
2182#define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4)
2183
2184static int imx_uart_probe(struct platform_device *pdev)
2185{
2186 struct device_node *np = pdev->dev.of_node;
2187 struct imx_port *sport;
2188 void __iomem *base;
2189 u32 dma_buf_conf[2];
2190 int ret = 0;
2191 u32 ucr1;
2192 struct resource *res;
2193 int txirq, rxirq, rtsirq;
2194
2195 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2196 if (!sport)
2197 return -ENOMEM;
2198
2199 sport->devdata = of_device_get_match_data(&pdev->dev);
2200
2201 ret = of_alias_get_id(np, "serial");
2202 if (ret < 0) {
2203 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2204 return ret;
2205 }
2206 sport->port.line = ret;
2207
2208 if (of_get_property(np, "uart-has-rtscts", NULL) ||
2209 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
2210 sport->have_rtscts = 1;
2211
2212 if (of_get_property(np, "fsl,dte-mode", NULL))
2213 sport->dte_mode = 1;
2214
2215 if (of_get_property(np, "rts-gpios", NULL))
2216 sport->have_rtsgpio = 1;
2217
2218 if (of_get_property(np, "fsl,inverted-tx", NULL))
2219 sport->inverted_tx = 1;
2220
2221 if (of_get_property(np, "fsl,inverted-rx", NULL))
2222 sport->inverted_rx = 1;
2223
2224 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) {
2225 sport->rx_period_length = dma_buf_conf[0];
2226 sport->rx_periods = dma_buf_conf[1];
2227 } else {
2228 sport->rx_period_length = RX_DMA_PERIOD_LEN;
2229 sport->rx_periods = RX_DMA_PERIODS;
2230 }
2231
2232 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2233 dev_err(&pdev->dev, "serial%d out of range\n",
2234 sport->port.line);
2235 return -EINVAL;
2236 }
2237
2238 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2239 base = devm_ioremap_resource(&pdev->dev, res);
2240 if (IS_ERR(base))
2241 return PTR_ERR(base);
2242
2243 rxirq = platform_get_irq(pdev, 0);
2244 if (rxirq < 0)
2245 return rxirq;
2246 txirq = platform_get_irq_optional(pdev, 1);
2247 rtsirq = platform_get_irq_optional(pdev, 2);
2248
2249 sport->port.dev = &pdev->dev;
2250 sport->port.mapbase = res->start;
2251 sport->port.membase = base;
2252 sport->port.type = PORT_IMX;
2253 sport->port.iotype = UPIO_MEM;
2254 sport->port.irq = rxirq;
2255 sport->port.fifosize = 32;
2256 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2257 sport->port.ops = &imx_uart_pops;
2258 sport->port.rs485_config = imx_uart_rs485_config;
2259 sport->port.flags = UPF_BOOT_AUTOCONF;
2260 timer_setup(&sport->timer, imx_uart_timeout, 0);
2261
2262 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2263 if (IS_ERR(sport->gpios))
2264 return PTR_ERR(sport->gpios);
2265
2266 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2267 if (IS_ERR(sport->clk_ipg)) {
2268 ret = PTR_ERR(sport->clk_ipg);
2269 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2270 return ret;
2271 }
2272
2273 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2274 if (IS_ERR(sport->clk_per)) {
2275 ret = PTR_ERR(sport->clk_per);
2276 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2277 return ret;
2278 }
2279
2280 sport->port.uartclk = clk_get_rate(sport->clk_per);
2281
2282 /* For register access, we only need to enable the ipg clock. */
2283 ret = clk_prepare_enable(sport->clk_ipg);
2284 if (ret) {
2285 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2286 return ret;
2287 }
2288
2289 /* initialize shadow register values */
2290 sport->ucr1 = readl(sport->port.membase + UCR1);
2291 sport->ucr2 = readl(sport->port.membase + UCR2);
2292 sport->ucr3 = readl(sport->port.membase + UCR3);
2293 sport->ucr4 = readl(sport->port.membase + UCR4);
2294 sport->ufcr = readl(sport->port.membase + UFCR);
2295
2296 ret = uart_get_rs485_mode(&sport->port);
2297 if (ret) {
2298 clk_disable_unprepare(sport->clk_ipg);
2299 return ret;
2300 }
2301
2302 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2303 (!sport->have_rtscts && !sport->have_rtsgpio))
2304 dev_err(&pdev->dev, "no RTS control, disabling rs485\n");
2305
2306 /*
2307 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2308 * signal cannot be set low during transmission in case the
2309 * receiver is off (limitation of the i.MX UART IP).
2310 */
2311 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2312 sport->have_rtscts && !sport->have_rtsgpio &&
2313 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2314 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2315 dev_err(&pdev->dev,
2316 "low-active RTS not possible when receiver is off, enabling receiver\n");
2317
2318 imx_uart_rs485_config(&sport->port, &sport->port.rs485);
2319
2320 /* Disable interrupts before requesting them */
2321 ucr1 = imx_uart_readl(sport, UCR1);
2322 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2323 imx_uart_writel(sport, ucr1, UCR1);
2324
2325 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2326 /*
2327 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2328 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2329 * and DCD (when they are outputs) or enables the respective
2330 * irqs. So set this bit early, i.e. before requesting irqs.
2331 */
2332 u32 ufcr = imx_uart_readl(sport, UFCR);
2333 if (!(ufcr & UFCR_DCEDTE))
2334 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2335
2336 /*
2337 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2338 * enabled later because they cannot be cleared
2339 * (confirmed on i.MX25) which makes them unusable.
2340 */
2341 imx_uart_writel(sport,
2342 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2343 UCR3);
2344
2345 } else {
2346 u32 ucr3 = UCR3_DSR;
2347 u32 ufcr = imx_uart_readl(sport, UFCR);
2348 if (ufcr & UFCR_DCEDTE)
2349 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2350
2351 if (!imx_uart_is_imx1(sport))
2352 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2353 imx_uart_writel(sport, ucr3, UCR3);
2354 }
2355
2356 clk_disable_unprepare(sport->clk_ipg);
2357
2358 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2359 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2360 sport->trigger_start_tx.function = imx_trigger_start_tx;
2361 sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2362
2363 /*
2364 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2365 * chips only have one interrupt.
2366 */
2367 if (txirq > 0) {
2368 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2369 dev_name(&pdev->dev), sport);
2370 if (ret) {
2371 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2372 ret);
2373 return ret;
2374 }
2375
2376 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2377 dev_name(&pdev->dev), sport);
2378 if (ret) {
2379 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2380 ret);
2381 return ret;
2382 }
2383
2384 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2385 dev_name(&pdev->dev), sport);
2386 if (ret) {
2387 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2388 ret);
2389 return ret;
2390 }
2391 } else {
2392 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2393 dev_name(&pdev->dev), sport);
2394 if (ret) {
2395 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2396 return ret;
2397 }
2398 }
2399
2400 imx_uart_ports[sport->port.line] = sport;
2401
2402 platform_set_drvdata(pdev, sport);
2403
2404 return uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2405}
2406
2407static int imx_uart_remove(struct platform_device *pdev)
2408{
2409 struct imx_port *sport = platform_get_drvdata(pdev);
2410
2411 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2412}
2413
2414static void imx_uart_restore_context(struct imx_port *sport)
2415{
2416 unsigned long flags;
2417
2418 spin_lock_irqsave(&sport->port.lock, flags);
2419 if (!sport->context_saved) {
2420 spin_unlock_irqrestore(&sport->port.lock, flags);
2421 return;
2422 }
2423
2424 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2425 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2426 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2427 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2428 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2429 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2430 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2431 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2432 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2433 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2434 sport->context_saved = false;
2435 spin_unlock_irqrestore(&sport->port.lock, flags);
2436}
2437
2438static void imx_uart_save_context(struct imx_port *sport)
2439{
2440 unsigned long flags;
2441
2442 /* Save necessary regs */
2443 spin_lock_irqsave(&sport->port.lock, flags);
2444 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2445 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2446 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2447 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2448 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2449 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2450 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2451 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2452 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2453 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2454 sport->context_saved = true;
2455 spin_unlock_irqrestore(&sport->port.lock, flags);
2456}
2457
2458static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2459{
2460 u32 ucr3;
2461
2462 ucr3 = imx_uart_readl(sport, UCR3);
2463 if (on) {
2464 imx_uart_writel(sport, USR1_AWAKE, USR1);
2465 ucr3 |= UCR3_AWAKEN;
2466 } else {
2467 ucr3 &= ~UCR3_AWAKEN;
2468 }
2469 imx_uart_writel(sport, ucr3, UCR3);
2470
2471 if (sport->have_rtscts) {
2472 u32 ucr1 = imx_uart_readl(sport, UCR1);
2473 if (on)
2474 ucr1 |= UCR1_RTSDEN;
2475 else
2476 ucr1 &= ~UCR1_RTSDEN;
2477 imx_uart_writel(sport, ucr1, UCR1);
2478 }
2479}
2480
2481static int imx_uart_suspend_noirq(struct device *dev)
2482{
2483 struct imx_port *sport = dev_get_drvdata(dev);
2484
2485 imx_uart_save_context(sport);
2486
2487 clk_disable(sport->clk_ipg);
2488
2489 pinctrl_pm_select_sleep_state(dev);
2490
2491 return 0;
2492}
2493
2494static int imx_uart_resume_noirq(struct device *dev)
2495{
2496 struct imx_port *sport = dev_get_drvdata(dev);
2497 int ret;
2498
2499 pinctrl_pm_select_default_state(dev);
2500
2501 ret = clk_enable(sport->clk_ipg);
2502 if (ret)
2503 return ret;
2504
2505 imx_uart_restore_context(sport);
2506
2507 return 0;
2508}
2509
2510static int imx_uart_suspend(struct device *dev)
2511{
2512 struct imx_port *sport = dev_get_drvdata(dev);
2513 int ret;
2514
2515 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2516 disable_irq(sport->port.irq);
2517
2518 ret = clk_prepare_enable(sport->clk_ipg);
2519 if (ret)
2520 return ret;
2521
2522 /* enable wakeup from i.MX UART */
2523 imx_uart_enable_wakeup(sport, true);
2524
2525 return 0;
2526}
2527
2528static int imx_uart_resume(struct device *dev)
2529{
2530 struct imx_port *sport = dev_get_drvdata(dev);
2531
2532 /* disable wakeup from i.MX UART */
2533 imx_uart_enable_wakeup(sport, false);
2534
2535 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2536 enable_irq(sport->port.irq);
2537
2538 clk_disable_unprepare(sport->clk_ipg);
2539
2540 return 0;
2541}
2542
2543static int imx_uart_freeze(struct device *dev)
2544{
2545 struct imx_port *sport = dev_get_drvdata(dev);
2546
2547 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2548
2549 return clk_prepare_enable(sport->clk_ipg);
2550}
2551
2552static int imx_uart_thaw(struct device *dev)
2553{
2554 struct imx_port *sport = dev_get_drvdata(dev);
2555
2556 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2557
2558 clk_disable_unprepare(sport->clk_ipg);
2559
2560 return 0;
2561}
2562
2563static const struct dev_pm_ops imx_uart_pm_ops = {
2564 .suspend_noirq = imx_uart_suspend_noirq,
2565 .resume_noirq = imx_uart_resume_noirq,
2566 .freeze_noirq = imx_uart_suspend_noirq,
2567 .restore_noirq = imx_uart_resume_noirq,
2568 .suspend = imx_uart_suspend,
2569 .resume = imx_uart_resume,
2570 .freeze = imx_uart_freeze,
2571 .thaw = imx_uart_thaw,
2572 .restore = imx_uart_thaw,
2573};
2574
2575static struct platform_driver imx_uart_platform_driver = {
2576 .probe = imx_uart_probe,
2577 .remove = imx_uart_remove,
2578
2579 .driver = {
2580 .name = "imx-uart",
2581 .of_match_table = imx_uart_dt_ids,
2582 .pm = &imx_uart_pm_ops,
2583 },
2584};
2585
2586static int __init imx_uart_init(void)
2587{
2588 int ret = uart_register_driver(&imx_uart_uart_driver);
2589
2590 if (ret)
2591 return ret;
2592
2593 ret = platform_driver_register(&imx_uart_platform_driver);
2594 if (ret != 0)
2595 uart_unregister_driver(&imx_uart_uart_driver);
2596
2597 return ret;
2598}
2599
2600static void __exit imx_uart_exit(void)
2601{
2602 platform_driver_unregister(&imx_uart_platform_driver);
2603 uart_unregister_driver(&imx_uart_uart_driver);
2604}
2605
2606module_init(imx_uart_init);
2607module_exit(imx_uart_exit);
2608
2609MODULE_AUTHOR("Sascha Hauer");
2610MODULE_DESCRIPTION("IMX generic serial port driver");
2611MODULE_LICENSE("GPL");
2612MODULE_ALIAS("platform:imx-uart");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11#include <linux/module.h>
12#include <linux/ioport.h>
13#include <linux/init.h>
14#include <linux/console.h>
15#include <linux/sysrq.h>
16#include <linux/platform_device.h>
17#include <linux/tty.h>
18#include <linux/tty_flip.h>
19#include <linux/serial_core.h>
20#include <linux/serial.h>
21#include <linux/clk.h>
22#include <linux/delay.h>
23#include <linux/ktime.h>
24#include <linux/pinctrl/consumer.h>
25#include <linux/rational.h>
26#include <linux/slab.h>
27#include <linux/of.h>
28#include <linux/of_device.h>
29#include <linux/io.h>
30#include <linux/dma-mapping.h>
31
32#include <asm/irq.h>
33#include <linux/dma/imx-dma.h>
34
35#include "serial_mctrl_gpio.h"
36
37/* Register definitions */
38#define URXD0 0x0 /* Receiver Register */
39#define URTX0 0x40 /* Transmitter Register */
40#define UCR1 0x80 /* Control Register 1 */
41#define UCR2 0x84 /* Control Register 2 */
42#define UCR3 0x88 /* Control Register 3 */
43#define UCR4 0x8c /* Control Register 4 */
44#define UFCR 0x90 /* FIFO Control Register */
45#define USR1 0x94 /* Status Register 1 */
46#define USR2 0x98 /* Status Register 2 */
47#define UESC 0x9c /* Escape Character Register */
48#define UTIM 0xa0 /* Escape Timer Register */
49#define UBIR 0xa4 /* BRM Incremental Register */
50#define UBMR 0xa8 /* BRM Modulator Register */
51#define UBRC 0xac /* Baud Rate Count Register */
52#define IMX21_ONEMS 0xb0 /* One Millisecond register */
53#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
54#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
55
56/* UART Control Register Bit Fields.*/
57#define URXD_DUMMY_READ (1<<16)
58#define URXD_CHARRDY (1<<15)
59#define URXD_ERR (1<<14)
60#define URXD_OVRRUN (1<<13)
61#define URXD_FRMERR (1<<12)
62#define URXD_BRK (1<<11)
63#define URXD_PRERR (1<<10)
64#define URXD_RX_DATA (0xFF<<0)
65#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
66#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
67#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
68#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
69#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
70#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
71#define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
72#define UCR1_IREN (1<<7) /* Infrared interface enable */
73#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
74#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
75#define UCR1_SNDBRK (1<<4) /* Send break */
76#define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
77#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
78#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
79#define UCR1_DOZE (1<<1) /* Doze */
80#define UCR1_UARTEN (1<<0) /* UART enabled */
81#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
82#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
83#define UCR2_CTSC (1<<13) /* CTS pin control */
84#define UCR2_CTS (1<<12) /* Clear to send */
85#define UCR2_ESCEN (1<<11) /* Escape enable */
86#define UCR2_PREN (1<<8) /* Parity enable */
87#define UCR2_PROE (1<<7) /* Parity odd/even */
88#define UCR2_STPB (1<<6) /* Stop */
89#define UCR2_WS (1<<5) /* Word size */
90#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
91#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
92#define UCR2_TXEN (1<<2) /* Transmitter enabled */
93#define UCR2_RXEN (1<<1) /* Receiver enabled */
94#define UCR2_SRST (1<<0) /* SW reset */
95#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
96#define UCR3_PARERREN (1<<12) /* Parity enable */
97#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
98#define UCR3_DSR (1<<10) /* Data set ready */
99#define UCR3_DCD (1<<9) /* Data carrier detect */
100#define UCR3_RI (1<<8) /* Ring indicator */
101#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
102#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
103#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
104#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
105#define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
106#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
107#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
108#define UCR3_BPEN (1<<0) /* Preset registers enable */
109#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
110#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
111#define UCR4_INVR (1<<9) /* Inverted infrared reception */
112#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
113#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
114#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
115#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
116#define UCR4_IRSC (1<<5) /* IR special case */
117#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
118#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
119#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
120#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
121#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
122#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
123#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
124#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
125#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
126#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
127#define USR1_RTSS (1<<14) /* RTS pin status */
128#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
129#define USR1_RTSD (1<<12) /* RTS delta */
130#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
131#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
132#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
133#define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
134#define USR1_DTRD (1<<7) /* DTR Delta */
135#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
136#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
137#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
138#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
139#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
140#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
141#define USR2_IDLE (1<<12) /* Idle condition */
142#define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
143#define USR2_RIIN (1<<9) /* Ring Indicator Input */
144#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
145#define USR2_WAKE (1<<7) /* Wake */
146#define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
147#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
148#define USR2_TXDC (1<<3) /* Transmitter complete */
149#define USR2_BRCD (1<<2) /* Break condition */
150#define USR2_ORE (1<<1) /* Overrun error */
151#define USR2_RDR (1<<0) /* Recv data ready */
152#define UTS_FRCPERR (1<<13) /* Force parity error */
153#define UTS_LOOP (1<<12) /* Loop tx and rx */
154#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
155#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
156#define UTS_TXFULL (1<<4) /* TxFIFO full */
157#define UTS_RXFULL (1<<3) /* RxFIFO full */
158#define UTS_SOFTRST (1<<0) /* Software reset */
159
160/* We've been assigned a range on the "Low-density serial ports" major */
161#define SERIAL_IMX_MAJOR 207
162#define MINOR_START 16
163#define DEV_NAME "ttymxc"
164
165/*
166 * This determines how often we check the modem status signals
167 * for any change. They generally aren't connected to an IRQ
168 * so we have to poll them. We also check immediately before
169 * filling the TX fifo incase CTS has been dropped.
170 */
171#define MCTRL_TIMEOUT (250*HZ/1000)
172
173#define DRIVER_NAME "IMX-uart"
174
175#define UART_NR 8
176
177/* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
178enum imx_uart_type {
179 IMX1_UART,
180 IMX21_UART,
181 IMX53_UART,
182 IMX6Q_UART,
183};
184
185/* device type dependent stuff */
186struct imx_uart_data {
187 unsigned uts_reg;
188 enum imx_uart_type devtype;
189};
190
191enum imx_tx_state {
192 OFF,
193 WAIT_AFTER_RTS,
194 SEND,
195 WAIT_AFTER_SEND,
196};
197
198struct imx_port {
199 struct uart_port port;
200 struct timer_list timer;
201 unsigned int old_status;
202 unsigned int have_rtscts:1;
203 unsigned int have_rtsgpio:1;
204 unsigned int dte_mode:1;
205 unsigned int inverted_tx:1;
206 unsigned int inverted_rx:1;
207 struct clk *clk_ipg;
208 struct clk *clk_per;
209 const struct imx_uart_data *devdata;
210
211 struct mctrl_gpios *gpios;
212
213 /* shadow registers */
214 unsigned int ucr1;
215 unsigned int ucr2;
216 unsigned int ucr3;
217 unsigned int ucr4;
218 unsigned int ufcr;
219
220 /* DMA fields */
221 unsigned int dma_is_enabled:1;
222 unsigned int dma_is_rxing:1;
223 unsigned int dma_is_txing:1;
224 struct dma_chan *dma_chan_rx, *dma_chan_tx;
225 struct scatterlist rx_sgl, tx_sgl[2];
226 void *rx_buf;
227 struct circ_buf rx_ring;
228 unsigned int rx_buf_size;
229 unsigned int rx_period_length;
230 unsigned int rx_periods;
231 dma_cookie_t rx_cookie;
232 unsigned int tx_bytes;
233 unsigned int dma_tx_nents;
234 unsigned int saved_reg[10];
235 bool context_saved;
236
237 enum imx_tx_state tx_state;
238 struct hrtimer trigger_start_tx;
239 struct hrtimer trigger_stop_tx;
240};
241
242struct imx_port_ucrs {
243 unsigned int ucr1;
244 unsigned int ucr2;
245 unsigned int ucr3;
246};
247
248static struct imx_uart_data imx_uart_devdata[] = {
249 [IMX1_UART] = {
250 .uts_reg = IMX1_UTS,
251 .devtype = IMX1_UART,
252 },
253 [IMX21_UART] = {
254 .uts_reg = IMX21_UTS,
255 .devtype = IMX21_UART,
256 },
257 [IMX53_UART] = {
258 .uts_reg = IMX21_UTS,
259 .devtype = IMX53_UART,
260 },
261 [IMX6Q_UART] = {
262 .uts_reg = IMX21_UTS,
263 .devtype = IMX6Q_UART,
264 },
265};
266
267static const struct of_device_id imx_uart_dt_ids[] = {
268 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
269 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
270 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
271 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
272 { /* sentinel */ }
273};
274MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
275
276static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
277{
278 switch (offset) {
279 case UCR1:
280 sport->ucr1 = val;
281 break;
282 case UCR2:
283 sport->ucr2 = val;
284 break;
285 case UCR3:
286 sport->ucr3 = val;
287 break;
288 case UCR4:
289 sport->ucr4 = val;
290 break;
291 case UFCR:
292 sport->ufcr = val;
293 break;
294 default:
295 break;
296 }
297 writel(val, sport->port.membase + offset);
298}
299
300static u32 imx_uart_readl(struct imx_port *sport, u32 offset)
301{
302 switch (offset) {
303 case UCR1:
304 return sport->ucr1;
305 break;
306 case UCR2:
307 /*
308 * UCR2_SRST is the only bit in the cached registers that might
309 * differ from the value that was last written. As it only
310 * automatically becomes one after being cleared, reread
311 * conditionally.
312 */
313 if (!(sport->ucr2 & UCR2_SRST))
314 sport->ucr2 = readl(sport->port.membase + offset);
315 return sport->ucr2;
316 break;
317 case UCR3:
318 return sport->ucr3;
319 break;
320 case UCR4:
321 return sport->ucr4;
322 break;
323 case UFCR:
324 return sport->ufcr;
325 break;
326 default:
327 return readl(sport->port.membase + offset);
328 }
329}
330
331static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
332{
333 return sport->devdata->uts_reg;
334}
335
336static inline int imx_uart_is_imx1(struct imx_port *sport)
337{
338 return sport->devdata->devtype == IMX1_UART;
339}
340
341static inline int imx_uart_is_imx21(struct imx_port *sport)
342{
343 return sport->devdata->devtype == IMX21_UART;
344}
345
346static inline int imx_uart_is_imx53(struct imx_port *sport)
347{
348 return sport->devdata->devtype == IMX53_UART;
349}
350
351static inline int imx_uart_is_imx6q(struct imx_port *sport)
352{
353 return sport->devdata->devtype == IMX6Q_UART;
354}
355/*
356 * Save and restore functions for UCR1, UCR2 and UCR3 registers
357 */
358#if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
359static void imx_uart_ucrs_save(struct imx_port *sport,
360 struct imx_port_ucrs *ucr)
361{
362 /* save control registers */
363 ucr->ucr1 = imx_uart_readl(sport, UCR1);
364 ucr->ucr2 = imx_uart_readl(sport, UCR2);
365 ucr->ucr3 = imx_uart_readl(sport, UCR3);
366}
367
368static void imx_uart_ucrs_restore(struct imx_port *sport,
369 struct imx_port_ucrs *ucr)
370{
371 /* restore control registers */
372 imx_uart_writel(sport, ucr->ucr1, UCR1);
373 imx_uart_writel(sport, ucr->ucr2, UCR2);
374 imx_uart_writel(sport, ucr->ucr3, UCR3);
375}
376#endif
377
378/* called with port.lock taken and irqs caller dependent */
379static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
380{
381 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
382
383 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
384}
385
386/* called with port.lock taken and irqs caller dependent */
387static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
388{
389 *ucr2 &= ~UCR2_CTSC;
390 *ucr2 |= UCR2_CTS;
391
392 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
393}
394
395static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
396{
397 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
398}
399
400/* called with port.lock taken and irqs off */
401static void imx_uart_start_rx(struct uart_port *port)
402{
403 struct imx_port *sport = (struct imx_port *)port;
404 unsigned int ucr1, ucr2;
405
406 ucr1 = imx_uart_readl(sport, UCR1);
407 ucr2 = imx_uart_readl(sport, UCR2);
408
409 ucr2 |= UCR2_RXEN;
410
411 if (sport->dma_is_enabled) {
412 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
413 } else {
414 ucr1 |= UCR1_RRDYEN;
415 ucr2 |= UCR2_ATEN;
416 }
417
418 /* Write UCR2 first as it includes RXEN */
419 imx_uart_writel(sport, ucr2, UCR2);
420 imx_uart_writel(sport, ucr1, UCR1);
421}
422
423/* called with port.lock taken and irqs off */
424static void imx_uart_stop_tx(struct uart_port *port)
425{
426 struct imx_port *sport = (struct imx_port *)port;
427 u32 ucr1, ucr4, usr2;
428
429 if (sport->tx_state == OFF)
430 return;
431
432 /*
433 * We are maybe in the SMP context, so if the DMA TX thread is running
434 * on other cpu, we have to wait for it to finish.
435 */
436 if (sport->dma_is_txing)
437 return;
438
439 ucr1 = imx_uart_readl(sport, UCR1);
440 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
441
442 usr2 = imx_uart_readl(sport, USR2);
443 if (!(usr2 & USR2_TXDC)) {
444 /* The shifter is still busy, so retry once TC triggers */
445 return;
446 }
447
448 ucr4 = imx_uart_readl(sport, UCR4);
449 ucr4 &= ~UCR4_TCEN;
450 imx_uart_writel(sport, ucr4, UCR4);
451
452 /* in rs485 mode disable transmitter */
453 if (port->rs485.flags & SER_RS485_ENABLED) {
454 if (sport->tx_state == SEND) {
455 sport->tx_state = WAIT_AFTER_SEND;
456
457 if (port->rs485.delay_rts_after_send > 0) {
458 start_hrtimer_ms(&sport->trigger_stop_tx,
459 port->rs485.delay_rts_after_send);
460 return;
461 }
462
463 /* continue without any delay */
464 }
465
466 if (sport->tx_state == WAIT_AFTER_RTS ||
467 sport->tx_state == WAIT_AFTER_SEND) {
468 u32 ucr2;
469
470 hrtimer_try_to_cancel(&sport->trigger_start_tx);
471
472 ucr2 = imx_uart_readl(sport, UCR2);
473 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
474 imx_uart_rts_active(sport, &ucr2);
475 else
476 imx_uart_rts_inactive(sport, &ucr2);
477 imx_uart_writel(sport, ucr2, UCR2);
478
479 imx_uart_start_rx(port);
480
481 sport->tx_state = OFF;
482 }
483 } else {
484 sport->tx_state = OFF;
485 }
486}
487
488/* called with port.lock taken and irqs off */
489static void imx_uart_stop_rx(struct uart_port *port)
490{
491 struct imx_port *sport = (struct imx_port *)port;
492 u32 ucr1, ucr2, ucr4, uts;
493
494 ucr1 = imx_uart_readl(sport, UCR1);
495 ucr2 = imx_uart_readl(sport, UCR2);
496 ucr4 = imx_uart_readl(sport, UCR4);
497
498 if (sport->dma_is_enabled) {
499 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
500 } else {
501 ucr1 &= ~UCR1_RRDYEN;
502 ucr2 &= ~UCR2_ATEN;
503 ucr4 &= ~UCR4_OREN;
504 }
505 imx_uart_writel(sport, ucr1, UCR1);
506 imx_uart_writel(sport, ucr4, UCR4);
507
508 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
509 if (port->rs485.flags & SER_RS485_ENABLED &&
510 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
511 sport->have_rtscts && !sport->have_rtsgpio) {
512 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
513 uts |= UTS_LOOP;
514 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
515 ucr2 |= UCR2_RXEN;
516 } else {
517 ucr2 &= ~UCR2_RXEN;
518 }
519
520 imx_uart_writel(sport, ucr2, UCR2);
521}
522
523/* called with port.lock taken and irqs off */
524static void imx_uart_enable_ms(struct uart_port *port)
525{
526 struct imx_port *sport = (struct imx_port *)port;
527
528 mod_timer(&sport->timer, jiffies);
529
530 mctrl_gpio_enable_ms(sport->gpios);
531}
532
533static void imx_uart_dma_tx(struct imx_port *sport);
534
535/* called with port.lock taken and irqs off */
536static inline void imx_uart_transmit_buffer(struct imx_port *sport)
537{
538 struct circ_buf *xmit = &sport->port.state->xmit;
539
540 if (sport->port.x_char) {
541 /* Send next char */
542 imx_uart_writel(sport, sport->port.x_char, URTX0);
543 sport->port.icount.tx++;
544 sport->port.x_char = 0;
545 return;
546 }
547
548 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
549 imx_uart_stop_tx(&sport->port);
550 return;
551 }
552
553 if (sport->dma_is_enabled) {
554 u32 ucr1;
555 /*
556 * We've just sent a X-char Ensure the TX DMA is enabled
557 * and the TX IRQ is disabled.
558 **/
559 ucr1 = imx_uart_readl(sport, UCR1);
560 ucr1 &= ~UCR1_TRDYEN;
561 if (sport->dma_is_txing) {
562 ucr1 |= UCR1_TXDMAEN;
563 imx_uart_writel(sport, ucr1, UCR1);
564 } else {
565 imx_uart_writel(sport, ucr1, UCR1);
566 imx_uart_dma_tx(sport);
567 }
568
569 return;
570 }
571
572 while (!uart_circ_empty(xmit) &&
573 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
574 /* send xmit->buf[xmit->tail]
575 * out the port here */
576 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
577 uart_xmit_advance(&sport->port, 1);
578 }
579
580 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
581 uart_write_wakeup(&sport->port);
582
583 if (uart_circ_empty(xmit))
584 imx_uart_stop_tx(&sport->port);
585}
586
587static void imx_uart_dma_tx_callback(void *data)
588{
589 struct imx_port *sport = data;
590 struct scatterlist *sgl = &sport->tx_sgl[0];
591 struct circ_buf *xmit = &sport->port.state->xmit;
592 unsigned long flags;
593 u32 ucr1;
594
595 spin_lock_irqsave(&sport->port.lock, flags);
596
597 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
598
599 ucr1 = imx_uart_readl(sport, UCR1);
600 ucr1 &= ~UCR1_TXDMAEN;
601 imx_uart_writel(sport, ucr1, UCR1);
602
603 uart_xmit_advance(&sport->port, sport->tx_bytes);
604
605 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
606
607 sport->dma_is_txing = 0;
608
609 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
610 uart_write_wakeup(&sport->port);
611
612 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
613 imx_uart_dma_tx(sport);
614 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
615 u32 ucr4 = imx_uart_readl(sport, UCR4);
616 ucr4 |= UCR4_TCEN;
617 imx_uart_writel(sport, ucr4, UCR4);
618 }
619
620 spin_unlock_irqrestore(&sport->port.lock, flags);
621}
622
623/* called with port.lock taken and irqs off */
624static void imx_uart_dma_tx(struct imx_port *sport)
625{
626 struct circ_buf *xmit = &sport->port.state->xmit;
627 struct scatterlist *sgl = sport->tx_sgl;
628 struct dma_async_tx_descriptor *desc;
629 struct dma_chan *chan = sport->dma_chan_tx;
630 struct device *dev = sport->port.dev;
631 u32 ucr1, ucr4;
632 int ret;
633
634 if (sport->dma_is_txing)
635 return;
636
637 ucr4 = imx_uart_readl(sport, UCR4);
638 ucr4 &= ~UCR4_TCEN;
639 imx_uart_writel(sport, ucr4, UCR4);
640
641 sport->tx_bytes = uart_circ_chars_pending(xmit);
642
643 if (xmit->tail < xmit->head || xmit->head == 0) {
644 sport->dma_tx_nents = 1;
645 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
646 } else {
647 sport->dma_tx_nents = 2;
648 sg_init_table(sgl, 2);
649 sg_set_buf(sgl, xmit->buf + xmit->tail,
650 UART_XMIT_SIZE - xmit->tail);
651 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
652 }
653
654 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
655 if (ret == 0) {
656 dev_err(dev, "DMA mapping error for TX.\n");
657 return;
658 }
659 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
660 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
661 if (!desc) {
662 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
663 DMA_TO_DEVICE);
664 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
665 return;
666 }
667 desc->callback = imx_uart_dma_tx_callback;
668 desc->callback_param = sport;
669
670 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
671 uart_circ_chars_pending(xmit));
672
673 ucr1 = imx_uart_readl(sport, UCR1);
674 ucr1 |= UCR1_TXDMAEN;
675 imx_uart_writel(sport, ucr1, UCR1);
676
677 /* fire it */
678 sport->dma_is_txing = 1;
679 dmaengine_submit(desc);
680 dma_async_issue_pending(chan);
681 return;
682}
683
684/* called with port.lock taken and irqs off */
685static void imx_uart_start_tx(struct uart_port *port)
686{
687 struct imx_port *sport = (struct imx_port *)port;
688 u32 ucr1;
689
690 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
691 return;
692
693 /*
694 * We cannot simply do nothing here if sport->tx_state == SEND already
695 * because UCR1_TXMPTYEN might already have been cleared in
696 * imx_uart_stop_tx(), but tx_state is still SEND.
697 */
698
699 if (port->rs485.flags & SER_RS485_ENABLED) {
700 if (sport->tx_state == OFF) {
701 u32 ucr2 = imx_uart_readl(sport, UCR2);
702 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
703 imx_uart_rts_active(sport, &ucr2);
704 else
705 imx_uart_rts_inactive(sport, &ucr2);
706 imx_uart_writel(sport, ucr2, UCR2);
707
708 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
709 imx_uart_stop_rx(port);
710
711 sport->tx_state = WAIT_AFTER_RTS;
712
713 if (port->rs485.delay_rts_before_send > 0) {
714 start_hrtimer_ms(&sport->trigger_start_tx,
715 port->rs485.delay_rts_before_send);
716 return;
717 }
718
719 /* continue without any delay */
720 }
721
722 if (sport->tx_state == WAIT_AFTER_SEND
723 || sport->tx_state == WAIT_AFTER_RTS) {
724
725 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
726
727 /*
728 * Enable transmitter and shifter empty irq only if DMA
729 * is off. In the DMA case this is done in the
730 * tx-callback.
731 */
732 if (!sport->dma_is_enabled) {
733 u32 ucr4 = imx_uart_readl(sport, UCR4);
734 ucr4 |= UCR4_TCEN;
735 imx_uart_writel(sport, ucr4, UCR4);
736 }
737
738 sport->tx_state = SEND;
739 }
740 } else {
741 sport->tx_state = SEND;
742 }
743
744 if (!sport->dma_is_enabled) {
745 ucr1 = imx_uart_readl(sport, UCR1);
746 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
747 }
748
749 if (sport->dma_is_enabled) {
750 if (sport->port.x_char) {
751 /* We have X-char to send, so enable TX IRQ and
752 * disable TX DMA to let TX interrupt to send X-char */
753 ucr1 = imx_uart_readl(sport, UCR1);
754 ucr1 &= ~UCR1_TXDMAEN;
755 ucr1 |= UCR1_TRDYEN;
756 imx_uart_writel(sport, ucr1, UCR1);
757 return;
758 }
759
760 if (!uart_circ_empty(&port->state->xmit) &&
761 !uart_tx_stopped(port))
762 imx_uart_dma_tx(sport);
763 return;
764 }
765}
766
767static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
768{
769 struct imx_port *sport = dev_id;
770 u32 usr1;
771
772 imx_uart_writel(sport, USR1_RTSD, USR1);
773 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
774 uart_handle_cts_change(&sport->port, !!usr1);
775 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
776
777 return IRQ_HANDLED;
778}
779
780static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
781{
782 struct imx_port *sport = dev_id;
783 irqreturn_t ret;
784
785 spin_lock(&sport->port.lock);
786
787 ret = __imx_uart_rtsint(irq, dev_id);
788
789 spin_unlock(&sport->port.lock);
790
791 return ret;
792}
793
794static irqreturn_t imx_uart_txint(int irq, void *dev_id)
795{
796 struct imx_port *sport = dev_id;
797
798 spin_lock(&sport->port.lock);
799 imx_uart_transmit_buffer(sport);
800 spin_unlock(&sport->port.lock);
801 return IRQ_HANDLED;
802}
803
804static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
805{
806 struct imx_port *sport = dev_id;
807 unsigned int rx, flg, ignored = 0;
808 struct tty_port *port = &sport->port.state->port;
809
810 while (imx_uart_readl(sport, USR2) & USR2_RDR) {
811 u32 usr2;
812
813 flg = TTY_NORMAL;
814 sport->port.icount.rx++;
815
816 rx = imx_uart_readl(sport, URXD0);
817
818 usr2 = imx_uart_readl(sport, USR2);
819 if (usr2 & USR2_BRCD) {
820 imx_uart_writel(sport, USR2_BRCD, USR2);
821 if (uart_handle_break(&sport->port))
822 continue;
823 }
824
825 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
826 continue;
827
828 if (unlikely(rx & URXD_ERR)) {
829 if (rx & URXD_BRK)
830 sport->port.icount.brk++;
831 else if (rx & URXD_PRERR)
832 sport->port.icount.parity++;
833 else if (rx & URXD_FRMERR)
834 sport->port.icount.frame++;
835 if (rx & URXD_OVRRUN)
836 sport->port.icount.overrun++;
837
838 if (rx & sport->port.ignore_status_mask) {
839 if (++ignored > 100)
840 goto out;
841 continue;
842 }
843
844 rx &= (sport->port.read_status_mask | 0xFF);
845
846 if (rx & URXD_BRK)
847 flg = TTY_BREAK;
848 else if (rx & URXD_PRERR)
849 flg = TTY_PARITY;
850 else if (rx & URXD_FRMERR)
851 flg = TTY_FRAME;
852 if (rx & URXD_OVRRUN)
853 flg = TTY_OVERRUN;
854
855 sport->port.sysrq = 0;
856 }
857
858 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
859 goto out;
860
861 if (tty_insert_flip_char(port, rx, flg) == 0)
862 sport->port.icount.buf_overrun++;
863 }
864
865out:
866 tty_flip_buffer_push(port);
867
868 return IRQ_HANDLED;
869}
870
871static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
872{
873 struct imx_port *sport = dev_id;
874 irqreturn_t ret;
875
876 spin_lock(&sport->port.lock);
877
878 ret = __imx_uart_rxint(irq, dev_id);
879
880 spin_unlock(&sport->port.lock);
881
882 return ret;
883}
884
885static void imx_uart_clear_rx_errors(struct imx_port *sport);
886
887/*
888 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
889 */
890static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
891{
892 unsigned int tmp = TIOCM_DSR;
893 unsigned usr1 = imx_uart_readl(sport, USR1);
894 unsigned usr2 = imx_uart_readl(sport, USR2);
895
896 if (usr1 & USR1_RTSS)
897 tmp |= TIOCM_CTS;
898
899 /* in DCE mode DCDIN is always 0 */
900 if (!(usr2 & USR2_DCDIN))
901 tmp |= TIOCM_CAR;
902
903 if (sport->dte_mode)
904 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
905 tmp |= TIOCM_RI;
906
907 return tmp;
908}
909
910/*
911 * Handle any change of modem status signal since we were last called.
912 */
913static void imx_uart_mctrl_check(struct imx_port *sport)
914{
915 unsigned int status, changed;
916
917 status = imx_uart_get_hwmctrl(sport);
918 changed = status ^ sport->old_status;
919
920 if (changed == 0)
921 return;
922
923 sport->old_status = status;
924
925 if (changed & TIOCM_RI && status & TIOCM_RI)
926 sport->port.icount.rng++;
927 if (changed & TIOCM_DSR)
928 sport->port.icount.dsr++;
929 if (changed & TIOCM_CAR)
930 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
931 if (changed & TIOCM_CTS)
932 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
933
934 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
935}
936
937static irqreturn_t imx_uart_int(int irq, void *dev_id)
938{
939 struct imx_port *sport = dev_id;
940 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
941 irqreturn_t ret = IRQ_NONE;
942
943 spin_lock(&sport->port.lock);
944
945 usr1 = imx_uart_readl(sport, USR1);
946 usr2 = imx_uart_readl(sport, USR2);
947 ucr1 = imx_uart_readl(sport, UCR1);
948 ucr2 = imx_uart_readl(sport, UCR2);
949 ucr3 = imx_uart_readl(sport, UCR3);
950 ucr4 = imx_uart_readl(sport, UCR4);
951
952 /*
953 * Even if a condition is true that can trigger an irq only handle it if
954 * the respective irq source is enabled. This prevents some undesired
955 * actions, for example if a character that sits in the RX FIFO and that
956 * should be fetched via DMA is tried to be fetched using PIO. Or the
957 * receiver is currently off and so reading from URXD0 results in an
958 * exception. So just mask the (raw) status bits for disabled irqs.
959 */
960 if ((ucr1 & UCR1_RRDYEN) == 0)
961 usr1 &= ~USR1_RRDY;
962 if ((ucr2 & UCR2_ATEN) == 0)
963 usr1 &= ~USR1_AGTIM;
964 if ((ucr1 & UCR1_TRDYEN) == 0)
965 usr1 &= ~USR1_TRDY;
966 if ((ucr4 & UCR4_TCEN) == 0)
967 usr2 &= ~USR2_TXDC;
968 if ((ucr3 & UCR3_DTRDEN) == 0)
969 usr1 &= ~USR1_DTRD;
970 if ((ucr1 & UCR1_RTSDEN) == 0)
971 usr1 &= ~USR1_RTSD;
972 if ((ucr3 & UCR3_AWAKEN) == 0)
973 usr1 &= ~USR1_AWAKE;
974 if ((ucr4 & UCR4_OREN) == 0)
975 usr2 &= ~USR2_ORE;
976
977 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
978 imx_uart_writel(sport, USR1_AGTIM, USR1);
979
980 __imx_uart_rxint(irq, dev_id);
981 ret = IRQ_HANDLED;
982 }
983
984 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
985 imx_uart_transmit_buffer(sport);
986 ret = IRQ_HANDLED;
987 }
988
989 if (usr1 & USR1_DTRD) {
990 imx_uart_writel(sport, USR1_DTRD, USR1);
991
992 imx_uart_mctrl_check(sport);
993
994 ret = IRQ_HANDLED;
995 }
996
997 if (usr1 & USR1_RTSD) {
998 __imx_uart_rtsint(irq, dev_id);
999 ret = IRQ_HANDLED;
1000 }
1001
1002 if (usr1 & USR1_AWAKE) {
1003 imx_uart_writel(sport, USR1_AWAKE, USR1);
1004 ret = IRQ_HANDLED;
1005 }
1006
1007 if (usr2 & USR2_ORE) {
1008 sport->port.icount.overrun++;
1009 imx_uart_writel(sport, USR2_ORE, USR2);
1010 ret = IRQ_HANDLED;
1011 }
1012
1013 spin_unlock(&sport->port.lock);
1014
1015 return ret;
1016}
1017
1018/*
1019 * Return TIOCSER_TEMT when transmitter is not busy.
1020 */
1021static unsigned int imx_uart_tx_empty(struct uart_port *port)
1022{
1023 struct imx_port *sport = (struct imx_port *)port;
1024 unsigned int ret;
1025
1026 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1027
1028 /* If the TX DMA is working, return 0. */
1029 if (sport->dma_is_txing)
1030 ret = 0;
1031
1032 return ret;
1033}
1034
1035/* called with port.lock taken and irqs off */
1036static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1037{
1038 struct imx_port *sport = (struct imx_port *)port;
1039 unsigned int ret = imx_uart_get_hwmctrl(sport);
1040
1041 mctrl_gpio_get(sport->gpios, &ret);
1042
1043 return ret;
1044}
1045
1046/* called with port.lock taken and irqs off */
1047static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1048{
1049 struct imx_port *sport = (struct imx_port *)port;
1050 u32 ucr3, uts;
1051
1052 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1053 u32 ucr2;
1054
1055 /*
1056 * Turn off autoRTS if RTS is lowered and restore autoRTS
1057 * setting if RTS is raised.
1058 */
1059 ucr2 = imx_uart_readl(sport, UCR2);
1060 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1061 if (mctrl & TIOCM_RTS) {
1062 ucr2 |= UCR2_CTS;
1063 /*
1064 * UCR2_IRTS is unset if and only if the port is
1065 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1066 * to get the state to restore to.
1067 */
1068 if (!(ucr2 & UCR2_IRTS))
1069 ucr2 |= UCR2_CTSC;
1070 }
1071 imx_uart_writel(sport, ucr2, UCR2);
1072 }
1073
1074 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1075 if (!(mctrl & TIOCM_DTR))
1076 ucr3 |= UCR3_DSR;
1077 imx_uart_writel(sport, ucr3, UCR3);
1078
1079 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1080 if (mctrl & TIOCM_LOOP)
1081 uts |= UTS_LOOP;
1082 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1083
1084 mctrl_gpio_set(sport->gpios, mctrl);
1085}
1086
1087/*
1088 * Interrupts always disabled.
1089 */
1090static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1091{
1092 struct imx_port *sport = (struct imx_port *)port;
1093 unsigned long flags;
1094 u32 ucr1;
1095
1096 spin_lock_irqsave(&sport->port.lock, flags);
1097
1098 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1099
1100 if (break_state != 0)
1101 ucr1 |= UCR1_SNDBRK;
1102
1103 imx_uart_writel(sport, ucr1, UCR1);
1104
1105 spin_unlock_irqrestore(&sport->port.lock, flags);
1106}
1107
1108/*
1109 * This is our per-port timeout handler, for checking the
1110 * modem status signals.
1111 */
1112static void imx_uart_timeout(struct timer_list *t)
1113{
1114 struct imx_port *sport = from_timer(sport, t, timer);
1115 unsigned long flags;
1116
1117 if (sport->port.state) {
1118 spin_lock_irqsave(&sport->port.lock, flags);
1119 imx_uart_mctrl_check(sport);
1120 spin_unlock_irqrestore(&sport->port.lock, flags);
1121
1122 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1123 }
1124}
1125
1126/*
1127 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1128 * [1] the RX DMA buffer is full.
1129 * [2] the aging timer expires
1130 *
1131 * Condition [2] is triggered when a character has been sitting in the FIFO
1132 * for at least 8 byte durations.
1133 */
1134static void imx_uart_dma_rx_callback(void *data)
1135{
1136 struct imx_port *sport = data;
1137 struct dma_chan *chan = sport->dma_chan_rx;
1138 struct scatterlist *sgl = &sport->rx_sgl;
1139 struct tty_port *port = &sport->port.state->port;
1140 struct dma_tx_state state;
1141 struct circ_buf *rx_ring = &sport->rx_ring;
1142 enum dma_status status;
1143 unsigned int w_bytes = 0;
1144 unsigned int r_bytes;
1145 unsigned int bd_size;
1146
1147 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1148
1149 if (status == DMA_ERROR) {
1150 imx_uart_clear_rx_errors(sport);
1151 return;
1152 }
1153
1154 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1155
1156 /*
1157 * The state-residue variable represents the empty space
1158 * relative to the entire buffer. Taking this in consideration
1159 * the head is always calculated base on the buffer total
1160 * length - DMA transaction residue. The UART script from the
1161 * SDMA firmware will jump to the next buffer descriptor,
1162 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1163 * Taking this in consideration the tail is always at the
1164 * beginning of the buffer descriptor that contains the head.
1165 */
1166
1167 /* Calculate the head */
1168 rx_ring->head = sg_dma_len(sgl) - state.residue;
1169
1170 /* Calculate the tail. */
1171 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1172 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1173
1174 if (rx_ring->head <= sg_dma_len(sgl) &&
1175 rx_ring->head > rx_ring->tail) {
1176
1177 /* Move data from tail to head */
1178 r_bytes = rx_ring->head - rx_ring->tail;
1179
1180 /* CPU claims ownership of RX DMA buffer */
1181 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1182 DMA_FROM_DEVICE);
1183
1184 w_bytes = tty_insert_flip_string(port,
1185 sport->rx_buf + rx_ring->tail, r_bytes);
1186
1187 /* UART retrieves ownership of RX DMA buffer */
1188 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1189 DMA_FROM_DEVICE);
1190
1191 if (w_bytes != r_bytes)
1192 sport->port.icount.buf_overrun++;
1193
1194 sport->port.icount.rx += w_bytes;
1195 } else {
1196 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1197 WARN_ON(rx_ring->head <= rx_ring->tail);
1198 }
1199 }
1200
1201 if (w_bytes) {
1202 tty_flip_buffer_push(port);
1203 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1204 }
1205}
1206
1207static int imx_uart_start_rx_dma(struct imx_port *sport)
1208{
1209 struct scatterlist *sgl = &sport->rx_sgl;
1210 struct dma_chan *chan = sport->dma_chan_rx;
1211 struct device *dev = sport->port.dev;
1212 struct dma_async_tx_descriptor *desc;
1213 int ret;
1214
1215 sport->rx_ring.head = 0;
1216 sport->rx_ring.tail = 0;
1217
1218 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size);
1219 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1220 if (ret == 0) {
1221 dev_err(dev, "DMA mapping error for RX.\n");
1222 return -EINVAL;
1223 }
1224
1225 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1226 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1227 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1228
1229 if (!desc) {
1230 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1231 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1232 return -EINVAL;
1233 }
1234 desc->callback = imx_uart_dma_rx_callback;
1235 desc->callback_param = sport;
1236
1237 dev_dbg(dev, "RX: prepare for the DMA.\n");
1238 sport->dma_is_rxing = 1;
1239 sport->rx_cookie = dmaengine_submit(desc);
1240 dma_async_issue_pending(chan);
1241 return 0;
1242}
1243
1244static void imx_uart_clear_rx_errors(struct imx_port *sport)
1245{
1246 struct tty_port *port = &sport->port.state->port;
1247 u32 usr1, usr2;
1248
1249 usr1 = imx_uart_readl(sport, USR1);
1250 usr2 = imx_uart_readl(sport, USR2);
1251
1252 if (usr2 & USR2_BRCD) {
1253 sport->port.icount.brk++;
1254 imx_uart_writel(sport, USR2_BRCD, USR2);
1255 uart_handle_break(&sport->port);
1256 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1257 sport->port.icount.buf_overrun++;
1258 tty_flip_buffer_push(port);
1259 } else {
1260 if (usr1 & USR1_FRAMERR) {
1261 sport->port.icount.frame++;
1262 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1263 } else if (usr1 & USR1_PARITYERR) {
1264 sport->port.icount.parity++;
1265 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1266 }
1267 }
1268
1269 if (usr2 & USR2_ORE) {
1270 sport->port.icount.overrun++;
1271 imx_uart_writel(sport, USR2_ORE, USR2);
1272 }
1273
1274}
1275
1276#define TXTL_DEFAULT 2 /* reset default */
1277#define RXTL_DEFAULT 8 /* 8 characters or aging timer */
1278#define TXTL_DMA 8 /* DMA burst setting */
1279#define RXTL_DMA 9 /* DMA burst setting */
1280
1281static void imx_uart_setup_ufcr(struct imx_port *sport,
1282 unsigned char txwl, unsigned char rxwl)
1283{
1284 unsigned int val;
1285
1286 /* set receiver / transmitter trigger level */
1287 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1288 val |= txwl << UFCR_TXTL_SHF | rxwl;
1289 imx_uart_writel(sport, val, UFCR);
1290}
1291
1292static void imx_uart_dma_exit(struct imx_port *sport)
1293{
1294 if (sport->dma_chan_rx) {
1295 dmaengine_terminate_sync(sport->dma_chan_rx);
1296 dma_release_channel(sport->dma_chan_rx);
1297 sport->dma_chan_rx = NULL;
1298 sport->rx_cookie = -EINVAL;
1299 kfree(sport->rx_buf);
1300 sport->rx_buf = NULL;
1301 }
1302
1303 if (sport->dma_chan_tx) {
1304 dmaengine_terminate_sync(sport->dma_chan_tx);
1305 dma_release_channel(sport->dma_chan_tx);
1306 sport->dma_chan_tx = NULL;
1307 }
1308}
1309
1310static int imx_uart_dma_init(struct imx_port *sport)
1311{
1312 struct dma_slave_config slave_config = {};
1313 struct device *dev = sport->port.dev;
1314 int ret;
1315
1316 /* Prepare for RX : */
1317 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1318 if (!sport->dma_chan_rx) {
1319 dev_dbg(dev, "cannot get the DMA channel.\n");
1320 ret = -EINVAL;
1321 goto err;
1322 }
1323
1324 slave_config.direction = DMA_DEV_TO_MEM;
1325 slave_config.src_addr = sport->port.mapbase + URXD0;
1326 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1327 /* one byte less than the watermark level to enable the aging timer */
1328 slave_config.src_maxburst = RXTL_DMA - 1;
1329 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1330 if (ret) {
1331 dev_err(dev, "error in RX dma configuration.\n");
1332 goto err;
1333 }
1334
1335 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods;
1336 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL);
1337 if (!sport->rx_buf) {
1338 ret = -ENOMEM;
1339 goto err;
1340 }
1341 sport->rx_ring.buf = sport->rx_buf;
1342
1343 /* Prepare for TX : */
1344 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1345 if (!sport->dma_chan_tx) {
1346 dev_err(dev, "cannot get the TX DMA channel!\n");
1347 ret = -EINVAL;
1348 goto err;
1349 }
1350
1351 slave_config.direction = DMA_MEM_TO_DEV;
1352 slave_config.dst_addr = sport->port.mapbase + URTX0;
1353 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1354 slave_config.dst_maxburst = TXTL_DMA;
1355 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1356 if (ret) {
1357 dev_err(dev, "error in TX dma configuration.");
1358 goto err;
1359 }
1360
1361 return 0;
1362err:
1363 imx_uart_dma_exit(sport);
1364 return ret;
1365}
1366
1367static void imx_uart_enable_dma(struct imx_port *sport)
1368{
1369 u32 ucr1;
1370
1371 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1372
1373 /* set UCR1 */
1374 ucr1 = imx_uart_readl(sport, UCR1);
1375 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1376 imx_uart_writel(sport, ucr1, UCR1);
1377
1378 sport->dma_is_enabled = 1;
1379}
1380
1381static void imx_uart_disable_dma(struct imx_port *sport)
1382{
1383 u32 ucr1;
1384
1385 /* clear UCR1 */
1386 ucr1 = imx_uart_readl(sport, UCR1);
1387 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1388 imx_uart_writel(sport, ucr1, UCR1);
1389
1390 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1391
1392 sport->dma_is_enabled = 0;
1393}
1394
1395/* half the RX buffer size */
1396#define CTSTL 16
1397
1398static int imx_uart_startup(struct uart_port *port)
1399{
1400 struct imx_port *sport = (struct imx_port *)port;
1401 int retval, i;
1402 unsigned long flags;
1403 int dma_is_inited = 0;
1404 u32 ucr1, ucr2, ucr3, ucr4, uts;
1405
1406 retval = clk_prepare_enable(sport->clk_per);
1407 if (retval)
1408 return retval;
1409 retval = clk_prepare_enable(sport->clk_ipg);
1410 if (retval) {
1411 clk_disable_unprepare(sport->clk_per);
1412 return retval;
1413 }
1414
1415 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1416
1417 /* disable the DREN bit (Data Ready interrupt enable) before
1418 * requesting IRQs
1419 */
1420 ucr4 = imx_uart_readl(sport, UCR4);
1421
1422 /* set the trigger level for CTS */
1423 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1424 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1425
1426 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1427
1428 /* Can we enable the DMA support? */
1429 if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1430 dma_is_inited = 1;
1431
1432 spin_lock_irqsave(&sport->port.lock, flags);
1433 /* Reset fifo's and state machines */
1434 i = 100;
1435
1436 ucr2 = imx_uart_readl(sport, UCR2);
1437 ucr2 &= ~UCR2_SRST;
1438 imx_uart_writel(sport, ucr2, UCR2);
1439
1440 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1441 udelay(1);
1442
1443 /*
1444 * Finally, clear and enable interrupts
1445 */
1446 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1447 imx_uart_writel(sport, USR2_ORE, USR2);
1448
1449 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1450 ucr1 |= UCR1_UARTEN;
1451 if (sport->have_rtscts)
1452 ucr1 |= UCR1_RTSDEN;
1453
1454 imx_uart_writel(sport, ucr1, UCR1);
1455
1456 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1457 if (!dma_is_inited)
1458 ucr4 |= UCR4_OREN;
1459 if (sport->inverted_rx)
1460 ucr4 |= UCR4_INVR;
1461 imx_uart_writel(sport, ucr4, UCR4);
1462
1463 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1464 /*
1465 * configure tx polarity before enabling tx
1466 */
1467 if (sport->inverted_tx)
1468 ucr3 |= UCR3_INVT;
1469
1470 if (!imx_uart_is_imx1(sport)) {
1471 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1472
1473 if (sport->dte_mode)
1474 /* disable broken interrupts */
1475 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1476 }
1477 imx_uart_writel(sport, ucr3, UCR3);
1478
1479 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1480 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1481 if (!sport->have_rtscts)
1482 ucr2 |= UCR2_IRTS;
1483 /*
1484 * make sure the edge sensitive RTS-irq is disabled,
1485 * we're using RTSD instead.
1486 */
1487 if (!imx_uart_is_imx1(sport))
1488 ucr2 &= ~UCR2_RTSEN;
1489 imx_uart_writel(sport, ucr2, UCR2);
1490
1491 /*
1492 * Enable modem status interrupts
1493 */
1494 imx_uart_enable_ms(&sport->port);
1495
1496 if (dma_is_inited) {
1497 imx_uart_enable_dma(sport);
1498 imx_uart_start_rx_dma(sport);
1499 } else {
1500 ucr1 = imx_uart_readl(sport, UCR1);
1501 ucr1 |= UCR1_RRDYEN;
1502 imx_uart_writel(sport, ucr1, UCR1);
1503
1504 ucr2 = imx_uart_readl(sport, UCR2);
1505 ucr2 |= UCR2_ATEN;
1506 imx_uart_writel(sport, ucr2, UCR2);
1507 }
1508
1509 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
1510 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
1511 uts &= ~UTS_LOOP;
1512 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1513
1514 spin_unlock_irqrestore(&sport->port.lock, flags);
1515
1516 return 0;
1517}
1518
1519static void imx_uart_shutdown(struct uart_port *port)
1520{
1521 struct imx_port *sport = (struct imx_port *)port;
1522 unsigned long flags;
1523 u32 ucr1, ucr2, ucr4, uts;
1524
1525 if (sport->dma_is_enabled) {
1526 dmaengine_terminate_sync(sport->dma_chan_tx);
1527 if (sport->dma_is_txing) {
1528 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1529 sport->dma_tx_nents, DMA_TO_DEVICE);
1530 sport->dma_is_txing = 0;
1531 }
1532 dmaengine_terminate_sync(sport->dma_chan_rx);
1533 if (sport->dma_is_rxing) {
1534 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1535 1, DMA_FROM_DEVICE);
1536 sport->dma_is_rxing = 0;
1537 }
1538
1539 spin_lock_irqsave(&sport->port.lock, flags);
1540 imx_uart_stop_tx(port);
1541 imx_uart_stop_rx(port);
1542 imx_uart_disable_dma(sport);
1543 spin_unlock_irqrestore(&sport->port.lock, flags);
1544 imx_uart_dma_exit(sport);
1545 }
1546
1547 mctrl_gpio_disable_ms(sport->gpios);
1548
1549 spin_lock_irqsave(&sport->port.lock, flags);
1550 ucr2 = imx_uart_readl(sport, UCR2);
1551 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1552 imx_uart_writel(sport, ucr2, UCR2);
1553 spin_unlock_irqrestore(&sport->port.lock, flags);
1554
1555 /*
1556 * Stop our timer.
1557 */
1558 del_timer_sync(&sport->timer);
1559
1560 /*
1561 * Disable all interrupts, port and break condition.
1562 */
1563
1564 spin_lock_irqsave(&sport->port.lock, flags);
1565
1566 ucr1 = imx_uart_readl(sport, UCR1);
1567 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN | UCR1_ATDMAEN);
1568 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
1569 if (port->rs485.flags & SER_RS485_ENABLED &&
1570 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
1571 sport->have_rtscts && !sport->have_rtsgpio) {
1572 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
1573 uts |= UTS_LOOP;
1574 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1575 ucr1 |= UCR1_UARTEN;
1576 } else {
1577 ucr1 &= ~UCR1_UARTEN;
1578 }
1579 imx_uart_writel(sport, ucr1, UCR1);
1580
1581 ucr4 = imx_uart_readl(sport, UCR4);
1582 ucr4 &= ~UCR4_TCEN;
1583 imx_uart_writel(sport, ucr4, UCR4);
1584
1585 spin_unlock_irqrestore(&sport->port.lock, flags);
1586
1587 clk_disable_unprepare(sport->clk_per);
1588 clk_disable_unprepare(sport->clk_ipg);
1589}
1590
1591/* called with port.lock taken and irqs off */
1592static void imx_uart_flush_buffer(struct uart_port *port)
1593{
1594 struct imx_port *sport = (struct imx_port *)port;
1595 struct scatterlist *sgl = &sport->tx_sgl[0];
1596 u32 ucr2;
1597 int i = 100, ubir, ubmr, uts;
1598
1599 if (!sport->dma_chan_tx)
1600 return;
1601
1602 sport->tx_bytes = 0;
1603 dmaengine_terminate_all(sport->dma_chan_tx);
1604 if (sport->dma_is_txing) {
1605 u32 ucr1;
1606
1607 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1608 DMA_TO_DEVICE);
1609 ucr1 = imx_uart_readl(sport, UCR1);
1610 ucr1 &= ~UCR1_TXDMAEN;
1611 imx_uart_writel(sport, ucr1, UCR1);
1612 sport->dma_is_txing = 0;
1613 }
1614
1615 /*
1616 * According to the Reference Manual description of the UART SRST bit:
1617 *
1618 * "Reset the transmit and receive state machines,
1619 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1620 * and UTS[6-3]".
1621 *
1622 * We don't need to restore the old values from USR1, USR2, URXD and
1623 * UTXD. UBRC is read only, so only save/restore the other three
1624 * registers.
1625 */
1626 ubir = imx_uart_readl(sport, UBIR);
1627 ubmr = imx_uart_readl(sport, UBMR);
1628 uts = imx_uart_readl(sport, IMX21_UTS);
1629
1630 ucr2 = imx_uart_readl(sport, UCR2);
1631 ucr2 &= ~UCR2_SRST;
1632 imx_uart_writel(sport, ucr2, UCR2);
1633
1634 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1635 udelay(1);
1636
1637 /* Restore the registers */
1638 imx_uart_writel(sport, ubir, UBIR);
1639 imx_uart_writel(sport, ubmr, UBMR);
1640 imx_uart_writel(sport, uts, IMX21_UTS);
1641}
1642
1643static void
1644imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1645 const struct ktermios *old)
1646{
1647 struct imx_port *sport = (struct imx_port *)port;
1648 unsigned long flags;
1649 u32 ucr2, old_ucr2, ufcr;
1650 unsigned int baud, quot;
1651 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1652 unsigned long div;
1653 unsigned long num, denom, old_ubir, old_ubmr;
1654 uint64_t tdiv64;
1655
1656 /*
1657 * We only support CS7 and CS8.
1658 */
1659 while ((termios->c_cflag & CSIZE) != CS7 &&
1660 (termios->c_cflag & CSIZE) != CS8) {
1661 termios->c_cflag &= ~CSIZE;
1662 termios->c_cflag |= old_csize;
1663 old_csize = CS8;
1664 }
1665
1666 del_timer_sync(&sport->timer);
1667
1668 /*
1669 * Ask the core to calculate the divisor for us.
1670 */
1671 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1672 quot = uart_get_divisor(port, baud);
1673
1674 spin_lock_irqsave(&sport->port.lock, flags);
1675
1676 /*
1677 * Read current UCR2 and save it for future use, then clear all the bits
1678 * except those we will or may need to preserve.
1679 */
1680 old_ucr2 = imx_uart_readl(sport, UCR2);
1681 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1682
1683 ucr2 |= UCR2_SRST | UCR2_IRTS;
1684 if ((termios->c_cflag & CSIZE) == CS8)
1685 ucr2 |= UCR2_WS;
1686
1687 if (!sport->have_rtscts)
1688 termios->c_cflag &= ~CRTSCTS;
1689
1690 if (port->rs485.flags & SER_RS485_ENABLED) {
1691 /*
1692 * RTS is mandatory for rs485 operation, so keep
1693 * it under manual control and keep transmitter
1694 * disabled.
1695 */
1696 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1697 imx_uart_rts_active(sport, &ucr2);
1698 else
1699 imx_uart_rts_inactive(sport, &ucr2);
1700
1701 } else if (termios->c_cflag & CRTSCTS) {
1702 /*
1703 * Only let receiver control RTS output if we were not requested
1704 * to have RTS inactive (which then should take precedence).
1705 */
1706 if (ucr2 & UCR2_CTS)
1707 ucr2 |= UCR2_CTSC;
1708 }
1709
1710 if (termios->c_cflag & CRTSCTS)
1711 ucr2 &= ~UCR2_IRTS;
1712 if (termios->c_cflag & CSTOPB)
1713 ucr2 |= UCR2_STPB;
1714 if (termios->c_cflag & PARENB) {
1715 ucr2 |= UCR2_PREN;
1716 if (termios->c_cflag & PARODD)
1717 ucr2 |= UCR2_PROE;
1718 }
1719
1720 sport->port.read_status_mask = 0;
1721 if (termios->c_iflag & INPCK)
1722 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1723 if (termios->c_iflag & (BRKINT | PARMRK))
1724 sport->port.read_status_mask |= URXD_BRK;
1725
1726 /*
1727 * Characters to ignore
1728 */
1729 sport->port.ignore_status_mask = 0;
1730 if (termios->c_iflag & IGNPAR)
1731 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1732 if (termios->c_iflag & IGNBRK) {
1733 sport->port.ignore_status_mask |= URXD_BRK;
1734 /*
1735 * If we're ignoring parity and break indicators,
1736 * ignore overruns too (for real raw support).
1737 */
1738 if (termios->c_iflag & IGNPAR)
1739 sport->port.ignore_status_mask |= URXD_OVRRUN;
1740 }
1741
1742 if ((termios->c_cflag & CREAD) == 0)
1743 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1744
1745 /*
1746 * Update the per-port timeout.
1747 */
1748 uart_update_timeout(port, termios->c_cflag, baud);
1749
1750 /* custom-baudrate handling */
1751 div = sport->port.uartclk / (baud * 16);
1752 if (baud == 38400 && quot != div)
1753 baud = sport->port.uartclk / (quot * 16);
1754
1755 div = sport->port.uartclk / (baud * 16);
1756 if (div > 7)
1757 div = 7;
1758 if (!div)
1759 div = 1;
1760
1761 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1762 1 << 16, 1 << 16, &num, &denom);
1763
1764 tdiv64 = sport->port.uartclk;
1765 tdiv64 *= num;
1766 do_div(tdiv64, denom * 16 * div);
1767 tty_termios_encode_baud_rate(termios,
1768 (speed_t)tdiv64, (speed_t)tdiv64);
1769
1770 num -= 1;
1771 denom -= 1;
1772
1773 ufcr = imx_uart_readl(sport, UFCR);
1774 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1775 imx_uart_writel(sport, ufcr, UFCR);
1776
1777 /*
1778 * Two registers below should always be written both and in this
1779 * particular order. One consequence is that we need to check if any of
1780 * them changes and then update both. We do need the check for change
1781 * as even writing the same values seem to "restart"
1782 * transmission/receiving logic in the hardware, that leads to data
1783 * breakage even when rate doesn't in fact change. E.g., user switches
1784 * RTS/CTS handshake and suddenly gets broken bytes.
1785 */
1786 old_ubir = imx_uart_readl(sport, UBIR);
1787 old_ubmr = imx_uart_readl(sport, UBMR);
1788 if (old_ubir != num || old_ubmr != denom) {
1789 imx_uart_writel(sport, num, UBIR);
1790 imx_uart_writel(sport, denom, UBMR);
1791 }
1792
1793 if (!imx_uart_is_imx1(sport))
1794 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1795 IMX21_ONEMS);
1796
1797 imx_uart_writel(sport, ucr2, UCR2);
1798
1799 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1800 imx_uart_enable_ms(&sport->port);
1801
1802 spin_unlock_irqrestore(&sport->port.lock, flags);
1803}
1804
1805static const char *imx_uart_type(struct uart_port *port)
1806{
1807 struct imx_port *sport = (struct imx_port *)port;
1808
1809 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1810}
1811
1812/*
1813 * Configure/autoconfigure the port.
1814 */
1815static void imx_uart_config_port(struct uart_port *port, int flags)
1816{
1817 struct imx_port *sport = (struct imx_port *)port;
1818
1819 if (flags & UART_CONFIG_TYPE)
1820 sport->port.type = PORT_IMX;
1821}
1822
1823/*
1824 * Verify the new serial_struct (for TIOCSSERIAL).
1825 * The only change we allow are to the flags and type, and
1826 * even then only between PORT_IMX and PORT_UNKNOWN
1827 */
1828static int
1829imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1830{
1831 struct imx_port *sport = (struct imx_port *)port;
1832 int ret = 0;
1833
1834 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1835 ret = -EINVAL;
1836 if (sport->port.irq != ser->irq)
1837 ret = -EINVAL;
1838 if (ser->io_type != UPIO_MEM)
1839 ret = -EINVAL;
1840 if (sport->port.uartclk / 16 != ser->baud_base)
1841 ret = -EINVAL;
1842 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1843 ret = -EINVAL;
1844 if (sport->port.iobase != ser->port)
1845 ret = -EINVAL;
1846 if (ser->hub6 != 0)
1847 ret = -EINVAL;
1848 return ret;
1849}
1850
1851#if defined(CONFIG_CONSOLE_POLL)
1852
1853static int imx_uart_poll_init(struct uart_port *port)
1854{
1855 struct imx_port *sport = (struct imx_port *)port;
1856 unsigned long flags;
1857 u32 ucr1, ucr2;
1858 int retval;
1859
1860 retval = clk_prepare_enable(sport->clk_ipg);
1861 if (retval)
1862 return retval;
1863 retval = clk_prepare_enable(sport->clk_per);
1864 if (retval)
1865 clk_disable_unprepare(sport->clk_ipg);
1866
1867 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1868
1869 spin_lock_irqsave(&sport->port.lock, flags);
1870
1871 /*
1872 * Be careful about the order of enabling bits here. First enable the
1873 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1874 * This prevents that a character that already sits in the RX fifo is
1875 * triggering an irq but the try to fetch it from there results in an
1876 * exception because UARTEN or RXEN is still off.
1877 */
1878 ucr1 = imx_uart_readl(sport, UCR1);
1879 ucr2 = imx_uart_readl(sport, UCR2);
1880
1881 if (imx_uart_is_imx1(sport))
1882 ucr1 |= IMX1_UCR1_UARTCLKEN;
1883
1884 ucr1 |= UCR1_UARTEN;
1885 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1886
1887 ucr2 |= UCR2_RXEN | UCR2_TXEN;
1888 ucr2 &= ~UCR2_ATEN;
1889
1890 imx_uart_writel(sport, ucr1, UCR1);
1891 imx_uart_writel(sport, ucr2, UCR2);
1892
1893 /* now enable irqs */
1894 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1895 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1896
1897 spin_unlock_irqrestore(&sport->port.lock, flags);
1898
1899 return 0;
1900}
1901
1902static int imx_uart_poll_get_char(struct uart_port *port)
1903{
1904 struct imx_port *sport = (struct imx_port *)port;
1905 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1906 return NO_POLL_CHAR;
1907
1908 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1909}
1910
1911static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1912{
1913 struct imx_port *sport = (struct imx_port *)port;
1914 unsigned int status;
1915
1916 /* drain */
1917 do {
1918 status = imx_uart_readl(sport, USR1);
1919 } while (~status & USR1_TRDY);
1920
1921 /* write */
1922 imx_uart_writel(sport, c, URTX0);
1923
1924 /* flush */
1925 do {
1926 status = imx_uart_readl(sport, USR2);
1927 } while (~status & USR2_TXDC);
1928}
1929#endif
1930
1931/* called with port.lock taken and irqs off or from .probe without locking */
1932static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termios,
1933 struct serial_rs485 *rs485conf)
1934{
1935 struct imx_port *sport = (struct imx_port *)port;
1936 u32 ucr2;
1937
1938 if (rs485conf->flags & SER_RS485_ENABLED) {
1939 /* Enable receiver if low-active RTS signal is requested */
1940 if (sport->have_rtscts && !sport->have_rtsgpio &&
1941 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1942 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1943
1944 /* disable transmitter */
1945 ucr2 = imx_uart_readl(sport, UCR2);
1946 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1947 imx_uart_rts_active(sport, &ucr2);
1948 else
1949 imx_uart_rts_inactive(sport, &ucr2);
1950 imx_uart_writel(sport, ucr2, UCR2);
1951 }
1952
1953 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1954 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1955 rs485conf->flags & SER_RS485_RX_DURING_TX)
1956 imx_uart_start_rx(port);
1957
1958 return 0;
1959}
1960
1961static const struct uart_ops imx_uart_pops = {
1962 .tx_empty = imx_uart_tx_empty,
1963 .set_mctrl = imx_uart_set_mctrl,
1964 .get_mctrl = imx_uart_get_mctrl,
1965 .stop_tx = imx_uart_stop_tx,
1966 .start_tx = imx_uart_start_tx,
1967 .stop_rx = imx_uart_stop_rx,
1968 .enable_ms = imx_uart_enable_ms,
1969 .break_ctl = imx_uart_break_ctl,
1970 .startup = imx_uart_startup,
1971 .shutdown = imx_uart_shutdown,
1972 .flush_buffer = imx_uart_flush_buffer,
1973 .set_termios = imx_uart_set_termios,
1974 .type = imx_uart_type,
1975 .config_port = imx_uart_config_port,
1976 .verify_port = imx_uart_verify_port,
1977#if defined(CONFIG_CONSOLE_POLL)
1978 .poll_init = imx_uart_poll_init,
1979 .poll_get_char = imx_uart_poll_get_char,
1980 .poll_put_char = imx_uart_poll_put_char,
1981#endif
1982};
1983
1984static struct imx_port *imx_uart_ports[UART_NR];
1985
1986#if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
1987static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch)
1988{
1989 struct imx_port *sport = (struct imx_port *)port;
1990
1991 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1992 barrier();
1993
1994 imx_uart_writel(sport, ch, URTX0);
1995}
1996
1997/*
1998 * Interrupts are disabled on entering
1999 */
2000static void
2001imx_uart_console_write(struct console *co, const char *s, unsigned int count)
2002{
2003 struct imx_port *sport = imx_uart_ports[co->index];
2004 struct imx_port_ucrs old_ucr;
2005 unsigned long flags;
2006 unsigned int ucr1;
2007 int locked = 1;
2008
2009 if (sport->port.sysrq)
2010 locked = 0;
2011 else if (oops_in_progress)
2012 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2013 else
2014 spin_lock_irqsave(&sport->port.lock, flags);
2015
2016 /*
2017 * First, save UCR1/2/3 and then disable interrupts
2018 */
2019 imx_uart_ucrs_save(sport, &old_ucr);
2020 ucr1 = old_ucr.ucr1;
2021
2022 if (imx_uart_is_imx1(sport))
2023 ucr1 |= IMX1_UCR1_UARTCLKEN;
2024 ucr1 |= UCR1_UARTEN;
2025 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2026
2027 imx_uart_writel(sport, ucr1, UCR1);
2028
2029 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2030
2031 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
2032
2033 /*
2034 * Finally, wait for transmitter to become empty
2035 * and restore UCR1/2/3
2036 */
2037 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC));
2038
2039 imx_uart_ucrs_restore(sport, &old_ucr);
2040
2041 if (locked)
2042 spin_unlock_irqrestore(&sport->port.lock, flags);
2043}
2044
2045/*
2046 * If the port was already initialised (eg, by a boot loader),
2047 * try to determine the current setup.
2048 */
2049static void
2050imx_uart_console_get_options(struct imx_port *sport, int *baud,
2051 int *parity, int *bits)
2052{
2053
2054 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2055 /* ok, the port was enabled */
2056 unsigned int ucr2, ubir, ubmr, uartclk;
2057 unsigned int baud_raw;
2058 unsigned int ucfr_rfdiv;
2059
2060 ucr2 = imx_uart_readl(sport, UCR2);
2061
2062 *parity = 'n';
2063 if (ucr2 & UCR2_PREN) {
2064 if (ucr2 & UCR2_PROE)
2065 *parity = 'o';
2066 else
2067 *parity = 'e';
2068 }
2069
2070 if (ucr2 & UCR2_WS)
2071 *bits = 8;
2072 else
2073 *bits = 7;
2074
2075 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2076 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2077
2078 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2079 if (ucfr_rfdiv == 6)
2080 ucfr_rfdiv = 7;
2081 else
2082 ucfr_rfdiv = 6 - ucfr_rfdiv;
2083
2084 uartclk = clk_get_rate(sport->clk_per);
2085 uartclk /= ucfr_rfdiv;
2086
2087 { /*
2088 * The next code provides exact computation of
2089 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2090 * without need of float support or long long division,
2091 * which would be required to prevent 32bit arithmetic overflow
2092 */
2093 unsigned int mul = ubir + 1;
2094 unsigned int div = 16 * (ubmr + 1);
2095 unsigned int rem = uartclk % div;
2096
2097 baud_raw = (uartclk / div) * mul;
2098 baud_raw += (rem * mul + div / 2) / div;
2099 *baud = (baud_raw + 50) / 100 * 100;
2100 }
2101
2102 if (*baud != baud_raw)
2103 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2104 baud_raw, *baud);
2105 }
2106}
2107
2108static int
2109imx_uart_console_setup(struct console *co, char *options)
2110{
2111 struct imx_port *sport;
2112 int baud = 9600;
2113 int bits = 8;
2114 int parity = 'n';
2115 int flow = 'n';
2116 int retval;
2117
2118 /*
2119 * Check whether an invalid uart number has been specified, and
2120 * if so, search for the first available port that does have
2121 * console support.
2122 */
2123 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2124 co->index = 0;
2125 sport = imx_uart_ports[co->index];
2126 if (sport == NULL)
2127 return -ENODEV;
2128
2129 /* For setting the registers, we only need to enable the ipg clock. */
2130 retval = clk_prepare_enable(sport->clk_ipg);
2131 if (retval)
2132 goto error_console;
2133
2134 if (options)
2135 uart_parse_options(options, &baud, &parity, &bits, &flow);
2136 else
2137 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2138
2139 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2140
2141 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2142
2143 if (retval) {
2144 clk_disable_unprepare(sport->clk_ipg);
2145 goto error_console;
2146 }
2147
2148 retval = clk_prepare_enable(sport->clk_per);
2149 if (retval)
2150 clk_disable_unprepare(sport->clk_ipg);
2151
2152error_console:
2153 return retval;
2154}
2155
2156static int
2157imx_uart_console_exit(struct console *co)
2158{
2159 struct imx_port *sport = imx_uart_ports[co->index];
2160
2161 clk_disable_unprepare(sport->clk_per);
2162 clk_disable_unprepare(sport->clk_ipg);
2163
2164 return 0;
2165}
2166
2167static struct uart_driver imx_uart_uart_driver;
2168static struct console imx_uart_console = {
2169 .name = DEV_NAME,
2170 .write = imx_uart_console_write,
2171 .device = uart_console_device,
2172 .setup = imx_uart_console_setup,
2173 .exit = imx_uart_console_exit,
2174 .flags = CON_PRINTBUFFER,
2175 .index = -1,
2176 .data = &imx_uart_uart_driver,
2177};
2178
2179#define IMX_CONSOLE &imx_uart_console
2180
2181#else
2182#define IMX_CONSOLE NULL
2183#endif
2184
2185static struct uart_driver imx_uart_uart_driver = {
2186 .owner = THIS_MODULE,
2187 .driver_name = DRIVER_NAME,
2188 .dev_name = DEV_NAME,
2189 .major = SERIAL_IMX_MAJOR,
2190 .minor = MINOR_START,
2191 .nr = ARRAY_SIZE(imx_uart_ports),
2192 .cons = IMX_CONSOLE,
2193};
2194
2195static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2196{
2197 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2198 unsigned long flags;
2199
2200 spin_lock_irqsave(&sport->port.lock, flags);
2201 if (sport->tx_state == WAIT_AFTER_RTS)
2202 imx_uart_start_tx(&sport->port);
2203 spin_unlock_irqrestore(&sport->port.lock, flags);
2204
2205 return HRTIMER_NORESTART;
2206}
2207
2208static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2209{
2210 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2211 unsigned long flags;
2212
2213 spin_lock_irqsave(&sport->port.lock, flags);
2214 if (sport->tx_state == WAIT_AFTER_SEND)
2215 imx_uart_stop_tx(&sport->port);
2216 spin_unlock_irqrestore(&sport->port.lock, flags);
2217
2218 return HRTIMER_NORESTART;
2219}
2220
2221static const struct serial_rs485 imx_no_rs485 = {}; /* No RS485 if no RTS */
2222static const struct serial_rs485 imx_rs485_supported = {
2223 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
2224 SER_RS485_RX_DURING_TX,
2225 .delay_rts_before_send = 1,
2226 .delay_rts_after_send = 1,
2227};
2228
2229/* Default RX DMA buffer configuration */
2230#define RX_DMA_PERIODS 16
2231#define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4)
2232
2233static int imx_uart_probe(struct platform_device *pdev)
2234{
2235 struct device_node *np = pdev->dev.of_node;
2236 struct imx_port *sport;
2237 void __iomem *base;
2238 u32 dma_buf_conf[2];
2239 int ret = 0;
2240 u32 ucr1, ucr2, uts;
2241 struct resource *res;
2242 int txirq, rxirq, rtsirq;
2243
2244 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2245 if (!sport)
2246 return -ENOMEM;
2247
2248 sport->devdata = of_device_get_match_data(&pdev->dev);
2249
2250 ret = of_alias_get_id(np, "serial");
2251 if (ret < 0) {
2252 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2253 return ret;
2254 }
2255 sport->port.line = ret;
2256
2257 if (of_get_property(np, "uart-has-rtscts", NULL) ||
2258 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
2259 sport->have_rtscts = 1;
2260
2261 if (of_get_property(np, "fsl,dte-mode", NULL))
2262 sport->dte_mode = 1;
2263
2264 if (of_get_property(np, "rts-gpios", NULL))
2265 sport->have_rtsgpio = 1;
2266
2267 if (of_get_property(np, "fsl,inverted-tx", NULL))
2268 sport->inverted_tx = 1;
2269
2270 if (of_get_property(np, "fsl,inverted-rx", NULL))
2271 sport->inverted_rx = 1;
2272
2273 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) {
2274 sport->rx_period_length = dma_buf_conf[0];
2275 sport->rx_periods = dma_buf_conf[1];
2276 } else {
2277 sport->rx_period_length = RX_DMA_PERIOD_LEN;
2278 sport->rx_periods = RX_DMA_PERIODS;
2279 }
2280
2281 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2282 dev_err(&pdev->dev, "serial%d out of range\n",
2283 sport->port.line);
2284 return -EINVAL;
2285 }
2286
2287 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2288 base = devm_ioremap_resource(&pdev->dev, res);
2289 if (IS_ERR(base))
2290 return PTR_ERR(base);
2291
2292 rxirq = platform_get_irq(pdev, 0);
2293 if (rxirq < 0)
2294 return rxirq;
2295 txirq = platform_get_irq_optional(pdev, 1);
2296 rtsirq = platform_get_irq_optional(pdev, 2);
2297
2298 sport->port.dev = &pdev->dev;
2299 sport->port.mapbase = res->start;
2300 sport->port.membase = base;
2301 sport->port.type = PORT_IMX;
2302 sport->port.iotype = UPIO_MEM;
2303 sport->port.irq = rxirq;
2304 sport->port.fifosize = 32;
2305 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2306 sport->port.ops = &imx_uart_pops;
2307 sport->port.rs485_config = imx_uart_rs485_config;
2308 /* RTS is required to control the RS485 transmitter */
2309 if (sport->have_rtscts || sport->have_rtsgpio)
2310 sport->port.rs485_supported = imx_rs485_supported;
2311 else
2312 sport->port.rs485_supported = imx_no_rs485;
2313 sport->port.flags = UPF_BOOT_AUTOCONF;
2314 timer_setup(&sport->timer, imx_uart_timeout, 0);
2315
2316 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2317 if (IS_ERR(sport->gpios))
2318 return PTR_ERR(sport->gpios);
2319
2320 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2321 if (IS_ERR(sport->clk_ipg)) {
2322 ret = PTR_ERR(sport->clk_ipg);
2323 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2324 return ret;
2325 }
2326
2327 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2328 if (IS_ERR(sport->clk_per)) {
2329 ret = PTR_ERR(sport->clk_per);
2330 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2331 return ret;
2332 }
2333
2334 sport->port.uartclk = clk_get_rate(sport->clk_per);
2335
2336 /* For register access, we only need to enable the ipg clock. */
2337 ret = clk_prepare_enable(sport->clk_ipg);
2338 if (ret) {
2339 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2340 return ret;
2341 }
2342
2343 /* initialize shadow register values */
2344 sport->ucr1 = readl(sport->port.membase + UCR1);
2345 sport->ucr2 = readl(sport->port.membase + UCR2);
2346 sport->ucr3 = readl(sport->port.membase + UCR3);
2347 sport->ucr4 = readl(sport->port.membase + UCR4);
2348 sport->ufcr = readl(sport->port.membase + UFCR);
2349
2350 ret = uart_get_rs485_mode(&sport->port);
2351 if (ret) {
2352 clk_disable_unprepare(sport->clk_ipg);
2353 return ret;
2354 }
2355
2356 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2357 (!sport->have_rtscts && !sport->have_rtsgpio))
2358 dev_err(&pdev->dev, "no RTS control, disabling rs485\n");
2359
2360 /*
2361 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2362 * signal cannot be set low during transmission in case the
2363 * receiver is off (limitation of the i.MX UART IP).
2364 */
2365 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2366 sport->have_rtscts && !sport->have_rtsgpio &&
2367 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2368 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2369 dev_err(&pdev->dev,
2370 "low-active RTS not possible when receiver is off, enabling receiver\n");
2371
2372 /* Disable interrupts before requesting them */
2373 ucr1 = imx_uart_readl(sport, UCR1);
2374 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2375 imx_uart_writel(sport, ucr1, UCR1);
2376
2377 /*
2378 * In case RS485 is enabled without GPIO RTS control, the UART IP
2379 * is used to control CTS signal. Keep both the UART and Receiver
2380 * enabled, otherwise the UART IP pulls CTS signal always HIGH no
2381 * matter how the UCR2 CTSC and CTS bits are set. To prevent any
2382 * data from being fed into the RX FIFO, enable loopback mode in
2383 * UTS register, which disconnects the RX path from external RXD
2384 * pin and connects it to the Transceiver, which is disabled, so
2385 * no data can be fed to the RX FIFO that way.
2386 */
2387 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2388 sport->have_rtscts && !sport->have_rtsgpio) {
2389 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
2390 uts |= UTS_LOOP;
2391 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
2392
2393 ucr1 = imx_uart_readl(sport, UCR1);
2394 ucr1 |= UCR1_UARTEN;
2395 imx_uart_writel(sport, ucr1, UCR1);
2396
2397 ucr2 = imx_uart_readl(sport, UCR2);
2398 ucr2 |= UCR2_RXEN;
2399 imx_uart_writel(sport, ucr2, UCR2);
2400 }
2401
2402 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2403 /*
2404 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2405 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2406 * and DCD (when they are outputs) or enables the respective
2407 * irqs. So set this bit early, i.e. before requesting irqs.
2408 */
2409 u32 ufcr = imx_uart_readl(sport, UFCR);
2410 if (!(ufcr & UFCR_DCEDTE))
2411 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2412
2413 /*
2414 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2415 * enabled later because they cannot be cleared
2416 * (confirmed on i.MX25) which makes them unusable.
2417 */
2418 imx_uart_writel(sport,
2419 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2420 UCR3);
2421
2422 } else {
2423 u32 ucr3 = UCR3_DSR;
2424 u32 ufcr = imx_uart_readl(sport, UFCR);
2425 if (ufcr & UFCR_DCEDTE)
2426 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2427
2428 if (!imx_uart_is_imx1(sport))
2429 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2430 imx_uart_writel(sport, ucr3, UCR3);
2431 }
2432
2433 clk_disable_unprepare(sport->clk_ipg);
2434
2435 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2436 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2437 sport->trigger_start_tx.function = imx_trigger_start_tx;
2438 sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2439
2440 /*
2441 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2442 * chips only have one interrupt.
2443 */
2444 if (txirq > 0) {
2445 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2446 dev_name(&pdev->dev), sport);
2447 if (ret) {
2448 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2449 ret);
2450 return ret;
2451 }
2452
2453 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2454 dev_name(&pdev->dev), sport);
2455 if (ret) {
2456 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2457 ret);
2458 return ret;
2459 }
2460
2461 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2462 dev_name(&pdev->dev), sport);
2463 if (ret) {
2464 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2465 ret);
2466 return ret;
2467 }
2468 } else {
2469 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2470 dev_name(&pdev->dev), sport);
2471 if (ret) {
2472 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2473 return ret;
2474 }
2475 }
2476
2477 imx_uart_ports[sport->port.line] = sport;
2478
2479 platform_set_drvdata(pdev, sport);
2480
2481 return uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2482}
2483
2484static int imx_uart_remove(struct platform_device *pdev)
2485{
2486 struct imx_port *sport = platform_get_drvdata(pdev);
2487
2488 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2489}
2490
2491static void imx_uart_restore_context(struct imx_port *sport)
2492{
2493 unsigned long flags;
2494
2495 spin_lock_irqsave(&sport->port.lock, flags);
2496 if (!sport->context_saved) {
2497 spin_unlock_irqrestore(&sport->port.lock, flags);
2498 return;
2499 }
2500
2501 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2502 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2503 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2504 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2505 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2506 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2507 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2508 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2509 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2510 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2511 sport->context_saved = false;
2512 spin_unlock_irqrestore(&sport->port.lock, flags);
2513}
2514
2515static void imx_uart_save_context(struct imx_port *sport)
2516{
2517 unsigned long flags;
2518
2519 /* Save necessary regs */
2520 spin_lock_irqsave(&sport->port.lock, flags);
2521 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2522 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2523 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2524 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2525 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2526 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2527 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2528 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2529 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2530 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2531 sport->context_saved = true;
2532 spin_unlock_irqrestore(&sport->port.lock, flags);
2533}
2534
2535static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2536{
2537 u32 ucr3;
2538
2539 ucr3 = imx_uart_readl(sport, UCR3);
2540 if (on) {
2541 imx_uart_writel(sport, USR1_AWAKE, USR1);
2542 ucr3 |= UCR3_AWAKEN;
2543 } else {
2544 ucr3 &= ~UCR3_AWAKEN;
2545 }
2546 imx_uart_writel(sport, ucr3, UCR3);
2547
2548 if (sport->have_rtscts) {
2549 u32 ucr1 = imx_uart_readl(sport, UCR1);
2550 if (on) {
2551 imx_uart_writel(sport, USR1_RTSD, USR1);
2552 ucr1 |= UCR1_RTSDEN;
2553 } else {
2554 ucr1 &= ~UCR1_RTSDEN;
2555 }
2556 imx_uart_writel(sport, ucr1, UCR1);
2557 }
2558}
2559
2560static int imx_uart_suspend_noirq(struct device *dev)
2561{
2562 struct imx_port *sport = dev_get_drvdata(dev);
2563
2564 imx_uart_save_context(sport);
2565
2566 clk_disable(sport->clk_ipg);
2567
2568 pinctrl_pm_select_sleep_state(dev);
2569
2570 return 0;
2571}
2572
2573static int imx_uart_resume_noirq(struct device *dev)
2574{
2575 struct imx_port *sport = dev_get_drvdata(dev);
2576 int ret;
2577
2578 pinctrl_pm_select_default_state(dev);
2579
2580 ret = clk_enable(sport->clk_ipg);
2581 if (ret)
2582 return ret;
2583
2584 imx_uart_restore_context(sport);
2585
2586 return 0;
2587}
2588
2589static int imx_uart_suspend(struct device *dev)
2590{
2591 struct imx_port *sport = dev_get_drvdata(dev);
2592 int ret;
2593
2594 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2595 disable_irq(sport->port.irq);
2596
2597 ret = clk_prepare_enable(sport->clk_ipg);
2598 if (ret)
2599 return ret;
2600
2601 /* enable wakeup from i.MX UART */
2602 imx_uart_enable_wakeup(sport, true);
2603
2604 return 0;
2605}
2606
2607static int imx_uart_resume(struct device *dev)
2608{
2609 struct imx_port *sport = dev_get_drvdata(dev);
2610
2611 /* disable wakeup from i.MX UART */
2612 imx_uart_enable_wakeup(sport, false);
2613
2614 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2615 enable_irq(sport->port.irq);
2616
2617 clk_disable_unprepare(sport->clk_ipg);
2618
2619 return 0;
2620}
2621
2622static int imx_uart_freeze(struct device *dev)
2623{
2624 struct imx_port *sport = dev_get_drvdata(dev);
2625
2626 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2627
2628 return clk_prepare_enable(sport->clk_ipg);
2629}
2630
2631static int imx_uart_thaw(struct device *dev)
2632{
2633 struct imx_port *sport = dev_get_drvdata(dev);
2634
2635 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2636
2637 clk_disable_unprepare(sport->clk_ipg);
2638
2639 return 0;
2640}
2641
2642static const struct dev_pm_ops imx_uart_pm_ops = {
2643 .suspend_noirq = imx_uart_suspend_noirq,
2644 .resume_noirq = imx_uart_resume_noirq,
2645 .freeze_noirq = imx_uart_suspend_noirq,
2646 .thaw_noirq = imx_uart_resume_noirq,
2647 .restore_noirq = imx_uart_resume_noirq,
2648 .suspend = imx_uart_suspend,
2649 .resume = imx_uart_resume,
2650 .freeze = imx_uart_freeze,
2651 .thaw = imx_uart_thaw,
2652 .restore = imx_uart_thaw,
2653};
2654
2655static struct platform_driver imx_uart_platform_driver = {
2656 .probe = imx_uart_probe,
2657 .remove = imx_uart_remove,
2658
2659 .driver = {
2660 .name = "imx-uart",
2661 .of_match_table = imx_uart_dt_ids,
2662 .pm = &imx_uart_pm_ops,
2663 },
2664};
2665
2666static int __init imx_uart_init(void)
2667{
2668 int ret = uart_register_driver(&imx_uart_uart_driver);
2669
2670 if (ret)
2671 return ret;
2672
2673 ret = platform_driver_register(&imx_uart_platform_driver);
2674 if (ret != 0)
2675 uart_unregister_driver(&imx_uart_uart_driver);
2676
2677 return ret;
2678}
2679
2680static void __exit imx_uart_exit(void)
2681{
2682 platform_driver_unregister(&imx_uart_platform_driver);
2683 uart_unregister_driver(&imx_uart_uart_driver);
2684}
2685
2686module_init(imx_uart_init);
2687module_exit(imx_uart_exit);
2688
2689MODULE_AUTHOR("Sascha Hauer");
2690MODULE_DESCRIPTION("IMX generic serial port driver");
2691MODULE_LICENSE("GPL");
2692MODULE_ALIAS("platform:imx-uart");