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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11#include <linux/module.h>
12#include <linux/ioport.h>
13#include <linux/init.h>
14#include <linux/console.h>
15#include <linux/sysrq.h>
16#include <linux/platform_device.h>
17#include <linux/tty.h>
18#include <linux/tty_flip.h>
19#include <linux/serial_core.h>
20#include <linux/serial.h>
21#include <linux/clk.h>
22#include <linux/delay.h>
23#include <linux/ktime.h>
24#include <linux/pinctrl/consumer.h>
25#include <linux/rational.h>
26#include <linux/slab.h>
27#include <linux/of.h>
28#include <linux/of_device.h>
29#include <linux/io.h>
30#include <linux/dma-mapping.h>
31
32#include <asm/irq.h>
33#include <linux/platform_data/dma-imx.h>
34
35#include "serial_mctrl_gpio.h"
36
37/* Register definitions */
38#define URXD0 0x0 /* Receiver Register */
39#define URTX0 0x40 /* Transmitter Register */
40#define UCR1 0x80 /* Control Register 1 */
41#define UCR2 0x84 /* Control Register 2 */
42#define UCR3 0x88 /* Control Register 3 */
43#define UCR4 0x8c /* Control Register 4 */
44#define UFCR 0x90 /* FIFO Control Register */
45#define USR1 0x94 /* Status Register 1 */
46#define USR2 0x98 /* Status Register 2 */
47#define UESC 0x9c /* Escape Character Register */
48#define UTIM 0xa0 /* Escape Timer Register */
49#define UBIR 0xa4 /* BRM Incremental Register */
50#define UBMR 0xa8 /* BRM Modulator Register */
51#define UBRC 0xac /* Baud Rate Count Register */
52#define IMX21_ONEMS 0xb0 /* One Millisecond register */
53#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
54#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
55
56/* UART Control Register Bit Fields.*/
57#define URXD_DUMMY_READ (1<<16)
58#define URXD_CHARRDY (1<<15)
59#define URXD_ERR (1<<14)
60#define URXD_OVRRUN (1<<13)
61#define URXD_FRMERR (1<<12)
62#define URXD_BRK (1<<11)
63#define URXD_PRERR (1<<10)
64#define URXD_RX_DATA (0xFF<<0)
65#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
66#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
67#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
68#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
69#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
70#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
71#define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
72#define UCR1_IREN (1<<7) /* Infrared interface enable */
73#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
74#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
75#define UCR1_SNDBRK (1<<4) /* Send break */
76#define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
77#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
78#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
79#define UCR1_DOZE (1<<1) /* Doze */
80#define UCR1_UARTEN (1<<0) /* UART enabled */
81#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
82#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
83#define UCR2_CTSC (1<<13) /* CTS pin control */
84#define UCR2_CTS (1<<12) /* Clear to send */
85#define UCR2_ESCEN (1<<11) /* Escape enable */
86#define UCR2_PREN (1<<8) /* Parity enable */
87#define UCR2_PROE (1<<7) /* Parity odd/even */
88#define UCR2_STPB (1<<6) /* Stop */
89#define UCR2_WS (1<<5) /* Word size */
90#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
91#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
92#define UCR2_TXEN (1<<2) /* Transmitter enabled */
93#define UCR2_RXEN (1<<1) /* Receiver enabled */
94#define UCR2_SRST (1<<0) /* SW reset */
95#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
96#define UCR3_PARERREN (1<<12) /* Parity enable */
97#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
98#define UCR3_DSR (1<<10) /* Data set ready */
99#define UCR3_DCD (1<<9) /* Data carrier detect */
100#define UCR3_RI (1<<8) /* Ring indicator */
101#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
102#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
103#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
104#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
105#define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
106#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
107#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
108#define UCR3_BPEN (1<<0) /* Preset registers enable */
109#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
110#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
111#define UCR4_INVR (1<<9) /* Inverted infrared reception */
112#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
113#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
114#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
115#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
116#define UCR4_IRSC (1<<5) /* IR special case */
117#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
118#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
119#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
120#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
121#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
122#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
123#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
124#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
125#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
126#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
127#define USR1_RTSS (1<<14) /* RTS pin status */
128#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
129#define USR1_RTSD (1<<12) /* RTS delta */
130#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
131#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
132#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
133#define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
134#define USR1_DTRD (1<<7) /* DTR Delta */
135#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
136#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
137#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
138#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
139#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
140#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
141#define USR2_IDLE (1<<12) /* Idle condition */
142#define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
143#define USR2_RIIN (1<<9) /* Ring Indicator Input */
144#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
145#define USR2_WAKE (1<<7) /* Wake */
146#define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
147#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
148#define USR2_TXDC (1<<3) /* Transmitter complete */
149#define USR2_BRCD (1<<2) /* Break condition */
150#define USR2_ORE (1<<1) /* Overrun error */
151#define USR2_RDR (1<<0) /* Recv data ready */
152#define UTS_FRCPERR (1<<13) /* Force parity error */
153#define UTS_LOOP (1<<12) /* Loop tx and rx */
154#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
155#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
156#define UTS_TXFULL (1<<4) /* TxFIFO full */
157#define UTS_RXFULL (1<<3) /* RxFIFO full */
158#define UTS_SOFTRST (1<<0) /* Software reset */
159
160/* We've been assigned a range on the "Low-density serial ports" major */
161#define SERIAL_IMX_MAJOR 207
162#define MINOR_START 16
163#define DEV_NAME "ttymxc"
164
165/*
166 * This determines how often we check the modem status signals
167 * for any change. They generally aren't connected to an IRQ
168 * so we have to poll them. We also check immediately before
169 * filling the TX fifo incase CTS has been dropped.
170 */
171#define MCTRL_TIMEOUT (250*HZ/1000)
172
173#define DRIVER_NAME "IMX-uart"
174
175#define UART_NR 8
176
177/* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
178enum imx_uart_type {
179 IMX1_UART,
180 IMX21_UART,
181 IMX53_UART,
182 IMX6Q_UART,
183};
184
185/* device type dependent stuff */
186struct imx_uart_data {
187 unsigned uts_reg;
188 enum imx_uart_type devtype;
189};
190
191enum imx_tx_state {
192 OFF,
193 WAIT_AFTER_RTS,
194 SEND,
195 WAIT_AFTER_SEND,
196};
197
198struct imx_port {
199 struct uart_port port;
200 struct timer_list timer;
201 unsigned int old_status;
202 unsigned int have_rtscts:1;
203 unsigned int have_rtsgpio:1;
204 unsigned int dte_mode:1;
205 unsigned int inverted_tx:1;
206 unsigned int inverted_rx:1;
207 struct clk *clk_ipg;
208 struct clk *clk_per;
209 const struct imx_uart_data *devdata;
210
211 struct mctrl_gpios *gpios;
212
213 /* shadow registers */
214 unsigned int ucr1;
215 unsigned int ucr2;
216 unsigned int ucr3;
217 unsigned int ucr4;
218 unsigned int ufcr;
219
220 /* DMA fields */
221 unsigned int dma_is_enabled:1;
222 unsigned int dma_is_rxing:1;
223 unsigned int dma_is_txing:1;
224 struct dma_chan *dma_chan_rx, *dma_chan_tx;
225 struct scatterlist rx_sgl, tx_sgl[2];
226 void *rx_buf;
227 struct circ_buf rx_ring;
228 unsigned int rx_buf_size;
229 unsigned int rx_period_length;
230 unsigned int rx_periods;
231 dma_cookie_t rx_cookie;
232 unsigned int tx_bytes;
233 unsigned int dma_tx_nents;
234 unsigned int saved_reg[10];
235 bool context_saved;
236
237 enum imx_tx_state tx_state;
238 struct hrtimer trigger_start_tx;
239 struct hrtimer trigger_stop_tx;
240};
241
242struct imx_port_ucrs {
243 unsigned int ucr1;
244 unsigned int ucr2;
245 unsigned int ucr3;
246};
247
248static struct imx_uart_data imx_uart_devdata[] = {
249 [IMX1_UART] = {
250 .uts_reg = IMX1_UTS,
251 .devtype = IMX1_UART,
252 },
253 [IMX21_UART] = {
254 .uts_reg = IMX21_UTS,
255 .devtype = IMX21_UART,
256 },
257 [IMX53_UART] = {
258 .uts_reg = IMX21_UTS,
259 .devtype = IMX53_UART,
260 },
261 [IMX6Q_UART] = {
262 .uts_reg = IMX21_UTS,
263 .devtype = IMX6Q_UART,
264 },
265};
266
267static const struct of_device_id imx_uart_dt_ids[] = {
268 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
269 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
270 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
271 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
272 { /* sentinel */ }
273};
274MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
275
276static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
277{
278 switch (offset) {
279 case UCR1:
280 sport->ucr1 = val;
281 break;
282 case UCR2:
283 sport->ucr2 = val;
284 break;
285 case UCR3:
286 sport->ucr3 = val;
287 break;
288 case UCR4:
289 sport->ucr4 = val;
290 break;
291 case UFCR:
292 sport->ufcr = val;
293 break;
294 default:
295 break;
296 }
297 writel(val, sport->port.membase + offset);
298}
299
300static u32 imx_uart_readl(struct imx_port *sport, u32 offset)
301{
302 switch (offset) {
303 case UCR1:
304 return sport->ucr1;
305 break;
306 case UCR2:
307 /*
308 * UCR2_SRST is the only bit in the cached registers that might
309 * differ from the value that was last written. As it only
310 * automatically becomes one after being cleared, reread
311 * conditionally.
312 */
313 if (!(sport->ucr2 & UCR2_SRST))
314 sport->ucr2 = readl(sport->port.membase + offset);
315 return sport->ucr2;
316 break;
317 case UCR3:
318 return sport->ucr3;
319 break;
320 case UCR4:
321 return sport->ucr4;
322 break;
323 case UFCR:
324 return sport->ufcr;
325 break;
326 default:
327 return readl(sport->port.membase + offset);
328 }
329}
330
331static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
332{
333 return sport->devdata->uts_reg;
334}
335
336static inline int imx_uart_is_imx1(struct imx_port *sport)
337{
338 return sport->devdata->devtype == IMX1_UART;
339}
340
341static inline int imx_uart_is_imx21(struct imx_port *sport)
342{
343 return sport->devdata->devtype == IMX21_UART;
344}
345
346static inline int imx_uart_is_imx53(struct imx_port *sport)
347{
348 return sport->devdata->devtype == IMX53_UART;
349}
350
351static inline int imx_uart_is_imx6q(struct imx_port *sport)
352{
353 return sport->devdata->devtype == IMX6Q_UART;
354}
355/*
356 * Save and restore functions for UCR1, UCR2 and UCR3 registers
357 */
358#if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
359static void imx_uart_ucrs_save(struct imx_port *sport,
360 struct imx_port_ucrs *ucr)
361{
362 /* save control registers */
363 ucr->ucr1 = imx_uart_readl(sport, UCR1);
364 ucr->ucr2 = imx_uart_readl(sport, UCR2);
365 ucr->ucr3 = imx_uart_readl(sport, UCR3);
366}
367
368static void imx_uart_ucrs_restore(struct imx_port *sport,
369 struct imx_port_ucrs *ucr)
370{
371 /* restore control registers */
372 imx_uart_writel(sport, ucr->ucr1, UCR1);
373 imx_uart_writel(sport, ucr->ucr2, UCR2);
374 imx_uart_writel(sport, ucr->ucr3, UCR3);
375}
376#endif
377
378/* called with port.lock taken and irqs caller dependent */
379static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
380{
381 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
382
383 sport->port.mctrl |= TIOCM_RTS;
384 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
385}
386
387/* called with port.lock taken and irqs caller dependent */
388static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
389{
390 *ucr2 &= ~UCR2_CTSC;
391 *ucr2 |= UCR2_CTS;
392
393 sport->port.mctrl &= ~TIOCM_RTS;
394 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
395}
396
397static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
398{
399 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
400}
401
402/* called with port.lock taken and irqs off */
403static void imx_uart_start_rx(struct uart_port *port)
404{
405 struct imx_port *sport = (struct imx_port *)port;
406 unsigned int ucr1, ucr2;
407
408 ucr1 = imx_uart_readl(sport, UCR1);
409 ucr2 = imx_uart_readl(sport, UCR2);
410
411 ucr2 |= UCR2_RXEN;
412
413 if (sport->dma_is_enabled) {
414 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
415 } else {
416 ucr1 |= UCR1_RRDYEN;
417 ucr2 |= UCR2_ATEN;
418 }
419
420 /* Write UCR2 first as it includes RXEN */
421 imx_uart_writel(sport, ucr2, UCR2);
422 imx_uart_writel(sport, ucr1, UCR1);
423}
424
425/* called with port.lock taken and irqs off */
426static void imx_uart_stop_tx(struct uart_port *port)
427{
428 struct imx_port *sport = (struct imx_port *)port;
429 u32 ucr1, ucr4, usr2;
430
431 if (sport->tx_state == OFF)
432 return;
433
434 /*
435 * We are maybe in the SMP context, so if the DMA TX thread is running
436 * on other cpu, we have to wait for it to finish.
437 */
438 if (sport->dma_is_txing)
439 return;
440
441 ucr1 = imx_uart_readl(sport, UCR1);
442 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
443
444 usr2 = imx_uart_readl(sport, USR2);
445 if (!(usr2 & USR2_TXDC)) {
446 /* The shifter is still busy, so retry once TC triggers */
447 return;
448 }
449
450 ucr4 = imx_uart_readl(sport, UCR4);
451 ucr4 &= ~UCR4_TCEN;
452 imx_uart_writel(sport, ucr4, UCR4);
453
454 /* in rs485 mode disable transmitter */
455 if (port->rs485.flags & SER_RS485_ENABLED) {
456 if (sport->tx_state == SEND) {
457 sport->tx_state = WAIT_AFTER_SEND;
458 start_hrtimer_ms(&sport->trigger_stop_tx,
459 port->rs485.delay_rts_after_send);
460 return;
461 }
462
463 if (sport->tx_state == WAIT_AFTER_RTS ||
464 sport->tx_state == WAIT_AFTER_SEND) {
465 u32 ucr2;
466
467 hrtimer_try_to_cancel(&sport->trigger_start_tx);
468
469 ucr2 = imx_uart_readl(sport, UCR2);
470 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
471 imx_uart_rts_active(sport, &ucr2);
472 else
473 imx_uart_rts_inactive(sport, &ucr2);
474 imx_uart_writel(sport, ucr2, UCR2);
475
476 imx_uart_start_rx(port);
477
478 sport->tx_state = OFF;
479 }
480 } else {
481 sport->tx_state = OFF;
482 }
483}
484
485/* called with port.lock taken and irqs off */
486static void imx_uart_stop_rx(struct uart_port *port)
487{
488 struct imx_port *sport = (struct imx_port *)port;
489 u32 ucr1, ucr2;
490
491 ucr1 = imx_uart_readl(sport, UCR1);
492 ucr2 = imx_uart_readl(sport, UCR2);
493
494 if (sport->dma_is_enabled) {
495 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
496 } else {
497 ucr1 &= ~UCR1_RRDYEN;
498 ucr2 &= ~UCR2_ATEN;
499 }
500 imx_uart_writel(sport, ucr1, UCR1);
501
502 ucr2 &= ~UCR2_RXEN;
503 imx_uart_writel(sport, ucr2, UCR2);
504}
505
506/* called with port.lock taken and irqs off */
507static void imx_uart_enable_ms(struct uart_port *port)
508{
509 struct imx_port *sport = (struct imx_port *)port;
510
511 mod_timer(&sport->timer, jiffies);
512
513 mctrl_gpio_enable_ms(sport->gpios);
514}
515
516static void imx_uart_dma_tx(struct imx_port *sport);
517
518/* called with port.lock taken and irqs off */
519static inline void imx_uart_transmit_buffer(struct imx_port *sport)
520{
521 struct circ_buf *xmit = &sport->port.state->xmit;
522
523 if (sport->port.x_char) {
524 /* Send next char */
525 imx_uart_writel(sport, sport->port.x_char, URTX0);
526 sport->port.icount.tx++;
527 sport->port.x_char = 0;
528 return;
529 }
530
531 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
532 imx_uart_stop_tx(&sport->port);
533 return;
534 }
535
536 if (sport->dma_is_enabled) {
537 u32 ucr1;
538 /*
539 * We've just sent a X-char Ensure the TX DMA is enabled
540 * and the TX IRQ is disabled.
541 **/
542 ucr1 = imx_uart_readl(sport, UCR1);
543 ucr1 &= ~UCR1_TRDYEN;
544 if (sport->dma_is_txing) {
545 ucr1 |= UCR1_TXDMAEN;
546 imx_uart_writel(sport, ucr1, UCR1);
547 } else {
548 imx_uart_writel(sport, ucr1, UCR1);
549 imx_uart_dma_tx(sport);
550 }
551
552 return;
553 }
554
555 while (!uart_circ_empty(xmit) &&
556 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
557 /* send xmit->buf[xmit->tail]
558 * out the port here */
559 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
560 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
561 sport->port.icount.tx++;
562 }
563
564 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
565 uart_write_wakeup(&sport->port);
566
567 if (uart_circ_empty(xmit))
568 imx_uart_stop_tx(&sport->port);
569}
570
571static void imx_uart_dma_tx_callback(void *data)
572{
573 struct imx_port *sport = data;
574 struct scatterlist *sgl = &sport->tx_sgl[0];
575 struct circ_buf *xmit = &sport->port.state->xmit;
576 unsigned long flags;
577 u32 ucr1;
578
579 spin_lock_irqsave(&sport->port.lock, flags);
580
581 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
582
583 ucr1 = imx_uart_readl(sport, UCR1);
584 ucr1 &= ~UCR1_TXDMAEN;
585 imx_uart_writel(sport, ucr1, UCR1);
586
587 /* update the stat */
588 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
589 sport->port.icount.tx += sport->tx_bytes;
590
591 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
592
593 sport->dma_is_txing = 0;
594
595 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
596 uart_write_wakeup(&sport->port);
597
598 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
599 imx_uart_dma_tx(sport);
600 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
601 u32 ucr4 = imx_uart_readl(sport, UCR4);
602 ucr4 |= UCR4_TCEN;
603 imx_uart_writel(sport, ucr4, UCR4);
604 }
605
606 spin_unlock_irqrestore(&sport->port.lock, flags);
607}
608
609/* called with port.lock taken and irqs off */
610static void imx_uart_dma_tx(struct imx_port *sport)
611{
612 struct circ_buf *xmit = &sport->port.state->xmit;
613 struct scatterlist *sgl = sport->tx_sgl;
614 struct dma_async_tx_descriptor *desc;
615 struct dma_chan *chan = sport->dma_chan_tx;
616 struct device *dev = sport->port.dev;
617 u32 ucr1, ucr4;
618 int ret;
619
620 if (sport->dma_is_txing)
621 return;
622
623 ucr4 = imx_uart_readl(sport, UCR4);
624 ucr4 &= ~UCR4_TCEN;
625 imx_uart_writel(sport, ucr4, UCR4);
626
627 sport->tx_bytes = uart_circ_chars_pending(xmit);
628
629 if (xmit->tail < xmit->head || xmit->head == 0) {
630 sport->dma_tx_nents = 1;
631 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
632 } else {
633 sport->dma_tx_nents = 2;
634 sg_init_table(sgl, 2);
635 sg_set_buf(sgl, xmit->buf + xmit->tail,
636 UART_XMIT_SIZE - xmit->tail);
637 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
638 }
639
640 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
641 if (ret == 0) {
642 dev_err(dev, "DMA mapping error for TX.\n");
643 return;
644 }
645 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
646 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
647 if (!desc) {
648 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
649 DMA_TO_DEVICE);
650 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
651 return;
652 }
653 desc->callback = imx_uart_dma_tx_callback;
654 desc->callback_param = sport;
655
656 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
657 uart_circ_chars_pending(xmit));
658
659 ucr1 = imx_uart_readl(sport, UCR1);
660 ucr1 |= UCR1_TXDMAEN;
661 imx_uart_writel(sport, ucr1, UCR1);
662
663 /* fire it */
664 sport->dma_is_txing = 1;
665 dmaengine_submit(desc);
666 dma_async_issue_pending(chan);
667 return;
668}
669
670/* called with port.lock taken and irqs off */
671static void imx_uart_start_tx(struct uart_port *port)
672{
673 struct imx_port *sport = (struct imx_port *)port;
674 u32 ucr1;
675
676 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
677 return;
678
679 /*
680 * We cannot simply do nothing here if sport->tx_state == SEND already
681 * because UCR1_TXMPTYEN might already have been cleared in
682 * imx_uart_stop_tx(), but tx_state is still SEND.
683 */
684
685 if (port->rs485.flags & SER_RS485_ENABLED) {
686 if (sport->tx_state == OFF) {
687 u32 ucr2 = imx_uart_readl(sport, UCR2);
688 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
689 imx_uart_rts_active(sport, &ucr2);
690 else
691 imx_uart_rts_inactive(sport, &ucr2);
692 imx_uart_writel(sport, ucr2, UCR2);
693
694 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
695 imx_uart_stop_rx(port);
696
697 sport->tx_state = WAIT_AFTER_RTS;
698 start_hrtimer_ms(&sport->trigger_start_tx,
699 port->rs485.delay_rts_before_send);
700 return;
701 }
702
703 if (sport->tx_state == WAIT_AFTER_SEND
704 || sport->tx_state == WAIT_AFTER_RTS) {
705
706 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
707
708 /*
709 * Enable transmitter and shifter empty irq only if DMA
710 * is off. In the DMA case this is done in the
711 * tx-callback.
712 */
713 if (!sport->dma_is_enabled) {
714 u32 ucr4 = imx_uart_readl(sport, UCR4);
715 ucr4 |= UCR4_TCEN;
716 imx_uart_writel(sport, ucr4, UCR4);
717 }
718
719 sport->tx_state = SEND;
720 }
721 } else {
722 sport->tx_state = SEND;
723 }
724
725 if (!sport->dma_is_enabled) {
726 ucr1 = imx_uart_readl(sport, UCR1);
727 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
728 }
729
730 if (sport->dma_is_enabled) {
731 if (sport->port.x_char) {
732 /* We have X-char to send, so enable TX IRQ and
733 * disable TX DMA to let TX interrupt to send X-char */
734 ucr1 = imx_uart_readl(sport, UCR1);
735 ucr1 &= ~UCR1_TXDMAEN;
736 ucr1 |= UCR1_TRDYEN;
737 imx_uart_writel(sport, ucr1, UCR1);
738 return;
739 }
740
741 if (!uart_circ_empty(&port->state->xmit) &&
742 !uart_tx_stopped(port))
743 imx_uart_dma_tx(sport);
744 return;
745 }
746}
747
748static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
749{
750 struct imx_port *sport = dev_id;
751 u32 usr1;
752
753 imx_uart_writel(sport, USR1_RTSD, USR1);
754 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
755 uart_handle_cts_change(&sport->port, !!usr1);
756 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
757
758 return IRQ_HANDLED;
759}
760
761static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
762{
763 struct imx_port *sport = dev_id;
764 irqreturn_t ret;
765
766 spin_lock(&sport->port.lock);
767
768 ret = __imx_uart_rtsint(irq, dev_id);
769
770 spin_unlock(&sport->port.lock);
771
772 return ret;
773}
774
775static irqreturn_t imx_uart_txint(int irq, void *dev_id)
776{
777 struct imx_port *sport = dev_id;
778
779 spin_lock(&sport->port.lock);
780 imx_uart_transmit_buffer(sport);
781 spin_unlock(&sport->port.lock);
782 return IRQ_HANDLED;
783}
784
785static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
786{
787 struct imx_port *sport = dev_id;
788 unsigned int rx, flg, ignored = 0;
789 struct tty_port *port = &sport->port.state->port;
790
791 while (imx_uart_readl(sport, USR2) & USR2_RDR) {
792 u32 usr2;
793
794 flg = TTY_NORMAL;
795 sport->port.icount.rx++;
796
797 rx = imx_uart_readl(sport, URXD0);
798
799 usr2 = imx_uart_readl(sport, USR2);
800 if (usr2 & USR2_BRCD) {
801 imx_uart_writel(sport, USR2_BRCD, USR2);
802 if (uart_handle_break(&sport->port))
803 continue;
804 }
805
806 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
807 continue;
808
809 if (unlikely(rx & URXD_ERR)) {
810 if (rx & URXD_BRK)
811 sport->port.icount.brk++;
812 else if (rx & URXD_PRERR)
813 sport->port.icount.parity++;
814 else if (rx & URXD_FRMERR)
815 sport->port.icount.frame++;
816 if (rx & URXD_OVRRUN)
817 sport->port.icount.overrun++;
818
819 if (rx & sport->port.ignore_status_mask) {
820 if (++ignored > 100)
821 goto out;
822 continue;
823 }
824
825 rx &= (sport->port.read_status_mask | 0xFF);
826
827 if (rx & URXD_BRK)
828 flg = TTY_BREAK;
829 else if (rx & URXD_PRERR)
830 flg = TTY_PARITY;
831 else if (rx & URXD_FRMERR)
832 flg = TTY_FRAME;
833 if (rx & URXD_OVRRUN)
834 flg = TTY_OVERRUN;
835
836 sport->port.sysrq = 0;
837 }
838
839 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
840 goto out;
841
842 if (tty_insert_flip_char(port, rx, flg) == 0)
843 sport->port.icount.buf_overrun++;
844 }
845
846out:
847 tty_flip_buffer_push(port);
848
849 return IRQ_HANDLED;
850}
851
852static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
853{
854 struct imx_port *sport = dev_id;
855 irqreturn_t ret;
856
857 spin_lock(&sport->port.lock);
858
859 ret = __imx_uart_rxint(irq, dev_id);
860
861 spin_unlock(&sport->port.lock);
862
863 return ret;
864}
865
866static void imx_uart_clear_rx_errors(struct imx_port *sport);
867
868/*
869 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
870 */
871static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
872{
873 unsigned int tmp = TIOCM_DSR;
874 unsigned usr1 = imx_uart_readl(sport, USR1);
875 unsigned usr2 = imx_uart_readl(sport, USR2);
876
877 if (usr1 & USR1_RTSS)
878 tmp |= TIOCM_CTS;
879
880 /* in DCE mode DCDIN is always 0 */
881 if (!(usr2 & USR2_DCDIN))
882 tmp |= TIOCM_CAR;
883
884 if (sport->dte_mode)
885 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
886 tmp |= TIOCM_RI;
887
888 return tmp;
889}
890
891/*
892 * Handle any change of modem status signal since we were last called.
893 */
894static void imx_uart_mctrl_check(struct imx_port *sport)
895{
896 unsigned int status, changed;
897
898 status = imx_uart_get_hwmctrl(sport);
899 changed = status ^ sport->old_status;
900
901 if (changed == 0)
902 return;
903
904 sport->old_status = status;
905
906 if (changed & TIOCM_RI && status & TIOCM_RI)
907 sport->port.icount.rng++;
908 if (changed & TIOCM_DSR)
909 sport->port.icount.dsr++;
910 if (changed & TIOCM_CAR)
911 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
912 if (changed & TIOCM_CTS)
913 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
914
915 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
916}
917
918static irqreturn_t imx_uart_int(int irq, void *dev_id)
919{
920 struct imx_port *sport = dev_id;
921 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
922 irqreturn_t ret = IRQ_NONE;
923
924 spin_lock(&sport->port.lock);
925
926 usr1 = imx_uart_readl(sport, USR1);
927 usr2 = imx_uart_readl(sport, USR2);
928 ucr1 = imx_uart_readl(sport, UCR1);
929 ucr2 = imx_uart_readl(sport, UCR2);
930 ucr3 = imx_uart_readl(sport, UCR3);
931 ucr4 = imx_uart_readl(sport, UCR4);
932
933 /*
934 * Even if a condition is true that can trigger an irq only handle it if
935 * the respective irq source is enabled. This prevents some undesired
936 * actions, for example if a character that sits in the RX FIFO and that
937 * should be fetched via DMA is tried to be fetched using PIO. Or the
938 * receiver is currently off and so reading from URXD0 results in an
939 * exception. So just mask the (raw) status bits for disabled irqs.
940 */
941 if ((ucr1 & UCR1_RRDYEN) == 0)
942 usr1 &= ~USR1_RRDY;
943 if ((ucr2 & UCR2_ATEN) == 0)
944 usr1 &= ~USR1_AGTIM;
945 if ((ucr1 & UCR1_TRDYEN) == 0)
946 usr1 &= ~USR1_TRDY;
947 if ((ucr4 & UCR4_TCEN) == 0)
948 usr2 &= ~USR2_TXDC;
949 if ((ucr3 & UCR3_DTRDEN) == 0)
950 usr1 &= ~USR1_DTRD;
951 if ((ucr1 & UCR1_RTSDEN) == 0)
952 usr1 &= ~USR1_RTSD;
953 if ((ucr3 & UCR3_AWAKEN) == 0)
954 usr1 &= ~USR1_AWAKE;
955 if ((ucr4 & UCR4_OREN) == 0)
956 usr2 &= ~USR2_ORE;
957
958 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
959 imx_uart_writel(sport, USR1_AGTIM, USR1);
960
961 __imx_uart_rxint(irq, dev_id);
962 ret = IRQ_HANDLED;
963 }
964
965 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
966 imx_uart_transmit_buffer(sport);
967 ret = IRQ_HANDLED;
968 }
969
970 if (usr1 & USR1_DTRD) {
971 imx_uart_writel(sport, USR1_DTRD, USR1);
972
973 imx_uart_mctrl_check(sport);
974
975 ret = IRQ_HANDLED;
976 }
977
978 if (usr1 & USR1_RTSD) {
979 __imx_uart_rtsint(irq, dev_id);
980 ret = IRQ_HANDLED;
981 }
982
983 if (usr1 & USR1_AWAKE) {
984 imx_uart_writel(sport, USR1_AWAKE, USR1);
985 ret = IRQ_HANDLED;
986 }
987
988 if (usr2 & USR2_ORE) {
989 sport->port.icount.overrun++;
990 imx_uart_writel(sport, USR2_ORE, USR2);
991 ret = IRQ_HANDLED;
992 }
993
994 spin_unlock(&sport->port.lock);
995
996 return ret;
997}
998
999/*
1000 * Return TIOCSER_TEMT when transmitter is not busy.
1001 */
1002static unsigned int imx_uart_tx_empty(struct uart_port *port)
1003{
1004 struct imx_port *sport = (struct imx_port *)port;
1005 unsigned int ret;
1006
1007 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1008
1009 /* If the TX DMA is working, return 0. */
1010 if (sport->dma_is_txing)
1011 ret = 0;
1012
1013 return ret;
1014}
1015
1016/* called with port.lock taken and irqs off */
1017static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1018{
1019 struct imx_port *sport = (struct imx_port *)port;
1020 unsigned int ret = imx_uart_get_hwmctrl(sport);
1021
1022 mctrl_gpio_get(sport->gpios, &ret);
1023
1024 return ret;
1025}
1026
1027/* called with port.lock taken and irqs off */
1028static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1029{
1030 struct imx_port *sport = (struct imx_port *)port;
1031 u32 ucr3, uts;
1032
1033 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1034 u32 ucr2;
1035
1036 /*
1037 * Turn off autoRTS if RTS is lowered and restore autoRTS
1038 * setting if RTS is raised.
1039 */
1040 ucr2 = imx_uart_readl(sport, UCR2);
1041 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1042 if (mctrl & TIOCM_RTS) {
1043 ucr2 |= UCR2_CTS;
1044 /*
1045 * UCR2_IRTS is unset if and only if the port is
1046 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1047 * to get the state to restore to.
1048 */
1049 if (!(ucr2 & UCR2_IRTS))
1050 ucr2 |= UCR2_CTSC;
1051 }
1052 imx_uart_writel(sport, ucr2, UCR2);
1053 }
1054
1055 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1056 if (!(mctrl & TIOCM_DTR))
1057 ucr3 |= UCR3_DSR;
1058 imx_uart_writel(sport, ucr3, UCR3);
1059
1060 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1061 if (mctrl & TIOCM_LOOP)
1062 uts |= UTS_LOOP;
1063 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1064
1065 mctrl_gpio_set(sport->gpios, mctrl);
1066}
1067
1068/*
1069 * Interrupts always disabled.
1070 */
1071static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1072{
1073 struct imx_port *sport = (struct imx_port *)port;
1074 unsigned long flags;
1075 u32 ucr1;
1076
1077 spin_lock_irqsave(&sport->port.lock, flags);
1078
1079 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1080
1081 if (break_state != 0)
1082 ucr1 |= UCR1_SNDBRK;
1083
1084 imx_uart_writel(sport, ucr1, UCR1);
1085
1086 spin_unlock_irqrestore(&sport->port.lock, flags);
1087}
1088
1089/*
1090 * This is our per-port timeout handler, for checking the
1091 * modem status signals.
1092 */
1093static void imx_uart_timeout(struct timer_list *t)
1094{
1095 struct imx_port *sport = from_timer(sport, t, timer);
1096 unsigned long flags;
1097
1098 if (sport->port.state) {
1099 spin_lock_irqsave(&sport->port.lock, flags);
1100 imx_uart_mctrl_check(sport);
1101 spin_unlock_irqrestore(&sport->port.lock, flags);
1102
1103 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1104 }
1105}
1106
1107/*
1108 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1109 * [1] the RX DMA buffer is full.
1110 * [2] the aging timer expires
1111 *
1112 * Condition [2] is triggered when a character has been sitting in the FIFO
1113 * for at least 8 byte durations.
1114 */
1115static void imx_uart_dma_rx_callback(void *data)
1116{
1117 struct imx_port *sport = data;
1118 struct dma_chan *chan = sport->dma_chan_rx;
1119 struct scatterlist *sgl = &sport->rx_sgl;
1120 struct tty_port *port = &sport->port.state->port;
1121 struct dma_tx_state state;
1122 struct circ_buf *rx_ring = &sport->rx_ring;
1123 enum dma_status status;
1124 unsigned int w_bytes = 0;
1125 unsigned int r_bytes;
1126 unsigned int bd_size;
1127
1128 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1129
1130 if (status == DMA_ERROR) {
1131 imx_uart_clear_rx_errors(sport);
1132 return;
1133 }
1134
1135 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1136
1137 /*
1138 * The state-residue variable represents the empty space
1139 * relative to the entire buffer. Taking this in consideration
1140 * the head is always calculated base on the buffer total
1141 * length - DMA transaction residue. The UART script from the
1142 * SDMA firmware will jump to the next buffer descriptor,
1143 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1144 * Taking this in consideration the tail is always at the
1145 * beginning of the buffer descriptor that contains the head.
1146 */
1147
1148 /* Calculate the head */
1149 rx_ring->head = sg_dma_len(sgl) - state.residue;
1150
1151 /* Calculate the tail. */
1152 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1153 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1154
1155 if (rx_ring->head <= sg_dma_len(sgl) &&
1156 rx_ring->head > rx_ring->tail) {
1157
1158 /* Move data from tail to head */
1159 r_bytes = rx_ring->head - rx_ring->tail;
1160
1161 /* CPU claims ownership of RX DMA buffer */
1162 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1163 DMA_FROM_DEVICE);
1164
1165 w_bytes = tty_insert_flip_string(port,
1166 sport->rx_buf + rx_ring->tail, r_bytes);
1167
1168 /* UART retrieves ownership of RX DMA buffer */
1169 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1170 DMA_FROM_DEVICE);
1171
1172 if (w_bytes != r_bytes)
1173 sport->port.icount.buf_overrun++;
1174
1175 sport->port.icount.rx += w_bytes;
1176 } else {
1177 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1178 WARN_ON(rx_ring->head <= rx_ring->tail);
1179 }
1180 }
1181
1182 if (w_bytes) {
1183 tty_flip_buffer_push(port);
1184 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1185 }
1186}
1187
1188static int imx_uart_start_rx_dma(struct imx_port *sport)
1189{
1190 struct scatterlist *sgl = &sport->rx_sgl;
1191 struct dma_chan *chan = sport->dma_chan_rx;
1192 struct device *dev = sport->port.dev;
1193 struct dma_async_tx_descriptor *desc;
1194 int ret;
1195
1196 sport->rx_ring.head = 0;
1197 sport->rx_ring.tail = 0;
1198
1199 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size);
1200 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1201 if (ret == 0) {
1202 dev_err(dev, "DMA mapping error for RX.\n");
1203 return -EINVAL;
1204 }
1205
1206 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1207 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1208 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1209
1210 if (!desc) {
1211 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1212 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1213 return -EINVAL;
1214 }
1215 desc->callback = imx_uart_dma_rx_callback;
1216 desc->callback_param = sport;
1217
1218 dev_dbg(dev, "RX: prepare for the DMA.\n");
1219 sport->dma_is_rxing = 1;
1220 sport->rx_cookie = dmaengine_submit(desc);
1221 dma_async_issue_pending(chan);
1222 return 0;
1223}
1224
1225static void imx_uart_clear_rx_errors(struct imx_port *sport)
1226{
1227 struct tty_port *port = &sport->port.state->port;
1228 u32 usr1, usr2;
1229
1230 usr1 = imx_uart_readl(sport, USR1);
1231 usr2 = imx_uart_readl(sport, USR2);
1232
1233 if (usr2 & USR2_BRCD) {
1234 sport->port.icount.brk++;
1235 imx_uart_writel(sport, USR2_BRCD, USR2);
1236 uart_handle_break(&sport->port);
1237 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1238 sport->port.icount.buf_overrun++;
1239 tty_flip_buffer_push(port);
1240 } else {
1241 if (usr1 & USR1_FRAMERR) {
1242 sport->port.icount.frame++;
1243 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1244 } else if (usr1 & USR1_PARITYERR) {
1245 sport->port.icount.parity++;
1246 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1247 }
1248 }
1249
1250 if (usr2 & USR2_ORE) {
1251 sport->port.icount.overrun++;
1252 imx_uart_writel(sport, USR2_ORE, USR2);
1253 }
1254
1255}
1256
1257#define TXTL_DEFAULT 2 /* reset default */
1258#define RXTL_DEFAULT 1 /* reset default */
1259#define TXTL_DMA 8 /* DMA burst setting */
1260#define RXTL_DMA 9 /* DMA burst setting */
1261
1262static void imx_uart_setup_ufcr(struct imx_port *sport,
1263 unsigned char txwl, unsigned char rxwl)
1264{
1265 unsigned int val;
1266
1267 /* set receiver / transmitter trigger level */
1268 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1269 val |= txwl << UFCR_TXTL_SHF | rxwl;
1270 imx_uart_writel(sport, val, UFCR);
1271}
1272
1273static void imx_uart_dma_exit(struct imx_port *sport)
1274{
1275 if (sport->dma_chan_rx) {
1276 dmaengine_terminate_sync(sport->dma_chan_rx);
1277 dma_release_channel(sport->dma_chan_rx);
1278 sport->dma_chan_rx = NULL;
1279 sport->rx_cookie = -EINVAL;
1280 kfree(sport->rx_buf);
1281 sport->rx_buf = NULL;
1282 }
1283
1284 if (sport->dma_chan_tx) {
1285 dmaengine_terminate_sync(sport->dma_chan_tx);
1286 dma_release_channel(sport->dma_chan_tx);
1287 sport->dma_chan_tx = NULL;
1288 }
1289}
1290
1291static int imx_uart_dma_init(struct imx_port *sport)
1292{
1293 struct dma_slave_config slave_config = {};
1294 struct device *dev = sport->port.dev;
1295 int ret;
1296
1297 /* Prepare for RX : */
1298 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1299 if (!sport->dma_chan_rx) {
1300 dev_dbg(dev, "cannot get the DMA channel.\n");
1301 ret = -EINVAL;
1302 goto err;
1303 }
1304
1305 slave_config.direction = DMA_DEV_TO_MEM;
1306 slave_config.src_addr = sport->port.mapbase + URXD0;
1307 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1308 /* one byte less than the watermark level to enable the aging timer */
1309 slave_config.src_maxburst = RXTL_DMA - 1;
1310 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1311 if (ret) {
1312 dev_err(dev, "error in RX dma configuration.\n");
1313 goto err;
1314 }
1315
1316 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods;
1317 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL);
1318 if (!sport->rx_buf) {
1319 ret = -ENOMEM;
1320 goto err;
1321 }
1322 sport->rx_ring.buf = sport->rx_buf;
1323
1324 /* Prepare for TX : */
1325 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1326 if (!sport->dma_chan_tx) {
1327 dev_err(dev, "cannot get the TX DMA channel!\n");
1328 ret = -EINVAL;
1329 goto err;
1330 }
1331
1332 slave_config.direction = DMA_MEM_TO_DEV;
1333 slave_config.dst_addr = sport->port.mapbase + URTX0;
1334 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1335 slave_config.dst_maxburst = TXTL_DMA;
1336 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1337 if (ret) {
1338 dev_err(dev, "error in TX dma configuration.");
1339 goto err;
1340 }
1341
1342 return 0;
1343err:
1344 imx_uart_dma_exit(sport);
1345 return ret;
1346}
1347
1348static void imx_uart_enable_dma(struct imx_port *sport)
1349{
1350 u32 ucr1;
1351
1352 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1353
1354 /* set UCR1 */
1355 ucr1 = imx_uart_readl(sport, UCR1);
1356 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1357 imx_uart_writel(sport, ucr1, UCR1);
1358
1359 sport->dma_is_enabled = 1;
1360}
1361
1362static void imx_uart_disable_dma(struct imx_port *sport)
1363{
1364 u32 ucr1;
1365
1366 /* clear UCR1 */
1367 ucr1 = imx_uart_readl(sport, UCR1);
1368 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1369 imx_uart_writel(sport, ucr1, UCR1);
1370
1371 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1372
1373 sport->dma_is_enabled = 0;
1374}
1375
1376/* half the RX buffer size */
1377#define CTSTL 16
1378
1379static int imx_uart_startup(struct uart_port *port)
1380{
1381 struct imx_port *sport = (struct imx_port *)port;
1382 int retval, i;
1383 unsigned long flags;
1384 int dma_is_inited = 0;
1385 u32 ucr1, ucr2, ucr3, ucr4;
1386
1387 retval = clk_prepare_enable(sport->clk_per);
1388 if (retval)
1389 return retval;
1390 retval = clk_prepare_enable(sport->clk_ipg);
1391 if (retval) {
1392 clk_disable_unprepare(sport->clk_per);
1393 return retval;
1394 }
1395
1396 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1397
1398 /* disable the DREN bit (Data Ready interrupt enable) before
1399 * requesting IRQs
1400 */
1401 ucr4 = imx_uart_readl(sport, UCR4);
1402
1403 /* set the trigger level for CTS */
1404 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1405 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1406
1407 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1408
1409 /* Can we enable the DMA support? */
1410 if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1411 dma_is_inited = 1;
1412
1413 spin_lock_irqsave(&sport->port.lock, flags);
1414 /* Reset fifo's and state machines */
1415 i = 100;
1416
1417 ucr2 = imx_uart_readl(sport, UCR2);
1418 ucr2 &= ~UCR2_SRST;
1419 imx_uart_writel(sport, ucr2, UCR2);
1420
1421 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1422 udelay(1);
1423
1424 /*
1425 * Finally, clear and enable interrupts
1426 */
1427 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1428 imx_uart_writel(sport, USR2_ORE, USR2);
1429
1430 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1431 ucr1 |= UCR1_UARTEN;
1432 if (sport->have_rtscts)
1433 ucr1 |= UCR1_RTSDEN;
1434
1435 imx_uart_writel(sport, ucr1, UCR1);
1436
1437 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1438 if (!sport->dma_is_enabled)
1439 ucr4 |= UCR4_OREN;
1440 if (sport->inverted_rx)
1441 ucr4 |= UCR4_INVR;
1442 imx_uart_writel(sport, ucr4, UCR4);
1443
1444 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1445 /*
1446 * configure tx polarity before enabling tx
1447 */
1448 if (sport->inverted_tx)
1449 ucr3 |= UCR3_INVT;
1450
1451 if (!imx_uart_is_imx1(sport)) {
1452 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1453
1454 if (sport->dte_mode)
1455 /* disable broken interrupts */
1456 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1457 }
1458 imx_uart_writel(sport, ucr3, UCR3);
1459
1460 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1461 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1462 if (!sport->have_rtscts)
1463 ucr2 |= UCR2_IRTS;
1464 /*
1465 * make sure the edge sensitive RTS-irq is disabled,
1466 * we're using RTSD instead.
1467 */
1468 if (!imx_uart_is_imx1(sport))
1469 ucr2 &= ~UCR2_RTSEN;
1470 imx_uart_writel(sport, ucr2, UCR2);
1471
1472 /*
1473 * Enable modem status interrupts
1474 */
1475 imx_uart_enable_ms(&sport->port);
1476
1477 if (dma_is_inited) {
1478 imx_uart_enable_dma(sport);
1479 imx_uart_start_rx_dma(sport);
1480 } else {
1481 ucr1 = imx_uart_readl(sport, UCR1);
1482 ucr1 |= UCR1_RRDYEN;
1483 imx_uart_writel(sport, ucr1, UCR1);
1484
1485 ucr2 = imx_uart_readl(sport, UCR2);
1486 ucr2 |= UCR2_ATEN;
1487 imx_uart_writel(sport, ucr2, UCR2);
1488 }
1489
1490 spin_unlock_irqrestore(&sport->port.lock, flags);
1491
1492 return 0;
1493}
1494
1495static void imx_uart_shutdown(struct uart_port *port)
1496{
1497 struct imx_port *sport = (struct imx_port *)port;
1498 unsigned long flags;
1499 u32 ucr1, ucr2, ucr4;
1500
1501 if (sport->dma_is_enabled) {
1502 dmaengine_terminate_sync(sport->dma_chan_tx);
1503 if (sport->dma_is_txing) {
1504 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1505 sport->dma_tx_nents, DMA_TO_DEVICE);
1506 sport->dma_is_txing = 0;
1507 }
1508 dmaengine_terminate_sync(sport->dma_chan_rx);
1509 if (sport->dma_is_rxing) {
1510 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1511 1, DMA_FROM_DEVICE);
1512 sport->dma_is_rxing = 0;
1513 }
1514
1515 spin_lock_irqsave(&sport->port.lock, flags);
1516 imx_uart_stop_tx(port);
1517 imx_uart_stop_rx(port);
1518 imx_uart_disable_dma(sport);
1519 spin_unlock_irqrestore(&sport->port.lock, flags);
1520 imx_uart_dma_exit(sport);
1521 }
1522
1523 mctrl_gpio_disable_ms(sport->gpios);
1524
1525 spin_lock_irqsave(&sport->port.lock, flags);
1526 ucr2 = imx_uart_readl(sport, UCR2);
1527 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1528 imx_uart_writel(sport, ucr2, UCR2);
1529 spin_unlock_irqrestore(&sport->port.lock, flags);
1530
1531 /*
1532 * Stop our timer.
1533 */
1534 del_timer_sync(&sport->timer);
1535
1536 /*
1537 * Disable all interrupts, port and break condition.
1538 */
1539
1540 spin_lock_irqsave(&sport->port.lock, flags);
1541
1542 ucr1 = imx_uart_readl(sport, UCR1);
1543 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN);
1544 imx_uart_writel(sport, ucr1, UCR1);
1545
1546 ucr4 = imx_uart_readl(sport, UCR4);
1547 ucr4 &= ~(UCR4_OREN | UCR4_TCEN);
1548 imx_uart_writel(sport, ucr4, UCR4);
1549
1550 spin_unlock_irqrestore(&sport->port.lock, flags);
1551
1552 clk_disable_unprepare(sport->clk_per);
1553 clk_disable_unprepare(sport->clk_ipg);
1554}
1555
1556/* called with port.lock taken and irqs off */
1557static void imx_uart_flush_buffer(struct uart_port *port)
1558{
1559 struct imx_port *sport = (struct imx_port *)port;
1560 struct scatterlist *sgl = &sport->tx_sgl[0];
1561 u32 ucr2;
1562 int i = 100, ubir, ubmr, uts;
1563
1564 if (!sport->dma_chan_tx)
1565 return;
1566
1567 sport->tx_bytes = 0;
1568 dmaengine_terminate_all(sport->dma_chan_tx);
1569 if (sport->dma_is_txing) {
1570 u32 ucr1;
1571
1572 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1573 DMA_TO_DEVICE);
1574 ucr1 = imx_uart_readl(sport, UCR1);
1575 ucr1 &= ~UCR1_TXDMAEN;
1576 imx_uart_writel(sport, ucr1, UCR1);
1577 sport->dma_is_txing = 0;
1578 }
1579
1580 /*
1581 * According to the Reference Manual description of the UART SRST bit:
1582 *
1583 * "Reset the transmit and receive state machines,
1584 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1585 * and UTS[6-3]".
1586 *
1587 * We don't need to restore the old values from USR1, USR2, URXD and
1588 * UTXD. UBRC is read only, so only save/restore the other three
1589 * registers.
1590 */
1591 ubir = imx_uart_readl(sport, UBIR);
1592 ubmr = imx_uart_readl(sport, UBMR);
1593 uts = imx_uart_readl(sport, IMX21_UTS);
1594
1595 ucr2 = imx_uart_readl(sport, UCR2);
1596 ucr2 &= ~UCR2_SRST;
1597 imx_uart_writel(sport, ucr2, UCR2);
1598
1599 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1600 udelay(1);
1601
1602 /* Restore the registers */
1603 imx_uart_writel(sport, ubir, UBIR);
1604 imx_uart_writel(sport, ubmr, UBMR);
1605 imx_uart_writel(sport, uts, IMX21_UTS);
1606}
1607
1608static void
1609imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1610 struct ktermios *old)
1611{
1612 struct imx_port *sport = (struct imx_port *)port;
1613 unsigned long flags;
1614 u32 ucr2, old_ucr2, ufcr;
1615 unsigned int baud, quot;
1616 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1617 unsigned long div;
1618 unsigned long num, denom, old_ubir, old_ubmr;
1619 uint64_t tdiv64;
1620
1621 /*
1622 * We only support CS7 and CS8.
1623 */
1624 while ((termios->c_cflag & CSIZE) != CS7 &&
1625 (termios->c_cflag & CSIZE) != CS8) {
1626 termios->c_cflag &= ~CSIZE;
1627 termios->c_cflag |= old_csize;
1628 old_csize = CS8;
1629 }
1630
1631 del_timer_sync(&sport->timer);
1632
1633 /*
1634 * Ask the core to calculate the divisor for us.
1635 */
1636 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1637 quot = uart_get_divisor(port, baud);
1638
1639 spin_lock_irqsave(&sport->port.lock, flags);
1640
1641 /*
1642 * Read current UCR2 and save it for future use, then clear all the bits
1643 * except those we will or may need to preserve.
1644 */
1645 old_ucr2 = imx_uart_readl(sport, UCR2);
1646 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1647
1648 ucr2 |= UCR2_SRST | UCR2_IRTS;
1649 if ((termios->c_cflag & CSIZE) == CS8)
1650 ucr2 |= UCR2_WS;
1651
1652 if (!sport->have_rtscts)
1653 termios->c_cflag &= ~CRTSCTS;
1654
1655 if (port->rs485.flags & SER_RS485_ENABLED) {
1656 /*
1657 * RTS is mandatory for rs485 operation, so keep
1658 * it under manual control and keep transmitter
1659 * disabled.
1660 */
1661 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1662 imx_uart_rts_active(sport, &ucr2);
1663 else
1664 imx_uart_rts_inactive(sport, &ucr2);
1665
1666 } else if (termios->c_cflag & CRTSCTS) {
1667 /*
1668 * Only let receiver control RTS output if we were not requested
1669 * to have RTS inactive (which then should take precedence).
1670 */
1671 if (ucr2 & UCR2_CTS)
1672 ucr2 |= UCR2_CTSC;
1673 }
1674
1675 if (termios->c_cflag & CRTSCTS)
1676 ucr2 &= ~UCR2_IRTS;
1677 if (termios->c_cflag & CSTOPB)
1678 ucr2 |= UCR2_STPB;
1679 if (termios->c_cflag & PARENB) {
1680 ucr2 |= UCR2_PREN;
1681 if (termios->c_cflag & PARODD)
1682 ucr2 |= UCR2_PROE;
1683 }
1684
1685 sport->port.read_status_mask = 0;
1686 if (termios->c_iflag & INPCK)
1687 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1688 if (termios->c_iflag & (BRKINT | PARMRK))
1689 sport->port.read_status_mask |= URXD_BRK;
1690
1691 /*
1692 * Characters to ignore
1693 */
1694 sport->port.ignore_status_mask = 0;
1695 if (termios->c_iflag & IGNPAR)
1696 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1697 if (termios->c_iflag & IGNBRK) {
1698 sport->port.ignore_status_mask |= URXD_BRK;
1699 /*
1700 * If we're ignoring parity and break indicators,
1701 * ignore overruns too (for real raw support).
1702 */
1703 if (termios->c_iflag & IGNPAR)
1704 sport->port.ignore_status_mask |= URXD_OVRRUN;
1705 }
1706
1707 if ((termios->c_cflag & CREAD) == 0)
1708 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1709
1710 /*
1711 * Update the per-port timeout.
1712 */
1713 uart_update_timeout(port, termios->c_cflag, baud);
1714
1715 /* custom-baudrate handling */
1716 div = sport->port.uartclk / (baud * 16);
1717 if (baud == 38400 && quot != div)
1718 baud = sport->port.uartclk / (quot * 16);
1719
1720 div = sport->port.uartclk / (baud * 16);
1721 if (div > 7)
1722 div = 7;
1723 if (!div)
1724 div = 1;
1725
1726 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1727 1 << 16, 1 << 16, &num, &denom);
1728
1729 tdiv64 = sport->port.uartclk;
1730 tdiv64 *= num;
1731 do_div(tdiv64, denom * 16 * div);
1732 tty_termios_encode_baud_rate(termios,
1733 (speed_t)tdiv64, (speed_t)tdiv64);
1734
1735 num -= 1;
1736 denom -= 1;
1737
1738 ufcr = imx_uart_readl(sport, UFCR);
1739 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1740 imx_uart_writel(sport, ufcr, UFCR);
1741
1742 /*
1743 * Two registers below should always be written both and in this
1744 * particular order. One consequence is that we need to check if any of
1745 * them changes and then update both. We do need the check for change
1746 * as even writing the same values seem to "restart"
1747 * transmission/receiving logic in the hardware, that leads to data
1748 * breakage even when rate doesn't in fact change. E.g., user switches
1749 * RTS/CTS handshake and suddenly gets broken bytes.
1750 */
1751 old_ubir = imx_uart_readl(sport, UBIR);
1752 old_ubmr = imx_uart_readl(sport, UBMR);
1753 if (old_ubir != num || old_ubmr != denom) {
1754 imx_uart_writel(sport, num, UBIR);
1755 imx_uart_writel(sport, denom, UBMR);
1756 }
1757
1758 if (!imx_uart_is_imx1(sport))
1759 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1760 IMX21_ONEMS);
1761
1762 imx_uart_writel(sport, ucr2, UCR2);
1763
1764 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1765 imx_uart_enable_ms(&sport->port);
1766
1767 spin_unlock_irqrestore(&sport->port.lock, flags);
1768}
1769
1770static const char *imx_uart_type(struct uart_port *port)
1771{
1772 struct imx_port *sport = (struct imx_port *)port;
1773
1774 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1775}
1776
1777/*
1778 * Configure/autoconfigure the port.
1779 */
1780static void imx_uart_config_port(struct uart_port *port, int flags)
1781{
1782 struct imx_port *sport = (struct imx_port *)port;
1783
1784 if (flags & UART_CONFIG_TYPE)
1785 sport->port.type = PORT_IMX;
1786}
1787
1788/*
1789 * Verify the new serial_struct (for TIOCSSERIAL).
1790 * The only change we allow are to the flags and type, and
1791 * even then only between PORT_IMX and PORT_UNKNOWN
1792 */
1793static int
1794imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1795{
1796 struct imx_port *sport = (struct imx_port *)port;
1797 int ret = 0;
1798
1799 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1800 ret = -EINVAL;
1801 if (sport->port.irq != ser->irq)
1802 ret = -EINVAL;
1803 if (ser->io_type != UPIO_MEM)
1804 ret = -EINVAL;
1805 if (sport->port.uartclk / 16 != ser->baud_base)
1806 ret = -EINVAL;
1807 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1808 ret = -EINVAL;
1809 if (sport->port.iobase != ser->port)
1810 ret = -EINVAL;
1811 if (ser->hub6 != 0)
1812 ret = -EINVAL;
1813 return ret;
1814}
1815
1816#if defined(CONFIG_CONSOLE_POLL)
1817
1818static int imx_uart_poll_init(struct uart_port *port)
1819{
1820 struct imx_port *sport = (struct imx_port *)port;
1821 unsigned long flags;
1822 u32 ucr1, ucr2;
1823 int retval;
1824
1825 retval = clk_prepare_enable(sport->clk_ipg);
1826 if (retval)
1827 return retval;
1828 retval = clk_prepare_enable(sport->clk_per);
1829 if (retval)
1830 clk_disable_unprepare(sport->clk_ipg);
1831
1832 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1833
1834 spin_lock_irqsave(&sport->port.lock, flags);
1835
1836 /*
1837 * Be careful about the order of enabling bits here. First enable the
1838 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1839 * This prevents that a character that already sits in the RX fifo is
1840 * triggering an irq but the try to fetch it from there results in an
1841 * exception because UARTEN or RXEN is still off.
1842 */
1843 ucr1 = imx_uart_readl(sport, UCR1);
1844 ucr2 = imx_uart_readl(sport, UCR2);
1845
1846 if (imx_uart_is_imx1(sport))
1847 ucr1 |= IMX1_UCR1_UARTCLKEN;
1848
1849 ucr1 |= UCR1_UARTEN;
1850 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1851
1852 ucr2 |= UCR2_RXEN | UCR2_TXEN;
1853 ucr2 &= ~UCR2_ATEN;
1854
1855 imx_uart_writel(sport, ucr1, UCR1);
1856 imx_uart_writel(sport, ucr2, UCR2);
1857
1858 /* now enable irqs */
1859 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1860 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1861
1862 spin_unlock_irqrestore(&sport->port.lock, flags);
1863
1864 return 0;
1865}
1866
1867static int imx_uart_poll_get_char(struct uart_port *port)
1868{
1869 struct imx_port *sport = (struct imx_port *)port;
1870 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1871 return NO_POLL_CHAR;
1872
1873 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1874}
1875
1876static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1877{
1878 struct imx_port *sport = (struct imx_port *)port;
1879 unsigned int status;
1880
1881 /* drain */
1882 do {
1883 status = imx_uart_readl(sport, USR1);
1884 } while (~status & USR1_TRDY);
1885
1886 /* write */
1887 imx_uart_writel(sport, c, URTX0);
1888
1889 /* flush */
1890 do {
1891 status = imx_uart_readl(sport, USR2);
1892 } while (~status & USR2_TXDC);
1893}
1894#endif
1895
1896/* called with port.lock taken and irqs off or from .probe without locking */
1897static int imx_uart_rs485_config(struct uart_port *port,
1898 struct serial_rs485 *rs485conf)
1899{
1900 struct imx_port *sport = (struct imx_port *)port;
1901 u32 ucr2;
1902
1903 /* RTS is required to control the transmitter */
1904 if (!sport->have_rtscts && !sport->have_rtsgpio)
1905 rs485conf->flags &= ~SER_RS485_ENABLED;
1906
1907 if (rs485conf->flags & SER_RS485_ENABLED) {
1908 /* Enable receiver if low-active RTS signal is requested */
1909 if (sport->have_rtscts && !sport->have_rtsgpio &&
1910 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1911 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1912
1913 /* disable transmitter */
1914 ucr2 = imx_uart_readl(sport, UCR2);
1915 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1916 imx_uart_rts_active(sport, &ucr2);
1917 else
1918 imx_uart_rts_inactive(sport, &ucr2);
1919 imx_uart_writel(sport, ucr2, UCR2);
1920 }
1921
1922 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1923 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1924 rs485conf->flags & SER_RS485_RX_DURING_TX)
1925 imx_uart_start_rx(port);
1926
1927 port->rs485 = *rs485conf;
1928
1929 return 0;
1930}
1931
1932static const struct uart_ops imx_uart_pops = {
1933 .tx_empty = imx_uart_tx_empty,
1934 .set_mctrl = imx_uart_set_mctrl,
1935 .get_mctrl = imx_uart_get_mctrl,
1936 .stop_tx = imx_uart_stop_tx,
1937 .start_tx = imx_uart_start_tx,
1938 .stop_rx = imx_uart_stop_rx,
1939 .enable_ms = imx_uart_enable_ms,
1940 .break_ctl = imx_uart_break_ctl,
1941 .startup = imx_uart_startup,
1942 .shutdown = imx_uart_shutdown,
1943 .flush_buffer = imx_uart_flush_buffer,
1944 .set_termios = imx_uart_set_termios,
1945 .type = imx_uart_type,
1946 .config_port = imx_uart_config_port,
1947 .verify_port = imx_uart_verify_port,
1948#if defined(CONFIG_CONSOLE_POLL)
1949 .poll_init = imx_uart_poll_init,
1950 .poll_get_char = imx_uart_poll_get_char,
1951 .poll_put_char = imx_uart_poll_put_char,
1952#endif
1953};
1954
1955static struct imx_port *imx_uart_ports[UART_NR];
1956
1957#if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
1958static void imx_uart_console_putchar(struct uart_port *port, int ch)
1959{
1960 struct imx_port *sport = (struct imx_port *)port;
1961
1962 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1963 barrier();
1964
1965 imx_uart_writel(sport, ch, URTX0);
1966}
1967
1968/*
1969 * Interrupts are disabled on entering
1970 */
1971static void
1972imx_uart_console_write(struct console *co, const char *s, unsigned int count)
1973{
1974 struct imx_port *sport = imx_uart_ports[co->index];
1975 struct imx_port_ucrs old_ucr;
1976 unsigned long flags;
1977 unsigned int ucr1;
1978 int locked = 1;
1979
1980 if (sport->port.sysrq)
1981 locked = 0;
1982 else if (oops_in_progress)
1983 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1984 else
1985 spin_lock_irqsave(&sport->port.lock, flags);
1986
1987 /*
1988 * First, save UCR1/2/3 and then disable interrupts
1989 */
1990 imx_uart_ucrs_save(sport, &old_ucr);
1991 ucr1 = old_ucr.ucr1;
1992
1993 if (imx_uart_is_imx1(sport))
1994 ucr1 |= IMX1_UCR1_UARTCLKEN;
1995 ucr1 |= UCR1_UARTEN;
1996 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1997
1998 imx_uart_writel(sport, ucr1, UCR1);
1999
2000 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2001
2002 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
2003
2004 /*
2005 * Finally, wait for transmitter to become empty
2006 * and restore UCR1/2/3
2007 */
2008 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC));
2009
2010 imx_uart_ucrs_restore(sport, &old_ucr);
2011
2012 if (locked)
2013 spin_unlock_irqrestore(&sport->port.lock, flags);
2014}
2015
2016/*
2017 * If the port was already initialised (eg, by a boot loader),
2018 * try to determine the current setup.
2019 */
2020static void __init
2021imx_uart_console_get_options(struct imx_port *sport, int *baud,
2022 int *parity, int *bits)
2023{
2024
2025 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2026 /* ok, the port was enabled */
2027 unsigned int ucr2, ubir, ubmr, uartclk;
2028 unsigned int baud_raw;
2029 unsigned int ucfr_rfdiv;
2030
2031 ucr2 = imx_uart_readl(sport, UCR2);
2032
2033 *parity = 'n';
2034 if (ucr2 & UCR2_PREN) {
2035 if (ucr2 & UCR2_PROE)
2036 *parity = 'o';
2037 else
2038 *parity = 'e';
2039 }
2040
2041 if (ucr2 & UCR2_WS)
2042 *bits = 8;
2043 else
2044 *bits = 7;
2045
2046 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2047 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2048
2049 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2050 if (ucfr_rfdiv == 6)
2051 ucfr_rfdiv = 7;
2052 else
2053 ucfr_rfdiv = 6 - ucfr_rfdiv;
2054
2055 uartclk = clk_get_rate(sport->clk_per);
2056 uartclk /= ucfr_rfdiv;
2057
2058 { /*
2059 * The next code provides exact computation of
2060 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2061 * without need of float support or long long division,
2062 * which would be required to prevent 32bit arithmetic overflow
2063 */
2064 unsigned int mul = ubir + 1;
2065 unsigned int div = 16 * (ubmr + 1);
2066 unsigned int rem = uartclk % div;
2067
2068 baud_raw = (uartclk / div) * mul;
2069 baud_raw += (rem * mul + div / 2) / div;
2070 *baud = (baud_raw + 50) / 100 * 100;
2071 }
2072
2073 if (*baud != baud_raw)
2074 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2075 baud_raw, *baud);
2076 }
2077}
2078
2079static int __init
2080imx_uart_console_setup(struct console *co, char *options)
2081{
2082 struct imx_port *sport;
2083 int baud = 9600;
2084 int bits = 8;
2085 int parity = 'n';
2086 int flow = 'n';
2087 int retval;
2088
2089 /*
2090 * Check whether an invalid uart number has been specified, and
2091 * if so, search for the first available port that does have
2092 * console support.
2093 */
2094 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2095 co->index = 0;
2096 sport = imx_uart_ports[co->index];
2097 if (sport == NULL)
2098 return -ENODEV;
2099
2100 /* For setting the registers, we only need to enable the ipg clock. */
2101 retval = clk_prepare_enable(sport->clk_ipg);
2102 if (retval)
2103 goto error_console;
2104
2105 if (options)
2106 uart_parse_options(options, &baud, &parity, &bits, &flow);
2107 else
2108 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2109
2110 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2111
2112 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2113
2114 if (retval) {
2115 clk_disable_unprepare(sport->clk_ipg);
2116 goto error_console;
2117 }
2118
2119 retval = clk_prepare_enable(sport->clk_per);
2120 if (retval)
2121 clk_disable_unprepare(sport->clk_ipg);
2122
2123error_console:
2124 return retval;
2125}
2126
2127static struct uart_driver imx_uart_uart_driver;
2128static struct console imx_uart_console = {
2129 .name = DEV_NAME,
2130 .write = imx_uart_console_write,
2131 .device = uart_console_device,
2132 .setup = imx_uart_console_setup,
2133 .flags = CON_PRINTBUFFER,
2134 .index = -1,
2135 .data = &imx_uart_uart_driver,
2136};
2137
2138#define IMX_CONSOLE &imx_uart_console
2139
2140#else
2141#define IMX_CONSOLE NULL
2142#endif
2143
2144static struct uart_driver imx_uart_uart_driver = {
2145 .owner = THIS_MODULE,
2146 .driver_name = DRIVER_NAME,
2147 .dev_name = DEV_NAME,
2148 .major = SERIAL_IMX_MAJOR,
2149 .minor = MINOR_START,
2150 .nr = ARRAY_SIZE(imx_uart_ports),
2151 .cons = IMX_CONSOLE,
2152};
2153
2154static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2155{
2156 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2157 unsigned long flags;
2158
2159 spin_lock_irqsave(&sport->port.lock, flags);
2160 if (sport->tx_state == WAIT_AFTER_RTS)
2161 imx_uart_start_tx(&sport->port);
2162 spin_unlock_irqrestore(&sport->port.lock, flags);
2163
2164 return HRTIMER_NORESTART;
2165}
2166
2167static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2168{
2169 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2170 unsigned long flags;
2171
2172 spin_lock_irqsave(&sport->port.lock, flags);
2173 if (sport->tx_state == WAIT_AFTER_SEND)
2174 imx_uart_stop_tx(&sport->port);
2175 spin_unlock_irqrestore(&sport->port.lock, flags);
2176
2177 return HRTIMER_NORESTART;
2178}
2179
2180/* Default RX DMA buffer configuration */
2181#define RX_DMA_PERIODS 16
2182#define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4)
2183
2184static int imx_uart_probe(struct platform_device *pdev)
2185{
2186 struct device_node *np = pdev->dev.of_node;
2187 struct imx_port *sport;
2188 void __iomem *base;
2189 u32 dma_buf_conf[2];
2190 int ret = 0;
2191 u32 ucr1;
2192 struct resource *res;
2193 int txirq, rxirq, rtsirq;
2194
2195 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2196 if (!sport)
2197 return -ENOMEM;
2198
2199 sport->devdata = of_device_get_match_data(&pdev->dev);
2200
2201 ret = of_alias_get_id(np, "serial");
2202 if (ret < 0) {
2203 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2204 return ret;
2205 }
2206 sport->port.line = ret;
2207
2208 if (of_get_property(np, "uart-has-rtscts", NULL) ||
2209 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
2210 sport->have_rtscts = 1;
2211
2212 if (of_get_property(np, "fsl,dte-mode", NULL))
2213 sport->dte_mode = 1;
2214
2215 if (of_get_property(np, "rts-gpios", NULL))
2216 sport->have_rtsgpio = 1;
2217
2218 if (of_get_property(np, "fsl,inverted-tx", NULL))
2219 sport->inverted_tx = 1;
2220
2221 if (of_get_property(np, "fsl,inverted-rx", NULL))
2222 sport->inverted_rx = 1;
2223
2224 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) {
2225 sport->rx_period_length = dma_buf_conf[0];
2226 sport->rx_periods = dma_buf_conf[1];
2227 } else {
2228 sport->rx_period_length = RX_DMA_PERIOD_LEN;
2229 sport->rx_periods = RX_DMA_PERIODS;
2230 }
2231
2232 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2233 dev_err(&pdev->dev, "serial%d out of range\n",
2234 sport->port.line);
2235 return -EINVAL;
2236 }
2237
2238 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2239 base = devm_ioremap_resource(&pdev->dev, res);
2240 if (IS_ERR(base))
2241 return PTR_ERR(base);
2242
2243 rxirq = platform_get_irq(pdev, 0);
2244 if (rxirq < 0)
2245 return rxirq;
2246 txirq = platform_get_irq_optional(pdev, 1);
2247 rtsirq = platform_get_irq_optional(pdev, 2);
2248
2249 sport->port.dev = &pdev->dev;
2250 sport->port.mapbase = res->start;
2251 sport->port.membase = base;
2252 sport->port.type = PORT_IMX;
2253 sport->port.iotype = UPIO_MEM;
2254 sport->port.irq = rxirq;
2255 sport->port.fifosize = 32;
2256 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2257 sport->port.ops = &imx_uart_pops;
2258 sport->port.rs485_config = imx_uart_rs485_config;
2259 sport->port.flags = UPF_BOOT_AUTOCONF;
2260 timer_setup(&sport->timer, imx_uart_timeout, 0);
2261
2262 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2263 if (IS_ERR(sport->gpios))
2264 return PTR_ERR(sport->gpios);
2265
2266 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2267 if (IS_ERR(sport->clk_ipg)) {
2268 ret = PTR_ERR(sport->clk_ipg);
2269 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2270 return ret;
2271 }
2272
2273 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2274 if (IS_ERR(sport->clk_per)) {
2275 ret = PTR_ERR(sport->clk_per);
2276 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2277 return ret;
2278 }
2279
2280 sport->port.uartclk = clk_get_rate(sport->clk_per);
2281
2282 /* For register access, we only need to enable the ipg clock. */
2283 ret = clk_prepare_enable(sport->clk_ipg);
2284 if (ret) {
2285 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2286 return ret;
2287 }
2288
2289 /* initialize shadow register values */
2290 sport->ucr1 = readl(sport->port.membase + UCR1);
2291 sport->ucr2 = readl(sport->port.membase + UCR2);
2292 sport->ucr3 = readl(sport->port.membase + UCR3);
2293 sport->ucr4 = readl(sport->port.membase + UCR4);
2294 sport->ufcr = readl(sport->port.membase + UFCR);
2295
2296 ret = uart_get_rs485_mode(&sport->port);
2297 if (ret) {
2298 clk_disable_unprepare(sport->clk_ipg);
2299 return ret;
2300 }
2301
2302 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2303 (!sport->have_rtscts && !sport->have_rtsgpio))
2304 dev_err(&pdev->dev, "no RTS control, disabling rs485\n");
2305
2306 /*
2307 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2308 * signal cannot be set low during transmission in case the
2309 * receiver is off (limitation of the i.MX UART IP).
2310 */
2311 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2312 sport->have_rtscts && !sport->have_rtsgpio &&
2313 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2314 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2315 dev_err(&pdev->dev,
2316 "low-active RTS not possible when receiver is off, enabling receiver\n");
2317
2318 imx_uart_rs485_config(&sport->port, &sport->port.rs485);
2319
2320 /* Disable interrupts before requesting them */
2321 ucr1 = imx_uart_readl(sport, UCR1);
2322 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2323 imx_uart_writel(sport, ucr1, UCR1);
2324
2325 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2326 /*
2327 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2328 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2329 * and DCD (when they are outputs) or enables the respective
2330 * irqs. So set this bit early, i.e. before requesting irqs.
2331 */
2332 u32 ufcr = imx_uart_readl(sport, UFCR);
2333 if (!(ufcr & UFCR_DCEDTE))
2334 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2335
2336 /*
2337 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2338 * enabled later because they cannot be cleared
2339 * (confirmed on i.MX25) which makes them unusable.
2340 */
2341 imx_uart_writel(sport,
2342 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2343 UCR3);
2344
2345 } else {
2346 u32 ucr3 = UCR3_DSR;
2347 u32 ufcr = imx_uart_readl(sport, UFCR);
2348 if (ufcr & UFCR_DCEDTE)
2349 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2350
2351 if (!imx_uart_is_imx1(sport))
2352 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2353 imx_uart_writel(sport, ucr3, UCR3);
2354 }
2355
2356 clk_disable_unprepare(sport->clk_ipg);
2357
2358 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2359 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2360 sport->trigger_start_tx.function = imx_trigger_start_tx;
2361 sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2362
2363 /*
2364 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2365 * chips only have one interrupt.
2366 */
2367 if (txirq > 0) {
2368 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2369 dev_name(&pdev->dev), sport);
2370 if (ret) {
2371 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2372 ret);
2373 return ret;
2374 }
2375
2376 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2377 dev_name(&pdev->dev), sport);
2378 if (ret) {
2379 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2380 ret);
2381 return ret;
2382 }
2383
2384 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2385 dev_name(&pdev->dev), sport);
2386 if (ret) {
2387 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2388 ret);
2389 return ret;
2390 }
2391 } else {
2392 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2393 dev_name(&pdev->dev), sport);
2394 if (ret) {
2395 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2396 return ret;
2397 }
2398 }
2399
2400 imx_uart_ports[sport->port.line] = sport;
2401
2402 platform_set_drvdata(pdev, sport);
2403
2404 return uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2405}
2406
2407static int imx_uart_remove(struct platform_device *pdev)
2408{
2409 struct imx_port *sport = platform_get_drvdata(pdev);
2410
2411 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2412}
2413
2414static void imx_uart_restore_context(struct imx_port *sport)
2415{
2416 unsigned long flags;
2417
2418 spin_lock_irqsave(&sport->port.lock, flags);
2419 if (!sport->context_saved) {
2420 spin_unlock_irqrestore(&sport->port.lock, flags);
2421 return;
2422 }
2423
2424 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2425 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2426 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2427 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2428 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2429 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2430 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2431 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2432 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2433 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2434 sport->context_saved = false;
2435 spin_unlock_irqrestore(&sport->port.lock, flags);
2436}
2437
2438static void imx_uart_save_context(struct imx_port *sport)
2439{
2440 unsigned long flags;
2441
2442 /* Save necessary regs */
2443 spin_lock_irqsave(&sport->port.lock, flags);
2444 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2445 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2446 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2447 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2448 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2449 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2450 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2451 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2452 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2453 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2454 sport->context_saved = true;
2455 spin_unlock_irqrestore(&sport->port.lock, flags);
2456}
2457
2458static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2459{
2460 u32 ucr3;
2461
2462 ucr3 = imx_uart_readl(sport, UCR3);
2463 if (on) {
2464 imx_uart_writel(sport, USR1_AWAKE, USR1);
2465 ucr3 |= UCR3_AWAKEN;
2466 } else {
2467 ucr3 &= ~UCR3_AWAKEN;
2468 }
2469 imx_uart_writel(sport, ucr3, UCR3);
2470
2471 if (sport->have_rtscts) {
2472 u32 ucr1 = imx_uart_readl(sport, UCR1);
2473 if (on)
2474 ucr1 |= UCR1_RTSDEN;
2475 else
2476 ucr1 &= ~UCR1_RTSDEN;
2477 imx_uart_writel(sport, ucr1, UCR1);
2478 }
2479}
2480
2481static int imx_uart_suspend_noirq(struct device *dev)
2482{
2483 struct imx_port *sport = dev_get_drvdata(dev);
2484
2485 imx_uart_save_context(sport);
2486
2487 clk_disable(sport->clk_ipg);
2488
2489 pinctrl_pm_select_sleep_state(dev);
2490
2491 return 0;
2492}
2493
2494static int imx_uart_resume_noirq(struct device *dev)
2495{
2496 struct imx_port *sport = dev_get_drvdata(dev);
2497 int ret;
2498
2499 pinctrl_pm_select_default_state(dev);
2500
2501 ret = clk_enable(sport->clk_ipg);
2502 if (ret)
2503 return ret;
2504
2505 imx_uart_restore_context(sport);
2506
2507 return 0;
2508}
2509
2510static int imx_uart_suspend(struct device *dev)
2511{
2512 struct imx_port *sport = dev_get_drvdata(dev);
2513 int ret;
2514
2515 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2516 disable_irq(sport->port.irq);
2517
2518 ret = clk_prepare_enable(sport->clk_ipg);
2519 if (ret)
2520 return ret;
2521
2522 /* enable wakeup from i.MX UART */
2523 imx_uart_enable_wakeup(sport, true);
2524
2525 return 0;
2526}
2527
2528static int imx_uart_resume(struct device *dev)
2529{
2530 struct imx_port *sport = dev_get_drvdata(dev);
2531
2532 /* disable wakeup from i.MX UART */
2533 imx_uart_enable_wakeup(sport, false);
2534
2535 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2536 enable_irq(sport->port.irq);
2537
2538 clk_disable_unprepare(sport->clk_ipg);
2539
2540 return 0;
2541}
2542
2543static int imx_uart_freeze(struct device *dev)
2544{
2545 struct imx_port *sport = dev_get_drvdata(dev);
2546
2547 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2548
2549 return clk_prepare_enable(sport->clk_ipg);
2550}
2551
2552static int imx_uart_thaw(struct device *dev)
2553{
2554 struct imx_port *sport = dev_get_drvdata(dev);
2555
2556 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2557
2558 clk_disable_unprepare(sport->clk_ipg);
2559
2560 return 0;
2561}
2562
2563static const struct dev_pm_ops imx_uart_pm_ops = {
2564 .suspend_noirq = imx_uart_suspend_noirq,
2565 .resume_noirq = imx_uart_resume_noirq,
2566 .freeze_noirq = imx_uart_suspend_noirq,
2567 .restore_noirq = imx_uart_resume_noirq,
2568 .suspend = imx_uart_suspend,
2569 .resume = imx_uart_resume,
2570 .freeze = imx_uart_freeze,
2571 .thaw = imx_uart_thaw,
2572 .restore = imx_uart_thaw,
2573};
2574
2575static struct platform_driver imx_uart_platform_driver = {
2576 .probe = imx_uart_probe,
2577 .remove = imx_uart_remove,
2578
2579 .driver = {
2580 .name = "imx-uart",
2581 .of_match_table = imx_uart_dt_ids,
2582 .pm = &imx_uart_pm_ops,
2583 },
2584};
2585
2586static int __init imx_uart_init(void)
2587{
2588 int ret = uart_register_driver(&imx_uart_uart_driver);
2589
2590 if (ret)
2591 return ret;
2592
2593 ret = platform_driver_register(&imx_uart_platform_driver);
2594 if (ret != 0)
2595 uart_unregister_driver(&imx_uart_uart_driver);
2596
2597 return ret;
2598}
2599
2600static void __exit imx_uart_exit(void)
2601{
2602 platform_driver_unregister(&imx_uart_platform_driver);
2603 uart_unregister_driver(&imx_uart_uart_driver);
2604}
2605
2606module_init(imx_uart_init);
2607module_exit(imx_uart_exit);
2608
2609MODULE_AUTHOR("Sascha Hauer");
2610MODULE_DESCRIPTION("IMX generic serial port driver");
2611MODULE_LICENSE("GPL");
2612MODULE_ALIAS("platform:imx-uart");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12#define SUPPORT_SYSRQ
13#endif
14
15#include <linux/module.h>
16#include <linux/ioport.h>
17#include <linux/init.h>
18#include <linux/console.h>
19#include <linux/sysrq.h>
20#include <linux/platform_device.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/serial_core.h>
24#include <linux/serial.h>
25#include <linux/clk.h>
26#include <linux/delay.h>
27#include <linux/rational.h>
28#include <linux/slab.h>
29#include <linux/of.h>
30#include <linux/of_device.h>
31#include <linux/io.h>
32#include <linux/dma-mapping.h>
33
34#include <asm/irq.h>
35#include <linux/platform_data/serial-imx.h>
36#include <linux/platform_data/dma-imx.h>
37
38#include "serial_mctrl_gpio.h"
39
40/* Register definitions */
41#define URXD0 0x0 /* Receiver Register */
42#define URTX0 0x40 /* Transmitter Register */
43#define UCR1 0x80 /* Control Register 1 */
44#define UCR2 0x84 /* Control Register 2 */
45#define UCR3 0x88 /* Control Register 3 */
46#define UCR4 0x8c /* Control Register 4 */
47#define UFCR 0x90 /* FIFO Control Register */
48#define USR1 0x94 /* Status Register 1 */
49#define USR2 0x98 /* Status Register 2 */
50#define UESC 0x9c /* Escape Character Register */
51#define UTIM 0xa0 /* Escape Timer Register */
52#define UBIR 0xa4 /* BRM Incremental Register */
53#define UBMR 0xa8 /* BRM Modulator Register */
54#define UBRC 0xac /* Baud Rate Count Register */
55#define IMX21_ONEMS 0xb0 /* One Millisecond register */
56#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
57#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
58
59/* UART Control Register Bit Fields.*/
60#define URXD_DUMMY_READ (1<<16)
61#define URXD_CHARRDY (1<<15)
62#define URXD_ERR (1<<14)
63#define URXD_OVRRUN (1<<13)
64#define URXD_FRMERR (1<<12)
65#define URXD_BRK (1<<11)
66#define URXD_PRERR (1<<10)
67#define URXD_RX_DATA (0xFF<<0)
68#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
69#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
70#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
71#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
72#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
73#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
74#define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
75#define UCR1_IREN (1<<7) /* Infrared interface enable */
76#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
77#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
78#define UCR1_SNDBRK (1<<4) /* Send break */
79#define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
80#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
81#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
82#define UCR1_DOZE (1<<1) /* Doze */
83#define UCR1_UARTEN (1<<0) /* UART enabled */
84#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
85#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
86#define UCR2_CTSC (1<<13) /* CTS pin control */
87#define UCR2_CTS (1<<12) /* Clear to send */
88#define UCR2_ESCEN (1<<11) /* Escape enable */
89#define UCR2_PREN (1<<8) /* Parity enable */
90#define UCR2_PROE (1<<7) /* Parity odd/even */
91#define UCR2_STPB (1<<6) /* Stop */
92#define UCR2_WS (1<<5) /* Word size */
93#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
94#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
95#define UCR2_TXEN (1<<2) /* Transmitter enabled */
96#define UCR2_RXEN (1<<1) /* Receiver enabled */
97#define UCR2_SRST (1<<0) /* SW reset */
98#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
99#define UCR3_PARERREN (1<<12) /* Parity enable */
100#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
101#define UCR3_DSR (1<<10) /* Data set ready */
102#define UCR3_DCD (1<<9) /* Data carrier detect */
103#define UCR3_RI (1<<8) /* Ring indicator */
104#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
105#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
106#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
107#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
108#define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
109#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
110#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
111#define UCR3_BPEN (1<<0) /* Preset registers enable */
112#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
113#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
114#define UCR4_INVR (1<<9) /* Inverted infrared reception */
115#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
116#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
117#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
118#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
119#define UCR4_IRSC (1<<5) /* IR special case */
120#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
121#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
122#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
123#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
124#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
125#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
126#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
127#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
128#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
129#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
130#define USR1_RTSS (1<<14) /* RTS pin status */
131#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
132#define USR1_RTSD (1<<12) /* RTS delta */
133#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
134#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
135#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
136#define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
137#define USR1_DTRD (1<<7) /* DTR Delta */
138#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
139#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
140#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
141#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
142#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
143#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
144#define USR2_IDLE (1<<12) /* Idle condition */
145#define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
146#define USR2_RIIN (1<<9) /* Ring Indicator Input */
147#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
148#define USR2_WAKE (1<<7) /* Wake */
149#define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
150#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
151#define USR2_TXDC (1<<3) /* Transmitter complete */
152#define USR2_BRCD (1<<2) /* Break condition */
153#define USR2_ORE (1<<1) /* Overrun error */
154#define USR2_RDR (1<<0) /* Recv data ready */
155#define UTS_FRCPERR (1<<13) /* Force parity error */
156#define UTS_LOOP (1<<12) /* Loop tx and rx */
157#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
158#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
159#define UTS_TXFULL (1<<4) /* TxFIFO full */
160#define UTS_RXFULL (1<<3) /* RxFIFO full */
161#define UTS_SOFTRST (1<<0) /* Software reset */
162
163/* We've been assigned a range on the "Low-density serial ports" major */
164#define SERIAL_IMX_MAJOR 207
165#define MINOR_START 16
166#define DEV_NAME "ttymxc"
167
168/*
169 * This determines how often we check the modem status signals
170 * for any change. They generally aren't connected to an IRQ
171 * so we have to poll them. We also check immediately before
172 * filling the TX fifo incase CTS has been dropped.
173 */
174#define MCTRL_TIMEOUT (250*HZ/1000)
175
176#define DRIVER_NAME "IMX-uart"
177
178#define UART_NR 8
179
180/* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
181enum imx_uart_type {
182 IMX1_UART,
183 IMX21_UART,
184 IMX53_UART,
185 IMX6Q_UART,
186};
187
188/* device type dependent stuff */
189struct imx_uart_data {
190 unsigned uts_reg;
191 enum imx_uart_type devtype;
192};
193
194struct imx_port {
195 struct uart_port port;
196 struct timer_list timer;
197 unsigned int old_status;
198 unsigned int have_rtscts:1;
199 unsigned int have_rtsgpio:1;
200 unsigned int dte_mode:1;
201 struct clk *clk_ipg;
202 struct clk *clk_per;
203 const struct imx_uart_data *devdata;
204
205 struct mctrl_gpios *gpios;
206
207 /* shadow registers */
208 unsigned int ucr1;
209 unsigned int ucr2;
210 unsigned int ucr3;
211 unsigned int ucr4;
212 unsigned int ufcr;
213
214 /* DMA fields */
215 unsigned int dma_is_enabled:1;
216 unsigned int dma_is_rxing:1;
217 unsigned int dma_is_txing:1;
218 struct dma_chan *dma_chan_rx, *dma_chan_tx;
219 struct scatterlist rx_sgl, tx_sgl[2];
220 void *rx_buf;
221 struct circ_buf rx_ring;
222 unsigned int rx_periods;
223 dma_cookie_t rx_cookie;
224 unsigned int tx_bytes;
225 unsigned int dma_tx_nents;
226 unsigned int saved_reg[10];
227 bool context_saved;
228};
229
230struct imx_port_ucrs {
231 unsigned int ucr1;
232 unsigned int ucr2;
233 unsigned int ucr3;
234};
235
236static struct imx_uart_data imx_uart_devdata[] = {
237 [IMX1_UART] = {
238 .uts_reg = IMX1_UTS,
239 .devtype = IMX1_UART,
240 },
241 [IMX21_UART] = {
242 .uts_reg = IMX21_UTS,
243 .devtype = IMX21_UART,
244 },
245 [IMX53_UART] = {
246 .uts_reg = IMX21_UTS,
247 .devtype = IMX53_UART,
248 },
249 [IMX6Q_UART] = {
250 .uts_reg = IMX21_UTS,
251 .devtype = IMX6Q_UART,
252 },
253};
254
255static const struct platform_device_id imx_uart_devtype[] = {
256 {
257 .name = "imx1-uart",
258 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
259 }, {
260 .name = "imx21-uart",
261 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
262 }, {
263 .name = "imx53-uart",
264 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART],
265 }, {
266 .name = "imx6q-uart",
267 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
268 }, {
269 /* sentinel */
270 }
271};
272MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
273
274static const struct of_device_id imx_uart_dt_ids[] = {
275 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
276 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
277 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
278 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
279 { /* sentinel */ }
280};
281MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
282
283static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
284{
285 switch (offset) {
286 case UCR1:
287 sport->ucr1 = val;
288 break;
289 case UCR2:
290 sport->ucr2 = val;
291 break;
292 case UCR3:
293 sport->ucr3 = val;
294 break;
295 case UCR4:
296 sport->ucr4 = val;
297 break;
298 case UFCR:
299 sport->ufcr = val;
300 break;
301 default:
302 break;
303 }
304 writel(val, sport->port.membase + offset);
305}
306
307static u32 imx_uart_readl(struct imx_port *sport, u32 offset)
308{
309 switch (offset) {
310 case UCR1:
311 return sport->ucr1;
312 break;
313 case UCR2:
314 /*
315 * UCR2_SRST is the only bit in the cached registers that might
316 * differ from the value that was last written. As it only
317 * clears after being set, reread conditionally.
318 */
319 if (!(sport->ucr2 & UCR2_SRST))
320 sport->ucr2 = readl(sport->port.membase + offset);
321 return sport->ucr2;
322 break;
323 case UCR3:
324 return sport->ucr3;
325 break;
326 case UCR4:
327 return sport->ucr4;
328 break;
329 case UFCR:
330 return sport->ufcr;
331 break;
332 default:
333 return readl(sport->port.membase + offset);
334 }
335}
336
337static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
338{
339 return sport->devdata->uts_reg;
340}
341
342static inline int imx_uart_is_imx1(struct imx_port *sport)
343{
344 return sport->devdata->devtype == IMX1_UART;
345}
346
347static inline int imx_uart_is_imx21(struct imx_port *sport)
348{
349 return sport->devdata->devtype == IMX21_UART;
350}
351
352static inline int imx_uart_is_imx53(struct imx_port *sport)
353{
354 return sport->devdata->devtype == IMX53_UART;
355}
356
357static inline int imx_uart_is_imx6q(struct imx_port *sport)
358{
359 return sport->devdata->devtype == IMX6Q_UART;
360}
361/*
362 * Save and restore functions for UCR1, UCR2 and UCR3 registers
363 */
364#if defined(CONFIG_SERIAL_IMX_CONSOLE)
365static void imx_uart_ucrs_save(struct imx_port *sport,
366 struct imx_port_ucrs *ucr)
367{
368 /* save control registers */
369 ucr->ucr1 = imx_uart_readl(sport, UCR1);
370 ucr->ucr2 = imx_uart_readl(sport, UCR2);
371 ucr->ucr3 = imx_uart_readl(sport, UCR3);
372}
373
374static void imx_uart_ucrs_restore(struct imx_port *sport,
375 struct imx_port_ucrs *ucr)
376{
377 /* restore control registers */
378 imx_uart_writel(sport, ucr->ucr1, UCR1);
379 imx_uart_writel(sport, ucr->ucr2, UCR2);
380 imx_uart_writel(sport, ucr->ucr3, UCR3);
381}
382#endif
383
384static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
385{
386 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
387
388 sport->port.mctrl |= TIOCM_RTS;
389 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
390}
391
392static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
393{
394 *ucr2 &= ~UCR2_CTSC;
395 *ucr2 |= UCR2_CTS;
396
397 sport->port.mctrl &= ~TIOCM_RTS;
398 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
399}
400
401static void imx_uart_rts_auto(struct imx_port *sport, u32 *ucr2)
402{
403 *ucr2 |= UCR2_CTSC;
404}
405
406/* called with port.lock taken and irqs off */
407static void imx_uart_start_rx(struct uart_port *port)
408{
409 struct imx_port *sport = (struct imx_port *)port;
410 unsigned int ucr1, ucr2;
411
412 ucr1 = imx_uart_readl(sport, UCR1);
413 ucr2 = imx_uart_readl(sport, UCR2);
414
415 ucr2 |= UCR2_RXEN;
416
417 if (sport->dma_is_enabled) {
418 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
419 } else {
420 ucr1 |= UCR1_RRDYEN;
421 ucr2 |= UCR2_ATEN;
422 }
423
424 /* Write UCR2 first as it includes RXEN */
425 imx_uart_writel(sport, ucr2, UCR2);
426 imx_uart_writel(sport, ucr1, UCR1);
427}
428
429/* called with port.lock taken and irqs off */
430static void imx_uart_stop_tx(struct uart_port *port)
431{
432 struct imx_port *sport = (struct imx_port *)port;
433 u32 ucr1;
434
435 /*
436 * We are maybe in the SMP context, so if the DMA TX thread is running
437 * on other cpu, we have to wait for it to finish.
438 */
439 if (sport->dma_is_txing)
440 return;
441
442 ucr1 = imx_uart_readl(sport, UCR1);
443 imx_uart_writel(sport, ucr1 & ~UCR1_TXMPTYEN, UCR1);
444
445 /* in rs485 mode disable transmitter if shifter is empty */
446 if (port->rs485.flags & SER_RS485_ENABLED &&
447 imx_uart_readl(sport, USR2) & USR2_TXDC) {
448 u32 ucr2 = imx_uart_readl(sport, UCR2), ucr4;
449 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
450 imx_uart_rts_active(sport, &ucr2);
451 else
452 imx_uart_rts_inactive(sport, &ucr2);
453 imx_uart_writel(sport, ucr2, UCR2);
454
455 imx_uart_start_rx(port);
456
457 ucr4 = imx_uart_readl(sport, UCR4);
458 ucr4 &= ~UCR4_TCEN;
459 imx_uart_writel(sport, ucr4, UCR4);
460 }
461}
462
463/* called with port.lock taken and irqs off */
464static void imx_uart_stop_rx(struct uart_port *port)
465{
466 struct imx_port *sport = (struct imx_port *)port;
467 u32 ucr1, ucr2;
468
469 ucr1 = imx_uart_readl(sport, UCR1);
470 ucr2 = imx_uart_readl(sport, UCR2);
471
472 if (sport->dma_is_enabled) {
473 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
474 } else {
475 ucr1 &= ~UCR1_RRDYEN;
476 ucr2 &= ~UCR2_ATEN;
477 }
478 imx_uart_writel(sport, ucr1, UCR1);
479
480 ucr2 &= ~UCR2_RXEN;
481 imx_uart_writel(sport, ucr2, UCR2);
482}
483
484/* called with port.lock taken and irqs off */
485static void imx_uart_enable_ms(struct uart_port *port)
486{
487 struct imx_port *sport = (struct imx_port *)port;
488
489 mod_timer(&sport->timer, jiffies);
490
491 mctrl_gpio_enable_ms(sport->gpios);
492}
493
494static void imx_uart_dma_tx(struct imx_port *sport);
495
496/* called with port.lock taken and irqs off */
497static inline void imx_uart_transmit_buffer(struct imx_port *sport)
498{
499 struct circ_buf *xmit = &sport->port.state->xmit;
500
501 if (sport->port.x_char) {
502 /* Send next char */
503 imx_uart_writel(sport, sport->port.x_char, URTX0);
504 sport->port.icount.tx++;
505 sport->port.x_char = 0;
506 return;
507 }
508
509 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
510 imx_uart_stop_tx(&sport->port);
511 return;
512 }
513
514 if (sport->dma_is_enabled) {
515 u32 ucr1;
516 /*
517 * We've just sent a X-char Ensure the TX DMA is enabled
518 * and the TX IRQ is disabled.
519 **/
520 ucr1 = imx_uart_readl(sport, UCR1);
521 ucr1 &= ~UCR1_TXMPTYEN;
522 if (sport->dma_is_txing) {
523 ucr1 |= UCR1_TXDMAEN;
524 imx_uart_writel(sport, ucr1, UCR1);
525 } else {
526 imx_uart_writel(sport, ucr1, UCR1);
527 imx_uart_dma_tx(sport);
528 }
529
530 return;
531 }
532
533 while (!uart_circ_empty(xmit) &&
534 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
535 /* send xmit->buf[xmit->tail]
536 * out the port here */
537 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
538 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
539 sport->port.icount.tx++;
540 }
541
542 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
543 uart_write_wakeup(&sport->port);
544
545 if (uart_circ_empty(xmit))
546 imx_uart_stop_tx(&sport->port);
547}
548
549static void imx_uart_dma_tx_callback(void *data)
550{
551 struct imx_port *sport = data;
552 struct scatterlist *sgl = &sport->tx_sgl[0];
553 struct circ_buf *xmit = &sport->port.state->xmit;
554 unsigned long flags;
555 u32 ucr1;
556
557 spin_lock_irqsave(&sport->port.lock, flags);
558
559 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
560
561 ucr1 = imx_uart_readl(sport, UCR1);
562 ucr1 &= ~UCR1_TXDMAEN;
563 imx_uart_writel(sport, ucr1, UCR1);
564
565 /* update the stat */
566 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
567 sport->port.icount.tx += sport->tx_bytes;
568
569 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
570
571 sport->dma_is_txing = 0;
572
573 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
574 uart_write_wakeup(&sport->port);
575
576 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
577 imx_uart_dma_tx(sport);
578 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
579 u32 ucr4 = imx_uart_readl(sport, UCR4);
580 ucr4 |= UCR4_TCEN;
581 imx_uart_writel(sport, ucr4, UCR4);
582 }
583
584 spin_unlock_irqrestore(&sport->port.lock, flags);
585}
586
587/* called with port.lock taken and irqs off */
588static void imx_uart_dma_tx(struct imx_port *sport)
589{
590 struct circ_buf *xmit = &sport->port.state->xmit;
591 struct scatterlist *sgl = sport->tx_sgl;
592 struct dma_async_tx_descriptor *desc;
593 struct dma_chan *chan = sport->dma_chan_tx;
594 struct device *dev = sport->port.dev;
595 u32 ucr1, ucr4;
596 int ret;
597
598 if (sport->dma_is_txing)
599 return;
600
601 ucr4 = imx_uart_readl(sport, UCR4);
602 ucr4 &= ~UCR4_TCEN;
603 imx_uart_writel(sport, ucr4, UCR4);
604
605 sport->tx_bytes = uart_circ_chars_pending(xmit);
606
607 if (xmit->tail < xmit->head) {
608 sport->dma_tx_nents = 1;
609 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
610 } else {
611 sport->dma_tx_nents = 2;
612 sg_init_table(sgl, 2);
613 sg_set_buf(sgl, xmit->buf + xmit->tail,
614 UART_XMIT_SIZE - xmit->tail);
615 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
616 }
617
618 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
619 if (ret == 0) {
620 dev_err(dev, "DMA mapping error for TX.\n");
621 return;
622 }
623 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
624 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
625 if (!desc) {
626 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
627 DMA_TO_DEVICE);
628 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
629 return;
630 }
631 desc->callback = imx_uart_dma_tx_callback;
632 desc->callback_param = sport;
633
634 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
635 uart_circ_chars_pending(xmit));
636
637 ucr1 = imx_uart_readl(sport, UCR1);
638 ucr1 |= UCR1_TXDMAEN;
639 imx_uart_writel(sport, ucr1, UCR1);
640
641 /* fire it */
642 sport->dma_is_txing = 1;
643 dmaengine_submit(desc);
644 dma_async_issue_pending(chan);
645 return;
646}
647
648/* called with port.lock taken and irqs off */
649static void imx_uart_start_tx(struct uart_port *port)
650{
651 struct imx_port *sport = (struct imx_port *)port;
652 u32 ucr1;
653
654 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
655 return;
656
657 if (port->rs485.flags & SER_RS485_ENABLED) {
658 u32 ucr2;
659
660 ucr2 = imx_uart_readl(sport, UCR2);
661 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
662 imx_uart_rts_active(sport, &ucr2);
663 else
664 imx_uart_rts_inactive(sport, &ucr2);
665 imx_uart_writel(sport, ucr2, UCR2);
666
667 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
668 imx_uart_stop_rx(port);
669
670 /*
671 * Enable transmitter and shifter empty irq only if DMA is off.
672 * In the DMA case this is done in the tx-callback.
673 */
674 if (!sport->dma_is_enabled) {
675 u32 ucr4 = imx_uart_readl(sport, UCR4);
676 ucr4 |= UCR4_TCEN;
677 imx_uart_writel(sport, ucr4, UCR4);
678 }
679 }
680
681 if (!sport->dma_is_enabled) {
682 ucr1 = imx_uart_readl(sport, UCR1);
683 imx_uart_writel(sport, ucr1 | UCR1_TXMPTYEN, UCR1);
684 }
685
686 if (sport->dma_is_enabled) {
687 if (sport->port.x_char) {
688 /* We have X-char to send, so enable TX IRQ and
689 * disable TX DMA to let TX interrupt to send X-char */
690 ucr1 = imx_uart_readl(sport, UCR1);
691 ucr1 &= ~UCR1_TXDMAEN;
692 ucr1 |= UCR1_TXMPTYEN;
693 imx_uart_writel(sport, ucr1, UCR1);
694 return;
695 }
696
697 if (!uart_circ_empty(&port->state->xmit) &&
698 !uart_tx_stopped(port))
699 imx_uart_dma_tx(sport);
700 return;
701 }
702}
703
704static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
705{
706 struct imx_port *sport = dev_id;
707 u32 usr1;
708 unsigned long flags;
709
710 spin_lock_irqsave(&sport->port.lock, flags);
711
712 imx_uart_writel(sport, USR1_RTSD, USR1);
713 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
714 uart_handle_cts_change(&sport->port, !!usr1);
715 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
716
717 spin_unlock_irqrestore(&sport->port.lock, flags);
718 return IRQ_HANDLED;
719}
720
721static irqreturn_t imx_uart_txint(int irq, void *dev_id)
722{
723 struct imx_port *sport = dev_id;
724 unsigned long flags;
725
726 spin_lock_irqsave(&sport->port.lock, flags);
727 imx_uart_transmit_buffer(sport);
728 spin_unlock_irqrestore(&sport->port.lock, flags);
729 return IRQ_HANDLED;
730}
731
732static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
733{
734 struct imx_port *sport = dev_id;
735 unsigned int rx, flg, ignored = 0;
736 struct tty_port *port = &sport->port.state->port;
737 unsigned long flags;
738
739 spin_lock_irqsave(&sport->port.lock, flags);
740
741 while (imx_uart_readl(sport, USR2) & USR2_RDR) {
742 u32 usr2;
743
744 flg = TTY_NORMAL;
745 sport->port.icount.rx++;
746
747 rx = imx_uart_readl(sport, URXD0);
748
749 usr2 = imx_uart_readl(sport, USR2);
750 if (usr2 & USR2_BRCD) {
751 imx_uart_writel(sport, USR2_BRCD, USR2);
752 if (uart_handle_break(&sport->port))
753 continue;
754 }
755
756 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
757 continue;
758
759 if (unlikely(rx & URXD_ERR)) {
760 if (rx & URXD_BRK)
761 sport->port.icount.brk++;
762 else if (rx & URXD_PRERR)
763 sport->port.icount.parity++;
764 else if (rx & URXD_FRMERR)
765 sport->port.icount.frame++;
766 if (rx & URXD_OVRRUN)
767 sport->port.icount.overrun++;
768
769 if (rx & sport->port.ignore_status_mask) {
770 if (++ignored > 100)
771 goto out;
772 continue;
773 }
774
775 rx &= (sport->port.read_status_mask | 0xFF);
776
777 if (rx & URXD_BRK)
778 flg = TTY_BREAK;
779 else if (rx & URXD_PRERR)
780 flg = TTY_PARITY;
781 else if (rx & URXD_FRMERR)
782 flg = TTY_FRAME;
783 if (rx & URXD_OVRRUN)
784 flg = TTY_OVERRUN;
785
786#ifdef SUPPORT_SYSRQ
787 sport->port.sysrq = 0;
788#endif
789 }
790
791 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
792 goto out;
793
794 if (tty_insert_flip_char(port, rx, flg) == 0)
795 sport->port.icount.buf_overrun++;
796 }
797
798out:
799 spin_unlock_irqrestore(&sport->port.lock, flags);
800 tty_flip_buffer_push(port);
801 return IRQ_HANDLED;
802}
803
804static void imx_uart_clear_rx_errors(struct imx_port *sport);
805
806/*
807 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
808 */
809static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
810{
811 unsigned int tmp = TIOCM_DSR;
812 unsigned usr1 = imx_uart_readl(sport, USR1);
813 unsigned usr2 = imx_uart_readl(sport, USR2);
814
815 if (usr1 & USR1_RTSS)
816 tmp |= TIOCM_CTS;
817
818 /* in DCE mode DCDIN is always 0 */
819 if (!(usr2 & USR2_DCDIN))
820 tmp |= TIOCM_CAR;
821
822 if (sport->dte_mode)
823 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
824 tmp |= TIOCM_RI;
825
826 return tmp;
827}
828
829/*
830 * Handle any change of modem status signal since we were last called.
831 */
832static void imx_uart_mctrl_check(struct imx_port *sport)
833{
834 unsigned int status, changed;
835
836 status = imx_uart_get_hwmctrl(sport);
837 changed = status ^ sport->old_status;
838
839 if (changed == 0)
840 return;
841
842 sport->old_status = status;
843
844 if (changed & TIOCM_RI && status & TIOCM_RI)
845 sport->port.icount.rng++;
846 if (changed & TIOCM_DSR)
847 sport->port.icount.dsr++;
848 if (changed & TIOCM_CAR)
849 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
850 if (changed & TIOCM_CTS)
851 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
852
853 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
854}
855
856static irqreturn_t imx_uart_int(int irq, void *dev_id)
857{
858 struct imx_port *sport = dev_id;
859 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
860 irqreturn_t ret = IRQ_NONE;
861
862 usr1 = imx_uart_readl(sport, USR1);
863 usr2 = imx_uart_readl(sport, USR2);
864 ucr1 = imx_uart_readl(sport, UCR1);
865 ucr2 = imx_uart_readl(sport, UCR2);
866 ucr3 = imx_uart_readl(sport, UCR3);
867 ucr4 = imx_uart_readl(sport, UCR4);
868
869 /*
870 * Even if a condition is true that can trigger an irq only handle it if
871 * the respective irq source is enabled. This prevents some undesired
872 * actions, for example if a character that sits in the RX FIFO and that
873 * should be fetched via DMA is tried to be fetched using PIO. Or the
874 * receiver is currently off and so reading from URXD0 results in an
875 * exception. So just mask the (raw) status bits for disabled irqs.
876 */
877 if ((ucr1 & UCR1_RRDYEN) == 0)
878 usr1 &= ~USR1_RRDY;
879 if ((ucr2 & UCR2_ATEN) == 0)
880 usr1 &= ~USR1_AGTIM;
881 if ((ucr1 & UCR1_TXMPTYEN) == 0)
882 usr1 &= ~USR1_TRDY;
883 if ((ucr4 & UCR4_TCEN) == 0)
884 usr2 &= ~USR2_TXDC;
885 if ((ucr3 & UCR3_DTRDEN) == 0)
886 usr1 &= ~USR1_DTRD;
887 if ((ucr1 & UCR1_RTSDEN) == 0)
888 usr1 &= ~USR1_RTSD;
889 if ((ucr3 & UCR3_AWAKEN) == 0)
890 usr1 &= ~USR1_AWAKE;
891 if ((ucr4 & UCR4_OREN) == 0)
892 usr2 &= ~USR2_ORE;
893
894 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
895 imx_uart_rxint(irq, dev_id);
896 ret = IRQ_HANDLED;
897 }
898
899 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
900 imx_uart_txint(irq, dev_id);
901 ret = IRQ_HANDLED;
902 }
903
904 if (usr1 & USR1_DTRD) {
905 unsigned long flags;
906
907 imx_uart_writel(sport, USR1_DTRD, USR1);
908
909 spin_lock_irqsave(&sport->port.lock, flags);
910 imx_uart_mctrl_check(sport);
911 spin_unlock_irqrestore(&sport->port.lock, flags);
912
913 ret = IRQ_HANDLED;
914 }
915
916 if (usr1 & USR1_RTSD) {
917 imx_uart_rtsint(irq, dev_id);
918 ret = IRQ_HANDLED;
919 }
920
921 if (usr1 & USR1_AWAKE) {
922 imx_uart_writel(sport, USR1_AWAKE, USR1);
923 ret = IRQ_HANDLED;
924 }
925
926 if (usr2 & USR2_ORE) {
927 sport->port.icount.overrun++;
928 imx_uart_writel(sport, USR2_ORE, USR2);
929 ret = IRQ_HANDLED;
930 }
931
932 return ret;
933}
934
935/*
936 * Return TIOCSER_TEMT when transmitter is not busy.
937 */
938static unsigned int imx_uart_tx_empty(struct uart_port *port)
939{
940 struct imx_port *sport = (struct imx_port *)port;
941 unsigned int ret;
942
943 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
944
945 /* If the TX DMA is working, return 0. */
946 if (sport->dma_is_txing)
947 ret = 0;
948
949 return ret;
950}
951
952/* called with port.lock taken and irqs off */
953static unsigned int imx_uart_get_mctrl(struct uart_port *port)
954{
955 struct imx_port *sport = (struct imx_port *)port;
956 unsigned int ret = imx_uart_get_hwmctrl(sport);
957
958 mctrl_gpio_get(sport->gpios, &ret);
959
960 return ret;
961}
962
963/* called with port.lock taken and irqs off */
964static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
965{
966 struct imx_port *sport = (struct imx_port *)port;
967 u32 ucr3, uts;
968
969 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
970 u32 ucr2;
971
972 ucr2 = imx_uart_readl(sport, UCR2);
973 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
974 if (mctrl & TIOCM_RTS)
975 ucr2 |= UCR2_CTS | UCR2_CTSC;
976 imx_uart_writel(sport, ucr2, UCR2);
977 }
978
979 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
980 if (!(mctrl & TIOCM_DTR))
981 ucr3 |= UCR3_DSR;
982 imx_uart_writel(sport, ucr3, UCR3);
983
984 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
985 if (mctrl & TIOCM_LOOP)
986 uts |= UTS_LOOP;
987 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
988
989 mctrl_gpio_set(sport->gpios, mctrl);
990}
991
992/*
993 * Interrupts always disabled.
994 */
995static void imx_uart_break_ctl(struct uart_port *port, int break_state)
996{
997 struct imx_port *sport = (struct imx_port *)port;
998 unsigned long flags;
999 u32 ucr1;
1000
1001 spin_lock_irqsave(&sport->port.lock, flags);
1002
1003 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1004
1005 if (break_state != 0)
1006 ucr1 |= UCR1_SNDBRK;
1007
1008 imx_uart_writel(sport, ucr1, UCR1);
1009
1010 spin_unlock_irqrestore(&sport->port.lock, flags);
1011}
1012
1013/*
1014 * This is our per-port timeout handler, for checking the
1015 * modem status signals.
1016 */
1017static void imx_uart_timeout(struct timer_list *t)
1018{
1019 struct imx_port *sport = from_timer(sport, t, timer);
1020 unsigned long flags;
1021
1022 if (sport->port.state) {
1023 spin_lock_irqsave(&sport->port.lock, flags);
1024 imx_uart_mctrl_check(sport);
1025 spin_unlock_irqrestore(&sport->port.lock, flags);
1026
1027 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1028 }
1029}
1030
1031#define RX_BUF_SIZE (PAGE_SIZE)
1032
1033/*
1034 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1035 * [1] the RX DMA buffer is full.
1036 * [2] the aging timer expires
1037 *
1038 * Condition [2] is triggered when a character has been sitting in the FIFO
1039 * for at least 8 byte durations.
1040 */
1041static void imx_uart_dma_rx_callback(void *data)
1042{
1043 struct imx_port *sport = data;
1044 struct dma_chan *chan = sport->dma_chan_rx;
1045 struct scatterlist *sgl = &sport->rx_sgl;
1046 struct tty_port *port = &sport->port.state->port;
1047 struct dma_tx_state state;
1048 struct circ_buf *rx_ring = &sport->rx_ring;
1049 enum dma_status status;
1050 unsigned int w_bytes = 0;
1051 unsigned int r_bytes;
1052 unsigned int bd_size;
1053
1054 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
1055
1056 if (status == DMA_ERROR) {
1057 imx_uart_clear_rx_errors(sport);
1058 return;
1059 }
1060
1061 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1062
1063 /*
1064 * The state-residue variable represents the empty space
1065 * relative to the entire buffer. Taking this in consideration
1066 * the head is always calculated base on the buffer total
1067 * length - DMA transaction residue. The UART script from the
1068 * SDMA firmware will jump to the next buffer descriptor,
1069 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1070 * Taking this in consideration the tail is always at the
1071 * beginning of the buffer descriptor that contains the head.
1072 */
1073
1074 /* Calculate the head */
1075 rx_ring->head = sg_dma_len(sgl) - state.residue;
1076
1077 /* Calculate the tail. */
1078 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1079 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1080
1081 if (rx_ring->head <= sg_dma_len(sgl) &&
1082 rx_ring->head > rx_ring->tail) {
1083
1084 /* Move data from tail to head */
1085 r_bytes = rx_ring->head - rx_ring->tail;
1086
1087 /* CPU claims ownership of RX DMA buffer */
1088 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1089 DMA_FROM_DEVICE);
1090
1091 w_bytes = tty_insert_flip_string(port,
1092 sport->rx_buf + rx_ring->tail, r_bytes);
1093
1094 /* UART retrieves ownership of RX DMA buffer */
1095 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1096 DMA_FROM_DEVICE);
1097
1098 if (w_bytes != r_bytes)
1099 sport->port.icount.buf_overrun++;
1100
1101 sport->port.icount.rx += w_bytes;
1102 } else {
1103 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1104 WARN_ON(rx_ring->head <= rx_ring->tail);
1105 }
1106 }
1107
1108 if (w_bytes) {
1109 tty_flip_buffer_push(port);
1110 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1111 }
1112}
1113
1114/* RX DMA buffer periods */
1115#define RX_DMA_PERIODS 4
1116
1117static int imx_uart_start_rx_dma(struct imx_port *sport)
1118{
1119 struct scatterlist *sgl = &sport->rx_sgl;
1120 struct dma_chan *chan = sport->dma_chan_rx;
1121 struct device *dev = sport->port.dev;
1122 struct dma_async_tx_descriptor *desc;
1123 int ret;
1124
1125 sport->rx_ring.head = 0;
1126 sport->rx_ring.tail = 0;
1127 sport->rx_periods = RX_DMA_PERIODS;
1128
1129 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
1130 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1131 if (ret == 0) {
1132 dev_err(dev, "DMA mapping error for RX.\n");
1133 return -EINVAL;
1134 }
1135
1136 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1137 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1138 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1139
1140 if (!desc) {
1141 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1142 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1143 return -EINVAL;
1144 }
1145 desc->callback = imx_uart_dma_rx_callback;
1146 desc->callback_param = sport;
1147
1148 dev_dbg(dev, "RX: prepare for the DMA.\n");
1149 sport->dma_is_rxing = 1;
1150 sport->rx_cookie = dmaengine_submit(desc);
1151 dma_async_issue_pending(chan);
1152 return 0;
1153}
1154
1155static void imx_uart_clear_rx_errors(struct imx_port *sport)
1156{
1157 struct tty_port *port = &sport->port.state->port;
1158 u32 usr1, usr2;
1159
1160 usr1 = imx_uart_readl(sport, USR1);
1161 usr2 = imx_uart_readl(sport, USR2);
1162
1163 if (usr2 & USR2_BRCD) {
1164 sport->port.icount.brk++;
1165 imx_uart_writel(sport, USR2_BRCD, USR2);
1166 uart_handle_break(&sport->port);
1167 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1168 sport->port.icount.buf_overrun++;
1169 tty_flip_buffer_push(port);
1170 } else {
1171 dev_err(sport->port.dev, "DMA transaction error.\n");
1172 if (usr1 & USR1_FRAMERR) {
1173 sport->port.icount.frame++;
1174 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1175 } else if (usr1 & USR1_PARITYERR) {
1176 sport->port.icount.parity++;
1177 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1178 }
1179 }
1180
1181 if (usr2 & USR2_ORE) {
1182 sport->port.icount.overrun++;
1183 imx_uart_writel(sport, USR2_ORE, USR2);
1184 }
1185
1186}
1187
1188#define TXTL_DEFAULT 2 /* reset default */
1189#define RXTL_DEFAULT 1 /* reset default */
1190#define TXTL_DMA 8 /* DMA burst setting */
1191#define RXTL_DMA 9 /* DMA burst setting */
1192
1193static void imx_uart_setup_ufcr(struct imx_port *sport,
1194 unsigned char txwl, unsigned char rxwl)
1195{
1196 unsigned int val;
1197
1198 /* set receiver / transmitter trigger level */
1199 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1200 val |= txwl << UFCR_TXTL_SHF | rxwl;
1201 imx_uart_writel(sport, val, UFCR);
1202}
1203
1204static void imx_uart_dma_exit(struct imx_port *sport)
1205{
1206 if (sport->dma_chan_rx) {
1207 dmaengine_terminate_sync(sport->dma_chan_rx);
1208 dma_release_channel(sport->dma_chan_rx);
1209 sport->dma_chan_rx = NULL;
1210 sport->rx_cookie = -EINVAL;
1211 kfree(sport->rx_buf);
1212 sport->rx_buf = NULL;
1213 }
1214
1215 if (sport->dma_chan_tx) {
1216 dmaengine_terminate_sync(sport->dma_chan_tx);
1217 dma_release_channel(sport->dma_chan_tx);
1218 sport->dma_chan_tx = NULL;
1219 }
1220}
1221
1222static int imx_uart_dma_init(struct imx_port *sport)
1223{
1224 struct dma_slave_config slave_config = {};
1225 struct device *dev = sport->port.dev;
1226 int ret;
1227
1228 /* Prepare for RX : */
1229 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1230 if (!sport->dma_chan_rx) {
1231 dev_dbg(dev, "cannot get the DMA channel.\n");
1232 ret = -EINVAL;
1233 goto err;
1234 }
1235
1236 slave_config.direction = DMA_DEV_TO_MEM;
1237 slave_config.src_addr = sport->port.mapbase + URXD0;
1238 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1239 /* one byte less than the watermark level to enable the aging timer */
1240 slave_config.src_maxburst = RXTL_DMA - 1;
1241 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1242 if (ret) {
1243 dev_err(dev, "error in RX dma configuration.\n");
1244 goto err;
1245 }
1246
1247 sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL);
1248 if (!sport->rx_buf) {
1249 ret = -ENOMEM;
1250 goto err;
1251 }
1252 sport->rx_ring.buf = sport->rx_buf;
1253
1254 /* Prepare for TX : */
1255 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1256 if (!sport->dma_chan_tx) {
1257 dev_err(dev, "cannot get the TX DMA channel!\n");
1258 ret = -EINVAL;
1259 goto err;
1260 }
1261
1262 slave_config.direction = DMA_MEM_TO_DEV;
1263 slave_config.dst_addr = sport->port.mapbase + URTX0;
1264 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1265 slave_config.dst_maxburst = TXTL_DMA;
1266 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1267 if (ret) {
1268 dev_err(dev, "error in TX dma configuration.");
1269 goto err;
1270 }
1271
1272 return 0;
1273err:
1274 imx_uart_dma_exit(sport);
1275 return ret;
1276}
1277
1278static void imx_uart_enable_dma(struct imx_port *sport)
1279{
1280 u32 ucr1;
1281
1282 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1283
1284 /* set UCR1 */
1285 ucr1 = imx_uart_readl(sport, UCR1);
1286 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1287 imx_uart_writel(sport, ucr1, UCR1);
1288
1289 sport->dma_is_enabled = 1;
1290}
1291
1292static void imx_uart_disable_dma(struct imx_port *sport)
1293{
1294 u32 ucr1, ucr2;
1295
1296 /* clear UCR1 */
1297 ucr1 = imx_uart_readl(sport, UCR1);
1298 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1299 imx_uart_writel(sport, ucr1, UCR1);
1300
1301 /* clear UCR2 */
1302 ucr2 = imx_uart_readl(sport, UCR2);
1303 ucr2 &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN);
1304 imx_uart_writel(sport, ucr2, UCR2);
1305
1306 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1307
1308 sport->dma_is_enabled = 0;
1309}
1310
1311/* half the RX buffer size */
1312#define CTSTL 16
1313
1314static int imx_uart_startup(struct uart_port *port)
1315{
1316 struct imx_port *sport = (struct imx_port *)port;
1317 int retval, i;
1318 unsigned long flags;
1319 int dma_is_inited = 0;
1320 u32 ucr1, ucr2, ucr4;
1321
1322 retval = clk_prepare_enable(sport->clk_per);
1323 if (retval)
1324 return retval;
1325 retval = clk_prepare_enable(sport->clk_ipg);
1326 if (retval) {
1327 clk_disable_unprepare(sport->clk_per);
1328 return retval;
1329 }
1330
1331 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1332
1333 /* disable the DREN bit (Data Ready interrupt enable) before
1334 * requesting IRQs
1335 */
1336 ucr4 = imx_uart_readl(sport, UCR4);
1337
1338 /* set the trigger level for CTS */
1339 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1340 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1341
1342 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1343
1344 /* Can we enable the DMA support? */
1345 if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1346 dma_is_inited = 1;
1347
1348 spin_lock_irqsave(&sport->port.lock, flags);
1349 /* Reset fifo's and state machines */
1350 i = 100;
1351
1352 ucr2 = imx_uart_readl(sport, UCR2);
1353 ucr2 &= ~UCR2_SRST;
1354 imx_uart_writel(sport, ucr2, UCR2);
1355
1356 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1357 udelay(1);
1358
1359 /*
1360 * Finally, clear and enable interrupts
1361 */
1362 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1363 imx_uart_writel(sport, USR2_ORE, USR2);
1364
1365 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1366 ucr1 |= UCR1_UARTEN;
1367 if (sport->have_rtscts)
1368 ucr1 |= UCR1_RTSDEN;
1369
1370 imx_uart_writel(sport, ucr1, UCR1);
1371
1372 ucr4 = imx_uart_readl(sport, UCR4) & ~UCR4_OREN;
1373 if (!sport->dma_is_enabled)
1374 ucr4 |= UCR4_OREN;
1375 imx_uart_writel(sport, ucr4, UCR4);
1376
1377 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1378 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1379 if (!sport->have_rtscts)
1380 ucr2 |= UCR2_IRTS;
1381 /*
1382 * make sure the edge sensitive RTS-irq is disabled,
1383 * we're using RTSD instead.
1384 */
1385 if (!imx_uart_is_imx1(sport))
1386 ucr2 &= ~UCR2_RTSEN;
1387 imx_uart_writel(sport, ucr2, UCR2);
1388
1389 if (!imx_uart_is_imx1(sport)) {
1390 u32 ucr3;
1391
1392 ucr3 = imx_uart_readl(sport, UCR3);
1393
1394 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1395
1396 if (sport->dte_mode)
1397 /* disable broken interrupts */
1398 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1399
1400 imx_uart_writel(sport, ucr3, UCR3);
1401 }
1402
1403 /*
1404 * Enable modem status interrupts
1405 */
1406 imx_uart_enable_ms(&sport->port);
1407
1408 if (dma_is_inited) {
1409 imx_uart_enable_dma(sport);
1410 imx_uart_start_rx_dma(sport);
1411 } else {
1412 ucr1 = imx_uart_readl(sport, UCR1);
1413 ucr1 |= UCR1_RRDYEN;
1414 imx_uart_writel(sport, ucr1, UCR1);
1415
1416 ucr2 = imx_uart_readl(sport, UCR2);
1417 ucr2 |= UCR2_ATEN;
1418 imx_uart_writel(sport, ucr2, UCR2);
1419 }
1420
1421 spin_unlock_irqrestore(&sport->port.lock, flags);
1422
1423 return 0;
1424}
1425
1426static void imx_uart_shutdown(struct uart_port *port)
1427{
1428 struct imx_port *sport = (struct imx_port *)port;
1429 unsigned long flags;
1430 u32 ucr1, ucr2;
1431
1432 if (sport->dma_is_enabled) {
1433 sport->dma_is_rxing = 0;
1434 sport->dma_is_txing = 0;
1435 dmaengine_terminate_sync(sport->dma_chan_tx);
1436 dmaengine_terminate_sync(sport->dma_chan_rx);
1437
1438 spin_lock_irqsave(&sport->port.lock, flags);
1439 imx_uart_stop_tx(port);
1440 imx_uart_stop_rx(port);
1441 imx_uart_disable_dma(sport);
1442 spin_unlock_irqrestore(&sport->port.lock, flags);
1443 imx_uart_dma_exit(sport);
1444 }
1445
1446 mctrl_gpio_disable_ms(sport->gpios);
1447
1448 spin_lock_irqsave(&sport->port.lock, flags);
1449 ucr2 = imx_uart_readl(sport, UCR2);
1450 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1451 imx_uart_writel(sport, ucr2, UCR2);
1452 spin_unlock_irqrestore(&sport->port.lock, flags);
1453
1454 /*
1455 * Stop our timer.
1456 */
1457 del_timer_sync(&sport->timer);
1458
1459 /*
1460 * Disable all interrupts, port and break condition.
1461 */
1462
1463 spin_lock_irqsave(&sport->port.lock, flags);
1464 ucr1 = imx_uart_readl(sport, UCR1);
1465 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN);
1466
1467 imx_uart_writel(sport, ucr1, UCR1);
1468 spin_unlock_irqrestore(&sport->port.lock, flags);
1469
1470 clk_disable_unprepare(sport->clk_per);
1471 clk_disable_unprepare(sport->clk_ipg);
1472}
1473
1474/* called with port.lock taken and irqs off */
1475static void imx_uart_flush_buffer(struct uart_port *port)
1476{
1477 struct imx_port *sport = (struct imx_port *)port;
1478 struct scatterlist *sgl = &sport->tx_sgl[0];
1479 u32 ucr2;
1480 int i = 100, ubir, ubmr, uts;
1481
1482 if (!sport->dma_chan_tx)
1483 return;
1484
1485 sport->tx_bytes = 0;
1486 dmaengine_terminate_all(sport->dma_chan_tx);
1487 if (sport->dma_is_txing) {
1488 u32 ucr1;
1489
1490 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1491 DMA_TO_DEVICE);
1492 ucr1 = imx_uart_readl(sport, UCR1);
1493 ucr1 &= ~UCR1_TXDMAEN;
1494 imx_uart_writel(sport, ucr1, UCR1);
1495 sport->dma_is_txing = 0;
1496 }
1497
1498 /*
1499 * According to the Reference Manual description of the UART SRST bit:
1500 *
1501 * "Reset the transmit and receive state machines,
1502 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1503 * and UTS[6-3]".
1504 *
1505 * We don't need to restore the old values from USR1, USR2, URXD and
1506 * UTXD. UBRC is read only, so only save/restore the other three
1507 * registers.
1508 */
1509 ubir = imx_uart_readl(sport, UBIR);
1510 ubmr = imx_uart_readl(sport, UBMR);
1511 uts = imx_uart_readl(sport, IMX21_UTS);
1512
1513 ucr2 = imx_uart_readl(sport, UCR2);
1514 ucr2 &= ~UCR2_SRST;
1515 imx_uart_writel(sport, ucr2, UCR2);
1516
1517 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1518 udelay(1);
1519
1520 /* Restore the registers */
1521 imx_uart_writel(sport, ubir, UBIR);
1522 imx_uart_writel(sport, ubmr, UBMR);
1523 imx_uart_writel(sport, uts, IMX21_UTS);
1524}
1525
1526static void
1527imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1528 struct ktermios *old)
1529{
1530 struct imx_port *sport = (struct imx_port *)port;
1531 unsigned long flags;
1532 u32 ucr2, old_ucr1, old_ucr2, ufcr;
1533 unsigned int baud, quot;
1534 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1535 unsigned long div;
1536 unsigned long num, denom;
1537 uint64_t tdiv64;
1538
1539 /*
1540 * We only support CS7 and CS8.
1541 */
1542 while ((termios->c_cflag & CSIZE) != CS7 &&
1543 (termios->c_cflag & CSIZE) != CS8) {
1544 termios->c_cflag &= ~CSIZE;
1545 termios->c_cflag |= old_csize;
1546 old_csize = CS8;
1547 }
1548
1549 if ((termios->c_cflag & CSIZE) == CS8)
1550 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1551 else
1552 ucr2 = UCR2_SRST | UCR2_IRTS;
1553
1554 if (termios->c_cflag & CRTSCTS) {
1555 if (sport->have_rtscts) {
1556 ucr2 &= ~UCR2_IRTS;
1557
1558 if (port->rs485.flags & SER_RS485_ENABLED) {
1559 /*
1560 * RTS is mandatory for rs485 operation, so keep
1561 * it under manual control and keep transmitter
1562 * disabled.
1563 */
1564 if (port->rs485.flags &
1565 SER_RS485_RTS_AFTER_SEND)
1566 imx_uart_rts_active(sport, &ucr2);
1567 else
1568 imx_uart_rts_inactive(sport, &ucr2);
1569 } else {
1570 imx_uart_rts_auto(sport, &ucr2);
1571 }
1572 } else {
1573 termios->c_cflag &= ~CRTSCTS;
1574 }
1575 } else if (port->rs485.flags & SER_RS485_ENABLED) {
1576 /* disable transmitter */
1577 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1578 imx_uart_rts_active(sport, &ucr2);
1579 else
1580 imx_uart_rts_inactive(sport, &ucr2);
1581 }
1582
1583
1584 if (termios->c_cflag & CSTOPB)
1585 ucr2 |= UCR2_STPB;
1586 if (termios->c_cflag & PARENB) {
1587 ucr2 |= UCR2_PREN;
1588 if (termios->c_cflag & PARODD)
1589 ucr2 |= UCR2_PROE;
1590 }
1591
1592 del_timer_sync(&sport->timer);
1593
1594 /*
1595 * Ask the core to calculate the divisor for us.
1596 */
1597 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1598 quot = uart_get_divisor(port, baud);
1599
1600 spin_lock_irqsave(&sport->port.lock, flags);
1601
1602 sport->port.read_status_mask = 0;
1603 if (termios->c_iflag & INPCK)
1604 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1605 if (termios->c_iflag & (BRKINT | PARMRK))
1606 sport->port.read_status_mask |= URXD_BRK;
1607
1608 /*
1609 * Characters to ignore
1610 */
1611 sport->port.ignore_status_mask = 0;
1612 if (termios->c_iflag & IGNPAR)
1613 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1614 if (termios->c_iflag & IGNBRK) {
1615 sport->port.ignore_status_mask |= URXD_BRK;
1616 /*
1617 * If we're ignoring parity and break indicators,
1618 * ignore overruns too (for real raw support).
1619 */
1620 if (termios->c_iflag & IGNPAR)
1621 sport->port.ignore_status_mask |= URXD_OVRRUN;
1622 }
1623
1624 if ((termios->c_cflag & CREAD) == 0)
1625 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1626
1627 /*
1628 * Update the per-port timeout.
1629 */
1630 uart_update_timeout(port, termios->c_cflag, baud);
1631
1632 /*
1633 * disable interrupts and drain transmitter
1634 */
1635 old_ucr1 = imx_uart_readl(sport, UCR1);
1636 imx_uart_writel(sport,
1637 old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1638 UCR1);
1639 old_ucr2 = imx_uart_readl(sport, UCR2);
1640 imx_uart_writel(sport, old_ucr2 & ~UCR2_ATEN, UCR2);
1641
1642 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC))
1643 barrier();
1644
1645 /* then, disable everything */
1646 imx_uart_writel(sport, old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN | UCR2_ATEN), UCR2);
1647 old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN);
1648
1649 /* custom-baudrate handling */
1650 div = sport->port.uartclk / (baud * 16);
1651 if (baud == 38400 && quot != div)
1652 baud = sport->port.uartclk / (quot * 16);
1653
1654 div = sport->port.uartclk / (baud * 16);
1655 if (div > 7)
1656 div = 7;
1657 if (!div)
1658 div = 1;
1659
1660 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1661 1 << 16, 1 << 16, &num, &denom);
1662
1663 tdiv64 = sport->port.uartclk;
1664 tdiv64 *= num;
1665 do_div(tdiv64, denom * 16 * div);
1666 tty_termios_encode_baud_rate(termios,
1667 (speed_t)tdiv64, (speed_t)tdiv64);
1668
1669 num -= 1;
1670 denom -= 1;
1671
1672 ufcr = imx_uart_readl(sport, UFCR);
1673 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1674 imx_uart_writel(sport, ufcr, UFCR);
1675
1676 imx_uart_writel(sport, num, UBIR);
1677 imx_uart_writel(sport, denom, UBMR);
1678
1679 if (!imx_uart_is_imx1(sport))
1680 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1681 IMX21_ONEMS);
1682
1683 imx_uart_writel(sport, old_ucr1, UCR1);
1684
1685 /* set the parity, stop bits and data size */
1686 imx_uart_writel(sport, ucr2 | old_ucr2, UCR2);
1687
1688 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1689 imx_uart_enable_ms(&sport->port);
1690
1691 spin_unlock_irqrestore(&sport->port.lock, flags);
1692}
1693
1694static const char *imx_uart_type(struct uart_port *port)
1695{
1696 struct imx_port *sport = (struct imx_port *)port;
1697
1698 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1699}
1700
1701/*
1702 * Configure/autoconfigure the port.
1703 */
1704static void imx_uart_config_port(struct uart_port *port, int flags)
1705{
1706 struct imx_port *sport = (struct imx_port *)port;
1707
1708 if (flags & UART_CONFIG_TYPE)
1709 sport->port.type = PORT_IMX;
1710}
1711
1712/*
1713 * Verify the new serial_struct (for TIOCSSERIAL).
1714 * The only change we allow are to the flags and type, and
1715 * even then only between PORT_IMX and PORT_UNKNOWN
1716 */
1717static int
1718imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1719{
1720 struct imx_port *sport = (struct imx_port *)port;
1721 int ret = 0;
1722
1723 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1724 ret = -EINVAL;
1725 if (sport->port.irq != ser->irq)
1726 ret = -EINVAL;
1727 if (ser->io_type != UPIO_MEM)
1728 ret = -EINVAL;
1729 if (sport->port.uartclk / 16 != ser->baud_base)
1730 ret = -EINVAL;
1731 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1732 ret = -EINVAL;
1733 if (sport->port.iobase != ser->port)
1734 ret = -EINVAL;
1735 if (ser->hub6 != 0)
1736 ret = -EINVAL;
1737 return ret;
1738}
1739
1740#if defined(CONFIG_CONSOLE_POLL)
1741
1742static int imx_uart_poll_init(struct uart_port *port)
1743{
1744 struct imx_port *sport = (struct imx_port *)port;
1745 unsigned long flags;
1746 u32 ucr1, ucr2;
1747 int retval;
1748
1749 retval = clk_prepare_enable(sport->clk_ipg);
1750 if (retval)
1751 return retval;
1752 retval = clk_prepare_enable(sport->clk_per);
1753 if (retval)
1754 clk_disable_unprepare(sport->clk_ipg);
1755
1756 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1757
1758 spin_lock_irqsave(&sport->port.lock, flags);
1759
1760 /*
1761 * Be careful about the order of enabling bits here. First enable the
1762 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1763 * This prevents that a character that already sits in the RX fifo is
1764 * triggering an irq but the try to fetch it from there results in an
1765 * exception because UARTEN or RXEN is still off.
1766 */
1767 ucr1 = imx_uart_readl(sport, UCR1);
1768 ucr2 = imx_uart_readl(sport, UCR2);
1769
1770 if (imx_uart_is_imx1(sport))
1771 ucr1 |= IMX1_UCR1_UARTCLKEN;
1772
1773 ucr1 |= UCR1_UARTEN;
1774 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1775
1776 ucr2 |= UCR2_RXEN;
1777 ucr2 &= ~UCR2_ATEN;
1778
1779 imx_uart_writel(sport, ucr1, UCR1);
1780 imx_uart_writel(sport, ucr2, UCR2);
1781
1782 /* now enable irqs */
1783 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1784 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1785
1786 spin_unlock_irqrestore(&sport->port.lock, flags);
1787
1788 return 0;
1789}
1790
1791static int imx_uart_poll_get_char(struct uart_port *port)
1792{
1793 struct imx_port *sport = (struct imx_port *)port;
1794 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1795 return NO_POLL_CHAR;
1796
1797 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1798}
1799
1800static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1801{
1802 struct imx_port *sport = (struct imx_port *)port;
1803 unsigned int status;
1804
1805 /* drain */
1806 do {
1807 status = imx_uart_readl(sport, USR1);
1808 } while (~status & USR1_TRDY);
1809
1810 /* write */
1811 imx_uart_writel(sport, c, URTX0);
1812
1813 /* flush */
1814 do {
1815 status = imx_uart_readl(sport, USR2);
1816 } while (~status & USR2_TXDC);
1817}
1818#endif
1819
1820/* called with port.lock taken and irqs off or from .probe without locking */
1821static int imx_uart_rs485_config(struct uart_port *port,
1822 struct serial_rs485 *rs485conf)
1823{
1824 struct imx_port *sport = (struct imx_port *)port;
1825 u32 ucr2;
1826
1827 /* unimplemented */
1828 rs485conf->delay_rts_before_send = 0;
1829 rs485conf->delay_rts_after_send = 0;
1830
1831 /* RTS is required to control the transmitter */
1832 if (!sport->have_rtscts && !sport->have_rtsgpio)
1833 rs485conf->flags &= ~SER_RS485_ENABLED;
1834
1835 if (rs485conf->flags & SER_RS485_ENABLED) {
1836 /* Enable receiver if low-active RTS signal is requested */
1837 if (sport->have_rtscts && !sport->have_rtsgpio &&
1838 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1839 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1840
1841 /* disable transmitter */
1842 ucr2 = imx_uart_readl(sport, UCR2);
1843 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1844 imx_uart_rts_active(sport, &ucr2);
1845 else
1846 imx_uart_rts_inactive(sport, &ucr2);
1847 imx_uart_writel(sport, ucr2, UCR2);
1848 }
1849
1850 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1851 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1852 rs485conf->flags & SER_RS485_RX_DURING_TX)
1853 imx_uart_start_rx(port);
1854
1855 port->rs485 = *rs485conf;
1856
1857 return 0;
1858}
1859
1860static const struct uart_ops imx_uart_pops = {
1861 .tx_empty = imx_uart_tx_empty,
1862 .set_mctrl = imx_uart_set_mctrl,
1863 .get_mctrl = imx_uart_get_mctrl,
1864 .stop_tx = imx_uart_stop_tx,
1865 .start_tx = imx_uart_start_tx,
1866 .stop_rx = imx_uart_stop_rx,
1867 .enable_ms = imx_uart_enable_ms,
1868 .break_ctl = imx_uart_break_ctl,
1869 .startup = imx_uart_startup,
1870 .shutdown = imx_uart_shutdown,
1871 .flush_buffer = imx_uart_flush_buffer,
1872 .set_termios = imx_uart_set_termios,
1873 .type = imx_uart_type,
1874 .config_port = imx_uart_config_port,
1875 .verify_port = imx_uart_verify_port,
1876#if defined(CONFIG_CONSOLE_POLL)
1877 .poll_init = imx_uart_poll_init,
1878 .poll_get_char = imx_uart_poll_get_char,
1879 .poll_put_char = imx_uart_poll_put_char,
1880#endif
1881};
1882
1883static struct imx_port *imx_uart_ports[UART_NR];
1884
1885#ifdef CONFIG_SERIAL_IMX_CONSOLE
1886static void imx_uart_console_putchar(struct uart_port *port, int ch)
1887{
1888 struct imx_port *sport = (struct imx_port *)port;
1889
1890 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1891 barrier();
1892
1893 imx_uart_writel(sport, ch, URTX0);
1894}
1895
1896/*
1897 * Interrupts are disabled on entering
1898 */
1899static void
1900imx_uart_console_write(struct console *co, const char *s, unsigned int count)
1901{
1902 struct imx_port *sport = imx_uart_ports[co->index];
1903 struct imx_port_ucrs old_ucr;
1904 unsigned int ucr1;
1905 unsigned long flags = 0;
1906 int locked = 1;
1907 int retval;
1908
1909 retval = clk_enable(sport->clk_per);
1910 if (retval)
1911 return;
1912 retval = clk_enable(sport->clk_ipg);
1913 if (retval) {
1914 clk_disable(sport->clk_per);
1915 return;
1916 }
1917
1918 if (sport->port.sysrq)
1919 locked = 0;
1920 else if (oops_in_progress)
1921 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1922 else
1923 spin_lock_irqsave(&sport->port.lock, flags);
1924
1925 /*
1926 * First, save UCR1/2/3 and then disable interrupts
1927 */
1928 imx_uart_ucrs_save(sport, &old_ucr);
1929 ucr1 = old_ucr.ucr1;
1930
1931 if (imx_uart_is_imx1(sport))
1932 ucr1 |= IMX1_UCR1_UARTCLKEN;
1933 ucr1 |= UCR1_UARTEN;
1934 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1935
1936 imx_uart_writel(sport, ucr1, UCR1);
1937
1938 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
1939
1940 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
1941
1942 /*
1943 * Finally, wait for transmitter to become empty
1944 * and restore UCR1/2/3
1945 */
1946 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC));
1947
1948 imx_uart_ucrs_restore(sport, &old_ucr);
1949
1950 if (locked)
1951 spin_unlock_irqrestore(&sport->port.lock, flags);
1952
1953 clk_disable(sport->clk_ipg);
1954 clk_disable(sport->clk_per);
1955}
1956
1957/*
1958 * If the port was already initialised (eg, by a boot loader),
1959 * try to determine the current setup.
1960 */
1961static void __init
1962imx_uart_console_get_options(struct imx_port *sport, int *baud,
1963 int *parity, int *bits)
1964{
1965
1966 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
1967 /* ok, the port was enabled */
1968 unsigned int ucr2, ubir, ubmr, uartclk;
1969 unsigned int baud_raw;
1970 unsigned int ucfr_rfdiv;
1971
1972 ucr2 = imx_uart_readl(sport, UCR2);
1973
1974 *parity = 'n';
1975 if (ucr2 & UCR2_PREN) {
1976 if (ucr2 & UCR2_PROE)
1977 *parity = 'o';
1978 else
1979 *parity = 'e';
1980 }
1981
1982 if (ucr2 & UCR2_WS)
1983 *bits = 8;
1984 else
1985 *bits = 7;
1986
1987 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
1988 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
1989
1990 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
1991 if (ucfr_rfdiv == 6)
1992 ucfr_rfdiv = 7;
1993 else
1994 ucfr_rfdiv = 6 - ucfr_rfdiv;
1995
1996 uartclk = clk_get_rate(sport->clk_per);
1997 uartclk /= ucfr_rfdiv;
1998
1999 { /*
2000 * The next code provides exact computation of
2001 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2002 * without need of float support or long long division,
2003 * which would be required to prevent 32bit arithmetic overflow
2004 */
2005 unsigned int mul = ubir + 1;
2006 unsigned int div = 16 * (ubmr + 1);
2007 unsigned int rem = uartclk % div;
2008
2009 baud_raw = (uartclk / div) * mul;
2010 baud_raw += (rem * mul + div / 2) / div;
2011 *baud = (baud_raw + 50) / 100 * 100;
2012 }
2013
2014 if (*baud != baud_raw)
2015 pr_info("Console IMX rounded baud rate from %d to %d\n",
2016 baud_raw, *baud);
2017 }
2018}
2019
2020static int __init
2021imx_uart_console_setup(struct console *co, char *options)
2022{
2023 struct imx_port *sport;
2024 int baud = 9600;
2025 int bits = 8;
2026 int parity = 'n';
2027 int flow = 'n';
2028 int retval;
2029
2030 /*
2031 * Check whether an invalid uart number has been specified, and
2032 * if so, search for the first available port that does have
2033 * console support.
2034 */
2035 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2036 co->index = 0;
2037 sport = imx_uart_ports[co->index];
2038 if (sport == NULL)
2039 return -ENODEV;
2040
2041 /* For setting the registers, we only need to enable the ipg clock. */
2042 retval = clk_prepare_enable(sport->clk_ipg);
2043 if (retval)
2044 goto error_console;
2045
2046 if (options)
2047 uart_parse_options(options, &baud, &parity, &bits, &flow);
2048 else
2049 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2050
2051 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2052
2053 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2054
2055 clk_disable(sport->clk_ipg);
2056 if (retval) {
2057 clk_unprepare(sport->clk_ipg);
2058 goto error_console;
2059 }
2060
2061 retval = clk_prepare(sport->clk_per);
2062 if (retval)
2063 clk_disable_unprepare(sport->clk_ipg);
2064
2065error_console:
2066 return retval;
2067}
2068
2069static struct uart_driver imx_uart_uart_driver;
2070static struct console imx_uart_console = {
2071 .name = DEV_NAME,
2072 .write = imx_uart_console_write,
2073 .device = uart_console_device,
2074 .setup = imx_uart_console_setup,
2075 .flags = CON_PRINTBUFFER,
2076 .index = -1,
2077 .data = &imx_uart_uart_driver,
2078};
2079
2080#define IMX_CONSOLE &imx_uart_console
2081
2082#ifdef CONFIG_OF
2083static void imx_uart_console_early_putchar(struct uart_port *port, int ch)
2084{
2085 struct imx_port *sport = (struct imx_port *)port;
2086
2087 while (imx_uart_readl(sport, IMX21_UTS) & UTS_TXFULL)
2088 cpu_relax();
2089
2090 imx_uart_writel(sport, ch, URTX0);
2091}
2092
2093static void imx_uart_console_early_write(struct console *con, const char *s,
2094 unsigned count)
2095{
2096 struct earlycon_device *dev = con->data;
2097
2098 uart_console_write(&dev->port, s, count, imx_uart_console_early_putchar);
2099}
2100
2101static int __init
2102imx_console_early_setup(struct earlycon_device *dev, const char *opt)
2103{
2104 if (!dev->port.membase)
2105 return -ENODEV;
2106
2107 dev->con->write = imx_uart_console_early_write;
2108
2109 return 0;
2110}
2111OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
2112OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
2113#endif
2114
2115#else
2116#define IMX_CONSOLE NULL
2117#endif
2118
2119static struct uart_driver imx_uart_uart_driver = {
2120 .owner = THIS_MODULE,
2121 .driver_name = DRIVER_NAME,
2122 .dev_name = DEV_NAME,
2123 .major = SERIAL_IMX_MAJOR,
2124 .minor = MINOR_START,
2125 .nr = ARRAY_SIZE(imx_uart_ports),
2126 .cons = IMX_CONSOLE,
2127};
2128
2129#ifdef CONFIG_OF
2130/*
2131 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
2132 * could successfully get all information from dt or a negative errno.
2133 */
2134static int imx_uart_probe_dt(struct imx_port *sport,
2135 struct platform_device *pdev)
2136{
2137 struct device_node *np = pdev->dev.of_node;
2138 int ret;
2139
2140 sport->devdata = of_device_get_match_data(&pdev->dev);
2141 if (!sport->devdata)
2142 /* no device tree device */
2143 return 1;
2144
2145 ret = of_alias_get_id(np, "serial");
2146 if (ret < 0) {
2147 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2148 return ret;
2149 }
2150 sport->port.line = ret;
2151
2152 if (of_get_property(np, "uart-has-rtscts", NULL) ||
2153 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
2154 sport->have_rtscts = 1;
2155
2156 if (of_get_property(np, "fsl,dte-mode", NULL))
2157 sport->dte_mode = 1;
2158
2159 if (of_get_property(np, "rts-gpios", NULL))
2160 sport->have_rtsgpio = 1;
2161
2162 return 0;
2163}
2164#else
2165static inline int imx_uart_probe_dt(struct imx_port *sport,
2166 struct platform_device *pdev)
2167{
2168 return 1;
2169}
2170#endif
2171
2172static void imx_uart_probe_pdata(struct imx_port *sport,
2173 struct platform_device *pdev)
2174{
2175 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
2176
2177 sport->port.line = pdev->id;
2178 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
2179
2180 if (!pdata)
2181 return;
2182
2183 if (pdata->flags & IMXUART_HAVE_RTSCTS)
2184 sport->have_rtscts = 1;
2185}
2186
2187static int imx_uart_probe(struct platform_device *pdev)
2188{
2189 struct imx_port *sport;
2190 void __iomem *base;
2191 int ret = 0;
2192 u32 ucr1;
2193 struct resource *res;
2194 int txirq, rxirq, rtsirq;
2195
2196 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2197 if (!sport)
2198 return -ENOMEM;
2199
2200 ret = imx_uart_probe_dt(sport, pdev);
2201 if (ret > 0)
2202 imx_uart_probe_pdata(sport, pdev);
2203 else if (ret < 0)
2204 return ret;
2205
2206 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2207 dev_err(&pdev->dev, "serial%d out of range\n",
2208 sport->port.line);
2209 return -EINVAL;
2210 }
2211
2212 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2213 base = devm_ioremap_resource(&pdev->dev, res);
2214 if (IS_ERR(base))
2215 return PTR_ERR(base);
2216
2217 rxirq = platform_get_irq(pdev, 0);
2218 txirq = platform_get_irq(pdev, 1);
2219 rtsirq = platform_get_irq(pdev, 2);
2220
2221 sport->port.dev = &pdev->dev;
2222 sport->port.mapbase = res->start;
2223 sport->port.membase = base;
2224 sport->port.type = PORT_IMX,
2225 sport->port.iotype = UPIO_MEM;
2226 sport->port.irq = rxirq;
2227 sport->port.fifosize = 32;
2228 sport->port.ops = &imx_uart_pops;
2229 sport->port.rs485_config = imx_uart_rs485_config;
2230 sport->port.flags = UPF_BOOT_AUTOCONF;
2231 timer_setup(&sport->timer, imx_uart_timeout, 0);
2232
2233 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2234 if (IS_ERR(sport->gpios))
2235 return PTR_ERR(sport->gpios);
2236
2237 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2238 if (IS_ERR(sport->clk_ipg)) {
2239 ret = PTR_ERR(sport->clk_ipg);
2240 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2241 return ret;
2242 }
2243
2244 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2245 if (IS_ERR(sport->clk_per)) {
2246 ret = PTR_ERR(sport->clk_per);
2247 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2248 return ret;
2249 }
2250
2251 sport->port.uartclk = clk_get_rate(sport->clk_per);
2252
2253 /* For register access, we only need to enable the ipg clock. */
2254 ret = clk_prepare_enable(sport->clk_ipg);
2255 if (ret) {
2256 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2257 return ret;
2258 }
2259
2260 /* initialize shadow register values */
2261 sport->ucr1 = readl(sport->port.membase + UCR1);
2262 sport->ucr2 = readl(sport->port.membase + UCR2);
2263 sport->ucr3 = readl(sport->port.membase + UCR3);
2264 sport->ucr4 = readl(sport->port.membase + UCR4);
2265 sport->ufcr = readl(sport->port.membase + UFCR);
2266
2267 uart_get_rs485_mode(&pdev->dev, &sport->port.rs485);
2268
2269 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2270 (!sport->have_rtscts && !sport->have_rtsgpio))
2271 dev_err(&pdev->dev, "no RTS control, disabling rs485\n");
2272
2273 /*
2274 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2275 * signal cannot be set low during transmission in case the
2276 * receiver is off (limitation of the i.MX UART IP).
2277 */
2278 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2279 sport->have_rtscts && !sport->have_rtsgpio &&
2280 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2281 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2282 dev_err(&pdev->dev,
2283 "low-active RTS not possible when receiver is off, enabling receiver\n");
2284
2285 imx_uart_rs485_config(&sport->port, &sport->port.rs485);
2286
2287 /* Disable interrupts before requesting them */
2288 ucr1 = imx_uart_readl(sport, UCR1);
2289 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
2290 UCR1_TXMPTYEN | UCR1_RTSDEN);
2291 imx_uart_writel(sport, ucr1, UCR1);
2292
2293 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2294 /*
2295 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2296 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2297 * and DCD (when they are outputs) or enables the respective
2298 * irqs. So set this bit early, i.e. before requesting irqs.
2299 */
2300 u32 ufcr = imx_uart_readl(sport, UFCR);
2301 if (!(ufcr & UFCR_DCEDTE))
2302 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2303
2304 /*
2305 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2306 * enabled later because they cannot be cleared
2307 * (confirmed on i.MX25) which makes them unusable.
2308 */
2309 imx_uart_writel(sport,
2310 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2311 UCR3);
2312
2313 } else {
2314 u32 ucr3 = UCR3_DSR;
2315 u32 ufcr = imx_uart_readl(sport, UFCR);
2316 if (ufcr & UFCR_DCEDTE)
2317 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2318
2319 if (!imx_uart_is_imx1(sport))
2320 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2321 imx_uart_writel(sport, ucr3, UCR3);
2322 }
2323
2324 clk_disable_unprepare(sport->clk_ipg);
2325
2326 /*
2327 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2328 * chips only have one interrupt.
2329 */
2330 if (txirq > 0) {
2331 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2332 dev_name(&pdev->dev), sport);
2333 if (ret) {
2334 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2335 ret);
2336 return ret;
2337 }
2338
2339 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2340 dev_name(&pdev->dev), sport);
2341 if (ret) {
2342 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2343 ret);
2344 return ret;
2345 }
2346 } else {
2347 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2348 dev_name(&pdev->dev), sport);
2349 if (ret) {
2350 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2351 return ret;
2352 }
2353 }
2354
2355 imx_uart_ports[sport->port.line] = sport;
2356
2357 platform_set_drvdata(pdev, sport);
2358
2359 return uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2360}
2361
2362static int imx_uart_remove(struct platform_device *pdev)
2363{
2364 struct imx_port *sport = platform_get_drvdata(pdev);
2365
2366 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2367}
2368
2369static void imx_uart_restore_context(struct imx_port *sport)
2370{
2371 if (!sport->context_saved)
2372 return;
2373
2374 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2375 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2376 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2377 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2378 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2379 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2380 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2381 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2382 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2383 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2384 sport->context_saved = false;
2385}
2386
2387static void imx_uart_save_context(struct imx_port *sport)
2388{
2389 /* Save necessary regs */
2390 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2391 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2392 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2393 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2394 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2395 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2396 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2397 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2398 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2399 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2400 sport->context_saved = true;
2401}
2402
2403static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2404{
2405 u32 ucr3;
2406
2407 ucr3 = imx_uart_readl(sport, UCR3);
2408 if (on) {
2409 imx_uart_writel(sport, USR1_AWAKE, USR1);
2410 ucr3 |= UCR3_AWAKEN;
2411 } else {
2412 ucr3 &= ~UCR3_AWAKEN;
2413 }
2414 imx_uart_writel(sport, ucr3, UCR3);
2415
2416 if (sport->have_rtscts) {
2417 u32 ucr1 = imx_uart_readl(sport, UCR1);
2418 if (on)
2419 ucr1 |= UCR1_RTSDEN;
2420 else
2421 ucr1 &= ~UCR1_RTSDEN;
2422 imx_uart_writel(sport, ucr1, UCR1);
2423 }
2424}
2425
2426static int imx_uart_suspend_noirq(struct device *dev)
2427{
2428 struct platform_device *pdev = to_platform_device(dev);
2429 struct imx_port *sport = platform_get_drvdata(pdev);
2430
2431 imx_uart_save_context(sport);
2432
2433 clk_disable(sport->clk_ipg);
2434
2435 return 0;
2436}
2437
2438static int imx_uart_resume_noirq(struct device *dev)
2439{
2440 struct platform_device *pdev = to_platform_device(dev);
2441 struct imx_port *sport = platform_get_drvdata(pdev);
2442 int ret;
2443
2444 ret = clk_enable(sport->clk_ipg);
2445 if (ret)
2446 return ret;
2447
2448 imx_uart_restore_context(sport);
2449
2450 return 0;
2451}
2452
2453static int imx_uart_suspend(struct device *dev)
2454{
2455 struct platform_device *pdev = to_platform_device(dev);
2456 struct imx_port *sport = platform_get_drvdata(pdev);
2457 int ret;
2458
2459 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2460 disable_irq(sport->port.irq);
2461
2462 ret = clk_prepare_enable(sport->clk_ipg);
2463 if (ret)
2464 return ret;
2465
2466 /* enable wakeup from i.MX UART */
2467 imx_uart_enable_wakeup(sport, true);
2468
2469 return 0;
2470}
2471
2472static int imx_uart_resume(struct device *dev)
2473{
2474 struct platform_device *pdev = to_platform_device(dev);
2475 struct imx_port *sport = platform_get_drvdata(pdev);
2476
2477 /* disable wakeup from i.MX UART */
2478 imx_uart_enable_wakeup(sport, false);
2479
2480 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2481 enable_irq(sport->port.irq);
2482
2483 clk_disable_unprepare(sport->clk_ipg);
2484
2485 return 0;
2486}
2487
2488static int imx_uart_freeze(struct device *dev)
2489{
2490 struct platform_device *pdev = to_platform_device(dev);
2491 struct imx_port *sport = platform_get_drvdata(pdev);
2492
2493 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2494
2495 return clk_prepare_enable(sport->clk_ipg);
2496}
2497
2498static int imx_uart_thaw(struct device *dev)
2499{
2500 struct platform_device *pdev = to_platform_device(dev);
2501 struct imx_port *sport = platform_get_drvdata(pdev);
2502
2503 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2504
2505 clk_disable_unprepare(sport->clk_ipg);
2506
2507 return 0;
2508}
2509
2510static const struct dev_pm_ops imx_uart_pm_ops = {
2511 .suspend_noirq = imx_uart_suspend_noirq,
2512 .resume_noirq = imx_uart_resume_noirq,
2513 .freeze_noirq = imx_uart_suspend_noirq,
2514 .restore_noirq = imx_uart_resume_noirq,
2515 .suspend = imx_uart_suspend,
2516 .resume = imx_uart_resume,
2517 .freeze = imx_uart_freeze,
2518 .thaw = imx_uart_thaw,
2519 .restore = imx_uart_thaw,
2520};
2521
2522static struct platform_driver imx_uart_platform_driver = {
2523 .probe = imx_uart_probe,
2524 .remove = imx_uart_remove,
2525
2526 .id_table = imx_uart_devtype,
2527 .driver = {
2528 .name = "imx-uart",
2529 .of_match_table = imx_uart_dt_ids,
2530 .pm = &imx_uart_pm_ops,
2531 },
2532};
2533
2534static int __init imx_uart_init(void)
2535{
2536 int ret = uart_register_driver(&imx_uart_uart_driver);
2537
2538 if (ret)
2539 return ret;
2540
2541 ret = platform_driver_register(&imx_uart_platform_driver);
2542 if (ret != 0)
2543 uart_unregister_driver(&imx_uart_uart_driver);
2544
2545 return ret;
2546}
2547
2548static void __exit imx_uart_exit(void)
2549{
2550 platform_driver_unregister(&imx_uart_platform_driver);
2551 uart_unregister_driver(&imx_uart_uart_driver);
2552}
2553
2554module_init(imx_uart_init);
2555module_exit(imx_uart_exit);
2556
2557MODULE_AUTHOR("Sascha Hauer");
2558MODULE_DESCRIPTION("IMX generic serial port driver");
2559MODULE_LICENSE("GPL");
2560MODULE_ALIAS("platform:imx-uart");