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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for Atmel AT91 Serial ports
4 * Copyright (C) 2003 Rick Bronson
5 *
6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 *
9 * DMA support added by Chip Coldwell.
10 */
11#include <linux/tty.h>
12#include <linux/ioport.h>
13#include <linux/slab.h>
14#include <linux/init.h>
15#include <linux/serial.h>
16#include <linux/clk.h>
17#include <linux/console.h>
18#include <linux/sysrq.h>
19#include <linux/tty_flip.h>
20#include <linux/platform_device.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/dma-mapping.h>
24#include <linux/dmaengine.h>
25#include <linux/atmel_pdc.h>
26#include <linux/uaccess.h>
27#include <linux/platform_data/atmel.h>
28#include <linux/timer.h>
29#include <linux/err.h>
30#include <linux/irq.h>
31#include <linux/suspend.h>
32#include <linux/mm.h>
33#include <linux/io.h>
34
35#include <asm/div64.h>
36#include <asm/ioctls.h>
37
38#define PDC_BUFFER_SIZE 512
39/* Revisit: We should calculate this based on the actual port settings */
40#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
41
42/* The minium number of data FIFOs should be able to contain */
43#define ATMEL_MIN_FIFO_SIZE 8
44/*
45 * These two offsets are substracted from the RX FIFO size to define the RTS
46 * high and low thresholds
47 */
48#define ATMEL_RTS_HIGH_OFFSET 16
49#define ATMEL_RTS_LOW_OFFSET 20
50
51#include <linux/serial_core.h>
52
53#include "serial_mctrl_gpio.h"
54#include "atmel_serial.h"
55
56static void atmel_start_rx(struct uart_port *port);
57static void atmel_stop_rx(struct uart_port *port);
58
59#ifdef CONFIG_SERIAL_ATMEL_TTYAT
60
61/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
62 * should coexist with the 8250 driver, such as if we have an external 16C550
63 * UART. */
64#define SERIAL_ATMEL_MAJOR 204
65#define MINOR_START 154
66#define ATMEL_DEVICENAME "ttyAT"
67
68#else
69
70/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
71 * name, but it is legally reserved for the 8250 driver. */
72#define SERIAL_ATMEL_MAJOR TTY_MAJOR
73#define MINOR_START 64
74#define ATMEL_DEVICENAME "ttyS"
75
76#endif
77
78#define ATMEL_ISR_PASS_LIMIT 256
79
80struct atmel_dma_buffer {
81 unsigned char *buf;
82 dma_addr_t dma_addr;
83 unsigned int dma_size;
84 unsigned int ofs;
85};
86
87struct atmel_uart_char {
88 u16 status;
89 u16 ch;
90};
91
92/*
93 * Be careful, the real size of the ring buffer is
94 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
95 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
96 * DMA mode.
97 */
98#define ATMEL_SERIAL_RINGSIZE 1024
99
100/*
101 * at91: 6 USARTs and one DBGU port (SAM9260)
102 * samx7: 3 USARTs and 5 UARTs
103 */
104#define ATMEL_MAX_UART 8
105
106/*
107 * We wrap our port structure around the generic uart_port.
108 */
109struct atmel_uart_port {
110 struct uart_port uart; /* uart */
111 struct clk *clk; /* uart clock */
112 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
113 u32 backup_imr; /* IMR saved during suspend */
114 int break_active; /* break being received */
115
116 bool use_dma_rx; /* enable DMA receiver */
117 bool use_pdc_rx; /* enable PDC receiver */
118 short pdc_rx_idx; /* current PDC RX buffer */
119 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
120
121 bool use_dma_tx; /* enable DMA transmitter */
122 bool use_pdc_tx; /* enable PDC transmitter */
123 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
124
125 spinlock_t lock_tx; /* port lock */
126 spinlock_t lock_rx; /* port lock */
127 struct dma_chan *chan_tx;
128 struct dma_chan *chan_rx;
129 struct dma_async_tx_descriptor *desc_tx;
130 struct dma_async_tx_descriptor *desc_rx;
131 dma_cookie_t cookie_tx;
132 dma_cookie_t cookie_rx;
133 struct scatterlist sg_tx;
134 struct scatterlist sg_rx;
135 struct tasklet_struct tasklet_rx;
136 struct tasklet_struct tasklet_tx;
137 atomic_t tasklet_shutdown;
138 unsigned int irq_status_prev;
139 unsigned int tx_len;
140
141 struct circ_buf rx_ring;
142
143 struct mctrl_gpios *gpios;
144 u32 backup_mode; /* MR saved during iso7816 operations */
145 u32 backup_brgr; /* BRGR saved during iso7816 operations */
146 unsigned int tx_done_mask;
147 u32 fifo_size;
148 u32 rts_high;
149 u32 rts_low;
150 bool ms_irq_enabled;
151 u32 rtor; /* address of receiver timeout register if it exists */
152 bool has_frac_baudrate;
153 bool has_hw_timer;
154 struct timer_list uart_timer;
155
156 bool tx_stopped;
157 bool suspended;
158 unsigned int pending;
159 unsigned int pending_status;
160 spinlock_t lock_suspended;
161
162 bool hd_start_rx; /* can start RX during half-duplex operation */
163
164 /* ISO7816 */
165 unsigned int fidi_min;
166 unsigned int fidi_max;
167
168#ifdef CONFIG_PM
169 struct {
170 u32 cr;
171 u32 mr;
172 u32 imr;
173 u32 brgr;
174 u32 rtor;
175 u32 ttgr;
176 u32 fmr;
177 u32 fimr;
178 } cache;
179#endif
180
181 int (*prepare_rx)(struct uart_port *port);
182 int (*prepare_tx)(struct uart_port *port);
183 void (*schedule_rx)(struct uart_port *port);
184 void (*schedule_tx)(struct uart_port *port);
185 void (*release_rx)(struct uart_port *port);
186 void (*release_tx)(struct uart_port *port);
187};
188
189static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
190static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
191
192#if defined(CONFIG_OF)
193static const struct of_device_id atmel_serial_dt_ids[] = {
194 { .compatible = "atmel,at91rm9200-usart-serial" },
195 { /* sentinel */ }
196};
197#endif
198
199static inline struct atmel_uart_port *
200to_atmel_uart_port(struct uart_port *uart)
201{
202 return container_of(uart, struct atmel_uart_port, uart);
203}
204
205static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
206{
207 return __raw_readl(port->membase + reg);
208}
209
210static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
211{
212 __raw_writel(value, port->membase + reg);
213}
214
215static inline u8 atmel_uart_read_char(struct uart_port *port)
216{
217 return __raw_readb(port->membase + ATMEL_US_RHR);
218}
219
220static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
221{
222 __raw_writeb(value, port->membase + ATMEL_US_THR);
223}
224
225static inline int atmel_uart_is_half_duplex(struct uart_port *port)
226{
227 return ((port->rs485.flags & SER_RS485_ENABLED) &&
228 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
229 (port->iso7816.flags & SER_ISO7816_ENABLED);
230}
231
232#ifdef CONFIG_SERIAL_ATMEL_PDC
233static bool atmel_use_pdc_rx(struct uart_port *port)
234{
235 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
236
237 return atmel_port->use_pdc_rx;
238}
239
240static bool atmel_use_pdc_tx(struct uart_port *port)
241{
242 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
243
244 return atmel_port->use_pdc_tx;
245}
246#else
247static bool atmel_use_pdc_rx(struct uart_port *port)
248{
249 return false;
250}
251
252static bool atmel_use_pdc_tx(struct uart_port *port)
253{
254 return false;
255}
256#endif
257
258static bool atmel_use_dma_tx(struct uart_port *port)
259{
260 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
261
262 return atmel_port->use_dma_tx;
263}
264
265static bool atmel_use_dma_rx(struct uart_port *port)
266{
267 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
268
269 return atmel_port->use_dma_rx;
270}
271
272static bool atmel_use_fifo(struct uart_port *port)
273{
274 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
275
276 return atmel_port->fifo_size;
277}
278
279static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
280 struct tasklet_struct *t)
281{
282 if (!atomic_read(&atmel_port->tasklet_shutdown))
283 tasklet_schedule(t);
284}
285
286/* Enable or disable the rs485 support */
287static int atmel_config_rs485(struct uart_port *port,
288 struct serial_rs485 *rs485conf)
289{
290 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
291 unsigned int mode;
292
293 /* Disable interrupts */
294 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
295
296 mode = atmel_uart_readl(port, ATMEL_US_MR);
297
298 /* Resetting serial mode to RS232 (0x0) */
299 mode &= ~ATMEL_US_USMODE;
300
301 port->rs485 = *rs485conf;
302
303 if (rs485conf->flags & SER_RS485_ENABLED) {
304 dev_dbg(port->dev, "Setting UART to RS485\n");
305 if (port->rs485.flags & SER_RS485_RX_DURING_TX)
306 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
307 else
308 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
309
310 atmel_uart_writel(port, ATMEL_US_TTGR,
311 rs485conf->delay_rts_after_send);
312 mode |= ATMEL_US_USMODE_RS485;
313 } else {
314 dev_dbg(port->dev, "Setting UART to RS232\n");
315 if (atmel_use_pdc_tx(port))
316 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
317 ATMEL_US_TXBUFE;
318 else
319 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
320 }
321 atmel_uart_writel(port, ATMEL_US_MR, mode);
322
323 /* Enable interrupts */
324 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
325
326 return 0;
327}
328
329static unsigned int atmel_calc_cd(struct uart_port *port,
330 struct serial_iso7816 *iso7816conf)
331{
332 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
333 unsigned int cd;
334 u64 mck_rate;
335
336 mck_rate = (u64)clk_get_rate(atmel_port->clk);
337 do_div(mck_rate, iso7816conf->clk);
338 cd = mck_rate;
339 return cd;
340}
341
342static unsigned int atmel_calc_fidi(struct uart_port *port,
343 struct serial_iso7816 *iso7816conf)
344{
345 u64 fidi = 0;
346
347 if (iso7816conf->sc_fi && iso7816conf->sc_di) {
348 fidi = (u64)iso7816conf->sc_fi;
349 do_div(fidi, iso7816conf->sc_di);
350 }
351 return (u32)fidi;
352}
353
354/* Enable or disable the iso7816 support */
355/* Called with interrupts disabled */
356static int atmel_config_iso7816(struct uart_port *port,
357 struct serial_iso7816 *iso7816conf)
358{
359 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
360 unsigned int mode;
361 unsigned int cd, fidi;
362 int ret = 0;
363
364 /* Disable interrupts */
365 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
366
367 mode = atmel_uart_readl(port, ATMEL_US_MR);
368
369 if (iso7816conf->flags & SER_ISO7816_ENABLED) {
370 mode &= ~ATMEL_US_USMODE;
371
372 if (iso7816conf->tg > 255) {
373 dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n");
374 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
375 ret = -EINVAL;
376 goto err_out;
377 }
378
379 if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
380 == SER_ISO7816_T(0)) {
381 mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK;
382 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
383 == SER_ISO7816_T(1)) {
384 mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK;
385 } else {
386 dev_err(port->dev, "ISO7816: Type not supported\n");
387 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
388 ret = -EINVAL;
389 goto err_out;
390 }
391
392 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR);
393
394 /* select mck clock, and output */
395 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
396 /* set parity for normal/inverse mode + max iterations */
397 mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3);
398
399 cd = atmel_calc_cd(port, iso7816conf);
400 fidi = atmel_calc_fidi(port, iso7816conf);
401 if (fidi == 0) {
402 dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n");
403 } else if (fidi < atmel_port->fidi_min
404 || fidi > atmel_port->fidi_max) {
405 dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi);
406 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
407 ret = -EINVAL;
408 goto err_out;
409 }
410
411 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) {
412 /* port not yet in iso7816 mode: store configuration */
413 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR);
414 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
415 }
416
417 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg);
418 atmel_uart_writel(port, ATMEL_US_BRGR, cd);
419 atmel_uart_writel(port, ATMEL_US_FIDI, fidi);
420
421 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN);
422 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION;
423 } else {
424 dev_dbg(port->dev, "Setting UART back to RS232\n");
425 /* back to last RS232 settings */
426 mode = atmel_port->backup_mode;
427 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
428 atmel_uart_writel(port, ATMEL_US_TTGR, 0);
429 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr);
430 atmel_uart_writel(port, ATMEL_US_FIDI, 0x174);
431
432 if (atmel_use_pdc_tx(port))
433 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
434 ATMEL_US_TXBUFE;
435 else
436 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
437 }
438
439 port->iso7816 = *iso7816conf;
440
441 atmel_uart_writel(port, ATMEL_US_MR, mode);
442
443err_out:
444 /* Enable interrupts */
445 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
446
447 return ret;
448}
449
450/*
451 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
452 */
453static u_int atmel_tx_empty(struct uart_port *port)
454{
455 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
456
457 if (atmel_port->tx_stopped)
458 return TIOCSER_TEMT;
459 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
460 TIOCSER_TEMT :
461 0;
462}
463
464/*
465 * Set state of the modem control output lines
466 */
467static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
468{
469 unsigned int control = 0;
470 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
471 unsigned int rts_paused, rts_ready;
472 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
473
474 /* override mode to RS485 if needed, otherwise keep the current mode */
475 if (port->rs485.flags & SER_RS485_ENABLED) {
476 atmel_uart_writel(port, ATMEL_US_TTGR,
477 port->rs485.delay_rts_after_send);
478 mode &= ~ATMEL_US_USMODE;
479 mode |= ATMEL_US_USMODE_RS485;
480 }
481
482 /* set the RTS line state according to the mode */
483 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
484 /* force RTS line to high level */
485 rts_paused = ATMEL_US_RTSEN;
486
487 /* give the control of the RTS line back to the hardware */
488 rts_ready = ATMEL_US_RTSDIS;
489 } else {
490 /* force RTS line to high level */
491 rts_paused = ATMEL_US_RTSDIS;
492
493 /* force RTS line to low level */
494 rts_ready = ATMEL_US_RTSEN;
495 }
496
497 if (mctrl & TIOCM_RTS)
498 control |= rts_ready;
499 else
500 control |= rts_paused;
501
502 if (mctrl & TIOCM_DTR)
503 control |= ATMEL_US_DTREN;
504 else
505 control |= ATMEL_US_DTRDIS;
506
507 atmel_uart_writel(port, ATMEL_US_CR, control);
508
509 mctrl_gpio_set(atmel_port->gpios, mctrl);
510
511 /* Local loopback mode? */
512 mode &= ~ATMEL_US_CHMODE;
513 if (mctrl & TIOCM_LOOP)
514 mode |= ATMEL_US_CHMODE_LOC_LOOP;
515 else
516 mode |= ATMEL_US_CHMODE_NORMAL;
517
518 atmel_uart_writel(port, ATMEL_US_MR, mode);
519}
520
521/*
522 * Get state of the modem control input lines
523 */
524static u_int atmel_get_mctrl(struct uart_port *port)
525{
526 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
527 unsigned int ret = 0, status;
528
529 status = atmel_uart_readl(port, ATMEL_US_CSR);
530
531 /*
532 * The control signals are active low.
533 */
534 if (!(status & ATMEL_US_DCD))
535 ret |= TIOCM_CD;
536 if (!(status & ATMEL_US_CTS))
537 ret |= TIOCM_CTS;
538 if (!(status & ATMEL_US_DSR))
539 ret |= TIOCM_DSR;
540 if (!(status & ATMEL_US_RI))
541 ret |= TIOCM_RI;
542
543 return mctrl_gpio_get(atmel_port->gpios, &ret);
544}
545
546/*
547 * Stop transmitting.
548 */
549static void atmel_stop_tx(struct uart_port *port)
550{
551 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
552
553 if (atmel_use_pdc_tx(port)) {
554 /* disable PDC transmit */
555 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
556 }
557
558 /*
559 * Disable the transmitter.
560 * This is mandatory when DMA is used, otherwise the DMA buffer
561 * is fully transmitted.
562 */
563 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
564 atmel_port->tx_stopped = true;
565
566 /* Disable interrupts */
567 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
568
569 if (atmel_uart_is_half_duplex(port))
570 if (!atomic_read(&atmel_port->tasklet_shutdown))
571 atmel_start_rx(port);
572
573}
574
575/*
576 * Start transmitting.
577 */
578static void atmel_start_tx(struct uart_port *port)
579{
580 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
581
582 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
583 & ATMEL_PDC_TXTEN))
584 /* The transmitter is already running. Yes, we
585 really need this.*/
586 return;
587
588 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
589 if (atmel_uart_is_half_duplex(port))
590 atmel_stop_rx(port);
591
592 if (atmel_use_pdc_tx(port))
593 /* re-enable PDC transmit */
594 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
595
596 /* Enable interrupts */
597 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
598
599 /* re-enable the transmitter */
600 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
601 atmel_port->tx_stopped = false;
602}
603
604/*
605 * start receiving - port is in process of being opened.
606 */
607static void atmel_start_rx(struct uart_port *port)
608{
609 /* reset status and receiver */
610 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
611
612 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
613
614 if (atmel_use_pdc_rx(port)) {
615 /* enable PDC controller */
616 atmel_uart_writel(port, ATMEL_US_IER,
617 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
618 port->read_status_mask);
619 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
620 } else {
621 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
622 }
623}
624
625/*
626 * Stop receiving - port is in process of being closed.
627 */
628static void atmel_stop_rx(struct uart_port *port)
629{
630 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
631
632 if (atmel_use_pdc_rx(port)) {
633 /* disable PDC receive */
634 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
635 atmel_uart_writel(port, ATMEL_US_IDR,
636 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
637 port->read_status_mask);
638 } else {
639 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
640 }
641}
642
643/*
644 * Enable modem status interrupts
645 */
646static void atmel_enable_ms(struct uart_port *port)
647{
648 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
649 uint32_t ier = 0;
650
651 /*
652 * Interrupt should not be enabled twice
653 */
654 if (atmel_port->ms_irq_enabled)
655 return;
656
657 atmel_port->ms_irq_enabled = true;
658
659 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
660 ier |= ATMEL_US_CTSIC;
661
662 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
663 ier |= ATMEL_US_DSRIC;
664
665 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
666 ier |= ATMEL_US_RIIC;
667
668 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
669 ier |= ATMEL_US_DCDIC;
670
671 atmel_uart_writel(port, ATMEL_US_IER, ier);
672
673 mctrl_gpio_enable_ms(atmel_port->gpios);
674}
675
676/*
677 * Disable modem status interrupts
678 */
679static void atmel_disable_ms(struct uart_port *port)
680{
681 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
682 uint32_t idr = 0;
683
684 /*
685 * Interrupt should not be disabled twice
686 */
687 if (!atmel_port->ms_irq_enabled)
688 return;
689
690 atmel_port->ms_irq_enabled = false;
691
692 mctrl_gpio_disable_ms(atmel_port->gpios);
693
694 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
695 idr |= ATMEL_US_CTSIC;
696
697 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
698 idr |= ATMEL_US_DSRIC;
699
700 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
701 idr |= ATMEL_US_RIIC;
702
703 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
704 idr |= ATMEL_US_DCDIC;
705
706 atmel_uart_writel(port, ATMEL_US_IDR, idr);
707}
708
709/*
710 * Control the transmission of a break signal
711 */
712static void atmel_break_ctl(struct uart_port *port, int break_state)
713{
714 if (break_state != 0)
715 /* start break */
716 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
717 else
718 /* stop break */
719 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
720}
721
722/*
723 * Stores the incoming character in the ring buffer
724 */
725static void
726atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
727 unsigned int ch)
728{
729 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
730 struct circ_buf *ring = &atmel_port->rx_ring;
731 struct atmel_uart_char *c;
732
733 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
734 /* Buffer overflow, ignore char */
735 return;
736
737 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
738 c->status = status;
739 c->ch = ch;
740
741 /* Make sure the character is stored before we update head. */
742 smp_wmb();
743
744 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
745}
746
747/*
748 * Deal with parity, framing and overrun errors.
749 */
750static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
751{
752 /* clear error */
753 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
754
755 if (status & ATMEL_US_RXBRK) {
756 /* ignore side-effect */
757 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
758 port->icount.brk++;
759 }
760 if (status & ATMEL_US_PARE)
761 port->icount.parity++;
762 if (status & ATMEL_US_FRAME)
763 port->icount.frame++;
764 if (status & ATMEL_US_OVRE)
765 port->icount.overrun++;
766}
767
768/*
769 * Characters received (called from interrupt handler)
770 */
771static void atmel_rx_chars(struct uart_port *port)
772{
773 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
774 unsigned int status, ch;
775
776 status = atmel_uart_readl(port, ATMEL_US_CSR);
777 while (status & ATMEL_US_RXRDY) {
778 ch = atmel_uart_read_char(port);
779
780 /*
781 * note that the error handling code is
782 * out of the main execution path
783 */
784 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
785 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
786 || atmel_port->break_active)) {
787
788 /* clear error */
789 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
790
791 if (status & ATMEL_US_RXBRK
792 && !atmel_port->break_active) {
793 atmel_port->break_active = 1;
794 atmel_uart_writel(port, ATMEL_US_IER,
795 ATMEL_US_RXBRK);
796 } else {
797 /*
798 * This is either the end-of-break
799 * condition or we've received at
800 * least one character without RXBRK
801 * being set. In both cases, the next
802 * RXBRK will indicate start-of-break.
803 */
804 atmel_uart_writel(port, ATMEL_US_IDR,
805 ATMEL_US_RXBRK);
806 status &= ~ATMEL_US_RXBRK;
807 atmel_port->break_active = 0;
808 }
809 }
810
811 atmel_buffer_rx_char(port, status, ch);
812 status = atmel_uart_readl(port, ATMEL_US_CSR);
813 }
814
815 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
816}
817
818/*
819 * Transmit characters (called from tasklet with TXRDY interrupt
820 * disabled)
821 */
822static void atmel_tx_chars(struct uart_port *port)
823{
824 struct circ_buf *xmit = &port->state->xmit;
825 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
826
827 if (port->x_char &&
828 (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) {
829 atmel_uart_write_char(port, port->x_char);
830 port->icount.tx++;
831 port->x_char = 0;
832 }
833 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
834 return;
835
836 while (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY) {
837 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
838 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
839 port->icount.tx++;
840 if (uart_circ_empty(xmit))
841 break;
842 }
843
844 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
845 uart_write_wakeup(port);
846
847 if (!uart_circ_empty(xmit)) {
848 /* we still have characters to transmit, so we should continue
849 * transmitting them when TX is ready, regardless of
850 * mode or duplexity
851 */
852 atmel_port->tx_done_mask |= ATMEL_US_TXRDY;
853
854 /* Enable interrupts */
855 atmel_uart_writel(port, ATMEL_US_IER,
856 atmel_port->tx_done_mask);
857 } else {
858 if (atmel_uart_is_half_duplex(port))
859 atmel_port->tx_done_mask &= ~ATMEL_US_TXRDY;
860 }
861}
862
863static void atmel_complete_tx_dma(void *arg)
864{
865 struct atmel_uart_port *atmel_port = arg;
866 struct uart_port *port = &atmel_port->uart;
867 struct circ_buf *xmit = &port->state->xmit;
868 struct dma_chan *chan = atmel_port->chan_tx;
869 unsigned long flags;
870
871 spin_lock_irqsave(&port->lock, flags);
872
873 if (chan)
874 dmaengine_terminate_all(chan);
875 xmit->tail += atmel_port->tx_len;
876 xmit->tail &= UART_XMIT_SIZE - 1;
877
878 port->icount.tx += atmel_port->tx_len;
879
880 spin_lock_irq(&atmel_port->lock_tx);
881 async_tx_ack(atmel_port->desc_tx);
882 atmel_port->cookie_tx = -EINVAL;
883 atmel_port->desc_tx = NULL;
884 spin_unlock_irq(&atmel_port->lock_tx);
885
886 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
887 uart_write_wakeup(port);
888
889 /*
890 * xmit is a circular buffer so, if we have just send data from
891 * xmit->tail to the end of xmit->buf, now we have to transmit the
892 * remaining data from the beginning of xmit->buf to xmit->head.
893 */
894 if (!uart_circ_empty(xmit))
895 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
896 else if (atmel_uart_is_half_duplex(port)) {
897 /*
898 * DMA done, re-enable TXEMPTY and signal that we can stop
899 * TX and start RX for RS485
900 */
901 atmel_port->hd_start_rx = true;
902 atmel_uart_writel(port, ATMEL_US_IER,
903 atmel_port->tx_done_mask);
904 }
905
906 spin_unlock_irqrestore(&port->lock, flags);
907}
908
909static void atmel_release_tx_dma(struct uart_port *port)
910{
911 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
912 struct dma_chan *chan = atmel_port->chan_tx;
913
914 if (chan) {
915 dmaengine_terminate_all(chan);
916 dma_release_channel(chan);
917 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
918 DMA_TO_DEVICE);
919 }
920
921 atmel_port->desc_tx = NULL;
922 atmel_port->chan_tx = NULL;
923 atmel_port->cookie_tx = -EINVAL;
924}
925
926/*
927 * Called from tasklet with TXRDY interrupt is disabled.
928 */
929static void atmel_tx_dma(struct uart_port *port)
930{
931 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
932 struct circ_buf *xmit = &port->state->xmit;
933 struct dma_chan *chan = atmel_port->chan_tx;
934 struct dma_async_tx_descriptor *desc;
935 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
936 unsigned int tx_len, part1_len, part2_len, sg_len;
937 dma_addr_t phys_addr;
938
939 /* Make sure we have an idle channel */
940 if (atmel_port->desc_tx != NULL)
941 return;
942
943 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
944 /*
945 * DMA is idle now.
946 * Port xmit buffer is already mapped,
947 * and it is one page... Just adjust
948 * offsets and lengths. Since it is a circular buffer,
949 * we have to transmit till the end, and then the rest.
950 * Take the port lock to get a
951 * consistent xmit buffer state.
952 */
953 tx_len = CIRC_CNT_TO_END(xmit->head,
954 xmit->tail,
955 UART_XMIT_SIZE);
956
957 if (atmel_port->fifo_size) {
958 /* multi data mode */
959 part1_len = (tx_len & ~0x3); /* DWORD access */
960 part2_len = (tx_len & 0x3); /* BYTE access */
961 } else {
962 /* single data (legacy) mode */
963 part1_len = 0;
964 part2_len = tx_len; /* BYTE access only */
965 }
966
967 sg_init_table(sgl, 2);
968 sg_len = 0;
969 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
970 if (part1_len) {
971 sg = &sgl[sg_len++];
972 sg_dma_address(sg) = phys_addr;
973 sg_dma_len(sg) = part1_len;
974
975 phys_addr += part1_len;
976 }
977
978 if (part2_len) {
979 sg = &sgl[sg_len++];
980 sg_dma_address(sg) = phys_addr;
981 sg_dma_len(sg) = part2_len;
982 }
983
984 /*
985 * save tx_len so atmel_complete_tx_dma() will increase
986 * xmit->tail correctly
987 */
988 atmel_port->tx_len = tx_len;
989
990 desc = dmaengine_prep_slave_sg(chan,
991 sgl,
992 sg_len,
993 DMA_MEM_TO_DEV,
994 DMA_PREP_INTERRUPT |
995 DMA_CTRL_ACK);
996 if (!desc) {
997 dev_err(port->dev, "Failed to send via dma!\n");
998 return;
999 }
1000
1001 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
1002
1003 atmel_port->desc_tx = desc;
1004 desc->callback = atmel_complete_tx_dma;
1005 desc->callback_param = atmel_port;
1006 atmel_port->cookie_tx = dmaengine_submit(desc);
1007 }
1008
1009 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1010 uart_write_wakeup(port);
1011}
1012
1013static int atmel_prepare_tx_dma(struct uart_port *port)
1014{
1015 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1016 struct device *mfd_dev = port->dev->parent;
1017 dma_cap_mask_t mask;
1018 struct dma_slave_config config;
1019 int ret, nent;
1020
1021 dma_cap_zero(mask);
1022 dma_cap_set(DMA_SLAVE, mask);
1023
1024 atmel_port->chan_tx = dma_request_slave_channel(mfd_dev, "tx");
1025 if (atmel_port->chan_tx == NULL)
1026 goto chan_err;
1027 dev_info(port->dev, "using %s for tx DMA transfers\n",
1028 dma_chan_name(atmel_port->chan_tx));
1029
1030 spin_lock_init(&atmel_port->lock_tx);
1031 sg_init_table(&atmel_port->sg_tx, 1);
1032 /* UART circular tx buffer is an aligned page. */
1033 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
1034 sg_set_page(&atmel_port->sg_tx,
1035 virt_to_page(port->state->xmit.buf),
1036 UART_XMIT_SIZE,
1037 offset_in_page(port->state->xmit.buf));
1038 nent = dma_map_sg(port->dev,
1039 &atmel_port->sg_tx,
1040 1,
1041 DMA_TO_DEVICE);
1042
1043 if (!nent) {
1044 dev_dbg(port->dev, "need to release resource of dma\n");
1045 goto chan_err;
1046 } else {
1047 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1048 sg_dma_len(&atmel_port->sg_tx),
1049 port->state->xmit.buf,
1050 &sg_dma_address(&atmel_port->sg_tx));
1051 }
1052
1053 /* Configure the slave DMA */
1054 memset(&config, 0, sizeof(config));
1055 config.direction = DMA_MEM_TO_DEV;
1056 config.dst_addr_width = (atmel_port->fifo_size) ?
1057 DMA_SLAVE_BUSWIDTH_4_BYTES :
1058 DMA_SLAVE_BUSWIDTH_1_BYTE;
1059 config.dst_addr = port->mapbase + ATMEL_US_THR;
1060 config.dst_maxburst = 1;
1061
1062 ret = dmaengine_slave_config(atmel_port->chan_tx,
1063 &config);
1064 if (ret) {
1065 dev_err(port->dev, "DMA tx slave configuration failed\n");
1066 goto chan_err;
1067 }
1068
1069 return 0;
1070
1071chan_err:
1072 dev_err(port->dev, "TX channel not available, switch to pio\n");
1073 atmel_port->use_dma_tx = false;
1074 if (atmel_port->chan_tx)
1075 atmel_release_tx_dma(port);
1076 return -EINVAL;
1077}
1078
1079static void atmel_complete_rx_dma(void *arg)
1080{
1081 struct uart_port *port = arg;
1082 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1083
1084 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1085}
1086
1087static void atmel_release_rx_dma(struct uart_port *port)
1088{
1089 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1090 struct dma_chan *chan = atmel_port->chan_rx;
1091
1092 if (chan) {
1093 dmaengine_terminate_all(chan);
1094 dma_release_channel(chan);
1095 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1096 DMA_FROM_DEVICE);
1097 }
1098
1099 atmel_port->desc_rx = NULL;
1100 atmel_port->chan_rx = NULL;
1101 atmel_port->cookie_rx = -EINVAL;
1102}
1103
1104static void atmel_rx_from_dma(struct uart_port *port)
1105{
1106 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1107 struct tty_port *tport = &port->state->port;
1108 struct circ_buf *ring = &atmel_port->rx_ring;
1109 struct dma_chan *chan = atmel_port->chan_rx;
1110 struct dma_tx_state state;
1111 enum dma_status dmastat;
1112 size_t count;
1113
1114
1115 /* Reset the UART timeout early so that we don't miss one */
1116 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1117 dmastat = dmaengine_tx_status(chan,
1118 atmel_port->cookie_rx,
1119 &state);
1120 /* Restart a new tasklet if DMA status is error */
1121 if (dmastat == DMA_ERROR) {
1122 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1123 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1124 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1125 return;
1126 }
1127
1128 /* CPU claims ownership of RX DMA buffer */
1129 dma_sync_sg_for_cpu(port->dev,
1130 &atmel_port->sg_rx,
1131 1,
1132 DMA_FROM_DEVICE);
1133
1134 /*
1135 * ring->head points to the end of data already written by the DMA.
1136 * ring->tail points to the beginning of data to be read by the
1137 * framework.
1138 * The current transfer size should not be larger than the dma buffer
1139 * length.
1140 */
1141 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1142 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1143 /*
1144 * At this point ring->head may point to the first byte right after the
1145 * last byte of the dma buffer:
1146 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1147 *
1148 * However ring->tail must always points inside the dma buffer:
1149 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1150 *
1151 * Since we use a ring buffer, we have to handle the case
1152 * where head is lower than tail. In such a case, we first read from
1153 * tail to the end of the buffer then reset tail.
1154 */
1155 if (ring->head < ring->tail) {
1156 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1157
1158 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1159 ring->tail = 0;
1160 port->icount.rx += count;
1161 }
1162
1163 /* Finally we read data from tail to head */
1164 if (ring->tail < ring->head) {
1165 count = ring->head - ring->tail;
1166
1167 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1168 /* Wrap ring->head if needed */
1169 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1170 ring->head = 0;
1171 ring->tail = ring->head;
1172 port->icount.rx += count;
1173 }
1174
1175 /* USART retreives ownership of RX DMA buffer */
1176 dma_sync_sg_for_device(port->dev,
1177 &atmel_port->sg_rx,
1178 1,
1179 DMA_FROM_DEVICE);
1180
1181 tty_flip_buffer_push(tport);
1182
1183 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1184}
1185
1186static int atmel_prepare_rx_dma(struct uart_port *port)
1187{
1188 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1189 struct device *mfd_dev = port->dev->parent;
1190 struct dma_async_tx_descriptor *desc;
1191 dma_cap_mask_t mask;
1192 struct dma_slave_config config;
1193 struct circ_buf *ring;
1194 int ret, nent;
1195
1196 ring = &atmel_port->rx_ring;
1197
1198 dma_cap_zero(mask);
1199 dma_cap_set(DMA_CYCLIC, mask);
1200
1201 atmel_port->chan_rx = dma_request_slave_channel(mfd_dev, "rx");
1202 if (atmel_port->chan_rx == NULL)
1203 goto chan_err;
1204 dev_info(port->dev, "using %s for rx DMA transfers\n",
1205 dma_chan_name(atmel_port->chan_rx));
1206
1207 spin_lock_init(&atmel_port->lock_rx);
1208 sg_init_table(&atmel_port->sg_rx, 1);
1209 /* UART circular rx buffer is an aligned page. */
1210 BUG_ON(!PAGE_ALIGNED(ring->buf));
1211 sg_set_page(&atmel_port->sg_rx,
1212 virt_to_page(ring->buf),
1213 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1214 offset_in_page(ring->buf));
1215 nent = dma_map_sg(port->dev,
1216 &atmel_port->sg_rx,
1217 1,
1218 DMA_FROM_DEVICE);
1219
1220 if (!nent) {
1221 dev_dbg(port->dev, "need to release resource of dma\n");
1222 goto chan_err;
1223 } else {
1224 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1225 sg_dma_len(&atmel_port->sg_rx),
1226 ring->buf,
1227 &sg_dma_address(&atmel_port->sg_rx));
1228 }
1229
1230 /* Configure the slave DMA */
1231 memset(&config, 0, sizeof(config));
1232 config.direction = DMA_DEV_TO_MEM;
1233 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1234 config.src_addr = port->mapbase + ATMEL_US_RHR;
1235 config.src_maxburst = 1;
1236
1237 ret = dmaengine_slave_config(atmel_port->chan_rx,
1238 &config);
1239 if (ret) {
1240 dev_err(port->dev, "DMA rx slave configuration failed\n");
1241 goto chan_err;
1242 }
1243 /*
1244 * Prepare a cyclic dma transfer, assign 2 descriptors,
1245 * each one is half ring buffer size
1246 */
1247 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1248 sg_dma_address(&atmel_port->sg_rx),
1249 sg_dma_len(&atmel_port->sg_rx),
1250 sg_dma_len(&atmel_port->sg_rx)/2,
1251 DMA_DEV_TO_MEM,
1252 DMA_PREP_INTERRUPT);
1253 if (!desc) {
1254 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1255 goto chan_err;
1256 }
1257 desc->callback = atmel_complete_rx_dma;
1258 desc->callback_param = port;
1259 atmel_port->desc_rx = desc;
1260 atmel_port->cookie_rx = dmaengine_submit(desc);
1261
1262 return 0;
1263
1264chan_err:
1265 dev_err(port->dev, "RX channel not available, switch to pio\n");
1266 atmel_port->use_dma_rx = false;
1267 if (atmel_port->chan_rx)
1268 atmel_release_rx_dma(port);
1269 return -EINVAL;
1270}
1271
1272static void atmel_uart_timer_callback(struct timer_list *t)
1273{
1274 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1275 uart_timer);
1276 struct uart_port *port = &atmel_port->uart;
1277
1278 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1279 tasklet_schedule(&atmel_port->tasklet_rx);
1280 mod_timer(&atmel_port->uart_timer,
1281 jiffies + uart_poll_timeout(port));
1282 }
1283}
1284
1285/*
1286 * receive interrupt handler.
1287 */
1288static void
1289atmel_handle_receive(struct uart_port *port, unsigned int pending)
1290{
1291 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1292
1293 if (atmel_use_pdc_rx(port)) {
1294 /*
1295 * PDC receive. Just schedule the tasklet and let it
1296 * figure out the details.
1297 *
1298 * TODO: We're not handling error flags correctly at
1299 * the moment.
1300 */
1301 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1302 atmel_uart_writel(port, ATMEL_US_IDR,
1303 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1304 atmel_tasklet_schedule(atmel_port,
1305 &atmel_port->tasklet_rx);
1306 }
1307
1308 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1309 ATMEL_US_FRAME | ATMEL_US_PARE))
1310 atmel_pdc_rxerr(port, pending);
1311 }
1312
1313 if (atmel_use_dma_rx(port)) {
1314 if (pending & ATMEL_US_TIMEOUT) {
1315 atmel_uart_writel(port, ATMEL_US_IDR,
1316 ATMEL_US_TIMEOUT);
1317 atmel_tasklet_schedule(atmel_port,
1318 &atmel_port->tasklet_rx);
1319 }
1320 }
1321
1322 /* Interrupt receive */
1323 if (pending & ATMEL_US_RXRDY)
1324 atmel_rx_chars(port);
1325 else if (pending & ATMEL_US_RXBRK) {
1326 /*
1327 * End of break detected. If it came along with a
1328 * character, atmel_rx_chars will handle it.
1329 */
1330 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1331 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1332 atmel_port->break_active = 0;
1333 }
1334}
1335
1336/*
1337 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1338 */
1339static void
1340atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1341{
1342 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1343
1344 if (pending & atmel_port->tx_done_mask) {
1345 atmel_uart_writel(port, ATMEL_US_IDR,
1346 atmel_port->tx_done_mask);
1347
1348 /* Start RX if flag was set and FIFO is empty */
1349 if (atmel_port->hd_start_rx) {
1350 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1351 & ATMEL_US_TXEMPTY))
1352 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1353
1354 atmel_port->hd_start_rx = false;
1355 atmel_start_rx(port);
1356 }
1357
1358 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1359 }
1360}
1361
1362/*
1363 * status flags interrupt handler.
1364 */
1365static void
1366atmel_handle_status(struct uart_port *port, unsigned int pending,
1367 unsigned int status)
1368{
1369 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1370 unsigned int status_change;
1371
1372 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1373 | ATMEL_US_CTSIC)) {
1374 status_change = status ^ atmel_port->irq_status_prev;
1375 atmel_port->irq_status_prev = status;
1376
1377 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1378 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1379 /* TODO: All reads to CSR will clear these interrupts! */
1380 if (status_change & ATMEL_US_RI)
1381 port->icount.rng++;
1382 if (status_change & ATMEL_US_DSR)
1383 port->icount.dsr++;
1384 if (status_change & ATMEL_US_DCD)
1385 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1386 if (status_change & ATMEL_US_CTS)
1387 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1388
1389 wake_up_interruptible(&port->state->port.delta_msr_wait);
1390 }
1391 }
1392
1393 if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION))
1394 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending);
1395}
1396
1397/*
1398 * Interrupt handler
1399 */
1400static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1401{
1402 struct uart_port *port = dev_id;
1403 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1404 unsigned int status, pending, mask, pass_counter = 0;
1405
1406 spin_lock(&atmel_port->lock_suspended);
1407
1408 do {
1409 status = atmel_uart_readl(port, ATMEL_US_CSR);
1410 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1411 pending = status & mask;
1412 if (!pending)
1413 break;
1414
1415 if (atmel_port->suspended) {
1416 atmel_port->pending |= pending;
1417 atmel_port->pending_status = status;
1418 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1419 pm_system_wakeup();
1420 break;
1421 }
1422
1423 atmel_handle_receive(port, pending);
1424 atmel_handle_status(port, pending, status);
1425 atmel_handle_transmit(port, pending);
1426 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1427
1428 spin_unlock(&atmel_port->lock_suspended);
1429
1430 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1431}
1432
1433static void atmel_release_tx_pdc(struct uart_port *port)
1434{
1435 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1436 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1437
1438 dma_unmap_single(port->dev,
1439 pdc->dma_addr,
1440 pdc->dma_size,
1441 DMA_TO_DEVICE);
1442}
1443
1444/*
1445 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1446 */
1447static void atmel_tx_pdc(struct uart_port *port)
1448{
1449 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1450 struct circ_buf *xmit = &port->state->xmit;
1451 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1452 int count;
1453
1454 /* nothing left to transmit? */
1455 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1456 return;
1457
1458 xmit->tail += pdc->ofs;
1459 xmit->tail &= UART_XMIT_SIZE - 1;
1460
1461 port->icount.tx += pdc->ofs;
1462 pdc->ofs = 0;
1463
1464 /* more to transmit - setup next transfer */
1465
1466 /* disable PDC transmit */
1467 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1468
1469 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1470 dma_sync_single_for_device(port->dev,
1471 pdc->dma_addr,
1472 pdc->dma_size,
1473 DMA_TO_DEVICE);
1474
1475 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1476 pdc->ofs = count;
1477
1478 atmel_uart_writel(port, ATMEL_PDC_TPR,
1479 pdc->dma_addr + xmit->tail);
1480 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1481 /* re-enable PDC transmit */
1482 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1483 /* Enable interrupts */
1484 atmel_uart_writel(port, ATMEL_US_IER,
1485 atmel_port->tx_done_mask);
1486 } else {
1487 if (atmel_uart_is_half_duplex(port)) {
1488 /* DMA done, stop TX, start RX for RS485 */
1489 atmel_start_rx(port);
1490 }
1491 }
1492
1493 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1494 uart_write_wakeup(port);
1495}
1496
1497static int atmel_prepare_tx_pdc(struct uart_port *port)
1498{
1499 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1500 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1501 struct circ_buf *xmit = &port->state->xmit;
1502
1503 pdc->buf = xmit->buf;
1504 pdc->dma_addr = dma_map_single(port->dev,
1505 pdc->buf,
1506 UART_XMIT_SIZE,
1507 DMA_TO_DEVICE);
1508 pdc->dma_size = UART_XMIT_SIZE;
1509 pdc->ofs = 0;
1510
1511 return 0;
1512}
1513
1514static void atmel_rx_from_ring(struct uart_port *port)
1515{
1516 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1517 struct circ_buf *ring = &atmel_port->rx_ring;
1518 unsigned int flg;
1519 unsigned int status;
1520
1521 while (ring->head != ring->tail) {
1522 struct atmel_uart_char c;
1523
1524 /* Make sure c is loaded after head. */
1525 smp_rmb();
1526
1527 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1528
1529 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1530
1531 port->icount.rx++;
1532 status = c.status;
1533 flg = TTY_NORMAL;
1534
1535 /*
1536 * note that the error handling code is
1537 * out of the main execution path
1538 */
1539 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1540 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1541 if (status & ATMEL_US_RXBRK) {
1542 /* ignore side-effect */
1543 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1544
1545 port->icount.brk++;
1546 if (uart_handle_break(port))
1547 continue;
1548 }
1549 if (status & ATMEL_US_PARE)
1550 port->icount.parity++;
1551 if (status & ATMEL_US_FRAME)
1552 port->icount.frame++;
1553 if (status & ATMEL_US_OVRE)
1554 port->icount.overrun++;
1555
1556 status &= port->read_status_mask;
1557
1558 if (status & ATMEL_US_RXBRK)
1559 flg = TTY_BREAK;
1560 else if (status & ATMEL_US_PARE)
1561 flg = TTY_PARITY;
1562 else if (status & ATMEL_US_FRAME)
1563 flg = TTY_FRAME;
1564 }
1565
1566
1567 if (uart_handle_sysrq_char(port, c.ch))
1568 continue;
1569
1570 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1571 }
1572
1573 tty_flip_buffer_push(&port->state->port);
1574}
1575
1576static void atmel_release_rx_pdc(struct uart_port *port)
1577{
1578 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1579 int i;
1580
1581 for (i = 0; i < 2; i++) {
1582 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1583
1584 dma_unmap_single(port->dev,
1585 pdc->dma_addr,
1586 pdc->dma_size,
1587 DMA_FROM_DEVICE);
1588 kfree(pdc->buf);
1589 }
1590}
1591
1592static void atmel_rx_from_pdc(struct uart_port *port)
1593{
1594 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1595 struct tty_port *tport = &port->state->port;
1596 struct atmel_dma_buffer *pdc;
1597 int rx_idx = atmel_port->pdc_rx_idx;
1598 unsigned int head;
1599 unsigned int tail;
1600 unsigned int count;
1601
1602 do {
1603 /* Reset the UART timeout early so that we don't miss one */
1604 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1605
1606 pdc = &atmel_port->pdc_rx[rx_idx];
1607 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1608 tail = pdc->ofs;
1609
1610 /* If the PDC has switched buffers, RPR won't contain
1611 * any address within the current buffer. Since head
1612 * is unsigned, we just need a one-way comparison to
1613 * find out.
1614 *
1615 * In this case, we just need to consume the entire
1616 * buffer and resubmit it for DMA. This will clear the
1617 * ENDRX bit as well, so that we can safely re-enable
1618 * all interrupts below.
1619 */
1620 head = min(head, pdc->dma_size);
1621
1622 if (likely(head != tail)) {
1623 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1624 pdc->dma_size, DMA_FROM_DEVICE);
1625
1626 /*
1627 * head will only wrap around when we recycle
1628 * the DMA buffer, and when that happens, we
1629 * explicitly set tail to 0. So head will
1630 * always be greater than tail.
1631 */
1632 count = head - tail;
1633
1634 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1635 count);
1636
1637 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1638 pdc->dma_size, DMA_FROM_DEVICE);
1639
1640 port->icount.rx += count;
1641 pdc->ofs = head;
1642 }
1643
1644 /*
1645 * If the current buffer is full, we need to check if
1646 * the next one contains any additional data.
1647 */
1648 if (head >= pdc->dma_size) {
1649 pdc->ofs = 0;
1650 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1651 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1652
1653 rx_idx = !rx_idx;
1654 atmel_port->pdc_rx_idx = rx_idx;
1655 }
1656 } while (head >= pdc->dma_size);
1657
1658 tty_flip_buffer_push(tport);
1659
1660 atmel_uart_writel(port, ATMEL_US_IER,
1661 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1662}
1663
1664static int atmel_prepare_rx_pdc(struct uart_port *port)
1665{
1666 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1667 int i;
1668
1669 for (i = 0; i < 2; i++) {
1670 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1671
1672 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1673 if (pdc->buf == NULL) {
1674 if (i != 0) {
1675 dma_unmap_single(port->dev,
1676 atmel_port->pdc_rx[0].dma_addr,
1677 PDC_BUFFER_SIZE,
1678 DMA_FROM_DEVICE);
1679 kfree(atmel_port->pdc_rx[0].buf);
1680 }
1681 atmel_port->use_pdc_rx = false;
1682 return -ENOMEM;
1683 }
1684 pdc->dma_addr = dma_map_single(port->dev,
1685 pdc->buf,
1686 PDC_BUFFER_SIZE,
1687 DMA_FROM_DEVICE);
1688 pdc->dma_size = PDC_BUFFER_SIZE;
1689 pdc->ofs = 0;
1690 }
1691
1692 atmel_port->pdc_rx_idx = 0;
1693
1694 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1695 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1696
1697 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1698 atmel_port->pdc_rx[1].dma_addr);
1699 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1700
1701 return 0;
1702}
1703
1704/*
1705 * tasklet handling tty stuff outside the interrupt handler.
1706 */
1707static void atmel_tasklet_rx_func(struct tasklet_struct *t)
1708{
1709 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1710 tasklet_rx);
1711 struct uart_port *port = &atmel_port->uart;
1712
1713 /* The interrupt handler does not take the lock */
1714 spin_lock(&port->lock);
1715 atmel_port->schedule_rx(port);
1716 spin_unlock(&port->lock);
1717}
1718
1719static void atmel_tasklet_tx_func(struct tasklet_struct *t)
1720{
1721 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1722 tasklet_tx);
1723 struct uart_port *port = &atmel_port->uart;
1724
1725 /* The interrupt handler does not take the lock */
1726 spin_lock(&port->lock);
1727 atmel_port->schedule_tx(port);
1728 spin_unlock(&port->lock);
1729}
1730
1731static void atmel_init_property(struct atmel_uart_port *atmel_port,
1732 struct platform_device *pdev)
1733{
1734 struct device_node *np = pdev->dev.of_node;
1735
1736 /* DMA/PDC usage specification */
1737 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1738 if (of_property_read_bool(np, "dmas")) {
1739 atmel_port->use_dma_rx = true;
1740 atmel_port->use_pdc_rx = false;
1741 } else {
1742 atmel_port->use_dma_rx = false;
1743 atmel_port->use_pdc_rx = true;
1744 }
1745 } else {
1746 atmel_port->use_dma_rx = false;
1747 atmel_port->use_pdc_rx = false;
1748 }
1749
1750 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1751 if (of_property_read_bool(np, "dmas")) {
1752 atmel_port->use_dma_tx = true;
1753 atmel_port->use_pdc_tx = false;
1754 } else {
1755 atmel_port->use_dma_tx = false;
1756 atmel_port->use_pdc_tx = true;
1757 }
1758 } else {
1759 atmel_port->use_dma_tx = false;
1760 atmel_port->use_pdc_tx = false;
1761 }
1762}
1763
1764static void atmel_set_ops(struct uart_port *port)
1765{
1766 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1767
1768 if (atmel_use_dma_rx(port)) {
1769 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1770 atmel_port->schedule_rx = &atmel_rx_from_dma;
1771 atmel_port->release_rx = &atmel_release_rx_dma;
1772 } else if (atmel_use_pdc_rx(port)) {
1773 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1774 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1775 atmel_port->release_rx = &atmel_release_rx_pdc;
1776 } else {
1777 atmel_port->prepare_rx = NULL;
1778 atmel_port->schedule_rx = &atmel_rx_from_ring;
1779 atmel_port->release_rx = NULL;
1780 }
1781
1782 if (atmel_use_dma_tx(port)) {
1783 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1784 atmel_port->schedule_tx = &atmel_tx_dma;
1785 atmel_port->release_tx = &atmel_release_tx_dma;
1786 } else if (atmel_use_pdc_tx(port)) {
1787 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1788 atmel_port->schedule_tx = &atmel_tx_pdc;
1789 atmel_port->release_tx = &atmel_release_tx_pdc;
1790 } else {
1791 atmel_port->prepare_tx = NULL;
1792 atmel_port->schedule_tx = &atmel_tx_chars;
1793 atmel_port->release_tx = NULL;
1794 }
1795}
1796
1797/*
1798 * Get ip name usart or uart
1799 */
1800static void atmel_get_ip_name(struct uart_port *port)
1801{
1802 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1803 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1804 u32 version;
1805 u32 usart, dbgu_uart, new_uart;
1806 /* ASCII decoding for IP version */
1807 usart = 0x55534152; /* USAR(T) */
1808 dbgu_uart = 0x44424755; /* DBGU */
1809 new_uart = 0x55415254; /* UART */
1810
1811 /*
1812 * Only USART devices from at91sam9260 SOC implement fractional
1813 * baudrate. It is available for all asynchronous modes, with the
1814 * following restriction: the sampling clock's duty cycle is not
1815 * constant.
1816 */
1817 atmel_port->has_frac_baudrate = false;
1818 atmel_port->has_hw_timer = false;
1819
1820 if (name == new_uart) {
1821 dev_dbg(port->dev, "Uart with hw timer");
1822 atmel_port->has_hw_timer = true;
1823 atmel_port->rtor = ATMEL_UA_RTOR;
1824 } else if (name == usart) {
1825 dev_dbg(port->dev, "Usart\n");
1826 atmel_port->has_frac_baudrate = true;
1827 atmel_port->has_hw_timer = true;
1828 atmel_port->rtor = ATMEL_US_RTOR;
1829 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1830 switch (version) {
1831 case 0x814: /* sama5d2 */
1832 fallthrough;
1833 case 0x701: /* sama5d4 */
1834 atmel_port->fidi_min = 3;
1835 atmel_port->fidi_max = 65535;
1836 break;
1837 case 0x502: /* sam9x5, sama5d3 */
1838 atmel_port->fidi_min = 3;
1839 atmel_port->fidi_max = 2047;
1840 break;
1841 default:
1842 atmel_port->fidi_min = 1;
1843 atmel_port->fidi_max = 2047;
1844 }
1845 } else if (name == dbgu_uart) {
1846 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1847 } else {
1848 /* fallback for older SoCs: use version field */
1849 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1850 switch (version) {
1851 case 0x302:
1852 case 0x10213:
1853 case 0x10302:
1854 dev_dbg(port->dev, "This version is usart\n");
1855 atmel_port->has_frac_baudrate = true;
1856 atmel_port->has_hw_timer = true;
1857 atmel_port->rtor = ATMEL_US_RTOR;
1858 break;
1859 case 0x203:
1860 case 0x10202:
1861 dev_dbg(port->dev, "This version is uart\n");
1862 break;
1863 default:
1864 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1865 }
1866 }
1867}
1868
1869/*
1870 * Perform initialization and enable port for reception
1871 */
1872static int atmel_startup(struct uart_port *port)
1873{
1874 struct platform_device *pdev = to_platform_device(port->dev);
1875 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1876 int retval;
1877
1878 /*
1879 * Ensure that no interrupts are enabled otherwise when
1880 * request_irq() is called we could get stuck trying to
1881 * handle an unexpected interrupt
1882 */
1883 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1884 atmel_port->ms_irq_enabled = false;
1885
1886 /*
1887 * Allocate the IRQ
1888 */
1889 retval = request_irq(port->irq, atmel_interrupt,
1890 IRQF_SHARED | IRQF_COND_SUSPEND,
1891 dev_name(&pdev->dev), port);
1892 if (retval) {
1893 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1894 return retval;
1895 }
1896
1897 atomic_set(&atmel_port->tasklet_shutdown, 0);
1898 tasklet_setup(&atmel_port->tasklet_rx, atmel_tasklet_rx_func);
1899 tasklet_setup(&atmel_port->tasklet_tx, atmel_tasklet_tx_func);
1900
1901 /*
1902 * Initialize DMA (if necessary)
1903 */
1904 atmel_init_property(atmel_port, pdev);
1905 atmel_set_ops(port);
1906
1907 if (atmel_port->prepare_rx) {
1908 retval = atmel_port->prepare_rx(port);
1909 if (retval < 0)
1910 atmel_set_ops(port);
1911 }
1912
1913 if (atmel_port->prepare_tx) {
1914 retval = atmel_port->prepare_tx(port);
1915 if (retval < 0)
1916 atmel_set_ops(port);
1917 }
1918
1919 /*
1920 * Enable FIFO when available
1921 */
1922 if (atmel_port->fifo_size) {
1923 unsigned int txrdym = ATMEL_US_ONE_DATA;
1924 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1925 unsigned int fmr;
1926
1927 atmel_uart_writel(port, ATMEL_US_CR,
1928 ATMEL_US_FIFOEN |
1929 ATMEL_US_RXFCLR |
1930 ATMEL_US_TXFLCLR);
1931
1932 if (atmel_use_dma_tx(port))
1933 txrdym = ATMEL_US_FOUR_DATA;
1934
1935 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1936 if (atmel_port->rts_high &&
1937 atmel_port->rts_low)
1938 fmr |= ATMEL_US_FRTSC |
1939 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1940 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1941
1942 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1943 }
1944
1945 /* Save current CSR for comparison in atmel_tasklet_func() */
1946 atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR);
1947
1948 /*
1949 * Finally, enable the serial port
1950 */
1951 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1952 /* enable xmit & rcvr */
1953 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1954 atmel_port->tx_stopped = false;
1955
1956 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
1957
1958 if (atmel_use_pdc_rx(port)) {
1959 /* set UART timeout */
1960 if (!atmel_port->has_hw_timer) {
1961 mod_timer(&atmel_port->uart_timer,
1962 jiffies + uart_poll_timeout(port));
1963 /* set USART timeout */
1964 } else {
1965 atmel_uart_writel(port, atmel_port->rtor,
1966 PDC_RX_TIMEOUT);
1967 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1968
1969 atmel_uart_writel(port, ATMEL_US_IER,
1970 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1971 }
1972 /* enable PDC controller */
1973 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1974 } else if (atmel_use_dma_rx(port)) {
1975 /* set UART timeout */
1976 if (!atmel_port->has_hw_timer) {
1977 mod_timer(&atmel_port->uart_timer,
1978 jiffies + uart_poll_timeout(port));
1979 /* set USART timeout */
1980 } else {
1981 atmel_uart_writel(port, atmel_port->rtor,
1982 PDC_RX_TIMEOUT);
1983 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1984
1985 atmel_uart_writel(port, ATMEL_US_IER,
1986 ATMEL_US_TIMEOUT);
1987 }
1988 } else {
1989 /* enable receive only */
1990 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
1991 }
1992
1993 return 0;
1994}
1995
1996/*
1997 * Flush any TX data submitted for DMA. Called when the TX circular
1998 * buffer is reset.
1999 */
2000static void atmel_flush_buffer(struct uart_port *port)
2001{
2002 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2003
2004 if (atmel_use_pdc_tx(port)) {
2005 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
2006 atmel_port->pdc_tx.ofs = 0;
2007 }
2008 /*
2009 * in uart_flush_buffer(), the xmit circular buffer has just
2010 * been cleared, so we have to reset tx_len accordingly.
2011 */
2012 atmel_port->tx_len = 0;
2013}
2014
2015/*
2016 * Disable the port
2017 */
2018static void atmel_shutdown(struct uart_port *port)
2019{
2020 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2021
2022 /* Disable modem control lines interrupts */
2023 atmel_disable_ms(port);
2024
2025 /* Disable interrupts at device level */
2026 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2027
2028 /* Prevent spurious interrupts from scheduling the tasklet */
2029 atomic_inc(&atmel_port->tasklet_shutdown);
2030
2031 /*
2032 * Prevent any tasklets being scheduled during
2033 * cleanup
2034 */
2035 del_timer_sync(&atmel_port->uart_timer);
2036
2037 /* Make sure that no interrupt is on the fly */
2038 synchronize_irq(port->irq);
2039
2040 /*
2041 * Clear out any scheduled tasklets before
2042 * we destroy the buffers
2043 */
2044 tasklet_kill(&atmel_port->tasklet_rx);
2045 tasklet_kill(&atmel_port->tasklet_tx);
2046
2047 /*
2048 * Ensure everything is stopped and
2049 * disable port and break condition.
2050 */
2051 atmel_stop_rx(port);
2052 atmel_stop_tx(port);
2053
2054 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
2055
2056 /*
2057 * Shut-down the DMA.
2058 */
2059 if (atmel_port->release_rx)
2060 atmel_port->release_rx(port);
2061 if (atmel_port->release_tx)
2062 atmel_port->release_tx(port);
2063
2064 /*
2065 * Reset ring buffer pointers
2066 */
2067 atmel_port->rx_ring.head = 0;
2068 atmel_port->rx_ring.tail = 0;
2069
2070 /*
2071 * Free the interrupts
2072 */
2073 free_irq(port->irq, port);
2074
2075 atmel_flush_buffer(port);
2076}
2077
2078/*
2079 * Power / Clock management.
2080 */
2081static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2082 unsigned int oldstate)
2083{
2084 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2085
2086 switch (state) {
2087 case 0:
2088 /*
2089 * Enable the peripheral clock for this serial port.
2090 * This is called on uart_open() or a resume event.
2091 */
2092 clk_prepare_enable(atmel_port->clk);
2093
2094 /* re-enable interrupts if we disabled some on suspend */
2095 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2096 break;
2097 case 3:
2098 /* Back up the interrupt mask and disable all interrupts */
2099 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2100 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2101
2102 /*
2103 * Disable the peripheral clock for this serial port.
2104 * This is called on uart_close() or a suspend event.
2105 */
2106 clk_disable_unprepare(atmel_port->clk);
2107 break;
2108 default:
2109 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2110 }
2111}
2112
2113/*
2114 * Change the port parameters
2115 */
2116static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2117 struct ktermios *old)
2118{
2119 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2120 unsigned long flags;
2121 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2122
2123 /* save the current mode register */
2124 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2125
2126 /* reset the mode, clock divisor, parity, stop bits and data size */
2127 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2128 ATMEL_US_PAR | ATMEL_US_USMODE);
2129
2130 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2131
2132 /* byte size */
2133 switch (termios->c_cflag & CSIZE) {
2134 case CS5:
2135 mode |= ATMEL_US_CHRL_5;
2136 break;
2137 case CS6:
2138 mode |= ATMEL_US_CHRL_6;
2139 break;
2140 case CS7:
2141 mode |= ATMEL_US_CHRL_7;
2142 break;
2143 default:
2144 mode |= ATMEL_US_CHRL_8;
2145 break;
2146 }
2147
2148 /* stop bits */
2149 if (termios->c_cflag & CSTOPB)
2150 mode |= ATMEL_US_NBSTOP_2;
2151
2152 /* parity */
2153 if (termios->c_cflag & PARENB) {
2154 /* Mark or Space parity */
2155 if (termios->c_cflag & CMSPAR) {
2156 if (termios->c_cflag & PARODD)
2157 mode |= ATMEL_US_PAR_MARK;
2158 else
2159 mode |= ATMEL_US_PAR_SPACE;
2160 } else if (termios->c_cflag & PARODD)
2161 mode |= ATMEL_US_PAR_ODD;
2162 else
2163 mode |= ATMEL_US_PAR_EVEN;
2164 } else
2165 mode |= ATMEL_US_PAR_NONE;
2166
2167 spin_lock_irqsave(&port->lock, flags);
2168
2169 port->read_status_mask = ATMEL_US_OVRE;
2170 if (termios->c_iflag & INPCK)
2171 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2172 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2173 port->read_status_mask |= ATMEL_US_RXBRK;
2174
2175 if (atmel_use_pdc_rx(port))
2176 /* need to enable error interrupts */
2177 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2178
2179 /*
2180 * Characters to ignore
2181 */
2182 port->ignore_status_mask = 0;
2183 if (termios->c_iflag & IGNPAR)
2184 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2185 if (termios->c_iflag & IGNBRK) {
2186 port->ignore_status_mask |= ATMEL_US_RXBRK;
2187 /*
2188 * If we're ignoring parity and break indicators,
2189 * ignore overruns too (for real raw support).
2190 */
2191 if (termios->c_iflag & IGNPAR)
2192 port->ignore_status_mask |= ATMEL_US_OVRE;
2193 }
2194 /* TODO: Ignore all characters if CREAD is set.*/
2195
2196 /* update the per-port timeout */
2197 uart_update_timeout(port, termios->c_cflag, baud);
2198
2199 /*
2200 * save/disable interrupts. The tty layer will ensure that the
2201 * transmitter is empty if requested by the caller, so there's
2202 * no need to wait for it here.
2203 */
2204 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2205 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2206
2207 /* disable receiver and transmitter */
2208 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2209 atmel_port->tx_stopped = true;
2210
2211 /* mode */
2212 if (port->rs485.flags & SER_RS485_ENABLED) {
2213 atmel_uart_writel(port, ATMEL_US_TTGR,
2214 port->rs485.delay_rts_after_send);
2215 mode |= ATMEL_US_USMODE_RS485;
2216 } else if (port->iso7816.flags & SER_ISO7816_ENABLED) {
2217 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg);
2218 /* select mck clock, and output */
2219 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
2220 /* set max iterations */
2221 mode |= ATMEL_US_MAX_ITER(3);
2222 if ((port->iso7816.flags & SER_ISO7816_T_PARAM)
2223 == SER_ISO7816_T(0))
2224 mode |= ATMEL_US_USMODE_ISO7816_T0;
2225 else
2226 mode |= ATMEL_US_USMODE_ISO7816_T1;
2227 } else if (termios->c_cflag & CRTSCTS) {
2228 /* RS232 with hardware handshake (RTS/CTS) */
2229 if (atmel_use_fifo(port) &&
2230 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2231 /*
2232 * with ATMEL_US_USMODE_HWHS set, the controller will
2233 * be able to drive the RTS pin high/low when the RX
2234 * FIFO is above RXFTHRES/below RXFTHRES2.
2235 * It will also disable the transmitter when the CTS
2236 * pin is high.
2237 * This mode is not activated if CTS pin is a GPIO
2238 * because in this case, the transmitter is always
2239 * disabled (there must be an internal pull-up
2240 * responsible for this behaviour).
2241 * If the RTS pin is a GPIO, the controller won't be
2242 * able to drive it according to the FIFO thresholds,
2243 * but it will be handled by the driver.
2244 */
2245 mode |= ATMEL_US_USMODE_HWHS;
2246 } else {
2247 /*
2248 * For platforms without FIFO, the flow control is
2249 * handled by the driver.
2250 */
2251 mode |= ATMEL_US_USMODE_NORMAL;
2252 }
2253 } else {
2254 /* RS232 without hadware handshake */
2255 mode |= ATMEL_US_USMODE_NORMAL;
2256 }
2257
2258 /*
2259 * Set the baud rate:
2260 * Fractional baudrate allows to setup output frequency more
2261 * accurately. This feature is enabled only when using normal mode.
2262 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2263 * Currently, OVER is always set to 0 so we get
2264 * baudrate = selected clock / (16 * (CD + FP / 8))
2265 * then
2266 * 8 CD + FP = selected clock / (2 * baudrate)
2267 */
2268 if (atmel_port->has_frac_baudrate) {
2269 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2270 cd = div >> 3;
2271 fp = div & ATMEL_US_FP_MASK;
2272 } else {
2273 cd = uart_get_divisor(port, baud);
2274 }
2275
2276 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2277 cd /= 8;
2278 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2279 }
2280 quot = cd | fp << ATMEL_US_FP_OFFSET;
2281
2282 if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
2283 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2284
2285 /* set the mode, clock divisor, parity, stop bits and data size */
2286 atmel_uart_writel(port, ATMEL_US_MR, mode);
2287
2288 /*
2289 * when switching the mode, set the RTS line state according to the
2290 * new mode, otherwise keep the former state
2291 */
2292 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2293 unsigned int rts_state;
2294
2295 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2296 /* let the hardware control the RTS line */
2297 rts_state = ATMEL_US_RTSDIS;
2298 } else {
2299 /* force RTS line to low level */
2300 rts_state = ATMEL_US_RTSEN;
2301 }
2302
2303 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2304 }
2305
2306 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2307 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2308 atmel_port->tx_stopped = false;
2309
2310 /* restore interrupts */
2311 atmel_uart_writel(port, ATMEL_US_IER, imr);
2312
2313 /* CTS flow-control and modem-status interrupts */
2314 if (UART_ENABLE_MS(port, termios->c_cflag))
2315 atmel_enable_ms(port);
2316 else
2317 atmel_disable_ms(port);
2318
2319 spin_unlock_irqrestore(&port->lock, flags);
2320}
2321
2322static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2323{
2324 if (termios->c_line == N_PPS) {
2325 port->flags |= UPF_HARDPPS_CD;
2326 spin_lock_irq(&port->lock);
2327 atmel_enable_ms(port);
2328 spin_unlock_irq(&port->lock);
2329 } else {
2330 port->flags &= ~UPF_HARDPPS_CD;
2331 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2332 spin_lock_irq(&port->lock);
2333 atmel_disable_ms(port);
2334 spin_unlock_irq(&port->lock);
2335 }
2336 }
2337}
2338
2339/*
2340 * Return string describing the specified port
2341 */
2342static const char *atmel_type(struct uart_port *port)
2343{
2344 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2345}
2346
2347/*
2348 * Release the memory region(s) being used by 'port'.
2349 */
2350static void atmel_release_port(struct uart_port *port)
2351{
2352 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2353 int size = resource_size(mpdev->resource);
2354
2355 release_mem_region(port->mapbase, size);
2356
2357 if (port->flags & UPF_IOREMAP) {
2358 iounmap(port->membase);
2359 port->membase = NULL;
2360 }
2361}
2362
2363/*
2364 * Request the memory region(s) being used by 'port'.
2365 */
2366static int atmel_request_port(struct uart_port *port)
2367{
2368 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2369 int size = resource_size(mpdev->resource);
2370
2371 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2372 return -EBUSY;
2373
2374 if (port->flags & UPF_IOREMAP) {
2375 port->membase = ioremap(port->mapbase, size);
2376 if (port->membase == NULL) {
2377 release_mem_region(port->mapbase, size);
2378 return -ENOMEM;
2379 }
2380 }
2381
2382 return 0;
2383}
2384
2385/*
2386 * Configure/autoconfigure the port.
2387 */
2388static void atmel_config_port(struct uart_port *port, int flags)
2389{
2390 if (flags & UART_CONFIG_TYPE) {
2391 port->type = PORT_ATMEL;
2392 atmel_request_port(port);
2393 }
2394}
2395
2396/*
2397 * Verify the new serial_struct (for TIOCSSERIAL).
2398 */
2399static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2400{
2401 int ret = 0;
2402 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2403 ret = -EINVAL;
2404 if (port->irq != ser->irq)
2405 ret = -EINVAL;
2406 if (ser->io_type != SERIAL_IO_MEM)
2407 ret = -EINVAL;
2408 if (port->uartclk / 16 != ser->baud_base)
2409 ret = -EINVAL;
2410 if (port->mapbase != (unsigned long)ser->iomem_base)
2411 ret = -EINVAL;
2412 if (port->iobase != ser->port)
2413 ret = -EINVAL;
2414 if (ser->hub6 != 0)
2415 ret = -EINVAL;
2416 return ret;
2417}
2418
2419#ifdef CONFIG_CONSOLE_POLL
2420static int atmel_poll_get_char(struct uart_port *port)
2421{
2422 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2423 cpu_relax();
2424
2425 return atmel_uart_read_char(port);
2426}
2427
2428static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2429{
2430 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2431 cpu_relax();
2432
2433 atmel_uart_write_char(port, ch);
2434}
2435#endif
2436
2437static const struct uart_ops atmel_pops = {
2438 .tx_empty = atmel_tx_empty,
2439 .set_mctrl = atmel_set_mctrl,
2440 .get_mctrl = atmel_get_mctrl,
2441 .stop_tx = atmel_stop_tx,
2442 .start_tx = atmel_start_tx,
2443 .stop_rx = atmel_stop_rx,
2444 .enable_ms = atmel_enable_ms,
2445 .break_ctl = atmel_break_ctl,
2446 .startup = atmel_startup,
2447 .shutdown = atmel_shutdown,
2448 .flush_buffer = atmel_flush_buffer,
2449 .set_termios = atmel_set_termios,
2450 .set_ldisc = atmel_set_ldisc,
2451 .type = atmel_type,
2452 .release_port = atmel_release_port,
2453 .request_port = atmel_request_port,
2454 .config_port = atmel_config_port,
2455 .verify_port = atmel_verify_port,
2456 .pm = atmel_serial_pm,
2457#ifdef CONFIG_CONSOLE_POLL
2458 .poll_get_char = atmel_poll_get_char,
2459 .poll_put_char = atmel_poll_put_char,
2460#endif
2461};
2462
2463/*
2464 * Configure the port from the platform device resource info.
2465 */
2466static int atmel_init_port(struct atmel_uart_port *atmel_port,
2467 struct platform_device *pdev)
2468{
2469 int ret;
2470 struct uart_port *port = &atmel_port->uart;
2471 struct platform_device *mpdev = to_platform_device(pdev->dev.parent);
2472
2473 atmel_init_property(atmel_port, pdev);
2474 atmel_set_ops(port);
2475
2476 port->iotype = UPIO_MEM;
2477 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
2478 port->ops = &atmel_pops;
2479 port->fifosize = 1;
2480 port->dev = &pdev->dev;
2481 port->mapbase = mpdev->resource[0].start;
2482 port->irq = mpdev->resource[1].start;
2483 port->rs485_config = atmel_config_rs485;
2484 port->iso7816_config = atmel_config_iso7816;
2485 port->membase = NULL;
2486
2487 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2488
2489 ret = uart_get_rs485_mode(port);
2490 if (ret)
2491 return ret;
2492
2493 /* for console, the clock could already be configured */
2494 if (!atmel_port->clk) {
2495 atmel_port->clk = clk_get(&mpdev->dev, "usart");
2496 if (IS_ERR(atmel_port->clk)) {
2497 ret = PTR_ERR(atmel_port->clk);
2498 atmel_port->clk = NULL;
2499 return ret;
2500 }
2501 ret = clk_prepare_enable(atmel_port->clk);
2502 if (ret) {
2503 clk_put(atmel_port->clk);
2504 atmel_port->clk = NULL;
2505 return ret;
2506 }
2507 port->uartclk = clk_get_rate(atmel_port->clk);
2508 clk_disable_unprepare(atmel_port->clk);
2509 /* only enable clock when USART is in use */
2510 }
2511
2512 /*
2513 * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or
2514 * ENDTX|TXBUFE
2515 */
2516 if (atmel_uart_is_half_duplex(port))
2517 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2518 else if (atmel_use_pdc_tx(port)) {
2519 port->fifosize = PDC_BUFFER_SIZE;
2520 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2521 } else {
2522 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2523 }
2524
2525 return 0;
2526}
2527
2528#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2529static void atmel_console_putchar(struct uart_port *port, int ch)
2530{
2531 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2532 cpu_relax();
2533 atmel_uart_write_char(port, ch);
2534}
2535
2536/*
2537 * Interrupts are disabled on entering
2538 */
2539static void atmel_console_write(struct console *co, const char *s, u_int count)
2540{
2541 struct uart_port *port = &atmel_ports[co->index].uart;
2542 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2543 unsigned int status, imr;
2544 unsigned int pdc_tx;
2545
2546 /*
2547 * First, save IMR and then disable interrupts
2548 */
2549 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2550 atmel_uart_writel(port, ATMEL_US_IDR,
2551 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2552
2553 /* Store PDC transmit status and disable it */
2554 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2555 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2556
2557 /* Make sure that tx path is actually able to send characters */
2558 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2559 atmel_port->tx_stopped = false;
2560
2561 uart_console_write(port, s, count, atmel_console_putchar);
2562
2563 /*
2564 * Finally, wait for transmitter to become empty
2565 * and restore IMR
2566 */
2567 do {
2568 status = atmel_uart_readl(port, ATMEL_US_CSR);
2569 } while (!(status & ATMEL_US_TXRDY));
2570
2571 /* Restore PDC transmit status */
2572 if (pdc_tx)
2573 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2574
2575 /* set interrupts back the way they were */
2576 atmel_uart_writel(port, ATMEL_US_IER, imr);
2577}
2578
2579/*
2580 * If the port was already initialised (eg, by a boot loader),
2581 * try to determine the current setup.
2582 */
2583static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2584 int *parity, int *bits)
2585{
2586 unsigned int mr, quot;
2587
2588 /*
2589 * If the baud rate generator isn't running, the port wasn't
2590 * initialized by the boot loader.
2591 */
2592 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2593 if (!quot)
2594 return;
2595
2596 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2597 if (mr == ATMEL_US_CHRL_8)
2598 *bits = 8;
2599 else
2600 *bits = 7;
2601
2602 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2603 if (mr == ATMEL_US_PAR_EVEN)
2604 *parity = 'e';
2605 else if (mr == ATMEL_US_PAR_ODD)
2606 *parity = 'o';
2607
2608 /*
2609 * The serial core only rounds down when matching this to a
2610 * supported baud rate. Make sure we don't end up slightly
2611 * lower than one of those, as it would make us fall through
2612 * to a much lower baud rate than we really want.
2613 */
2614 *baud = port->uartclk / (16 * (quot - 1));
2615}
2616
2617static int __init atmel_console_setup(struct console *co, char *options)
2618{
2619 int ret;
2620 struct uart_port *port = &atmel_ports[co->index].uart;
2621 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2622 int baud = 115200;
2623 int bits = 8;
2624 int parity = 'n';
2625 int flow = 'n';
2626
2627 if (port->membase == NULL) {
2628 /* Port not initialized yet - delay setup */
2629 return -ENODEV;
2630 }
2631
2632 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2633 if (ret)
2634 return ret;
2635
2636 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2637 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2638 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2639 atmel_port->tx_stopped = false;
2640
2641 if (options)
2642 uart_parse_options(options, &baud, &parity, &bits, &flow);
2643 else
2644 atmel_console_get_options(port, &baud, &parity, &bits);
2645
2646 return uart_set_options(port, co, baud, parity, bits, flow);
2647}
2648
2649static struct uart_driver atmel_uart;
2650
2651static struct console atmel_console = {
2652 .name = ATMEL_DEVICENAME,
2653 .write = atmel_console_write,
2654 .device = uart_console_device,
2655 .setup = atmel_console_setup,
2656 .flags = CON_PRINTBUFFER,
2657 .index = -1,
2658 .data = &atmel_uart,
2659};
2660
2661#define ATMEL_CONSOLE_DEVICE (&atmel_console)
2662
2663#else
2664#define ATMEL_CONSOLE_DEVICE NULL
2665#endif
2666
2667static struct uart_driver atmel_uart = {
2668 .owner = THIS_MODULE,
2669 .driver_name = "atmel_serial",
2670 .dev_name = ATMEL_DEVICENAME,
2671 .major = SERIAL_ATMEL_MAJOR,
2672 .minor = MINOR_START,
2673 .nr = ATMEL_MAX_UART,
2674 .cons = ATMEL_CONSOLE_DEVICE,
2675};
2676
2677#ifdef CONFIG_PM
2678static bool atmel_serial_clk_will_stop(void)
2679{
2680#ifdef CONFIG_ARCH_AT91
2681 return at91_suspend_entering_slow_clock();
2682#else
2683 return false;
2684#endif
2685}
2686
2687static int atmel_serial_suspend(struct platform_device *pdev,
2688 pm_message_t state)
2689{
2690 struct uart_port *port = platform_get_drvdata(pdev);
2691 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2692
2693 if (uart_console(port) && console_suspend_enabled) {
2694 /* Drain the TX shifter */
2695 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2696 ATMEL_US_TXEMPTY))
2697 cpu_relax();
2698 }
2699
2700 if (uart_console(port) && !console_suspend_enabled) {
2701 /* Cache register values as we won't get a full shutdown/startup
2702 * cycle
2703 */
2704 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2705 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2706 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2707 atmel_port->cache.rtor = atmel_uart_readl(port,
2708 atmel_port->rtor);
2709 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2710 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2711 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2712 }
2713
2714 /* we can not wake up if we're running on slow clock */
2715 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2716 if (atmel_serial_clk_will_stop()) {
2717 unsigned long flags;
2718
2719 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2720 atmel_port->suspended = true;
2721 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2722 device_set_wakeup_enable(&pdev->dev, 0);
2723 }
2724
2725 uart_suspend_port(&atmel_uart, port);
2726
2727 return 0;
2728}
2729
2730static int atmel_serial_resume(struct platform_device *pdev)
2731{
2732 struct uart_port *port = platform_get_drvdata(pdev);
2733 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2734 unsigned long flags;
2735
2736 if (uart_console(port) && !console_suspend_enabled) {
2737 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2738 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2739 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2740 atmel_uart_writel(port, atmel_port->rtor,
2741 atmel_port->cache.rtor);
2742 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2743
2744 if (atmel_port->fifo_size) {
2745 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2746 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2747 atmel_uart_writel(port, ATMEL_US_FMR,
2748 atmel_port->cache.fmr);
2749 atmel_uart_writel(port, ATMEL_US_FIER,
2750 atmel_port->cache.fimr);
2751 }
2752 atmel_start_rx(port);
2753 }
2754
2755 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2756 if (atmel_port->pending) {
2757 atmel_handle_receive(port, atmel_port->pending);
2758 atmel_handle_status(port, atmel_port->pending,
2759 atmel_port->pending_status);
2760 atmel_handle_transmit(port, atmel_port->pending);
2761 atmel_port->pending = 0;
2762 }
2763 atmel_port->suspended = false;
2764 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2765
2766 uart_resume_port(&atmel_uart, port);
2767 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2768
2769 return 0;
2770}
2771#else
2772#define atmel_serial_suspend NULL
2773#define atmel_serial_resume NULL
2774#endif
2775
2776static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2777 struct platform_device *pdev)
2778{
2779 atmel_port->fifo_size = 0;
2780 atmel_port->rts_low = 0;
2781 atmel_port->rts_high = 0;
2782
2783 if (of_property_read_u32(pdev->dev.of_node,
2784 "atmel,fifo-size",
2785 &atmel_port->fifo_size))
2786 return;
2787
2788 if (!atmel_port->fifo_size)
2789 return;
2790
2791 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2792 atmel_port->fifo_size = 0;
2793 dev_err(&pdev->dev, "Invalid FIFO size\n");
2794 return;
2795 }
2796
2797 /*
2798 * 0 <= rts_low <= rts_high <= fifo_size
2799 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2800 * to flush their internal TX FIFO, commonly up to 16 data, before
2801 * actually stopping to send new data. So we try to set the RTS High
2802 * Threshold to a reasonably high value respecting this 16 data
2803 * empirical rule when possible.
2804 */
2805 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2806 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2807 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2808 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2809
2810 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2811 atmel_port->fifo_size);
2812 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2813 atmel_port->rts_high);
2814 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2815 atmel_port->rts_low);
2816}
2817
2818static int atmel_serial_probe(struct platform_device *pdev)
2819{
2820 struct atmel_uart_port *atmel_port;
2821 struct device_node *np = pdev->dev.parent->of_node;
2822 void *data;
2823 int ret;
2824 bool rs485_enabled;
2825
2826 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2827
2828 /*
2829 * In device tree there is no node with "atmel,at91rm9200-usart-serial"
2830 * as compatible string. This driver is probed by at91-usart mfd driver
2831 * which is just a wrapper over the atmel_serial driver and
2832 * spi-at91-usart driver. All attributes needed by this driver are
2833 * found in of_node of parent.
2834 */
2835 pdev->dev.of_node = np;
2836
2837 ret = of_alias_get_id(np, "serial");
2838 if (ret < 0)
2839 /* port id not found in platform data nor device-tree aliases:
2840 * auto-enumerate it */
2841 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2842
2843 if (ret >= ATMEL_MAX_UART) {
2844 ret = -ENODEV;
2845 goto err;
2846 }
2847
2848 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2849 /* port already in use */
2850 ret = -EBUSY;
2851 goto err;
2852 }
2853
2854 atmel_port = &atmel_ports[ret];
2855 atmel_port->backup_imr = 0;
2856 atmel_port->uart.line = ret;
2857 atmel_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_ATMEL_CONSOLE);
2858 atmel_serial_probe_fifos(atmel_port, pdev);
2859
2860 atomic_set(&atmel_port->tasklet_shutdown, 0);
2861 spin_lock_init(&atmel_port->lock_suspended);
2862
2863 ret = atmel_init_port(atmel_port, pdev);
2864 if (ret)
2865 goto err_clear_bit;
2866
2867 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2868 if (IS_ERR(atmel_port->gpios)) {
2869 ret = PTR_ERR(atmel_port->gpios);
2870 goto err_clear_bit;
2871 }
2872
2873 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2874 ret = -ENOMEM;
2875 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
2876 sizeof(struct atmel_uart_char),
2877 GFP_KERNEL);
2878 if (!data)
2879 goto err_alloc_ring;
2880 atmel_port->rx_ring.buf = data;
2881 }
2882
2883 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2884
2885 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2886 if (ret)
2887 goto err_add_port;
2888
2889#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2890 if (uart_console(&atmel_port->uart)
2891 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2892 /*
2893 * The serial core enabled the clock for us, so undo
2894 * the clk_prepare_enable() in atmel_console_setup()
2895 */
2896 clk_disable_unprepare(atmel_port->clk);
2897 }
2898#endif
2899
2900 device_init_wakeup(&pdev->dev, 1);
2901 platform_set_drvdata(pdev, atmel_port);
2902
2903 /*
2904 * The peripheral clock has been disabled by atmel_init_port():
2905 * enable it before accessing I/O registers
2906 */
2907 clk_prepare_enable(atmel_port->clk);
2908
2909 if (rs485_enabled) {
2910 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2911 ATMEL_US_USMODE_NORMAL);
2912 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2913 ATMEL_US_RTSEN);
2914 }
2915
2916 /*
2917 * Get port name of usart or uart
2918 */
2919 atmel_get_ip_name(&atmel_port->uart);
2920
2921 /*
2922 * The peripheral clock can now safely be disabled till the port
2923 * is used
2924 */
2925 clk_disable_unprepare(atmel_port->clk);
2926
2927 return 0;
2928
2929err_add_port:
2930 kfree(atmel_port->rx_ring.buf);
2931 atmel_port->rx_ring.buf = NULL;
2932err_alloc_ring:
2933 if (!uart_console(&atmel_port->uart)) {
2934 clk_put(atmel_port->clk);
2935 atmel_port->clk = NULL;
2936 }
2937err_clear_bit:
2938 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2939err:
2940 return ret;
2941}
2942
2943/*
2944 * Even if the driver is not modular, it makes sense to be able to
2945 * unbind a device: there can be many bound devices, and there are
2946 * situations where dynamic binding and unbinding can be useful.
2947 *
2948 * For example, a connected device can require a specific firmware update
2949 * protocol that needs bitbanging on IO lines, but use the regular serial
2950 * port in the normal case.
2951 */
2952static int atmel_serial_remove(struct platform_device *pdev)
2953{
2954 struct uart_port *port = platform_get_drvdata(pdev);
2955 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2956 int ret = 0;
2957
2958 tasklet_kill(&atmel_port->tasklet_rx);
2959 tasklet_kill(&atmel_port->tasklet_tx);
2960
2961 device_init_wakeup(&pdev->dev, 0);
2962
2963 ret = uart_remove_one_port(&atmel_uart, port);
2964
2965 kfree(atmel_port->rx_ring.buf);
2966
2967 /* "port" is allocated statically, so we shouldn't free it */
2968
2969 clear_bit(port->line, atmel_ports_in_use);
2970
2971 clk_put(atmel_port->clk);
2972 atmel_port->clk = NULL;
2973 pdev->dev.of_node = NULL;
2974
2975 return ret;
2976}
2977
2978static struct platform_driver atmel_serial_driver = {
2979 .probe = atmel_serial_probe,
2980 .remove = atmel_serial_remove,
2981 .suspend = atmel_serial_suspend,
2982 .resume = atmel_serial_resume,
2983 .driver = {
2984 .name = "atmel_usart_serial",
2985 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2986 },
2987};
2988
2989static int __init atmel_serial_init(void)
2990{
2991 int ret;
2992
2993 ret = uart_register_driver(&atmel_uart);
2994 if (ret)
2995 return ret;
2996
2997 ret = platform_driver_register(&atmel_serial_driver);
2998 if (ret)
2999 uart_unregister_driver(&atmel_uart);
3000
3001 return ret;
3002}
3003device_initcall(atmel_serial_init);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for Atmel AT91 Serial ports
4 * Copyright (C) 2003 Rick Bronson
5 *
6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 *
9 * DMA support added by Chip Coldwell.
10 */
11#include <linux/tty.h>
12#include <linux/ioport.h>
13#include <linux/slab.h>
14#include <linux/init.h>
15#include <linux/serial.h>
16#include <linux/clk.h>
17#include <linux/console.h>
18#include <linux/sysrq.h>
19#include <linux/tty_flip.h>
20#include <linux/platform_device.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/of_gpio.h>
24#include <linux/dma-mapping.h>
25#include <linux/dmaengine.h>
26#include <linux/atmel_pdc.h>
27#include <linux/uaccess.h>
28#include <linux/platform_data/atmel.h>
29#include <linux/timer.h>
30#include <linux/gpio.h>
31#include <linux/gpio/consumer.h>
32#include <linux/err.h>
33#include <linux/irq.h>
34#include <linux/suspend.h>
35#include <linux/mm.h>
36
37#include <asm/div64.h>
38#include <asm/io.h>
39#include <asm/ioctls.h>
40
41#define PDC_BUFFER_SIZE 512
42/* Revisit: We should calculate this based on the actual port settings */
43#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
44
45/* The minium number of data FIFOs should be able to contain */
46#define ATMEL_MIN_FIFO_SIZE 8
47/*
48 * These two offsets are substracted from the RX FIFO size to define the RTS
49 * high and low thresholds
50 */
51#define ATMEL_RTS_HIGH_OFFSET 16
52#define ATMEL_RTS_LOW_OFFSET 20
53
54#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
55#define SUPPORT_SYSRQ
56#endif
57
58#include <linux/serial_core.h>
59
60#include "serial_mctrl_gpio.h"
61#include "atmel_serial.h"
62
63static void atmel_start_rx(struct uart_port *port);
64static void atmel_stop_rx(struct uart_port *port);
65
66#ifdef CONFIG_SERIAL_ATMEL_TTYAT
67
68/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
69 * should coexist with the 8250 driver, such as if we have an external 16C550
70 * UART. */
71#define SERIAL_ATMEL_MAJOR 204
72#define MINOR_START 154
73#define ATMEL_DEVICENAME "ttyAT"
74
75#else
76
77/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
78 * name, but it is legally reserved for the 8250 driver. */
79#define SERIAL_ATMEL_MAJOR TTY_MAJOR
80#define MINOR_START 64
81#define ATMEL_DEVICENAME "ttyS"
82
83#endif
84
85#define ATMEL_ISR_PASS_LIMIT 256
86
87struct atmel_dma_buffer {
88 unsigned char *buf;
89 dma_addr_t dma_addr;
90 unsigned int dma_size;
91 unsigned int ofs;
92};
93
94struct atmel_uart_char {
95 u16 status;
96 u16 ch;
97};
98
99/*
100 * Be careful, the real size of the ring buffer is
101 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
102 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
103 * DMA mode.
104 */
105#define ATMEL_SERIAL_RINGSIZE 1024
106
107/*
108 * at91: 6 USARTs and one DBGU port (SAM9260)
109 * samx7: 3 USARTs and 5 UARTs
110 */
111#define ATMEL_MAX_UART 8
112
113/*
114 * We wrap our port structure around the generic uart_port.
115 */
116struct atmel_uart_port {
117 struct uart_port uart; /* uart */
118 struct clk *clk; /* uart clock */
119 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
120 u32 backup_imr; /* IMR saved during suspend */
121 int break_active; /* break being received */
122
123 bool use_dma_rx; /* enable DMA receiver */
124 bool use_pdc_rx; /* enable PDC receiver */
125 short pdc_rx_idx; /* current PDC RX buffer */
126 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
127
128 bool use_dma_tx; /* enable DMA transmitter */
129 bool use_pdc_tx; /* enable PDC transmitter */
130 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
131
132 spinlock_t lock_tx; /* port lock */
133 spinlock_t lock_rx; /* port lock */
134 struct dma_chan *chan_tx;
135 struct dma_chan *chan_rx;
136 struct dma_async_tx_descriptor *desc_tx;
137 struct dma_async_tx_descriptor *desc_rx;
138 dma_cookie_t cookie_tx;
139 dma_cookie_t cookie_rx;
140 struct scatterlist sg_tx;
141 struct scatterlist sg_rx;
142 struct tasklet_struct tasklet_rx;
143 struct tasklet_struct tasklet_tx;
144 atomic_t tasklet_shutdown;
145 unsigned int irq_status_prev;
146 unsigned int tx_len;
147
148 struct circ_buf rx_ring;
149
150 struct mctrl_gpios *gpios;
151 u32 backup_mode; /* MR saved during iso7816 operations */
152 u32 backup_brgr; /* BRGR saved during iso7816 operations */
153 unsigned int tx_done_mask;
154 u32 fifo_size;
155 u32 rts_high;
156 u32 rts_low;
157 bool ms_irq_enabled;
158 u32 rtor; /* address of receiver timeout register if it exists */
159 bool has_frac_baudrate;
160 bool has_hw_timer;
161 struct timer_list uart_timer;
162
163 bool tx_stopped;
164 bool suspended;
165 unsigned int pending;
166 unsigned int pending_status;
167 spinlock_t lock_suspended;
168
169 bool hd_start_rx; /* can start RX during half-duplex operation */
170
171 /* ISO7816 */
172 unsigned int fidi_min;
173 unsigned int fidi_max;
174
175#ifdef CONFIG_PM
176 struct {
177 u32 cr;
178 u32 mr;
179 u32 imr;
180 u32 brgr;
181 u32 rtor;
182 u32 ttgr;
183 u32 fmr;
184 u32 fimr;
185 } cache;
186#endif
187
188 int (*prepare_rx)(struct uart_port *port);
189 int (*prepare_tx)(struct uart_port *port);
190 void (*schedule_rx)(struct uart_port *port);
191 void (*schedule_tx)(struct uart_port *port);
192 void (*release_rx)(struct uart_port *port);
193 void (*release_tx)(struct uart_port *port);
194};
195
196static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
197static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
198
199#ifdef SUPPORT_SYSRQ
200static struct console atmel_console;
201#endif
202
203#if defined(CONFIG_OF)
204static const struct of_device_id atmel_serial_dt_ids[] = {
205 { .compatible = "atmel,at91rm9200-usart-serial" },
206 { /* sentinel */ }
207};
208#endif
209
210static inline struct atmel_uart_port *
211to_atmel_uart_port(struct uart_port *uart)
212{
213 return container_of(uart, struct atmel_uart_port, uart);
214}
215
216static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
217{
218 return __raw_readl(port->membase + reg);
219}
220
221static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
222{
223 __raw_writel(value, port->membase + reg);
224}
225
226static inline u8 atmel_uart_read_char(struct uart_port *port)
227{
228 return __raw_readb(port->membase + ATMEL_US_RHR);
229}
230
231static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
232{
233 __raw_writeb(value, port->membase + ATMEL_US_THR);
234}
235
236static inline int atmel_uart_is_half_duplex(struct uart_port *port)
237{
238 return ((port->rs485.flags & SER_RS485_ENABLED) &&
239 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
240 (port->iso7816.flags & SER_ISO7816_ENABLED);
241}
242
243#ifdef CONFIG_SERIAL_ATMEL_PDC
244static bool atmel_use_pdc_rx(struct uart_port *port)
245{
246 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
247
248 return atmel_port->use_pdc_rx;
249}
250
251static bool atmel_use_pdc_tx(struct uart_port *port)
252{
253 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
254
255 return atmel_port->use_pdc_tx;
256}
257#else
258static bool atmel_use_pdc_rx(struct uart_port *port)
259{
260 return false;
261}
262
263static bool atmel_use_pdc_tx(struct uart_port *port)
264{
265 return false;
266}
267#endif
268
269static bool atmel_use_dma_tx(struct uart_port *port)
270{
271 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
272
273 return atmel_port->use_dma_tx;
274}
275
276static bool atmel_use_dma_rx(struct uart_port *port)
277{
278 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
279
280 return atmel_port->use_dma_rx;
281}
282
283static bool atmel_use_fifo(struct uart_port *port)
284{
285 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
286
287 return atmel_port->fifo_size;
288}
289
290static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
291 struct tasklet_struct *t)
292{
293 if (!atomic_read(&atmel_port->tasklet_shutdown))
294 tasklet_schedule(t);
295}
296
297/* Enable or disable the rs485 support */
298static int atmel_config_rs485(struct uart_port *port,
299 struct serial_rs485 *rs485conf)
300{
301 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
302 unsigned int mode;
303
304 /* Disable interrupts */
305 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
306
307 mode = atmel_uart_readl(port, ATMEL_US_MR);
308
309 /* Resetting serial mode to RS232 (0x0) */
310 mode &= ~ATMEL_US_USMODE;
311
312 port->rs485 = *rs485conf;
313
314 if (rs485conf->flags & SER_RS485_ENABLED) {
315 dev_dbg(port->dev, "Setting UART to RS485\n");
316 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
317 atmel_uart_writel(port, ATMEL_US_TTGR,
318 rs485conf->delay_rts_after_send);
319 mode |= ATMEL_US_USMODE_RS485;
320 } else {
321 dev_dbg(port->dev, "Setting UART to RS232\n");
322 if (atmel_use_pdc_tx(port))
323 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
324 ATMEL_US_TXBUFE;
325 else
326 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
327 }
328 atmel_uart_writel(port, ATMEL_US_MR, mode);
329
330 /* Enable interrupts */
331 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
332
333 return 0;
334}
335
336static unsigned int atmel_calc_cd(struct uart_port *port,
337 struct serial_iso7816 *iso7816conf)
338{
339 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
340 unsigned int cd;
341 u64 mck_rate;
342
343 mck_rate = (u64)clk_get_rate(atmel_port->clk);
344 do_div(mck_rate, iso7816conf->clk);
345 cd = mck_rate;
346 return cd;
347}
348
349static unsigned int atmel_calc_fidi(struct uart_port *port,
350 struct serial_iso7816 *iso7816conf)
351{
352 u64 fidi = 0;
353
354 if (iso7816conf->sc_fi && iso7816conf->sc_di) {
355 fidi = (u64)iso7816conf->sc_fi;
356 do_div(fidi, iso7816conf->sc_di);
357 }
358 return (u32)fidi;
359}
360
361/* Enable or disable the iso7816 support */
362/* Called with interrupts disabled */
363static int atmel_config_iso7816(struct uart_port *port,
364 struct serial_iso7816 *iso7816conf)
365{
366 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
367 unsigned int mode;
368 unsigned int cd, fidi;
369 int ret = 0;
370
371 /* Disable interrupts */
372 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
373
374 mode = atmel_uart_readl(port, ATMEL_US_MR);
375
376 if (iso7816conf->flags & SER_ISO7816_ENABLED) {
377 mode &= ~ATMEL_US_USMODE;
378
379 if (iso7816conf->tg > 255) {
380 dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n");
381 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
382 ret = -EINVAL;
383 goto err_out;
384 }
385
386 if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
387 == SER_ISO7816_T(0)) {
388 mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK;
389 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
390 == SER_ISO7816_T(1)) {
391 mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK;
392 } else {
393 dev_err(port->dev, "ISO7816: Type not supported\n");
394 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
395 ret = -EINVAL;
396 goto err_out;
397 }
398
399 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR);
400
401 /* select mck clock, and output */
402 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
403 /* set parity for normal/inverse mode + max iterations */
404 mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3);
405
406 cd = atmel_calc_cd(port, iso7816conf);
407 fidi = atmel_calc_fidi(port, iso7816conf);
408 if (fidi == 0) {
409 dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n");
410 } else if (fidi < atmel_port->fidi_min
411 || fidi > atmel_port->fidi_max) {
412 dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi);
413 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
414 ret = -EINVAL;
415 goto err_out;
416 }
417
418 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) {
419 /* port not yet in iso7816 mode: store configuration */
420 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR);
421 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
422 }
423
424 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg);
425 atmel_uart_writel(port, ATMEL_US_BRGR, cd);
426 atmel_uart_writel(port, ATMEL_US_FIDI, fidi);
427
428 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN);
429 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION;
430 } else {
431 dev_dbg(port->dev, "Setting UART back to RS232\n");
432 /* back to last RS232 settings */
433 mode = atmel_port->backup_mode;
434 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
435 atmel_uart_writel(port, ATMEL_US_TTGR, 0);
436 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr);
437 atmel_uart_writel(port, ATMEL_US_FIDI, 0x174);
438
439 if (atmel_use_pdc_tx(port))
440 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
441 ATMEL_US_TXBUFE;
442 else
443 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
444 }
445
446 port->iso7816 = *iso7816conf;
447
448 atmel_uart_writel(port, ATMEL_US_MR, mode);
449
450err_out:
451 /* Enable interrupts */
452 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
453
454 return ret;
455}
456
457/*
458 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
459 */
460static u_int atmel_tx_empty(struct uart_port *port)
461{
462 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
463
464 if (atmel_port->tx_stopped)
465 return TIOCSER_TEMT;
466 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
467 TIOCSER_TEMT :
468 0;
469}
470
471/*
472 * Set state of the modem control output lines
473 */
474static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
475{
476 unsigned int control = 0;
477 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
478 unsigned int rts_paused, rts_ready;
479 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
480
481 /* override mode to RS485 if needed, otherwise keep the current mode */
482 if (port->rs485.flags & SER_RS485_ENABLED) {
483 atmel_uart_writel(port, ATMEL_US_TTGR,
484 port->rs485.delay_rts_after_send);
485 mode &= ~ATMEL_US_USMODE;
486 mode |= ATMEL_US_USMODE_RS485;
487 }
488
489 /* set the RTS line state according to the mode */
490 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
491 /* force RTS line to high level */
492 rts_paused = ATMEL_US_RTSEN;
493
494 /* give the control of the RTS line back to the hardware */
495 rts_ready = ATMEL_US_RTSDIS;
496 } else {
497 /* force RTS line to high level */
498 rts_paused = ATMEL_US_RTSDIS;
499
500 /* force RTS line to low level */
501 rts_ready = ATMEL_US_RTSEN;
502 }
503
504 if (mctrl & TIOCM_RTS)
505 control |= rts_ready;
506 else
507 control |= rts_paused;
508
509 if (mctrl & TIOCM_DTR)
510 control |= ATMEL_US_DTREN;
511 else
512 control |= ATMEL_US_DTRDIS;
513
514 atmel_uart_writel(port, ATMEL_US_CR, control);
515
516 mctrl_gpio_set(atmel_port->gpios, mctrl);
517
518 /* Local loopback mode? */
519 mode &= ~ATMEL_US_CHMODE;
520 if (mctrl & TIOCM_LOOP)
521 mode |= ATMEL_US_CHMODE_LOC_LOOP;
522 else
523 mode |= ATMEL_US_CHMODE_NORMAL;
524
525 atmel_uart_writel(port, ATMEL_US_MR, mode);
526}
527
528/*
529 * Get state of the modem control input lines
530 */
531static u_int atmel_get_mctrl(struct uart_port *port)
532{
533 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
534 unsigned int ret = 0, status;
535
536 status = atmel_uart_readl(port, ATMEL_US_CSR);
537
538 /*
539 * The control signals are active low.
540 */
541 if (!(status & ATMEL_US_DCD))
542 ret |= TIOCM_CD;
543 if (!(status & ATMEL_US_CTS))
544 ret |= TIOCM_CTS;
545 if (!(status & ATMEL_US_DSR))
546 ret |= TIOCM_DSR;
547 if (!(status & ATMEL_US_RI))
548 ret |= TIOCM_RI;
549
550 return mctrl_gpio_get(atmel_port->gpios, &ret);
551}
552
553/*
554 * Stop transmitting.
555 */
556static void atmel_stop_tx(struct uart_port *port)
557{
558 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
559
560 if (atmel_use_pdc_tx(port)) {
561 /* disable PDC transmit */
562 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
563 }
564
565 /*
566 * Disable the transmitter.
567 * This is mandatory when DMA is used, otherwise the DMA buffer
568 * is fully transmitted.
569 */
570 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
571 atmel_port->tx_stopped = true;
572
573 /* Disable interrupts */
574 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
575
576 if (atmel_uart_is_half_duplex(port))
577 atmel_start_rx(port);
578
579}
580
581/*
582 * Start transmitting.
583 */
584static void atmel_start_tx(struct uart_port *port)
585{
586 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
587
588 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
589 & ATMEL_PDC_TXTEN))
590 /* The transmitter is already running. Yes, we
591 really need this.*/
592 return;
593
594 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
595 if (atmel_uart_is_half_duplex(port))
596 atmel_stop_rx(port);
597
598 if (atmel_use_pdc_tx(port))
599 /* re-enable PDC transmit */
600 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
601
602 /* Enable interrupts */
603 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
604
605 /* re-enable the transmitter */
606 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
607 atmel_port->tx_stopped = false;
608}
609
610/*
611 * start receiving - port is in process of being opened.
612 */
613static void atmel_start_rx(struct uart_port *port)
614{
615 /* reset status and receiver */
616 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
617
618 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
619
620 if (atmel_use_pdc_rx(port)) {
621 /* enable PDC controller */
622 atmel_uart_writel(port, ATMEL_US_IER,
623 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
624 port->read_status_mask);
625 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
626 } else {
627 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
628 }
629}
630
631/*
632 * Stop receiving - port is in process of being closed.
633 */
634static void atmel_stop_rx(struct uart_port *port)
635{
636 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
637
638 if (atmel_use_pdc_rx(port)) {
639 /* disable PDC receive */
640 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
641 atmel_uart_writel(port, ATMEL_US_IDR,
642 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
643 port->read_status_mask);
644 } else {
645 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
646 }
647}
648
649/*
650 * Enable modem status interrupts
651 */
652static void atmel_enable_ms(struct uart_port *port)
653{
654 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
655 uint32_t ier = 0;
656
657 /*
658 * Interrupt should not be enabled twice
659 */
660 if (atmel_port->ms_irq_enabled)
661 return;
662
663 atmel_port->ms_irq_enabled = true;
664
665 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
666 ier |= ATMEL_US_CTSIC;
667
668 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
669 ier |= ATMEL_US_DSRIC;
670
671 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
672 ier |= ATMEL_US_RIIC;
673
674 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
675 ier |= ATMEL_US_DCDIC;
676
677 atmel_uart_writel(port, ATMEL_US_IER, ier);
678
679 mctrl_gpio_enable_ms(atmel_port->gpios);
680}
681
682/*
683 * Disable modem status interrupts
684 */
685static void atmel_disable_ms(struct uart_port *port)
686{
687 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
688 uint32_t idr = 0;
689
690 /*
691 * Interrupt should not be disabled twice
692 */
693 if (!atmel_port->ms_irq_enabled)
694 return;
695
696 atmel_port->ms_irq_enabled = false;
697
698 mctrl_gpio_disable_ms(atmel_port->gpios);
699
700 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
701 idr |= ATMEL_US_CTSIC;
702
703 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
704 idr |= ATMEL_US_DSRIC;
705
706 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
707 idr |= ATMEL_US_RIIC;
708
709 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
710 idr |= ATMEL_US_DCDIC;
711
712 atmel_uart_writel(port, ATMEL_US_IDR, idr);
713}
714
715/*
716 * Control the transmission of a break signal
717 */
718static void atmel_break_ctl(struct uart_port *port, int break_state)
719{
720 if (break_state != 0)
721 /* start break */
722 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
723 else
724 /* stop break */
725 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
726}
727
728/*
729 * Stores the incoming character in the ring buffer
730 */
731static void
732atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
733 unsigned int ch)
734{
735 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
736 struct circ_buf *ring = &atmel_port->rx_ring;
737 struct atmel_uart_char *c;
738
739 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
740 /* Buffer overflow, ignore char */
741 return;
742
743 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
744 c->status = status;
745 c->ch = ch;
746
747 /* Make sure the character is stored before we update head. */
748 smp_wmb();
749
750 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
751}
752
753/*
754 * Deal with parity, framing and overrun errors.
755 */
756static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
757{
758 /* clear error */
759 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
760
761 if (status & ATMEL_US_RXBRK) {
762 /* ignore side-effect */
763 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
764 port->icount.brk++;
765 }
766 if (status & ATMEL_US_PARE)
767 port->icount.parity++;
768 if (status & ATMEL_US_FRAME)
769 port->icount.frame++;
770 if (status & ATMEL_US_OVRE)
771 port->icount.overrun++;
772}
773
774/*
775 * Characters received (called from interrupt handler)
776 */
777static void atmel_rx_chars(struct uart_port *port)
778{
779 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
780 unsigned int status, ch;
781
782 status = atmel_uart_readl(port, ATMEL_US_CSR);
783 while (status & ATMEL_US_RXRDY) {
784 ch = atmel_uart_read_char(port);
785
786 /*
787 * note that the error handling code is
788 * out of the main execution path
789 */
790 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
791 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
792 || atmel_port->break_active)) {
793
794 /* clear error */
795 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
796
797 if (status & ATMEL_US_RXBRK
798 && !atmel_port->break_active) {
799 atmel_port->break_active = 1;
800 atmel_uart_writel(port, ATMEL_US_IER,
801 ATMEL_US_RXBRK);
802 } else {
803 /*
804 * This is either the end-of-break
805 * condition or we've received at
806 * least one character without RXBRK
807 * being set. In both cases, the next
808 * RXBRK will indicate start-of-break.
809 */
810 atmel_uart_writel(port, ATMEL_US_IDR,
811 ATMEL_US_RXBRK);
812 status &= ~ATMEL_US_RXBRK;
813 atmel_port->break_active = 0;
814 }
815 }
816
817 atmel_buffer_rx_char(port, status, ch);
818 status = atmel_uart_readl(port, ATMEL_US_CSR);
819 }
820
821 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
822}
823
824/*
825 * Transmit characters (called from tasklet with TXRDY interrupt
826 * disabled)
827 */
828static void atmel_tx_chars(struct uart_port *port)
829{
830 struct circ_buf *xmit = &port->state->xmit;
831 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
832
833 if (port->x_char &&
834 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
835 atmel_uart_write_char(port, port->x_char);
836 port->icount.tx++;
837 port->x_char = 0;
838 }
839 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
840 return;
841
842 while (atmel_uart_readl(port, ATMEL_US_CSR) &
843 atmel_port->tx_done_mask) {
844 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
845 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
846 port->icount.tx++;
847 if (uart_circ_empty(xmit))
848 break;
849 }
850
851 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
852 uart_write_wakeup(port);
853
854 if (!uart_circ_empty(xmit))
855 /* Enable interrupts */
856 atmel_uart_writel(port, ATMEL_US_IER,
857 atmel_port->tx_done_mask);
858}
859
860static void atmel_complete_tx_dma(void *arg)
861{
862 struct atmel_uart_port *atmel_port = arg;
863 struct uart_port *port = &atmel_port->uart;
864 struct circ_buf *xmit = &port->state->xmit;
865 struct dma_chan *chan = atmel_port->chan_tx;
866 unsigned long flags;
867
868 spin_lock_irqsave(&port->lock, flags);
869
870 if (chan)
871 dmaengine_terminate_all(chan);
872 xmit->tail += atmel_port->tx_len;
873 xmit->tail &= UART_XMIT_SIZE - 1;
874
875 port->icount.tx += atmel_port->tx_len;
876
877 spin_lock_irq(&atmel_port->lock_tx);
878 async_tx_ack(atmel_port->desc_tx);
879 atmel_port->cookie_tx = -EINVAL;
880 atmel_port->desc_tx = NULL;
881 spin_unlock_irq(&atmel_port->lock_tx);
882
883 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
884 uart_write_wakeup(port);
885
886 /*
887 * xmit is a circular buffer so, if we have just send data from
888 * xmit->tail to the end of xmit->buf, now we have to transmit the
889 * remaining data from the beginning of xmit->buf to xmit->head.
890 */
891 if (!uart_circ_empty(xmit))
892 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
893 else if (atmel_uart_is_half_duplex(port)) {
894 /*
895 * DMA done, re-enable TXEMPTY and signal that we can stop
896 * TX and start RX for RS485
897 */
898 atmel_port->hd_start_rx = true;
899 atmel_uart_writel(port, ATMEL_US_IER,
900 atmel_port->tx_done_mask);
901 }
902
903 spin_unlock_irqrestore(&port->lock, flags);
904}
905
906static void atmel_release_tx_dma(struct uart_port *port)
907{
908 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
909 struct dma_chan *chan = atmel_port->chan_tx;
910
911 if (chan) {
912 dmaengine_terminate_all(chan);
913 dma_release_channel(chan);
914 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
915 DMA_TO_DEVICE);
916 }
917
918 atmel_port->desc_tx = NULL;
919 atmel_port->chan_tx = NULL;
920 atmel_port->cookie_tx = -EINVAL;
921}
922
923/*
924 * Called from tasklet with TXRDY interrupt is disabled.
925 */
926static void atmel_tx_dma(struct uart_port *port)
927{
928 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
929 struct circ_buf *xmit = &port->state->xmit;
930 struct dma_chan *chan = atmel_port->chan_tx;
931 struct dma_async_tx_descriptor *desc;
932 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
933 unsigned int tx_len, part1_len, part2_len, sg_len;
934 dma_addr_t phys_addr;
935
936 /* Make sure we have an idle channel */
937 if (atmel_port->desc_tx != NULL)
938 return;
939
940 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
941 /*
942 * DMA is idle now.
943 * Port xmit buffer is already mapped,
944 * and it is one page... Just adjust
945 * offsets and lengths. Since it is a circular buffer,
946 * we have to transmit till the end, and then the rest.
947 * Take the port lock to get a
948 * consistent xmit buffer state.
949 */
950 tx_len = CIRC_CNT_TO_END(xmit->head,
951 xmit->tail,
952 UART_XMIT_SIZE);
953
954 if (atmel_port->fifo_size) {
955 /* multi data mode */
956 part1_len = (tx_len & ~0x3); /* DWORD access */
957 part2_len = (tx_len & 0x3); /* BYTE access */
958 } else {
959 /* single data (legacy) mode */
960 part1_len = 0;
961 part2_len = tx_len; /* BYTE access only */
962 }
963
964 sg_init_table(sgl, 2);
965 sg_len = 0;
966 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
967 if (part1_len) {
968 sg = &sgl[sg_len++];
969 sg_dma_address(sg) = phys_addr;
970 sg_dma_len(sg) = part1_len;
971
972 phys_addr += part1_len;
973 }
974
975 if (part2_len) {
976 sg = &sgl[sg_len++];
977 sg_dma_address(sg) = phys_addr;
978 sg_dma_len(sg) = part2_len;
979 }
980
981 /*
982 * save tx_len so atmel_complete_tx_dma() will increase
983 * xmit->tail correctly
984 */
985 atmel_port->tx_len = tx_len;
986
987 desc = dmaengine_prep_slave_sg(chan,
988 sgl,
989 sg_len,
990 DMA_MEM_TO_DEV,
991 DMA_PREP_INTERRUPT |
992 DMA_CTRL_ACK);
993 if (!desc) {
994 dev_err(port->dev, "Failed to send via dma!\n");
995 return;
996 }
997
998 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
999
1000 atmel_port->desc_tx = desc;
1001 desc->callback = atmel_complete_tx_dma;
1002 desc->callback_param = atmel_port;
1003 atmel_port->cookie_tx = dmaengine_submit(desc);
1004 }
1005
1006 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1007 uart_write_wakeup(port);
1008}
1009
1010static int atmel_prepare_tx_dma(struct uart_port *port)
1011{
1012 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1013 struct device *mfd_dev = port->dev->parent;
1014 dma_cap_mask_t mask;
1015 struct dma_slave_config config;
1016 int ret, nent;
1017
1018 dma_cap_zero(mask);
1019 dma_cap_set(DMA_SLAVE, mask);
1020
1021 atmel_port->chan_tx = dma_request_slave_channel(mfd_dev, "tx");
1022 if (atmel_port->chan_tx == NULL)
1023 goto chan_err;
1024 dev_info(port->dev, "using %s for tx DMA transfers\n",
1025 dma_chan_name(atmel_port->chan_tx));
1026
1027 spin_lock_init(&atmel_port->lock_tx);
1028 sg_init_table(&atmel_port->sg_tx, 1);
1029 /* UART circular tx buffer is an aligned page. */
1030 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
1031 sg_set_page(&atmel_port->sg_tx,
1032 virt_to_page(port->state->xmit.buf),
1033 UART_XMIT_SIZE,
1034 offset_in_page(port->state->xmit.buf));
1035 nent = dma_map_sg(port->dev,
1036 &atmel_port->sg_tx,
1037 1,
1038 DMA_TO_DEVICE);
1039
1040 if (!nent) {
1041 dev_dbg(port->dev, "need to release resource of dma\n");
1042 goto chan_err;
1043 } else {
1044 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1045 sg_dma_len(&atmel_port->sg_tx),
1046 port->state->xmit.buf,
1047 &sg_dma_address(&atmel_port->sg_tx));
1048 }
1049
1050 /* Configure the slave DMA */
1051 memset(&config, 0, sizeof(config));
1052 config.direction = DMA_MEM_TO_DEV;
1053 config.dst_addr_width = (atmel_port->fifo_size) ?
1054 DMA_SLAVE_BUSWIDTH_4_BYTES :
1055 DMA_SLAVE_BUSWIDTH_1_BYTE;
1056 config.dst_addr = port->mapbase + ATMEL_US_THR;
1057 config.dst_maxburst = 1;
1058
1059 ret = dmaengine_slave_config(atmel_port->chan_tx,
1060 &config);
1061 if (ret) {
1062 dev_err(port->dev, "DMA tx slave configuration failed\n");
1063 goto chan_err;
1064 }
1065
1066 return 0;
1067
1068chan_err:
1069 dev_err(port->dev, "TX channel not available, switch to pio\n");
1070 atmel_port->use_dma_tx = 0;
1071 if (atmel_port->chan_tx)
1072 atmel_release_tx_dma(port);
1073 return -EINVAL;
1074}
1075
1076static void atmel_complete_rx_dma(void *arg)
1077{
1078 struct uart_port *port = arg;
1079 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1080
1081 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1082}
1083
1084static void atmel_release_rx_dma(struct uart_port *port)
1085{
1086 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1087 struct dma_chan *chan = atmel_port->chan_rx;
1088
1089 if (chan) {
1090 dmaengine_terminate_all(chan);
1091 dma_release_channel(chan);
1092 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1093 DMA_FROM_DEVICE);
1094 }
1095
1096 atmel_port->desc_rx = NULL;
1097 atmel_port->chan_rx = NULL;
1098 atmel_port->cookie_rx = -EINVAL;
1099}
1100
1101static void atmel_rx_from_dma(struct uart_port *port)
1102{
1103 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1104 struct tty_port *tport = &port->state->port;
1105 struct circ_buf *ring = &atmel_port->rx_ring;
1106 struct dma_chan *chan = atmel_port->chan_rx;
1107 struct dma_tx_state state;
1108 enum dma_status dmastat;
1109 size_t count;
1110
1111
1112 /* Reset the UART timeout early so that we don't miss one */
1113 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1114 dmastat = dmaengine_tx_status(chan,
1115 atmel_port->cookie_rx,
1116 &state);
1117 /* Restart a new tasklet if DMA status is error */
1118 if (dmastat == DMA_ERROR) {
1119 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1120 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1121 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1122 return;
1123 }
1124
1125 /* CPU claims ownership of RX DMA buffer */
1126 dma_sync_sg_for_cpu(port->dev,
1127 &atmel_port->sg_rx,
1128 1,
1129 DMA_FROM_DEVICE);
1130
1131 /*
1132 * ring->head points to the end of data already written by the DMA.
1133 * ring->tail points to the beginning of data to be read by the
1134 * framework.
1135 * The current transfer size should not be larger than the dma buffer
1136 * length.
1137 */
1138 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1139 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1140 /*
1141 * At this point ring->head may point to the first byte right after the
1142 * last byte of the dma buffer:
1143 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1144 *
1145 * However ring->tail must always points inside the dma buffer:
1146 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1147 *
1148 * Since we use a ring buffer, we have to handle the case
1149 * where head is lower than tail. In such a case, we first read from
1150 * tail to the end of the buffer then reset tail.
1151 */
1152 if (ring->head < ring->tail) {
1153 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1154
1155 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1156 ring->tail = 0;
1157 port->icount.rx += count;
1158 }
1159
1160 /* Finally we read data from tail to head */
1161 if (ring->tail < ring->head) {
1162 count = ring->head - ring->tail;
1163
1164 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1165 /* Wrap ring->head if needed */
1166 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1167 ring->head = 0;
1168 ring->tail = ring->head;
1169 port->icount.rx += count;
1170 }
1171
1172 /* USART retreives ownership of RX DMA buffer */
1173 dma_sync_sg_for_device(port->dev,
1174 &atmel_port->sg_rx,
1175 1,
1176 DMA_FROM_DEVICE);
1177
1178 /*
1179 * Drop the lock here since it might end up calling
1180 * uart_start(), which takes the lock.
1181 */
1182 spin_unlock(&port->lock);
1183 tty_flip_buffer_push(tport);
1184 spin_lock(&port->lock);
1185
1186 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1187}
1188
1189static int atmel_prepare_rx_dma(struct uart_port *port)
1190{
1191 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1192 struct device *mfd_dev = port->dev->parent;
1193 struct dma_async_tx_descriptor *desc;
1194 dma_cap_mask_t mask;
1195 struct dma_slave_config config;
1196 struct circ_buf *ring;
1197 int ret, nent;
1198
1199 ring = &atmel_port->rx_ring;
1200
1201 dma_cap_zero(mask);
1202 dma_cap_set(DMA_CYCLIC, mask);
1203
1204 atmel_port->chan_rx = dma_request_slave_channel(mfd_dev, "rx");
1205 if (atmel_port->chan_rx == NULL)
1206 goto chan_err;
1207 dev_info(port->dev, "using %s for rx DMA transfers\n",
1208 dma_chan_name(atmel_port->chan_rx));
1209
1210 spin_lock_init(&atmel_port->lock_rx);
1211 sg_init_table(&atmel_port->sg_rx, 1);
1212 /* UART circular rx buffer is an aligned page. */
1213 BUG_ON(!PAGE_ALIGNED(ring->buf));
1214 sg_set_page(&atmel_port->sg_rx,
1215 virt_to_page(ring->buf),
1216 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1217 offset_in_page(ring->buf));
1218 nent = dma_map_sg(port->dev,
1219 &atmel_port->sg_rx,
1220 1,
1221 DMA_FROM_DEVICE);
1222
1223 if (!nent) {
1224 dev_dbg(port->dev, "need to release resource of dma\n");
1225 goto chan_err;
1226 } else {
1227 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1228 sg_dma_len(&atmel_port->sg_rx),
1229 ring->buf,
1230 &sg_dma_address(&atmel_port->sg_rx));
1231 }
1232
1233 /* Configure the slave DMA */
1234 memset(&config, 0, sizeof(config));
1235 config.direction = DMA_DEV_TO_MEM;
1236 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1237 config.src_addr = port->mapbase + ATMEL_US_RHR;
1238 config.src_maxburst = 1;
1239
1240 ret = dmaengine_slave_config(atmel_port->chan_rx,
1241 &config);
1242 if (ret) {
1243 dev_err(port->dev, "DMA rx slave configuration failed\n");
1244 goto chan_err;
1245 }
1246 /*
1247 * Prepare a cyclic dma transfer, assign 2 descriptors,
1248 * each one is half ring buffer size
1249 */
1250 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1251 sg_dma_address(&atmel_port->sg_rx),
1252 sg_dma_len(&atmel_port->sg_rx),
1253 sg_dma_len(&atmel_port->sg_rx)/2,
1254 DMA_DEV_TO_MEM,
1255 DMA_PREP_INTERRUPT);
1256 if (!desc) {
1257 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1258 goto chan_err;
1259 }
1260 desc->callback = atmel_complete_rx_dma;
1261 desc->callback_param = port;
1262 atmel_port->desc_rx = desc;
1263 atmel_port->cookie_rx = dmaengine_submit(desc);
1264
1265 return 0;
1266
1267chan_err:
1268 dev_err(port->dev, "RX channel not available, switch to pio\n");
1269 atmel_port->use_dma_rx = 0;
1270 if (atmel_port->chan_rx)
1271 atmel_release_rx_dma(port);
1272 return -EINVAL;
1273}
1274
1275static void atmel_uart_timer_callback(struct timer_list *t)
1276{
1277 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1278 uart_timer);
1279 struct uart_port *port = &atmel_port->uart;
1280
1281 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1282 tasklet_schedule(&atmel_port->tasklet_rx);
1283 mod_timer(&atmel_port->uart_timer,
1284 jiffies + uart_poll_timeout(port));
1285 }
1286}
1287
1288/*
1289 * receive interrupt handler.
1290 */
1291static void
1292atmel_handle_receive(struct uart_port *port, unsigned int pending)
1293{
1294 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1295
1296 if (atmel_use_pdc_rx(port)) {
1297 /*
1298 * PDC receive. Just schedule the tasklet and let it
1299 * figure out the details.
1300 *
1301 * TODO: We're not handling error flags correctly at
1302 * the moment.
1303 */
1304 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1305 atmel_uart_writel(port, ATMEL_US_IDR,
1306 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1307 atmel_tasklet_schedule(atmel_port,
1308 &atmel_port->tasklet_rx);
1309 }
1310
1311 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1312 ATMEL_US_FRAME | ATMEL_US_PARE))
1313 atmel_pdc_rxerr(port, pending);
1314 }
1315
1316 if (atmel_use_dma_rx(port)) {
1317 if (pending & ATMEL_US_TIMEOUT) {
1318 atmel_uart_writel(port, ATMEL_US_IDR,
1319 ATMEL_US_TIMEOUT);
1320 atmel_tasklet_schedule(atmel_port,
1321 &atmel_port->tasklet_rx);
1322 }
1323 }
1324
1325 /* Interrupt receive */
1326 if (pending & ATMEL_US_RXRDY)
1327 atmel_rx_chars(port);
1328 else if (pending & ATMEL_US_RXBRK) {
1329 /*
1330 * End of break detected. If it came along with a
1331 * character, atmel_rx_chars will handle it.
1332 */
1333 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1334 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1335 atmel_port->break_active = 0;
1336 }
1337}
1338
1339/*
1340 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1341 */
1342static void
1343atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1344{
1345 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1346
1347 if (pending & atmel_port->tx_done_mask) {
1348 atmel_uart_writel(port, ATMEL_US_IDR,
1349 atmel_port->tx_done_mask);
1350
1351 /* Start RX if flag was set and FIFO is empty */
1352 if (atmel_port->hd_start_rx) {
1353 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1354 & ATMEL_US_TXEMPTY))
1355 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1356
1357 atmel_port->hd_start_rx = false;
1358 atmel_start_rx(port);
1359 }
1360
1361 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1362 }
1363}
1364
1365/*
1366 * status flags interrupt handler.
1367 */
1368static void
1369atmel_handle_status(struct uart_port *port, unsigned int pending,
1370 unsigned int status)
1371{
1372 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1373 unsigned int status_change;
1374
1375 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1376 | ATMEL_US_CTSIC)) {
1377 status_change = status ^ atmel_port->irq_status_prev;
1378 atmel_port->irq_status_prev = status;
1379
1380 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1381 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1382 /* TODO: All reads to CSR will clear these interrupts! */
1383 if (status_change & ATMEL_US_RI)
1384 port->icount.rng++;
1385 if (status_change & ATMEL_US_DSR)
1386 port->icount.dsr++;
1387 if (status_change & ATMEL_US_DCD)
1388 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1389 if (status_change & ATMEL_US_CTS)
1390 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1391
1392 wake_up_interruptible(&port->state->port.delta_msr_wait);
1393 }
1394 }
1395
1396 if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION))
1397 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending);
1398}
1399
1400/*
1401 * Interrupt handler
1402 */
1403static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1404{
1405 struct uart_port *port = dev_id;
1406 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1407 unsigned int status, pending, mask, pass_counter = 0;
1408
1409 spin_lock(&atmel_port->lock_suspended);
1410
1411 do {
1412 status = atmel_uart_readl(port, ATMEL_US_CSR);
1413 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1414 pending = status & mask;
1415 if (!pending)
1416 break;
1417
1418 if (atmel_port->suspended) {
1419 atmel_port->pending |= pending;
1420 atmel_port->pending_status = status;
1421 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1422 pm_system_wakeup();
1423 break;
1424 }
1425
1426 atmel_handle_receive(port, pending);
1427 atmel_handle_status(port, pending, status);
1428 atmel_handle_transmit(port, pending);
1429 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1430
1431 spin_unlock(&atmel_port->lock_suspended);
1432
1433 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1434}
1435
1436static void atmel_release_tx_pdc(struct uart_port *port)
1437{
1438 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1439 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1440
1441 dma_unmap_single(port->dev,
1442 pdc->dma_addr,
1443 pdc->dma_size,
1444 DMA_TO_DEVICE);
1445}
1446
1447/*
1448 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1449 */
1450static void atmel_tx_pdc(struct uart_port *port)
1451{
1452 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1453 struct circ_buf *xmit = &port->state->xmit;
1454 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1455 int count;
1456
1457 /* nothing left to transmit? */
1458 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1459 return;
1460
1461 xmit->tail += pdc->ofs;
1462 xmit->tail &= UART_XMIT_SIZE - 1;
1463
1464 port->icount.tx += pdc->ofs;
1465 pdc->ofs = 0;
1466
1467 /* more to transmit - setup next transfer */
1468
1469 /* disable PDC transmit */
1470 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1471
1472 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1473 dma_sync_single_for_device(port->dev,
1474 pdc->dma_addr,
1475 pdc->dma_size,
1476 DMA_TO_DEVICE);
1477
1478 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1479 pdc->ofs = count;
1480
1481 atmel_uart_writel(port, ATMEL_PDC_TPR,
1482 pdc->dma_addr + xmit->tail);
1483 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1484 /* re-enable PDC transmit */
1485 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1486 /* Enable interrupts */
1487 atmel_uart_writel(port, ATMEL_US_IER,
1488 atmel_port->tx_done_mask);
1489 } else {
1490 if (atmel_uart_is_half_duplex(port)) {
1491 /* DMA done, stop TX, start RX for RS485 */
1492 atmel_start_rx(port);
1493 }
1494 }
1495
1496 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1497 uart_write_wakeup(port);
1498}
1499
1500static int atmel_prepare_tx_pdc(struct uart_port *port)
1501{
1502 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1503 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1504 struct circ_buf *xmit = &port->state->xmit;
1505
1506 pdc->buf = xmit->buf;
1507 pdc->dma_addr = dma_map_single(port->dev,
1508 pdc->buf,
1509 UART_XMIT_SIZE,
1510 DMA_TO_DEVICE);
1511 pdc->dma_size = UART_XMIT_SIZE;
1512 pdc->ofs = 0;
1513
1514 return 0;
1515}
1516
1517static void atmel_rx_from_ring(struct uart_port *port)
1518{
1519 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1520 struct circ_buf *ring = &atmel_port->rx_ring;
1521 unsigned int flg;
1522 unsigned int status;
1523
1524 while (ring->head != ring->tail) {
1525 struct atmel_uart_char c;
1526
1527 /* Make sure c is loaded after head. */
1528 smp_rmb();
1529
1530 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1531
1532 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1533
1534 port->icount.rx++;
1535 status = c.status;
1536 flg = TTY_NORMAL;
1537
1538 /*
1539 * note that the error handling code is
1540 * out of the main execution path
1541 */
1542 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1543 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1544 if (status & ATMEL_US_RXBRK) {
1545 /* ignore side-effect */
1546 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1547
1548 port->icount.brk++;
1549 if (uart_handle_break(port))
1550 continue;
1551 }
1552 if (status & ATMEL_US_PARE)
1553 port->icount.parity++;
1554 if (status & ATMEL_US_FRAME)
1555 port->icount.frame++;
1556 if (status & ATMEL_US_OVRE)
1557 port->icount.overrun++;
1558
1559 status &= port->read_status_mask;
1560
1561 if (status & ATMEL_US_RXBRK)
1562 flg = TTY_BREAK;
1563 else if (status & ATMEL_US_PARE)
1564 flg = TTY_PARITY;
1565 else if (status & ATMEL_US_FRAME)
1566 flg = TTY_FRAME;
1567 }
1568
1569
1570 if (uart_handle_sysrq_char(port, c.ch))
1571 continue;
1572
1573 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1574 }
1575
1576 /*
1577 * Drop the lock here since it might end up calling
1578 * uart_start(), which takes the lock.
1579 */
1580 spin_unlock(&port->lock);
1581 tty_flip_buffer_push(&port->state->port);
1582 spin_lock(&port->lock);
1583}
1584
1585static void atmel_release_rx_pdc(struct uart_port *port)
1586{
1587 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1588 int i;
1589
1590 for (i = 0; i < 2; i++) {
1591 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1592
1593 dma_unmap_single(port->dev,
1594 pdc->dma_addr,
1595 pdc->dma_size,
1596 DMA_FROM_DEVICE);
1597 kfree(pdc->buf);
1598 }
1599}
1600
1601static void atmel_rx_from_pdc(struct uart_port *port)
1602{
1603 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1604 struct tty_port *tport = &port->state->port;
1605 struct atmel_dma_buffer *pdc;
1606 int rx_idx = atmel_port->pdc_rx_idx;
1607 unsigned int head;
1608 unsigned int tail;
1609 unsigned int count;
1610
1611 do {
1612 /* Reset the UART timeout early so that we don't miss one */
1613 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1614
1615 pdc = &atmel_port->pdc_rx[rx_idx];
1616 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1617 tail = pdc->ofs;
1618
1619 /* If the PDC has switched buffers, RPR won't contain
1620 * any address within the current buffer. Since head
1621 * is unsigned, we just need a one-way comparison to
1622 * find out.
1623 *
1624 * In this case, we just need to consume the entire
1625 * buffer and resubmit it for DMA. This will clear the
1626 * ENDRX bit as well, so that we can safely re-enable
1627 * all interrupts below.
1628 */
1629 head = min(head, pdc->dma_size);
1630
1631 if (likely(head != tail)) {
1632 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1633 pdc->dma_size, DMA_FROM_DEVICE);
1634
1635 /*
1636 * head will only wrap around when we recycle
1637 * the DMA buffer, and when that happens, we
1638 * explicitly set tail to 0. So head will
1639 * always be greater than tail.
1640 */
1641 count = head - tail;
1642
1643 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1644 count);
1645
1646 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1647 pdc->dma_size, DMA_FROM_DEVICE);
1648
1649 port->icount.rx += count;
1650 pdc->ofs = head;
1651 }
1652
1653 /*
1654 * If the current buffer is full, we need to check if
1655 * the next one contains any additional data.
1656 */
1657 if (head >= pdc->dma_size) {
1658 pdc->ofs = 0;
1659 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1660 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1661
1662 rx_idx = !rx_idx;
1663 atmel_port->pdc_rx_idx = rx_idx;
1664 }
1665 } while (head >= pdc->dma_size);
1666
1667 /*
1668 * Drop the lock here since it might end up calling
1669 * uart_start(), which takes the lock.
1670 */
1671 spin_unlock(&port->lock);
1672 tty_flip_buffer_push(tport);
1673 spin_lock(&port->lock);
1674
1675 atmel_uart_writel(port, ATMEL_US_IER,
1676 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1677}
1678
1679static int atmel_prepare_rx_pdc(struct uart_port *port)
1680{
1681 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1682 int i;
1683
1684 for (i = 0; i < 2; i++) {
1685 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1686
1687 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1688 if (pdc->buf == NULL) {
1689 if (i != 0) {
1690 dma_unmap_single(port->dev,
1691 atmel_port->pdc_rx[0].dma_addr,
1692 PDC_BUFFER_SIZE,
1693 DMA_FROM_DEVICE);
1694 kfree(atmel_port->pdc_rx[0].buf);
1695 }
1696 atmel_port->use_pdc_rx = 0;
1697 return -ENOMEM;
1698 }
1699 pdc->dma_addr = dma_map_single(port->dev,
1700 pdc->buf,
1701 PDC_BUFFER_SIZE,
1702 DMA_FROM_DEVICE);
1703 pdc->dma_size = PDC_BUFFER_SIZE;
1704 pdc->ofs = 0;
1705 }
1706
1707 atmel_port->pdc_rx_idx = 0;
1708
1709 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1710 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1711
1712 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1713 atmel_port->pdc_rx[1].dma_addr);
1714 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1715
1716 return 0;
1717}
1718
1719/*
1720 * tasklet handling tty stuff outside the interrupt handler.
1721 */
1722static void atmel_tasklet_rx_func(unsigned long data)
1723{
1724 struct uart_port *port = (struct uart_port *)data;
1725 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1726
1727 /* The interrupt handler does not take the lock */
1728 spin_lock(&port->lock);
1729 atmel_port->schedule_rx(port);
1730 spin_unlock(&port->lock);
1731}
1732
1733static void atmel_tasklet_tx_func(unsigned long data)
1734{
1735 struct uart_port *port = (struct uart_port *)data;
1736 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1737
1738 /* The interrupt handler does not take the lock */
1739 spin_lock(&port->lock);
1740 atmel_port->schedule_tx(port);
1741 spin_unlock(&port->lock);
1742}
1743
1744static void atmel_init_property(struct atmel_uart_port *atmel_port,
1745 struct platform_device *pdev)
1746{
1747 struct device_node *np = pdev->dev.of_node;
1748
1749 /* DMA/PDC usage specification */
1750 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1751 if (of_property_read_bool(np, "dmas")) {
1752 atmel_port->use_dma_rx = true;
1753 atmel_port->use_pdc_rx = false;
1754 } else {
1755 atmel_port->use_dma_rx = false;
1756 atmel_port->use_pdc_rx = true;
1757 }
1758 } else {
1759 atmel_port->use_dma_rx = false;
1760 atmel_port->use_pdc_rx = false;
1761 }
1762
1763 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1764 if (of_property_read_bool(np, "dmas")) {
1765 atmel_port->use_dma_tx = true;
1766 atmel_port->use_pdc_tx = false;
1767 } else {
1768 atmel_port->use_dma_tx = false;
1769 atmel_port->use_pdc_tx = true;
1770 }
1771 } else {
1772 atmel_port->use_dma_tx = false;
1773 atmel_port->use_pdc_tx = false;
1774 }
1775}
1776
1777static void atmel_set_ops(struct uart_port *port)
1778{
1779 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1780
1781 if (atmel_use_dma_rx(port)) {
1782 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1783 atmel_port->schedule_rx = &atmel_rx_from_dma;
1784 atmel_port->release_rx = &atmel_release_rx_dma;
1785 } else if (atmel_use_pdc_rx(port)) {
1786 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1787 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1788 atmel_port->release_rx = &atmel_release_rx_pdc;
1789 } else {
1790 atmel_port->prepare_rx = NULL;
1791 atmel_port->schedule_rx = &atmel_rx_from_ring;
1792 atmel_port->release_rx = NULL;
1793 }
1794
1795 if (atmel_use_dma_tx(port)) {
1796 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1797 atmel_port->schedule_tx = &atmel_tx_dma;
1798 atmel_port->release_tx = &atmel_release_tx_dma;
1799 } else if (atmel_use_pdc_tx(port)) {
1800 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1801 atmel_port->schedule_tx = &atmel_tx_pdc;
1802 atmel_port->release_tx = &atmel_release_tx_pdc;
1803 } else {
1804 atmel_port->prepare_tx = NULL;
1805 atmel_port->schedule_tx = &atmel_tx_chars;
1806 atmel_port->release_tx = NULL;
1807 }
1808}
1809
1810/*
1811 * Get ip name usart or uart
1812 */
1813static void atmel_get_ip_name(struct uart_port *port)
1814{
1815 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1816 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1817 u32 version;
1818 u32 usart, dbgu_uart, new_uart;
1819 /* ASCII decoding for IP version */
1820 usart = 0x55534152; /* USAR(T) */
1821 dbgu_uart = 0x44424755; /* DBGU */
1822 new_uart = 0x55415254; /* UART */
1823
1824 /*
1825 * Only USART devices from at91sam9260 SOC implement fractional
1826 * baudrate. It is available for all asynchronous modes, with the
1827 * following restriction: the sampling clock's duty cycle is not
1828 * constant.
1829 */
1830 atmel_port->has_frac_baudrate = false;
1831 atmel_port->has_hw_timer = false;
1832
1833 if (name == new_uart) {
1834 dev_dbg(port->dev, "Uart with hw timer");
1835 atmel_port->has_hw_timer = true;
1836 atmel_port->rtor = ATMEL_UA_RTOR;
1837 } else if (name == usart) {
1838 dev_dbg(port->dev, "Usart\n");
1839 atmel_port->has_frac_baudrate = true;
1840 atmel_port->has_hw_timer = true;
1841 atmel_port->rtor = ATMEL_US_RTOR;
1842 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1843 switch (version) {
1844 case 0x814: /* sama5d2 */
1845 /* fall through */
1846 case 0x701: /* sama5d4 */
1847 atmel_port->fidi_min = 3;
1848 atmel_port->fidi_max = 65535;
1849 break;
1850 case 0x502: /* sam9x5, sama5d3 */
1851 atmel_port->fidi_min = 3;
1852 atmel_port->fidi_max = 2047;
1853 break;
1854 default:
1855 atmel_port->fidi_min = 1;
1856 atmel_port->fidi_max = 2047;
1857 }
1858 } else if (name == dbgu_uart) {
1859 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1860 } else {
1861 /* fallback for older SoCs: use version field */
1862 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1863 switch (version) {
1864 case 0x302:
1865 case 0x10213:
1866 case 0x10302:
1867 dev_dbg(port->dev, "This version is usart\n");
1868 atmel_port->has_frac_baudrate = true;
1869 atmel_port->has_hw_timer = true;
1870 atmel_port->rtor = ATMEL_US_RTOR;
1871 break;
1872 case 0x203:
1873 case 0x10202:
1874 dev_dbg(port->dev, "This version is uart\n");
1875 break;
1876 default:
1877 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1878 }
1879 }
1880}
1881
1882/*
1883 * Perform initialization and enable port for reception
1884 */
1885static int atmel_startup(struct uart_port *port)
1886{
1887 struct platform_device *pdev = to_platform_device(port->dev);
1888 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1889 int retval;
1890
1891 /*
1892 * Ensure that no interrupts are enabled otherwise when
1893 * request_irq() is called we could get stuck trying to
1894 * handle an unexpected interrupt
1895 */
1896 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1897 atmel_port->ms_irq_enabled = false;
1898
1899 /*
1900 * Allocate the IRQ
1901 */
1902 retval = request_irq(port->irq, atmel_interrupt,
1903 IRQF_SHARED | IRQF_COND_SUSPEND,
1904 dev_name(&pdev->dev), port);
1905 if (retval) {
1906 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1907 return retval;
1908 }
1909
1910 atomic_set(&atmel_port->tasklet_shutdown, 0);
1911 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1912 (unsigned long)port);
1913 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1914 (unsigned long)port);
1915
1916 /*
1917 * Initialize DMA (if necessary)
1918 */
1919 atmel_init_property(atmel_port, pdev);
1920 atmel_set_ops(port);
1921
1922 if (atmel_port->prepare_rx) {
1923 retval = atmel_port->prepare_rx(port);
1924 if (retval < 0)
1925 atmel_set_ops(port);
1926 }
1927
1928 if (atmel_port->prepare_tx) {
1929 retval = atmel_port->prepare_tx(port);
1930 if (retval < 0)
1931 atmel_set_ops(port);
1932 }
1933
1934 /*
1935 * Enable FIFO when available
1936 */
1937 if (atmel_port->fifo_size) {
1938 unsigned int txrdym = ATMEL_US_ONE_DATA;
1939 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1940 unsigned int fmr;
1941
1942 atmel_uart_writel(port, ATMEL_US_CR,
1943 ATMEL_US_FIFOEN |
1944 ATMEL_US_RXFCLR |
1945 ATMEL_US_TXFLCLR);
1946
1947 if (atmel_use_dma_tx(port))
1948 txrdym = ATMEL_US_FOUR_DATA;
1949
1950 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1951 if (atmel_port->rts_high &&
1952 atmel_port->rts_low)
1953 fmr |= ATMEL_US_FRTSC |
1954 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1955 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1956
1957 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1958 }
1959
1960 /* Save current CSR for comparison in atmel_tasklet_func() */
1961 atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR);
1962
1963 /*
1964 * Finally, enable the serial port
1965 */
1966 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1967 /* enable xmit & rcvr */
1968 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1969 atmel_port->tx_stopped = false;
1970
1971 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
1972
1973 if (atmel_use_pdc_rx(port)) {
1974 /* set UART timeout */
1975 if (!atmel_port->has_hw_timer) {
1976 mod_timer(&atmel_port->uart_timer,
1977 jiffies + uart_poll_timeout(port));
1978 /* set USART timeout */
1979 } else {
1980 atmel_uart_writel(port, atmel_port->rtor,
1981 PDC_RX_TIMEOUT);
1982 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1983
1984 atmel_uart_writel(port, ATMEL_US_IER,
1985 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1986 }
1987 /* enable PDC controller */
1988 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1989 } else if (atmel_use_dma_rx(port)) {
1990 /* set UART timeout */
1991 if (!atmel_port->has_hw_timer) {
1992 mod_timer(&atmel_port->uart_timer,
1993 jiffies + uart_poll_timeout(port));
1994 /* set USART timeout */
1995 } else {
1996 atmel_uart_writel(port, atmel_port->rtor,
1997 PDC_RX_TIMEOUT);
1998 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1999
2000 atmel_uart_writel(port, ATMEL_US_IER,
2001 ATMEL_US_TIMEOUT);
2002 }
2003 } else {
2004 /* enable receive only */
2005 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
2006 }
2007
2008 return 0;
2009}
2010
2011/*
2012 * Flush any TX data submitted for DMA. Called when the TX circular
2013 * buffer is reset.
2014 */
2015static void atmel_flush_buffer(struct uart_port *port)
2016{
2017 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2018
2019 if (atmel_use_pdc_tx(port)) {
2020 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
2021 atmel_port->pdc_tx.ofs = 0;
2022 }
2023 /*
2024 * in uart_flush_buffer(), the xmit circular buffer has just
2025 * been cleared, so we have to reset tx_len accordingly.
2026 */
2027 atmel_port->tx_len = 0;
2028}
2029
2030/*
2031 * Disable the port
2032 */
2033static void atmel_shutdown(struct uart_port *port)
2034{
2035 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2036
2037 /* Disable modem control lines interrupts */
2038 atmel_disable_ms(port);
2039
2040 /* Disable interrupts at device level */
2041 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2042
2043 /* Prevent spurious interrupts from scheduling the tasklet */
2044 atomic_inc(&atmel_port->tasklet_shutdown);
2045
2046 /*
2047 * Prevent any tasklets being scheduled during
2048 * cleanup
2049 */
2050 del_timer_sync(&atmel_port->uart_timer);
2051
2052 /* Make sure that no interrupt is on the fly */
2053 synchronize_irq(port->irq);
2054
2055 /*
2056 * Clear out any scheduled tasklets before
2057 * we destroy the buffers
2058 */
2059 tasklet_kill(&atmel_port->tasklet_rx);
2060 tasklet_kill(&atmel_port->tasklet_tx);
2061
2062 /*
2063 * Ensure everything is stopped and
2064 * disable port and break condition.
2065 */
2066 atmel_stop_rx(port);
2067 atmel_stop_tx(port);
2068
2069 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
2070
2071 /*
2072 * Shut-down the DMA.
2073 */
2074 if (atmel_port->release_rx)
2075 atmel_port->release_rx(port);
2076 if (atmel_port->release_tx)
2077 atmel_port->release_tx(port);
2078
2079 /*
2080 * Reset ring buffer pointers
2081 */
2082 atmel_port->rx_ring.head = 0;
2083 atmel_port->rx_ring.tail = 0;
2084
2085 /*
2086 * Free the interrupts
2087 */
2088 free_irq(port->irq, port);
2089
2090 atmel_flush_buffer(port);
2091}
2092
2093/*
2094 * Power / Clock management.
2095 */
2096static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2097 unsigned int oldstate)
2098{
2099 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2100
2101 switch (state) {
2102 case 0:
2103 /*
2104 * Enable the peripheral clock for this serial port.
2105 * This is called on uart_open() or a resume event.
2106 */
2107 clk_prepare_enable(atmel_port->clk);
2108
2109 /* re-enable interrupts if we disabled some on suspend */
2110 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2111 break;
2112 case 3:
2113 /* Back up the interrupt mask and disable all interrupts */
2114 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2115 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2116
2117 /*
2118 * Disable the peripheral clock for this serial port.
2119 * This is called on uart_close() or a suspend event.
2120 */
2121 clk_disable_unprepare(atmel_port->clk);
2122 break;
2123 default:
2124 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2125 }
2126}
2127
2128/*
2129 * Change the port parameters
2130 */
2131static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2132 struct ktermios *old)
2133{
2134 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2135 unsigned long flags;
2136 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2137
2138 /* save the current mode register */
2139 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2140
2141 /* reset the mode, clock divisor, parity, stop bits and data size */
2142 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2143 ATMEL_US_PAR | ATMEL_US_USMODE);
2144
2145 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2146
2147 /* byte size */
2148 switch (termios->c_cflag & CSIZE) {
2149 case CS5:
2150 mode |= ATMEL_US_CHRL_5;
2151 break;
2152 case CS6:
2153 mode |= ATMEL_US_CHRL_6;
2154 break;
2155 case CS7:
2156 mode |= ATMEL_US_CHRL_7;
2157 break;
2158 default:
2159 mode |= ATMEL_US_CHRL_8;
2160 break;
2161 }
2162
2163 /* stop bits */
2164 if (termios->c_cflag & CSTOPB)
2165 mode |= ATMEL_US_NBSTOP_2;
2166
2167 /* parity */
2168 if (termios->c_cflag & PARENB) {
2169 /* Mark or Space parity */
2170 if (termios->c_cflag & CMSPAR) {
2171 if (termios->c_cflag & PARODD)
2172 mode |= ATMEL_US_PAR_MARK;
2173 else
2174 mode |= ATMEL_US_PAR_SPACE;
2175 } else if (termios->c_cflag & PARODD)
2176 mode |= ATMEL_US_PAR_ODD;
2177 else
2178 mode |= ATMEL_US_PAR_EVEN;
2179 } else
2180 mode |= ATMEL_US_PAR_NONE;
2181
2182 spin_lock_irqsave(&port->lock, flags);
2183
2184 port->read_status_mask = ATMEL_US_OVRE;
2185 if (termios->c_iflag & INPCK)
2186 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2187 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2188 port->read_status_mask |= ATMEL_US_RXBRK;
2189
2190 if (atmel_use_pdc_rx(port))
2191 /* need to enable error interrupts */
2192 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2193
2194 /*
2195 * Characters to ignore
2196 */
2197 port->ignore_status_mask = 0;
2198 if (termios->c_iflag & IGNPAR)
2199 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2200 if (termios->c_iflag & IGNBRK) {
2201 port->ignore_status_mask |= ATMEL_US_RXBRK;
2202 /*
2203 * If we're ignoring parity and break indicators,
2204 * ignore overruns too (for real raw support).
2205 */
2206 if (termios->c_iflag & IGNPAR)
2207 port->ignore_status_mask |= ATMEL_US_OVRE;
2208 }
2209 /* TODO: Ignore all characters if CREAD is set.*/
2210
2211 /* update the per-port timeout */
2212 uart_update_timeout(port, termios->c_cflag, baud);
2213
2214 /*
2215 * save/disable interrupts. The tty layer will ensure that the
2216 * transmitter is empty if requested by the caller, so there's
2217 * no need to wait for it here.
2218 */
2219 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2220 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2221
2222 /* disable receiver and transmitter */
2223 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2224 atmel_port->tx_stopped = true;
2225
2226 /* mode */
2227 if (port->rs485.flags & SER_RS485_ENABLED) {
2228 atmel_uart_writel(port, ATMEL_US_TTGR,
2229 port->rs485.delay_rts_after_send);
2230 mode |= ATMEL_US_USMODE_RS485;
2231 } else if (port->iso7816.flags & SER_ISO7816_ENABLED) {
2232 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg);
2233 /* select mck clock, and output */
2234 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
2235 /* set max iterations */
2236 mode |= ATMEL_US_MAX_ITER(3);
2237 if ((port->iso7816.flags & SER_ISO7816_T_PARAM)
2238 == SER_ISO7816_T(0))
2239 mode |= ATMEL_US_USMODE_ISO7816_T0;
2240 else
2241 mode |= ATMEL_US_USMODE_ISO7816_T1;
2242 } else if (termios->c_cflag & CRTSCTS) {
2243 /* RS232 with hardware handshake (RTS/CTS) */
2244 if (atmel_use_fifo(port) &&
2245 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2246 /*
2247 * with ATMEL_US_USMODE_HWHS set, the controller will
2248 * be able to drive the RTS pin high/low when the RX
2249 * FIFO is above RXFTHRES/below RXFTHRES2.
2250 * It will also disable the transmitter when the CTS
2251 * pin is high.
2252 * This mode is not activated if CTS pin is a GPIO
2253 * because in this case, the transmitter is always
2254 * disabled (there must be an internal pull-up
2255 * responsible for this behaviour).
2256 * If the RTS pin is a GPIO, the controller won't be
2257 * able to drive it according to the FIFO thresholds,
2258 * but it will be handled by the driver.
2259 */
2260 mode |= ATMEL_US_USMODE_HWHS;
2261 } else {
2262 /*
2263 * For platforms without FIFO, the flow control is
2264 * handled by the driver.
2265 */
2266 mode |= ATMEL_US_USMODE_NORMAL;
2267 }
2268 } else {
2269 /* RS232 without hadware handshake */
2270 mode |= ATMEL_US_USMODE_NORMAL;
2271 }
2272
2273 /* set the mode, clock divisor, parity, stop bits and data size */
2274 atmel_uart_writel(port, ATMEL_US_MR, mode);
2275
2276 /*
2277 * when switching the mode, set the RTS line state according to the
2278 * new mode, otherwise keep the former state
2279 */
2280 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2281 unsigned int rts_state;
2282
2283 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2284 /* let the hardware control the RTS line */
2285 rts_state = ATMEL_US_RTSDIS;
2286 } else {
2287 /* force RTS line to low level */
2288 rts_state = ATMEL_US_RTSEN;
2289 }
2290
2291 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2292 }
2293
2294 /*
2295 * Set the baud rate:
2296 * Fractional baudrate allows to setup output frequency more
2297 * accurately. This feature is enabled only when using normal mode.
2298 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2299 * Currently, OVER is always set to 0 so we get
2300 * baudrate = selected clock / (16 * (CD + FP / 8))
2301 * then
2302 * 8 CD + FP = selected clock / (2 * baudrate)
2303 */
2304 if (atmel_port->has_frac_baudrate) {
2305 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2306 cd = div >> 3;
2307 fp = div & ATMEL_US_FP_MASK;
2308 } else {
2309 cd = uart_get_divisor(port, baud);
2310 }
2311
2312 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2313 cd /= 8;
2314 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2315 }
2316 quot = cd | fp << ATMEL_US_FP_OFFSET;
2317
2318 if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
2319 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2320 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2321 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2322 atmel_port->tx_stopped = false;
2323
2324 /* restore interrupts */
2325 atmel_uart_writel(port, ATMEL_US_IER, imr);
2326
2327 /* CTS flow-control and modem-status interrupts */
2328 if (UART_ENABLE_MS(port, termios->c_cflag))
2329 atmel_enable_ms(port);
2330 else
2331 atmel_disable_ms(port);
2332
2333 spin_unlock_irqrestore(&port->lock, flags);
2334}
2335
2336static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2337{
2338 if (termios->c_line == N_PPS) {
2339 port->flags |= UPF_HARDPPS_CD;
2340 spin_lock_irq(&port->lock);
2341 atmel_enable_ms(port);
2342 spin_unlock_irq(&port->lock);
2343 } else {
2344 port->flags &= ~UPF_HARDPPS_CD;
2345 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2346 spin_lock_irq(&port->lock);
2347 atmel_disable_ms(port);
2348 spin_unlock_irq(&port->lock);
2349 }
2350 }
2351}
2352
2353/*
2354 * Return string describing the specified port
2355 */
2356static const char *atmel_type(struct uart_port *port)
2357{
2358 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2359}
2360
2361/*
2362 * Release the memory region(s) being used by 'port'.
2363 */
2364static void atmel_release_port(struct uart_port *port)
2365{
2366 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2367 int size = resource_size(mpdev->resource);
2368
2369 release_mem_region(port->mapbase, size);
2370
2371 if (port->flags & UPF_IOREMAP) {
2372 iounmap(port->membase);
2373 port->membase = NULL;
2374 }
2375}
2376
2377/*
2378 * Request the memory region(s) being used by 'port'.
2379 */
2380static int atmel_request_port(struct uart_port *port)
2381{
2382 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2383 int size = resource_size(mpdev->resource);
2384
2385 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2386 return -EBUSY;
2387
2388 if (port->flags & UPF_IOREMAP) {
2389 port->membase = ioremap(port->mapbase, size);
2390 if (port->membase == NULL) {
2391 release_mem_region(port->mapbase, size);
2392 return -ENOMEM;
2393 }
2394 }
2395
2396 return 0;
2397}
2398
2399/*
2400 * Configure/autoconfigure the port.
2401 */
2402static void atmel_config_port(struct uart_port *port, int flags)
2403{
2404 if (flags & UART_CONFIG_TYPE) {
2405 port->type = PORT_ATMEL;
2406 atmel_request_port(port);
2407 }
2408}
2409
2410/*
2411 * Verify the new serial_struct (for TIOCSSERIAL).
2412 */
2413static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2414{
2415 int ret = 0;
2416 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2417 ret = -EINVAL;
2418 if (port->irq != ser->irq)
2419 ret = -EINVAL;
2420 if (ser->io_type != SERIAL_IO_MEM)
2421 ret = -EINVAL;
2422 if (port->uartclk / 16 != ser->baud_base)
2423 ret = -EINVAL;
2424 if (port->mapbase != (unsigned long)ser->iomem_base)
2425 ret = -EINVAL;
2426 if (port->iobase != ser->port)
2427 ret = -EINVAL;
2428 if (ser->hub6 != 0)
2429 ret = -EINVAL;
2430 return ret;
2431}
2432
2433#ifdef CONFIG_CONSOLE_POLL
2434static int atmel_poll_get_char(struct uart_port *port)
2435{
2436 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2437 cpu_relax();
2438
2439 return atmel_uart_read_char(port);
2440}
2441
2442static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2443{
2444 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2445 cpu_relax();
2446
2447 atmel_uart_write_char(port, ch);
2448}
2449#endif
2450
2451static const struct uart_ops atmel_pops = {
2452 .tx_empty = atmel_tx_empty,
2453 .set_mctrl = atmel_set_mctrl,
2454 .get_mctrl = atmel_get_mctrl,
2455 .stop_tx = atmel_stop_tx,
2456 .start_tx = atmel_start_tx,
2457 .stop_rx = atmel_stop_rx,
2458 .enable_ms = atmel_enable_ms,
2459 .break_ctl = atmel_break_ctl,
2460 .startup = atmel_startup,
2461 .shutdown = atmel_shutdown,
2462 .flush_buffer = atmel_flush_buffer,
2463 .set_termios = atmel_set_termios,
2464 .set_ldisc = atmel_set_ldisc,
2465 .type = atmel_type,
2466 .release_port = atmel_release_port,
2467 .request_port = atmel_request_port,
2468 .config_port = atmel_config_port,
2469 .verify_port = atmel_verify_port,
2470 .pm = atmel_serial_pm,
2471#ifdef CONFIG_CONSOLE_POLL
2472 .poll_get_char = atmel_poll_get_char,
2473 .poll_put_char = atmel_poll_put_char,
2474#endif
2475};
2476
2477/*
2478 * Configure the port from the platform device resource info.
2479 */
2480static int atmel_init_port(struct atmel_uart_port *atmel_port,
2481 struct platform_device *pdev)
2482{
2483 int ret;
2484 struct uart_port *port = &atmel_port->uart;
2485 struct platform_device *mpdev = to_platform_device(pdev->dev.parent);
2486
2487 atmel_init_property(atmel_port, pdev);
2488 atmel_set_ops(port);
2489
2490 uart_get_rs485_mode(&mpdev->dev, &port->rs485);
2491
2492 port->iotype = UPIO_MEM;
2493 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
2494 port->ops = &atmel_pops;
2495 port->fifosize = 1;
2496 port->dev = &pdev->dev;
2497 port->mapbase = mpdev->resource[0].start;
2498 port->irq = mpdev->resource[1].start;
2499 port->rs485_config = atmel_config_rs485;
2500 port->iso7816_config = atmel_config_iso7816;
2501 port->membase = NULL;
2502
2503 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2504
2505 /* for console, the clock could already be configured */
2506 if (!atmel_port->clk) {
2507 atmel_port->clk = clk_get(&mpdev->dev, "usart");
2508 if (IS_ERR(atmel_port->clk)) {
2509 ret = PTR_ERR(atmel_port->clk);
2510 atmel_port->clk = NULL;
2511 return ret;
2512 }
2513 ret = clk_prepare_enable(atmel_port->clk);
2514 if (ret) {
2515 clk_put(atmel_port->clk);
2516 atmel_port->clk = NULL;
2517 return ret;
2518 }
2519 port->uartclk = clk_get_rate(atmel_port->clk);
2520 clk_disable_unprepare(atmel_port->clk);
2521 /* only enable clock when USART is in use */
2522 }
2523
2524 /*
2525 * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or
2526 * ENDTX|TXBUFE
2527 */
2528 if (port->rs485.flags & SER_RS485_ENABLED ||
2529 port->iso7816.flags & SER_ISO7816_ENABLED)
2530 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2531 else if (atmel_use_pdc_tx(port)) {
2532 port->fifosize = PDC_BUFFER_SIZE;
2533 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2534 } else {
2535 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2536 }
2537
2538 return 0;
2539}
2540
2541#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2542static void atmel_console_putchar(struct uart_port *port, int ch)
2543{
2544 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2545 cpu_relax();
2546 atmel_uart_write_char(port, ch);
2547}
2548
2549/*
2550 * Interrupts are disabled on entering
2551 */
2552static void atmel_console_write(struct console *co, const char *s, u_int count)
2553{
2554 struct uart_port *port = &atmel_ports[co->index].uart;
2555 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2556 unsigned int status, imr;
2557 unsigned int pdc_tx;
2558
2559 /*
2560 * First, save IMR and then disable interrupts
2561 */
2562 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2563 atmel_uart_writel(port, ATMEL_US_IDR,
2564 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2565
2566 /* Store PDC transmit status and disable it */
2567 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2568 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2569
2570 /* Make sure that tx path is actually able to send characters */
2571 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2572 atmel_port->tx_stopped = false;
2573
2574 uart_console_write(port, s, count, atmel_console_putchar);
2575
2576 /*
2577 * Finally, wait for transmitter to become empty
2578 * and restore IMR
2579 */
2580 do {
2581 status = atmel_uart_readl(port, ATMEL_US_CSR);
2582 } while (!(status & ATMEL_US_TXRDY));
2583
2584 /* Restore PDC transmit status */
2585 if (pdc_tx)
2586 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2587
2588 /* set interrupts back the way they were */
2589 atmel_uart_writel(port, ATMEL_US_IER, imr);
2590}
2591
2592/*
2593 * If the port was already initialised (eg, by a boot loader),
2594 * try to determine the current setup.
2595 */
2596static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2597 int *parity, int *bits)
2598{
2599 unsigned int mr, quot;
2600
2601 /*
2602 * If the baud rate generator isn't running, the port wasn't
2603 * initialized by the boot loader.
2604 */
2605 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2606 if (!quot)
2607 return;
2608
2609 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2610 if (mr == ATMEL_US_CHRL_8)
2611 *bits = 8;
2612 else
2613 *bits = 7;
2614
2615 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2616 if (mr == ATMEL_US_PAR_EVEN)
2617 *parity = 'e';
2618 else if (mr == ATMEL_US_PAR_ODD)
2619 *parity = 'o';
2620
2621 /*
2622 * The serial core only rounds down when matching this to a
2623 * supported baud rate. Make sure we don't end up slightly
2624 * lower than one of those, as it would make us fall through
2625 * to a much lower baud rate than we really want.
2626 */
2627 *baud = port->uartclk / (16 * (quot - 1));
2628}
2629
2630static int __init atmel_console_setup(struct console *co, char *options)
2631{
2632 int ret;
2633 struct uart_port *port = &atmel_ports[co->index].uart;
2634 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2635 int baud = 115200;
2636 int bits = 8;
2637 int parity = 'n';
2638 int flow = 'n';
2639
2640 if (port->membase == NULL) {
2641 /* Port not initialized yet - delay setup */
2642 return -ENODEV;
2643 }
2644
2645 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2646 if (ret)
2647 return ret;
2648
2649 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2650 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2651 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2652 atmel_port->tx_stopped = false;
2653
2654 if (options)
2655 uart_parse_options(options, &baud, &parity, &bits, &flow);
2656 else
2657 atmel_console_get_options(port, &baud, &parity, &bits);
2658
2659 return uart_set_options(port, co, baud, parity, bits, flow);
2660}
2661
2662static struct uart_driver atmel_uart;
2663
2664static struct console atmel_console = {
2665 .name = ATMEL_DEVICENAME,
2666 .write = atmel_console_write,
2667 .device = uart_console_device,
2668 .setup = atmel_console_setup,
2669 .flags = CON_PRINTBUFFER,
2670 .index = -1,
2671 .data = &atmel_uart,
2672};
2673
2674#define ATMEL_CONSOLE_DEVICE (&atmel_console)
2675
2676static inline bool atmel_is_console_port(struct uart_port *port)
2677{
2678 return port->cons && port->cons->index == port->line;
2679}
2680
2681#else
2682#define ATMEL_CONSOLE_DEVICE NULL
2683
2684static inline bool atmel_is_console_port(struct uart_port *port)
2685{
2686 return false;
2687}
2688#endif
2689
2690static struct uart_driver atmel_uart = {
2691 .owner = THIS_MODULE,
2692 .driver_name = "atmel_serial",
2693 .dev_name = ATMEL_DEVICENAME,
2694 .major = SERIAL_ATMEL_MAJOR,
2695 .minor = MINOR_START,
2696 .nr = ATMEL_MAX_UART,
2697 .cons = ATMEL_CONSOLE_DEVICE,
2698};
2699
2700#ifdef CONFIG_PM
2701static bool atmel_serial_clk_will_stop(void)
2702{
2703#ifdef CONFIG_ARCH_AT91
2704 return at91_suspend_entering_slow_clock();
2705#else
2706 return false;
2707#endif
2708}
2709
2710static int atmel_serial_suspend(struct platform_device *pdev,
2711 pm_message_t state)
2712{
2713 struct uart_port *port = platform_get_drvdata(pdev);
2714 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2715
2716 if (atmel_is_console_port(port) && console_suspend_enabled) {
2717 /* Drain the TX shifter */
2718 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2719 ATMEL_US_TXEMPTY))
2720 cpu_relax();
2721 }
2722
2723 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2724 /* Cache register values as we won't get a full shutdown/startup
2725 * cycle
2726 */
2727 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2728 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2729 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2730 atmel_port->cache.rtor = atmel_uart_readl(port,
2731 atmel_port->rtor);
2732 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2733 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2734 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2735 }
2736
2737 /* we can not wake up if we're running on slow clock */
2738 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2739 if (atmel_serial_clk_will_stop()) {
2740 unsigned long flags;
2741
2742 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2743 atmel_port->suspended = true;
2744 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2745 device_set_wakeup_enable(&pdev->dev, 0);
2746 }
2747
2748 uart_suspend_port(&atmel_uart, port);
2749
2750 return 0;
2751}
2752
2753static int atmel_serial_resume(struct platform_device *pdev)
2754{
2755 struct uart_port *port = platform_get_drvdata(pdev);
2756 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2757 unsigned long flags;
2758
2759 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2760 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2761 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2762 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2763 atmel_uart_writel(port, atmel_port->rtor,
2764 atmel_port->cache.rtor);
2765 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2766
2767 if (atmel_port->fifo_size) {
2768 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2769 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2770 atmel_uart_writel(port, ATMEL_US_FMR,
2771 atmel_port->cache.fmr);
2772 atmel_uart_writel(port, ATMEL_US_FIER,
2773 atmel_port->cache.fimr);
2774 }
2775 atmel_start_rx(port);
2776 }
2777
2778 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2779 if (atmel_port->pending) {
2780 atmel_handle_receive(port, atmel_port->pending);
2781 atmel_handle_status(port, atmel_port->pending,
2782 atmel_port->pending_status);
2783 atmel_handle_transmit(port, atmel_port->pending);
2784 atmel_port->pending = 0;
2785 }
2786 atmel_port->suspended = false;
2787 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2788
2789 uart_resume_port(&atmel_uart, port);
2790 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2791
2792 return 0;
2793}
2794#else
2795#define atmel_serial_suspend NULL
2796#define atmel_serial_resume NULL
2797#endif
2798
2799static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2800 struct platform_device *pdev)
2801{
2802 atmel_port->fifo_size = 0;
2803 atmel_port->rts_low = 0;
2804 atmel_port->rts_high = 0;
2805
2806 if (of_property_read_u32(pdev->dev.of_node,
2807 "atmel,fifo-size",
2808 &atmel_port->fifo_size))
2809 return;
2810
2811 if (!atmel_port->fifo_size)
2812 return;
2813
2814 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2815 atmel_port->fifo_size = 0;
2816 dev_err(&pdev->dev, "Invalid FIFO size\n");
2817 return;
2818 }
2819
2820 /*
2821 * 0 <= rts_low <= rts_high <= fifo_size
2822 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2823 * to flush their internal TX FIFO, commonly up to 16 data, before
2824 * actually stopping to send new data. So we try to set the RTS High
2825 * Threshold to a reasonably high value respecting this 16 data
2826 * empirical rule when possible.
2827 */
2828 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2829 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2830 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2831 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2832
2833 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2834 atmel_port->fifo_size);
2835 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2836 atmel_port->rts_high);
2837 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2838 atmel_port->rts_low);
2839}
2840
2841static int atmel_serial_probe(struct platform_device *pdev)
2842{
2843 struct atmel_uart_port *atmel_port;
2844 struct device_node *np = pdev->dev.parent->of_node;
2845 void *data;
2846 int ret;
2847 bool rs485_enabled;
2848
2849 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2850
2851 /*
2852 * In device tree there is no node with "atmel,at91rm9200-usart-serial"
2853 * as compatible string. This driver is probed by at91-usart mfd driver
2854 * which is just a wrapper over the atmel_serial driver and
2855 * spi-at91-usart driver. All attributes needed by this driver are
2856 * found in of_node of parent.
2857 */
2858 pdev->dev.of_node = np;
2859
2860 ret = of_alias_get_id(np, "serial");
2861 if (ret < 0)
2862 /* port id not found in platform data nor device-tree aliases:
2863 * auto-enumerate it */
2864 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2865
2866 if (ret >= ATMEL_MAX_UART) {
2867 ret = -ENODEV;
2868 goto err;
2869 }
2870
2871 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2872 /* port already in use */
2873 ret = -EBUSY;
2874 goto err;
2875 }
2876
2877 atmel_port = &atmel_ports[ret];
2878 atmel_port->backup_imr = 0;
2879 atmel_port->uart.line = ret;
2880 atmel_serial_probe_fifos(atmel_port, pdev);
2881
2882 atomic_set(&atmel_port->tasklet_shutdown, 0);
2883 spin_lock_init(&atmel_port->lock_suspended);
2884
2885 ret = atmel_init_port(atmel_port, pdev);
2886 if (ret)
2887 goto err_clear_bit;
2888
2889 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2890 if (IS_ERR(atmel_port->gpios)) {
2891 ret = PTR_ERR(atmel_port->gpios);
2892 goto err_clear_bit;
2893 }
2894
2895 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2896 ret = -ENOMEM;
2897 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
2898 sizeof(struct atmel_uart_char),
2899 GFP_KERNEL);
2900 if (!data)
2901 goto err_alloc_ring;
2902 atmel_port->rx_ring.buf = data;
2903 }
2904
2905 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2906
2907 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2908 if (ret)
2909 goto err_add_port;
2910
2911#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2912 if (atmel_is_console_port(&atmel_port->uart)
2913 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2914 /*
2915 * The serial core enabled the clock for us, so undo
2916 * the clk_prepare_enable() in atmel_console_setup()
2917 */
2918 clk_disable_unprepare(atmel_port->clk);
2919 }
2920#endif
2921
2922 device_init_wakeup(&pdev->dev, 1);
2923 platform_set_drvdata(pdev, atmel_port);
2924
2925 /*
2926 * The peripheral clock has been disabled by atmel_init_port():
2927 * enable it before accessing I/O registers
2928 */
2929 clk_prepare_enable(atmel_port->clk);
2930
2931 if (rs485_enabled) {
2932 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2933 ATMEL_US_USMODE_NORMAL);
2934 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2935 ATMEL_US_RTSEN);
2936 }
2937
2938 /*
2939 * Get port name of usart or uart
2940 */
2941 atmel_get_ip_name(&atmel_port->uart);
2942
2943 /*
2944 * The peripheral clock can now safely be disabled till the port
2945 * is used
2946 */
2947 clk_disable_unprepare(atmel_port->clk);
2948
2949 return 0;
2950
2951err_add_port:
2952 kfree(atmel_port->rx_ring.buf);
2953 atmel_port->rx_ring.buf = NULL;
2954err_alloc_ring:
2955 if (!atmel_is_console_port(&atmel_port->uart)) {
2956 clk_put(atmel_port->clk);
2957 atmel_port->clk = NULL;
2958 }
2959err_clear_bit:
2960 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2961err:
2962 return ret;
2963}
2964
2965/*
2966 * Even if the driver is not modular, it makes sense to be able to
2967 * unbind a device: there can be many bound devices, and there are
2968 * situations where dynamic binding and unbinding can be useful.
2969 *
2970 * For example, a connected device can require a specific firmware update
2971 * protocol that needs bitbanging on IO lines, but use the regular serial
2972 * port in the normal case.
2973 */
2974static int atmel_serial_remove(struct platform_device *pdev)
2975{
2976 struct uart_port *port = platform_get_drvdata(pdev);
2977 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2978 int ret = 0;
2979
2980 tasklet_kill(&atmel_port->tasklet_rx);
2981 tasklet_kill(&atmel_port->tasklet_tx);
2982
2983 device_init_wakeup(&pdev->dev, 0);
2984
2985 ret = uart_remove_one_port(&atmel_uart, port);
2986
2987 kfree(atmel_port->rx_ring.buf);
2988
2989 /* "port" is allocated statically, so we shouldn't free it */
2990
2991 clear_bit(port->line, atmel_ports_in_use);
2992
2993 clk_put(atmel_port->clk);
2994 atmel_port->clk = NULL;
2995 pdev->dev.of_node = NULL;
2996
2997 return ret;
2998}
2999
3000static struct platform_driver atmel_serial_driver = {
3001 .probe = atmel_serial_probe,
3002 .remove = atmel_serial_remove,
3003 .suspend = atmel_serial_suspend,
3004 .resume = atmel_serial_resume,
3005 .driver = {
3006 .name = "atmel_usart_serial",
3007 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
3008 },
3009};
3010
3011static int __init atmel_serial_init(void)
3012{
3013 int ret;
3014
3015 ret = uart_register_driver(&atmel_uart);
3016 if (ret)
3017 return ret;
3018
3019 ret = platform_driver_register(&atmel_serial_driver);
3020 if (ret)
3021 uart_unregister_driver(&atmel_uart);
3022
3023 return ret;
3024}
3025device_initcall(atmel_serial_init);