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1/*
2 * Device Tree Source for AM4372 SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/bus/ti-sysc.h>
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/clock/am4.h>
15
16/ {
17 compatible = "ti,am4372", "ti,am43";
18 interrupt-parent = <&wakeupgen>;
19 #address-cells = <1>;
20 #size-cells = <1>;
21 chosen { };
22
23 memory@0 {
24 device_type = "memory";
25 reg = <0 0>;
26 };
27
28 aliases {
29 i2c0 = &i2c0;
30 i2c1 = &i2c1;
31 i2c2 = &i2c2;
32 serial0 = &uart0;
33 serial1 = &uart1;
34 serial2 = &uart2;
35 serial3 = &uart3;
36 serial4 = &uart4;
37 serial5 = &uart5;
38 ethernet0 = &cpsw_port1;
39 ethernet1 = &cpsw_port2;
40 spi0 = &qspi;
41 };
42
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46 cpu: cpu@0 {
47 compatible = "arm,cortex-a9";
48 enable-method = "ti,am4372";
49 device_type = "cpu";
50 reg = <0>;
51
52 clocks = <&dpll_mpu_ck>;
53 clock-names = "cpu";
54
55 operating-points-v2 = <&cpu0_opp_table>;
56
57 clock-latency = <300000>; /* From omap-cpufreq driver */
58 cpu-idle-states = <&mpu_gate>;
59 };
60
61 idle-states {
62 mpu_gate: mpu_gate {
63 compatible = "arm,idle-state";
64 entry-latency-us = <40>;
65 exit-latency-us = <100>;
66 min-residency-us = <300>;
67 local-timer-stop;
68 };
69 };
70 };
71
72 cpu0_opp_table: opp-table {
73 compatible = "operating-points-v2-ti-cpu";
74 syscon = <&scm_conf>;
75
76 opp50-300000000 {
77 opp-hz = /bits/ 64 <300000000>;
78 opp-microvolt = <950000 931000 969000>;
79 opp-supported-hw = <0xFF 0x01>;
80 opp-suspend;
81 };
82
83 opp100-600000000 {
84 opp-hz = /bits/ 64 <600000000>;
85 opp-microvolt = <1100000 1078000 1122000>;
86 opp-supported-hw = <0xFF 0x04>;
87 };
88
89 opp120-720000000 {
90 opp-hz = /bits/ 64 <720000000>;
91 opp-microvolt = <1200000 1176000 1224000>;
92 opp-supported-hw = <0xFF 0x08>;
93 };
94
95 oppturbo-800000000 {
96 opp-hz = /bits/ 64 <800000000>;
97 opp-microvolt = <1260000 1234800 1285200>;
98 opp-supported-hw = <0xFF 0x10>;
99 };
100
101 oppnitro-1000000000 {
102 opp-hz = /bits/ 64 <1000000000>;
103 opp-microvolt = <1325000 1298500 1351500>;
104 opp-supported-hw = <0xFF 0x20>;
105 };
106 };
107
108 soc {
109 compatible = "ti,omap-infra";
110 };
111
112 gic: interrupt-controller@48241000 {
113 compatible = "arm,cortex-a9-gic";
114 interrupt-controller;
115 #interrupt-cells = <3>;
116 reg = <0x48241000 0x1000>,
117 <0x48240100 0x0100>;
118 interrupt-parent = <&gic>;
119 };
120
121 wakeupgen: interrupt-controller@48281000 {
122 compatible = "ti,omap4-wugen-mpu";
123 interrupt-controller;
124 #interrupt-cells = <3>;
125 reg = <0x48281000 0x1000>;
126 interrupt-parent = <&gic>;
127 };
128
129 scu: scu@48240000 {
130 compatible = "arm,cortex-a9-scu";
131 reg = <0x48240000 0x100>;
132 };
133
134 global_timer: timer@48240200 {
135 compatible = "arm,cortex-a9-global-timer";
136 reg = <0x48240200 0x100>;
137 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
138 interrupt-parent = <&gic>;
139 clocks = <&mpu_periphclk>;
140 };
141
142 local_timer: timer@48240600 {
143 compatible = "arm,cortex-a9-twd-timer";
144 reg = <0x48240600 0x100>;
145 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
146 interrupt-parent = <&gic>;
147 clocks = <&mpu_periphclk>;
148 };
149
150 cache-controller@48242000 {
151 compatible = "arm,pl310-cache";
152 reg = <0x48242000 0x1000>;
153 cache-unified;
154 cache-level = <2>;
155 };
156
157 ocp@44000000 {
158 compatible = "simple-pm-bus";
159 power-domains = <&prm_per>;
160 clocks = <&l3_clkctrl AM4_L3_L3_MAIN_CLKCTRL 0>;
161 clock-names = "fck";
162 #address-cells = <1>;
163 #size-cells = <1>;
164 ranges;
165 ti,no-idle;
166
167 l3-noc@44000000 {
168 compatible = "ti,am4372-l3-noc";
169 reg = <0x44000000 0x400000>,
170 <0x44800000 0x400000>;
171 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
173 };
174
175 l4_wkup: interconnect@44c00000 {
176 };
177 l4_per: interconnect@48000000 {
178 };
179 l4_fast: interconnect@4a000000 {
180 };
181
182 target-module@4c000000 {
183 compatible = "ti,sysc-omap4-simple", "ti,sysc";
184 reg = <0x4c000000 0x4>;
185 reg-names = "rev";
186 clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>;
187 clock-names = "fck";
188 ti,no-idle;
189 #address-cells = <1>;
190 #size-cells = <1>;
191 ranges = <0x0 0x4c000000 0x1000000>;
192
193 emif: emif@0 {
194 compatible = "ti,emif-am4372";
195 reg = <0 0x1000000>;
196 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
197 sram = <&pm_sram_code
198 &pm_sram_data>;
199 };
200 };
201
202 target-module@49000000 {
203 compatible = "ti,sysc-omap4", "ti,sysc";
204 reg = <0x49000000 0x4>;
205 reg-names = "rev";
206 clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>;
207 clock-names = "fck";
208 #address-cells = <1>;
209 #size-cells = <1>;
210 ranges = <0x0 0x49000000 0x10000>;
211
212 edma: dma@0 {
213 compatible = "ti,edma3-tpcc";
214 reg = <0 0x10000>;
215 reg-names = "edma3_cc";
216 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
219 interrupt-names = "edma3_ccint", "edma3_mperr",
220 "edma3_ccerrint";
221 dma-requests = <64>;
222 #dma-cells = <2>;
223
224 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
225 <&edma_tptc2 0>;
226
227 ti,edma-memcpy-channels = <58 59>;
228 };
229 };
230
231 target-module@49800000 {
232 compatible = "ti,sysc-omap4", "ti,sysc";
233 reg = <0x49800000 0x4>,
234 <0x49800010 0x4>;
235 reg-names = "rev", "sysc";
236 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
237 ti,sysc-midle = <SYSC_IDLE_FORCE>;
238 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
239 <SYSC_IDLE_SMART>;
240 clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>;
241 clock-names = "fck";
242 #address-cells = <1>;
243 #size-cells = <1>;
244 ranges = <0x0 0x49800000 0x100000>;
245
246 edma_tptc0: dma@0 {
247 compatible = "ti,edma3-tptc";
248 reg = <0 0x100000>;
249 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
250 interrupt-names = "edma3_tcerrint";
251 };
252 };
253
254 target-module@49900000 {
255 compatible = "ti,sysc-omap4", "ti,sysc";
256 reg = <0x49900000 0x4>,
257 <0x49900010 0x4>;
258 reg-names = "rev", "sysc";
259 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
260 ti,sysc-midle = <SYSC_IDLE_FORCE>;
261 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
262 <SYSC_IDLE_SMART>;
263 clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>;
264 clock-names = "fck";
265 #address-cells = <1>;
266 #size-cells = <1>;
267 ranges = <0x0 0x49900000 0x100000>;
268
269 edma_tptc1: dma@0 {
270 compatible = "ti,edma3-tptc";
271 reg = <0 0x100000>;
272 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
273 interrupt-names = "edma3_tcerrint";
274 };
275 };
276
277 target-module@49a00000 {
278 compatible = "ti,sysc-omap4", "ti,sysc";
279 reg = <0x49a00000 0x4>,
280 <0x49a00010 0x4>;
281 reg-names = "rev", "sysc";
282 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
283 ti,sysc-midle = <SYSC_IDLE_FORCE>;
284 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
285 <SYSC_IDLE_SMART>;
286 clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>;
287 clock-names = "fck";
288 #address-cells = <1>;
289 #size-cells = <1>;
290 ranges = <0x0 0x49a00000 0x100000>;
291
292 edma_tptc2: dma@0 {
293 compatible = "ti,edma3-tptc";
294 reg = <0 0x100000>;
295 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
296 interrupt-names = "edma3_tcerrint";
297 };
298 };
299
300 target-module@47810000 {
301 compatible = "ti,sysc-omap2", "ti,sysc";
302 reg = <0x478102fc 0x4>,
303 <0x47810110 0x4>,
304 <0x47810114 0x4>;
305 reg-names = "rev", "sysc", "syss";
306 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
307 SYSC_OMAP2_ENAWAKEUP |
308 SYSC_OMAP2_SOFTRESET |
309 SYSC_OMAP2_AUTOIDLE)>;
310 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
311 <SYSC_IDLE_NO>,
312 <SYSC_IDLE_SMART>;
313 ti,syss-mask = <1>;
314 clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>;
315 clock-names = "fck";
316 #address-cells = <1>;
317 #size-cells = <1>;
318 ranges = <0x0 0x47810000 0x1000>;
319
320 mmc3: mmc@0 {
321 compatible = "ti,am437-sdhci";
322 ti,needs-special-reset;
323 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
324 reg = <0x0 0x1000>;
325 status = "disabled";
326 };
327 };
328
329 sham_target: target-module@53100000 {
330 compatible = "ti,sysc-omap3-sham", "ti,sysc";
331 reg = <0x53100100 0x4>,
332 <0x53100110 0x4>,
333 <0x53100114 0x4>;
334 reg-names = "rev", "sysc", "syss";
335 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
336 SYSC_OMAP2_AUTOIDLE)>;
337 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
338 <SYSC_IDLE_NO>,
339 <SYSC_IDLE_SMART>;
340 ti,syss-mask = <1>;
341 /* Domains (P, C): per_pwrdm, l3_clkdm */
342 clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
343 clock-names = "fck";
344 #address-cells = <1>;
345 #size-cells = <1>;
346 ranges = <0x0 0x53100000 0x1000>;
347
348 sham: sham@0 {
349 compatible = "ti,omap5-sham";
350 reg = <0 0x300>;
351 dmas = <&edma 36 0>;
352 dma-names = "rx";
353 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
354 };
355 };
356
357 aes_target: target-module@53501000 {
358 compatible = "ti,sysc-omap2", "ti,sysc";
359 reg = <0x53501080 0x4>,
360 <0x53501084 0x4>,
361 <0x53501088 0x4>;
362 reg-names = "rev", "sysc", "syss";
363 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
364 SYSC_OMAP2_AUTOIDLE)>;
365 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
366 <SYSC_IDLE_NO>,
367 <SYSC_IDLE_SMART>,
368 <SYSC_IDLE_SMART_WKUP>;
369 ti,syss-mask = <1>;
370 /* Domains (P, C): per_pwrdm, l3_clkdm */
371 clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
372 clock-names = "fck";
373 #address-cells = <1>;
374 #size-cells = <1>;
375 ranges = <0x0 0x53501000 0x1000>;
376
377 aes: aes@0 {
378 compatible = "ti,omap4-aes";
379 reg = <0 0xa0>;
380 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
381 dmas = <&edma 6 0>,
382 <&edma 5 0>;
383 dma-names = "tx", "rx";
384 };
385 };
386
387 des_target: target-module@53701000 {
388 compatible = "ti,sysc-omap2", "ti,sysc";
389 reg = <0x53701030 0x4>,
390 <0x53701034 0x4>,
391 <0x53701038 0x4>;
392 reg-names = "rev", "sysc", "syss";
393 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
394 SYSC_OMAP2_AUTOIDLE)>;
395 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
396 <SYSC_IDLE_NO>,
397 <SYSC_IDLE_SMART>,
398 <SYSC_IDLE_SMART_WKUP>;
399 ti,syss-mask = <1>;
400 /* Domains (P, C): per_pwrdm, l3_clkdm */
401 clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
402 clock-names = "fck";
403 #address-cells = <1>;
404 #size-cells = <1>;
405 ranges = <0 0x53701000 0x1000>;
406
407 des: des@0 {
408 compatible = "ti,omap4-des";
409 reg = <0 0xa0>;
410 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
411 dmas = <&edma 34 0>,
412 <&edma 33 0>;
413 dma-names = "tx", "rx";
414 };
415 };
416
417 pruss_tm: target-module@54400000 {
418 compatible = "ti,sysc-pruss", "ti,sysc";
419 reg = <0x54426000 0x4>,
420 <0x54426004 0x4>;
421 reg-names = "rev", "sysc";
422 ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
423 SYSC_PRUSS_SUB_MWAIT)>;
424 ti,sysc-midle = <SYSC_IDLE_FORCE>,
425 <SYSC_IDLE_NO>,
426 <SYSC_IDLE_SMART>;
427 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
428 <SYSC_IDLE_NO>,
429 <SYSC_IDLE_SMART>;
430 clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;
431 clock-names = "fck";
432 resets = <&prm_per 1>;
433 reset-names = "rstctrl";
434 #address-cells = <1>;
435 #size-cells = <1>;
436 ranges = <0x0 0x54400000 0x80000>;
437 };
438
439 target-module@50000000 {
440 compatible = "ti,sysc-omap2", "ti,sysc";
441 reg = <0x50000000 4>,
442 <0x50000010 4>,
443 <0x50000014 4>;
444 reg-names = "rev", "sysc", "syss";
445 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
446 <SYSC_IDLE_NO>,
447 <SYSC_IDLE_SMART>;
448 ti,syss-mask = <1>;
449 clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>;
450 clock-names = "fck";
451 #address-cells = <1>;
452 #size-cells = <1>;
453 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
454 <0x00000000 0x00000000 0x40000000>; /* data */
455
456 gpmc: gpmc@50000000 {
457 compatible = "ti,am3352-gpmc";
458 dmas = <&edma 52 0>;
459 dma-names = "rxtx";
460 clocks = <&l3s_gclk>;
461 clock-names = "fck";
462 reg = <0x50000000 0x2000>;
463 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
464 gpmc,num-cs = <7>;
465 gpmc,num-waitpins = <2>;
466 #address-cells = <2>;
467 #size-cells = <1>;
468 interrupt-controller;
469 #interrupt-cells = <2>;
470 gpio-controller;
471 #gpio-cells = <2>;
472 status = "disabled";
473 };
474 };
475
476 target-module@47900000 {
477 compatible = "ti,sysc-omap4", "ti,sysc";
478 reg = <0x47900000 0x4>,
479 <0x47900010 0x4>;
480 reg-names = "rev", "sysc";
481 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
482 <SYSC_IDLE_NO>,
483 <SYSC_IDLE_SMART>,
484 <SYSC_IDLE_SMART_WKUP>;
485 clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
486 clock-names = "fck";
487 #address-cells = <1>;
488 #size-cells = <1>;
489 ranges = <0x0 0x47900000 0x1000>,
490 <0x30000000 0x30000000 0x4000000>;
491
492 qspi: spi@0 {
493 compatible = "ti,am4372-qspi";
494 reg = <0 0x100>,
495 <0x30000000 0x4000000>;
496 reg-names = "qspi_base", "qspi_mmap";
497 clocks = <&dpll_per_m2_div4_ck>;
498 clock-names = "fck";
499 #address-cells = <1>;
500 #size-cells = <0>;
501 interrupts = <0 138 0x4>;
502 num-cs = <4>;
503 };
504 };
505
506 target-module@40300000 {
507 compatible = "ti,sysc-omap4-simple", "ti,sysc";
508 clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>;
509 clock-names = "fck";
510 ti,no-idle;
511 #address-cells = <1>;
512 #size-cells = <1>;
513 ranges = <0 0x40300000 0x40000>;
514
515 ocmcram: sram@0 {
516 compatible = "mmio-sram";
517 reg = <0 0x40000>; /* 256k */
518 ranges = <0 0 0x40000>;
519 #address-cells = <1>;
520 #size-cells = <1>;
521
522 pm_sram_code: pm-code-sram@0 {
523 compatible = "ti,sram";
524 reg = <0x0 0x1000>;
525 protect-exec;
526 };
527
528 pm_sram_data: pm-data-sram@1000 {
529 compatible = "ti,sram";
530 reg = <0x1000 0x1000>;
531 pool;
532 };
533 };
534 };
535
536 target-module@56000000 {
537 compatible = "ti,sysc-omap4", "ti,sysc";
538 reg = <0x5600fe00 0x4>,
539 <0x5600fe10 0x4>;
540 reg-names = "rev", "sysc";
541 ti,sysc-midle = <SYSC_IDLE_FORCE>,
542 <SYSC_IDLE_NO>,
543 <SYSC_IDLE_SMART>;
544 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
545 <SYSC_IDLE_NO>,
546 <SYSC_IDLE_SMART>;
547 clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
548 clock-names = "fck";
549 power-domains = <&prm_gfx>;
550 resets = <&prm_gfx 0>;
551 reset-names = "rstctrl";
552 #address-cells = <1>;
553 #size-cells = <1>;
554 ranges = <0 0x56000000 0x1000000>;
555 };
556 };
557};
558
559#include "am437x-l4.dtsi"
560#include "am43xx-clocks.dtsi"
561
562&prcm {
563 prm_mpu: prm@300 {
564 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
565 reg = <0x300 0x100>;
566 #power-domain-cells = <0>;
567 };
568
569 prm_gfx: prm@400 {
570 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
571 reg = <0x400 0x100>;
572 #power-domain-cells = <0>;
573 #reset-cells = <1>;
574 };
575
576 prm_rtc: prm@500 {
577 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
578 reg = <0x500 0x100>;
579 #power-domain-cells = <0>;
580 };
581
582 prm_tamper: prm@600 {
583 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
584 reg = <0x600 0x100>;
585 #power-domain-cells = <0>;
586 };
587
588 prm_cefuse: prm@700 {
589 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
590 reg = <0x700 0x100>;
591 #power-domain-cells = <0>;
592 };
593
594 prm_per: prm@800 {
595 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
596 reg = <0x800 0x100>;
597 #reset-cells = <1>;
598 #power-domain-cells = <0>;
599 };
600
601 prm_wkup: prm@2000 {
602 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
603 reg = <0x2000 0x100>;
604 #reset-cells = <1>;
605 #power-domain-cells = <0>;
606 };
607
608 prm_device: prm@4000 {
609 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
610 reg = <0x4000 0x100>;
611 #reset-cells = <1>;
612 };
613};
614
615/* Preferred always-on timer for clocksource */
616&timer1_target {
617 ti,no-reset-on-init;
618 ti,no-idle;
619 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>,
620 <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
621 clock-names = "fck", "ick";
622 timer@0 {
623 assigned-clocks = <&timer1_fck>;
624 assigned-clock-parents = <&sys_clkin_ck>;
625 };
626};
627
628/* Preferred timer for clockevent */
629&timer2_target {
630 ti,no-reset-on-init;
631 ti,no-idle;
632 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>,
633 <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>;
634 clock-names = "fck", "ick";
635 timer@0 {
636 assigned-clocks = <&timer2_fck>;
637 assigned-clock-parents = <&sys_clkin_ck>;
638 };
639};
1/*
2 * Device Tree Source for AM4372 SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/clock/am4.h>
14
15/ {
16 compatible = "ti,am4372", "ti,am43";
17 interrupt-parent = <&wakeupgen>;
18 #address-cells = <1>;
19 #size-cells = <1>;
20 chosen { };
21
22 memory@0 {
23 device_type = "memory";
24 reg = <0 0>;
25 };
26
27 aliases {
28 i2c0 = &i2c0;
29 i2c1 = &i2c1;
30 i2c2 = &i2c2;
31 serial0 = &uart0;
32 serial1 = &uart1;
33 serial2 = &uart2;
34 serial3 = &uart3;
35 serial4 = &uart4;
36 serial5 = &uart5;
37 ethernet0 = &cpsw_emac0;
38 ethernet1 = &cpsw_emac1;
39 spi0 = &qspi;
40 };
41
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45 cpu: cpu@0 {
46 compatible = "arm,cortex-a9";
47 device_type = "cpu";
48 reg = <0>;
49
50 clocks = <&dpll_mpu_ck>;
51 clock-names = "cpu";
52
53 operating-points-v2 = <&cpu0_opp_table>;
54
55 clock-latency = <300000>; /* From omap-cpufreq driver */
56 };
57 };
58
59 cpu0_opp_table: opp-table {
60 compatible = "operating-points-v2-ti-cpu";
61 syscon = <&scm_conf>;
62
63 opp50-300000000 {
64 opp-hz = /bits/ 64 <300000000>;
65 opp-microvolt = <950000 931000 969000>;
66 opp-supported-hw = <0xFF 0x01>;
67 opp-suspend;
68 };
69
70 opp100-600000000 {
71 opp-hz = /bits/ 64 <600000000>;
72 opp-microvolt = <1100000 1078000 1122000>;
73 opp-supported-hw = <0xFF 0x04>;
74 };
75
76 opp120-720000000 {
77 opp-hz = /bits/ 64 <720000000>;
78 opp-microvolt = <1200000 1176000 1224000>;
79 opp-supported-hw = <0xFF 0x08>;
80 };
81
82 oppturbo-800000000 {
83 opp-hz = /bits/ 64 <800000000>;
84 opp-microvolt = <1260000 1234800 1285200>;
85 opp-supported-hw = <0xFF 0x10>;
86 };
87
88 oppnitro-1000000000 {
89 opp-hz = /bits/ 64 <1000000000>;
90 opp-microvolt = <1325000 1298500 1351500>;
91 opp-supported-hw = <0xFF 0x20>;
92 };
93 };
94
95 soc {
96 compatible = "ti,omap-infra";
97 mpu {
98 compatible = "ti,omap4-mpu";
99 ti,hwmods = "mpu";
100 pm-sram = <&pm_sram_code
101 &pm_sram_data>;
102 };
103 };
104
105 gic: interrupt-controller@48241000 {
106 compatible = "arm,cortex-a9-gic";
107 interrupt-controller;
108 #interrupt-cells = <3>;
109 reg = <0x48241000 0x1000>,
110 <0x48240100 0x0100>;
111 interrupt-parent = <&gic>;
112 };
113
114 wakeupgen: interrupt-controller@48281000 {
115 compatible = "ti,omap4-wugen-mpu";
116 interrupt-controller;
117 #interrupt-cells = <3>;
118 reg = <0x48281000 0x1000>;
119 interrupt-parent = <&gic>;
120 };
121
122 scu: scu@48240000 {
123 compatible = "arm,cortex-a9-scu";
124 reg = <0x48240000 0x100>;
125 };
126
127 global_timer: timer@48240200 {
128 compatible = "arm,cortex-a9-global-timer";
129 reg = <0x48240200 0x100>;
130 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
131 interrupt-parent = <&gic>;
132 clocks = <&mpu_periphclk>;
133 };
134
135 local_timer: timer@48240600 {
136 compatible = "arm,cortex-a9-twd-timer";
137 reg = <0x48240600 0x100>;
138 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
139 interrupt-parent = <&gic>;
140 clocks = <&mpu_periphclk>;
141 };
142
143 l2-cache-controller@48242000 {
144 compatible = "arm,pl310-cache";
145 reg = <0x48242000 0x1000>;
146 cache-unified;
147 cache-level = <2>;
148 };
149
150 ocp@44000000 {
151 compatible = "ti,am4372-l3-noc", "simple-bus";
152 #address-cells = <1>;
153 #size-cells = <1>;
154 ranges;
155 ti,hwmods = "l3_main";
156 ti,no-idle;
157 reg = <0x44000000 0x400000
158 0x44800000 0x400000>;
159 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
161
162 l4_wkup: l4_wkup@44c00000 {
163 compatible = "ti,am4-l4-wkup", "simple-bus";
164 #address-cells = <1>;
165 #size-cells = <1>;
166 ranges = <0 0x44c00000 0x287000>;
167
168 wkup_m3: wkup_m3@100000 {
169 compatible = "ti,am4372-wkup-m3";
170 reg = <0x100000 0x4000>,
171 <0x180000 0x2000>;
172 reg-names = "umem", "dmem";
173 ti,hwmods = "wkup_m3";
174 ti,pm-firmware = "am335x-pm-firmware.elf";
175 };
176
177 prcm: prcm@1f0000 {
178 compatible = "ti,am4-prcm", "simple-bus";
179 reg = <0x1f0000 0x11000>;
180 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
181 #address-cells = <1>;
182 #size-cells = <1>;
183 ranges = <0 0x1f0000 0x11000>;
184
185 prcm_clocks: clocks {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 };
189
190 prcm_clockdomains: clockdomains {
191 };
192 };
193
194 scm: scm@210000 {
195 compatible = "ti,am4-scm", "simple-bus";
196 reg = <0x210000 0x4000>;
197 #address-cells = <1>;
198 #size-cells = <1>;
199 ranges = <0 0x210000 0x4000>;
200
201 am43xx_pinmux: pinmux@800 {
202 compatible = "ti,am437-padconf",
203 "pinctrl-single";
204 reg = <0x800 0x31c>;
205 #address-cells = <1>;
206 #size-cells = <0>;
207 #pinctrl-cells = <1>;
208 #interrupt-cells = <1>;
209 interrupt-controller;
210 pinctrl-single,register-width = <32>;
211 pinctrl-single,function-mask = <0xffffffff>;
212 };
213
214 scm_conf: scm_conf@0 {
215 compatible = "syscon";
216 reg = <0x0 0x800>;
217 #address-cells = <1>;
218 #size-cells = <1>;
219
220 scm_clocks: clocks {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 };
224 };
225
226 wkup_m3_ipc: wkup_m3_ipc@1324 {
227 compatible = "ti,am4372-wkup-m3-ipc";
228 reg = <0x1324 0x44>;
229 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
230 ti,rproc = <&wkup_m3>;
231 mboxes = <&mailbox &mbox_wkupm3>;
232 };
233
234 edma_xbar: dma-router@f90 {
235 compatible = "ti,am335x-edma-crossbar";
236 reg = <0xf90 0x40>;
237 #dma-cells = <3>;
238 dma-requests = <64>;
239 dma-masters = <&edma>;
240 };
241
242 scm_clockdomains: clockdomains {
243 };
244 };
245 };
246
247 emif: emif@4c000000 {
248 compatible = "ti,emif-am4372";
249 reg = <0x4c000000 0x1000000>;
250 ti,hwmods = "emif";
251 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
252 ti,no-idle;
253 sram = <&pm_sram_code
254 &pm_sram_data>;
255 };
256
257 edma: edma@49000000 {
258 compatible = "ti,edma3-tpcc";
259 ti,hwmods = "tpcc";
260 reg = <0x49000000 0x10000>;
261 reg-names = "edma3_cc";
262 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
265 interrupt-names = "edma3_ccint", "edma3_mperr",
266 "edma3_ccerrint";
267 dma-requests = <64>;
268 #dma-cells = <2>;
269
270 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
271 <&edma_tptc2 0>;
272
273 ti,edma-memcpy-channels = <58 59>;
274 };
275
276 edma_tptc0: tptc@49800000 {
277 compatible = "ti,edma3-tptc";
278 ti,hwmods = "tptc0";
279 reg = <0x49800000 0x100000>;
280 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
281 interrupt-names = "edma3_tcerrint";
282 };
283
284 edma_tptc1: tptc@49900000 {
285 compatible = "ti,edma3-tptc";
286 ti,hwmods = "tptc1";
287 reg = <0x49900000 0x100000>;
288 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
289 interrupt-names = "edma3_tcerrint";
290 };
291
292 edma_tptc2: tptc@49a00000 {
293 compatible = "ti,edma3-tptc";
294 ti,hwmods = "tptc2";
295 reg = <0x49a00000 0x100000>;
296 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
297 interrupt-names = "edma3_tcerrint";
298 };
299
300 uart0: serial@44e09000 {
301 compatible = "ti,am4372-uart","ti,omap2-uart";
302 reg = <0x44e09000 0x2000>;
303 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
304 ti,hwmods = "uart1";
305 };
306
307 uart1: serial@48022000 {
308 compatible = "ti,am4372-uart","ti,omap2-uart";
309 reg = <0x48022000 0x2000>;
310 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
311 ti,hwmods = "uart2";
312 status = "disabled";
313 };
314
315 uart2: serial@48024000 {
316 compatible = "ti,am4372-uart","ti,omap2-uart";
317 reg = <0x48024000 0x2000>;
318 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
319 ti,hwmods = "uart3";
320 status = "disabled";
321 };
322
323 uart3: serial@481a6000 {
324 compatible = "ti,am4372-uart","ti,omap2-uart";
325 reg = <0x481a6000 0x2000>;
326 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
327 ti,hwmods = "uart4";
328 status = "disabled";
329 };
330
331 uart4: serial@481a8000 {
332 compatible = "ti,am4372-uart","ti,omap2-uart";
333 reg = <0x481a8000 0x2000>;
334 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
335 ti,hwmods = "uart5";
336 status = "disabled";
337 };
338
339 uart5: serial@481aa000 {
340 compatible = "ti,am4372-uart","ti,omap2-uart";
341 reg = <0x481aa000 0x2000>;
342 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
343 ti,hwmods = "uart6";
344 status = "disabled";
345 };
346
347 mailbox: mailbox@480c8000 {
348 compatible = "ti,omap4-mailbox";
349 reg = <0x480C8000 0x200>;
350 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
351 ti,hwmods = "mailbox";
352 #mbox-cells = <1>;
353 ti,mbox-num-users = <4>;
354 ti,mbox-num-fifos = <8>;
355 mbox_wkupm3: wkup_m3 {
356 ti,mbox-send-noirq;
357 ti,mbox-tx = <0 0 0>;
358 ti,mbox-rx = <0 0 3>;
359 };
360 };
361
362 timer1: timer@44e31000 {
363 compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
364 reg = <0x44e31000 0x400>;
365 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
366 ti,timer-alwon;
367 ti,hwmods = "timer1";
368 clocks = <&timer1_fck>;
369 clock-names = "fck";
370 };
371
372 timer2: timer@48040000 {
373 compatible = "ti,am4372-timer","ti,am335x-timer";
374 reg = <0x48040000 0x400>;
375 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
376 ti,hwmods = "timer2";
377 clocks = <&timer2_fck>;
378 clock-names = "fck";
379 };
380
381 timer3: timer@48042000 {
382 compatible = "ti,am4372-timer","ti,am335x-timer";
383 reg = <0x48042000 0x400>;
384 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
385 ti,hwmods = "timer3";
386 status = "disabled";
387 };
388
389 timer4: timer@48044000 {
390 compatible = "ti,am4372-timer","ti,am335x-timer";
391 reg = <0x48044000 0x400>;
392 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
393 ti,timer-pwm;
394 ti,hwmods = "timer4";
395 status = "disabled";
396 };
397
398 timer5: timer@48046000 {
399 compatible = "ti,am4372-timer","ti,am335x-timer";
400 reg = <0x48046000 0x400>;
401 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
402 ti,timer-pwm;
403 ti,hwmods = "timer5";
404 status = "disabled";
405 };
406
407 timer6: timer@48048000 {
408 compatible = "ti,am4372-timer","ti,am335x-timer";
409 reg = <0x48048000 0x400>;
410 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
411 ti,timer-pwm;
412 ti,hwmods = "timer6";
413 status = "disabled";
414 };
415
416 timer7: timer@4804a000 {
417 compatible = "ti,am4372-timer","ti,am335x-timer";
418 reg = <0x4804a000 0x400>;
419 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
420 ti,timer-pwm;
421 ti,hwmods = "timer7";
422 status = "disabled";
423 };
424
425 timer8: timer@481c1000 {
426 compatible = "ti,am4372-timer","ti,am335x-timer";
427 reg = <0x481c1000 0x400>;
428 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
429 ti,hwmods = "timer8";
430 status = "disabled";
431 };
432
433 timer9: timer@4833d000 {
434 compatible = "ti,am4372-timer","ti,am335x-timer";
435 reg = <0x4833d000 0x400>;
436 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
437 ti,hwmods = "timer9";
438 status = "disabled";
439 };
440
441 timer10: timer@4833f000 {
442 compatible = "ti,am4372-timer","ti,am335x-timer";
443 reg = <0x4833f000 0x400>;
444 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
445 ti,hwmods = "timer10";
446 status = "disabled";
447 };
448
449 timer11: timer@48341000 {
450 compatible = "ti,am4372-timer","ti,am335x-timer";
451 reg = <0x48341000 0x400>;
452 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
453 ti,hwmods = "timer11";
454 status = "disabled";
455 };
456
457 counter32k: counter@44e86000 {
458 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
459 reg = <0x44e86000 0x40>;
460 ti,hwmods = "counter_32k";
461 };
462
463 rtc: rtc@44e3e000 {
464 compatible = "ti,am4372-rtc", "ti,am3352-rtc",
465 "ti,da830-rtc";
466 reg = <0x44e3e000 0x1000>;
467 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
468 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
469 ti,hwmods = "rtc";
470 clocks = <&clk_32768_ck>;
471 clock-names = "int-clk";
472 status = "disabled";
473 };
474
475 wdt: wdt@44e35000 {
476 compatible = "ti,am4372-wdt","ti,omap3-wdt";
477 reg = <0x44e35000 0x1000>;
478 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
479 ti,hwmods = "wd_timer2";
480 };
481
482 gpio0: gpio@44e07000 {
483 compatible = "ti,am4372-gpio","ti,omap4-gpio";
484 reg = <0x44e07000 0x1000>;
485 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
486 gpio-controller;
487 #gpio-cells = <2>;
488 interrupt-controller;
489 #interrupt-cells = <2>;
490 ti,hwmods = "gpio1";
491 status = "disabled";
492 };
493
494 gpio1: gpio@4804c000 {
495 compatible = "ti,am4372-gpio","ti,omap4-gpio";
496 reg = <0x4804c000 0x1000>;
497 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
498 gpio-controller;
499 #gpio-cells = <2>;
500 interrupt-controller;
501 #interrupt-cells = <2>;
502 ti,hwmods = "gpio2";
503 status = "disabled";
504 };
505
506 gpio2: gpio@481ac000 {
507 compatible = "ti,am4372-gpio","ti,omap4-gpio";
508 reg = <0x481ac000 0x1000>;
509 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
510 gpio-controller;
511 #gpio-cells = <2>;
512 interrupt-controller;
513 #interrupt-cells = <2>;
514 ti,hwmods = "gpio3";
515 status = "disabled";
516 };
517
518 gpio3: gpio@481ae000 {
519 compatible = "ti,am4372-gpio","ti,omap4-gpio";
520 reg = <0x481ae000 0x1000>;
521 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
522 gpio-controller;
523 #gpio-cells = <2>;
524 interrupt-controller;
525 #interrupt-cells = <2>;
526 ti,hwmods = "gpio4";
527 status = "disabled";
528 };
529
530 gpio4: gpio@48320000 {
531 compatible = "ti,am4372-gpio","ti,omap4-gpio";
532 reg = <0x48320000 0x1000>;
533 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
534 gpio-controller;
535 #gpio-cells = <2>;
536 interrupt-controller;
537 #interrupt-cells = <2>;
538 ti,hwmods = "gpio5";
539 status = "disabled";
540 };
541
542 gpio5: gpio@48322000 {
543 compatible = "ti,am4372-gpio","ti,omap4-gpio";
544 reg = <0x48322000 0x1000>;
545 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
546 gpio-controller;
547 #gpio-cells = <2>;
548 interrupt-controller;
549 #interrupt-cells = <2>;
550 ti,hwmods = "gpio6";
551 status = "disabled";
552 };
553
554 hwspinlock: spinlock@480ca000 {
555 compatible = "ti,omap4-hwspinlock";
556 reg = <0x480ca000 0x1000>;
557 ti,hwmods = "spinlock";
558 #hwlock-cells = <1>;
559 };
560
561 i2c0: i2c@44e0b000 {
562 compatible = "ti,am4372-i2c","ti,omap4-i2c";
563 reg = <0x44e0b000 0x1000>;
564 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
565 ti,hwmods = "i2c1";
566 #address-cells = <1>;
567 #size-cells = <0>;
568 status = "disabled";
569 };
570
571 i2c1: i2c@4802a000 {
572 compatible = "ti,am4372-i2c","ti,omap4-i2c";
573 reg = <0x4802a000 0x1000>;
574 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
575 ti,hwmods = "i2c2";
576 #address-cells = <1>;
577 #size-cells = <0>;
578 status = "disabled";
579 };
580
581 i2c2: i2c@4819c000 {
582 compatible = "ti,am4372-i2c","ti,omap4-i2c";
583 reg = <0x4819c000 0x1000>;
584 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
585 ti,hwmods = "i2c3";
586 #address-cells = <1>;
587 #size-cells = <0>;
588 status = "disabled";
589 };
590
591 spi0: spi@48030000 {
592 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
593 reg = <0x48030000 0x400>;
594 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
595 ti,hwmods = "spi0";
596 #address-cells = <1>;
597 #size-cells = <0>;
598 status = "disabled";
599 };
600
601 mmc1: mmc@48060000 {
602 compatible = "ti,omap4-hsmmc";
603 reg = <0x48060000 0x1000>;
604 ti,hwmods = "mmc1";
605 ti,dual-volt;
606 ti,needs-special-reset;
607 dmas = <&edma 24 0>,
608 <&edma 25 0>;
609 dma-names = "tx", "rx";
610 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
611 status = "disabled";
612 };
613
614 mmc2: mmc@481d8000 {
615 compatible = "ti,omap4-hsmmc";
616 reg = <0x481d8000 0x1000>;
617 ti,hwmods = "mmc2";
618 ti,needs-special-reset;
619 dmas = <&edma 2 0>,
620 <&edma 3 0>;
621 dma-names = "tx", "rx";
622 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
623 status = "disabled";
624 };
625
626 mmc3: mmc@47810000 {
627 compatible = "ti,omap4-hsmmc";
628 reg = <0x47810000 0x1000>;
629 ti,hwmods = "mmc3";
630 ti,needs-special-reset;
631 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
632 status = "disabled";
633 };
634
635 spi1: spi@481a0000 {
636 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
637 reg = <0x481a0000 0x400>;
638 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
639 ti,hwmods = "spi1";
640 #address-cells = <1>;
641 #size-cells = <0>;
642 status = "disabled";
643 };
644
645 spi2: spi@481a2000 {
646 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
647 reg = <0x481a2000 0x400>;
648 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
649 ti,hwmods = "spi2";
650 #address-cells = <1>;
651 #size-cells = <0>;
652 status = "disabled";
653 };
654
655 spi3: spi@481a4000 {
656 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
657 reg = <0x481a4000 0x400>;
658 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
659 ti,hwmods = "spi3";
660 #address-cells = <1>;
661 #size-cells = <0>;
662 status = "disabled";
663 };
664
665 spi4: spi@48345000 {
666 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
667 reg = <0x48345000 0x400>;
668 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
669 ti,hwmods = "spi4";
670 #address-cells = <1>;
671 #size-cells = <0>;
672 status = "disabled";
673 };
674
675 mac: ethernet@4a100000 {
676 compatible = "ti,am4372-cpsw","ti,cpsw";
677 reg = <0x4a100000 0x800
678 0x4a101200 0x100>;
679 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
680 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
681 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
682 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
683 #address-cells = <1>;
684 #size-cells = <1>;
685 ti,hwmods = "cpgmac0";
686 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>,
687 <&dpll_clksel_mac_clk>;
688 clock-names = "fck", "cpts", "50mclk";
689 assigned-clocks = <&dpll_clksel_mac_clk>;
690 assigned-clock-rates = <50000000>;
691 status = "disabled";
692 cpdma_channels = <8>;
693 ale_entries = <1024>;
694 bd_ram_size = <0x2000>;
695 mac_control = <0x20>;
696 slaves = <2>;
697 active_slave = <0>;
698 cpts_clock_mult = <0x80000000>;
699 cpts_clock_shift = <29>;
700 ranges;
701 syscon = <&scm_conf>;
702
703 davinci_mdio: mdio@4a101000 {
704 compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio";
705 reg = <0x4a101000 0x100>;
706 #address-cells = <1>;
707 #size-cells = <0>;
708 ti,hwmods = "davinci_mdio";
709 bus_freq = <1000000>;
710 status = "disabled";
711 };
712
713 cpsw_emac0: slave@4a100200 {
714 /* Filled in by U-Boot */
715 mac-address = [ 00 00 00 00 00 00 ];
716 };
717
718 cpsw_emac1: slave@4a100300 {
719 /* Filled in by U-Boot */
720 mac-address = [ 00 00 00 00 00 00 ];
721 };
722
723 phy_sel: cpsw-phy-sel@44e10650 {
724 compatible = "ti,am43xx-cpsw-phy-sel";
725 reg= <0x44e10650 0x4>;
726 reg-names = "gmii-sel";
727 };
728 };
729
730 epwmss0: epwmss@48300000 {
731 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
732 reg = <0x48300000 0x10>;
733 #address-cells = <1>;
734 #size-cells = <1>;
735 ranges;
736 ti,hwmods = "epwmss0";
737 status = "disabled";
738
739 ecap0: ecap@48300100 {
740 compatible = "ti,am4372-ecap",
741 "ti,am3352-ecap",
742 "ti,am33xx-ecap";
743 #pwm-cells = <3>;
744 reg = <0x48300100 0x80>;
745 clocks = <&l4ls_gclk>;
746 clock-names = "fck";
747 status = "disabled";
748 };
749
750 ehrpwm0: pwm@48300200 {
751 compatible = "ti,am4372-ehrpwm",
752 "ti,am3352-ehrpwm",
753 "ti,am33xx-ehrpwm";
754 #pwm-cells = <3>;
755 reg = <0x48300200 0x80>;
756 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
757 clock-names = "tbclk", "fck";
758 status = "disabled";
759 };
760 };
761
762 epwmss1: epwmss@48302000 {
763 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
764 reg = <0x48302000 0x10>;
765 #address-cells = <1>;
766 #size-cells = <1>;
767 ranges;
768 ti,hwmods = "epwmss1";
769 status = "disabled";
770
771 ecap1: ecap@48302100 {
772 compatible = "ti,am4372-ecap",
773 "ti,am3352-ecap",
774 "ti,am33xx-ecap";
775 #pwm-cells = <3>;
776 reg = <0x48302100 0x80>;
777 clocks = <&l4ls_gclk>;
778 clock-names = "fck";
779 status = "disabled";
780 };
781
782 ehrpwm1: pwm@48302200 {
783 compatible = "ti,am4372-ehrpwm",
784 "ti,am3352-ehrpwm",
785 "ti,am33xx-ehrpwm";
786 #pwm-cells = <3>;
787 reg = <0x48302200 0x80>;
788 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
789 clock-names = "tbclk", "fck";
790 status = "disabled";
791 };
792 };
793
794 epwmss2: epwmss@48304000 {
795 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
796 reg = <0x48304000 0x10>;
797 #address-cells = <1>;
798 #size-cells = <1>;
799 ranges;
800 ti,hwmods = "epwmss2";
801 status = "disabled";
802
803 ecap2: ecap@48304100 {
804 compatible = "ti,am4372-ecap",
805 "ti,am3352-ecap",
806 "ti,am33xx-ecap";
807 #pwm-cells = <3>;
808 reg = <0x48304100 0x80>;
809 clocks = <&l4ls_gclk>;
810 clock-names = "fck";
811 status = "disabled";
812 };
813
814 ehrpwm2: pwm@48304200 {
815 compatible = "ti,am4372-ehrpwm",
816 "ti,am3352-ehrpwm",
817 "ti,am33xx-ehrpwm";
818 #pwm-cells = <3>;
819 reg = <0x48304200 0x80>;
820 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
821 clock-names = "tbclk", "fck";
822 status = "disabled";
823 };
824 };
825
826 epwmss3: epwmss@48306000 {
827 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
828 reg = <0x48306000 0x10>;
829 #address-cells = <1>;
830 #size-cells = <1>;
831 ranges;
832 ti,hwmods = "epwmss3";
833 status = "disabled";
834
835 ehrpwm3: pwm@48306200 {
836 compatible = "ti,am4372-ehrpwm",
837 "ti,am3352-ehrpwm",
838 "ti,am33xx-ehrpwm";
839 #pwm-cells = <3>;
840 reg = <0x48306200 0x80>;
841 clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>;
842 clock-names = "tbclk", "fck";
843 status = "disabled";
844 };
845 };
846
847 epwmss4: epwmss@48308000 {
848 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
849 reg = <0x48308000 0x10>;
850 #address-cells = <1>;
851 #size-cells = <1>;
852 ranges;
853 ti,hwmods = "epwmss4";
854 status = "disabled";
855
856 ehrpwm4: pwm@48308200 {
857 compatible = "ti,am4372-ehrpwm",
858 "ti,am3352-ehrpwm",
859 "ti,am33xx-ehrpwm";
860 #pwm-cells = <3>;
861 reg = <0x48308200 0x80>;
862 clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>;
863 clock-names = "tbclk", "fck";
864 status = "disabled";
865 };
866 };
867
868 epwmss5: epwmss@4830a000 {
869 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
870 reg = <0x4830a000 0x10>;
871 #address-cells = <1>;
872 #size-cells = <1>;
873 ranges;
874 ti,hwmods = "epwmss5";
875 status = "disabled";
876
877 ehrpwm5: pwm@4830a200 {
878 compatible = "ti,am4372-ehrpwm",
879 "ti,am3352-ehrpwm",
880 "ti,am33xx-ehrpwm";
881 #pwm-cells = <3>;
882 reg = <0x4830a200 0x80>;
883 clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>;
884 clock-names = "tbclk", "fck";
885 status = "disabled";
886 };
887 };
888
889 tscadc: tscadc@44e0d000 {
890 compatible = "ti,am3359-tscadc";
891 reg = <0x44e0d000 0x1000>;
892 ti,hwmods = "adc_tsc";
893 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
894 clocks = <&adc_tsc_fck>;
895 clock-names = "fck";
896 status = "disabled";
897 dmas = <&edma 53 0>, <&edma 57 0>;
898 dma-names = "fifo0", "fifo1";
899
900 tsc {
901 compatible = "ti,am3359-tsc";
902 };
903
904 adc {
905 #io-channel-cells = <1>;
906 compatible = "ti,am3359-adc";
907 };
908
909 };
910
911 sham: sham@53100000 {
912 compatible = "ti,omap5-sham";
913 ti,hwmods = "sham";
914 reg = <0x53100000 0x300>;
915 dmas = <&edma 36 0>;
916 dma-names = "rx";
917 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
918 };
919
920 aes: aes@53501000 {
921 compatible = "ti,omap4-aes";
922 ti,hwmods = "aes";
923 reg = <0x53501000 0xa0>;
924 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
925 dmas = <&edma 6 0>,
926 <&edma 5 0>;
927 dma-names = "tx", "rx";
928 };
929
930 des: des@53701000 {
931 compatible = "ti,omap4-des";
932 ti,hwmods = "des";
933 reg = <0x53701000 0xa0>;
934 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
935 dmas = <&edma 34 0>,
936 <&edma 33 0>;
937 dma-names = "tx", "rx";
938 };
939
940 rng: rng@48310000 {
941 compatible = "ti,omap4-rng";
942 ti,hwmods = "rng";
943 reg = <0x48310000 0x2000>;
944 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
945 };
946
947 mcasp0: mcasp@48038000 {
948 compatible = "ti,am33xx-mcasp-audio";
949 ti,hwmods = "mcasp0";
950 reg = <0x48038000 0x2000>,
951 <0x46000000 0x400000>;
952 reg-names = "mpu", "dat";
953 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
955 interrupt-names = "tx", "rx";
956 status = "disabled";
957 dmas = <&edma 8 2>,
958 <&edma 9 2>;
959 dma-names = "tx", "rx";
960 };
961
962 mcasp1: mcasp@4803c000 {
963 compatible = "ti,am33xx-mcasp-audio";
964 ti,hwmods = "mcasp1";
965 reg = <0x4803C000 0x2000>,
966 <0x46400000 0x400000>;
967 reg-names = "mpu", "dat";
968 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
970 interrupt-names = "tx", "rx";
971 status = "disabled";
972 dmas = <&edma 10 2>,
973 <&edma 11 2>;
974 dma-names = "tx", "rx";
975 };
976
977 elm: elm@48080000 {
978 compatible = "ti,am3352-elm";
979 reg = <0x48080000 0x2000>;
980 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
981 ti,hwmods = "elm";
982 clocks = <&l4ls_gclk>;
983 clock-names = "fck";
984 status = "disabled";
985 };
986
987 gpmc: gpmc@50000000 {
988 compatible = "ti,am3352-gpmc";
989 ti,hwmods = "gpmc";
990 dmas = <&edma 52 0>;
991 dma-names = "rxtx";
992 clocks = <&l3s_gclk>;
993 clock-names = "fck";
994 reg = <0x50000000 0x2000>;
995 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
996 gpmc,num-cs = <7>;
997 gpmc,num-waitpins = <2>;
998 #address-cells = <2>;
999 #size-cells = <1>;
1000 interrupt-controller;
1001 #interrupt-cells = <2>;
1002 gpio-controller;
1003 #gpio-cells = <2>;
1004 status = "disabled";
1005 };
1006
1007 ocp2scp0: ocp2scp@483a8000 {
1008 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
1009 #address-cells = <1>;
1010 #size-cells = <1>;
1011 ranges;
1012 ti,hwmods = "ocp2scp0";
1013
1014 usb2_phy1: phy@483a8000 {
1015 compatible = "ti,am437x-usb2";
1016 reg = <0x483a8000 0x8000>;
1017 syscon-phy-power = <&scm_conf 0x620>;
1018 clocks = <&usb_phy0_always_on_clk32k>,
1019 <&l4_per_clkctrl AM4_USB_OTG_SS0_CLKCTRL 8>;
1020 clock-names = "wkupclk", "refclk";
1021 #phy-cells = <0>;
1022 status = "disabled";
1023 };
1024 };
1025
1026 ocp2scp1: ocp2scp@483e8000 {
1027 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
1028 #address-cells = <1>;
1029 #size-cells = <1>;
1030 ranges;
1031 ti,hwmods = "ocp2scp1";
1032
1033 usb2_phy2: phy@483e8000 {
1034 compatible = "ti,am437x-usb2";
1035 reg = <0x483e8000 0x8000>;
1036 syscon-phy-power = <&scm_conf 0x628>;
1037 clocks = <&usb_phy1_always_on_clk32k>,
1038 <&l4_per_clkctrl AM4_USB_OTG_SS1_CLKCTRL 8>;
1039 clock-names = "wkupclk", "refclk";
1040 #phy-cells = <0>;
1041 status = "disabled";
1042 };
1043 };
1044
1045 dwc3_1: omap_dwc3@48380000 {
1046 compatible = "ti,am437x-dwc3";
1047 ti,hwmods = "usb_otg_ss0";
1048 reg = <0x48380000 0x10000>;
1049 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
1050 #address-cells = <1>;
1051 #size-cells = <1>;
1052 utmi-mode = <1>;
1053 ranges;
1054
1055 usb1: usb@48390000 {
1056 compatible = "synopsys,dwc3";
1057 reg = <0x48390000 0x10000>;
1058 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1059 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1060 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
1061 interrupt-names = "peripheral",
1062 "host",
1063 "otg";
1064 phys = <&usb2_phy1>;
1065 phy-names = "usb2-phy";
1066 maximum-speed = "high-speed";
1067 dr_mode = "otg";
1068 status = "disabled";
1069 snps,dis_u3_susphy_quirk;
1070 snps,dis_u2_susphy_quirk;
1071 };
1072 };
1073
1074 dwc3_2: omap_dwc3@483c0000 {
1075 compatible = "ti,am437x-dwc3";
1076 ti,hwmods = "usb_otg_ss1";
1077 reg = <0x483c0000 0x10000>;
1078 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
1079 #address-cells = <1>;
1080 #size-cells = <1>;
1081 utmi-mode = <1>;
1082 ranges;
1083
1084 usb2: usb@483d0000 {
1085 compatible = "synopsys,dwc3";
1086 reg = <0x483d0000 0x10000>;
1087 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
1088 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
1089 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
1090 interrupt-names = "peripheral",
1091 "host",
1092 "otg";
1093 phys = <&usb2_phy2>;
1094 phy-names = "usb2-phy";
1095 maximum-speed = "high-speed";
1096 dr_mode = "otg";
1097 status = "disabled";
1098 snps,dis_u3_susphy_quirk;
1099 snps,dis_u2_susphy_quirk;
1100 };
1101 };
1102
1103 qspi: qspi@47900000 {
1104 compatible = "ti,am4372-qspi";
1105 reg = <0x47900000 0x100>,
1106 <0x30000000 0x4000000>;
1107 reg-names = "qspi_base", "qspi_mmap";
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1110 ti,hwmods = "qspi";
1111 interrupts = <0 138 0x4>;
1112 num-cs = <4>;
1113 status = "disabled";
1114 };
1115
1116 hdq: hdq@48347000 {
1117 compatible = "ti,am4372-hdq";
1118 reg = <0x48347000 0x1000>;
1119 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
1120 clocks = <&func_12m_clk>;
1121 clock-names = "fck";
1122 ti,hwmods = "hdq1w";
1123 status = "disabled";
1124 };
1125
1126 dss: dss@4832a000 {
1127 compatible = "ti,omap3-dss";
1128 reg = <0x4832a000 0x200>;
1129 status = "disabled";
1130 ti,hwmods = "dss_core";
1131 clocks = <&disp_clk>;
1132 clock-names = "fck";
1133 #address-cells = <1>;
1134 #size-cells = <1>;
1135 ranges;
1136
1137 dispc: dispc@4832a400 {
1138 compatible = "ti,omap3-dispc";
1139 reg = <0x4832a400 0x400>;
1140 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1141 ti,hwmods = "dss_dispc";
1142 clocks = <&disp_clk>;
1143 clock-names = "fck";
1144 };
1145
1146 rfbi: rfbi@4832a800 {
1147 compatible = "ti,omap3-rfbi";
1148 reg = <0x4832a800 0x100>;
1149 ti,hwmods = "dss_rfbi";
1150 clocks = <&disp_clk>;
1151 clock-names = "fck";
1152 status = "disabled";
1153 };
1154 };
1155
1156 ocmcram: ocmcram@40300000 {
1157 compatible = "mmio-sram";
1158 reg = <0x40300000 0x40000>; /* 256k */
1159 ranges = <0x0 0x40300000 0x40000>;
1160 #address-cells = <1>;
1161 #size-cells = <1>;
1162
1163 pm_sram_code: pm-sram-code@0 {
1164 compatible = "ti,sram";
1165 reg = <0x0 0x1000>;
1166 protect-exec;
1167 };
1168
1169 pm_sram_data: pm-sram-data@1000 {
1170 compatible = "ti,sram";
1171 reg = <0x1000 0x1000>;
1172 pool;
1173 };
1174 };
1175
1176 dcan0: can@481cc000 {
1177 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
1178 ti,hwmods = "d_can0";
1179 clocks = <&dcan0_fck>;
1180 clock-names = "fck";
1181 reg = <0x481cc000 0x2000>;
1182 syscon-raminit = <&scm_conf 0x644 0>;
1183 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1184 status = "disabled";
1185 };
1186
1187 dcan1: can@481d0000 {
1188 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
1189 ti,hwmods = "d_can1";
1190 clocks = <&dcan1_fck>;
1191 clock-names = "fck";
1192 reg = <0x481d0000 0x2000>;
1193 syscon-raminit = <&scm_conf 0x644 1>;
1194 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1195 status = "disabled";
1196 };
1197
1198 vpfe0: vpfe@48326000 {
1199 compatible = "ti,am437x-vpfe";
1200 reg = <0x48326000 0x2000>;
1201 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1202 ti,hwmods = "vpfe0";
1203 status = "disabled";
1204 };
1205
1206 vpfe1: vpfe@48328000 {
1207 compatible = "ti,am437x-vpfe";
1208 reg = <0x48328000 0x2000>;
1209 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1210 ti,hwmods = "vpfe1";
1211 status = "disabled";
1212 };
1213 };
1214};
1215
1216#include "am43xx-clocks.dtsi"