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1/*
2 * Device Tree Source for AM4372 SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/bus/ti-sysc.h>
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/clock/am4.h>
15
16/ {
17 compatible = "ti,am4372", "ti,am43";
18 interrupt-parent = <&wakeupgen>;
19 #address-cells = <1>;
20 #size-cells = <1>;
21 chosen { };
22
23 memory@0 {
24 device_type = "memory";
25 reg = <0 0>;
26 };
27
28 aliases {
29 i2c0 = &i2c0;
30 i2c1 = &i2c1;
31 i2c2 = &i2c2;
32 serial0 = &uart0;
33 serial1 = &uart1;
34 serial2 = &uart2;
35 serial3 = &uart3;
36 serial4 = &uart4;
37 serial5 = &uart5;
38 ethernet0 = &cpsw_port1;
39 ethernet1 = &cpsw_port2;
40 spi0 = &qspi;
41 };
42
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46 cpu: cpu@0 {
47 compatible = "arm,cortex-a9";
48 enable-method = "ti,am4372";
49 device_type = "cpu";
50 reg = <0>;
51
52 clocks = <&dpll_mpu_ck>;
53 clock-names = "cpu";
54
55 operating-points-v2 = <&cpu0_opp_table>;
56
57 clock-latency = <300000>; /* From omap-cpufreq driver */
58 cpu-idle-states = <&mpu_gate>;
59 };
60
61 idle-states {
62 mpu_gate: mpu_gate {
63 compatible = "arm,idle-state";
64 entry-latency-us = <40>;
65 exit-latency-us = <100>;
66 min-residency-us = <300>;
67 local-timer-stop;
68 };
69 };
70 };
71
72 cpu0_opp_table: opp-table {
73 compatible = "operating-points-v2-ti-cpu";
74 syscon = <&scm_conf>;
75
76 opp50-300000000 {
77 opp-hz = /bits/ 64 <300000000>;
78 opp-microvolt = <950000 931000 969000>;
79 opp-supported-hw = <0xFF 0x01>;
80 opp-suspend;
81 };
82
83 opp100-600000000 {
84 opp-hz = /bits/ 64 <600000000>;
85 opp-microvolt = <1100000 1078000 1122000>;
86 opp-supported-hw = <0xFF 0x04>;
87 };
88
89 opp120-720000000 {
90 opp-hz = /bits/ 64 <720000000>;
91 opp-microvolt = <1200000 1176000 1224000>;
92 opp-supported-hw = <0xFF 0x08>;
93 };
94
95 oppturbo-800000000 {
96 opp-hz = /bits/ 64 <800000000>;
97 opp-microvolt = <1260000 1234800 1285200>;
98 opp-supported-hw = <0xFF 0x10>;
99 };
100
101 oppnitro-1000000000 {
102 opp-hz = /bits/ 64 <1000000000>;
103 opp-microvolt = <1325000 1298500 1351500>;
104 opp-supported-hw = <0xFF 0x20>;
105 };
106 };
107
108 soc {
109 compatible = "ti,omap-infra";
110 };
111
112 gic: interrupt-controller@48241000 {
113 compatible = "arm,cortex-a9-gic";
114 interrupt-controller;
115 #interrupt-cells = <3>;
116 reg = <0x48241000 0x1000>,
117 <0x48240100 0x0100>;
118 interrupt-parent = <&gic>;
119 };
120
121 wakeupgen: interrupt-controller@48281000 {
122 compatible = "ti,omap4-wugen-mpu";
123 interrupt-controller;
124 #interrupt-cells = <3>;
125 reg = <0x48281000 0x1000>;
126 interrupt-parent = <&gic>;
127 };
128
129 scu: scu@48240000 {
130 compatible = "arm,cortex-a9-scu";
131 reg = <0x48240000 0x100>;
132 };
133
134 global_timer: timer@48240200 {
135 compatible = "arm,cortex-a9-global-timer";
136 reg = <0x48240200 0x100>;
137 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
138 interrupt-parent = <&gic>;
139 clocks = <&mpu_periphclk>;
140 };
141
142 local_timer: timer@48240600 {
143 compatible = "arm,cortex-a9-twd-timer";
144 reg = <0x48240600 0x100>;
145 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
146 interrupt-parent = <&gic>;
147 clocks = <&mpu_periphclk>;
148 };
149
150 cache-controller@48242000 {
151 compatible = "arm,pl310-cache";
152 reg = <0x48242000 0x1000>;
153 cache-unified;
154 cache-level = <2>;
155 };
156
157 ocp@44000000 {
158 compatible = "simple-pm-bus";
159 power-domains = <&prm_per>;
160 clocks = <&l3_clkctrl AM4_L3_L3_MAIN_CLKCTRL 0>;
161 clock-names = "fck";
162 #address-cells = <1>;
163 #size-cells = <1>;
164 ranges;
165 ti,no-idle;
166
167 l3-noc@44000000 {
168 compatible = "ti,am4372-l3-noc";
169 reg = <0x44000000 0x400000>,
170 <0x44800000 0x400000>;
171 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
173 };
174
175 l4_wkup: interconnect@44c00000 {
176 };
177 l4_per: interconnect@48000000 {
178 };
179 l4_fast: interconnect@4a000000 {
180 };
181
182 target-module@4c000000 {
183 compatible = "ti,sysc-omap4-simple", "ti,sysc";
184 reg = <0x4c000000 0x4>;
185 reg-names = "rev";
186 clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>;
187 clock-names = "fck";
188 ti,no-idle;
189 #address-cells = <1>;
190 #size-cells = <1>;
191 ranges = <0x0 0x4c000000 0x1000000>;
192
193 emif: emif@0 {
194 compatible = "ti,emif-am4372";
195 reg = <0 0x1000000>;
196 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
197 sram = <&pm_sram_code
198 &pm_sram_data>;
199 };
200 };
201
202 target-module@49000000 {
203 compatible = "ti,sysc-omap4", "ti,sysc";
204 reg = <0x49000000 0x4>;
205 reg-names = "rev";
206 clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>;
207 clock-names = "fck";
208 #address-cells = <1>;
209 #size-cells = <1>;
210 ranges = <0x0 0x49000000 0x10000>;
211
212 edma: dma@0 {
213 compatible = "ti,edma3-tpcc";
214 reg = <0 0x10000>;
215 reg-names = "edma3_cc";
216 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
219 interrupt-names = "edma3_ccint", "edma3_mperr",
220 "edma3_ccerrint";
221 dma-requests = <64>;
222 #dma-cells = <2>;
223
224 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
225 <&edma_tptc2 0>;
226
227 ti,edma-memcpy-channels = <58 59>;
228 };
229 };
230
231 target-module@49800000 {
232 compatible = "ti,sysc-omap4", "ti,sysc";
233 reg = <0x49800000 0x4>,
234 <0x49800010 0x4>;
235 reg-names = "rev", "sysc";
236 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
237 ti,sysc-midle = <SYSC_IDLE_FORCE>;
238 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
239 <SYSC_IDLE_SMART>;
240 clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>;
241 clock-names = "fck";
242 #address-cells = <1>;
243 #size-cells = <1>;
244 ranges = <0x0 0x49800000 0x100000>;
245
246 edma_tptc0: dma@0 {
247 compatible = "ti,edma3-tptc";
248 reg = <0 0x100000>;
249 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
250 interrupt-names = "edma3_tcerrint";
251 };
252 };
253
254 target-module@49900000 {
255 compatible = "ti,sysc-omap4", "ti,sysc";
256 reg = <0x49900000 0x4>,
257 <0x49900010 0x4>;
258 reg-names = "rev", "sysc";
259 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
260 ti,sysc-midle = <SYSC_IDLE_FORCE>;
261 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
262 <SYSC_IDLE_SMART>;
263 clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>;
264 clock-names = "fck";
265 #address-cells = <1>;
266 #size-cells = <1>;
267 ranges = <0x0 0x49900000 0x100000>;
268
269 edma_tptc1: dma@0 {
270 compatible = "ti,edma3-tptc";
271 reg = <0 0x100000>;
272 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
273 interrupt-names = "edma3_tcerrint";
274 };
275 };
276
277 target-module@49a00000 {
278 compatible = "ti,sysc-omap4", "ti,sysc";
279 reg = <0x49a00000 0x4>,
280 <0x49a00010 0x4>;
281 reg-names = "rev", "sysc";
282 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
283 ti,sysc-midle = <SYSC_IDLE_FORCE>;
284 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
285 <SYSC_IDLE_SMART>;
286 clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>;
287 clock-names = "fck";
288 #address-cells = <1>;
289 #size-cells = <1>;
290 ranges = <0x0 0x49a00000 0x100000>;
291
292 edma_tptc2: dma@0 {
293 compatible = "ti,edma3-tptc";
294 reg = <0 0x100000>;
295 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
296 interrupt-names = "edma3_tcerrint";
297 };
298 };
299
300 target-module@47810000 {
301 compatible = "ti,sysc-omap2", "ti,sysc";
302 reg = <0x478102fc 0x4>,
303 <0x47810110 0x4>,
304 <0x47810114 0x4>;
305 reg-names = "rev", "sysc", "syss";
306 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
307 SYSC_OMAP2_ENAWAKEUP |
308 SYSC_OMAP2_SOFTRESET |
309 SYSC_OMAP2_AUTOIDLE)>;
310 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
311 <SYSC_IDLE_NO>,
312 <SYSC_IDLE_SMART>;
313 ti,syss-mask = <1>;
314 clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>;
315 clock-names = "fck";
316 #address-cells = <1>;
317 #size-cells = <1>;
318 ranges = <0x0 0x47810000 0x1000>;
319
320 mmc3: mmc@0 {
321 compatible = "ti,am437-sdhci";
322 ti,needs-special-reset;
323 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
324 reg = <0x0 0x1000>;
325 status = "disabled";
326 };
327 };
328
329 sham_target: target-module@53100000 {
330 compatible = "ti,sysc-omap3-sham", "ti,sysc";
331 reg = <0x53100100 0x4>,
332 <0x53100110 0x4>,
333 <0x53100114 0x4>;
334 reg-names = "rev", "sysc", "syss";
335 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
336 SYSC_OMAP2_AUTOIDLE)>;
337 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
338 <SYSC_IDLE_NO>,
339 <SYSC_IDLE_SMART>;
340 ti,syss-mask = <1>;
341 /* Domains (P, C): per_pwrdm, l3_clkdm */
342 clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
343 clock-names = "fck";
344 #address-cells = <1>;
345 #size-cells = <1>;
346 ranges = <0x0 0x53100000 0x1000>;
347
348 sham: sham@0 {
349 compatible = "ti,omap5-sham";
350 reg = <0 0x300>;
351 dmas = <&edma 36 0>;
352 dma-names = "rx";
353 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
354 };
355 };
356
357 aes_target: target-module@53501000 {
358 compatible = "ti,sysc-omap2", "ti,sysc";
359 reg = <0x53501080 0x4>,
360 <0x53501084 0x4>,
361 <0x53501088 0x4>;
362 reg-names = "rev", "sysc", "syss";
363 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
364 SYSC_OMAP2_AUTOIDLE)>;
365 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
366 <SYSC_IDLE_NO>,
367 <SYSC_IDLE_SMART>,
368 <SYSC_IDLE_SMART_WKUP>;
369 ti,syss-mask = <1>;
370 /* Domains (P, C): per_pwrdm, l3_clkdm */
371 clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
372 clock-names = "fck";
373 #address-cells = <1>;
374 #size-cells = <1>;
375 ranges = <0x0 0x53501000 0x1000>;
376
377 aes: aes@0 {
378 compatible = "ti,omap4-aes";
379 reg = <0 0xa0>;
380 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
381 dmas = <&edma 6 0>,
382 <&edma 5 0>;
383 dma-names = "tx", "rx";
384 };
385 };
386
387 des_target: target-module@53701000 {
388 compatible = "ti,sysc-omap2", "ti,sysc";
389 reg = <0x53701030 0x4>,
390 <0x53701034 0x4>,
391 <0x53701038 0x4>;
392 reg-names = "rev", "sysc", "syss";
393 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
394 SYSC_OMAP2_AUTOIDLE)>;
395 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
396 <SYSC_IDLE_NO>,
397 <SYSC_IDLE_SMART>,
398 <SYSC_IDLE_SMART_WKUP>;
399 ti,syss-mask = <1>;
400 /* Domains (P, C): per_pwrdm, l3_clkdm */
401 clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
402 clock-names = "fck";
403 #address-cells = <1>;
404 #size-cells = <1>;
405 ranges = <0 0x53701000 0x1000>;
406
407 des: des@0 {
408 compatible = "ti,omap4-des";
409 reg = <0 0xa0>;
410 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
411 dmas = <&edma 34 0>,
412 <&edma 33 0>;
413 dma-names = "tx", "rx";
414 };
415 };
416
417 pruss_tm: target-module@54400000 {
418 compatible = "ti,sysc-pruss", "ti,sysc";
419 reg = <0x54426000 0x4>,
420 <0x54426004 0x4>;
421 reg-names = "rev", "sysc";
422 ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
423 SYSC_PRUSS_SUB_MWAIT)>;
424 ti,sysc-midle = <SYSC_IDLE_FORCE>,
425 <SYSC_IDLE_NO>,
426 <SYSC_IDLE_SMART>;
427 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
428 <SYSC_IDLE_NO>,
429 <SYSC_IDLE_SMART>;
430 clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;
431 clock-names = "fck";
432 resets = <&prm_per 1>;
433 reset-names = "rstctrl";
434 #address-cells = <1>;
435 #size-cells = <1>;
436 ranges = <0x0 0x54400000 0x80000>;
437 };
438
439 target-module@50000000 {
440 compatible = "ti,sysc-omap2", "ti,sysc";
441 reg = <0x50000000 4>,
442 <0x50000010 4>,
443 <0x50000014 4>;
444 reg-names = "rev", "sysc", "syss";
445 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
446 <SYSC_IDLE_NO>,
447 <SYSC_IDLE_SMART>;
448 ti,syss-mask = <1>;
449 clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>;
450 clock-names = "fck";
451 #address-cells = <1>;
452 #size-cells = <1>;
453 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
454 <0x00000000 0x00000000 0x40000000>; /* data */
455
456 gpmc: gpmc@50000000 {
457 compatible = "ti,am3352-gpmc";
458 dmas = <&edma 52 0>;
459 dma-names = "rxtx";
460 clocks = <&l3s_gclk>;
461 clock-names = "fck";
462 reg = <0x50000000 0x2000>;
463 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
464 gpmc,num-cs = <7>;
465 gpmc,num-waitpins = <2>;
466 #address-cells = <2>;
467 #size-cells = <1>;
468 interrupt-controller;
469 #interrupt-cells = <2>;
470 gpio-controller;
471 #gpio-cells = <2>;
472 status = "disabled";
473 };
474 };
475
476 target-module@47900000 {
477 compatible = "ti,sysc-omap4", "ti,sysc";
478 reg = <0x47900000 0x4>,
479 <0x47900010 0x4>;
480 reg-names = "rev", "sysc";
481 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
482 <SYSC_IDLE_NO>,
483 <SYSC_IDLE_SMART>,
484 <SYSC_IDLE_SMART_WKUP>;
485 clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
486 clock-names = "fck";
487 #address-cells = <1>;
488 #size-cells = <1>;
489 ranges = <0x0 0x47900000 0x1000>,
490 <0x30000000 0x30000000 0x4000000>;
491
492 qspi: spi@0 {
493 compatible = "ti,am4372-qspi";
494 reg = <0 0x100>,
495 <0x30000000 0x4000000>;
496 reg-names = "qspi_base", "qspi_mmap";
497 clocks = <&dpll_per_m2_div4_ck>;
498 clock-names = "fck";
499 #address-cells = <1>;
500 #size-cells = <0>;
501 interrupts = <0 138 0x4>;
502 num-cs = <4>;
503 };
504 };
505
506 target-module@40300000 {
507 compatible = "ti,sysc-omap4-simple", "ti,sysc";
508 clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>;
509 clock-names = "fck";
510 ti,no-idle;
511 #address-cells = <1>;
512 #size-cells = <1>;
513 ranges = <0 0x40300000 0x40000>;
514
515 ocmcram: sram@0 {
516 compatible = "mmio-sram";
517 reg = <0 0x40000>; /* 256k */
518 ranges = <0 0 0x40000>;
519 #address-cells = <1>;
520 #size-cells = <1>;
521
522 pm_sram_code: pm-code-sram@0 {
523 compatible = "ti,sram";
524 reg = <0x0 0x1000>;
525 protect-exec;
526 };
527
528 pm_sram_data: pm-data-sram@1000 {
529 compatible = "ti,sram";
530 reg = <0x1000 0x1000>;
531 pool;
532 };
533 };
534 };
535
536 target-module@56000000 {
537 compatible = "ti,sysc-omap4", "ti,sysc";
538 reg = <0x5600fe00 0x4>,
539 <0x5600fe10 0x4>;
540 reg-names = "rev", "sysc";
541 ti,sysc-midle = <SYSC_IDLE_FORCE>,
542 <SYSC_IDLE_NO>,
543 <SYSC_IDLE_SMART>;
544 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
545 <SYSC_IDLE_NO>,
546 <SYSC_IDLE_SMART>;
547 clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
548 clock-names = "fck";
549 power-domains = <&prm_gfx>;
550 resets = <&prm_gfx 0>;
551 reset-names = "rstctrl";
552 #address-cells = <1>;
553 #size-cells = <1>;
554 ranges = <0 0x56000000 0x1000000>;
555 };
556 };
557};
558
559#include "am437x-l4.dtsi"
560#include "am43xx-clocks.dtsi"
561
562&prcm {
563 prm_mpu: prm@300 {
564 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
565 reg = <0x300 0x100>;
566 #power-domain-cells = <0>;
567 };
568
569 prm_gfx: prm@400 {
570 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
571 reg = <0x400 0x100>;
572 #power-domain-cells = <0>;
573 #reset-cells = <1>;
574 };
575
576 prm_rtc: prm@500 {
577 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
578 reg = <0x500 0x100>;
579 #power-domain-cells = <0>;
580 };
581
582 prm_tamper: prm@600 {
583 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
584 reg = <0x600 0x100>;
585 #power-domain-cells = <0>;
586 };
587
588 prm_cefuse: prm@700 {
589 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
590 reg = <0x700 0x100>;
591 #power-domain-cells = <0>;
592 };
593
594 prm_per: prm@800 {
595 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
596 reg = <0x800 0x100>;
597 #reset-cells = <1>;
598 #power-domain-cells = <0>;
599 };
600
601 prm_wkup: prm@2000 {
602 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
603 reg = <0x2000 0x100>;
604 #reset-cells = <1>;
605 #power-domain-cells = <0>;
606 };
607
608 prm_device: prm@4000 {
609 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
610 reg = <0x4000 0x100>;
611 #reset-cells = <1>;
612 };
613};
614
615/* Preferred always-on timer for clocksource */
616&timer1_target {
617 ti,no-reset-on-init;
618 ti,no-idle;
619 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>,
620 <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
621 clock-names = "fck", "ick";
622 timer@0 {
623 assigned-clocks = <&timer1_fck>;
624 assigned-clock-parents = <&sys_clkin_ck>;
625 };
626};
627
628/* Preferred timer for clockevent */
629&timer2_target {
630 ti,no-reset-on-init;
631 ti,no-idle;
632 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>,
633 <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>;
634 clock-names = "fck", "ick";
635 timer@0 {
636 assigned-clocks = <&timer2_fck>;
637 assigned-clock-parents = <&sys_clkin_ck>;
638 };
639};
1/*
2 * Device Tree Source for AM4372 SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
14#include "skeleton.dtsi"
15
16/ {
17 compatible = "ti,am4372", "ti,am43";
18 interrupt-parent = <&gic>;
19
20
21 aliases {
22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
25 serial0 = &uart0;
26 ethernet0 = &cpsw_emac0;
27 ethernet1 = &cpsw_emac1;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33 cpu@0 {
34 compatible = "arm,cortex-a9";
35 device_type = "cpu";
36 reg = <0>;
37
38 clocks = <&dpll_mpu_ck>;
39 clock-names = "cpu";
40
41 clock-latency = <300000>; /* From omap-cpufreq driver */
42 };
43 };
44
45 gic: interrupt-controller@48241000 {
46 compatible = "arm,cortex-a9-gic";
47 interrupt-controller;
48 #interrupt-cells = <3>;
49 reg = <0x48241000 0x1000>,
50 <0x48240100 0x0100>;
51 };
52
53 l2-cache-controller@48242000 {
54 compatible = "arm,pl310-cache";
55 reg = <0x48242000 0x1000>;
56 cache-unified;
57 cache-level = <2>;
58 };
59
60 am43xx_pinmux: pinmux@44e10800 {
61 compatible = "pinctrl-single";
62 reg = <0x44e10800 0x31c>;
63 #address-cells = <1>;
64 #size-cells = <0>;
65 pinctrl-single,register-width = <32>;
66 pinctrl-single,function-mask = <0xffffffff>;
67 };
68
69 ocp {
70 compatible = "simple-bus";
71 #address-cells = <1>;
72 #size-cells = <1>;
73 ranges;
74 ti,hwmods = "l3_main";
75
76 prcm: prcm@44df0000 {
77 compatible = "ti,am4-prcm";
78 reg = <0x44df0000 0x11000>;
79
80 prcm_clocks: clocks {
81 #address-cells = <1>;
82 #size-cells = <0>;
83 };
84
85 prcm_clockdomains: clockdomains {
86 };
87 };
88
89 scrm: scrm@44e10000 {
90 compatible = "ti,am4-scrm";
91 reg = <0x44e10000 0x2000>;
92
93 scrm_clocks: clocks {
94 #address-cells = <1>;
95 #size-cells = <0>;
96 };
97
98 scrm_clockdomains: clockdomains {
99 };
100 };
101
102 edma: edma@49000000 {
103 compatible = "ti,edma3";
104 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
105 reg = <0x49000000 0x10000>,
106 <0x44e10f90 0x10>;
107 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
110 #dma-cells = <1>;
111 dma-channels = <64>;
112 ti,edma-regions = <4>;
113 ti,edma-slots = <256>;
114 };
115
116 uart0: serial@44e09000 {
117 compatible = "ti,am4372-uart","ti,omap2-uart";
118 reg = <0x44e09000 0x2000>;
119 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
120 ti,hwmods = "uart1";
121 };
122
123 uart1: serial@48022000 {
124 compatible = "ti,am4372-uart","ti,omap2-uart";
125 reg = <0x48022000 0x2000>;
126 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
127 ti,hwmods = "uart2";
128 status = "disabled";
129 };
130
131 uart2: serial@48024000 {
132 compatible = "ti,am4372-uart","ti,omap2-uart";
133 reg = <0x48024000 0x2000>;
134 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
135 ti,hwmods = "uart3";
136 status = "disabled";
137 };
138
139 uart3: serial@481a6000 {
140 compatible = "ti,am4372-uart","ti,omap2-uart";
141 reg = <0x481a6000 0x2000>;
142 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
143 ti,hwmods = "uart4";
144 status = "disabled";
145 };
146
147 uart4: serial@481a8000 {
148 compatible = "ti,am4372-uart","ti,omap2-uart";
149 reg = <0x481a8000 0x2000>;
150 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
151 ti,hwmods = "uart5";
152 status = "disabled";
153 };
154
155 uart5: serial@481aa000 {
156 compatible = "ti,am4372-uart","ti,omap2-uart";
157 reg = <0x481aa000 0x2000>;
158 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
159 ti,hwmods = "uart6";
160 status = "disabled";
161 };
162
163 mailbox: mailbox@480C8000 {
164 compatible = "ti,omap4-mailbox";
165 reg = <0x480C8000 0x200>;
166 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
167 ti,hwmods = "mailbox";
168 ti,mbox-num-users = <4>;
169 ti,mbox-num-fifos = <8>;
170 ti,mbox-names = "wkup_m3";
171 ti,mbox-data = <0 0 0 0>;
172 status = "disabled";
173 };
174
175 timer1: timer@44e31000 {
176 compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
177 reg = <0x44e31000 0x400>;
178 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
179 ti,timer-alwon;
180 ti,hwmods = "timer1";
181 };
182
183 timer2: timer@48040000 {
184 compatible = "ti,am4372-timer","ti,am335x-timer";
185 reg = <0x48040000 0x400>;
186 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
187 ti,hwmods = "timer2";
188 };
189
190 timer3: timer@48042000 {
191 compatible = "ti,am4372-timer","ti,am335x-timer";
192 reg = <0x48042000 0x400>;
193 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
194 ti,hwmods = "timer3";
195 status = "disabled";
196 };
197
198 timer4: timer@48044000 {
199 compatible = "ti,am4372-timer","ti,am335x-timer";
200 reg = <0x48044000 0x400>;
201 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
202 ti,timer-pwm;
203 ti,hwmods = "timer4";
204 status = "disabled";
205 };
206
207 timer5: timer@48046000 {
208 compatible = "ti,am4372-timer","ti,am335x-timer";
209 reg = <0x48046000 0x400>;
210 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
211 ti,timer-pwm;
212 ti,hwmods = "timer5";
213 status = "disabled";
214 };
215
216 timer6: timer@48048000 {
217 compatible = "ti,am4372-timer","ti,am335x-timer";
218 reg = <0x48048000 0x400>;
219 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
220 ti,timer-pwm;
221 ti,hwmods = "timer6";
222 status = "disabled";
223 };
224
225 timer7: timer@4804a000 {
226 compatible = "ti,am4372-timer","ti,am335x-timer";
227 reg = <0x4804a000 0x400>;
228 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
229 ti,timer-pwm;
230 ti,hwmods = "timer7";
231 status = "disabled";
232 };
233
234 timer8: timer@481c1000 {
235 compatible = "ti,am4372-timer","ti,am335x-timer";
236 reg = <0x481c1000 0x400>;
237 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
238 ti,hwmods = "timer8";
239 status = "disabled";
240 };
241
242 timer9: timer@4833d000 {
243 compatible = "ti,am4372-timer","ti,am335x-timer";
244 reg = <0x4833d000 0x400>;
245 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
246 ti,hwmods = "timer9";
247 status = "disabled";
248 };
249
250 timer10: timer@4833f000 {
251 compatible = "ti,am4372-timer","ti,am335x-timer";
252 reg = <0x4833f000 0x400>;
253 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
254 ti,hwmods = "timer10";
255 status = "disabled";
256 };
257
258 timer11: timer@48341000 {
259 compatible = "ti,am4372-timer","ti,am335x-timer";
260 reg = <0x48341000 0x400>;
261 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
262 ti,hwmods = "timer11";
263 status = "disabled";
264 };
265
266 counter32k: counter@44e86000 {
267 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
268 reg = <0x44e86000 0x40>;
269 ti,hwmods = "counter_32k";
270 };
271
272 rtc@44e3e000 {
273 compatible = "ti,am4372-rtc","ti,da830-rtc";
274 reg = <0x44e3e000 0x1000>;
275 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
276 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
277 ti,hwmods = "rtc";
278 status = "disabled";
279 };
280
281 wdt@44e35000 {
282 compatible = "ti,am4372-wdt","ti,omap3-wdt";
283 reg = <0x44e35000 0x1000>;
284 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
285 ti,hwmods = "wd_timer2";
286 };
287
288 gpio0: gpio@44e07000 {
289 compatible = "ti,am4372-gpio","ti,omap4-gpio";
290 reg = <0x44e07000 0x1000>;
291 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
292 gpio-controller;
293 #gpio-cells = <2>;
294 interrupt-controller;
295 #interrupt-cells = <2>;
296 ti,hwmods = "gpio1";
297 status = "disabled";
298 };
299
300 gpio1: gpio@4804c000 {
301 compatible = "ti,am4372-gpio","ti,omap4-gpio";
302 reg = <0x4804c000 0x1000>;
303 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
304 gpio-controller;
305 #gpio-cells = <2>;
306 interrupt-controller;
307 #interrupt-cells = <2>;
308 ti,hwmods = "gpio2";
309 status = "disabled";
310 };
311
312 gpio2: gpio@481ac000 {
313 compatible = "ti,am4372-gpio","ti,omap4-gpio";
314 reg = <0x481ac000 0x1000>;
315 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
316 gpio-controller;
317 #gpio-cells = <2>;
318 interrupt-controller;
319 #interrupt-cells = <2>;
320 ti,hwmods = "gpio3";
321 status = "disabled";
322 };
323
324 gpio3: gpio@481ae000 {
325 compatible = "ti,am4372-gpio","ti,omap4-gpio";
326 reg = <0x481ae000 0x1000>;
327 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
328 gpio-controller;
329 #gpio-cells = <2>;
330 interrupt-controller;
331 #interrupt-cells = <2>;
332 ti,hwmods = "gpio4";
333 status = "disabled";
334 };
335
336 gpio4: gpio@48320000 {
337 compatible = "ti,am4372-gpio","ti,omap4-gpio";
338 reg = <0x48320000 0x1000>;
339 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
340 gpio-controller;
341 #gpio-cells = <2>;
342 interrupt-controller;
343 #interrupt-cells = <2>;
344 ti,hwmods = "gpio5";
345 status = "disabled";
346 };
347
348 gpio5: gpio@48322000 {
349 compatible = "ti,am4372-gpio","ti,omap4-gpio";
350 reg = <0x48322000 0x1000>;
351 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
352 gpio-controller;
353 #gpio-cells = <2>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
356 ti,hwmods = "gpio6";
357 status = "disabled";
358 };
359
360 hwspinlock: spinlock@480ca000 {
361 compatible = "ti,omap4-hwspinlock";
362 reg = <0x480ca000 0x1000>;
363 ti,hwmods = "spinlock";
364 #hwlock-cells = <1>;
365 };
366
367 i2c0: i2c@44e0b000 {
368 compatible = "ti,am4372-i2c","ti,omap4-i2c";
369 reg = <0x44e0b000 0x1000>;
370 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
371 ti,hwmods = "i2c1";
372 #address-cells = <1>;
373 #size-cells = <0>;
374 status = "disabled";
375 };
376
377 i2c1: i2c@4802a000 {
378 compatible = "ti,am4372-i2c","ti,omap4-i2c";
379 reg = <0x4802a000 0x1000>;
380 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
381 ti,hwmods = "i2c2";
382 #address-cells = <1>;
383 #size-cells = <0>;
384 status = "disabled";
385 };
386
387 i2c2: i2c@4819c000 {
388 compatible = "ti,am4372-i2c","ti,omap4-i2c";
389 reg = <0x4819c000 0x1000>;
390 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
391 ti,hwmods = "i2c3";
392 #address-cells = <1>;
393 #size-cells = <0>;
394 status = "disabled";
395 };
396
397 spi0: spi@48030000 {
398 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
399 reg = <0x48030000 0x400>;
400 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
401 ti,hwmods = "spi0";
402 #address-cells = <1>;
403 #size-cells = <0>;
404 status = "disabled";
405 };
406
407 mmc1: mmc@48060000 {
408 compatible = "ti,omap4-hsmmc";
409 reg = <0x48060000 0x1000>;
410 ti,hwmods = "mmc1";
411 ti,dual-volt;
412 ti,needs-special-reset;
413 dmas = <&edma 24
414 &edma 25>;
415 dma-names = "tx", "rx";
416 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
417 status = "disabled";
418 };
419
420 mmc2: mmc@481d8000 {
421 compatible = "ti,omap4-hsmmc";
422 reg = <0x481d8000 0x1000>;
423 ti,hwmods = "mmc2";
424 ti,needs-special-reset;
425 dmas = <&edma 2
426 &edma 3>;
427 dma-names = "tx", "rx";
428 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
429 status = "disabled";
430 };
431
432 mmc3: mmc@47810000 {
433 compatible = "ti,omap4-hsmmc";
434 reg = <0x47810000 0x1000>;
435 ti,hwmods = "mmc3";
436 ti,needs-special-reset;
437 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
438 status = "disabled";
439 };
440
441 spi1: spi@481a0000 {
442 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
443 reg = <0x481a0000 0x400>;
444 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
445 ti,hwmods = "spi1";
446 #address-cells = <1>;
447 #size-cells = <0>;
448 status = "disabled";
449 };
450
451 spi2: spi@481a2000 {
452 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
453 reg = <0x481a2000 0x400>;
454 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
455 ti,hwmods = "spi2";
456 #address-cells = <1>;
457 #size-cells = <0>;
458 status = "disabled";
459 };
460
461 spi3: spi@481a4000 {
462 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
463 reg = <0x481a4000 0x400>;
464 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
465 ti,hwmods = "spi3";
466 #address-cells = <1>;
467 #size-cells = <0>;
468 status = "disabled";
469 };
470
471 spi4: spi@48345000 {
472 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
473 reg = <0x48345000 0x400>;
474 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
475 ti,hwmods = "spi4";
476 #address-cells = <1>;
477 #size-cells = <0>;
478 status = "disabled";
479 };
480
481 mac: ethernet@4a100000 {
482 compatible = "ti,am4372-cpsw","ti,cpsw";
483 reg = <0x4a100000 0x800
484 0x4a101200 0x100>;
485 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
486 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
487 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
488 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
489 #address-cells = <1>;
490 #size-cells = <1>;
491 ti,hwmods = "cpgmac0";
492 status = "disabled";
493 cpdma_channels = <8>;
494 ale_entries = <1024>;
495 bd_ram_size = <0x2000>;
496 no_bd_ram = <0>;
497 rx_descs = <64>;
498 mac_control = <0x20>;
499 slaves = <2>;
500 active_slave = <0>;
501 cpts_clock_mult = <0x80000000>;
502 cpts_clock_shift = <29>;
503 ranges;
504
505 davinci_mdio: mdio@4a101000 {
506 compatible = "ti,am4372-mdio","ti,davinci_mdio";
507 reg = <0x4a101000 0x100>;
508 #address-cells = <1>;
509 #size-cells = <0>;
510 ti,hwmods = "davinci_mdio";
511 bus_freq = <1000000>;
512 status = "disabled";
513 };
514
515 cpsw_emac0: slave@4a100200 {
516 /* Filled in by U-Boot */
517 mac-address = [ 00 00 00 00 00 00 ];
518 };
519
520 cpsw_emac1: slave@4a100300 {
521 /* Filled in by U-Boot */
522 mac-address = [ 00 00 00 00 00 00 ];
523 };
524 };
525
526 epwmss0: epwmss@48300000 {
527 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
528 reg = <0x48300000 0x10>;
529 #address-cells = <1>;
530 #size-cells = <1>;
531 ranges;
532 ti,hwmods = "epwmss0";
533 status = "disabled";
534
535 ecap0: ecap@48300100 {
536 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
537 #pwm-cells = <3>;
538 reg = <0x48300100 0x80>;
539 ti,hwmods = "ecap0";
540 status = "disabled";
541 };
542
543 ehrpwm0: ehrpwm@48300200 {
544 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
545 #pwm-cells = <3>;
546 reg = <0x48300200 0x80>;
547 ti,hwmods = "ehrpwm0";
548 status = "disabled";
549 };
550 };
551
552 epwmss1: epwmss@48302000 {
553 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
554 reg = <0x48302000 0x10>;
555 #address-cells = <1>;
556 #size-cells = <1>;
557 ranges;
558 ti,hwmods = "epwmss1";
559 status = "disabled";
560
561 ecap1: ecap@48302100 {
562 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
563 #pwm-cells = <3>;
564 reg = <0x48302100 0x80>;
565 ti,hwmods = "ecap1";
566 status = "disabled";
567 };
568
569 ehrpwm1: ehrpwm@48302200 {
570 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
571 #pwm-cells = <3>;
572 reg = <0x48302200 0x80>;
573 ti,hwmods = "ehrpwm1";
574 status = "disabled";
575 };
576 };
577
578 epwmss2: epwmss@48304000 {
579 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
580 reg = <0x48304000 0x10>;
581 #address-cells = <1>;
582 #size-cells = <1>;
583 ranges;
584 ti,hwmods = "epwmss2";
585 status = "disabled";
586
587 ecap2: ecap@48304100 {
588 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
589 #pwm-cells = <3>;
590 reg = <0x48304100 0x80>;
591 ti,hwmods = "ecap2";
592 status = "disabled";
593 };
594
595 ehrpwm2: ehrpwm@48304200 {
596 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
597 #pwm-cells = <3>;
598 reg = <0x48304200 0x80>;
599 ti,hwmods = "ehrpwm2";
600 status = "disabled";
601 };
602 };
603
604 epwmss3: epwmss@48306000 {
605 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
606 reg = <0x48306000 0x10>;
607 #address-cells = <1>;
608 #size-cells = <1>;
609 ranges;
610 ti,hwmods = "epwmss3";
611 status = "disabled";
612
613 ehrpwm3: ehrpwm@48306200 {
614 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
615 #pwm-cells = <3>;
616 reg = <0x48306200 0x80>;
617 ti,hwmods = "ehrpwm3";
618 status = "disabled";
619 };
620 };
621
622 epwmss4: epwmss@48308000 {
623 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
624 reg = <0x48308000 0x10>;
625 #address-cells = <1>;
626 #size-cells = <1>;
627 ranges;
628 ti,hwmods = "epwmss4";
629 status = "disabled";
630
631 ehrpwm4: ehrpwm@48308200 {
632 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
633 #pwm-cells = <3>;
634 reg = <0x48308200 0x80>;
635 ti,hwmods = "ehrpwm4";
636 status = "disabled";
637 };
638 };
639
640 epwmss5: epwmss@4830a000 {
641 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
642 reg = <0x4830a000 0x10>;
643 #address-cells = <1>;
644 #size-cells = <1>;
645 ranges;
646 ti,hwmods = "epwmss5";
647 status = "disabled";
648
649 ehrpwm5: ehrpwm@4830a200 {
650 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
651 #pwm-cells = <3>;
652 reg = <0x4830a200 0x80>;
653 ti,hwmods = "ehrpwm5";
654 status = "disabled";
655 };
656 };
657
658 sham: sham@53100000 {
659 compatible = "ti,omap5-sham";
660 ti,hwmods = "sham";
661 reg = <0x53100000 0x300>;
662 dmas = <&edma 36>;
663 dma-names = "rx";
664 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
665 };
666
667 aes: aes@53501000 {
668 compatible = "ti,omap4-aes";
669 ti,hwmods = "aes";
670 reg = <0x53501000 0xa0>;
671 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
672 dmas = <&edma 6
673 &edma 5>;
674 dma-names = "tx", "rx";
675 };
676
677 des: des@53701000 {
678 compatible = "ti,omap4-des";
679 ti,hwmods = "des";
680 reg = <0x53701000 0xa0>;
681 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
682 dmas = <&edma 34
683 &edma 33>;
684 dma-names = "tx", "rx";
685 };
686
687 mcasp0: mcasp@48038000 {
688 compatible = "ti,am33xx-mcasp-audio";
689 ti,hwmods = "mcasp0";
690 reg = <0x48038000 0x2000>,
691 <0x46000000 0x400000>;
692 reg-names = "mpu", "dat";
693 interrupts = <80>, <81>;
694 interrupt-names = "tx", "rx";
695 status = "disabled";
696 dmas = <&edma 8>,
697 <&edma 9>;
698 dma-names = "tx", "rx";
699 };
700
701 mcasp1: mcasp@4803C000 {
702 compatible = "ti,am33xx-mcasp-audio";
703 ti,hwmods = "mcasp1";
704 reg = <0x4803C000 0x2000>,
705 <0x46400000 0x400000>;
706 reg-names = "mpu", "dat";
707 interrupts = <82>, <83>;
708 interrupt-names = "tx", "rx";
709 status = "disabled";
710 dmas = <&edma 10>,
711 <&edma 11>;
712 dma-names = "tx", "rx";
713 };
714
715 elm: elm@48080000 {
716 compatible = "ti,am3352-elm";
717 reg = <0x48080000 0x2000>;
718 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
719 ti,hwmods = "elm";
720 clocks = <&l4ls_gclk>;
721 clock-names = "fck";
722 status = "disabled";
723 };
724
725 gpmc: gpmc@50000000 {
726 compatible = "ti,am3352-gpmc";
727 ti,hwmods = "gpmc";
728 clocks = <&l3s_gclk>;
729 clock-names = "fck";
730 reg = <0x50000000 0x2000>;
731 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
732 gpmc,num-cs = <7>;
733 gpmc,num-waitpins = <2>;
734 #address-cells = <2>;
735 #size-cells = <1>;
736 status = "disabled";
737 };
738 };
739};
740
741/include/ "am43xx-clocks.dtsi"