Loading...
1/*
2 * Device Tree Source for AM4372 SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/bus/ti-sysc.h>
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/clock/am4.h>
15
16/ {
17 compatible = "ti,am4372", "ti,am43";
18 interrupt-parent = <&wakeupgen>;
19 #address-cells = <1>;
20 #size-cells = <1>;
21 chosen { };
22
23 memory@0 {
24 device_type = "memory";
25 reg = <0 0>;
26 };
27
28 aliases {
29 i2c0 = &i2c0;
30 i2c1 = &i2c1;
31 i2c2 = &i2c2;
32 serial0 = &uart0;
33 serial1 = &uart1;
34 serial2 = &uart2;
35 serial3 = &uart3;
36 serial4 = &uart4;
37 serial5 = &uart5;
38 ethernet0 = &cpsw_port1;
39 ethernet1 = &cpsw_port2;
40 spi0 = &qspi;
41 };
42
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46 cpu: cpu@0 {
47 compatible = "arm,cortex-a9";
48 enable-method = "ti,am4372";
49 device_type = "cpu";
50 reg = <0>;
51
52 clocks = <&dpll_mpu_ck>;
53 clock-names = "cpu";
54
55 operating-points-v2 = <&cpu0_opp_table>;
56
57 clock-latency = <300000>; /* From omap-cpufreq driver */
58 cpu-idle-states = <&mpu_gate>;
59 };
60
61 idle-states {
62 mpu_gate: mpu_gate {
63 compatible = "arm,idle-state";
64 entry-latency-us = <40>;
65 exit-latency-us = <100>;
66 min-residency-us = <300>;
67 local-timer-stop;
68 };
69 };
70 };
71
72 cpu0_opp_table: opp-table {
73 compatible = "operating-points-v2-ti-cpu";
74 syscon = <&scm_conf>;
75
76 opp50-300000000 {
77 opp-hz = /bits/ 64 <300000000>;
78 opp-microvolt = <950000 931000 969000>;
79 opp-supported-hw = <0xFF 0x01>;
80 opp-suspend;
81 };
82
83 opp100-600000000 {
84 opp-hz = /bits/ 64 <600000000>;
85 opp-microvolt = <1100000 1078000 1122000>;
86 opp-supported-hw = <0xFF 0x04>;
87 };
88
89 opp120-720000000 {
90 opp-hz = /bits/ 64 <720000000>;
91 opp-microvolt = <1200000 1176000 1224000>;
92 opp-supported-hw = <0xFF 0x08>;
93 };
94
95 oppturbo-800000000 {
96 opp-hz = /bits/ 64 <800000000>;
97 opp-microvolt = <1260000 1234800 1285200>;
98 opp-supported-hw = <0xFF 0x10>;
99 };
100
101 oppnitro-1000000000 {
102 opp-hz = /bits/ 64 <1000000000>;
103 opp-microvolt = <1325000 1298500 1351500>;
104 opp-supported-hw = <0xFF 0x20>;
105 };
106 };
107
108 soc {
109 compatible = "ti,omap-infra";
110 };
111
112 gic: interrupt-controller@48241000 {
113 compatible = "arm,cortex-a9-gic";
114 interrupt-controller;
115 #interrupt-cells = <3>;
116 reg = <0x48241000 0x1000>,
117 <0x48240100 0x0100>;
118 interrupt-parent = <&gic>;
119 };
120
121 wakeupgen: interrupt-controller@48281000 {
122 compatible = "ti,omap4-wugen-mpu";
123 interrupt-controller;
124 #interrupt-cells = <3>;
125 reg = <0x48281000 0x1000>;
126 interrupt-parent = <&gic>;
127 };
128
129 scu: scu@48240000 {
130 compatible = "arm,cortex-a9-scu";
131 reg = <0x48240000 0x100>;
132 };
133
134 global_timer: timer@48240200 {
135 compatible = "arm,cortex-a9-global-timer";
136 reg = <0x48240200 0x100>;
137 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
138 interrupt-parent = <&gic>;
139 clocks = <&mpu_periphclk>;
140 };
141
142 local_timer: timer@48240600 {
143 compatible = "arm,cortex-a9-twd-timer";
144 reg = <0x48240600 0x100>;
145 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
146 interrupt-parent = <&gic>;
147 clocks = <&mpu_periphclk>;
148 };
149
150 cache-controller@48242000 {
151 compatible = "arm,pl310-cache";
152 reg = <0x48242000 0x1000>;
153 cache-unified;
154 cache-level = <2>;
155 };
156
157 ocp@44000000 {
158 compatible = "simple-pm-bus";
159 power-domains = <&prm_per>;
160 clocks = <&l3_clkctrl AM4_L3_L3_MAIN_CLKCTRL 0>;
161 clock-names = "fck";
162 #address-cells = <1>;
163 #size-cells = <1>;
164 ranges;
165 ti,no-idle;
166
167 l3-noc@44000000 {
168 compatible = "ti,am4372-l3-noc";
169 reg = <0x44000000 0x400000>,
170 <0x44800000 0x400000>;
171 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
173 };
174
175 l4_wkup: interconnect@44c00000 {
176 };
177 l4_per: interconnect@48000000 {
178 };
179 l4_fast: interconnect@4a000000 {
180 };
181
182 target-module@4c000000 {
183 compatible = "ti,sysc-omap4-simple", "ti,sysc";
184 reg = <0x4c000000 0x4>;
185 reg-names = "rev";
186 clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>;
187 clock-names = "fck";
188 ti,no-idle;
189 #address-cells = <1>;
190 #size-cells = <1>;
191 ranges = <0x0 0x4c000000 0x1000000>;
192
193 emif: emif@0 {
194 compatible = "ti,emif-am4372";
195 reg = <0 0x1000000>;
196 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
197 sram = <&pm_sram_code
198 &pm_sram_data>;
199 };
200 };
201
202 target-module@49000000 {
203 compatible = "ti,sysc-omap4", "ti,sysc";
204 reg = <0x49000000 0x4>;
205 reg-names = "rev";
206 clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>;
207 clock-names = "fck";
208 #address-cells = <1>;
209 #size-cells = <1>;
210 ranges = <0x0 0x49000000 0x10000>;
211
212 edma: dma@0 {
213 compatible = "ti,edma3-tpcc";
214 reg = <0 0x10000>;
215 reg-names = "edma3_cc";
216 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
219 interrupt-names = "edma3_ccint", "edma3_mperr",
220 "edma3_ccerrint";
221 dma-requests = <64>;
222 #dma-cells = <2>;
223
224 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
225 <&edma_tptc2 0>;
226
227 ti,edma-memcpy-channels = <58 59>;
228 };
229 };
230
231 target-module@49800000 {
232 compatible = "ti,sysc-omap4", "ti,sysc";
233 reg = <0x49800000 0x4>,
234 <0x49800010 0x4>;
235 reg-names = "rev", "sysc";
236 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
237 ti,sysc-midle = <SYSC_IDLE_FORCE>;
238 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
239 <SYSC_IDLE_SMART>;
240 clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>;
241 clock-names = "fck";
242 #address-cells = <1>;
243 #size-cells = <1>;
244 ranges = <0x0 0x49800000 0x100000>;
245
246 edma_tptc0: dma@0 {
247 compatible = "ti,edma3-tptc";
248 reg = <0 0x100000>;
249 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
250 interrupt-names = "edma3_tcerrint";
251 };
252 };
253
254 target-module@49900000 {
255 compatible = "ti,sysc-omap4", "ti,sysc";
256 reg = <0x49900000 0x4>,
257 <0x49900010 0x4>;
258 reg-names = "rev", "sysc";
259 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
260 ti,sysc-midle = <SYSC_IDLE_FORCE>;
261 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
262 <SYSC_IDLE_SMART>;
263 clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>;
264 clock-names = "fck";
265 #address-cells = <1>;
266 #size-cells = <1>;
267 ranges = <0x0 0x49900000 0x100000>;
268
269 edma_tptc1: dma@0 {
270 compatible = "ti,edma3-tptc";
271 reg = <0 0x100000>;
272 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
273 interrupt-names = "edma3_tcerrint";
274 };
275 };
276
277 target-module@49a00000 {
278 compatible = "ti,sysc-omap4", "ti,sysc";
279 reg = <0x49a00000 0x4>,
280 <0x49a00010 0x4>;
281 reg-names = "rev", "sysc";
282 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
283 ti,sysc-midle = <SYSC_IDLE_FORCE>;
284 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
285 <SYSC_IDLE_SMART>;
286 clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>;
287 clock-names = "fck";
288 #address-cells = <1>;
289 #size-cells = <1>;
290 ranges = <0x0 0x49a00000 0x100000>;
291
292 edma_tptc2: dma@0 {
293 compatible = "ti,edma3-tptc";
294 reg = <0 0x100000>;
295 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
296 interrupt-names = "edma3_tcerrint";
297 };
298 };
299
300 target-module@47810000 {
301 compatible = "ti,sysc-omap2", "ti,sysc";
302 reg = <0x478102fc 0x4>,
303 <0x47810110 0x4>,
304 <0x47810114 0x4>;
305 reg-names = "rev", "sysc", "syss";
306 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
307 SYSC_OMAP2_ENAWAKEUP |
308 SYSC_OMAP2_SOFTRESET |
309 SYSC_OMAP2_AUTOIDLE)>;
310 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
311 <SYSC_IDLE_NO>,
312 <SYSC_IDLE_SMART>;
313 ti,syss-mask = <1>;
314 clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>;
315 clock-names = "fck";
316 #address-cells = <1>;
317 #size-cells = <1>;
318 ranges = <0x0 0x47810000 0x1000>;
319
320 mmc3: mmc@0 {
321 compatible = "ti,am437-sdhci";
322 ti,needs-special-reset;
323 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
324 reg = <0x0 0x1000>;
325 status = "disabled";
326 };
327 };
328
329 sham_target: target-module@53100000 {
330 compatible = "ti,sysc-omap3-sham", "ti,sysc";
331 reg = <0x53100100 0x4>,
332 <0x53100110 0x4>,
333 <0x53100114 0x4>;
334 reg-names = "rev", "sysc", "syss";
335 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
336 SYSC_OMAP2_AUTOIDLE)>;
337 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
338 <SYSC_IDLE_NO>,
339 <SYSC_IDLE_SMART>;
340 ti,syss-mask = <1>;
341 /* Domains (P, C): per_pwrdm, l3_clkdm */
342 clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
343 clock-names = "fck";
344 #address-cells = <1>;
345 #size-cells = <1>;
346 ranges = <0x0 0x53100000 0x1000>;
347
348 sham: sham@0 {
349 compatible = "ti,omap5-sham";
350 reg = <0 0x300>;
351 dmas = <&edma 36 0>;
352 dma-names = "rx";
353 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
354 };
355 };
356
357 aes_target: target-module@53501000 {
358 compatible = "ti,sysc-omap2", "ti,sysc";
359 reg = <0x53501080 0x4>,
360 <0x53501084 0x4>,
361 <0x53501088 0x4>;
362 reg-names = "rev", "sysc", "syss";
363 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
364 SYSC_OMAP2_AUTOIDLE)>;
365 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
366 <SYSC_IDLE_NO>,
367 <SYSC_IDLE_SMART>,
368 <SYSC_IDLE_SMART_WKUP>;
369 ti,syss-mask = <1>;
370 /* Domains (P, C): per_pwrdm, l3_clkdm */
371 clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
372 clock-names = "fck";
373 #address-cells = <1>;
374 #size-cells = <1>;
375 ranges = <0x0 0x53501000 0x1000>;
376
377 aes: aes@0 {
378 compatible = "ti,omap4-aes";
379 reg = <0 0xa0>;
380 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
381 dmas = <&edma 6 0>,
382 <&edma 5 0>;
383 dma-names = "tx", "rx";
384 };
385 };
386
387 des_target: target-module@53701000 {
388 compatible = "ti,sysc-omap2", "ti,sysc";
389 reg = <0x53701030 0x4>,
390 <0x53701034 0x4>,
391 <0x53701038 0x4>;
392 reg-names = "rev", "sysc", "syss";
393 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
394 SYSC_OMAP2_AUTOIDLE)>;
395 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
396 <SYSC_IDLE_NO>,
397 <SYSC_IDLE_SMART>,
398 <SYSC_IDLE_SMART_WKUP>;
399 ti,syss-mask = <1>;
400 /* Domains (P, C): per_pwrdm, l3_clkdm */
401 clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
402 clock-names = "fck";
403 #address-cells = <1>;
404 #size-cells = <1>;
405 ranges = <0 0x53701000 0x1000>;
406
407 des: des@0 {
408 compatible = "ti,omap4-des";
409 reg = <0 0xa0>;
410 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
411 dmas = <&edma 34 0>,
412 <&edma 33 0>;
413 dma-names = "tx", "rx";
414 };
415 };
416
417 pruss_tm: target-module@54400000 {
418 compatible = "ti,sysc-pruss", "ti,sysc";
419 reg = <0x54426000 0x4>,
420 <0x54426004 0x4>;
421 reg-names = "rev", "sysc";
422 ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
423 SYSC_PRUSS_SUB_MWAIT)>;
424 ti,sysc-midle = <SYSC_IDLE_FORCE>,
425 <SYSC_IDLE_NO>,
426 <SYSC_IDLE_SMART>;
427 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
428 <SYSC_IDLE_NO>,
429 <SYSC_IDLE_SMART>;
430 clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;
431 clock-names = "fck";
432 resets = <&prm_per 1>;
433 reset-names = "rstctrl";
434 #address-cells = <1>;
435 #size-cells = <1>;
436 ranges = <0x0 0x54400000 0x80000>;
437 };
438
439 target-module@50000000 {
440 compatible = "ti,sysc-omap2", "ti,sysc";
441 reg = <0x50000000 4>,
442 <0x50000010 4>,
443 <0x50000014 4>;
444 reg-names = "rev", "sysc", "syss";
445 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
446 <SYSC_IDLE_NO>,
447 <SYSC_IDLE_SMART>;
448 ti,syss-mask = <1>;
449 clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>;
450 clock-names = "fck";
451 #address-cells = <1>;
452 #size-cells = <1>;
453 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
454 <0x00000000 0x00000000 0x40000000>; /* data */
455
456 gpmc: gpmc@50000000 {
457 compatible = "ti,am3352-gpmc";
458 dmas = <&edma 52 0>;
459 dma-names = "rxtx";
460 clocks = <&l3s_gclk>;
461 clock-names = "fck";
462 reg = <0x50000000 0x2000>;
463 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
464 gpmc,num-cs = <7>;
465 gpmc,num-waitpins = <2>;
466 #address-cells = <2>;
467 #size-cells = <1>;
468 interrupt-controller;
469 #interrupt-cells = <2>;
470 gpio-controller;
471 #gpio-cells = <2>;
472 status = "disabled";
473 };
474 };
475
476 target-module@47900000 {
477 compatible = "ti,sysc-omap4", "ti,sysc";
478 reg = <0x47900000 0x4>,
479 <0x47900010 0x4>;
480 reg-names = "rev", "sysc";
481 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
482 <SYSC_IDLE_NO>,
483 <SYSC_IDLE_SMART>,
484 <SYSC_IDLE_SMART_WKUP>;
485 clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
486 clock-names = "fck";
487 #address-cells = <1>;
488 #size-cells = <1>;
489 ranges = <0x0 0x47900000 0x1000>,
490 <0x30000000 0x30000000 0x4000000>;
491
492 qspi: spi@0 {
493 compatible = "ti,am4372-qspi";
494 reg = <0 0x100>,
495 <0x30000000 0x4000000>;
496 reg-names = "qspi_base", "qspi_mmap";
497 clocks = <&dpll_per_m2_div4_ck>;
498 clock-names = "fck";
499 #address-cells = <1>;
500 #size-cells = <0>;
501 interrupts = <0 138 0x4>;
502 num-cs = <4>;
503 };
504 };
505
506 target-module@40300000 {
507 compatible = "ti,sysc-omap4-simple", "ti,sysc";
508 clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>;
509 clock-names = "fck";
510 ti,no-idle;
511 #address-cells = <1>;
512 #size-cells = <1>;
513 ranges = <0 0x40300000 0x40000>;
514
515 ocmcram: sram@0 {
516 compatible = "mmio-sram";
517 reg = <0 0x40000>; /* 256k */
518 ranges = <0 0 0x40000>;
519 #address-cells = <1>;
520 #size-cells = <1>;
521
522 pm_sram_code: pm-code-sram@0 {
523 compatible = "ti,sram";
524 reg = <0x0 0x1000>;
525 protect-exec;
526 };
527
528 pm_sram_data: pm-data-sram@1000 {
529 compatible = "ti,sram";
530 reg = <0x1000 0x1000>;
531 pool;
532 };
533 };
534 };
535
536 target-module@56000000 {
537 compatible = "ti,sysc-omap4", "ti,sysc";
538 reg = <0x5600fe00 0x4>,
539 <0x5600fe10 0x4>;
540 reg-names = "rev", "sysc";
541 ti,sysc-midle = <SYSC_IDLE_FORCE>,
542 <SYSC_IDLE_NO>,
543 <SYSC_IDLE_SMART>;
544 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
545 <SYSC_IDLE_NO>,
546 <SYSC_IDLE_SMART>;
547 clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
548 clock-names = "fck";
549 power-domains = <&prm_gfx>;
550 resets = <&prm_gfx 0>;
551 reset-names = "rstctrl";
552 #address-cells = <1>;
553 #size-cells = <1>;
554 ranges = <0 0x56000000 0x1000000>;
555 };
556 };
557};
558
559#include "am437x-l4.dtsi"
560#include "am43xx-clocks.dtsi"
561
562&prcm {
563 prm_mpu: prm@300 {
564 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
565 reg = <0x300 0x100>;
566 #power-domain-cells = <0>;
567 };
568
569 prm_gfx: prm@400 {
570 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
571 reg = <0x400 0x100>;
572 #power-domain-cells = <0>;
573 #reset-cells = <1>;
574 };
575
576 prm_rtc: prm@500 {
577 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
578 reg = <0x500 0x100>;
579 #power-domain-cells = <0>;
580 };
581
582 prm_tamper: prm@600 {
583 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
584 reg = <0x600 0x100>;
585 #power-domain-cells = <0>;
586 };
587
588 prm_cefuse: prm@700 {
589 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
590 reg = <0x700 0x100>;
591 #power-domain-cells = <0>;
592 };
593
594 prm_per: prm@800 {
595 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
596 reg = <0x800 0x100>;
597 #reset-cells = <1>;
598 #power-domain-cells = <0>;
599 };
600
601 prm_wkup: prm@2000 {
602 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
603 reg = <0x2000 0x100>;
604 #reset-cells = <1>;
605 #power-domain-cells = <0>;
606 };
607
608 prm_device: prm@4000 {
609 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
610 reg = <0x4000 0x100>;
611 #reset-cells = <1>;
612 };
613};
614
615/* Preferred always-on timer for clocksource */
616&timer1_target {
617 ti,no-reset-on-init;
618 ti,no-idle;
619 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>,
620 <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
621 clock-names = "fck", "ick";
622 timer@0 {
623 assigned-clocks = <&timer1_fck>;
624 assigned-clock-parents = <&sys_clkin_ck>;
625 };
626};
627
628/* Preferred timer for clockevent */
629&timer2_target {
630 ti,no-reset-on-init;
631 ti,no-idle;
632 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>,
633 <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>;
634 clock-names = "fck", "ick";
635 timer@0 {
636 assigned-clocks = <&timer2_fck>;
637 assigned-clock-parents = <&sys_clkin_ck>;
638 };
639};
1/*
2 * Device Tree Source for AM4372 SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
14#include "skeleton.dtsi"
15
16/ {
17 compatible = "ti,am4372", "ti,am43";
18 interrupt-parent = <&wakeupgen>;
19
20
21 aliases {
22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
25 serial0 = &uart0;
26 serial1 = &uart1;
27 serial2 = &uart2;
28 serial3 = &uart3;
29 serial4 = &uart4;
30 serial5 = &uart5;
31 ethernet0 = &cpsw_emac0;
32 ethernet1 = &cpsw_emac1;
33 spi0 = &qspi;
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39 cpu: cpu@0 {
40 compatible = "arm,cortex-a9";
41 device_type = "cpu";
42 reg = <0>;
43
44 clocks = <&dpll_mpu_ck>;
45 clock-names = "cpu";
46
47 clock-latency = <300000>; /* From omap-cpufreq driver */
48 };
49 };
50
51 gic: interrupt-controller@48241000 {
52 compatible = "arm,cortex-a9-gic";
53 interrupt-controller;
54 #interrupt-cells = <3>;
55 reg = <0x48241000 0x1000>,
56 <0x48240100 0x0100>;
57 interrupt-parent = <&gic>;
58 };
59
60 wakeupgen: interrupt-controller@48281000 {
61 compatible = "ti,omap4-wugen-mpu";
62 interrupt-controller;
63 #interrupt-cells = <3>;
64 reg = <0x48281000 0x1000>;
65 interrupt-parent = <&gic>;
66 };
67
68 scu: scu@48240000 {
69 compatible = "arm,cortex-a9-scu";
70 reg = <0x48240000 0x100>;
71 };
72
73 global_timer: timer@48240200 {
74 compatible = "arm,cortex-a9-global-timer";
75 reg = <0x48240200 0x100>;
76 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
77 interrupt-parent = <&gic>;
78 clocks = <&mpu_periphclk>;
79 };
80
81 local_timer: timer@48240600 {
82 compatible = "arm,cortex-a9-twd-timer";
83 reg = <0x48240600 0x100>;
84 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
85 interrupt-parent = <&gic>;
86 clocks = <&mpu_periphclk>;
87 };
88
89 l2-cache-controller@48242000 {
90 compatible = "arm,pl310-cache";
91 reg = <0x48242000 0x1000>;
92 cache-unified;
93 cache-level = <2>;
94 };
95
96 ocp {
97 compatible = "ti,am4372-l3-noc", "simple-bus";
98 #address-cells = <1>;
99 #size-cells = <1>;
100 ranges;
101 ti,hwmods = "l3_main";
102 reg = <0x44000000 0x400000
103 0x44800000 0x400000>;
104 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
106
107 l4_wkup: l4_wkup@44c00000 {
108 compatible = "ti,am4-l4-wkup", "simple-bus";
109 #address-cells = <1>;
110 #size-cells = <1>;
111 ranges = <0 0x44c00000 0x287000>;
112
113 wkup_m3: wkup_m3@100000 {
114 compatible = "ti,am4372-wkup-m3";
115 reg = <0x100000 0x4000>,
116 <0x180000 0x2000>;
117 reg-names = "umem", "dmem";
118 ti,hwmods = "wkup_m3";
119 ti,pm-firmware = "am335x-pm-firmware.elf";
120 };
121
122 prcm: prcm@1f0000 {
123 compatible = "ti,am4-prcm";
124 reg = <0x1f0000 0x11000>;
125 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
126
127 prcm_clocks: clocks {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 };
131
132 prcm_clockdomains: clockdomains {
133 };
134 };
135
136 scm: scm@210000 {
137 compatible = "ti,am4-scm", "simple-bus";
138 reg = <0x210000 0x4000>;
139 #address-cells = <1>;
140 #size-cells = <1>;
141 ranges = <0 0x210000 0x4000>;
142
143 am43xx_pinmux: pinmux@800 {
144 compatible = "ti,am437-padconf",
145 "pinctrl-single";
146 reg = <0x800 0x31c>;
147 #address-cells = <1>;
148 #size-cells = <0>;
149 #interrupt-cells = <1>;
150 interrupt-controller;
151 pinctrl-single,register-width = <32>;
152 pinctrl-single,function-mask = <0xffffffff>;
153 };
154
155 scm_conf: scm_conf@0 {
156 compatible = "syscon";
157 reg = <0x0 0x800>;
158 #address-cells = <1>;
159 #size-cells = <1>;
160
161 scm_clocks: clocks {
162 #address-cells = <1>;
163 #size-cells = <0>;
164 };
165 };
166
167 wkup_m3_ipc: wkup_m3_ipc@1324 {
168 compatible = "ti,am4372-wkup-m3-ipc";
169 reg = <0x1324 0x44>;
170 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
171 ti,rproc = <&wkup_m3>;
172 mboxes = <&mailbox &mbox_wkupm3>;
173 };
174
175 edma_xbar: dma-router@f90 {
176 compatible = "ti,am335x-edma-crossbar";
177 reg = <0xf90 0x40>;
178 #dma-cells = <3>;
179 dma-requests = <64>;
180 dma-masters = <&edma>;
181 };
182
183 scm_clockdomains: clockdomains {
184 };
185 };
186 };
187
188 emif: emif@4c000000 {
189 compatible = "ti,emif-am4372";
190 reg = <0x4c000000 0x1000000>;
191 ti,hwmods = "emif";
192 };
193
194 edma: edma@49000000 {
195 compatible = "ti,edma3-tpcc";
196 ti,hwmods = "tpcc";
197 reg = <0x49000000 0x10000>;
198 reg-names = "edma3_cc";
199 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
202 interrupt-names = "edma3_ccint", "emda3_mperr",
203 "edma3_ccerrint";
204 dma-requests = <64>;
205 #dma-cells = <2>;
206
207 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
208 <&edma_tptc2 0>;
209
210 ti,edma-memcpy-channels = <58 59>;
211 };
212
213 edma_tptc0: tptc@49800000 {
214 compatible = "ti,edma3-tptc";
215 ti,hwmods = "tptc0";
216 reg = <0x49800000 0x100000>;
217 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
218 interrupt-names = "edma3_tcerrint";
219 };
220
221 edma_tptc1: tptc@49900000 {
222 compatible = "ti,edma3-tptc";
223 ti,hwmods = "tptc1";
224 reg = <0x49900000 0x100000>;
225 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
226 interrupt-names = "edma3_tcerrint";
227 };
228
229 edma_tptc2: tptc@49a00000 {
230 compatible = "ti,edma3-tptc";
231 ti,hwmods = "tptc2";
232 reg = <0x49a00000 0x100000>;
233 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
234 interrupt-names = "edma3_tcerrint";
235 };
236
237 uart0: serial@44e09000 {
238 compatible = "ti,am4372-uart","ti,omap2-uart";
239 reg = <0x44e09000 0x2000>;
240 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
241 ti,hwmods = "uart1";
242 };
243
244 uart1: serial@48022000 {
245 compatible = "ti,am4372-uart","ti,omap2-uart";
246 reg = <0x48022000 0x2000>;
247 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
248 ti,hwmods = "uart2";
249 status = "disabled";
250 };
251
252 uart2: serial@48024000 {
253 compatible = "ti,am4372-uart","ti,omap2-uart";
254 reg = <0x48024000 0x2000>;
255 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
256 ti,hwmods = "uart3";
257 status = "disabled";
258 };
259
260 uart3: serial@481a6000 {
261 compatible = "ti,am4372-uart","ti,omap2-uart";
262 reg = <0x481a6000 0x2000>;
263 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
264 ti,hwmods = "uart4";
265 status = "disabled";
266 };
267
268 uart4: serial@481a8000 {
269 compatible = "ti,am4372-uart","ti,omap2-uart";
270 reg = <0x481a8000 0x2000>;
271 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
272 ti,hwmods = "uart5";
273 status = "disabled";
274 };
275
276 uart5: serial@481aa000 {
277 compatible = "ti,am4372-uart","ti,omap2-uart";
278 reg = <0x481aa000 0x2000>;
279 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
280 ti,hwmods = "uart6";
281 status = "disabled";
282 };
283
284 mailbox: mailbox@480C8000 {
285 compatible = "ti,omap4-mailbox";
286 reg = <0x480C8000 0x200>;
287 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
288 ti,hwmods = "mailbox";
289 #mbox-cells = <1>;
290 ti,mbox-num-users = <4>;
291 ti,mbox-num-fifos = <8>;
292 mbox_wkupm3: wkup_m3 {
293 ti,mbox-send-noirq;
294 ti,mbox-tx = <0 0 0>;
295 ti,mbox-rx = <0 0 3>;
296 };
297 };
298
299 timer1: timer@44e31000 {
300 compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
301 reg = <0x44e31000 0x400>;
302 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
303 ti,timer-alwon;
304 ti,hwmods = "timer1";
305 };
306
307 timer2: timer@48040000 {
308 compatible = "ti,am4372-timer","ti,am335x-timer";
309 reg = <0x48040000 0x400>;
310 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
311 ti,hwmods = "timer2";
312 };
313
314 timer3: timer@48042000 {
315 compatible = "ti,am4372-timer","ti,am335x-timer";
316 reg = <0x48042000 0x400>;
317 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
318 ti,hwmods = "timer3";
319 status = "disabled";
320 };
321
322 timer4: timer@48044000 {
323 compatible = "ti,am4372-timer","ti,am335x-timer";
324 reg = <0x48044000 0x400>;
325 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
326 ti,timer-pwm;
327 ti,hwmods = "timer4";
328 status = "disabled";
329 };
330
331 timer5: timer@48046000 {
332 compatible = "ti,am4372-timer","ti,am335x-timer";
333 reg = <0x48046000 0x400>;
334 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
335 ti,timer-pwm;
336 ti,hwmods = "timer5";
337 status = "disabled";
338 };
339
340 timer6: timer@48048000 {
341 compatible = "ti,am4372-timer","ti,am335x-timer";
342 reg = <0x48048000 0x400>;
343 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
344 ti,timer-pwm;
345 ti,hwmods = "timer6";
346 status = "disabled";
347 };
348
349 timer7: timer@4804a000 {
350 compatible = "ti,am4372-timer","ti,am335x-timer";
351 reg = <0x4804a000 0x400>;
352 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
353 ti,timer-pwm;
354 ti,hwmods = "timer7";
355 status = "disabled";
356 };
357
358 timer8: timer@481c1000 {
359 compatible = "ti,am4372-timer","ti,am335x-timer";
360 reg = <0x481c1000 0x400>;
361 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
362 ti,hwmods = "timer8";
363 status = "disabled";
364 };
365
366 timer9: timer@4833d000 {
367 compatible = "ti,am4372-timer","ti,am335x-timer";
368 reg = <0x4833d000 0x400>;
369 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
370 ti,hwmods = "timer9";
371 status = "disabled";
372 };
373
374 timer10: timer@4833f000 {
375 compatible = "ti,am4372-timer","ti,am335x-timer";
376 reg = <0x4833f000 0x400>;
377 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
378 ti,hwmods = "timer10";
379 status = "disabled";
380 };
381
382 timer11: timer@48341000 {
383 compatible = "ti,am4372-timer","ti,am335x-timer";
384 reg = <0x48341000 0x400>;
385 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
386 ti,hwmods = "timer11";
387 status = "disabled";
388 };
389
390 counter32k: counter@44e86000 {
391 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
392 reg = <0x44e86000 0x40>;
393 ti,hwmods = "counter_32k";
394 };
395
396 rtc: rtc@44e3e000 {
397 compatible = "ti,am4372-rtc", "ti,am3352-rtc",
398 "ti,da830-rtc";
399 reg = <0x44e3e000 0x1000>;
400 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
401 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
402 ti,hwmods = "rtc";
403 clocks = <&clk_32768_ck>;
404 clock-names = "int-clk";
405 status = "disabled";
406 };
407
408 wdt: wdt@44e35000 {
409 compatible = "ti,am4372-wdt","ti,omap3-wdt";
410 reg = <0x44e35000 0x1000>;
411 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
412 ti,hwmods = "wd_timer2";
413 };
414
415 gpio0: gpio@44e07000 {
416 compatible = "ti,am4372-gpio","ti,omap4-gpio";
417 reg = <0x44e07000 0x1000>;
418 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
419 gpio-controller;
420 #gpio-cells = <2>;
421 interrupt-controller;
422 #interrupt-cells = <2>;
423 ti,hwmods = "gpio1";
424 status = "disabled";
425 };
426
427 gpio1: gpio@4804c000 {
428 compatible = "ti,am4372-gpio","ti,omap4-gpio";
429 reg = <0x4804c000 0x1000>;
430 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
431 gpio-controller;
432 #gpio-cells = <2>;
433 interrupt-controller;
434 #interrupt-cells = <2>;
435 ti,hwmods = "gpio2";
436 status = "disabled";
437 };
438
439 gpio2: gpio@481ac000 {
440 compatible = "ti,am4372-gpio","ti,omap4-gpio";
441 reg = <0x481ac000 0x1000>;
442 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
443 gpio-controller;
444 #gpio-cells = <2>;
445 interrupt-controller;
446 #interrupt-cells = <2>;
447 ti,hwmods = "gpio3";
448 status = "disabled";
449 };
450
451 gpio3: gpio@481ae000 {
452 compatible = "ti,am4372-gpio","ti,omap4-gpio";
453 reg = <0x481ae000 0x1000>;
454 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
455 gpio-controller;
456 #gpio-cells = <2>;
457 interrupt-controller;
458 #interrupt-cells = <2>;
459 ti,hwmods = "gpio4";
460 status = "disabled";
461 };
462
463 gpio4: gpio@48320000 {
464 compatible = "ti,am4372-gpio","ti,omap4-gpio";
465 reg = <0x48320000 0x1000>;
466 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
467 gpio-controller;
468 #gpio-cells = <2>;
469 interrupt-controller;
470 #interrupt-cells = <2>;
471 ti,hwmods = "gpio5";
472 status = "disabled";
473 };
474
475 gpio5: gpio@48322000 {
476 compatible = "ti,am4372-gpio","ti,omap4-gpio";
477 reg = <0x48322000 0x1000>;
478 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
479 gpio-controller;
480 #gpio-cells = <2>;
481 interrupt-controller;
482 #interrupt-cells = <2>;
483 ti,hwmods = "gpio6";
484 status = "disabled";
485 };
486
487 hwspinlock: spinlock@480ca000 {
488 compatible = "ti,omap4-hwspinlock";
489 reg = <0x480ca000 0x1000>;
490 ti,hwmods = "spinlock";
491 #hwlock-cells = <1>;
492 };
493
494 i2c0: i2c@44e0b000 {
495 compatible = "ti,am4372-i2c","ti,omap4-i2c";
496 reg = <0x44e0b000 0x1000>;
497 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
498 ti,hwmods = "i2c1";
499 #address-cells = <1>;
500 #size-cells = <0>;
501 status = "disabled";
502 };
503
504 i2c1: i2c@4802a000 {
505 compatible = "ti,am4372-i2c","ti,omap4-i2c";
506 reg = <0x4802a000 0x1000>;
507 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
508 ti,hwmods = "i2c2";
509 #address-cells = <1>;
510 #size-cells = <0>;
511 status = "disabled";
512 };
513
514 i2c2: i2c@4819c000 {
515 compatible = "ti,am4372-i2c","ti,omap4-i2c";
516 reg = <0x4819c000 0x1000>;
517 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
518 ti,hwmods = "i2c3";
519 #address-cells = <1>;
520 #size-cells = <0>;
521 status = "disabled";
522 };
523
524 spi0: spi@48030000 {
525 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
526 reg = <0x48030000 0x400>;
527 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
528 ti,hwmods = "spi0";
529 #address-cells = <1>;
530 #size-cells = <0>;
531 status = "disabled";
532 };
533
534 mmc1: mmc@48060000 {
535 compatible = "ti,omap4-hsmmc";
536 reg = <0x48060000 0x1000>;
537 ti,hwmods = "mmc1";
538 ti,dual-volt;
539 ti,needs-special-reset;
540 dmas = <&edma 24 0>,
541 <&edma 25 0>;
542 dma-names = "tx", "rx";
543 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
544 status = "disabled";
545 };
546
547 mmc2: mmc@481d8000 {
548 compatible = "ti,omap4-hsmmc";
549 reg = <0x481d8000 0x1000>;
550 ti,hwmods = "mmc2";
551 ti,needs-special-reset;
552 dmas = <&edma 2 0>,
553 <&edma 3 0>;
554 dma-names = "tx", "rx";
555 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
556 status = "disabled";
557 };
558
559 mmc3: mmc@47810000 {
560 compatible = "ti,omap4-hsmmc";
561 reg = <0x47810000 0x1000>;
562 ti,hwmods = "mmc3";
563 ti,needs-special-reset;
564 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
565 status = "disabled";
566 };
567
568 spi1: spi@481a0000 {
569 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
570 reg = <0x481a0000 0x400>;
571 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
572 ti,hwmods = "spi1";
573 #address-cells = <1>;
574 #size-cells = <0>;
575 status = "disabled";
576 };
577
578 spi2: spi@481a2000 {
579 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
580 reg = <0x481a2000 0x400>;
581 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
582 ti,hwmods = "spi2";
583 #address-cells = <1>;
584 #size-cells = <0>;
585 status = "disabled";
586 };
587
588 spi3: spi@481a4000 {
589 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
590 reg = <0x481a4000 0x400>;
591 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
592 ti,hwmods = "spi3";
593 #address-cells = <1>;
594 #size-cells = <0>;
595 status = "disabled";
596 };
597
598 spi4: spi@48345000 {
599 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
600 reg = <0x48345000 0x400>;
601 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
602 ti,hwmods = "spi4";
603 #address-cells = <1>;
604 #size-cells = <0>;
605 status = "disabled";
606 };
607
608 mac: ethernet@4a100000 {
609 compatible = "ti,am4372-cpsw","ti,cpsw";
610 reg = <0x4a100000 0x800
611 0x4a101200 0x100>;
612 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
613 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
614 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
615 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
616 #address-cells = <1>;
617 #size-cells = <1>;
618 ti,hwmods = "cpgmac0";
619 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>,
620 <&dpll_clksel_mac_clk>;
621 clock-names = "fck", "cpts", "50mclk";
622 assigned-clocks = <&dpll_clksel_mac_clk>;
623 assigned-clock-rates = <50000000>;
624 status = "disabled";
625 cpdma_channels = <8>;
626 ale_entries = <1024>;
627 bd_ram_size = <0x2000>;
628 no_bd_ram = <0>;
629 rx_descs = <64>;
630 mac_control = <0x20>;
631 slaves = <2>;
632 active_slave = <0>;
633 cpts_clock_mult = <0x80000000>;
634 cpts_clock_shift = <29>;
635 ranges;
636 syscon = <&scm_conf>;
637
638 davinci_mdio: mdio@4a101000 {
639 compatible = "ti,am4372-mdio","ti,davinci_mdio";
640 reg = <0x4a101000 0x100>;
641 #address-cells = <1>;
642 #size-cells = <0>;
643 ti,hwmods = "davinci_mdio";
644 bus_freq = <1000000>;
645 status = "disabled";
646 };
647
648 cpsw_emac0: slave@4a100200 {
649 /* Filled in by U-Boot */
650 mac-address = [ 00 00 00 00 00 00 ];
651 };
652
653 cpsw_emac1: slave@4a100300 {
654 /* Filled in by U-Boot */
655 mac-address = [ 00 00 00 00 00 00 ];
656 };
657
658 phy_sel: cpsw-phy-sel@44e10650 {
659 compatible = "ti,am43xx-cpsw-phy-sel";
660 reg= <0x44e10650 0x4>;
661 reg-names = "gmii-sel";
662 };
663 };
664
665 epwmss0: epwmss@48300000 {
666 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
667 reg = <0x48300000 0x10>;
668 #address-cells = <1>;
669 #size-cells = <1>;
670 ranges;
671 ti,hwmods = "epwmss0";
672 status = "disabled";
673
674 ecap0: ecap@48300100 {
675 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
676 #pwm-cells = <3>;
677 reg = <0x48300100 0x80>;
678 ti,hwmods = "ecap0";
679 status = "disabled";
680 };
681
682 ehrpwm0: ehrpwm@48300200 {
683 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
684 #pwm-cells = <3>;
685 reg = <0x48300200 0x80>;
686 ti,hwmods = "ehrpwm0";
687 status = "disabled";
688 };
689 };
690
691 epwmss1: epwmss@48302000 {
692 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
693 reg = <0x48302000 0x10>;
694 #address-cells = <1>;
695 #size-cells = <1>;
696 ranges;
697 ti,hwmods = "epwmss1";
698 status = "disabled";
699
700 ecap1: ecap@48302100 {
701 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
702 #pwm-cells = <3>;
703 reg = <0x48302100 0x80>;
704 ti,hwmods = "ecap1";
705 status = "disabled";
706 };
707
708 ehrpwm1: ehrpwm@48302200 {
709 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
710 #pwm-cells = <3>;
711 reg = <0x48302200 0x80>;
712 ti,hwmods = "ehrpwm1";
713 status = "disabled";
714 };
715 };
716
717 epwmss2: epwmss@48304000 {
718 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
719 reg = <0x48304000 0x10>;
720 #address-cells = <1>;
721 #size-cells = <1>;
722 ranges;
723 ti,hwmods = "epwmss2";
724 status = "disabled";
725
726 ecap2: ecap@48304100 {
727 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
728 #pwm-cells = <3>;
729 reg = <0x48304100 0x80>;
730 ti,hwmods = "ecap2";
731 status = "disabled";
732 };
733
734 ehrpwm2: ehrpwm@48304200 {
735 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
736 #pwm-cells = <3>;
737 reg = <0x48304200 0x80>;
738 ti,hwmods = "ehrpwm2";
739 status = "disabled";
740 };
741 };
742
743 epwmss3: epwmss@48306000 {
744 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
745 reg = <0x48306000 0x10>;
746 #address-cells = <1>;
747 #size-cells = <1>;
748 ranges;
749 ti,hwmods = "epwmss3";
750 status = "disabled";
751
752 ehrpwm3: ehrpwm@48306200 {
753 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
754 #pwm-cells = <3>;
755 reg = <0x48306200 0x80>;
756 ti,hwmods = "ehrpwm3";
757 status = "disabled";
758 };
759 };
760
761 epwmss4: epwmss@48308000 {
762 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
763 reg = <0x48308000 0x10>;
764 #address-cells = <1>;
765 #size-cells = <1>;
766 ranges;
767 ti,hwmods = "epwmss4";
768 status = "disabled";
769
770 ehrpwm4: ehrpwm@48308200 {
771 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
772 #pwm-cells = <3>;
773 reg = <0x48308200 0x80>;
774 ti,hwmods = "ehrpwm4";
775 status = "disabled";
776 };
777 };
778
779 epwmss5: epwmss@4830a000 {
780 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
781 reg = <0x4830a000 0x10>;
782 #address-cells = <1>;
783 #size-cells = <1>;
784 ranges;
785 ti,hwmods = "epwmss5";
786 status = "disabled";
787
788 ehrpwm5: ehrpwm@4830a200 {
789 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
790 #pwm-cells = <3>;
791 reg = <0x4830a200 0x80>;
792 ti,hwmods = "ehrpwm5";
793 status = "disabled";
794 };
795 };
796
797 tscadc: tscadc@44e0d000 {
798 compatible = "ti,am3359-tscadc";
799 reg = <0x44e0d000 0x1000>;
800 ti,hwmods = "adc_tsc";
801 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&adc_tsc_fck>;
803 clock-names = "fck";
804 status = "disabled";
805
806 tsc {
807 compatible = "ti,am3359-tsc";
808 };
809
810 adc {
811 #io-channel-cells = <1>;
812 compatible = "ti,am3359-adc";
813 };
814
815 };
816
817 sham: sham@53100000 {
818 compatible = "ti,omap5-sham";
819 ti,hwmods = "sham";
820 reg = <0x53100000 0x300>;
821 dmas = <&edma 36 0>;
822 dma-names = "rx";
823 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
824 };
825
826 aes: aes@53501000 {
827 compatible = "ti,omap4-aes";
828 ti,hwmods = "aes";
829 reg = <0x53501000 0xa0>;
830 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
831 dmas = <&edma 6 0>,
832 <&edma 5 0>;
833 dma-names = "tx", "rx";
834 };
835
836 des: des@53701000 {
837 compatible = "ti,omap4-des";
838 ti,hwmods = "des";
839 reg = <0x53701000 0xa0>;
840 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
841 dmas = <&edma 34 0>,
842 <&edma 33 0>;
843 dma-names = "tx", "rx";
844 };
845
846 mcasp0: mcasp@48038000 {
847 compatible = "ti,am33xx-mcasp-audio";
848 ti,hwmods = "mcasp0";
849 reg = <0x48038000 0x2000>,
850 <0x46000000 0x400000>;
851 reg-names = "mpu", "dat";
852 interrupts = <80>, <81>;
853 interrupt-names = "tx", "rx";
854 status = "disabled";
855 dmas = <&edma 8 2>,
856 <&edma 9 2>;
857 dma-names = "tx", "rx";
858 };
859
860 mcasp1: mcasp@4803C000 {
861 compatible = "ti,am33xx-mcasp-audio";
862 ti,hwmods = "mcasp1";
863 reg = <0x4803C000 0x2000>,
864 <0x46400000 0x400000>;
865 reg-names = "mpu", "dat";
866 interrupts = <82>, <83>;
867 interrupt-names = "tx", "rx";
868 status = "disabled";
869 dmas = <&edma 10 2>,
870 <&edma 11 2>;
871 dma-names = "tx", "rx";
872 };
873
874 elm: elm@48080000 {
875 compatible = "ti,am3352-elm";
876 reg = <0x48080000 0x2000>;
877 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
878 ti,hwmods = "elm";
879 clocks = <&l4ls_gclk>;
880 clock-names = "fck";
881 status = "disabled";
882 };
883
884 gpmc: gpmc@50000000 {
885 compatible = "ti,am3352-gpmc";
886 ti,hwmods = "gpmc";
887 dmas = <&edma 52 0>;
888 dma-names = "rxtx";
889 clocks = <&l3s_gclk>;
890 clock-names = "fck";
891 reg = <0x50000000 0x2000>;
892 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
893 gpmc,num-cs = <7>;
894 gpmc,num-waitpins = <2>;
895 #address-cells = <2>;
896 #size-cells = <1>;
897 interrupt-controller;
898 #interrupt-cells = <2>;
899 status = "disabled";
900 };
901
902 ocp2scp0: ocp2scp@483a8000 {
903 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
904 #address-cells = <1>;
905 #size-cells = <1>;
906 ranges;
907 ti,hwmods = "ocp2scp0";
908
909 usb2_phy1: phy@483a8000 {
910 compatible = "ti,am437x-usb2";
911 reg = <0x483a8000 0x8000>;
912 syscon-phy-power = <&scm_conf 0x620>;
913 clocks = <&usb_phy0_always_on_clk32k>,
914 <&usb_otg_ss0_refclk960m>;
915 clock-names = "wkupclk", "refclk";
916 #phy-cells = <0>;
917 status = "disabled";
918 };
919 };
920
921 ocp2scp1: ocp2scp@483e8000 {
922 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
923 #address-cells = <1>;
924 #size-cells = <1>;
925 ranges;
926 ti,hwmods = "ocp2scp1";
927
928 usb2_phy2: phy@483e8000 {
929 compatible = "ti,am437x-usb2";
930 reg = <0x483e8000 0x8000>;
931 syscon-phy-power = <&scm_conf 0x628>;
932 clocks = <&usb_phy1_always_on_clk32k>,
933 <&usb_otg_ss1_refclk960m>;
934 clock-names = "wkupclk", "refclk";
935 #phy-cells = <0>;
936 status = "disabled";
937 };
938 };
939
940 dwc3_1: omap_dwc3@48380000 {
941 compatible = "ti,am437x-dwc3";
942 ti,hwmods = "usb_otg_ss0";
943 reg = <0x48380000 0x10000>;
944 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
945 #address-cells = <1>;
946 #size-cells = <1>;
947 utmi-mode = <1>;
948 ranges;
949
950 usb1: usb@48390000 {
951 compatible = "synopsys,dwc3";
952 reg = <0x48390000 0x10000>;
953 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
955 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
956 interrupt-names = "peripheral",
957 "host",
958 "otg";
959 phys = <&usb2_phy1>;
960 phy-names = "usb2-phy";
961 maximum-speed = "high-speed";
962 dr_mode = "otg";
963 status = "disabled";
964 snps,dis_u3_susphy_quirk;
965 snps,dis_u2_susphy_quirk;
966 };
967 };
968
969 dwc3_2: omap_dwc3@483c0000 {
970 compatible = "ti,am437x-dwc3";
971 ti,hwmods = "usb_otg_ss1";
972 reg = <0x483c0000 0x10000>;
973 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
974 #address-cells = <1>;
975 #size-cells = <1>;
976 utmi-mode = <1>;
977 ranges;
978
979 usb2: usb@483d0000 {
980 compatible = "synopsys,dwc3";
981 reg = <0x483d0000 0x10000>;
982 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
985 interrupt-names = "peripheral",
986 "host",
987 "otg";
988 phys = <&usb2_phy2>;
989 phy-names = "usb2-phy";
990 maximum-speed = "high-speed";
991 dr_mode = "otg";
992 status = "disabled";
993 snps,dis_u3_susphy_quirk;
994 snps,dis_u2_susphy_quirk;
995 };
996 };
997
998 qspi: qspi@47900000 {
999 compatible = "ti,am4372-qspi";
1000 reg = <0x47900000 0x100>,
1001 <0x30000000 0x4000000>;
1002 reg-names = "qspi_base", "qspi_mmap";
1003 #address-cells = <1>;
1004 #size-cells = <0>;
1005 ti,hwmods = "qspi";
1006 interrupts = <0 138 0x4>;
1007 num-cs = <4>;
1008 status = "disabled";
1009 };
1010
1011 hdq: hdq@48347000 {
1012 compatible = "ti,am4372-hdq";
1013 reg = <0x48347000 0x1000>;
1014 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
1015 clocks = <&func_12m_clk>;
1016 clock-names = "fck";
1017 ti,hwmods = "hdq1w";
1018 status = "disabled";
1019 };
1020
1021 dss: dss@4832a000 {
1022 compatible = "ti,omap3-dss";
1023 reg = <0x4832a000 0x200>;
1024 status = "disabled";
1025 ti,hwmods = "dss_core";
1026 clocks = <&disp_clk>;
1027 clock-names = "fck";
1028 #address-cells = <1>;
1029 #size-cells = <1>;
1030 ranges;
1031
1032 dispc: dispc@4832a400 {
1033 compatible = "ti,omap3-dispc";
1034 reg = <0x4832a400 0x400>;
1035 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1036 ti,hwmods = "dss_dispc";
1037 clocks = <&disp_clk>;
1038 clock-names = "fck";
1039 };
1040
1041 rfbi: rfbi@4832a800 {
1042 compatible = "ti,omap3-rfbi";
1043 reg = <0x4832a800 0x100>;
1044 ti,hwmods = "dss_rfbi";
1045 clocks = <&disp_clk>;
1046 clock-names = "fck";
1047 status = "disabled";
1048 };
1049 };
1050
1051 ocmcram: ocmcram@40300000 {
1052 compatible = "mmio-sram";
1053 reg = <0x40300000 0x40000>; /* 256k */
1054 };
1055
1056 dcan0: can@481cc000 {
1057 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
1058 ti,hwmods = "d_can0";
1059 clocks = <&dcan0_fck>;
1060 clock-names = "fck";
1061 reg = <0x481cc000 0x2000>;
1062 syscon-raminit = <&scm_conf 0x644 0>;
1063 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1064 status = "disabled";
1065 };
1066
1067 dcan1: can@481d0000 {
1068 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
1069 ti,hwmods = "d_can1";
1070 clocks = <&dcan1_fck>;
1071 clock-names = "fck";
1072 reg = <0x481d0000 0x2000>;
1073 syscon-raminit = <&scm_conf 0x644 1>;
1074 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1075 status = "disabled";
1076 };
1077
1078 vpfe0: vpfe@48326000 {
1079 compatible = "ti,am437x-vpfe";
1080 reg = <0x48326000 0x2000>;
1081 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1082 ti,hwmods = "vpfe0";
1083 status = "disabled";
1084 };
1085
1086 vpfe1: vpfe@48328000 {
1087 compatible = "ti,am437x-vpfe";
1088 reg = <0x48328000 0x2000>;
1089 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1090 ti,hwmods = "vpfe1";
1091 status = "disabled";
1092 };
1093 };
1094};
1095
1096/include/ "am43xx-clocks.dtsi"