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1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include "msm_drv.h"
19#include "msm_gpu.h"
20#include "msm_kms.h"
21
22static void msm_fb_output_poll_changed(struct drm_device *dev)
23{
24 struct msm_drm_private *priv = dev->dev_private;
25 if (priv->fbdev)
26 drm_fb_helper_hotplug_event(priv->fbdev);
27}
28
29static const struct drm_mode_config_funcs mode_config_funcs = {
30 .fb_create = msm_framebuffer_create,
31 .output_poll_changed = msm_fb_output_poll_changed,
32 .atomic_check = msm_atomic_check,
33 .atomic_commit = msm_atomic_commit,
34};
35
36int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu)
37{
38 struct msm_drm_private *priv = dev->dev_private;
39 int idx = priv->num_mmus++;
40
41 if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus)))
42 return -EINVAL;
43
44 priv->mmus[idx] = mmu;
45
46 return idx;
47}
48
49#ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
50static bool reglog = false;
51MODULE_PARM_DESC(reglog, "Enable register read/write logging");
52module_param(reglog, bool, 0600);
53#else
54#define reglog 0
55#endif
56
57#ifdef CONFIG_DRM_FBDEV_EMULATION
58static bool fbdev = true;
59MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
60module_param(fbdev, bool, 0600);
61#endif
62
63static char *vram = "16m";
64MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
65module_param(vram, charp, 0);
66
67/*
68 * Util/helpers:
69 */
70
71void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
72 const char *dbgname)
73{
74 struct resource *res;
75 unsigned long size;
76 void __iomem *ptr;
77
78 if (name)
79 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
80 else
81 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
82
83 if (!res) {
84 dev_err(&pdev->dev, "failed to get memory resource: %s\n", name);
85 return ERR_PTR(-EINVAL);
86 }
87
88 size = resource_size(res);
89
90 ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
91 if (!ptr) {
92 dev_err(&pdev->dev, "failed to ioremap: %s\n", name);
93 return ERR_PTR(-ENOMEM);
94 }
95
96 if (reglog)
97 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
98
99 return ptr;
100}
101
102void msm_writel(u32 data, void __iomem *addr)
103{
104 if (reglog)
105 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
106 writel(data, addr);
107}
108
109u32 msm_readl(const void __iomem *addr)
110{
111 u32 val = readl(addr);
112 if (reglog)
113 printk(KERN_ERR "IO:R %p %08x\n", addr, val);
114 return val;
115}
116
117struct vblank_event {
118 struct list_head node;
119 int crtc_id;
120 bool enable;
121};
122
123static void vblank_ctrl_worker(struct work_struct *work)
124{
125 struct msm_vblank_ctrl *vbl_ctrl = container_of(work,
126 struct msm_vblank_ctrl, work);
127 struct msm_drm_private *priv = container_of(vbl_ctrl,
128 struct msm_drm_private, vblank_ctrl);
129 struct msm_kms *kms = priv->kms;
130 struct vblank_event *vbl_ev, *tmp;
131 unsigned long flags;
132
133 spin_lock_irqsave(&vbl_ctrl->lock, flags);
134 list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
135 list_del(&vbl_ev->node);
136 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
137
138 if (vbl_ev->enable)
139 kms->funcs->enable_vblank(kms,
140 priv->crtcs[vbl_ev->crtc_id]);
141 else
142 kms->funcs->disable_vblank(kms,
143 priv->crtcs[vbl_ev->crtc_id]);
144
145 kfree(vbl_ev);
146
147 spin_lock_irqsave(&vbl_ctrl->lock, flags);
148 }
149
150 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
151}
152
153static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
154 int crtc_id, bool enable)
155{
156 struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
157 struct vblank_event *vbl_ev;
158 unsigned long flags;
159
160 vbl_ev = kzalloc(sizeof(*vbl_ev), GFP_ATOMIC);
161 if (!vbl_ev)
162 return -ENOMEM;
163
164 vbl_ev->crtc_id = crtc_id;
165 vbl_ev->enable = enable;
166
167 spin_lock_irqsave(&vbl_ctrl->lock, flags);
168 list_add_tail(&vbl_ev->node, &vbl_ctrl->event_list);
169 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
170
171 queue_work(priv->wq, &vbl_ctrl->work);
172
173 return 0;
174}
175
176/*
177 * DRM operations:
178 */
179
180static int msm_unload(struct drm_device *dev)
181{
182 struct msm_drm_private *priv = dev->dev_private;
183 struct msm_kms *kms = priv->kms;
184 struct msm_gpu *gpu = priv->gpu;
185 struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
186 struct vblank_event *vbl_ev, *tmp;
187
188 /* We must cancel and cleanup any pending vblank enable/disable
189 * work before drm_irq_uninstall() to avoid work re-enabling an
190 * irq after uninstall has disabled it.
191 */
192 cancel_work_sync(&vbl_ctrl->work);
193 list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
194 list_del(&vbl_ev->node);
195 kfree(vbl_ev);
196 }
197
198 drm_kms_helper_poll_fini(dev);
199
200#ifdef CONFIG_DRM_FBDEV_EMULATION
201 if (fbdev && priv->fbdev)
202 msm_fbdev_free(dev);
203#endif
204 drm_mode_config_cleanup(dev);
205 drm_vblank_cleanup(dev);
206
207 pm_runtime_get_sync(dev->dev);
208 drm_irq_uninstall(dev);
209 pm_runtime_put_sync(dev->dev);
210
211 flush_workqueue(priv->wq);
212 destroy_workqueue(priv->wq);
213
214 if (kms) {
215 pm_runtime_disable(dev->dev);
216 kms->funcs->destroy(kms);
217 }
218
219 if (gpu) {
220 mutex_lock(&dev->struct_mutex);
221 gpu->funcs->pm_suspend(gpu);
222 mutex_unlock(&dev->struct_mutex);
223 gpu->funcs->destroy(gpu);
224 }
225
226 if (priv->vram.paddr) {
227 DEFINE_DMA_ATTRS(attrs);
228 dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
229 drm_mm_takedown(&priv->vram.mm);
230 dma_free_attrs(dev->dev, priv->vram.size, NULL,
231 priv->vram.paddr, &attrs);
232 }
233
234 component_unbind_all(dev->dev, dev);
235
236 dev->dev_private = NULL;
237
238 kfree(priv);
239
240 return 0;
241}
242
243static int get_mdp_ver(struct platform_device *pdev)
244{
245 struct device *dev = &pdev->dev;
246
247 return (int) (unsigned long) of_device_get_match_data(dev);
248}
249
250#include <linux/of_address.h>
251
252static int msm_init_vram(struct drm_device *dev)
253{
254 struct msm_drm_private *priv = dev->dev_private;
255 struct device_node *node;
256 unsigned long size = 0;
257 int ret = 0;
258
259 /* In the device-tree world, we could have a 'memory-region'
260 * phandle, which gives us a link to our "vram". Allocating
261 * is all nicely abstracted behind the dma api, but we need
262 * to know the entire size to allocate it all in one go. There
263 * are two cases:
264 * 1) device with no IOMMU, in which case we need exclusive
265 * access to a VRAM carveout big enough for all gpu
266 * buffers
267 * 2) device with IOMMU, but where the bootloader puts up
268 * a splash screen. In this case, the VRAM carveout
269 * need only be large enough for fbdev fb. But we need
270 * exclusive access to the buffer to avoid the kernel
271 * using those pages for other purposes (which appears
272 * as corruption on screen before we have a chance to
273 * load and do initial modeset)
274 */
275
276 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
277 if (node) {
278 struct resource r;
279 ret = of_address_to_resource(node, 0, &r);
280 if (ret)
281 return ret;
282 size = r.end - r.start;
283 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
284
285 /* if we have no IOMMU, then we need to use carveout allocator.
286 * Grab the entire CMA chunk carved out in early startup in
287 * mach-msm:
288 */
289 } else if (!iommu_present(&platform_bus_type)) {
290 DRM_INFO("using %s VRAM carveout\n", vram);
291 size = memparse(vram, NULL);
292 }
293
294 if (size) {
295 DEFINE_DMA_ATTRS(attrs);
296 void *p;
297
298 priv->vram.size = size;
299
300 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
301
302 dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
303 dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
304
305 /* note that for no-kernel-mapping, the vaddr returned
306 * is bogus, but non-null if allocation succeeded:
307 */
308 p = dma_alloc_attrs(dev->dev, size,
309 &priv->vram.paddr, GFP_KERNEL, &attrs);
310 if (!p) {
311 dev_err(dev->dev, "failed to allocate VRAM\n");
312 priv->vram.paddr = 0;
313 return -ENOMEM;
314 }
315
316 dev_info(dev->dev, "VRAM: %08x->%08x\n",
317 (uint32_t)priv->vram.paddr,
318 (uint32_t)(priv->vram.paddr + size));
319 }
320
321 return ret;
322}
323
324static int msm_load(struct drm_device *dev, unsigned long flags)
325{
326 struct platform_device *pdev = dev->platformdev;
327 struct msm_drm_private *priv;
328 struct msm_kms *kms;
329 int ret;
330
331 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
332 if (!priv) {
333 dev_err(dev->dev, "failed to allocate private data\n");
334 return -ENOMEM;
335 }
336
337 dev->dev_private = priv;
338
339 priv->wq = alloc_ordered_workqueue("msm", 0);
340 init_waitqueue_head(&priv->fence_event);
341 init_waitqueue_head(&priv->pending_crtcs_event);
342
343 INIT_LIST_HEAD(&priv->inactive_list);
344 INIT_LIST_HEAD(&priv->fence_cbs);
345 INIT_LIST_HEAD(&priv->vblank_ctrl.event_list);
346 INIT_WORK(&priv->vblank_ctrl.work, vblank_ctrl_worker);
347 spin_lock_init(&priv->vblank_ctrl.lock);
348
349 drm_mode_config_init(dev);
350
351 platform_set_drvdata(pdev, dev);
352
353 /* Bind all our sub-components: */
354 ret = component_bind_all(dev->dev, dev);
355 if (ret)
356 return ret;
357
358 ret = msm_init_vram(dev);
359 if (ret)
360 goto fail;
361
362 switch (get_mdp_ver(pdev)) {
363 case 4:
364 kms = mdp4_kms_init(dev);
365 break;
366 case 5:
367 kms = mdp5_kms_init(dev);
368 break;
369 default:
370 kms = ERR_PTR(-ENODEV);
371 break;
372 }
373
374 if (IS_ERR(kms)) {
375 /*
376 * NOTE: once we have GPU support, having no kms should not
377 * be considered fatal.. ideally we would still support gpu
378 * and (for example) use dmabuf/prime to share buffers with
379 * imx drm driver on iMX5
380 */
381 dev_err(dev->dev, "failed to load kms\n");
382 ret = PTR_ERR(kms);
383 goto fail;
384 }
385
386 priv->kms = kms;
387
388 if (kms) {
389 pm_runtime_enable(dev->dev);
390 ret = kms->funcs->hw_init(kms);
391 if (ret) {
392 dev_err(dev->dev, "kms hw init failed: %d\n", ret);
393 goto fail;
394 }
395 }
396
397 dev->mode_config.funcs = &mode_config_funcs;
398
399 ret = drm_vblank_init(dev, priv->num_crtcs);
400 if (ret < 0) {
401 dev_err(dev->dev, "failed to initialize vblank\n");
402 goto fail;
403 }
404
405 pm_runtime_get_sync(dev->dev);
406 ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0));
407 pm_runtime_put_sync(dev->dev);
408 if (ret < 0) {
409 dev_err(dev->dev, "failed to install IRQ handler\n");
410 goto fail;
411 }
412
413 drm_mode_config_reset(dev);
414
415#ifdef CONFIG_DRM_FBDEV_EMULATION
416 if (fbdev)
417 priv->fbdev = msm_fbdev_init(dev);
418#endif
419
420 ret = msm_debugfs_late_init(dev);
421 if (ret)
422 goto fail;
423
424 drm_kms_helper_poll_init(dev);
425
426 return 0;
427
428fail:
429 msm_unload(dev);
430 return ret;
431}
432
433static void load_gpu(struct drm_device *dev)
434{
435 static DEFINE_MUTEX(init_lock);
436 struct msm_drm_private *priv = dev->dev_private;
437
438 mutex_lock(&init_lock);
439
440 if (!priv->gpu)
441 priv->gpu = adreno_load_gpu(dev);
442
443 mutex_unlock(&init_lock);
444}
445
446static int msm_open(struct drm_device *dev, struct drm_file *file)
447{
448 struct msm_file_private *ctx;
449
450 /* For now, load gpu on open.. to avoid the requirement of having
451 * firmware in the initrd.
452 */
453 load_gpu(dev);
454
455 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
456 if (!ctx)
457 return -ENOMEM;
458
459 file->driver_priv = ctx;
460
461 return 0;
462}
463
464static void msm_preclose(struct drm_device *dev, struct drm_file *file)
465{
466 struct msm_drm_private *priv = dev->dev_private;
467 struct msm_file_private *ctx = file->driver_priv;
468 struct msm_kms *kms = priv->kms;
469
470 mutex_lock(&dev->struct_mutex);
471 if (ctx == priv->lastctx)
472 priv->lastctx = NULL;
473 mutex_unlock(&dev->struct_mutex);
474
475 kfree(ctx);
476}
477
478static void msm_lastclose(struct drm_device *dev)
479{
480 struct msm_drm_private *priv = dev->dev_private;
481 if (priv->fbdev)
482 drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
483}
484
485static irqreturn_t msm_irq(int irq, void *arg)
486{
487 struct drm_device *dev = arg;
488 struct msm_drm_private *priv = dev->dev_private;
489 struct msm_kms *kms = priv->kms;
490 BUG_ON(!kms);
491 return kms->funcs->irq(kms);
492}
493
494static void msm_irq_preinstall(struct drm_device *dev)
495{
496 struct msm_drm_private *priv = dev->dev_private;
497 struct msm_kms *kms = priv->kms;
498 BUG_ON(!kms);
499 kms->funcs->irq_preinstall(kms);
500}
501
502static int msm_irq_postinstall(struct drm_device *dev)
503{
504 struct msm_drm_private *priv = dev->dev_private;
505 struct msm_kms *kms = priv->kms;
506 BUG_ON(!kms);
507 return kms->funcs->irq_postinstall(kms);
508}
509
510static void msm_irq_uninstall(struct drm_device *dev)
511{
512 struct msm_drm_private *priv = dev->dev_private;
513 struct msm_kms *kms = priv->kms;
514 BUG_ON(!kms);
515 kms->funcs->irq_uninstall(kms);
516}
517
518static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe)
519{
520 struct msm_drm_private *priv = dev->dev_private;
521 struct msm_kms *kms = priv->kms;
522 if (!kms)
523 return -ENXIO;
524 DBG("dev=%p, crtc=%u", dev, pipe);
525 return vblank_ctrl_queue_work(priv, pipe, true);
526}
527
528static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe)
529{
530 struct msm_drm_private *priv = dev->dev_private;
531 struct msm_kms *kms = priv->kms;
532 if (!kms)
533 return;
534 DBG("dev=%p, crtc=%u", dev, pipe);
535 vblank_ctrl_queue_work(priv, pipe, false);
536}
537
538/*
539 * DRM debugfs:
540 */
541
542#ifdef CONFIG_DEBUG_FS
543static int msm_gpu_show(struct drm_device *dev, struct seq_file *m)
544{
545 struct msm_drm_private *priv = dev->dev_private;
546 struct msm_gpu *gpu = priv->gpu;
547
548 if (gpu) {
549 seq_printf(m, "%s Status:\n", gpu->name);
550 gpu->funcs->show(gpu, m);
551 }
552
553 return 0;
554}
555
556static int msm_gem_show(struct drm_device *dev, struct seq_file *m)
557{
558 struct msm_drm_private *priv = dev->dev_private;
559 struct msm_gpu *gpu = priv->gpu;
560
561 if (gpu) {
562 seq_printf(m, "Active Objects (%s):\n", gpu->name);
563 msm_gem_describe_objects(&gpu->active_list, m);
564 }
565
566 seq_printf(m, "Inactive Objects:\n");
567 msm_gem_describe_objects(&priv->inactive_list, m);
568
569 return 0;
570}
571
572static int msm_mm_show(struct drm_device *dev, struct seq_file *m)
573{
574 return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm);
575}
576
577static int msm_fb_show(struct drm_device *dev, struct seq_file *m)
578{
579 struct msm_drm_private *priv = dev->dev_private;
580 struct drm_framebuffer *fb, *fbdev_fb = NULL;
581
582 if (priv->fbdev) {
583 seq_printf(m, "fbcon ");
584 fbdev_fb = priv->fbdev->fb;
585 msm_framebuffer_describe(fbdev_fb, m);
586 }
587
588 mutex_lock(&dev->mode_config.fb_lock);
589 list_for_each_entry(fb, &dev->mode_config.fb_list, head) {
590 if (fb == fbdev_fb)
591 continue;
592
593 seq_printf(m, "user ");
594 msm_framebuffer_describe(fb, m);
595 }
596 mutex_unlock(&dev->mode_config.fb_lock);
597
598 return 0;
599}
600
601static int show_locked(struct seq_file *m, void *arg)
602{
603 struct drm_info_node *node = (struct drm_info_node *) m->private;
604 struct drm_device *dev = node->minor->dev;
605 int (*show)(struct drm_device *dev, struct seq_file *m) =
606 node->info_ent->data;
607 int ret;
608
609 ret = mutex_lock_interruptible(&dev->struct_mutex);
610 if (ret)
611 return ret;
612
613 ret = show(dev, m);
614
615 mutex_unlock(&dev->struct_mutex);
616
617 return ret;
618}
619
620static struct drm_info_list msm_debugfs_list[] = {
621 {"gpu", show_locked, 0, msm_gpu_show},
622 {"gem", show_locked, 0, msm_gem_show},
623 { "mm", show_locked, 0, msm_mm_show },
624 { "fb", show_locked, 0, msm_fb_show },
625};
626
627static int late_init_minor(struct drm_minor *minor)
628{
629 int ret;
630
631 if (!minor)
632 return 0;
633
634 ret = msm_rd_debugfs_init(minor);
635 if (ret) {
636 dev_err(minor->dev->dev, "could not install rd debugfs\n");
637 return ret;
638 }
639
640 ret = msm_perf_debugfs_init(minor);
641 if (ret) {
642 dev_err(minor->dev->dev, "could not install perf debugfs\n");
643 return ret;
644 }
645
646 return 0;
647}
648
649int msm_debugfs_late_init(struct drm_device *dev)
650{
651 int ret;
652 ret = late_init_minor(dev->primary);
653 if (ret)
654 return ret;
655 ret = late_init_minor(dev->render);
656 if (ret)
657 return ret;
658 ret = late_init_minor(dev->control);
659 return ret;
660}
661
662static int msm_debugfs_init(struct drm_minor *minor)
663{
664 struct drm_device *dev = minor->dev;
665 int ret;
666
667 ret = drm_debugfs_create_files(msm_debugfs_list,
668 ARRAY_SIZE(msm_debugfs_list),
669 minor->debugfs_root, minor);
670
671 if (ret) {
672 dev_err(dev->dev, "could not install msm_debugfs_list\n");
673 return ret;
674 }
675
676 return 0;
677}
678
679static void msm_debugfs_cleanup(struct drm_minor *minor)
680{
681 drm_debugfs_remove_files(msm_debugfs_list,
682 ARRAY_SIZE(msm_debugfs_list), minor);
683 if (!minor->dev->dev_private)
684 return;
685 msm_rd_debugfs_cleanup(minor);
686 msm_perf_debugfs_cleanup(minor);
687}
688#endif
689
690/*
691 * Fences:
692 */
693
694int msm_wait_fence(struct drm_device *dev, uint32_t fence,
695 ktime_t *timeout , bool interruptible)
696{
697 struct msm_drm_private *priv = dev->dev_private;
698 int ret;
699
700 if (!priv->gpu)
701 return 0;
702
703 if (fence > priv->gpu->submitted_fence) {
704 DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
705 fence, priv->gpu->submitted_fence);
706 return -EINVAL;
707 }
708
709 if (!timeout) {
710 /* no-wait: */
711 ret = fence_completed(dev, fence) ? 0 : -EBUSY;
712 } else {
713 ktime_t now = ktime_get();
714 unsigned long remaining_jiffies;
715
716 if (ktime_compare(*timeout, now) < 0) {
717 remaining_jiffies = 0;
718 } else {
719 ktime_t rem = ktime_sub(*timeout, now);
720 struct timespec ts = ktime_to_timespec(rem);
721 remaining_jiffies = timespec_to_jiffies(&ts);
722 }
723
724 if (interruptible)
725 ret = wait_event_interruptible_timeout(priv->fence_event,
726 fence_completed(dev, fence),
727 remaining_jiffies);
728 else
729 ret = wait_event_timeout(priv->fence_event,
730 fence_completed(dev, fence),
731 remaining_jiffies);
732
733 if (ret == 0) {
734 DBG("timeout waiting for fence: %u (completed: %u)",
735 fence, priv->completed_fence);
736 ret = -ETIMEDOUT;
737 } else if (ret != -ERESTARTSYS) {
738 ret = 0;
739 }
740 }
741
742 return ret;
743}
744
745int msm_queue_fence_cb(struct drm_device *dev,
746 struct msm_fence_cb *cb, uint32_t fence)
747{
748 struct msm_drm_private *priv = dev->dev_private;
749 int ret = 0;
750
751 mutex_lock(&dev->struct_mutex);
752 if (!list_empty(&cb->work.entry)) {
753 ret = -EINVAL;
754 } else if (fence > priv->completed_fence) {
755 cb->fence = fence;
756 list_add_tail(&cb->work.entry, &priv->fence_cbs);
757 } else {
758 queue_work(priv->wq, &cb->work);
759 }
760 mutex_unlock(&dev->struct_mutex);
761
762 return ret;
763}
764
765/* called from workqueue */
766void msm_update_fence(struct drm_device *dev, uint32_t fence)
767{
768 struct msm_drm_private *priv = dev->dev_private;
769
770 mutex_lock(&dev->struct_mutex);
771 priv->completed_fence = max(fence, priv->completed_fence);
772
773 while (!list_empty(&priv->fence_cbs)) {
774 struct msm_fence_cb *cb;
775
776 cb = list_first_entry(&priv->fence_cbs,
777 struct msm_fence_cb, work.entry);
778
779 if (cb->fence > priv->completed_fence)
780 break;
781
782 list_del_init(&cb->work.entry);
783 queue_work(priv->wq, &cb->work);
784 }
785
786 mutex_unlock(&dev->struct_mutex);
787
788 wake_up_all(&priv->fence_event);
789}
790
791void __msm_fence_worker(struct work_struct *work)
792{
793 struct msm_fence_cb *cb = container_of(work, struct msm_fence_cb, work);
794 cb->func(cb);
795}
796
797/*
798 * DRM ioctls:
799 */
800
801static int msm_ioctl_get_param(struct drm_device *dev, void *data,
802 struct drm_file *file)
803{
804 struct msm_drm_private *priv = dev->dev_private;
805 struct drm_msm_param *args = data;
806 struct msm_gpu *gpu;
807
808 /* for now, we just have 3d pipe.. eventually this would need to
809 * be more clever to dispatch to appropriate gpu module:
810 */
811 if (args->pipe != MSM_PIPE_3D0)
812 return -EINVAL;
813
814 gpu = priv->gpu;
815
816 if (!gpu)
817 return -ENXIO;
818
819 return gpu->funcs->get_param(gpu, args->param, &args->value);
820}
821
822static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
823 struct drm_file *file)
824{
825 struct drm_msm_gem_new *args = data;
826
827 if (args->flags & ~MSM_BO_FLAGS) {
828 DRM_ERROR("invalid flags: %08x\n", args->flags);
829 return -EINVAL;
830 }
831
832 return msm_gem_new_handle(dev, file, args->size,
833 args->flags, &args->handle);
834}
835
836static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
837{
838 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
839}
840
841static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
842 struct drm_file *file)
843{
844 struct drm_msm_gem_cpu_prep *args = data;
845 struct drm_gem_object *obj;
846 ktime_t timeout = to_ktime(args->timeout);
847 int ret;
848
849 if (args->op & ~MSM_PREP_FLAGS) {
850 DRM_ERROR("invalid op: %08x\n", args->op);
851 return -EINVAL;
852 }
853
854 obj = drm_gem_object_lookup(dev, file, args->handle);
855 if (!obj)
856 return -ENOENT;
857
858 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
859
860 drm_gem_object_unreference_unlocked(obj);
861
862 return ret;
863}
864
865static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
866 struct drm_file *file)
867{
868 struct drm_msm_gem_cpu_fini *args = data;
869 struct drm_gem_object *obj;
870 int ret;
871
872 obj = drm_gem_object_lookup(dev, file, args->handle);
873 if (!obj)
874 return -ENOENT;
875
876 ret = msm_gem_cpu_fini(obj);
877
878 drm_gem_object_unreference_unlocked(obj);
879
880 return ret;
881}
882
883static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
884 struct drm_file *file)
885{
886 struct drm_msm_gem_info *args = data;
887 struct drm_gem_object *obj;
888 int ret = 0;
889
890 if (args->pad)
891 return -EINVAL;
892
893 obj = drm_gem_object_lookup(dev, file, args->handle);
894 if (!obj)
895 return -ENOENT;
896
897 args->offset = msm_gem_mmap_offset(obj);
898
899 drm_gem_object_unreference_unlocked(obj);
900
901 return ret;
902}
903
904static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
905 struct drm_file *file)
906{
907 struct drm_msm_wait_fence *args = data;
908 ktime_t timeout = to_ktime(args->timeout);
909
910 if (args->pad) {
911 DRM_ERROR("invalid pad: %08x\n", args->pad);
912 return -EINVAL;
913 }
914
915 return msm_wait_fence(dev, args->fence, &timeout, true);
916}
917
918static const struct drm_ioctl_desc msm_ioctls[] = {
919 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW),
920 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW),
921 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW),
922 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
923 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
924 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW),
925 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW),
926};
927
928static const struct vm_operations_struct vm_ops = {
929 .fault = msm_gem_fault,
930 .open = drm_gem_vm_open,
931 .close = drm_gem_vm_close,
932};
933
934static const struct file_operations fops = {
935 .owner = THIS_MODULE,
936 .open = drm_open,
937 .release = drm_release,
938 .unlocked_ioctl = drm_ioctl,
939#ifdef CONFIG_COMPAT
940 .compat_ioctl = drm_compat_ioctl,
941#endif
942 .poll = drm_poll,
943 .read = drm_read,
944 .llseek = no_llseek,
945 .mmap = msm_gem_mmap,
946};
947
948static struct drm_driver msm_driver = {
949 .driver_features = DRIVER_HAVE_IRQ |
950 DRIVER_GEM |
951 DRIVER_PRIME |
952 DRIVER_RENDER |
953 DRIVER_ATOMIC |
954 DRIVER_MODESET,
955 .load = msm_load,
956 .unload = msm_unload,
957 .open = msm_open,
958 .preclose = msm_preclose,
959 .lastclose = msm_lastclose,
960 .set_busid = drm_platform_set_busid,
961 .irq_handler = msm_irq,
962 .irq_preinstall = msm_irq_preinstall,
963 .irq_postinstall = msm_irq_postinstall,
964 .irq_uninstall = msm_irq_uninstall,
965 .get_vblank_counter = drm_vblank_no_hw_counter,
966 .enable_vblank = msm_enable_vblank,
967 .disable_vblank = msm_disable_vblank,
968 .gem_free_object = msm_gem_free_object,
969 .gem_vm_ops = &vm_ops,
970 .dumb_create = msm_gem_dumb_create,
971 .dumb_map_offset = msm_gem_dumb_map_offset,
972 .dumb_destroy = drm_gem_dumb_destroy,
973 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
974 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
975 .gem_prime_export = drm_gem_prime_export,
976 .gem_prime_import = drm_gem_prime_import,
977 .gem_prime_pin = msm_gem_prime_pin,
978 .gem_prime_unpin = msm_gem_prime_unpin,
979 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
980 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
981 .gem_prime_vmap = msm_gem_prime_vmap,
982 .gem_prime_vunmap = msm_gem_prime_vunmap,
983 .gem_prime_mmap = msm_gem_prime_mmap,
984#ifdef CONFIG_DEBUG_FS
985 .debugfs_init = msm_debugfs_init,
986 .debugfs_cleanup = msm_debugfs_cleanup,
987#endif
988 .ioctls = msm_ioctls,
989 .num_ioctls = DRM_MSM_NUM_IOCTLS,
990 .fops = &fops,
991 .name = "msm",
992 .desc = "MSM Snapdragon DRM",
993 .date = "20130625",
994 .major = 1,
995 .minor = 0,
996};
997
998#ifdef CONFIG_PM_SLEEP
999static int msm_pm_suspend(struct device *dev)
1000{
1001 struct drm_device *ddev = dev_get_drvdata(dev);
1002
1003 drm_kms_helper_poll_disable(ddev);
1004
1005 return 0;
1006}
1007
1008static int msm_pm_resume(struct device *dev)
1009{
1010 struct drm_device *ddev = dev_get_drvdata(dev);
1011
1012 drm_kms_helper_poll_enable(ddev);
1013
1014 return 0;
1015}
1016#endif
1017
1018static const struct dev_pm_ops msm_pm_ops = {
1019 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1020};
1021
1022/*
1023 * Componentized driver support:
1024 */
1025
1026/*
1027 * NOTE: duplication of the same code as exynos or imx (or probably any other).
1028 * so probably some room for some helpers
1029 */
1030static int compare_of(struct device *dev, void *data)
1031{
1032 return dev->of_node == data;
1033}
1034
1035static int add_components(struct device *dev, struct component_match **matchptr,
1036 const char *name)
1037{
1038 struct device_node *np = dev->of_node;
1039 unsigned i;
1040
1041 for (i = 0; ; i++) {
1042 struct device_node *node;
1043
1044 node = of_parse_phandle(np, name, i);
1045 if (!node)
1046 break;
1047
1048 component_match_add(dev, matchptr, compare_of, node);
1049 }
1050
1051 return 0;
1052}
1053
1054static int msm_drm_bind(struct device *dev)
1055{
1056 return drm_platform_init(&msm_driver, to_platform_device(dev));
1057}
1058
1059static void msm_drm_unbind(struct device *dev)
1060{
1061 drm_put_dev(platform_get_drvdata(to_platform_device(dev)));
1062}
1063
1064static const struct component_master_ops msm_drm_ops = {
1065 .bind = msm_drm_bind,
1066 .unbind = msm_drm_unbind,
1067};
1068
1069/*
1070 * Platform driver:
1071 */
1072
1073static int msm_pdev_probe(struct platform_device *pdev)
1074{
1075 struct component_match *match = NULL;
1076
1077 add_components(&pdev->dev, &match, "connectors");
1078 add_components(&pdev->dev, &match, "gpus");
1079
1080 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
1081 return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1082}
1083
1084static int msm_pdev_remove(struct platform_device *pdev)
1085{
1086 component_master_del(&pdev->dev, &msm_drm_ops);
1087
1088 return 0;
1089}
1090
1091static const struct platform_device_id msm_id[] = {
1092 { "mdp", 0 },
1093 { }
1094};
1095
1096static const struct of_device_id dt_match[] = {
1097 { .compatible = "qcom,mdp4", .data = (void *) 4 }, /* mdp4 */
1098 { .compatible = "qcom,mdp5", .data = (void *) 5 }, /* mdp5 */
1099 /* to support downstream DT files */
1100 { .compatible = "qcom,mdss_mdp", .data = (void *) 5 }, /* mdp5 */
1101 {}
1102};
1103MODULE_DEVICE_TABLE(of, dt_match);
1104
1105static struct platform_driver msm_platform_driver = {
1106 .probe = msm_pdev_probe,
1107 .remove = msm_pdev_remove,
1108 .driver = {
1109 .name = "msm",
1110 .of_match_table = dt_match,
1111 .pm = &msm_pm_ops,
1112 },
1113 .id_table = msm_id,
1114};
1115
1116static int __init msm_drm_register(void)
1117{
1118 DBG("init");
1119 msm_dsi_register();
1120 msm_edp_register();
1121 msm_hdmi_register();
1122 adreno_register();
1123 return platform_driver_register(&msm_platform_driver);
1124}
1125
1126static void __exit msm_drm_unregister(void)
1127{
1128 DBG("fini");
1129 platform_driver_unregister(&msm_platform_driver);
1130 msm_hdmi_unregister();
1131 adreno_unregister();
1132 msm_edp_unregister();
1133 msm_dsi_unregister();
1134}
1135
1136module_init(msm_drm_register);
1137module_exit(msm_drm_unregister);
1138
1139MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1140MODULE_DESCRIPTION("MSM DRM Driver");
1141MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8#include <linux/dma-mapping.h>
9#include <linux/fault-inject.h>
10#include <linux/kthread.h>
11#include <linux/sched/mm.h>
12#include <linux/uaccess.h>
13#include <uapi/linux/sched/types.h>
14
15#include <drm/drm_bridge.h>
16#include <drm/drm_drv.h>
17#include <drm/drm_file.h>
18#include <drm/drm_ioctl.h>
19#include <drm/drm_prime.h>
20#include <drm/drm_of.h>
21#include <drm/drm_vblank.h>
22
23#include "disp/msm_disp_snapshot.h"
24#include "msm_drv.h"
25#include "msm_debugfs.h"
26#include "msm_fence.h"
27#include "msm_gem.h"
28#include "msm_gpu.h"
29#include "msm_kms.h"
30#include "msm_mmu.h"
31#include "adreno/adreno_gpu.h"
32
33/*
34 * MSM driver version:
35 * - 1.0.0 - initial interface
36 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
37 * - 1.2.0 - adds explicit fence support for submit ioctl
38 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
39 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
40 * MSM_GEM_INFO ioctl.
41 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
42 * GEM object's debug name
43 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
44 * - 1.6.0 - Syncobj support
45 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
46 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
47 * - 1.9.0 - Add MSM_SUBMIT_FENCE_SN_IN
48 */
49#define MSM_VERSION_MAJOR 1
50#define MSM_VERSION_MINOR 9
51#define MSM_VERSION_PATCHLEVEL 0
52
53static const struct drm_mode_config_funcs mode_config_funcs = {
54 .fb_create = msm_framebuffer_create,
55 .output_poll_changed = drm_fb_helper_output_poll_changed,
56 .atomic_check = drm_atomic_helper_check,
57 .atomic_commit = drm_atomic_helper_commit,
58};
59
60static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
61 .atomic_commit_tail = msm_atomic_commit_tail,
62};
63
64#ifdef CONFIG_DRM_FBDEV_EMULATION
65static bool fbdev = true;
66MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
67module_param(fbdev, bool, 0600);
68#endif
69
70static char *vram = "16m";
71MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
72module_param(vram, charp, 0);
73
74bool dumpstate;
75MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
76module_param(dumpstate, bool, 0600);
77
78static bool modeset = true;
79MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
80module_param(modeset, bool, 0600);
81
82#ifdef CONFIG_FAULT_INJECTION
83DECLARE_FAULT_ATTR(fail_gem_alloc);
84DECLARE_FAULT_ATTR(fail_gem_iova);
85#endif
86
87static irqreturn_t msm_irq(int irq, void *arg)
88{
89 struct drm_device *dev = arg;
90 struct msm_drm_private *priv = dev->dev_private;
91 struct msm_kms *kms = priv->kms;
92
93 BUG_ON(!kms);
94
95 return kms->funcs->irq(kms);
96}
97
98static void msm_irq_preinstall(struct drm_device *dev)
99{
100 struct msm_drm_private *priv = dev->dev_private;
101 struct msm_kms *kms = priv->kms;
102
103 BUG_ON(!kms);
104
105 kms->funcs->irq_preinstall(kms);
106}
107
108static int msm_irq_postinstall(struct drm_device *dev)
109{
110 struct msm_drm_private *priv = dev->dev_private;
111 struct msm_kms *kms = priv->kms;
112
113 BUG_ON(!kms);
114
115 if (kms->funcs->irq_postinstall)
116 return kms->funcs->irq_postinstall(kms);
117
118 return 0;
119}
120
121static int msm_irq_install(struct drm_device *dev, unsigned int irq)
122{
123 struct msm_drm_private *priv = dev->dev_private;
124 struct msm_kms *kms = priv->kms;
125 int ret;
126
127 if (irq == IRQ_NOTCONNECTED)
128 return -ENOTCONN;
129
130 msm_irq_preinstall(dev);
131
132 ret = request_irq(irq, msm_irq, 0, dev->driver->name, dev);
133 if (ret)
134 return ret;
135
136 kms->irq_requested = true;
137
138 ret = msm_irq_postinstall(dev);
139 if (ret) {
140 free_irq(irq, dev);
141 return ret;
142 }
143
144 return 0;
145}
146
147static void msm_irq_uninstall(struct drm_device *dev)
148{
149 struct msm_drm_private *priv = dev->dev_private;
150 struct msm_kms *kms = priv->kms;
151
152 kms->funcs->irq_uninstall(kms);
153 if (kms->irq_requested)
154 free_irq(kms->irq, dev);
155}
156
157struct msm_vblank_work {
158 struct work_struct work;
159 int crtc_id;
160 bool enable;
161 struct msm_drm_private *priv;
162};
163
164static void vblank_ctrl_worker(struct work_struct *work)
165{
166 struct msm_vblank_work *vbl_work = container_of(work,
167 struct msm_vblank_work, work);
168 struct msm_drm_private *priv = vbl_work->priv;
169 struct msm_kms *kms = priv->kms;
170
171 if (vbl_work->enable)
172 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
173 else
174 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
175
176 kfree(vbl_work);
177}
178
179static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
180 int crtc_id, bool enable)
181{
182 struct msm_vblank_work *vbl_work;
183
184 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
185 if (!vbl_work)
186 return -ENOMEM;
187
188 INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
189
190 vbl_work->crtc_id = crtc_id;
191 vbl_work->enable = enable;
192 vbl_work->priv = priv;
193
194 queue_work(priv->wq, &vbl_work->work);
195
196 return 0;
197}
198
199static int msm_drm_uninit(struct device *dev)
200{
201 struct platform_device *pdev = to_platform_device(dev);
202 struct msm_drm_private *priv = platform_get_drvdata(pdev);
203 struct drm_device *ddev = priv->dev;
204 struct msm_kms *kms = priv->kms;
205 int i;
206
207 /*
208 * Shutdown the hw if we're far enough along where things might be on.
209 * If we run this too early, we'll end up panicking in any variety of
210 * places. Since we don't register the drm device until late in
211 * msm_drm_init, drm_dev->registered is used as an indicator that the
212 * shutdown will be successful.
213 */
214 if (ddev->registered) {
215 drm_dev_unregister(ddev);
216 drm_atomic_helper_shutdown(ddev);
217 }
218
219 /* We must cancel and cleanup any pending vblank enable/disable
220 * work before msm_irq_uninstall() to avoid work re-enabling an
221 * irq after uninstall has disabled it.
222 */
223
224 flush_workqueue(priv->wq);
225
226 /* clean up event worker threads */
227 for (i = 0; i < priv->num_crtcs; i++) {
228 if (priv->event_thread[i].worker)
229 kthread_destroy_worker(priv->event_thread[i].worker);
230 }
231
232 msm_gem_shrinker_cleanup(ddev);
233
234 drm_kms_helper_poll_fini(ddev);
235
236 msm_perf_debugfs_cleanup(priv);
237 msm_rd_debugfs_cleanup(priv);
238
239#ifdef CONFIG_DRM_FBDEV_EMULATION
240 if (fbdev && priv->fbdev)
241 msm_fbdev_free(ddev);
242#endif
243
244 msm_disp_snapshot_destroy(ddev);
245
246 drm_mode_config_cleanup(ddev);
247
248 for (i = 0; i < priv->num_bridges; i++)
249 drm_bridge_remove(priv->bridges[i]);
250 priv->num_bridges = 0;
251
252 pm_runtime_get_sync(dev);
253 msm_irq_uninstall(ddev);
254 pm_runtime_put_sync(dev);
255
256 if (kms && kms->funcs)
257 kms->funcs->destroy(kms);
258
259 if (priv->vram.paddr) {
260 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
261 drm_mm_takedown(&priv->vram.mm);
262 dma_free_attrs(dev, priv->vram.size, NULL,
263 priv->vram.paddr, attrs);
264 }
265
266 component_unbind_all(dev, ddev);
267
268 ddev->dev_private = NULL;
269 drm_dev_put(ddev);
270
271 destroy_workqueue(priv->wq);
272
273 return 0;
274}
275
276#include <linux/of_address.h>
277
278struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev)
279{
280 struct msm_gem_address_space *aspace;
281 struct msm_mmu *mmu;
282 struct device *mdp_dev = dev->dev;
283 struct device *mdss_dev = mdp_dev->parent;
284 struct device *iommu_dev;
285
286 /*
287 * IOMMUs can be a part of MDSS device tree binding, or the
288 * MDP/DPU device.
289 */
290 if (device_iommu_mapped(mdp_dev))
291 iommu_dev = mdp_dev;
292 else
293 iommu_dev = mdss_dev;
294
295 mmu = msm_iommu_new(iommu_dev, 0);
296 if (IS_ERR(mmu))
297 return ERR_CAST(mmu);
298
299 if (!mmu) {
300 drm_info(dev, "no IOMMU, fallback to phys contig buffers for scanout\n");
301 return NULL;
302 }
303
304 aspace = msm_gem_address_space_create(mmu, "mdp_kms",
305 0x1000, 0x100000000 - 0x1000);
306 if (IS_ERR(aspace)) {
307 dev_err(mdp_dev, "aspace create, error %pe\n", aspace);
308 mmu->funcs->destroy(mmu);
309 }
310
311 return aspace;
312}
313
314bool msm_use_mmu(struct drm_device *dev)
315{
316 struct msm_drm_private *priv = dev->dev_private;
317
318 /*
319 * a2xx comes with its own MMU
320 * On other platforms IOMMU can be declared specified either for the
321 * MDP/DPU device or for its parent, MDSS device.
322 */
323 return priv->is_a2xx ||
324 device_iommu_mapped(dev->dev) ||
325 device_iommu_mapped(dev->dev->parent);
326}
327
328static int msm_init_vram(struct drm_device *dev)
329{
330 struct msm_drm_private *priv = dev->dev_private;
331 struct device_node *node;
332 unsigned long size = 0;
333 int ret = 0;
334
335 /* In the device-tree world, we could have a 'memory-region'
336 * phandle, which gives us a link to our "vram". Allocating
337 * is all nicely abstracted behind the dma api, but we need
338 * to know the entire size to allocate it all in one go. There
339 * are two cases:
340 * 1) device with no IOMMU, in which case we need exclusive
341 * access to a VRAM carveout big enough for all gpu
342 * buffers
343 * 2) device with IOMMU, but where the bootloader puts up
344 * a splash screen. In this case, the VRAM carveout
345 * need only be large enough for fbdev fb. But we need
346 * exclusive access to the buffer to avoid the kernel
347 * using those pages for other purposes (which appears
348 * as corruption on screen before we have a chance to
349 * load and do initial modeset)
350 */
351
352 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
353 if (node) {
354 struct resource r;
355 ret = of_address_to_resource(node, 0, &r);
356 of_node_put(node);
357 if (ret)
358 return ret;
359 size = r.end - r.start + 1;
360 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
361
362 /* if we have no IOMMU, then we need to use carveout allocator.
363 * Grab the entire DMA chunk carved out in early startup in
364 * mach-msm:
365 */
366 } else if (!msm_use_mmu(dev)) {
367 DRM_INFO("using %s VRAM carveout\n", vram);
368 size = memparse(vram, NULL);
369 }
370
371 if (size) {
372 unsigned long attrs = 0;
373 void *p;
374
375 priv->vram.size = size;
376
377 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
378 spin_lock_init(&priv->vram.lock);
379
380 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
381 attrs |= DMA_ATTR_WRITE_COMBINE;
382
383 /* note that for no-kernel-mapping, the vaddr returned
384 * is bogus, but non-null if allocation succeeded:
385 */
386 p = dma_alloc_attrs(dev->dev, size,
387 &priv->vram.paddr, GFP_KERNEL, attrs);
388 if (!p) {
389 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
390 priv->vram.paddr = 0;
391 return -ENOMEM;
392 }
393
394 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
395 (uint32_t)priv->vram.paddr,
396 (uint32_t)(priv->vram.paddr + size));
397 }
398
399 return ret;
400}
401
402static int msm_drm_init(struct device *dev, const struct drm_driver *drv)
403{
404 struct msm_drm_private *priv = dev_get_drvdata(dev);
405 struct drm_device *ddev;
406 struct msm_kms *kms;
407 int ret, i;
408
409 if (drm_firmware_drivers_only())
410 return -ENODEV;
411
412 ddev = drm_dev_alloc(drv, dev);
413 if (IS_ERR(ddev)) {
414 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
415 return PTR_ERR(ddev);
416 }
417 ddev->dev_private = priv;
418 priv->dev = ddev;
419
420 priv->wq = alloc_ordered_workqueue("msm", 0);
421
422 INIT_LIST_HEAD(&priv->objects);
423 mutex_init(&priv->obj_lock);
424
425 /*
426 * Initialize the LRUs:
427 */
428 mutex_init(&priv->lru.lock);
429 drm_gem_lru_init(&priv->lru.unbacked, &priv->lru.lock);
430 drm_gem_lru_init(&priv->lru.pinned, &priv->lru.lock);
431 drm_gem_lru_init(&priv->lru.willneed, &priv->lru.lock);
432 drm_gem_lru_init(&priv->lru.dontneed, &priv->lru.lock);
433
434 /* Teach lockdep about lock ordering wrt. shrinker: */
435 fs_reclaim_acquire(GFP_KERNEL);
436 might_lock(&priv->lru.lock);
437 fs_reclaim_release(GFP_KERNEL);
438
439 drm_mode_config_init(ddev);
440
441 ret = msm_init_vram(ddev);
442 if (ret)
443 return ret;
444
445 /* Bind all our sub-components: */
446 ret = component_bind_all(dev, ddev);
447 if (ret)
448 return ret;
449
450 dma_set_max_seg_size(dev, UINT_MAX);
451
452 msm_gem_shrinker_init(ddev);
453
454 if (priv->kms_init) {
455 ret = priv->kms_init(ddev);
456 if (ret) {
457 DRM_DEV_ERROR(dev, "failed to load kms\n");
458 priv->kms = NULL;
459 goto err_msm_uninit;
460 }
461 kms = priv->kms;
462 } else {
463 /* valid only for the dummy headless case, where of_node=NULL */
464 WARN_ON(dev->of_node);
465 kms = NULL;
466 }
467
468 /* Enable normalization of plane zpos */
469 ddev->mode_config.normalize_zpos = true;
470
471 if (kms) {
472 kms->dev = ddev;
473 ret = kms->funcs->hw_init(kms);
474 if (ret) {
475 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
476 goto err_msm_uninit;
477 }
478 }
479
480 drm_helper_move_panel_connectors_to_head(ddev);
481
482 ddev->mode_config.funcs = &mode_config_funcs;
483 ddev->mode_config.helper_private = &mode_config_helper_funcs;
484
485 for (i = 0; i < priv->num_crtcs; i++) {
486 /* initialize event thread */
487 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
488 priv->event_thread[i].dev = ddev;
489 priv->event_thread[i].worker = kthread_create_worker(0,
490 "crtc_event:%d", priv->event_thread[i].crtc_id);
491 if (IS_ERR(priv->event_thread[i].worker)) {
492 ret = PTR_ERR(priv->event_thread[i].worker);
493 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
494 ret = PTR_ERR(priv->event_thread[i].worker);
495 goto err_msm_uninit;
496 }
497
498 sched_set_fifo(priv->event_thread[i].worker->task);
499 }
500
501 ret = drm_vblank_init(ddev, priv->num_crtcs);
502 if (ret < 0) {
503 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
504 goto err_msm_uninit;
505 }
506
507 if (kms) {
508 pm_runtime_get_sync(dev);
509 ret = msm_irq_install(ddev, kms->irq);
510 pm_runtime_put_sync(dev);
511 if (ret < 0) {
512 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
513 goto err_msm_uninit;
514 }
515 }
516
517 ret = drm_dev_register(ddev, 0);
518 if (ret)
519 goto err_msm_uninit;
520
521 if (kms) {
522 ret = msm_disp_snapshot_init(ddev);
523 if (ret)
524 DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret);
525 }
526 drm_mode_config_reset(ddev);
527
528#ifdef CONFIG_DRM_FBDEV_EMULATION
529 if (kms && fbdev)
530 priv->fbdev = msm_fbdev_init(ddev);
531#endif
532
533 ret = msm_debugfs_late_init(ddev);
534 if (ret)
535 goto err_msm_uninit;
536
537 drm_kms_helper_poll_init(ddev);
538
539 return 0;
540
541err_msm_uninit:
542 msm_drm_uninit(dev);
543 return ret;
544}
545
546/*
547 * DRM operations:
548 */
549
550static void load_gpu(struct drm_device *dev)
551{
552 static DEFINE_MUTEX(init_lock);
553 struct msm_drm_private *priv = dev->dev_private;
554
555 mutex_lock(&init_lock);
556
557 if (!priv->gpu)
558 priv->gpu = adreno_load_gpu(dev);
559
560 mutex_unlock(&init_lock);
561}
562
563static int context_init(struct drm_device *dev, struct drm_file *file)
564{
565 static atomic_t ident = ATOMIC_INIT(0);
566 struct msm_drm_private *priv = dev->dev_private;
567 struct msm_file_private *ctx;
568
569 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
570 if (!ctx)
571 return -ENOMEM;
572
573 INIT_LIST_HEAD(&ctx->submitqueues);
574 rwlock_init(&ctx->queuelock);
575
576 kref_init(&ctx->ref);
577 msm_submitqueue_init(dev, ctx);
578
579 ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current);
580 file->driver_priv = ctx;
581
582 ctx->seqno = atomic_inc_return(&ident);
583
584 return 0;
585}
586
587static int msm_open(struct drm_device *dev, struct drm_file *file)
588{
589 /* For now, load gpu on open.. to avoid the requirement of having
590 * firmware in the initrd.
591 */
592 load_gpu(dev);
593
594 return context_init(dev, file);
595}
596
597static void context_close(struct msm_file_private *ctx)
598{
599 msm_submitqueue_close(ctx);
600 msm_file_private_put(ctx);
601}
602
603static void msm_postclose(struct drm_device *dev, struct drm_file *file)
604{
605 struct msm_drm_private *priv = dev->dev_private;
606 struct msm_file_private *ctx = file->driver_priv;
607
608 /*
609 * It is not possible to set sysprof param to non-zero if gpu
610 * is not initialized:
611 */
612 if (priv->gpu)
613 msm_file_private_set_sysprof(ctx, priv->gpu, 0);
614
615 context_close(ctx);
616}
617
618int msm_crtc_enable_vblank(struct drm_crtc *crtc)
619{
620 struct drm_device *dev = crtc->dev;
621 unsigned int pipe = crtc->index;
622 struct msm_drm_private *priv = dev->dev_private;
623 struct msm_kms *kms = priv->kms;
624 if (!kms)
625 return -ENXIO;
626 drm_dbg_vbl(dev, "crtc=%u", pipe);
627 return vblank_ctrl_queue_work(priv, pipe, true);
628}
629
630void msm_crtc_disable_vblank(struct drm_crtc *crtc)
631{
632 struct drm_device *dev = crtc->dev;
633 unsigned int pipe = crtc->index;
634 struct msm_drm_private *priv = dev->dev_private;
635 struct msm_kms *kms = priv->kms;
636 if (!kms)
637 return;
638 drm_dbg_vbl(dev, "crtc=%u", pipe);
639 vblank_ctrl_queue_work(priv, pipe, false);
640}
641
642/*
643 * DRM ioctls:
644 */
645
646static int msm_ioctl_get_param(struct drm_device *dev, void *data,
647 struct drm_file *file)
648{
649 struct msm_drm_private *priv = dev->dev_private;
650 struct drm_msm_param *args = data;
651 struct msm_gpu *gpu;
652
653 /* for now, we just have 3d pipe.. eventually this would need to
654 * be more clever to dispatch to appropriate gpu module:
655 */
656 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0))
657 return -EINVAL;
658
659 gpu = priv->gpu;
660
661 if (!gpu)
662 return -ENXIO;
663
664 return gpu->funcs->get_param(gpu, file->driver_priv,
665 args->param, &args->value, &args->len);
666}
667
668static int msm_ioctl_set_param(struct drm_device *dev, void *data,
669 struct drm_file *file)
670{
671 struct msm_drm_private *priv = dev->dev_private;
672 struct drm_msm_param *args = data;
673 struct msm_gpu *gpu;
674
675 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0))
676 return -EINVAL;
677
678 gpu = priv->gpu;
679
680 if (!gpu)
681 return -ENXIO;
682
683 return gpu->funcs->set_param(gpu, file->driver_priv,
684 args->param, args->value, args->len);
685}
686
687static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
688 struct drm_file *file)
689{
690 struct drm_msm_gem_new *args = data;
691 uint32_t flags = args->flags;
692
693 if (args->flags & ~MSM_BO_FLAGS) {
694 DRM_ERROR("invalid flags: %08x\n", args->flags);
695 return -EINVAL;
696 }
697
698 /*
699 * Uncached CPU mappings are deprecated, as of:
700 *
701 * 9ef364432db4 ("drm/msm: deprecate MSM_BO_UNCACHED (map as writecombine instead)")
702 *
703 * So promote them to WC.
704 */
705 if (flags & MSM_BO_UNCACHED) {
706 flags &= ~MSM_BO_CACHED;
707 flags |= MSM_BO_WC;
708 }
709
710 if (should_fail(&fail_gem_alloc, args->size))
711 return -ENOMEM;
712
713 return msm_gem_new_handle(dev, file, args->size,
714 args->flags, &args->handle, NULL);
715}
716
717static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
718{
719 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
720}
721
722static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
723 struct drm_file *file)
724{
725 struct drm_msm_gem_cpu_prep *args = data;
726 struct drm_gem_object *obj;
727 ktime_t timeout = to_ktime(args->timeout);
728 int ret;
729
730 if (args->op & ~MSM_PREP_FLAGS) {
731 DRM_ERROR("invalid op: %08x\n", args->op);
732 return -EINVAL;
733 }
734
735 obj = drm_gem_object_lookup(file, args->handle);
736 if (!obj)
737 return -ENOENT;
738
739 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
740
741 drm_gem_object_put(obj);
742
743 return ret;
744}
745
746static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
747 struct drm_file *file)
748{
749 struct drm_msm_gem_cpu_fini *args = data;
750 struct drm_gem_object *obj;
751 int ret;
752
753 obj = drm_gem_object_lookup(file, args->handle);
754 if (!obj)
755 return -ENOENT;
756
757 ret = msm_gem_cpu_fini(obj);
758
759 drm_gem_object_put(obj);
760
761 return ret;
762}
763
764static int msm_ioctl_gem_info_iova(struct drm_device *dev,
765 struct drm_file *file, struct drm_gem_object *obj,
766 uint64_t *iova)
767{
768 struct msm_drm_private *priv = dev->dev_private;
769 struct msm_file_private *ctx = file->driver_priv;
770
771 if (!priv->gpu)
772 return -EINVAL;
773
774 if (should_fail(&fail_gem_iova, obj->size))
775 return -ENOMEM;
776
777 /*
778 * Don't pin the memory here - just get an address so that userspace can
779 * be productive
780 */
781 return msm_gem_get_iova(obj, ctx->aspace, iova);
782}
783
784static int msm_ioctl_gem_info_set_iova(struct drm_device *dev,
785 struct drm_file *file, struct drm_gem_object *obj,
786 uint64_t iova)
787{
788 struct msm_drm_private *priv = dev->dev_private;
789 struct msm_file_private *ctx = file->driver_priv;
790
791 if (!priv->gpu)
792 return -EINVAL;
793
794 /* Only supported if per-process address space is supported: */
795 if (priv->gpu->aspace == ctx->aspace)
796 return -EOPNOTSUPP;
797
798 if (should_fail(&fail_gem_iova, obj->size))
799 return -ENOMEM;
800
801 return msm_gem_set_iova(obj, ctx->aspace, iova);
802}
803
804static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
805 struct drm_file *file)
806{
807 struct drm_msm_gem_info *args = data;
808 struct drm_gem_object *obj;
809 struct msm_gem_object *msm_obj;
810 int i, ret = 0;
811
812 if (args->pad)
813 return -EINVAL;
814
815 switch (args->info) {
816 case MSM_INFO_GET_OFFSET:
817 case MSM_INFO_GET_IOVA:
818 case MSM_INFO_SET_IOVA:
819 case MSM_INFO_GET_FLAGS:
820 /* value returned as immediate, not pointer, so len==0: */
821 if (args->len)
822 return -EINVAL;
823 break;
824 case MSM_INFO_SET_NAME:
825 case MSM_INFO_GET_NAME:
826 break;
827 default:
828 return -EINVAL;
829 }
830
831 obj = drm_gem_object_lookup(file, args->handle);
832 if (!obj)
833 return -ENOENT;
834
835 msm_obj = to_msm_bo(obj);
836
837 switch (args->info) {
838 case MSM_INFO_GET_OFFSET:
839 args->value = msm_gem_mmap_offset(obj);
840 break;
841 case MSM_INFO_GET_IOVA:
842 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value);
843 break;
844 case MSM_INFO_SET_IOVA:
845 ret = msm_ioctl_gem_info_set_iova(dev, file, obj, args->value);
846 break;
847 case MSM_INFO_GET_FLAGS:
848 if (obj->import_attach) {
849 ret = -EINVAL;
850 break;
851 }
852 /* Hide internal kernel-only flags: */
853 args->value = to_msm_bo(obj)->flags & MSM_BO_FLAGS;
854 ret = 0;
855 break;
856 case MSM_INFO_SET_NAME:
857 /* length check should leave room for terminating null: */
858 if (args->len >= sizeof(msm_obj->name)) {
859 ret = -EINVAL;
860 break;
861 }
862 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
863 args->len)) {
864 msm_obj->name[0] = '\0';
865 ret = -EFAULT;
866 break;
867 }
868 msm_obj->name[args->len] = '\0';
869 for (i = 0; i < args->len; i++) {
870 if (!isprint(msm_obj->name[i])) {
871 msm_obj->name[i] = '\0';
872 break;
873 }
874 }
875 break;
876 case MSM_INFO_GET_NAME:
877 if (args->value && (args->len < strlen(msm_obj->name))) {
878 ret = -EINVAL;
879 break;
880 }
881 args->len = strlen(msm_obj->name);
882 if (args->value) {
883 if (copy_to_user(u64_to_user_ptr(args->value),
884 msm_obj->name, args->len))
885 ret = -EFAULT;
886 }
887 break;
888 }
889
890 drm_gem_object_put(obj);
891
892 return ret;
893}
894
895static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id,
896 ktime_t timeout)
897{
898 struct dma_fence *fence;
899 int ret;
900
901 if (fence_after(fence_id, queue->last_fence)) {
902 DRM_ERROR_RATELIMITED("waiting on invalid fence: %u (of %u)\n",
903 fence_id, queue->last_fence);
904 return -EINVAL;
905 }
906
907 /*
908 * Map submitqueue scoped "seqno" (which is actually an idr key)
909 * back to underlying dma-fence
910 *
911 * The fence is removed from the fence_idr when the submit is
912 * retired, so if the fence is not found it means there is nothing
913 * to wait for
914 */
915 ret = mutex_lock_interruptible(&queue->idr_lock);
916 if (ret)
917 return ret;
918 fence = idr_find(&queue->fence_idr, fence_id);
919 if (fence)
920 fence = dma_fence_get_rcu(fence);
921 mutex_unlock(&queue->idr_lock);
922
923 if (!fence)
924 return 0;
925
926 ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout));
927 if (ret == 0) {
928 ret = -ETIMEDOUT;
929 } else if (ret != -ERESTARTSYS) {
930 ret = 0;
931 }
932
933 dma_fence_put(fence);
934
935 return ret;
936}
937
938static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
939 struct drm_file *file)
940{
941 struct msm_drm_private *priv = dev->dev_private;
942 struct drm_msm_wait_fence *args = data;
943 struct msm_gpu_submitqueue *queue;
944 int ret;
945
946 if (args->pad) {
947 DRM_ERROR("invalid pad: %08x\n", args->pad);
948 return -EINVAL;
949 }
950
951 if (!priv->gpu)
952 return 0;
953
954 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
955 if (!queue)
956 return -ENOENT;
957
958 ret = wait_fence(queue, args->fence, to_ktime(args->timeout));
959
960 msm_submitqueue_put(queue);
961
962 return ret;
963}
964
965static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
966 struct drm_file *file)
967{
968 struct drm_msm_gem_madvise *args = data;
969 struct drm_gem_object *obj;
970 int ret;
971
972 switch (args->madv) {
973 case MSM_MADV_DONTNEED:
974 case MSM_MADV_WILLNEED:
975 break;
976 default:
977 return -EINVAL;
978 }
979
980 obj = drm_gem_object_lookup(file, args->handle);
981 if (!obj) {
982 return -ENOENT;
983 }
984
985 ret = msm_gem_madvise(obj, args->madv);
986 if (ret >= 0) {
987 args->retained = ret;
988 ret = 0;
989 }
990
991 drm_gem_object_put(obj);
992
993 return ret;
994}
995
996
997static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
998 struct drm_file *file)
999{
1000 struct drm_msm_submitqueue *args = data;
1001
1002 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
1003 return -EINVAL;
1004
1005 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
1006 args->flags, &args->id);
1007}
1008
1009static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
1010 struct drm_file *file)
1011{
1012 return msm_submitqueue_query(dev, file->driver_priv, data);
1013}
1014
1015static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
1016 struct drm_file *file)
1017{
1018 u32 id = *(u32 *) data;
1019
1020 return msm_submitqueue_remove(file->driver_priv, id);
1021}
1022
1023static const struct drm_ioctl_desc msm_ioctls[] = {
1024 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW),
1025 DRM_IOCTL_DEF_DRV(MSM_SET_PARAM, msm_ioctl_set_param, DRM_RENDER_ALLOW),
1026 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW),
1027 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW),
1028 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
1029 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
1030 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW),
1031 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW),
1032 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW),
1033 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW),
1034 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
1035 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
1036};
1037
1038static void msm_fop_show_fdinfo(struct seq_file *m, struct file *f)
1039{
1040 struct drm_file *file = f->private_data;
1041 struct drm_device *dev = file->minor->dev;
1042 struct msm_drm_private *priv = dev->dev_private;
1043 struct drm_printer p = drm_seq_file_printer(m);
1044
1045 if (!priv->gpu)
1046 return;
1047
1048 msm_gpu_show_fdinfo(priv->gpu, file->driver_priv, &p);
1049}
1050
1051static const struct file_operations fops = {
1052 .owner = THIS_MODULE,
1053 DRM_GEM_FOPS,
1054 .show_fdinfo = msm_fop_show_fdinfo,
1055};
1056
1057static const struct drm_driver msm_driver = {
1058 .driver_features = DRIVER_GEM |
1059 DRIVER_RENDER |
1060 DRIVER_ATOMIC |
1061 DRIVER_MODESET |
1062 DRIVER_SYNCOBJ,
1063 .open = msm_open,
1064 .postclose = msm_postclose,
1065 .lastclose = drm_fb_helper_lastclose,
1066 .dumb_create = msm_gem_dumb_create,
1067 .dumb_map_offset = msm_gem_dumb_map_offset,
1068 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1069 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1070 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1071 .gem_prime_mmap = msm_gem_prime_mmap,
1072#ifdef CONFIG_DEBUG_FS
1073 .debugfs_init = msm_debugfs_init,
1074#endif
1075 .ioctls = msm_ioctls,
1076 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1077 .fops = &fops,
1078 .name = "msm",
1079 .desc = "MSM Snapdragon DRM",
1080 .date = "20130625",
1081 .major = MSM_VERSION_MAJOR,
1082 .minor = MSM_VERSION_MINOR,
1083 .patchlevel = MSM_VERSION_PATCHLEVEL,
1084};
1085
1086int msm_pm_prepare(struct device *dev)
1087{
1088 struct msm_drm_private *priv = dev_get_drvdata(dev);
1089 struct drm_device *ddev = priv ? priv->dev : NULL;
1090
1091 if (!priv || !priv->kms)
1092 return 0;
1093
1094 return drm_mode_config_helper_suspend(ddev);
1095}
1096
1097void msm_pm_complete(struct device *dev)
1098{
1099 struct msm_drm_private *priv = dev_get_drvdata(dev);
1100 struct drm_device *ddev = priv ? priv->dev : NULL;
1101
1102 if (!priv || !priv->kms)
1103 return;
1104
1105 drm_mode_config_helper_resume(ddev);
1106}
1107
1108static const struct dev_pm_ops msm_pm_ops = {
1109 .prepare = msm_pm_prepare,
1110 .complete = msm_pm_complete,
1111};
1112
1113/*
1114 * Componentized driver support:
1115 */
1116
1117/*
1118 * Identify what components need to be added by parsing what remote-endpoints
1119 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1120 * is no external component that we need to add since LVDS is within MDP4
1121 * itself.
1122 */
1123static int add_components_mdp(struct device *master_dev,
1124 struct component_match **matchptr)
1125{
1126 struct device_node *np = master_dev->of_node;
1127 struct device_node *ep_node;
1128
1129 for_each_endpoint_of_node(np, ep_node) {
1130 struct device_node *intf;
1131 struct of_endpoint ep;
1132 int ret;
1133
1134 ret = of_graph_parse_endpoint(ep_node, &ep);
1135 if (ret) {
1136 DRM_DEV_ERROR(master_dev, "unable to parse port endpoint\n");
1137 of_node_put(ep_node);
1138 return ret;
1139 }
1140
1141 /*
1142 * The LCDC/LVDS port on MDP4 is a speacial case where the
1143 * remote-endpoint isn't a component that we need to add
1144 */
1145 if (of_device_is_compatible(np, "qcom,mdp4") &&
1146 ep.port == 0)
1147 continue;
1148
1149 /*
1150 * It's okay if some of the ports don't have a remote endpoint
1151 * specified. It just means that the port isn't connected to
1152 * any external interface.
1153 */
1154 intf = of_graph_get_remote_port_parent(ep_node);
1155 if (!intf)
1156 continue;
1157
1158 if (of_device_is_available(intf))
1159 drm_of_component_match_add(master_dev, matchptr,
1160 component_compare_of, intf);
1161
1162 of_node_put(intf);
1163 }
1164
1165 return 0;
1166}
1167
1168/*
1169 * We don't know what's the best binding to link the gpu with the drm device.
1170 * Fow now, we just hunt for all the possible gpus that we support, and add them
1171 * as components.
1172 */
1173static const struct of_device_id msm_gpu_match[] = {
1174 { .compatible = "qcom,adreno" },
1175 { .compatible = "qcom,adreno-3xx" },
1176 { .compatible = "amd,imageon" },
1177 { .compatible = "qcom,kgsl-3d0" },
1178 { },
1179};
1180
1181static int add_gpu_components(struct device *dev,
1182 struct component_match **matchptr)
1183{
1184 struct device_node *np;
1185
1186 np = of_find_matching_node(NULL, msm_gpu_match);
1187 if (!np)
1188 return 0;
1189
1190 if (of_device_is_available(np))
1191 drm_of_component_match_add(dev, matchptr, component_compare_of, np);
1192
1193 of_node_put(np);
1194
1195 return 0;
1196}
1197
1198static int msm_drm_bind(struct device *dev)
1199{
1200 return msm_drm_init(dev, &msm_driver);
1201}
1202
1203static void msm_drm_unbind(struct device *dev)
1204{
1205 msm_drm_uninit(dev);
1206}
1207
1208const struct component_master_ops msm_drm_ops = {
1209 .bind = msm_drm_bind,
1210 .unbind = msm_drm_unbind,
1211};
1212
1213int msm_drv_probe(struct device *master_dev,
1214 int (*kms_init)(struct drm_device *dev))
1215{
1216 struct msm_drm_private *priv;
1217 struct component_match *match = NULL;
1218 int ret;
1219
1220 priv = devm_kzalloc(master_dev, sizeof(*priv), GFP_KERNEL);
1221 if (!priv)
1222 return -ENOMEM;
1223
1224 priv->kms_init = kms_init;
1225 dev_set_drvdata(master_dev, priv);
1226
1227 /* Add mdp components if we have KMS. */
1228 if (kms_init) {
1229 ret = add_components_mdp(master_dev, &match);
1230 if (ret)
1231 return ret;
1232 }
1233
1234 ret = add_gpu_components(master_dev, &match);
1235 if (ret)
1236 return ret;
1237
1238 /* on all devices that I am aware of, iommu's which can map
1239 * any address the cpu can see are used:
1240 */
1241 ret = dma_set_mask_and_coherent(master_dev, ~0);
1242 if (ret)
1243 return ret;
1244
1245 ret = component_master_add_with_match(master_dev, &msm_drm_ops, match);
1246 if (ret)
1247 return ret;
1248
1249 return 0;
1250}
1251
1252/*
1253 * Platform driver:
1254 * Used only for headlesss GPU instances
1255 */
1256
1257static int msm_pdev_probe(struct platform_device *pdev)
1258{
1259 return msm_drv_probe(&pdev->dev, NULL);
1260}
1261
1262static int msm_pdev_remove(struct platform_device *pdev)
1263{
1264 component_master_del(&pdev->dev, &msm_drm_ops);
1265
1266 return 0;
1267}
1268
1269void msm_drv_shutdown(struct platform_device *pdev)
1270{
1271 struct msm_drm_private *priv = platform_get_drvdata(pdev);
1272 struct drm_device *drm = priv ? priv->dev : NULL;
1273
1274 /*
1275 * Shutdown the hw if we're far enough along where things might be on.
1276 * If we run this too early, we'll end up panicking in any variety of
1277 * places. Since we don't register the drm device until late in
1278 * msm_drm_init, drm_dev->registered is used as an indicator that the
1279 * shutdown will be successful.
1280 */
1281 if (drm && drm->registered && priv->kms)
1282 drm_atomic_helper_shutdown(drm);
1283}
1284
1285static struct platform_driver msm_platform_driver = {
1286 .probe = msm_pdev_probe,
1287 .remove = msm_pdev_remove,
1288 .shutdown = msm_drv_shutdown,
1289 .driver = {
1290 .name = "msm",
1291 .pm = &msm_pm_ops,
1292 },
1293};
1294
1295static int __init msm_drm_register(void)
1296{
1297 if (!modeset)
1298 return -EINVAL;
1299
1300 DBG("init");
1301 msm_mdp_register();
1302 msm_dpu_register();
1303 msm_dsi_register();
1304 msm_hdmi_register();
1305 msm_dp_register();
1306 adreno_register();
1307 msm_mdp4_register();
1308 msm_mdss_register();
1309 return platform_driver_register(&msm_platform_driver);
1310}
1311
1312static void __exit msm_drm_unregister(void)
1313{
1314 DBG("fini");
1315 platform_driver_unregister(&msm_platform_driver);
1316 msm_mdss_unregister();
1317 msm_mdp4_unregister();
1318 msm_dp_unregister();
1319 msm_hdmi_unregister();
1320 adreno_unregister();
1321 msm_dsi_unregister();
1322 msm_mdp_unregister();
1323 msm_dpu_unregister();
1324}
1325
1326module_init(msm_drm_register);
1327module_exit(msm_drm_unregister);
1328
1329MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1330MODULE_DESCRIPTION("MSM DRM Driver");
1331MODULE_LICENSE("GPL");