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1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include "msm_drv.h"
19#include "msm_gpu.h"
20#include "msm_kms.h"
21
22static void msm_fb_output_poll_changed(struct drm_device *dev)
23{
24 struct msm_drm_private *priv = dev->dev_private;
25 if (priv->fbdev)
26 drm_fb_helper_hotplug_event(priv->fbdev);
27}
28
29static const struct drm_mode_config_funcs mode_config_funcs = {
30 .fb_create = msm_framebuffer_create,
31 .output_poll_changed = msm_fb_output_poll_changed,
32 .atomic_check = msm_atomic_check,
33 .atomic_commit = msm_atomic_commit,
34};
35
36int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu)
37{
38 struct msm_drm_private *priv = dev->dev_private;
39 int idx = priv->num_mmus++;
40
41 if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus)))
42 return -EINVAL;
43
44 priv->mmus[idx] = mmu;
45
46 return idx;
47}
48
49#ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
50static bool reglog = false;
51MODULE_PARM_DESC(reglog, "Enable register read/write logging");
52module_param(reglog, bool, 0600);
53#else
54#define reglog 0
55#endif
56
57#ifdef CONFIG_DRM_FBDEV_EMULATION
58static bool fbdev = true;
59MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
60module_param(fbdev, bool, 0600);
61#endif
62
63static char *vram = "16m";
64MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
65module_param(vram, charp, 0);
66
67/*
68 * Util/helpers:
69 */
70
71void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
72 const char *dbgname)
73{
74 struct resource *res;
75 unsigned long size;
76 void __iomem *ptr;
77
78 if (name)
79 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
80 else
81 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
82
83 if (!res) {
84 dev_err(&pdev->dev, "failed to get memory resource: %s\n", name);
85 return ERR_PTR(-EINVAL);
86 }
87
88 size = resource_size(res);
89
90 ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
91 if (!ptr) {
92 dev_err(&pdev->dev, "failed to ioremap: %s\n", name);
93 return ERR_PTR(-ENOMEM);
94 }
95
96 if (reglog)
97 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
98
99 return ptr;
100}
101
102void msm_writel(u32 data, void __iomem *addr)
103{
104 if (reglog)
105 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
106 writel(data, addr);
107}
108
109u32 msm_readl(const void __iomem *addr)
110{
111 u32 val = readl(addr);
112 if (reglog)
113 printk(KERN_ERR "IO:R %p %08x\n", addr, val);
114 return val;
115}
116
117struct vblank_event {
118 struct list_head node;
119 int crtc_id;
120 bool enable;
121};
122
123static void vblank_ctrl_worker(struct work_struct *work)
124{
125 struct msm_vblank_ctrl *vbl_ctrl = container_of(work,
126 struct msm_vblank_ctrl, work);
127 struct msm_drm_private *priv = container_of(vbl_ctrl,
128 struct msm_drm_private, vblank_ctrl);
129 struct msm_kms *kms = priv->kms;
130 struct vblank_event *vbl_ev, *tmp;
131 unsigned long flags;
132
133 spin_lock_irqsave(&vbl_ctrl->lock, flags);
134 list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
135 list_del(&vbl_ev->node);
136 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
137
138 if (vbl_ev->enable)
139 kms->funcs->enable_vblank(kms,
140 priv->crtcs[vbl_ev->crtc_id]);
141 else
142 kms->funcs->disable_vblank(kms,
143 priv->crtcs[vbl_ev->crtc_id]);
144
145 kfree(vbl_ev);
146
147 spin_lock_irqsave(&vbl_ctrl->lock, flags);
148 }
149
150 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
151}
152
153static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
154 int crtc_id, bool enable)
155{
156 struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
157 struct vblank_event *vbl_ev;
158 unsigned long flags;
159
160 vbl_ev = kzalloc(sizeof(*vbl_ev), GFP_ATOMIC);
161 if (!vbl_ev)
162 return -ENOMEM;
163
164 vbl_ev->crtc_id = crtc_id;
165 vbl_ev->enable = enable;
166
167 spin_lock_irqsave(&vbl_ctrl->lock, flags);
168 list_add_tail(&vbl_ev->node, &vbl_ctrl->event_list);
169 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
170
171 queue_work(priv->wq, &vbl_ctrl->work);
172
173 return 0;
174}
175
176/*
177 * DRM operations:
178 */
179
180static int msm_unload(struct drm_device *dev)
181{
182 struct msm_drm_private *priv = dev->dev_private;
183 struct msm_kms *kms = priv->kms;
184 struct msm_gpu *gpu = priv->gpu;
185 struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
186 struct vblank_event *vbl_ev, *tmp;
187
188 /* We must cancel and cleanup any pending vblank enable/disable
189 * work before drm_irq_uninstall() to avoid work re-enabling an
190 * irq after uninstall has disabled it.
191 */
192 cancel_work_sync(&vbl_ctrl->work);
193 list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
194 list_del(&vbl_ev->node);
195 kfree(vbl_ev);
196 }
197
198 drm_kms_helper_poll_fini(dev);
199
200#ifdef CONFIG_DRM_FBDEV_EMULATION
201 if (fbdev && priv->fbdev)
202 msm_fbdev_free(dev);
203#endif
204 drm_mode_config_cleanup(dev);
205 drm_vblank_cleanup(dev);
206
207 pm_runtime_get_sync(dev->dev);
208 drm_irq_uninstall(dev);
209 pm_runtime_put_sync(dev->dev);
210
211 flush_workqueue(priv->wq);
212 destroy_workqueue(priv->wq);
213
214 if (kms) {
215 pm_runtime_disable(dev->dev);
216 kms->funcs->destroy(kms);
217 }
218
219 if (gpu) {
220 mutex_lock(&dev->struct_mutex);
221 gpu->funcs->pm_suspend(gpu);
222 mutex_unlock(&dev->struct_mutex);
223 gpu->funcs->destroy(gpu);
224 }
225
226 if (priv->vram.paddr) {
227 DEFINE_DMA_ATTRS(attrs);
228 dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
229 drm_mm_takedown(&priv->vram.mm);
230 dma_free_attrs(dev->dev, priv->vram.size, NULL,
231 priv->vram.paddr, &attrs);
232 }
233
234 component_unbind_all(dev->dev, dev);
235
236 dev->dev_private = NULL;
237
238 kfree(priv);
239
240 return 0;
241}
242
243static int get_mdp_ver(struct platform_device *pdev)
244{
245 struct device *dev = &pdev->dev;
246
247 return (int) (unsigned long) of_device_get_match_data(dev);
248}
249
250#include <linux/of_address.h>
251
252static int msm_init_vram(struct drm_device *dev)
253{
254 struct msm_drm_private *priv = dev->dev_private;
255 struct device_node *node;
256 unsigned long size = 0;
257 int ret = 0;
258
259 /* In the device-tree world, we could have a 'memory-region'
260 * phandle, which gives us a link to our "vram". Allocating
261 * is all nicely abstracted behind the dma api, but we need
262 * to know the entire size to allocate it all in one go. There
263 * are two cases:
264 * 1) device with no IOMMU, in which case we need exclusive
265 * access to a VRAM carveout big enough for all gpu
266 * buffers
267 * 2) device with IOMMU, but where the bootloader puts up
268 * a splash screen. In this case, the VRAM carveout
269 * need only be large enough for fbdev fb. But we need
270 * exclusive access to the buffer to avoid the kernel
271 * using those pages for other purposes (which appears
272 * as corruption on screen before we have a chance to
273 * load and do initial modeset)
274 */
275
276 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
277 if (node) {
278 struct resource r;
279 ret = of_address_to_resource(node, 0, &r);
280 if (ret)
281 return ret;
282 size = r.end - r.start;
283 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
284
285 /* if we have no IOMMU, then we need to use carveout allocator.
286 * Grab the entire CMA chunk carved out in early startup in
287 * mach-msm:
288 */
289 } else if (!iommu_present(&platform_bus_type)) {
290 DRM_INFO("using %s VRAM carveout\n", vram);
291 size = memparse(vram, NULL);
292 }
293
294 if (size) {
295 DEFINE_DMA_ATTRS(attrs);
296 void *p;
297
298 priv->vram.size = size;
299
300 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
301
302 dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
303 dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
304
305 /* note that for no-kernel-mapping, the vaddr returned
306 * is bogus, but non-null if allocation succeeded:
307 */
308 p = dma_alloc_attrs(dev->dev, size,
309 &priv->vram.paddr, GFP_KERNEL, &attrs);
310 if (!p) {
311 dev_err(dev->dev, "failed to allocate VRAM\n");
312 priv->vram.paddr = 0;
313 return -ENOMEM;
314 }
315
316 dev_info(dev->dev, "VRAM: %08x->%08x\n",
317 (uint32_t)priv->vram.paddr,
318 (uint32_t)(priv->vram.paddr + size));
319 }
320
321 return ret;
322}
323
324static int msm_load(struct drm_device *dev, unsigned long flags)
325{
326 struct platform_device *pdev = dev->platformdev;
327 struct msm_drm_private *priv;
328 struct msm_kms *kms;
329 int ret;
330
331 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
332 if (!priv) {
333 dev_err(dev->dev, "failed to allocate private data\n");
334 return -ENOMEM;
335 }
336
337 dev->dev_private = priv;
338
339 priv->wq = alloc_ordered_workqueue("msm", 0);
340 init_waitqueue_head(&priv->fence_event);
341 init_waitqueue_head(&priv->pending_crtcs_event);
342
343 INIT_LIST_HEAD(&priv->inactive_list);
344 INIT_LIST_HEAD(&priv->fence_cbs);
345 INIT_LIST_HEAD(&priv->vblank_ctrl.event_list);
346 INIT_WORK(&priv->vblank_ctrl.work, vblank_ctrl_worker);
347 spin_lock_init(&priv->vblank_ctrl.lock);
348
349 drm_mode_config_init(dev);
350
351 platform_set_drvdata(pdev, dev);
352
353 /* Bind all our sub-components: */
354 ret = component_bind_all(dev->dev, dev);
355 if (ret)
356 return ret;
357
358 ret = msm_init_vram(dev);
359 if (ret)
360 goto fail;
361
362 switch (get_mdp_ver(pdev)) {
363 case 4:
364 kms = mdp4_kms_init(dev);
365 break;
366 case 5:
367 kms = mdp5_kms_init(dev);
368 break;
369 default:
370 kms = ERR_PTR(-ENODEV);
371 break;
372 }
373
374 if (IS_ERR(kms)) {
375 /*
376 * NOTE: once we have GPU support, having no kms should not
377 * be considered fatal.. ideally we would still support gpu
378 * and (for example) use dmabuf/prime to share buffers with
379 * imx drm driver on iMX5
380 */
381 dev_err(dev->dev, "failed to load kms\n");
382 ret = PTR_ERR(kms);
383 goto fail;
384 }
385
386 priv->kms = kms;
387
388 if (kms) {
389 pm_runtime_enable(dev->dev);
390 ret = kms->funcs->hw_init(kms);
391 if (ret) {
392 dev_err(dev->dev, "kms hw init failed: %d\n", ret);
393 goto fail;
394 }
395 }
396
397 dev->mode_config.funcs = &mode_config_funcs;
398
399 ret = drm_vblank_init(dev, priv->num_crtcs);
400 if (ret < 0) {
401 dev_err(dev->dev, "failed to initialize vblank\n");
402 goto fail;
403 }
404
405 pm_runtime_get_sync(dev->dev);
406 ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0));
407 pm_runtime_put_sync(dev->dev);
408 if (ret < 0) {
409 dev_err(dev->dev, "failed to install IRQ handler\n");
410 goto fail;
411 }
412
413 drm_mode_config_reset(dev);
414
415#ifdef CONFIG_DRM_FBDEV_EMULATION
416 if (fbdev)
417 priv->fbdev = msm_fbdev_init(dev);
418#endif
419
420 ret = msm_debugfs_late_init(dev);
421 if (ret)
422 goto fail;
423
424 drm_kms_helper_poll_init(dev);
425
426 return 0;
427
428fail:
429 msm_unload(dev);
430 return ret;
431}
432
433static void load_gpu(struct drm_device *dev)
434{
435 static DEFINE_MUTEX(init_lock);
436 struct msm_drm_private *priv = dev->dev_private;
437
438 mutex_lock(&init_lock);
439
440 if (!priv->gpu)
441 priv->gpu = adreno_load_gpu(dev);
442
443 mutex_unlock(&init_lock);
444}
445
446static int msm_open(struct drm_device *dev, struct drm_file *file)
447{
448 struct msm_file_private *ctx;
449
450 /* For now, load gpu on open.. to avoid the requirement of having
451 * firmware in the initrd.
452 */
453 load_gpu(dev);
454
455 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
456 if (!ctx)
457 return -ENOMEM;
458
459 file->driver_priv = ctx;
460
461 return 0;
462}
463
464static void msm_preclose(struct drm_device *dev, struct drm_file *file)
465{
466 struct msm_drm_private *priv = dev->dev_private;
467 struct msm_file_private *ctx = file->driver_priv;
468 struct msm_kms *kms = priv->kms;
469
470 mutex_lock(&dev->struct_mutex);
471 if (ctx == priv->lastctx)
472 priv->lastctx = NULL;
473 mutex_unlock(&dev->struct_mutex);
474
475 kfree(ctx);
476}
477
478static void msm_lastclose(struct drm_device *dev)
479{
480 struct msm_drm_private *priv = dev->dev_private;
481 if (priv->fbdev)
482 drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
483}
484
485static irqreturn_t msm_irq(int irq, void *arg)
486{
487 struct drm_device *dev = arg;
488 struct msm_drm_private *priv = dev->dev_private;
489 struct msm_kms *kms = priv->kms;
490 BUG_ON(!kms);
491 return kms->funcs->irq(kms);
492}
493
494static void msm_irq_preinstall(struct drm_device *dev)
495{
496 struct msm_drm_private *priv = dev->dev_private;
497 struct msm_kms *kms = priv->kms;
498 BUG_ON(!kms);
499 kms->funcs->irq_preinstall(kms);
500}
501
502static int msm_irq_postinstall(struct drm_device *dev)
503{
504 struct msm_drm_private *priv = dev->dev_private;
505 struct msm_kms *kms = priv->kms;
506 BUG_ON(!kms);
507 return kms->funcs->irq_postinstall(kms);
508}
509
510static void msm_irq_uninstall(struct drm_device *dev)
511{
512 struct msm_drm_private *priv = dev->dev_private;
513 struct msm_kms *kms = priv->kms;
514 BUG_ON(!kms);
515 kms->funcs->irq_uninstall(kms);
516}
517
518static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe)
519{
520 struct msm_drm_private *priv = dev->dev_private;
521 struct msm_kms *kms = priv->kms;
522 if (!kms)
523 return -ENXIO;
524 DBG("dev=%p, crtc=%u", dev, pipe);
525 return vblank_ctrl_queue_work(priv, pipe, true);
526}
527
528static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe)
529{
530 struct msm_drm_private *priv = dev->dev_private;
531 struct msm_kms *kms = priv->kms;
532 if (!kms)
533 return;
534 DBG("dev=%p, crtc=%u", dev, pipe);
535 vblank_ctrl_queue_work(priv, pipe, false);
536}
537
538/*
539 * DRM debugfs:
540 */
541
542#ifdef CONFIG_DEBUG_FS
543static int msm_gpu_show(struct drm_device *dev, struct seq_file *m)
544{
545 struct msm_drm_private *priv = dev->dev_private;
546 struct msm_gpu *gpu = priv->gpu;
547
548 if (gpu) {
549 seq_printf(m, "%s Status:\n", gpu->name);
550 gpu->funcs->show(gpu, m);
551 }
552
553 return 0;
554}
555
556static int msm_gem_show(struct drm_device *dev, struct seq_file *m)
557{
558 struct msm_drm_private *priv = dev->dev_private;
559 struct msm_gpu *gpu = priv->gpu;
560
561 if (gpu) {
562 seq_printf(m, "Active Objects (%s):\n", gpu->name);
563 msm_gem_describe_objects(&gpu->active_list, m);
564 }
565
566 seq_printf(m, "Inactive Objects:\n");
567 msm_gem_describe_objects(&priv->inactive_list, m);
568
569 return 0;
570}
571
572static int msm_mm_show(struct drm_device *dev, struct seq_file *m)
573{
574 return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm);
575}
576
577static int msm_fb_show(struct drm_device *dev, struct seq_file *m)
578{
579 struct msm_drm_private *priv = dev->dev_private;
580 struct drm_framebuffer *fb, *fbdev_fb = NULL;
581
582 if (priv->fbdev) {
583 seq_printf(m, "fbcon ");
584 fbdev_fb = priv->fbdev->fb;
585 msm_framebuffer_describe(fbdev_fb, m);
586 }
587
588 mutex_lock(&dev->mode_config.fb_lock);
589 list_for_each_entry(fb, &dev->mode_config.fb_list, head) {
590 if (fb == fbdev_fb)
591 continue;
592
593 seq_printf(m, "user ");
594 msm_framebuffer_describe(fb, m);
595 }
596 mutex_unlock(&dev->mode_config.fb_lock);
597
598 return 0;
599}
600
601static int show_locked(struct seq_file *m, void *arg)
602{
603 struct drm_info_node *node = (struct drm_info_node *) m->private;
604 struct drm_device *dev = node->minor->dev;
605 int (*show)(struct drm_device *dev, struct seq_file *m) =
606 node->info_ent->data;
607 int ret;
608
609 ret = mutex_lock_interruptible(&dev->struct_mutex);
610 if (ret)
611 return ret;
612
613 ret = show(dev, m);
614
615 mutex_unlock(&dev->struct_mutex);
616
617 return ret;
618}
619
620static struct drm_info_list msm_debugfs_list[] = {
621 {"gpu", show_locked, 0, msm_gpu_show},
622 {"gem", show_locked, 0, msm_gem_show},
623 { "mm", show_locked, 0, msm_mm_show },
624 { "fb", show_locked, 0, msm_fb_show },
625};
626
627static int late_init_minor(struct drm_minor *minor)
628{
629 int ret;
630
631 if (!minor)
632 return 0;
633
634 ret = msm_rd_debugfs_init(minor);
635 if (ret) {
636 dev_err(minor->dev->dev, "could not install rd debugfs\n");
637 return ret;
638 }
639
640 ret = msm_perf_debugfs_init(minor);
641 if (ret) {
642 dev_err(minor->dev->dev, "could not install perf debugfs\n");
643 return ret;
644 }
645
646 return 0;
647}
648
649int msm_debugfs_late_init(struct drm_device *dev)
650{
651 int ret;
652 ret = late_init_minor(dev->primary);
653 if (ret)
654 return ret;
655 ret = late_init_minor(dev->render);
656 if (ret)
657 return ret;
658 ret = late_init_minor(dev->control);
659 return ret;
660}
661
662static int msm_debugfs_init(struct drm_minor *minor)
663{
664 struct drm_device *dev = minor->dev;
665 int ret;
666
667 ret = drm_debugfs_create_files(msm_debugfs_list,
668 ARRAY_SIZE(msm_debugfs_list),
669 minor->debugfs_root, minor);
670
671 if (ret) {
672 dev_err(dev->dev, "could not install msm_debugfs_list\n");
673 return ret;
674 }
675
676 return 0;
677}
678
679static void msm_debugfs_cleanup(struct drm_minor *minor)
680{
681 drm_debugfs_remove_files(msm_debugfs_list,
682 ARRAY_SIZE(msm_debugfs_list), minor);
683 if (!minor->dev->dev_private)
684 return;
685 msm_rd_debugfs_cleanup(minor);
686 msm_perf_debugfs_cleanup(minor);
687}
688#endif
689
690/*
691 * Fences:
692 */
693
694int msm_wait_fence(struct drm_device *dev, uint32_t fence,
695 ktime_t *timeout , bool interruptible)
696{
697 struct msm_drm_private *priv = dev->dev_private;
698 int ret;
699
700 if (!priv->gpu)
701 return 0;
702
703 if (fence > priv->gpu->submitted_fence) {
704 DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
705 fence, priv->gpu->submitted_fence);
706 return -EINVAL;
707 }
708
709 if (!timeout) {
710 /* no-wait: */
711 ret = fence_completed(dev, fence) ? 0 : -EBUSY;
712 } else {
713 ktime_t now = ktime_get();
714 unsigned long remaining_jiffies;
715
716 if (ktime_compare(*timeout, now) < 0) {
717 remaining_jiffies = 0;
718 } else {
719 ktime_t rem = ktime_sub(*timeout, now);
720 struct timespec ts = ktime_to_timespec(rem);
721 remaining_jiffies = timespec_to_jiffies(&ts);
722 }
723
724 if (interruptible)
725 ret = wait_event_interruptible_timeout(priv->fence_event,
726 fence_completed(dev, fence),
727 remaining_jiffies);
728 else
729 ret = wait_event_timeout(priv->fence_event,
730 fence_completed(dev, fence),
731 remaining_jiffies);
732
733 if (ret == 0) {
734 DBG("timeout waiting for fence: %u (completed: %u)",
735 fence, priv->completed_fence);
736 ret = -ETIMEDOUT;
737 } else if (ret != -ERESTARTSYS) {
738 ret = 0;
739 }
740 }
741
742 return ret;
743}
744
745int msm_queue_fence_cb(struct drm_device *dev,
746 struct msm_fence_cb *cb, uint32_t fence)
747{
748 struct msm_drm_private *priv = dev->dev_private;
749 int ret = 0;
750
751 mutex_lock(&dev->struct_mutex);
752 if (!list_empty(&cb->work.entry)) {
753 ret = -EINVAL;
754 } else if (fence > priv->completed_fence) {
755 cb->fence = fence;
756 list_add_tail(&cb->work.entry, &priv->fence_cbs);
757 } else {
758 queue_work(priv->wq, &cb->work);
759 }
760 mutex_unlock(&dev->struct_mutex);
761
762 return ret;
763}
764
765/* called from workqueue */
766void msm_update_fence(struct drm_device *dev, uint32_t fence)
767{
768 struct msm_drm_private *priv = dev->dev_private;
769
770 mutex_lock(&dev->struct_mutex);
771 priv->completed_fence = max(fence, priv->completed_fence);
772
773 while (!list_empty(&priv->fence_cbs)) {
774 struct msm_fence_cb *cb;
775
776 cb = list_first_entry(&priv->fence_cbs,
777 struct msm_fence_cb, work.entry);
778
779 if (cb->fence > priv->completed_fence)
780 break;
781
782 list_del_init(&cb->work.entry);
783 queue_work(priv->wq, &cb->work);
784 }
785
786 mutex_unlock(&dev->struct_mutex);
787
788 wake_up_all(&priv->fence_event);
789}
790
791void __msm_fence_worker(struct work_struct *work)
792{
793 struct msm_fence_cb *cb = container_of(work, struct msm_fence_cb, work);
794 cb->func(cb);
795}
796
797/*
798 * DRM ioctls:
799 */
800
801static int msm_ioctl_get_param(struct drm_device *dev, void *data,
802 struct drm_file *file)
803{
804 struct msm_drm_private *priv = dev->dev_private;
805 struct drm_msm_param *args = data;
806 struct msm_gpu *gpu;
807
808 /* for now, we just have 3d pipe.. eventually this would need to
809 * be more clever to dispatch to appropriate gpu module:
810 */
811 if (args->pipe != MSM_PIPE_3D0)
812 return -EINVAL;
813
814 gpu = priv->gpu;
815
816 if (!gpu)
817 return -ENXIO;
818
819 return gpu->funcs->get_param(gpu, args->param, &args->value);
820}
821
822static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
823 struct drm_file *file)
824{
825 struct drm_msm_gem_new *args = data;
826
827 if (args->flags & ~MSM_BO_FLAGS) {
828 DRM_ERROR("invalid flags: %08x\n", args->flags);
829 return -EINVAL;
830 }
831
832 return msm_gem_new_handle(dev, file, args->size,
833 args->flags, &args->handle);
834}
835
836static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
837{
838 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
839}
840
841static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
842 struct drm_file *file)
843{
844 struct drm_msm_gem_cpu_prep *args = data;
845 struct drm_gem_object *obj;
846 ktime_t timeout = to_ktime(args->timeout);
847 int ret;
848
849 if (args->op & ~MSM_PREP_FLAGS) {
850 DRM_ERROR("invalid op: %08x\n", args->op);
851 return -EINVAL;
852 }
853
854 obj = drm_gem_object_lookup(dev, file, args->handle);
855 if (!obj)
856 return -ENOENT;
857
858 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
859
860 drm_gem_object_unreference_unlocked(obj);
861
862 return ret;
863}
864
865static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
866 struct drm_file *file)
867{
868 struct drm_msm_gem_cpu_fini *args = data;
869 struct drm_gem_object *obj;
870 int ret;
871
872 obj = drm_gem_object_lookup(dev, file, args->handle);
873 if (!obj)
874 return -ENOENT;
875
876 ret = msm_gem_cpu_fini(obj);
877
878 drm_gem_object_unreference_unlocked(obj);
879
880 return ret;
881}
882
883static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
884 struct drm_file *file)
885{
886 struct drm_msm_gem_info *args = data;
887 struct drm_gem_object *obj;
888 int ret = 0;
889
890 if (args->pad)
891 return -EINVAL;
892
893 obj = drm_gem_object_lookup(dev, file, args->handle);
894 if (!obj)
895 return -ENOENT;
896
897 args->offset = msm_gem_mmap_offset(obj);
898
899 drm_gem_object_unreference_unlocked(obj);
900
901 return ret;
902}
903
904static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
905 struct drm_file *file)
906{
907 struct drm_msm_wait_fence *args = data;
908 ktime_t timeout = to_ktime(args->timeout);
909
910 if (args->pad) {
911 DRM_ERROR("invalid pad: %08x\n", args->pad);
912 return -EINVAL;
913 }
914
915 return msm_wait_fence(dev, args->fence, &timeout, true);
916}
917
918static const struct drm_ioctl_desc msm_ioctls[] = {
919 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW),
920 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW),
921 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW),
922 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
923 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
924 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW),
925 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW),
926};
927
928static const struct vm_operations_struct vm_ops = {
929 .fault = msm_gem_fault,
930 .open = drm_gem_vm_open,
931 .close = drm_gem_vm_close,
932};
933
934static const struct file_operations fops = {
935 .owner = THIS_MODULE,
936 .open = drm_open,
937 .release = drm_release,
938 .unlocked_ioctl = drm_ioctl,
939#ifdef CONFIG_COMPAT
940 .compat_ioctl = drm_compat_ioctl,
941#endif
942 .poll = drm_poll,
943 .read = drm_read,
944 .llseek = no_llseek,
945 .mmap = msm_gem_mmap,
946};
947
948static struct drm_driver msm_driver = {
949 .driver_features = DRIVER_HAVE_IRQ |
950 DRIVER_GEM |
951 DRIVER_PRIME |
952 DRIVER_RENDER |
953 DRIVER_ATOMIC |
954 DRIVER_MODESET,
955 .load = msm_load,
956 .unload = msm_unload,
957 .open = msm_open,
958 .preclose = msm_preclose,
959 .lastclose = msm_lastclose,
960 .set_busid = drm_platform_set_busid,
961 .irq_handler = msm_irq,
962 .irq_preinstall = msm_irq_preinstall,
963 .irq_postinstall = msm_irq_postinstall,
964 .irq_uninstall = msm_irq_uninstall,
965 .get_vblank_counter = drm_vblank_no_hw_counter,
966 .enable_vblank = msm_enable_vblank,
967 .disable_vblank = msm_disable_vblank,
968 .gem_free_object = msm_gem_free_object,
969 .gem_vm_ops = &vm_ops,
970 .dumb_create = msm_gem_dumb_create,
971 .dumb_map_offset = msm_gem_dumb_map_offset,
972 .dumb_destroy = drm_gem_dumb_destroy,
973 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
974 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
975 .gem_prime_export = drm_gem_prime_export,
976 .gem_prime_import = drm_gem_prime_import,
977 .gem_prime_pin = msm_gem_prime_pin,
978 .gem_prime_unpin = msm_gem_prime_unpin,
979 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
980 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
981 .gem_prime_vmap = msm_gem_prime_vmap,
982 .gem_prime_vunmap = msm_gem_prime_vunmap,
983 .gem_prime_mmap = msm_gem_prime_mmap,
984#ifdef CONFIG_DEBUG_FS
985 .debugfs_init = msm_debugfs_init,
986 .debugfs_cleanup = msm_debugfs_cleanup,
987#endif
988 .ioctls = msm_ioctls,
989 .num_ioctls = DRM_MSM_NUM_IOCTLS,
990 .fops = &fops,
991 .name = "msm",
992 .desc = "MSM Snapdragon DRM",
993 .date = "20130625",
994 .major = 1,
995 .minor = 0,
996};
997
998#ifdef CONFIG_PM_SLEEP
999static int msm_pm_suspend(struct device *dev)
1000{
1001 struct drm_device *ddev = dev_get_drvdata(dev);
1002
1003 drm_kms_helper_poll_disable(ddev);
1004
1005 return 0;
1006}
1007
1008static int msm_pm_resume(struct device *dev)
1009{
1010 struct drm_device *ddev = dev_get_drvdata(dev);
1011
1012 drm_kms_helper_poll_enable(ddev);
1013
1014 return 0;
1015}
1016#endif
1017
1018static const struct dev_pm_ops msm_pm_ops = {
1019 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1020};
1021
1022/*
1023 * Componentized driver support:
1024 */
1025
1026/*
1027 * NOTE: duplication of the same code as exynos or imx (or probably any other).
1028 * so probably some room for some helpers
1029 */
1030static int compare_of(struct device *dev, void *data)
1031{
1032 return dev->of_node == data;
1033}
1034
1035static int add_components(struct device *dev, struct component_match **matchptr,
1036 const char *name)
1037{
1038 struct device_node *np = dev->of_node;
1039 unsigned i;
1040
1041 for (i = 0; ; i++) {
1042 struct device_node *node;
1043
1044 node = of_parse_phandle(np, name, i);
1045 if (!node)
1046 break;
1047
1048 component_match_add(dev, matchptr, compare_of, node);
1049 }
1050
1051 return 0;
1052}
1053
1054static int msm_drm_bind(struct device *dev)
1055{
1056 return drm_platform_init(&msm_driver, to_platform_device(dev));
1057}
1058
1059static void msm_drm_unbind(struct device *dev)
1060{
1061 drm_put_dev(platform_get_drvdata(to_platform_device(dev)));
1062}
1063
1064static const struct component_master_ops msm_drm_ops = {
1065 .bind = msm_drm_bind,
1066 .unbind = msm_drm_unbind,
1067};
1068
1069/*
1070 * Platform driver:
1071 */
1072
1073static int msm_pdev_probe(struct platform_device *pdev)
1074{
1075 struct component_match *match = NULL;
1076
1077 add_components(&pdev->dev, &match, "connectors");
1078 add_components(&pdev->dev, &match, "gpus");
1079
1080 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
1081 return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1082}
1083
1084static int msm_pdev_remove(struct platform_device *pdev)
1085{
1086 component_master_del(&pdev->dev, &msm_drm_ops);
1087
1088 return 0;
1089}
1090
1091static const struct platform_device_id msm_id[] = {
1092 { "mdp", 0 },
1093 { }
1094};
1095
1096static const struct of_device_id dt_match[] = {
1097 { .compatible = "qcom,mdp4", .data = (void *) 4 }, /* mdp4 */
1098 { .compatible = "qcom,mdp5", .data = (void *) 5 }, /* mdp5 */
1099 /* to support downstream DT files */
1100 { .compatible = "qcom,mdss_mdp", .data = (void *) 5 }, /* mdp5 */
1101 {}
1102};
1103MODULE_DEVICE_TABLE(of, dt_match);
1104
1105static struct platform_driver msm_platform_driver = {
1106 .probe = msm_pdev_probe,
1107 .remove = msm_pdev_remove,
1108 .driver = {
1109 .name = "msm",
1110 .of_match_table = dt_match,
1111 .pm = &msm_pm_ops,
1112 },
1113 .id_table = msm_id,
1114};
1115
1116static int __init msm_drm_register(void)
1117{
1118 DBG("init");
1119 msm_dsi_register();
1120 msm_edp_register();
1121 msm_hdmi_register();
1122 adreno_register();
1123 return platform_driver_register(&msm_platform_driver);
1124}
1125
1126static void __exit msm_drm_unregister(void)
1127{
1128 DBG("fini");
1129 platform_driver_unregister(&msm_platform_driver);
1130 msm_hdmi_unregister();
1131 adreno_unregister();
1132 msm_edp_unregister();
1133 msm_dsi_unregister();
1134}
1135
1136module_init(msm_drm_register);
1137module_exit(msm_drm_unregister);
1138
1139MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1140MODULE_DESCRIPTION("MSM DRM Driver");
1141MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8#include <linux/dma-mapping.h>
9#include <linux/kthread.h>
10#include <linux/sched/mm.h>
11#include <linux/uaccess.h>
12#include <uapi/linux/sched/types.h>
13
14#include <drm/drm_drv.h>
15#include <drm/drm_file.h>
16#include <drm/drm_ioctl.h>
17#include <drm/drm_irq.h>
18#include <drm/drm_prime.h>
19#include <drm/drm_of.h>
20#include <drm/drm_vblank.h>
21
22#include "disp/msm_disp_snapshot.h"
23#include "msm_drv.h"
24#include "msm_debugfs.h"
25#include "msm_fence.h"
26#include "msm_gem.h"
27#include "msm_gpu.h"
28#include "msm_kms.h"
29#include "adreno/adreno_gpu.h"
30
31/*
32 * MSM driver version:
33 * - 1.0.0 - initial interface
34 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
35 * - 1.2.0 - adds explicit fence support for submit ioctl
36 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
37 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
38 * MSM_GEM_INFO ioctl.
39 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
40 * GEM object's debug name
41 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
42 * - 1.6.0 - Syncobj support
43 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
44 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
45 */
46#define MSM_VERSION_MAJOR 1
47#define MSM_VERSION_MINOR 8
48#define MSM_VERSION_PATCHLEVEL 0
49
50static const struct drm_mode_config_funcs mode_config_funcs = {
51 .fb_create = msm_framebuffer_create,
52 .output_poll_changed = drm_fb_helper_output_poll_changed,
53 .atomic_check = drm_atomic_helper_check,
54 .atomic_commit = drm_atomic_helper_commit,
55};
56
57static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
58 .atomic_commit_tail = msm_atomic_commit_tail,
59};
60
61#ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
62static bool reglog = false;
63MODULE_PARM_DESC(reglog, "Enable register read/write logging");
64module_param(reglog, bool, 0600);
65#else
66#define reglog 0
67#endif
68
69#ifdef CONFIG_DRM_FBDEV_EMULATION
70static bool fbdev = true;
71MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
72module_param(fbdev, bool, 0600);
73#endif
74
75static char *vram = "16m";
76MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
77module_param(vram, charp, 0);
78
79bool dumpstate = false;
80MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
81module_param(dumpstate, bool, 0600);
82
83static bool modeset = true;
84MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
85module_param(modeset, bool, 0600);
86
87/*
88 * Util/helpers:
89 */
90
91struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
92 const char *name)
93{
94 int i;
95 char n[32];
96
97 snprintf(n, sizeof(n), "%s_clk", name);
98
99 for (i = 0; bulk && i < count; i++) {
100 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
101 return bulk[i].clk;
102 }
103
104
105 return NULL;
106}
107
108struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
109{
110 struct clk *clk;
111 char name2[32];
112
113 clk = devm_clk_get(&pdev->dev, name);
114 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
115 return clk;
116
117 snprintf(name2, sizeof(name2), "%s_clk", name);
118
119 clk = devm_clk_get(&pdev->dev, name2);
120 if (!IS_ERR(clk))
121 dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
122 "\"%s\" instead of \"%s\"\n", name, name2);
123
124 return clk;
125}
126
127static void __iomem *_msm_ioremap(struct platform_device *pdev, const char *name,
128 const char *dbgname, bool quiet, phys_addr_t *psize)
129{
130 struct resource *res;
131 unsigned long size;
132 void __iomem *ptr;
133
134 if (name)
135 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
136 else
137 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
138
139 if (!res) {
140 if (!quiet)
141 DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name);
142 return ERR_PTR(-EINVAL);
143 }
144
145 size = resource_size(res);
146
147 ptr = devm_ioremap(&pdev->dev, res->start, size);
148 if (!ptr) {
149 if (!quiet)
150 DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name);
151 return ERR_PTR(-ENOMEM);
152 }
153
154 if (reglog)
155 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
156
157 if (psize)
158 *psize = size;
159
160 return ptr;
161}
162
163void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
164 const char *dbgname)
165{
166 return _msm_ioremap(pdev, name, dbgname, false, NULL);
167}
168
169void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
170 const char *dbgname)
171{
172 return _msm_ioremap(pdev, name, dbgname, true, NULL);
173}
174
175void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
176 const char *dbgname, phys_addr_t *psize)
177{
178 return _msm_ioremap(pdev, name, dbgname, false, psize);
179}
180
181void msm_writel(u32 data, void __iomem *addr)
182{
183 if (reglog)
184 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
185 writel(data, addr);
186}
187
188u32 msm_readl(const void __iomem *addr)
189{
190 u32 val = readl(addr);
191 if (reglog)
192 pr_err("IO:R %p %08x\n", addr, val);
193 return val;
194}
195
196void msm_rmw(void __iomem *addr, u32 mask, u32 or)
197{
198 u32 val = msm_readl(addr);
199
200 val &= ~mask;
201 msm_writel(val | or, addr);
202}
203
204struct msm_vblank_work {
205 struct work_struct work;
206 int crtc_id;
207 bool enable;
208 struct msm_drm_private *priv;
209};
210
211static void vblank_ctrl_worker(struct work_struct *work)
212{
213 struct msm_vblank_work *vbl_work = container_of(work,
214 struct msm_vblank_work, work);
215 struct msm_drm_private *priv = vbl_work->priv;
216 struct msm_kms *kms = priv->kms;
217
218 if (vbl_work->enable)
219 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
220 else
221 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
222
223 kfree(vbl_work);
224}
225
226static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
227 int crtc_id, bool enable)
228{
229 struct msm_vblank_work *vbl_work;
230
231 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
232 if (!vbl_work)
233 return -ENOMEM;
234
235 INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
236
237 vbl_work->crtc_id = crtc_id;
238 vbl_work->enable = enable;
239 vbl_work->priv = priv;
240
241 queue_work(priv->wq, &vbl_work->work);
242
243 return 0;
244}
245
246static int msm_drm_uninit(struct device *dev)
247{
248 struct platform_device *pdev = to_platform_device(dev);
249 struct drm_device *ddev = platform_get_drvdata(pdev);
250 struct msm_drm_private *priv = ddev->dev_private;
251 struct msm_kms *kms = priv->kms;
252 struct msm_mdss *mdss = priv->mdss;
253 int i;
254
255 /*
256 * Shutdown the hw if we're far enough along where things might be on.
257 * If we run this too early, we'll end up panicking in any variety of
258 * places. Since we don't register the drm device until late in
259 * msm_drm_init, drm_dev->registered is used as an indicator that the
260 * shutdown will be successful.
261 */
262 if (ddev->registered) {
263 drm_dev_unregister(ddev);
264 drm_atomic_helper_shutdown(ddev);
265 }
266
267 /* We must cancel and cleanup any pending vblank enable/disable
268 * work before drm_irq_uninstall() to avoid work re-enabling an
269 * irq after uninstall has disabled it.
270 */
271
272 flush_workqueue(priv->wq);
273
274 /* clean up event worker threads */
275 for (i = 0; i < priv->num_crtcs; i++) {
276 if (priv->event_thread[i].worker)
277 kthread_destroy_worker(priv->event_thread[i].worker);
278 }
279
280 msm_gem_shrinker_cleanup(ddev);
281
282 drm_kms_helper_poll_fini(ddev);
283
284 msm_perf_debugfs_cleanup(priv);
285 msm_rd_debugfs_cleanup(priv);
286
287#ifdef CONFIG_DRM_FBDEV_EMULATION
288 if (fbdev && priv->fbdev)
289 msm_fbdev_free(ddev);
290#endif
291
292 msm_disp_snapshot_destroy(ddev);
293
294 drm_mode_config_cleanup(ddev);
295
296 pm_runtime_get_sync(dev);
297 drm_irq_uninstall(ddev);
298 pm_runtime_put_sync(dev);
299
300 if (kms && kms->funcs)
301 kms->funcs->destroy(kms);
302
303 if (priv->vram.paddr) {
304 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
305 drm_mm_takedown(&priv->vram.mm);
306 dma_free_attrs(dev, priv->vram.size, NULL,
307 priv->vram.paddr, attrs);
308 }
309
310 component_unbind_all(dev, ddev);
311
312 if (mdss && mdss->funcs)
313 mdss->funcs->destroy(ddev);
314
315 ddev->dev_private = NULL;
316 drm_dev_put(ddev);
317
318 destroy_workqueue(priv->wq);
319 kfree(priv);
320
321 return 0;
322}
323
324#define KMS_MDP4 4
325#define KMS_MDP5 5
326#define KMS_DPU 3
327
328static int get_mdp_ver(struct platform_device *pdev)
329{
330 struct device *dev = &pdev->dev;
331
332 return (int) (unsigned long) of_device_get_match_data(dev);
333}
334
335#include <linux/of_address.h>
336
337bool msm_use_mmu(struct drm_device *dev)
338{
339 struct msm_drm_private *priv = dev->dev_private;
340
341 /* a2xx comes with its own MMU */
342 return priv->is_a2xx || iommu_present(&platform_bus_type);
343}
344
345static int msm_init_vram(struct drm_device *dev)
346{
347 struct msm_drm_private *priv = dev->dev_private;
348 struct device_node *node;
349 unsigned long size = 0;
350 int ret = 0;
351
352 /* In the device-tree world, we could have a 'memory-region'
353 * phandle, which gives us a link to our "vram". Allocating
354 * is all nicely abstracted behind the dma api, but we need
355 * to know the entire size to allocate it all in one go. There
356 * are two cases:
357 * 1) device with no IOMMU, in which case we need exclusive
358 * access to a VRAM carveout big enough for all gpu
359 * buffers
360 * 2) device with IOMMU, but where the bootloader puts up
361 * a splash screen. In this case, the VRAM carveout
362 * need only be large enough for fbdev fb. But we need
363 * exclusive access to the buffer to avoid the kernel
364 * using those pages for other purposes (which appears
365 * as corruption on screen before we have a chance to
366 * load and do initial modeset)
367 */
368
369 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
370 if (node) {
371 struct resource r;
372 ret = of_address_to_resource(node, 0, &r);
373 of_node_put(node);
374 if (ret)
375 return ret;
376 size = r.end - r.start;
377 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
378
379 /* if we have no IOMMU, then we need to use carveout allocator.
380 * Grab the entire CMA chunk carved out in early startup in
381 * mach-msm:
382 */
383 } else if (!msm_use_mmu(dev)) {
384 DRM_INFO("using %s VRAM carveout\n", vram);
385 size = memparse(vram, NULL);
386 }
387
388 if (size) {
389 unsigned long attrs = 0;
390 void *p;
391
392 priv->vram.size = size;
393
394 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
395 spin_lock_init(&priv->vram.lock);
396
397 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
398 attrs |= DMA_ATTR_WRITE_COMBINE;
399
400 /* note that for no-kernel-mapping, the vaddr returned
401 * is bogus, but non-null if allocation succeeded:
402 */
403 p = dma_alloc_attrs(dev->dev, size,
404 &priv->vram.paddr, GFP_KERNEL, attrs);
405 if (!p) {
406 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
407 priv->vram.paddr = 0;
408 return -ENOMEM;
409 }
410
411 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
412 (uint32_t)priv->vram.paddr,
413 (uint32_t)(priv->vram.paddr + size));
414 }
415
416 return ret;
417}
418
419static int msm_drm_init(struct device *dev, const struct drm_driver *drv)
420{
421 struct platform_device *pdev = to_platform_device(dev);
422 struct drm_device *ddev;
423 struct msm_drm_private *priv;
424 struct msm_kms *kms;
425 struct msm_mdss *mdss;
426 int ret, i;
427
428 ddev = drm_dev_alloc(drv, dev);
429 if (IS_ERR(ddev)) {
430 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
431 return PTR_ERR(ddev);
432 }
433
434 platform_set_drvdata(pdev, ddev);
435
436 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
437 if (!priv) {
438 ret = -ENOMEM;
439 goto err_put_drm_dev;
440 }
441
442 ddev->dev_private = priv;
443 priv->dev = ddev;
444
445 switch (get_mdp_ver(pdev)) {
446 case KMS_MDP5:
447 ret = mdp5_mdss_init(ddev);
448 break;
449 case KMS_DPU:
450 ret = dpu_mdss_init(ddev);
451 break;
452 default:
453 ret = 0;
454 break;
455 }
456 if (ret)
457 goto err_free_priv;
458
459 mdss = priv->mdss;
460
461 priv->wq = alloc_ordered_workqueue("msm", 0);
462 priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD;
463
464 INIT_LIST_HEAD(&priv->objects);
465 mutex_init(&priv->obj_lock);
466
467 INIT_LIST_HEAD(&priv->inactive_willneed);
468 INIT_LIST_HEAD(&priv->inactive_dontneed);
469 INIT_LIST_HEAD(&priv->inactive_unpinned);
470 mutex_init(&priv->mm_lock);
471
472 /* Teach lockdep about lock ordering wrt. shrinker: */
473 fs_reclaim_acquire(GFP_KERNEL);
474 might_lock(&priv->mm_lock);
475 fs_reclaim_release(GFP_KERNEL);
476
477 drm_mode_config_init(ddev);
478
479 ret = msm_init_vram(ddev);
480 if (ret)
481 goto err_destroy_mdss;
482
483 /* Bind all our sub-components: */
484 ret = component_bind_all(dev, ddev);
485 if (ret)
486 goto err_destroy_mdss;
487
488 dma_set_max_seg_size(dev, UINT_MAX);
489
490 msm_gem_shrinker_init(ddev);
491
492 switch (get_mdp_ver(pdev)) {
493 case KMS_MDP4:
494 kms = mdp4_kms_init(ddev);
495 priv->kms = kms;
496 break;
497 case KMS_MDP5:
498 kms = mdp5_kms_init(ddev);
499 break;
500 case KMS_DPU:
501 kms = dpu_kms_init(ddev);
502 priv->kms = kms;
503 break;
504 default:
505 /* valid only for the dummy headless case, where of_node=NULL */
506 WARN_ON(dev->of_node);
507 kms = NULL;
508 break;
509 }
510
511 if (IS_ERR(kms)) {
512 DRM_DEV_ERROR(dev, "failed to load kms\n");
513 ret = PTR_ERR(kms);
514 priv->kms = NULL;
515 goto err_msm_uninit;
516 }
517
518 /* Enable normalization of plane zpos */
519 ddev->mode_config.normalize_zpos = true;
520
521 if (kms) {
522 kms->dev = ddev;
523 ret = kms->funcs->hw_init(kms);
524 if (ret) {
525 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
526 goto err_msm_uninit;
527 }
528 }
529
530 ddev->mode_config.funcs = &mode_config_funcs;
531 ddev->mode_config.helper_private = &mode_config_helper_funcs;
532
533 for (i = 0; i < priv->num_crtcs; i++) {
534 /* initialize event thread */
535 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
536 priv->event_thread[i].dev = ddev;
537 priv->event_thread[i].worker = kthread_create_worker(0,
538 "crtc_event:%d", priv->event_thread[i].crtc_id);
539 if (IS_ERR(priv->event_thread[i].worker)) {
540 ret = PTR_ERR(priv->event_thread[i].worker);
541 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
542 ret = PTR_ERR(priv->event_thread[i].worker);
543 goto err_msm_uninit;
544 }
545
546 sched_set_fifo(priv->event_thread[i].worker->task);
547 }
548
549 ret = drm_vblank_init(ddev, priv->num_crtcs);
550 if (ret < 0) {
551 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
552 goto err_msm_uninit;
553 }
554
555 if (kms) {
556 pm_runtime_get_sync(dev);
557 ret = drm_irq_install(ddev, kms->irq);
558 pm_runtime_put_sync(dev);
559 if (ret < 0) {
560 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
561 goto err_msm_uninit;
562 }
563 }
564
565 ret = drm_dev_register(ddev, 0);
566 if (ret)
567 goto err_msm_uninit;
568
569 if (kms) {
570 ret = msm_disp_snapshot_init(ddev);
571 if (ret)
572 DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret);
573 }
574 drm_mode_config_reset(ddev);
575
576#ifdef CONFIG_DRM_FBDEV_EMULATION
577 if (kms && fbdev)
578 priv->fbdev = msm_fbdev_init(ddev);
579#endif
580
581 ret = msm_debugfs_late_init(ddev);
582 if (ret)
583 goto err_msm_uninit;
584
585 drm_kms_helper_poll_init(ddev);
586
587 return 0;
588
589err_msm_uninit:
590 msm_drm_uninit(dev);
591 return ret;
592err_destroy_mdss:
593 if (mdss && mdss->funcs)
594 mdss->funcs->destroy(ddev);
595err_free_priv:
596 kfree(priv);
597err_put_drm_dev:
598 drm_dev_put(ddev);
599 platform_set_drvdata(pdev, NULL);
600 return ret;
601}
602
603/*
604 * DRM operations:
605 */
606
607static void load_gpu(struct drm_device *dev)
608{
609 static DEFINE_MUTEX(init_lock);
610 struct msm_drm_private *priv = dev->dev_private;
611
612 mutex_lock(&init_lock);
613
614 if (!priv->gpu)
615 priv->gpu = adreno_load_gpu(dev);
616
617 mutex_unlock(&init_lock);
618}
619
620static int context_init(struct drm_device *dev, struct drm_file *file)
621{
622 static atomic_t ident = ATOMIC_INIT(0);
623 struct msm_drm_private *priv = dev->dev_private;
624 struct msm_file_private *ctx;
625
626 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
627 if (!ctx)
628 return -ENOMEM;
629
630 kref_init(&ctx->ref);
631 msm_submitqueue_init(dev, ctx);
632
633 ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current);
634 file->driver_priv = ctx;
635
636 ctx->seqno = atomic_inc_return(&ident);
637
638 return 0;
639}
640
641static int msm_open(struct drm_device *dev, struct drm_file *file)
642{
643 /* For now, load gpu on open.. to avoid the requirement of having
644 * firmware in the initrd.
645 */
646 load_gpu(dev);
647
648 return context_init(dev, file);
649}
650
651static void context_close(struct msm_file_private *ctx)
652{
653 msm_submitqueue_close(ctx);
654 msm_file_private_put(ctx);
655}
656
657static void msm_postclose(struct drm_device *dev, struct drm_file *file)
658{
659 struct msm_drm_private *priv = dev->dev_private;
660 struct msm_file_private *ctx = file->driver_priv;
661
662 mutex_lock(&dev->struct_mutex);
663 if (ctx == priv->lastctx)
664 priv->lastctx = NULL;
665 mutex_unlock(&dev->struct_mutex);
666
667 context_close(ctx);
668}
669
670static irqreturn_t msm_irq(int irq, void *arg)
671{
672 struct drm_device *dev = arg;
673 struct msm_drm_private *priv = dev->dev_private;
674 struct msm_kms *kms = priv->kms;
675 BUG_ON(!kms);
676 return kms->funcs->irq(kms);
677}
678
679static void msm_irq_preinstall(struct drm_device *dev)
680{
681 struct msm_drm_private *priv = dev->dev_private;
682 struct msm_kms *kms = priv->kms;
683 BUG_ON(!kms);
684 kms->funcs->irq_preinstall(kms);
685}
686
687static int msm_irq_postinstall(struct drm_device *dev)
688{
689 struct msm_drm_private *priv = dev->dev_private;
690 struct msm_kms *kms = priv->kms;
691 BUG_ON(!kms);
692
693 if (kms->funcs->irq_postinstall)
694 return kms->funcs->irq_postinstall(kms);
695
696 return 0;
697}
698
699static void msm_irq_uninstall(struct drm_device *dev)
700{
701 struct msm_drm_private *priv = dev->dev_private;
702 struct msm_kms *kms = priv->kms;
703 BUG_ON(!kms);
704 kms->funcs->irq_uninstall(kms);
705}
706
707int msm_crtc_enable_vblank(struct drm_crtc *crtc)
708{
709 struct drm_device *dev = crtc->dev;
710 unsigned int pipe = crtc->index;
711 struct msm_drm_private *priv = dev->dev_private;
712 struct msm_kms *kms = priv->kms;
713 if (!kms)
714 return -ENXIO;
715 drm_dbg_vbl(dev, "crtc=%u", pipe);
716 return vblank_ctrl_queue_work(priv, pipe, true);
717}
718
719void msm_crtc_disable_vblank(struct drm_crtc *crtc)
720{
721 struct drm_device *dev = crtc->dev;
722 unsigned int pipe = crtc->index;
723 struct msm_drm_private *priv = dev->dev_private;
724 struct msm_kms *kms = priv->kms;
725 if (!kms)
726 return;
727 drm_dbg_vbl(dev, "crtc=%u", pipe);
728 vblank_ctrl_queue_work(priv, pipe, false);
729}
730
731/*
732 * DRM ioctls:
733 */
734
735static int msm_ioctl_get_param(struct drm_device *dev, void *data,
736 struct drm_file *file)
737{
738 struct msm_drm_private *priv = dev->dev_private;
739 struct drm_msm_param *args = data;
740 struct msm_gpu *gpu;
741
742 /* for now, we just have 3d pipe.. eventually this would need to
743 * be more clever to dispatch to appropriate gpu module:
744 */
745 if (args->pipe != MSM_PIPE_3D0)
746 return -EINVAL;
747
748 gpu = priv->gpu;
749
750 if (!gpu)
751 return -ENXIO;
752
753 return gpu->funcs->get_param(gpu, args->param, &args->value);
754}
755
756static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
757 struct drm_file *file)
758{
759 struct drm_msm_gem_new *args = data;
760
761 if (args->flags & ~MSM_BO_FLAGS) {
762 DRM_ERROR("invalid flags: %08x\n", args->flags);
763 return -EINVAL;
764 }
765
766 return msm_gem_new_handle(dev, file, args->size,
767 args->flags, &args->handle, NULL);
768}
769
770static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
771{
772 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
773}
774
775static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
776 struct drm_file *file)
777{
778 struct drm_msm_gem_cpu_prep *args = data;
779 struct drm_gem_object *obj;
780 ktime_t timeout = to_ktime(args->timeout);
781 int ret;
782
783 if (args->op & ~MSM_PREP_FLAGS) {
784 DRM_ERROR("invalid op: %08x\n", args->op);
785 return -EINVAL;
786 }
787
788 obj = drm_gem_object_lookup(file, args->handle);
789 if (!obj)
790 return -ENOENT;
791
792 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
793
794 drm_gem_object_put(obj);
795
796 return ret;
797}
798
799static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
800 struct drm_file *file)
801{
802 struct drm_msm_gem_cpu_fini *args = data;
803 struct drm_gem_object *obj;
804 int ret;
805
806 obj = drm_gem_object_lookup(file, args->handle);
807 if (!obj)
808 return -ENOENT;
809
810 ret = msm_gem_cpu_fini(obj);
811
812 drm_gem_object_put(obj);
813
814 return ret;
815}
816
817static int msm_ioctl_gem_info_iova(struct drm_device *dev,
818 struct drm_file *file, struct drm_gem_object *obj,
819 uint64_t *iova)
820{
821 struct msm_drm_private *priv = dev->dev_private;
822 struct msm_file_private *ctx = file->driver_priv;
823
824 if (!priv->gpu)
825 return -EINVAL;
826
827 /*
828 * Don't pin the memory here - just get an address so that userspace can
829 * be productive
830 */
831 return msm_gem_get_iova(obj, ctx->aspace, iova);
832}
833
834static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
835 struct drm_file *file)
836{
837 struct drm_msm_gem_info *args = data;
838 struct drm_gem_object *obj;
839 struct msm_gem_object *msm_obj;
840 int i, ret = 0;
841
842 if (args->pad)
843 return -EINVAL;
844
845 switch (args->info) {
846 case MSM_INFO_GET_OFFSET:
847 case MSM_INFO_GET_IOVA:
848 /* value returned as immediate, not pointer, so len==0: */
849 if (args->len)
850 return -EINVAL;
851 break;
852 case MSM_INFO_SET_NAME:
853 case MSM_INFO_GET_NAME:
854 break;
855 default:
856 return -EINVAL;
857 }
858
859 obj = drm_gem_object_lookup(file, args->handle);
860 if (!obj)
861 return -ENOENT;
862
863 msm_obj = to_msm_bo(obj);
864
865 switch (args->info) {
866 case MSM_INFO_GET_OFFSET:
867 args->value = msm_gem_mmap_offset(obj);
868 break;
869 case MSM_INFO_GET_IOVA:
870 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value);
871 break;
872 case MSM_INFO_SET_NAME:
873 /* length check should leave room for terminating null: */
874 if (args->len >= sizeof(msm_obj->name)) {
875 ret = -EINVAL;
876 break;
877 }
878 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
879 args->len)) {
880 msm_obj->name[0] = '\0';
881 ret = -EFAULT;
882 break;
883 }
884 msm_obj->name[args->len] = '\0';
885 for (i = 0; i < args->len; i++) {
886 if (!isprint(msm_obj->name[i])) {
887 msm_obj->name[i] = '\0';
888 break;
889 }
890 }
891 break;
892 case MSM_INFO_GET_NAME:
893 if (args->value && (args->len < strlen(msm_obj->name))) {
894 ret = -EINVAL;
895 break;
896 }
897 args->len = strlen(msm_obj->name);
898 if (args->value) {
899 if (copy_to_user(u64_to_user_ptr(args->value),
900 msm_obj->name, args->len))
901 ret = -EFAULT;
902 }
903 break;
904 }
905
906 drm_gem_object_put(obj);
907
908 return ret;
909}
910
911static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
912 struct drm_file *file)
913{
914 struct msm_drm_private *priv = dev->dev_private;
915 struct drm_msm_wait_fence *args = data;
916 ktime_t timeout = to_ktime(args->timeout);
917 struct msm_gpu_submitqueue *queue;
918 struct msm_gpu *gpu = priv->gpu;
919 int ret;
920
921 if (args->pad) {
922 DRM_ERROR("invalid pad: %08x\n", args->pad);
923 return -EINVAL;
924 }
925
926 if (!gpu)
927 return 0;
928
929 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
930 if (!queue)
931 return -ENOENT;
932
933 ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout,
934 true);
935
936 msm_submitqueue_put(queue);
937 return ret;
938}
939
940static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
941 struct drm_file *file)
942{
943 struct drm_msm_gem_madvise *args = data;
944 struct drm_gem_object *obj;
945 int ret;
946
947 switch (args->madv) {
948 case MSM_MADV_DONTNEED:
949 case MSM_MADV_WILLNEED:
950 break;
951 default:
952 return -EINVAL;
953 }
954
955 obj = drm_gem_object_lookup(file, args->handle);
956 if (!obj) {
957 return -ENOENT;
958 }
959
960 ret = msm_gem_madvise(obj, args->madv);
961 if (ret >= 0) {
962 args->retained = ret;
963 ret = 0;
964 }
965
966 drm_gem_object_put(obj);
967
968 return ret;
969}
970
971
972static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
973 struct drm_file *file)
974{
975 struct drm_msm_submitqueue *args = data;
976
977 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
978 return -EINVAL;
979
980 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
981 args->flags, &args->id);
982}
983
984static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
985 struct drm_file *file)
986{
987 return msm_submitqueue_query(dev, file->driver_priv, data);
988}
989
990static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
991 struct drm_file *file)
992{
993 u32 id = *(u32 *) data;
994
995 return msm_submitqueue_remove(file->driver_priv, id);
996}
997
998static const struct drm_ioctl_desc msm_ioctls[] = {
999 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW),
1000 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW),
1001 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW),
1002 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
1003 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
1004 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW),
1005 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW),
1006 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW),
1007 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW),
1008 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
1009 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
1010};
1011
1012static const struct file_operations fops = {
1013 .owner = THIS_MODULE,
1014 .open = drm_open,
1015 .release = drm_release,
1016 .unlocked_ioctl = drm_ioctl,
1017 .compat_ioctl = drm_compat_ioctl,
1018 .poll = drm_poll,
1019 .read = drm_read,
1020 .llseek = no_llseek,
1021 .mmap = msm_gem_mmap,
1022};
1023
1024static const struct drm_driver msm_driver = {
1025 .driver_features = DRIVER_GEM |
1026 DRIVER_RENDER |
1027 DRIVER_ATOMIC |
1028 DRIVER_MODESET |
1029 DRIVER_SYNCOBJ,
1030 .open = msm_open,
1031 .postclose = msm_postclose,
1032 .lastclose = drm_fb_helper_lastclose,
1033 .irq_handler = msm_irq,
1034 .irq_preinstall = msm_irq_preinstall,
1035 .irq_postinstall = msm_irq_postinstall,
1036 .irq_uninstall = msm_irq_uninstall,
1037 .dumb_create = msm_gem_dumb_create,
1038 .dumb_map_offset = msm_gem_dumb_map_offset,
1039 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1040 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1041 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1042 .gem_prime_mmap = msm_gem_prime_mmap,
1043#ifdef CONFIG_DEBUG_FS
1044 .debugfs_init = msm_debugfs_init,
1045#endif
1046 .ioctls = msm_ioctls,
1047 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1048 .fops = &fops,
1049 .name = "msm",
1050 .desc = "MSM Snapdragon DRM",
1051 .date = "20130625",
1052 .major = MSM_VERSION_MAJOR,
1053 .minor = MSM_VERSION_MINOR,
1054 .patchlevel = MSM_VERSION_PATCHLEVEL,
1055};
1056
1057static int __maybe_unused msm_runtime_suspend(struct device *dev)
1058{
1059 struct drm_device *ddev = dev_get_drvdata(dev);
1060 struct msm_drm_private *priv = ddev->dev_private;
1061 struct msm_mdss *mdss = priv->mdss;
1062
1063 DBG("");
1064
1065 if (mdss && mdss->funcs)
1066 return mdss->funcs->disable(mdss);
1067
1068 return 0;
1069}
1070
1071static int __maybe_unused msm_runtime_resume(struct device *dev)
1072{
1073 struct drm_device *ddev = dev_get_drvdata(dev);
1074 struct msm_drm_private *priv = ddev->dev_private;
1075 struct msm_mdss *mdss = priv->mdss;
1076
1077 DBG("");
1078
1079 if (mdss && mdss->funcs)
1080 return mdss->funcs->enable(mdss);
1081
1082 return 0;
1083}
1084
1085static int __maybe_unused msm_pm_suspend(struct device *dev)
1086{
1087
1088 if (pm_runtime_suspended(dev))
1089 return 0;
1090
1091 return msm_runtime_suspend(dev);
1092}
1093
1094static int __maybe_unused msm_pm_resume(struct device *dev)
1095{
1096 if (pm_runtime_suspended(dev))
1097 return 0;
1098
1099 return msm_runtime_resume(dev);
1100}
1101
1102static int __maybe_unused msm_pm_prepare(struct device *dev)
1103{
1104 struct drm_device *ddev = dev_get_drvdata(dev);
1105 struct msm_drm_private *priv = ddev ? ddev->dev_private : NULL;
1106
1107 if (!priv || !priv->kms)
1108 return 0;
1109
1110 return drm_mode_config_helper_suspend(ddev);
1111}
1112
1113static void __maybe_unused msm_pm_complete(struct device *dev)
1114{
1115 struct drm_device *ddev = dev_get_drvdata(dev);
1116 struct msm_drm_private *priv = ddev ? ddev->dev_private : NULL;
1117
1118 if (!priv || !priv->kms)
1119 return;
1120
1121 drm_mode_config_helper_resume(ddev);
1122}
1123
1124static const struct dev_pm_ops msm_pm_ops = {
1125 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1126 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
1127 .prepare = msm_pm_prepare,
1128 .complete = msm_pm_complete,
1129};
1130
1131/*
1132 * Componentized driver support:
1133 */
1134
1135/*
1136 * NOTE: duplication of the same code as exynos or imx (or probably any other).
1137 * so probably some room for some helpers
1138 */
1139static int compare_of(struct device *dev, void *data)
1140{
1141 return dev->of_node == data;
1142}
1143
1144/*
1145 * Identify what components need to be added by parsing what remote-endpoints
1146 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1147 * is no external component that we need to add since LVDS is within MDP4
1148 * itself.
1149 */
1150static int add_components_mdp(struct device *mdp_dev,
1151 struct component_match **matchptr)
1152{
1153 struct device_node *np = mdp_dev->of_node;
1154 struct device_node *ep_node;
1155 struct device *master_dev;
1156
1157 /*
1158 * on MDP4 based platforms, the MDP platform device is the component
1159 * master that adds other display interface components to itself.
1160 *
1161 * on MDP5 based platforms, the MDSS platform device is the component
1162 * master that adds MDP5 and other display interface components to
1163 * itself.
1164 */
1165 if (of_device_is_compatible(np, "qcom,mdp4"))
1166 master_dev = mdp_dev;
1167 else
1168 master_dev = mdp_dev->parent;
1169
1170 for_each_endpoint_of_node(np, ep_node) {
1171 struct device_node *intf;
1172 struct of_endpoint ep;
1173 int ret;
1174
1175 ret = of_graph_parse_endpoint(ep_node, &ep);
1176 if (ret) {
1177 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n");
1178 of_node_put(ep_node);
1179 return ret;
1180 }
1181
1182 /*
1183 * The LCDC/LVDS port on MDP4 is a speacial case where the
1184 * remote-endpoint isn't a component that we need to add
1185 */
1186 if (of_device_is_compatible(np, "qcom,mdp4") &&
1187 ep.port == 0)
1188 continue;
1189
1190 /*
1191 * It's okay if some of the ports don't have a remote endpoint
1192 * specified. It just means that the port isn't connected to
1193 * any external interface.
1194 */
1195 intf = of_graph_get_remote_port_parent(ep_node);
1196 if (!intf)
1197 continue;
1198
1199 if (of_device_is_available(intf))
1200 drm_of_component_match_add(master_dev, matchptr,
1201 compare_of, intf);
1202
1203 of_node_put(intf);
1204 }
1205
1206 return 0;
1207}
1208
1209static int compare_name_mdp(struct device *dev, void *data)
1210{
1211 return (strstr(dev_name(dev), "mdp") != NULL);
1212}
1213
1214static int add_display_components(struct platform_device *pdev,
1215 struct component_match **matchptr)
1216{
1217 struct device *mdp_dev;
1218 struct device *dev = &pdev->dev;
1219 int ret;
1220
1221 /*
1222 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
1223 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
1224 * Populate the children devices, find the MDP5/DPU node, and then add
1225 * the interfaces to our components list.
1226 */
1227 switch (get_mdp_ver(pdev)) {
1228 case KMS_MDP5:
1229 case KMS_DPU:
1230 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1231 if (ret) {
1232 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
1233 return ret;
1234 }
1235
1236 mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
1237 if (!mdp_dev) {
1238 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n");
1239 of_platform_depopulate(dev);
1240 return -ENODEV;
1241 }
1242
1243 put_device(mdp_dev);
1244
1245 /* add the MDP component itself */
1246 drm_of_component_match_add(dev, matchptr, compare_of,
1247 mdp_dev->of_node);
1248 break;
1249 case KMS_MDP4:
1250 /* MDP4 */
1251 mdp_dev = dev;
1252 break;
1253 }
1254
1255 ret = add_components_mdp(mdp_dev, matchptr);
1256 if (ret)
1257 of_platform_depopulate(dev);
1258
1259 return ret;
1260}
1261
1262/*
1263 * We don't know what's the best binding to link the gpu with the drm device.
1264 * Fow now, we just hunt for all the possible gpus that we support, and add them
1265 * as components.
1266 */
1267static const struct of_device_id msm_gpu_match[] = {
1268 { .compatible = "qcom,adreno" },
1269 { .compatible = "qcom,adreno-3xx" },
1270 { .compatible = "amd,imageon" },
1271 { .compatible = "qcom,kgsl-3d0" },
1272 { },
1273};
1274
1275static int add_gpu_components(struct device *dev,
1276 struct component_match **matchptr)
1277{
1278 struct device_node *np;
1279
1280 np = of_find_matching_node(NULL, msm_gpu_match);
1281 if (!np)
1282 return 0;
1283
1284 if (of_device_is_available(np))
1285 drm_of_component_match_add(dev, matchptr, compare_of, np);
1286
1287 of_node_put(np);
1288
1289 return 0;
1290}
1291
1292static int msm_drm_bind(struct device *dev)
1293{
1294 return msm_drm_init(dev, &msm_driver);
1295}
1296
1297static void msm_drm_unbind(struct device *dev)
1298{
1299 msm_drm_uninit(dev);
1300}
1301
1302static const struct component_master_ops msm_drm_ops = {
1303 .bind = msm_drm_bind,
1304 .unbind = msm_drm_unbind,
1305};
1306
1307/*
1308 * Platform driver:
1309 */
1310
1311static int msm_pdev_probe(struct platform_device *pdev)
1312{
1313 struct component_match *match = NULL;
1314 int ret;
1315
1316 if (get_mdp_ver(pdev)) {
1317 ret = add_display_components(pdev, &match);
1318 if (ret)
1319 return ret;
1320 }
1321
1322 ret = add_gpu_components(&pdev->dev, &match);
1323 if (ret)
1324 goto fail;
1325
1326 /* on all devices that I am aware of, iommu's which can map
1327 * any address the cpu can see are used:
1328 */
1329 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1330 if (ret)
1331 goto fail;
1332
1333 ret = component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1334 if (ret)
1335 goto fail;
1336
1337 return 0;
1338
1339fail:
1340 of_platform_depopulate(&pdev->dev);
1341 return ret;
1342}
1343
1344static int msm_pdev_remove(struct platform_device *pdev)
1345{
1346 component_master_del(&pdev->dev, &msm_drm_ops);
1347 of_platform_depopulate(&pdev->dev);
1348
1349 return 0;
1350}
1351
1352static void msm_pdev_shutdown(struct platform_device *pdev)
1353{
1354 struct drm_device *drm = platform_get_drvdata(pdev);
1355 struct msm_drm_private *priv = drm ? drm->dev_private : NULL;
1356
1357 if (!priv || !priv->kms)
1358 return;
1359
1360 drm_atomic_helper_shutdown(drm);
1361}
1362
1363static const struct of_device_id dt_match[] = {
1364 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1365 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
1366 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
1367 { .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU },
1368 { .compatible = "qcom,sc7280-mdss", .data = (void *)KMS_DPU },
1369 { .compatible = "qcom,sm8150-mdss", .data = (void *)KMS_DPU },
1370 { .compatible = "qcom,sm8250-mdss", .data = (void *)KMS_DPU },
1371 {}
1372};
1373MODULE_DEVICE_TABLE(of, dt_match);
1374
1375static struct platform_driver msm_platform_driver = {
1376 .probe = msm_pdev_probe,
1377 .remove = msm_pdev_remove,
1378 .shutdown = msm_pdev_shutdown,
1379 .driver = {
1380 .name = "msm",
1381 .of_match_table = dt_match,
1382 .pm = &msm_pm_ops,
1383 },
1384};
1385
1386static int __init msm_drm_register(void)
1387{
1388 if (!modeset)
1389 return -EINVAL;
1390
1391 DBG("init");
1392 msm_mdp_register();
1393 msm_dpu_register();
1394 msm_dsi_register();
1395 msm_edp_register();
1396 msm_hdmi_register();
1397 msm_dp_register();
1398 adreno_register();
1399 return platform_driver_register(&msm_platform_driver);
1400}
1401
1402static void __exit msm_drm_unregister(void)
1403{
1404 DBG("fini");
1405 platform_driver_unregister(&msm_platform_driver);
1406 msm_dp_unregister();
1407 msm_hdmi_unregister();
1408 adreno_unregister();
1409 msm_edp_unregister();
1410 msm_dsi_unregister();
1411 msm_mdp_unregister();
1412 msm_dpu_unregister();
1413}
1414
1415module_init(msm_drm_register);
1416module_exit(msm_drm_unregister);
1417
1418MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1419MODULE_DESCRIPTION("MSM DRM Driver");
1420MODULE_LICENSE("GPL");