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1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 *
27 * Contributors:
28 * Niu Bing <bing.niu@intel.com>
29 * Zhi Wang <zhi.a.wang@intel.com>
30 *
31 */
32
33#ifndef _GVT_H_
34#define _GVT_H_
35
36#include <uapi/linux/pci_regs.h>
37#include <linux/kvm_host.h>
38#include <linux/vfio.h>
39#include <linux/mdev.h>
40
41#include "i915_drv.h"
42#include "intel_gvt.h"
43
44#include "debug.h"
45#include "mmio.h"
46#include "reg.h"
47#include "interrupt.h"
48#include "gtt.h"
49#include "display.h"
50#include "edid.h"
51#include "execlist.h"
52#include "scheduler.h"
53#include "sched_policy.h"
54#include "mmio_context.h"
55#include "cmd_parser.h"
56#include "fb_decoder.h"
57#include "dmabuf.h"
58#include "page_track.h"
59
60#define GVT_MAX_VGPU 8
61
62/* Describe per-platform limitations. */
63struct intel_gvt_device_info {
64 u32 max_support_vgpus;
65 u32 cfg_space_size;
66 u32 mmio_size;
67 u32 mmio_bar;
68 unsigned long msi_cap_offset;
69 u32 gtt_start_offset;
70 u32 gtt_entry_size;
71 u32 gtt_entry_size_shift;
72 int gmadr_bytes_in_cmd;
73 u32 max_surface_size;
74};
75
76/* GM resources owned by a vGPU */
77struct intel_vgpu_gm {
78 u64 aperture_sz;
79 u64 hidden_sz;
80 struct drm_mm_node low_gm_node;
81 struct drm_mm_node high_gm_node;
82};
83
84#define INTEL_GVT_MAX_NUM_FENCES 32
85
86/* Fences owned by a vGPU */
87struct intel_vgpu_fence {
88 struct i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES];
89 u32 base;
90 u32 size;
91};
92
93struct intel_vgpu_mmio {
94 void *vreg;
95};
96
97#define INTEL_GVT_MAX_BAR_NUM 4
98
99struct intel_vgpu_pci_bar {
100 u64 size;
101 bool tracked;
102};
103
104struct intel_vgpu_cfg_space {
105 unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE];
106 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM];
107 u32 pmcsr_off;
108};
109
110#define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)
111
112struct intel_vgpu_irq {
113 bool irq_warn_once[INTEL_GVT_EVENT_MAX];
114 DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES],
115 INTEL_GVT_EVENT_MAX);
116};
117
118struct intel_vgpu_opregion {
119 bool mapped;
120 void *va;
121 u32 gfn[INTEL_GVT_OPREGION_PAGES];
122};
123
124#define vgpu_opregion(vgpu) (&(vgpu->opregion))
125
126struct intel_vgpu_display {
127 struct intel_vgpu_i2c_edid i2c_edid;
128 struct intel_vgpu_port ports[I915_MAX_PORTS];
129 struct intel_vgpu_sbi sbi;
130 enum port port_num;
131};
132
133struct vgpu_sched_ctl {
134 int weight;
135};
136
137enum {
138 INTEL_VGPU_EXECLIST_SUBMISSION = 1,
139 INTEL_VGPU_GUC_SUBMISSION,
140};
141
142struct intel_vgpu_submission_ops {
143 const char *name;
144 int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
145 void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
146 void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
147};
148
149struct intel_vgpu_submission {
150 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
151 struct list_head workload_q_head[I915_NUM_ENGINES];
152 struct intel_context *shadow[I915_NUM_ENGINES];
153 struct kmem_cache *workloads;
154 atomic_t running_workload_num;
155 union {
156 u64 i915_context_pml4;
157 u64 i915_context_pdps[GEN8_3LVL_PDPES];
158 };
159 DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
160 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
161 void *ring_scan_buffer[I915_NUM_ENGINES];
162 int ring_scan_buffer_size[I915_NUM_ENGINES];
163 const struct intel_vgpu_submission_ops *ops;
164 int virtual_submission_interface;
165 bool active;
166 struct {
167 u32 lrca;
168 bool valid;
169 u64 ring_context_gpa;
170 } last_ctx[I915_NUM_ENGINES];
171};
172
173#define KVMGT_DEBUGFS_FILENAME "kvmgt_nr_cache_entries"
174
175enum {
176 INTEL_VGPU_STATUS_ATTACHED = 0,
177 INTEL_VGPU_STATUS_ACTIVE,
178 INTEL_VGPU_STATUS_NR_BITS,
179};
180
181struct intel_vgpu {
182 struct vfio_device vfio_device;
183 struct intel_gvt *gvt;
184 struct mutex vgpu_lock;
185 int id;
186 DECLARE_BITMAP(status, INTEL_VGPU_STATUS_NR_BITS);
187 bool pv_notified;
188 bool failsafe;
189 unsigned int resetting_eng;
190
191 /* Both sched_data and sched_ctl can be seen a part of the global gvt
192 * scheduler structure. So below 2 vgpu data are protected
193 * by sched_lock, not vgpu_lock.
194 */
195 void *sched_data;
196 struct vgpu_sched_ctl sched_ctl;
197
198 struct intel_vgpu_fence fence;
199 struct intel_vgpu_gm gm;
200 struct intel_vgpu_cfg_space cfg_space;
201 struct intel_vgpu_mmio mmio;
202 struct intel_vgpu_irq irq;
203 struct intel_vgpu_gtt gtt;
204 struct intel_vgpu_opregion opregion;
205 struct intel_vgpu_display display;
206 struct intel_vgpu_submission submission;
207 struct radix_tree_root page_track_tree;
208 u32 hws_pga[I915_NUM_ENGINES];
209 /* Set on PCI_D3, reset on DMLR, not reflecting the actual PM state */
210 bool d3_entered;
211
212 struct dentry *debugfs;
213
214 struct list_head dmabuf_obj_list_head;
215 struct mutex dmabuf_lock;
216 struct idr object_idr;
217 struct intel_vgpu_vblank_timer vblank_timer;
218
219 u32 scan_nonprivbb;
220
221 struct vfio_region *region;
222 int num_regions;
223 struct eventfd_ctx *intx_trigger;
224 struct eventfd_ctx *msi_trigger;
225
226 /*
227 * Two caches are used to avoid mapping duplicated pages (eg.
228 * scratch pages). This help to reduce dma setup overhead.
229 */
230 struct rb_root gfn_cache;
231 struct rb_root dma_addr_cache;
232 unsigned long nr_cache_entries;
233 struct mutex cache_lock;
234
235 struct kvm_page_track_notifier_node track_node;
236#define NR_BKT (1 << 18)
237 struct hlist_head ptable[NR_BKT];
238#undef NR_BKT
239};
240
241/* validating GM healthy status*/
242#define vgpu_is_vm_unhealthy(ret_val) \
243 (((ret_val) == -EBADRQC) || ((ret_val) == -EFAULT))
244
245struct intel_gvt_gm {
246 unsigned long vgpu_allocated_low_gm_size;
247 unsigned long vgpu_allocated_high_gm_size;
248};
249
250struct intel_gvt_fence {
251 unsigned long vgpu_allocated_fence_num;
252};
253
254/* Special MMIO blocks. */
255struct gvt_mmio_block {
256 unsigned int device;
257 i915_reg_t offset;
258 unsigned int size;
259 gvt_mmio_func read;
260 gvt_mmio_func write;
261};
262
263#define INTEL_GVT_MMIO_HASH_BITS 11
264
265struct intel_gvt_mmio {
266 u16 *mmio_attribute;
267/* Register contains RO bits */
268#define F_RO (1 << 0)
269/* Register contains graphics address */
270#define F_GMADR (1 << 1)
271/* Mode mask registers with high 16 bits as the mask bits */
272#define F_MODE_MASK (1 << 2)
273/* This reg can be accessed by GPU commands */
274#define F_CMD_ACCESS (1 << 3)
275/* This reg has been accessed by a VM */
276#define F_ACCESSED (1 << 4)
277/* This reg requires save & restore during host PM suspend/resume */
278#define F_PM_SAVE (1 << 5)
279/* This reg could be accessed by unaligned address */
280#define F_UNALIGN (1 << 6)
281/* This reg is in GVT's mmio save-restor list and in hardware
282 * logical context image
283 */
284#define F_SR_IN_CTX (1 << 7)
285/* Value of command write of this reg needs to be patched */
286#define F_CMD_WRITE_PATCH (1 << 8)
287
288 struct gvt_mmio_block *mmio_block;
289 unsigned int num_mmio_block;
290
291 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
292 unsigned long num_tracked_mmio;
293};
294
295struct intel_gvt_firmware {
296 void *cfg_space;
297 void *mmio;
298 bool firmware_loaded;
299};
300
301struct intel_vgpu_config {
302 unsigned int low_mm;
303 unsigned int high_mm;
304 unsigned int fence;
305
306 /*
307 * A vGPU with a weight of 8 will get twice as much GPU as a vGPU with
308 * a weight of 4 on a contended host, different vGPU type has different
309 * weight set. Legal weights range from 1 to 16.
310 */
311 unsigned int weight;
312 enum intel_vgpu_edid edid;
313 const char *name;
314};
315
316struct intel_vgpu_type {
317 struct mdev_type type;
318 char name[16];
319 const struct intel_vgpu_config *conf;
320};
321
322struct intel_gvt {
323 /* GVT scope lock, protect GVT itself, and all resource currently
324 * not yet protected by special locks(vgpu and scheduler lock).
325 */
326 struct mutex lock;
327 /* scheduler scope lock, protect gvt and vgpu schedule related data */
328 struct mutex sched_lock;
329
330 struct intel_gt *gt;
331 struct idr vgpu_idr; /* vGPU IDR pool */
332
333 struct intel_gvt_device_info device_info;
334 struct intel_gvt_gm gm;
335 struct intel_gvt_fence fence;
336 struct intel_gvt_mmio mmio;
337 struct intel_gvt_firmware firmware;
338 struct intel_gvt_irq irq;
339 struct intel_gvt_gtt gtt;
340 struct intel_gvt_workload_scheduler scheduler;
341 struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES];
342 DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS);
343 struct mdev_parent parent;
344 struct mdev_type **mdev_types;
345 struct intel_vgpu_type *types;
346 unsigned int num_types;
347 struct intel_vgpu *idle_vgpu;
348
349 struct task_struct *service_thread;
350 wait_queue_head_t service_thread_wq;
351
352 /* service_request is always used in bit operation, we should always
353 * use it with atomic bit ops so that no need to use gvt big lock.
354 */
355 unsigned long service_request;
356
357 struct {
358 struct engine_mmio *mmio;
359 int ctx_mmio_count[I915_NUM_ENGINES];
360 u32 *tlb_mmio_offset_list;
361 u32 tlb_mmio_offset_list_cnt;
362 u32 *mocs_mmio_offset_list;
363 u32 mocs_mmio_offset_list_cnt;
364 } engine_mmio_list;
365 bool is_reg_whitelist_updated;
366
367 struct dentry *debugfs_root;
368};
369
370static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915)
371{
372 return i915->gvt;
373}
374
375enum {
376 /* Scheduling trigger by timer */
377 INTEL_GVT_REQUEST_SCHED = 0,
378
379 /* Scheduling trigger by event */
380 INTEL_GVT_REQUEST_EVENT_SCHED = 1,
381
382 /* per-vGPU vblank emulation request */
383 INTEL_GVT_REQUEST_EMULATE_VBLANK = 2,
384 INTEL_GVT_REQUEST_EMULATE_VBLANK_MAX = INTEL_GVT_REQUEST_EMULATE_VBLANK
385 + GVT_MAX_VGPU,
386};
387
388static inline void intel_gvt_request_service(struct intel_gvt *gvt,
389 int service)
390{
391 set_bit(service, (void *)&gvt->service_request);
392 wake_up(&gvt->service_thread_wq);
393}
394
395void intel_gvt_free_firmware(struct intel_gvt *gvt);
396int intel_gvt_load_firmware(struct intel_gvt *gvt);
397
398/* Aperture/GM space definitions for GVT device */
399#define MB_TO_BYTES(mb) ((mb) << 20ULL)
400#define BYTES_TO_MB(b) ((b) >> 20ULL)
401
402#define HOST_LOW_GM_SIZE MB_TO_BYTES(128)
403#define HOST_HIGH_GM_SIZE MB_TO_BYTES(384)
404#define HOST_FENCE 4
405
406#define gvt_to_ggtt(gvt) ((gvt)->gt->ggtt)
407
408/* Aperture/GM space definitions for GVT device */
409#define gvt_aperture_sz(gvt) gvt_to_ggtt(gvt)->mappable_end
410#define gvt_aperture_pa_base(gvt) gvt_to_ggtt(gvt)->gmadr.start
411
412#define gvt_ggtt_gm_sz(gvt) gvt_to_ggtt(gvt)->vm.total
413#define gvt_ggtt_sz(gvt) (gvt_to_ggtt(gvt)->vm.total >> PAGE_SHIFT << 3)
414#define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt))
415
416#define gvt_aperture_gmadr_base(gvt) (0)
417#define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \
418 + gvt_aperture_sz(gvt) - 1)
419
420#define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \
421 + gvt_aperture_sz(gvt))
422#define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \
423 + gvt_hidden_sz(gvt) - 1)
424
425#define gvt_fence_sz(gvt) (gvt_to_ggtt(gvt)->num_fences)
426
427/* Aperture/GM space definitions for vGPU */
428#define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start)
429#define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start)
430#define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz)
431#define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz)
432
433#define vgpu_aperture_pa_base(vgpu) \
434 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu))
435
436#define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz)
437
438#define vgpu_aperture_pa_end(vgpu) \
439 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
440
441#define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu))
442#define vgpu_aperture_gmadr_end(vgpu) \
443 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
444
445#define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu))
446#define vgpu_hidden_gmadr_end(vgpu) \
447 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)
448
449#define vgpu_fence_base(vgpu) (vgpu->fence.base)
450#define vgpu_fence_sz(vgpu) (vgpu->fence.size)
451
452/* ring context size i.e. the first 0x50 dwords*/
453#define RING_CTX_SIZE 320
454
455int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
456 const struct intel_vgpu_config *conf);
457void intel_vgpu_reset_resource(struct intel_vgpu *vgpu);
458void intel_vgpu_free_resource(struct intel_vgpu *vgpu);
459void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
460 u32 fence, u64 value);
461
462/* Macros for easily accessing vGPU virtual/shadow register.
463 Explicitly seperate use for typed MMIO reg or real offset.*/
464#define vgpu_vreg_t(vgpu, reg) \
465 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
466#define vgpu_vreg(vgpu, offset) \
467 (*(u32 *)(vgpu->mmio.vreg + (offset)))
468#define vgpu_vreg64_t(vgpu, reg) \
469 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
470#define vgpu_vreg64(vgpu, offset) \
471 (*(u64 *)(vgpu->mmio.vreg + (offset)))
472
473#define for_each_active_vgpu(gvt, vgpu, id) \
474 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \
475 for_each_if(test_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status))
476
477static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu,
478 u32 offset, u32 val, bool low)
479{
480 u32 *pval;
481
482 /* BAR offset should be 32 bits algiend */
483 offset = rounddown(offset, 4);
484 pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);
485
486 if (low) {
487 /*
488 * only update bit 31 - bit 4,
489 * leave the bit 3 - bit 0 unchanged.
490 */
491 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0));
492 } else {
493 *pval = val;
494 }
495}
496
497int intel_gvt_init_vgpu_types(struct intel_gvt *gvt);
498void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt);
499
500struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt);
501void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu);
502int intel_gvt_create_vgpu(struct intel_vgpu *vgpu,
503 const struct intel_vgpu_config *conf);
504void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu);
505void intel_gvt_release_vgpu(struct intel_vgpu *vgpu);
506void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
507 intel_engine_mask_t engine_mask);
508void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu);
509void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu);
510void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu);
511
512int intel_gvt_set_opregion(struct intel_vgpu *vgpu);
513int intel_gvt_set_edid(struct intel_vgpu *vgpu, int port_num);
514
515/* validating GM functions */
516#define vgpu_gmadr_is_aperture(vgpu, gmadr) \
517 ((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \
518 (gmadr <= vgpu_aperture_gmadr_end(vgpu)))
519
520#define vgpu_gmadr_is_hidden(vgpu, gmadr) \
521 ((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \
522 (gmadr <= vgpu_hidden_gmadr_end(vgpu)))
523
524#define vgpu_gmadr_is_valid(vgpu, gmadr) \
525 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \
526 (vgpu_gmadr_is_hidden(vgpu, gmadr))))
527
528#define gvt_gmadr_is_aperture(gvt, gmadr) \
529 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \
530 (gmadr <= gvt_aperture_gmadr_end(gvt)))
531
532#define gvt_gmadr_is_hidden(gvt, gmadr) \
533 ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \
534 (gmadr <= gvt_hidden_gmadr_end(gvt)))
535
536#define gvt_gmadr_is_valid(gvt, gmadr) \
537 (gvt_gmadr_is_aperture(gvt, gmadr) || \
538 gvt_gmadr_is_hidden(gvt, gmadr))
539
540bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size);
541int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr);
542int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr);
543int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
544 unsigned long *h_index);
545int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
546 unsigned long *g_index);
547
548void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
549 bool primary);
550void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu);
551
552int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
553 void *p_data, unsigned int bytes);
554
555int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
556 void *p_data, unsigned int bytes);
557
558void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected);
559
560static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar)
561{
562 /* We are 64bit bar. */
563 return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) &
564 PCI_BASE_ADDRESS_MEM_MASK;
565}
566
567void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu);
568int intel_vgpu_init_opregion(struct intel_vgpu *vgpu);
569int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa);
570
571int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci);
572void populate_pvinfo_page(struct intel_vgpu *vgpu);
573
574int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload);
575void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason);
576void intel_vgpu_detach_regions(struct intel_vgpu *vgpu);
577
578enum {
579 GVT_FAILSAFE_UNSUPPORTED_GUEST,
580 GVT_FAILSAFE_INSUFFICIENT_RESOURCE,
581 GVT_FAILSAFE_GUEST_ERR,
582};
583
584static inline void mmio_hw_access_pre(struct intel_gt *gt)
585{
586 intel_runtime_pm_get(gt->uncore->rpm);
587}
588
589static inline void mmio_hw_access_post(struct intel_gt *gt)
590{
591 intel_runtime_pm_put_unchecked(gt->uncore->rpm);
592}
593
594/**
595 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed
596 * @gvt: a GVT device
597 * @offset: register offset
598 *
599 */
600static inline void intel_gvt_mmio_set_accessed(
601 struct intel_gvt *gvt, unsigned int offset)
602{
603 gvt->mmio.mmio_attribute[offset >> 2] |= F_ACCESSED;
604}
605
606/**
607 * intel_gvt_mmio_is_cmd_accessible - if a MMIO could be accessed by command
608 * @gvt: a GVT device
609 * @offset: register offset
610 *
611 * Returns:
612 * True if an MMIO is able to be accessed by GPU commands
613 */
614static inline bool intel_gvt_mmio_is_cmd_accessible(
615 struct intel_gvt *gvt, unsigned int offset)
616{
617 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS;
618}
619
620/**
621 * intel_gvt_mmio_set_cmd_accessible -
622 * mark a MMIO could be accessible by command
623 * @gvt: a GVT device
624 * @offset: register offset
625 *
626 */
627static inline void intel_gvt_mmio_set_cmd_accessible(
628 struct intel_gvt *gvt, unsigned int offset)
629{
630 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_ACCESS;
631}
632
633/**
634 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned
635 * @gvt: a GVT device
636 * @offset: register offset
637 *
638 */
639static inline bool intel_gvt_mmio_is_unalign(
640 struct intel_gvt *gvt, unsigned int offset)
641{
642 return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN;
643}
644
645/**
646 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask
647 * @gvt: a GVT device
648 * @offset: register offset
649 *
650 * Returns:
651 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't.
652 *
653 */
654static inline bool intel_gvt_mmio_has_mode_mask(
655 struct intel_gvt *gvt, unsigned int offset)
656{
657 return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK;
658}
659
660/**
661 * intel_gvt_mmio_is_sr_in_ctx -
662 * check if an MMIO has F_SR_IN_CTX mask
663 * @gvt: a GVT device
664 * @offset: register offset
665 *
666 * Returns:
667 * True if an MMIO has an F_SR_IN_CTX mask, false if it isn't.
668 *
669 */
670static inline bool intel_gvt_mmio_is_sr_in_ctx(
671 struct intel_gvt *gvt, unsigned int offset)
672{
673 return gvt->mmio.mmio_attribute[offset >> 2] & F_SR_IN_CTX;
674}
675
676/**
677 * intel_gvt_mmio_set_sr_in_ctx -
678 * mask an MMIO in GVT's mmio save-restore list and also
679 * in hardware logical context image
680 * @gvt: a GVT device
681 * @offset: register offset
682 *
683 */
684static inline void intel_gvt_mmio_set_sr_in_ctx(
685 struct intel_gvt *gvt, unsigned int offset)
686{
687 gvt->mmio.mmio_attribute[offset >> 2] |= F_SR_IN_CTX;
688}
689
690void intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu);
691/**
692 * intel_gvt_mmio_set_cmd_write_patch -
693 * mark an MMIO if its cmd write needs to be
694 * patched
695 * @gvt: a GVT device
696 * @offset: register offset
697 *
698 */
699static inline void intel_gvt_mmio_set_cmd_write_patch(
700 struct intel_gvt *gvt, unsigned int offset)
701{
702 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_WRITE_PATCH;
703}
704
705/**
706 * intel_gvt_mmio_is_cmd_write_patch - check if an mmio's cmd access needs to
707 * be patched
708 * @gvt: a GVT device
709 * @offset: register offset
710 *
711 * Returns:
712 * True if GPU commmand write to an MMIO should be patched
713 */
714static inline bool intel_gvt_mmio_is_cmd_write_patch(
715 struct intel_gvt *gvt, unsigned int offset)
716{
717 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_WRITE_PATCH;
718}
719
720/**
721 * intel_gvt_read_gpa - copy data from GPA to host data buffer
722 * @vgpu: a vGPU
723 * @gpa: guest physical address
724 * @buf: host data buffer
725 * @len: data length
726 *
727 * Returns:
728 * Zero on success, negative error code if failed.
729 */
730static inline int intel_gvt_read_gpa(struct intel_vgpu *vgpu, unsigned long gpa,
731 void *buf, unsigned long len)
732{
733 if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))
734 return -ESRCH;
735 return vfio_dma_rw(&vgpu->vfio_device, gpa, buf, len, false);
736}
737
738/**
739 * intel_gvt_write_gpa - copy data from host data buffer to GPA
740 * @vgpu: a vGPU
741 * @gpa: guest physical address
742 * @buf: host data buffer
743 * @len: data length
744 *
745 * Returns:
746 * Zero on success, negative error code if failed.
747 */
748static inline int intel_gvt_write_gpa(struct intel_vgpu *vgpu,
749 unsigned long gpa, void *buf, unsigned long len)
750{
751 if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))
752 return -ESRCH;
753 return vfio_dma_rw(&vgpu->vfio_device, gpa, buf, len, true);
754}
755
756void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu);
757void intel_gvt_debugfs_init(struct intel_gvt *gvt);
758void intel_gvt_debugfs_clean(struct intel_gvt *gvt);
759
760int intel_gvt_page_track_add(struct intel_vgpu *info, u64 gfn);
761int intel_gvt_page_track_remove(struct intel_vgpu *info, u64 gfn);
762int intel_gvt_dma_pin_guest_page(struct intel_vgpu *vgpu, dma_addr_t dma_addr);
763int intel_gvt_dma_map_guest_page(struct intel_vgpu *vgpu, unsigned long gfn,
764 unsigned long size, dma_addr_t *dma_addr);
765void intel_gvt_dma_unmap_guest_page(struct intel_vgpu *vgpu,
766 dma_addr_t dma_addr);
767
768#include "trace.h"
769
770#endif